WO2022203207A1 - Circuit de régulation comprenant une pluralité de régulateurs linéaires et son procédé de fonctionnement - Google Patents

Circuit de régulation comprenant une pluralité de régulateurs linéaires et son procédé de fonctionnement Download PDF

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Publication number
WO2022203207A1
WO2022203207A1 PCT/KR2022/002328 KR2022002328W WO2022203207A1 WO 2022203207 A1 WO2022203207 A1 WO 2022203207A1 KR 2022002328 W KR2022002328 W KR 2022002328W WO 2022203207 A1 WO2022203207 A1 WO 2022203207A1
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Prior art keywords
ldo
ldos
parallel
circuit
control
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PCT/KR2022/002328
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English (en)
Korean (ko)
Inventor
윤철하
윤철은
이민우
최규식
최항석
한윤희
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삼성전자 주식회사
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Publication of WO2022203207A1 publication Critical patent/WO2022203207A1/fr

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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof

Definitions

  • Embodiments of the present disclosure disclose a regulating circuit including a plurality of linear regulators in an electronic device and a method of operating the regulating circuit.
  • PDA personal digital assistant
  • smart phone smart phone
  • tablet PC personal computer
  • AI artificial intelligence speaker
  • wearable device wearable device
  • digital camera digital camera
  • Various types of electronic devices, such as digital cameras), and/or Internet of things (IoT) devices are widely used.
  • IoT Internet of things
  • an electronic device may include a regulator circuit (eg, a power supply integrated circuit (IC)) for providing stable and accurate power to an internal system (eg, a hardware module and/or a device thereof).
  • a regulator circuit eg, a power supply integrated circuit (IC)
  • the regulating circuit may be a circuit that converts power input from the outside into DC power required by the system.
  • a DC/DC converter a device for stabilizing a voltage may be referred to as a power regulator, and the power regulator may be classified into a linear regulator and a switching regulator.
  • An electronic device can design a regulating circuit as a linear regulator (eg, LDO, low drop out) that operates even with a low input/output potential difference for a low power supply.
  • a linear regulator may require a relatively low input voltage to output the same voltage.
  • the electronic device may use an LDO that operates even with a low input/output potential difference.
  • the input voltage may be set low, and by operating at a low potential difference, it may be designed to suppress heat generation due to less energy loss.
  • each system or component
  • the electronic device requires a power supply specification (eg, voltage and/or current) This is getting higher and higher.
  • a power supply specification eg, voltage and/or current
  • the specification of the power supply IC in the electronic device also increases, so that it is not possible to use the existing power IC, and a case in which a new power IC needs to be additionally used may occur frequently. This can cause an increase in power supply IC development costs.
  • a power IC having a reconfigurable structure which is designed to bundle and use adjacent switching mode power supplies (SMPS) even after mass production, but this is a buck converter (buck converter). converter) may be limited in the case of a switching type.
  • SMPS switching mode power supplies
  • buck converter buck converter
  • LDO LDO
  • a problem of current balancing may occur when connected in parallel, and thus, a reconfigurable structure has not been proposed until now.
  • a regulating circuit design including a parallel connection structure of a plurality of linear regulators in an electronic device and a method of operating the regulating circuit are disclosed.
  • a re-configurable regulator in response to an increase in the current specification of a system in an electronic device, can be used to provide stable power supply by utilizing an existing power supply IC without additionally configuring a new power supply IC.
  • a rating circuit design and an operating method thereof are disclosed.
  • a regulation capable of increasing current balancing and current capacity by increasing the size of a pass transistor (pass TR) of each LDO through parallel connection of a plurality of low drop outs (LDOs) Disclosed is a circuit and a method of operating the same.
  • a regulating circuit of an electronic device includes a plurality of parallel-connectable low drop outs (LDOs), and a control circuitry operatively connected to the plurality of LDOs, and the control circuit to form one control loop related to the control of the plurality of parallel-connected LDOs, and to operate at least one of the plurality of parallel-connected LDOs based on the power required by the system, the plurality of It can be set to control the LDO.
  • LDOs parallel-connectable low drop outs
  • a method of operating a regulating circuit of an electronic device includes an operation of detecting activation of at least one low drop out (LDO) in a regulating circuit, and a plurality of parallel-connected LDOs based on the activation of the LDO.
  • LDO low drop out
  • the operation of determining whether the operation is interlocked or the operation alone, when determining the operation of one LDO alone, setting the compensation circuit related to the use of the independently operated LDO and the connection between the pass transistor of the LDO and the error amplifier When determining the operation of controlling the LDO to operate in the first operation mode and the interworking operation of the plurality of parallel-connected LDOs through and controlling the plurality of LDOs to operate in the second operation mode through a connection between a pass transistor of the LDO and an error amplifier of at least one auxiliary LDO connected in parallel to the reference LDO.
  • a computer-readable recording medium recording a program for executing the method in a processor may be included.
  • the electronic device can be reconfigured to provide power according to the required power specification with an existing power IC without developing a new power supply IC corresponding to the required power specification or applying an additional power IC.
  • an electronic device may be able to design a more flexible power source, thereby preventing various losses (eg, increase in development time, development cost, and/or product unit price) due to the development of a new power supply IC. have.
  • an electronic device may connect a plurality of output voltages in parallel to use it as a single power source, and separate power sources with remaining capacity to design a required power rail. Accordingly, support according to a change in system usage may be possible through parallel connection of an existing power supply IC without the need to manufacture and add a new power supply IC according to a change in system specification in the electronic device.
  • FIG. 1 is a block diagram of an electronic device in a network environment according to various embodiments of the present disclosure
  • FIG. 2 is a diagram schematically illustrating an example of a configuration of an electronic device according to various embodiments of the present disclosure
  • 3A is a diagram schematically illustrating a design of an LDO connected in parallel in an electronic device and an operation thereof according to various embodiments of the present disclosure
  • 3B is a diagram schematically illustrating a design of an LDO connected in parallel in an electronic device and an operation thereof according to various embodiments of the present disclosure
  • FIG. 4 is a diagram illustrating an example of a regulating circuit design in an electronic device according to an embodiment.
  • FIG. 5 is a diagram illustrating another example of a regulating circuit design in an electronic device according to an embodiment.
  • FIG. 6 is a diagram illustrating another example of a regulating circuit design in an electronic device according to an exemplary embodiment.
  • FIG. 7 is a flowchart illustrating a method of operating an electronic device according to various embodiments of the present disclosure
  • FIG. 1 is a block diagram of an electronic device 101 in a network environment 100 according to various embodiments of the present disclosure.
  • the electronic device 101 communicates with the electronic device 102 through a first network 198 (eg, a short-range wireless communication network) or a second network 199 . It may communicate with at least one of the electronic device 104 and the server 108 through (eg, a long-distance wireless communication network). According to an embodiment, the electronic device 101 may communicate with the electronic device 104 through the server 108 .
  • the electronic device 101 includes a processor 120 , a memory 130 , an input module 150 , a sound output module 155 , a display module 160 , an audio module 170 , and a sensor module ( 176), interface 177, connection terminal 178, haptic module 179, camera module 180, power management module 188, battery 189, communication module 190, subscriber identification module 196 , or an antenna module 197 .
  • at least one of these components eg, the connection terminal 178
  • some of these components are integrated into one component (eg, display module 160 ). can be
  • the processor 120 for example, executes software (eg, a program 140) to execute at least one other component (eg, a hardware or software component) of the electronic device 101 connected to the processor 120. It can control and perform various data processing or operations. According to one embodiment, as at least part of data processing or operation, the processor 120 converts commands or data received from other components (eg, the sensor module 176 or the communication module 190 ) to the volatile memory 132 . may be stored in , process commands or data stored in the volatile memory 132 , and store the result data in the non-volatile memory 134 .
  • software eg, a program 140
  • the processor 120 converts commands or data received from other components (eg, the sensor module 176 or the communication module 190 ) to the volatile memory 132 .
  • the volatile memory 132 may be stored in , process commands or data stored in the volatile memory 132 , and store the result data in the non-volatile memory 134 .
  • the processor 120 is a main processor 121 (eg, a central processing unit (CPU) or an application processor (AP)) or an auxiliary processor capable of operating independently or together with it ( 123) (eg, graphic processing unit (GPU), neural processing unit (NPU), image signal processor (ISP), sensor hub processor, or communication processor (CP, communication processor)) may be included.
  • main processor 121 eg, a central processing unit (CPU) or an application processor (AP)
  • auxiliary processor capable of operating independently or together with it eg, graphic processing unit (GPU), neural processing unit (NPU), image signal processor (ISP), sensor hub processor, or communication processor (CP, communication processor)
  • the electronic device 101 includes the main processor 121 and the sub-processor 123
  • the sub-processor 123 uses less power than the main processor 121 or is set to be specialized for a specified function.
  • the auxiliary processor 123 may be implemented separately from or as a part of the main processor 121 .
  • the auxiliary processor 123 is, for example, on behalf of the main processor 121 or the main processor 121 while the main processor 121 is in an inactive (eg, sleep) state. At least one of the components of the electronic device 101 (eg, the display module 160 , the sensor module 176 , or At least some of functions or states related to the communication module 190 may be controlled.
  • the coprocessor 123 eg, an image signal processor or a communication processor
  • the auxiliary processor 123 may include a hardware structure specialized for processing an artificial intelligence model. Artificial intelligence models can be created through machine learning.
  • Such learning may be performed, for example, in the electronic device 101 itself on which the artificial intelligence model is performed, or may be performed through a separate server (eg, the server 108).
  • the learning algorithm may include, for example, supervised learning, unsupervised learning, semi-supervised learning, or reinforcement learning, but in the above example not limited
  • the artificial intelligence model may include a plurality of artificial neural network layers.
  • Artificial neural networks include deep neural networks (DNNs), convolutional neural networks (CNNs), recurrent neural networks (RNNs), restricted boltzmann machines (RBMs), deep belief networks (DBNs), bidirectional recurrent deep neural networks (BRDNNs), It may be one of deep Q-networks or a combination of two or more of the above, but is not limited to the above example.
  • the artificial intelligence model may include, in addition to, or alternatively, a software structure in addition to the hardware structure.
  • the memory 130 may store various data used by at least one component (eg, the processor 120 or the sensor module 176 ) of the electronic device 101 .
  • the data may include, for example, input data or output data for software (eg, the program 140 ) and instructions related thereto.
  • the memory 130 may include a volatile memory 132 or a non-volatile memory 134 .
  • the program 140 may be stored as software in the memory 130 , and may include, for example, an operating system (OS) 142 , middleware 144 or an application 146 . have.
  • OS operating system
  • middleware middleware
  • application application
  • the input module 150 may receive a command or data to be used by a component (eg, the processor 120 ) of the electronic device 101 from the outside (eg, a user) of the electronic device 101 .
  • the input module 150 may include, for example, a microphone, a mouse, a keyboard, a key (eg, a button), or a digital pen (eg, a stylus pen).
  • the sound output module 155 may output a sound signal to the outside of the electronic device 101 .
  • the sound output module 155 may include, for example, a speaker or a receiver.
  • the speaker can be used for general purposes such as multimedia playback or recording playback.
  • the receiver can be used to receive incoming calls. According to one embodiment, the receiver may be implemented separately from or as part of the speaker.
  • the display module 160 may visually provide information to the outside (eg, a user) of the electronic device 101 .
  • the display module 160 may include, for example, a control circuit for controlling a display, a hologram device, or a projector and a corresponding device.
  • the display module 160 may include a touch sensor configured to sense a touch or a pressure sensor configured to measure the intensity of a force generated by the touch.
  • the audio module 170 may convert a sound into an electric signal or, conversely, convert an electric signal into a sound. According to an embodiment, the audio module 170 acquires a sound through the input module 150 or an external electronic device (eg, a sound output module 155 ) directly or wirelessly connected to the electronic device 101 .
  • the electronic device 102) eg, a speaker or headphones
  • the sensor module 176 detects an operating state (eg, power or temperature) of the electronic device 101 or an external environmental state (eg, a user state), and generates an electrical signal or data value corresponding to the sensed state. can do.
  • the sensor module 176 may include, for example, a gesture sensor, a gyro sensor, a barometric pressure sensor, a magnetic sensor, an acceleration sensor, a grip sensor, a proximity sensor, a color sensor, an IR (infrared) sensor, a biometric sensor, It may include a temperature sensor, a humidity sensor, or an illuminance sensor.
  • the interface 177 may support one or more specified protocols that may be used by the electronic device 101 to directly or wirelessly connect with an external electronic device (eg, the electronic device 102 ).
  • the interface 177 may include, for example, a high definition multimedia interface (HDMI), a universal serial bus (USB) interface, a secure digital (SD) card interface, or an audio interface.
  • HDMI high definition multimedia interface
  • USB universal serial bus
  • SD secure digital
  • the connection terminal 178 may include a connector through which the electronic device 101 can be physically connected to an external electronic device (eg, the electronic device 102 ).
  • the connection terminal 178 may include, for example, an HDMI connector, a USB connector, an SD card connector, or an audio connector (eg, a headphone connector).
  • the haptic module 179 may convert an electrical signal into a mechanical stimulus (eg, vibration or movement) or an electrical stimulus that the user can perceive through tactile or kinesthetic sense.
  • the haptic module 179 may include, for example, a motor, a piezoelectric element, or an electrical stimulation device.
  • the camera module 180 may capture still images and moving images. According to an embodiment, the camera module 180 may include one or more lenses, image sensors, image signal processors, or flashes.
  • the power management module 188 may manage power supplied to the electronic device 101 .
  • the power management module 188 may be implemented as, for example, at least a part of a power management integrated circuit (PMIC).
  • PMIC power management integrated circuit
  • the battery 189 may supply power to at least one component of the electronic device 101 .
  • battery 189 may include, for example, a non-rechargeable primary cell, a rechargeable secondary cell, or a fuel cell.
  • the communication module 190 is a direct (eg, wired) communication channel or a wireless communication channel between the electronic device 101 and an external electronic device (eg, the electronic device 102, the electronic device 104, or the server 108). It can support establishment and communication performance through the established communication channel.
  • the communication module 190 may include one or more communication processors that operate independently of the processor 120 (eg, an application processor) and support direct (eg, wired) communication or wireless communication.
  • the communication module 190 is a wireless communication module 192 (eg, a cellular communication module, a short-range wireless communication module, or a global navigation satellite system (GNSS) communication module) or a wired communication module 194 (eg, : It may include a local area network (LAN) communication module, or a power line communication module).
  • a wireless communication module 192 eg, a cellular communication module, a short-range wireless communication module, or a global navigation satellite system (GNSS) communication module
  • GNSS global navigation satellite system
  • wired communication module 194 eg, : It may include a local area network (LAN) communication module, or a power line communication module.
  • a corresponding communication module among these communication modules is a first network 198 (eg, a short-range communication network such as Bluetooth, wireless fidelity (WiFi) direct, or infrared data association (IrDA)) or a second network 199 (eg, legacy It may communicate with the external electronic device 104 through a cellular network, a 5G network, a next-generation communication network, the Internet, or a computer network (eg, a telecommunication network such as a LAN or a wide area network (WAN)).
  • a first network 198 eg, a short-range communication network such as Bluetooth, wireless fidelity (WiFi) direct, or infrared data association (IrDA)
  • a second network 199 eg, legacy It may communicate with the external electronic device 104 through a cellular network, a 5G network, a next-generation communication network, the Internet, or a computer network (eg, a telecommunication network such as a LAN or a wide area network (WAN)).
  • the wireless communication module 192 uses subscriber information (eg, International Mobile Subscriber Identifier (IMSI)) stored in the subscriber identification module 196 within a communication network such as the first network 198 or the second network 199 .
  • subscriber information eg, International Mobile Subscriber Identifier (IMSI)
  • IMSI International Mobile Subscriber Identifier
  • the electronic device 101 may be identified or authenticated.
  • the wireless communication module 192 may support a 5G network after a 4G network and a next-generation communication technology, for example, a new radio access technology (NR).
  • NR access technology includes high-speed transmission of high-capacity data (eMBB, enhanced mobile broadband), minimization of terminal power and massive machine type communications (mMTC), or high reliability and low latency (URLLC, ultra-reliable and low-latency). communications) can be supported.
  • the wireless communication module 192 may support a high frequency band (eg, mmWave band) to achieve a high data rate, for example.
  • the wireless communication module 192 uses various techniques for securing performance in a high-frequency band, for example, beamforming, massive multiple-input and multiple-output (MIMO), all-dimensional multiplexing.
  • MIMO massive multiple-input and multiple-output
  • the wireless communication module 192 may support various requirements defined in the electronic device 101 , an external electronic device (eg, the electronic device 104 ), or a network system (eg, the second network 199 ).
  • the wireless communication module 192 may include a peak data rate (eg, 20 Gbps or more) for realizing eMBB, loss coverage (eg, 164 dB or less) for realizing mMTC, or U-plane latency for realizing URLLC ( Example: Downlink (DL) and uplink (UL) each 0.5 ms or less, or round trip 1 ms or less) can be supported.
  • a peak data rate eg, 20 Gbps or more
  • loss coverage eg, 164 dB or less
  • U-plane latency for realizing URLLC
  • the antenna module 197 may transmit or receive a signal or power to the outside (eg, an external electronic device).
  • the antenna module 197 may include an antenna including a conductor formed on a substrate (eg, a PCB) or a radiator formed of a conductive pattern.
  • the antenna module 197 may include a plurality of antennas (eg, an array antenna). In this case, at least one antenna suitable for a communication method used in a communication network such as the first network 198 or the second network 199 is connected from the plurality of antennas by, for example, the communication module 190 . can be selected. A signal or power may be transmitted or received between the communication module 190 and an external electronic device through the selected at least one antenna.
  • other components eg, a radio frequency integrated circuit (RFIC)
  • RFIC radio frequency integrated circuit
  • the antenna module 197 may form a mmWave antenna module.
  • the mmWave antenna module comprises a printed circuit board, an RFIC disposed on or adjacent to a first side (eg, bottom side) of the printed circuit board and capable of supporting a designated high frequency band (eg, mmWave band); and a plurality of antennas (eg, an array antenna) disposed on or adjacent to a second side (eg, top or side) of the printed circuit board and capable of transmitting or receiving signals of the designated high frequency band. can do.
  • peripheral devices eg, a bus, general purpose input and output (GPIO), serial peripheral interface (SPI), or mobile industry processor interface (MIPI)
  • GPIO general purpose input and output
  • SPI serial peripheral interface
  • MIPI mobile industry processor interface
  • the command or data may be transmitted or received between the electronic device 101 and the external electronic device 104 through the server 108 connected to the second network 199 .
  • Each of the external electronic devices 102 or 104 may be the same as or different from the electronic device 101 .
  • all or part of the operations performed by the electronic device 101 may be executed by one or more external electronic devices 102 , 104 , or 108 .
  • the electronic device 101 may perform the function or service itself instead of executing the function or service itself.
  • one or more external electronic devices may be requested to perform at least a part of the function or the service.
  • One or more external electronic devices that have received the request may execute at least a part of the requested function or service, or an additional function or service related to the request, and transmit a result of the execution to the electronic device 101 .
  • the electronic device 101 may process the result as it is or additionally and provide it as at least a part of a response to the request.
  • cloud computing, distributed computing, mobile edge computing (MEC), or client-server computing technology may be used.
  • the electronic device 101 may provide an ultra-low latency service using, for example, distributed computing or mobile edge computing.
  • the external electronic device 104 may include an Internet of things (IoT) device.
  • the server 108 may be an intelligent server using machine learning and/or neural networks.
  • the external electronic device 104 or the server 108 may be included in the second network 199 .
  • the electronic device 101 may be applied to an intelligent service (eg, smart home, smart city, smart car, or health care) based on 5G communication technology and IoT-related technology.
  • the electronic device may have various types of devices.
  • the electronic device may include, for example, a portable communication device (eg, a smart phone), a computer device, a portable multimedia device, a portable medical device, a camera, a wearable device, or a home appliance device.
  • a portable communication device eg, a smart phone
  • a computer device e.g., a smart phone
  • a portable multimedia device e.g., a portable medical device
  • a camera e.g., a portable medical device
  • a camera e.g., a portable medical device
  • a camera e.g., a portable medical device
  • a wearable device e.g., a smart bracelet
  • a home appliance device e.g., a home appliance
  • first”, “second”, or “first” or “second” may simply be used to distinguish the component from other such components, and refer to those components in other aspects (e.g., importance or order) is not limited. It is said that one (eg, first) component is “coupled” or “connected” to another (eg, second) component, with or without the terms “functionally” or “communicatively”. When referenced, it means that one component can be connected to the other component directly (eg by wire), wirelessly, or through a third component.
  • module used in various embodiments of this document may include a unit implemented in hardware, software, or firmware, and is interchangeable with terms such as, for example, logic, logic block, component, or circuit.
  • a module may be an integrally formed part or a minimum unit or a part of the part that performs one or more functions.
  • the module may be implemented in the form of an application-specific integrated circuit (ASIC).
  • ASIC application-specific integrated circuit
  • Various embodiments of the present document include one or more instructions stored in a storage medium (eg, internal memory 136 or external memory 138) readable by a machine (eg, electronic device 101).
  • a storage medium eg, internal memory 136 or external memory 138
  • the processor eg, the processor 120
  • the device eg, the electronic device 101
  • the one or more instructions may include code generated by a compiler or code executable by an interpreter.
  • the device-readable storage medium may be provided in the form of a non-transitory storage medium.
  • 'non-transitory' only means that the storage medium is a tangible device and does not contain a signal (eg, electromagnetic wave), and this term is used in cases where data is semi-permanently stored in the storage medium and It does not distinguish between temporary storage cases.
  • a signal eg, electromagnetic wave
  • the method according to various embodiments disclosed in this document may be provided in a computer program product (computer program product).
  • Computer program products may be traded between sellers and buyers as commodities.
  • the computer program product is distributed in the form of a machine-readable storage medium (eg compact disc read only memory (CD-ROM)), or via an application store (eg Play Store TM ) or on two user devices ( It can be distributed (eg downloaded or uploaded) directly or online between smartphones (eg: smartphones).
  • a portion of the computer program product may be temporarily stored or temporarily generated in a machine-readable storage medium such as a memory of a server of a manufacturer, a server of an application store, or a memory of a relay server.
  • each component eg, a module or a program of the above-described components may include a singular or a plurality of entities, and some of the plurality of entities may be separately disposed in other components. have.
  • one or more components or operations among the above-described corresponding components may be omitted, or one or more other components or operations may be added.
  • a plurality of components eg, a module or a program
  • the integrated component may perform one or more functions of each component of the plurality of components identically or similarly to those performed by the corresponding component among the plurality of components prior to the integration. .
  • operations performed by a module, program, or other component are executed sequentially, in parallel, repetitively, or heuristically, or one or more of the operations are executed in a different order. , may be omitted, or one or more other operations may be added.
  • FIG. 2 is a diagram schematically illustrating an example of a configuration of an electronic device according to various embodiments of the present disclosure
  • the electronic device 101 may include a regulating circuit 200 , a power supply module 300 , and a control circuitry 400 .
  • the regulating circuit 200 and the control circuit 400 are separately illustrated, but the regulating circuit 200 according to an embodiment of the present disclosure includes the control circuit ( 400) can be understood as including.
  • the power supply module 300 may generate a plurality of power voltages based on an external power voltage and provide an input voltage Vin among them to the regulating circuit 200 .
  • the regulating circuit 200 may include a plurality of LDOs (eg, a first LDO 210 and at least one second LDO 220 ). According to an embodiment, the regulating circuit 200 may generate the output voltage Vout by regulating the input voltage Vin received from the power supply module 300 . In an embodiment, the regulating circuit 200 may receive a mode setting signal (eg, a switching control signal for parallel connection between LDOs) from the control circuit 400, and based on the mode setting signal, a plurality of systems ( Alternatively, various voltages may be provided to a component) (eg, a hardware module such as a camera module and/or a device or function block thereof).
  • a mode setting signal eg, a switching control signal for parallel connection between LDOs
  • the control circuit 400 may generate a mode setting signal in response to a supply voltage request signal for at least one of a plurality of systems.
  • the control circuit 400 may receive a supply voltage request signal from at least one of the plurality of systems, and generate a mode setting signal based on a requirement (eg, voltage) included in the received voltage request signal. have.
  • the control circuit 400 may control the at least one LDO by transmitting a mode setting signal to at least one LDO (eg, the first LDO 210 and the at least one second LDO 220 ).
  • the first LDO 210 provides an output voltage Vout having a specific voltage to the system of the electronic device 101 by regulating the step-down voltage received from the power supply module 300 . can do.
  • the second LDO 220 may be connected in parallel with the first LDO 210 through one designated connection line. According to an embodiment, the second LDO 220 is connected in parallel with the first LDO 210 , and operates as one LDO together with the first LDO 210 , or independently of the first LDO 210 . can work
  • the regulating circuit 200 may further include a plurality of other LDOs, and Additional LDOs can be connected in parallel in sequence.
  • the second LDO 220 may represent a plurality of LDOs.
  • a structure of the first LDO 210 and the second LDO 220 and a design for connecting them in parallel according to an embodiment will be described with reference to the drawings to be described later.
  • the electronic device 101 is not limited to the components shown in FIG. 2 , and at least one component may be omitted or added.
  • the electronic device 101 includes various hardware modules such as a camera module (eg, the camera module 180 of FIG. 1 ) and/or a display module (eg, the display module 160 of FIG. 1 ). can do.
  • Various embodiments described in the present disclosure may be implemented in a recording medium readable by a computer or a similar device using software, hardware, or a combination thereof.
  • 3A and 3B are diagrams schematically illustrating a design of an LDO connected in parallel in an electronic device and an operation thereof according to various embodiments of the present disclosure
  • FIG. 3A may show a comparative example in which a general regulating circuit operates in the electronic device 101 .
  • FIG. 3B may show an example in which the regulating circuit according to an embodiment of the present disclosure operates in the electronic device 101 .
  • the power IC 310 may be implemented as, for example, at least a part of the power management module 188 (eg, a PMIC, power management integrated circuit) of FIG. 1 .
  • the system 320 is a hardware module (eg, a camera module) requiring power supply from the electronic device 101 and/or an internal element (or functional block) of the hardware module. can represent
  • the electronic device 101 has a power specification (eg, voltage and/or a function block) required by at least some elements (or functional blocks) of the system 320 .
  • a power specification eg, voltage and/or a function block
  • current may increase.
  • some devices (eg, a New block) of the system 320 may change from a first power specification (eg, a current capacity of about 1.0A) to a second power specification (eg, a current capacity of about 1.5A). .
  • a new LDO 330 (eg, a New LDO block) is added to the outside of the power IC 310 , and a corresponding system 320 through the added new LDO 330 . It is designed to supply power to devices (eg New block) of In this case, not only the cost increases due to the additional design of the new LDO 330 , but also the existing power rails (eg, power rails of LDO1 and LDO2 ) are unused, which may be inefficient in circuit design.
  • the existing power rails eg, power rails of LDO1 and LDO2
  • At least two LDOs may be connected in parallel to provide power corresponding to the increased current capacity of the system 320 .
  • a new LDO eg, the new LDO 330 in FIG. 3A
  • a plurality of existing LDOs eg, LDO1 and LDO2 ) are not added.
  • LDO1 and LDO2 may be connected in parallel 350 to provide power corresponding to the increased current capacity of the system 320 .
  • outputs of a plurality of LDOs connected in parallel may be separated, and through this, a voltage may be operated to provide a voltage with sufficient current capacity for each of the plurality of LDOs. In this way, as the outputs of the plurality of LDOs are separated, the number of power rails 340 may be increased.
  • a plurality of output voltages of a plurality of LDOs may be connected in parallel ( 350 ) to be used as one power source ( 360 ), and a power supply remaining in capacity may be separated to design a required power rail. have. Therefore, according to the embodiment of the present disclosure, there is no need to manufacture a new power supply IC according to the specification change of the system 320 (eg, a camera module), and a structure reconfigurable using the existing power supply IC 310 ( By changing the design to a re-configurable structure, it may be possible to supply stable power to the system 320 having an increased current specification.
  • FIG. 4 may show an example of a regulating circuit design in an electronic device according to an embodiment.
  • the regulating circuit 200 of the electronic device 101 includes a plurality of LDOs (eg, a first LDO 410 and a second LDO 420 ) and a control circuit 400 .
  • LDO input eg, VIN (input)
  • LDO output eg, VO (output)
  • GND eg, ground
  • an input of each of the LDOs 410 and 420 may represent an input voltage
  • an output of each of the LDOs 410 and 420 may represent an output voltage
  • the inputs of the plurality of LDOs 410 and 420 may use one input in common
  • the outputs of the plurality of LDOs 410 and 420 are independent for each of the plurality of LDOs 410 and 420 . It can be configured to use one output in common when separated into two or combined in parallel (eg, electrically connected).
  • the control circuit 400 forms an independent control loop for each of the plurality of LDOs 410 and 420 connected in parallel.
  • a plurality of LDOs 410 and 420 may be controlled.
  • the control circuit 400 may control the plurality of LDOs 410 and 420 to form one control loop by grouping the plurality of LDOs 410 and 420 connected in parallel.
  • the control circuit 400 operates the plurality of LDOs 410 to operate at least one LDO among the plurality of LDOs 410 and 420 connected in parallel based on the power required by the system (eg, a device of hardware). , 420) can be controlled.
  • the control circuit 400 is a first operation mode signal or each of the plurality of LDOs 410 and 420 for a first operation mode for allowing each LDO of the plurality of LDOs 410 and 420 to operate independently.
  • a second operation mode signal for a second operation mode for causing the LDOs to operate simultaneously may be provided.
  • the first operation mode signal and the second operation mode signal may be provided to the plurality of LDOs 410 and 420 as a mode setting signal (or control signal) from the control circuit 400 .
  • the first operation mode signal and the second operation mode signal are switched from the control circuit 400 through one control line 430 to the switch circuits 413, respectively, corresponding to the plurality of LDOs 410 and 420, respectively. 423) can be provided.
  • the first LDO 410 may drive a corresponding system with the first output voltage.
  • the second LDO 420 may drive a corresponding system with the second output voltage.
  • the first LDO 410 and the second LDO 420 may be connected to each other in parallel.
  • the second LDO 420 may be coupled (or electrically connected) to the first LDO 410 in parallel.
  • the third LDO 410 and the second LDO 420 increase in current capacity according to the coupling. With the output voltage, it is possible to drive the corresponding system.
  • the first LDO 410 may represent a reference LDO for parallel connection between the plurality of LDOs 410 and 420 in the regulating circuit 200 of the present disclosure.
  • the first LDO 410 includes a pass transistor 411 (or an output transistor), an error amp (EA1) 412 , a switch circuit 413 , and a compensation circuit. (ZF1) 414 .
  • the switch circuit 413 may include a switch SW.
  • the switch SW includes the pass transistor 411 (eg, a gate driver of the pass transistor 411 ) and the error amplifier EA1 based on the first operation mode signal of the control circuit 400 . ) (412) can be switched to connect.
  • the switch circuit 413 may switch the first LDO 410 to operate independently based on the first operation mode signal.
  • the switch SW may be switched to be connected to the compensation circuit ZF1 for compensating a circuit related to a single operation of the first LDO 410 .
  • the switch SW connects the connection line 440 between the pass transistor 411 and the switch circuit 423 of the second LDO 420 based on the second operation mode signal of the control circuit 400 . It is possible to switch between the pass transistor 411 and the error amplifier (EA2) 422 of the second LDO 420 through the connection. For example, in the switch circuit 413 , based on the second operation mode signal, the first LDO 410 is interlocked with (or connected to) the second LDO 420 to form the first LDO 410 and the second LDO ( 420) can be switched to operate as one LDO.
  • EA2 error amplifier
  • the compensation circuit (ZF1) 414 may be a circuit that compensates for the frequency characteristic or stability inside the first LDO 410 .
  • the pass transistor 411 in the first LDO 410 , may be connected to the compensation circuits ZF1 and 414 in the first operation mode, and stability is guaranteed based on the compensation circuits ZF1 and 414 .
  • the pass transistor 411 in the first LDO 410 , may be connected to the second compensation circuit ZF21 of the compensation circuit 424 of the second LDO 420 in the second operation mode, and the second Stability may be guaranteed based on the second compensation circuit ZF21 of the LDO 420 .
  • the first operation mode signal or the second operation mode signal may be received as a mode setting signal (or control signal) from the control circuit 400 through the control line 430 .
  • the pass transistor 411 is a transistor operating in a linear region, may have a linear resistance controlled by a gate voltage, and may operate as an on/off switch.
  • the pass transistor 411 may pass or turn off the input voltage VIN.
  • the pass transistor 411 may be disposed between the input voltage VIN and the output voltage VO in the first LDO 410 , and an input/output required for the pass transistor 411 to stably operate.
  • An output voltage can be generated based on the lowest potential difference (or drop out voltage).
  • the minimum input voltage value required for operation of the first LDO 410 is set, and in this case (VO + drop out voltage) may be the minimum operating voltage value of the first LDO 410 .
  • the error amplifier (EA1) 412 may represent an amplifier that compares the reference voltage Vref and the voltage returned by feedback from the output and amplifies the error by the error.
  • the voltage at the non-inverting terminal may be the same as the reference voltage Vref
  • the output voltage Vo is determined by the resistance ratio of the two resistors (eg, R1 and R2).
  • the output voltage Vo may be calculated as in the example of Equation 1 below.
  • the second LDO 420 is connected in parallel to the first LDO 410 , which is the reference LDO of the regulating circuit 200 , and operates alone or in conjunction with the first LDO 410 . It may indicate an auxiliary LDO to In one embodiment, the secondary LDO may include one or more LDOs. According to an embodiment, the second LDO 420 may include a pass transistor 421 (or an output transistor), an error amplifier (EA2) 422 , a switch circuit 423 , and a compensation circuit 424 . .
  • EA2 error amplifier
  • the switch circuit 423 may include a first switch SW1 and a second switch SW2.
  • the first switch SW1 and the second switch SW2 connect between the pass transistor 421 and the error amplifier EA2 422 based on the first operation mode signal of the control circuit 400 .
  • the switch circuit 423 may switch the second LDO 420 to operate independently based on the first operation mode signal.
  • the first switch SW1 is switched to be connected to the first compensation circuit ZF2 for compensating a circuit related to a single operation of the second LDO 420 , and the second switch SW2 is open (or open).
  • the second switch SW2 is connected between the first LDO 410 and the second LDO 420 (eg, the pass transistor 411 of the first LDO 410 and It is possible to switch to open the error amplifier (EA2) 422 of the second LDO 420 .
  • EA2 error amplifier
  • the first switch SW1 and the second switch SW2 are the pass transistor 411 of the first LDO 410 and the second LDO ( Switch to connect between the pass transistor 411 of the first LDO 410 and the error amplifier EA2 422 of the second LDO 420 through the connection line 440 between the switch circuit 423 of the 420 . can do.
  • the second LDO 420 is interlocked with (or connected to) the first LDO 410 to form the first LDO 410 and the second LDO ( 420) can be switched to operate as one LDO.
  • the first switch SW1 is switched to be connected to the second compensation circuit ZF21 for compensating a circuit related to the interlocking operation of the first LDO 410 and the second LDO 420
  • the second switch ( SW2 may be switched to connect between the pass transistor 411 of the first LDO 410 and the error amplifier EA2 422 of the second LDO 420 .
  • the first switch SW1 and the second switch SW2 may operate complementaryly.
  • the first switch SW1 may be connected to the first compensation circuit ZF2
  • the second switch SW2 may be open (or open).
  • the first switch SW1 is connected to the second compensation circuit ZF21, and the second switch SW2 is closed (or shorted) to the first LDO 410 .
  • the pass transistor 411) and the second LDO 420 eg, the error amplifier (EA2) 422
  • the compensation circuit 424 (eg, the first compensation circuit ZF2 and the second compensation circuit ZF21) may be a circuit that compensates for the frequency characteristic or stability inside the second LDO 420 .
  • the pass transistor 421 of the second LDO 420 may be connected to the first compensation circuit ZF2 of the compensation circuit 424 in the first operation mode, and the first Stability may be guaranteed based on the compensation circuit ZF2.
  • the pass transistor 411 of the first LDO 410 and the pass transistor 421 of the second LDO 420 are the first of the compensation circuit 424 in the second operation mode.
  • the first operation mode signal or the second operation mode signal may be received as a mode setting signal (or control signal) from the control circuit 400 through the control line 430 .
  • the pass transistor 421 is a transistor operating in a linear region, may have a linear resistance controlled by a gate voltage, and may operate as an on/off switch.
  • the pass transistor 421 may pass or turn off the input voltage VIN.
  • the pass transistor 421 may be disposed between the input voltage VIN and the output voltage VO in the second LDO 420 , and an input/output required for the pass transistor 421 to stably operate.
  • An output voltage can be generated based on the lowest potential difference (or drop out voltage). For example, the lowest input voltage value required for operation of the second LDO 420 is set, and in this case (VO + drop out voltage) may be the lowest operating voltage value of the second LDO 420 .
  • the error amplifier (EA2) 422 may represent an amplifier that compares the reference voltage Vref with the voltage fed back from the output and amplifies the error by the error.
  • the voltage of the non-inverting terminal of the error amplifier (EA2) 422 may be the same as the reference voltage Vref, and the output voltage Vo may be determined by the resistance ratio of the two resistors (eg, R1 and R2).
  • the output voltage Vo may be calculated as in the example of ⁇ Equation 1>.
  • each of the switch circuits 413 and 423 of the first LDO 410 and the second LDO 420 may control an electrical connection based on an external signal (eg, the control circuit 400). It can be composed of various switch elements.
  • the first LDO 410 regulates an input voltage (or a supply voltage) (eg, LDO input), generates an output voltage, and provides an output voltage to a corresponding external device through an output node. can do.
  • the first LDO 410 receives an input voltage through a designated power line 450 in the first operation mode, and regulates the first LDO 410 alone to increase the first output voltage.
  • the first LDO 410 receives an input voltage through a designated power line 450 , and the switch SW of the switch circuit 413 activates the second LDO 420 . It can be switched to connect with
  • the first LDO 410 is connected to the first LDO 410 and the second by the error amplifier (EA2) 422 of the second LDO 420 based on the switching of the switch circuit 413 . It is regulated by interworking of the LDO 420 and may generate a second output voltage different from the first output voltage. In an embodiment, the second output voltage may have an output voltage having an increased current capacity compared to the first output voltage.
  • EA2 error amplifier
  • the regulating circuit 200 may include a plurality of LDOs 410 and 420 .
  • the regulating circuit 200 may be formed such that each LDO of the plurality of LDOs 410 and 420 has an individual control loop that can be independently controlled.
  • the regulating circuit 200 may operate such that the plurality of LDOs 410 and 420 form one control loop to control the plurality of LDOs 410 and 420 .
  • the plurality of LDOs 410 and 420 may each independently operate based on an operation mode, or the plurality of LDOs 410 and 420 may operate together with one LDO.
  • the first LDO 410 and the second LDO 420 are an amplifier (eg, an error amplifier) amplifying the difference between the reference voltage Vref and the feedback voltage. 412 and 422) and pass transistors 411 and 421 providing a final output voltage based on the output voltage of the amplifier, respectively.
  • the first LDO 410 and the second LDO 420 may be configured to include different types of pass transistors 411 and 421 .
  • the regulating circuit 200 is designed to enable parallel connection of a plurality of LDOs 410 and 420 , thereby designing a re-configurable LDO design. may be possible
  • parallel connection of a plurality of LDOs is not possible, but according to an embodiment of the present disclosure, the control loop for each LDO of the plurality of LDOs is operated as one LDO without separately operating, so that current balancing ( current balancing) control may be possible.
  • the plurality of LDOs 410 and 420 may be controlled by one internal control loop. Accordingly, according to an embodiment of the present disclosure, the current capacity may be increased due to the effect of increasing the size of the pass transistor when a plurality of LDOs are connected in parallel. In an embodiment, when the size of the pass transistor increases, the stability of the LDO may also increase.
  • the current capacity can be increased when operating as one LDO by interlocking the plurality of LDOs 410 and 420 according to parallel connection, and a plurality of parallel-connected LDOs
  • the LDOs 410 and 420 By separating the LDOs 410 and 420, it is possible to provide an effect of diversifying the current capacity and increasing the number of power rails when operating independently. For example, due to the increase of the power rail in the regulating circuit 200, more systems (or external devices) can be connected.
  • the first LDO 410 may receive a voltage from at least one second LDO 420 connected in parallel, and thus A stable output voltage (eg, an output voltage with increased amperage) can be generated.
  • FIG. 4 illustrates an example of parallel connection and controlling the parallel connection by two LDOs (eg, the first LDO 410 and the second LDO 420 ), various embodiments are not limited thereto.
  • the circuit design of FIG. 4 may be an example, and according to another embodiment, one or more auxiliary LDOs (eg, second LDO, third LDO, .
  • FIG. 5 Another example of a regulating circuit 200 according to an embodiment is shown in FIG. 5 .
  • FIG. 5 is a diagram illustrating another example of a regulating circuit design in an electronic device according to an embodiment.
  • the regulating circuit 400 includes a plurality of LDOs 410 , 420 , 530 , and as illustrated in FIG. 4 , a first LDO 410 and a second LDO ( In addition to the parallel connection of the 420 , an example of sequentially parallel-connecting at least one additional LDO (eg, the n-th LDO 530 ) after the second LDO 420 may be shown.
  • the first LDO 410 and the second LDO 420 may correspond to the first LDO 410 and the second LDO 420 as described in the description with reference to FIG. 4 . and a description overlapping with FIG. 4 will be omitted.
  • the regulating circuit 200 may include a control circuit 400 , a first LDO 410 , a second LDO 420 , and an n-th LDO 530 .
  • the control circuit 400 forms an independent control loop for each of the plurality of LDOs 410, 420, and 530 connected in parallel.
  • a plurality of LDOs 410 , 420 , and 530 may be controlled.
  • the control circuit 400 includes a plurality of LDOs 410, 420, and 530 connected in parallel to form one control loop as a group. can be controlled
  • the control circuit 400 operates the plurality of LDOs to operate at least one LDO among the plurality of parallel-connected LDOs 410, 420, and 530 based on the power required by the system (eg, a device of hardware). (410, 420, 530) can be controlled.
  • the control circuit 400 is a first operation mode signal or a plurality of LDOs 410, 420, for a first operation mode for each LDO of the plurality of LDOs 410, 420, 530 to operate independently.
  • 530 may provide a second operation mode signal for a second operation mode that allows each of the LDOs to operate simultaneously.
  • the first operation mode signal and the second operation mode signal may be provided to the plurality of LDOs 410 , 420 , and 530 as a mode setting signal (or control signal) from the control circuit 400 .
  • the first operation mode signal and the second operation mode signal are switched from the control circuit 400 through one control line 430 to the plurality of LDOs 410 , 420 , 530 respectively corresponding to the switch circuit ( 413, 423, 533).
  • the first LDO 410 and the second LDO 420 may respectively correspond to the first LDO 410 and the second LDO 420 as described in the description with reference to FIG. 4 .
  • the n-th LDO 530 may include a configuration (or design) corresponding to the second LDO 420 as described in the description with reference to FIG. 4 .
  • the n-th LDO 530 may drive a corresponding system with the n-th output voltage.
  • the n-th LDO 530 may be coupled (or electrically connected) to the first LDO 410 and the second LDO 420 in parallel.
  • the first LDO 410 , the second LDO 420 , and the n-th LDO 530 are coupled in parallel, the first LDO 410 , the second LDO 420 and the n-th LDO
  • the current capacity according to the combination of 530 may drive a corresponding system with an increased output voltage.
  • the first LDO 410 may represent a reference LDO for parallel connection between the plurality of LDOs 410 , 420 , and 530 in the regulating circuit 200 of the present disclosure.
  • the first LDO 410 includes a pass transistor 411 (or an output transistor), an error amplifier (EA1) 412 , a switch circuit 413 , and a compensation circuit ZF1 . (414).
  • the second LDO 420 and the n-th LDO 530 are connected in parallel to the first LDO 410 that is the reference LDO of the regulating circuit 200, either alone or the first LDO It may indicate an auxiliary LDO operating in conjunction with 410 .
  • the second LDO 420 includes a pass transistor 421 (or an output transistor), an error amplifier (EA2) 422 , a switch circuit 423 , and a compensation circuit 424 .
  • the nth LDO 530 may include a configuration corresponding to the second LDO 420 , for example, the nth LDO 530 may include a pass transistor 531 (or an output transistor). , an error amplifier (EAn) 532 , a switch circuit 533 , and a compensation circuit 534 .
  • the n-th LDO 530 illustrated in FIG. 5 will be described.
  • the switch circuit 533 may include a first switch SW3 and a second switch SW4 .
  • the first switch SW3 and the second switch SW4 connect between the pass transistor 531 and the error amplifier (EAn) 532 based on the first operation mode signal of the control circuit 400 .
  • the switch circuit 533 may switch the n-th LDO 530 to operate independently based on the first operation mode signal.
  • the first switch SW3 is switched to be connected to the first compensation circuit ZFn for compensating a circuit related to a single operation of the n-th LDO 530
  • the second switch SW4 is open (or open).
  • the second switch SW4 is connected between the first LDO 410 and the n-th LDO 530 (eg, the pass transistor 411 of the first LDO 410 ) based on the first operation mode signal. It is possible to switch to open the error amplifier (EAn) 532 of the n-th LDO 530 .
  • EAn error amplifier
  • the first switch SW3 and the second switch SW4 are connected to the first LDO 410 and the second LDO through the connection line 440 based on the second operation mode signal of the control circuit 400 .
  • Switching may be performed to connect the pass transistors 411 and 421 of the 420 and the error amplifier (EAn) 532 of the n-th LDO 530 .
  • the n-th LDO 530 is interlocked with (or connected to) the first LDO 410 and the second LDO 420 to form the first LDO ( 410), the second LDO 420, and the n-th LDO 530 may be switched to operate as one LDO.
  • the first switch SW3 is switched to be connected to the second compensation circuit ZFn1 for compensating a circuit related to the interlocking operation of the first LDO 410 and the n-th LDO 530
  • the second switch ( SW4 may be switched to connect between the pass transistors 411 and 421 of the first LDO 410 and the second LDO 420 and the error amplifier (EAn) 532 of the n-th LDO 530 .
  • the first switch SW3 and the second switch SW4 may operate complementary.
  • the first switch SW3 in the first operation mode, the first switch SW3 may be connected to the first compensation circuit ZFn, and the second switch SW4 may be open (or open).
  • the first switch SW3 in the second operation mode, the first switch SW3 is connected to the second compensation circuit ZFn1 , and the second switch SW4 is closed (or short-circuited) to the first LDO 410 and the second It may be connected to the LDO 420 (eg, pass transistors 411 and 421 ) and the n-th LDO 530 (eg, an error amplifier (EAn) 532 ).
  • LDO 420 eg, pass transistors 411 and 421
  • the n-th LDO 530 eg, an error amplifier (EAn) 532 .
  • the compensation circuit 534 (eg, the first compensation circuit ZFn and the second compensation circuit ZFn1 ) may be a circuit compensating for frequency characteristics or stability inside the n-th LDO 530 .
  • the n-th LDO 530 switches to connect the first compensation circuit ZFn of the compensation circuit 534 in the first operation mode, and stability is guaranteed based on the first compensation circuit ZFn.
  • the n-th LDO 530 switches to connect the second compensation circuit ZFn1 of the compensation circuit 534 in the second operation mode, and stability is guaranteed based on the second compensation circuit ZFn1.
  • the first operation mode signal or the second operation mode signal may be received as a mode setting signal (or control signal) from the control circuit 400 through the control line 430 .
  • the pass transistor 531 is a transistor operating in a linear region, may have a linear resistance controlled by a gate voltage, and may operate as an on/off switch.
  • the pass transistor 531 may pass or turn off the input voltage VIN.
  • the pass transistor 421 may be disposed between the input voltage VIN and the output voltage VO in the second LDO 420 , and an input/output required for the pass transistor 531 to stably operate.
  • An output voltage can be generated based on the lowest potential difference (or drop out voltage).
  • the minimum input voltage value required for operation of the n-th LDO 530 is set, and in this case (VO + drop out voltage) may be the minimum operating voltage value of the n-th LDO 420 .
  • the error amplifier (EAn) 532 may represent an amplifier that compares the reference voltage Vref with the voltage fed back from the output and amplifies the error by the error.
  • the voltage of the non-inverting terminal of the error amplifier (EAn) 532 may be the same as the reference voltage Vref, and the output voltage Vo is determined by the resistance value ratio of the two resistors (eg, R1 and R2).
  • the output voltage Vo may be calculated as in the example of ⁇ Equation 1>.
  • each of the switch circuits 413 , 423 , and 533 of the first LDO 410 , the second LDO 420 , and the third LDO 530 is an external signal (eg, the control circuit 400 ). It may be composed of various switch elements that can control the electrical connection based on the
  • the first LDO 410 may generate an output voltage by regulating an input voltage (or a supply voltage), and may provide it to a corresponding external device through an output node.
  • the first LDO 410 receives an input voltage through a designated power line 450 in the first operation mode, and regulates the first LDO 410 alone to increase the first output voltage.
  • the first LDO 410 receives an input voltage through a designated power line 450 in the second operation mode, and the switch SW of the switch circuit 413 activates the second LDO 420 . And it can be switched to be connected to the n-th LDO (530).
  • the first LDO 410 receives a voltage from the second LDO 420 and the nth LDO 530 based on the switching of the switch circuit 413 , and the first LDO 410 , the nth LDO 530 , The second LDO 420 and the n-th LDO 530 may be regulated to generate a second output voltage different from the first output voltage.
  • the second output voltage may have an output voltage having an increased current capacity compared to the first output voltage.
  • the regulating circuit 200 may include a plurality of LDOs 410 , 420 , and 530 .
  • the regulating circuit 200 may be formed so that each LDO of the plurality of LDOs 410 , 420 , and 530 has an individual control loop that can be independently controlled.
  • the regulating circuit 200 may operate such that the plurality of LDOs 410 , 420 , and 530 form one control loop to control the plurality of LDOs 410 , 420 , and 530 .
  • the plurality of LDOs 410, 420, and 530 may each independently operate based on an operation mode, or the plurality of LDOs 410, 420, and 530 may operate together with one LDO.
  • the first LDO 410 , the second LDO 420 , and the n-th LDO 530 amplify the difference between the reference voltage Vref and the feedback voltage.
  • amplifiers eg, error amplifiers 412 , 422 , and 532
  • pass transistors 411 , 421 , and 531 that provide a final output voltage based on the output voltage of the amplifier, respectively.
  • the first LDO 410 , the second LDO 420 , and the n-th LDO 530 may be configured to include different types of pass transistors 411 , 421 , and 531 .
  • the regulating circuit 200 is designed to enable parallel connection of at least three or more LDOs 410 , 420 , and 530 . design may be possible.
  • the first LDO 410 includes a plurality of LDOs connected in parallel (eg, the second LDO 420 and the n-th LDO 530 ). ), it is possible to generate a stable output voltage (eg, an output voltage with increased current capacity) by regulating it.
  • a stable output voltage eg, an output voltage with increased current capacity
  • FIGS. 4 and 5 an example of parallel connection and control of a plurality of LDOs in one control circuit 400 is illustrated, but various embodiments are not limited thereto.
  • the circuit design of FIGS. 4 and/or 5 may be an example, and according to another embodiment, a plurality of control circuits are configured, and a pair of a reference LDO and at least one auxiliary LDO is configured for each of the plurality of control circuits. may include an embodiment that connects them in parallel and controls them.
  • FIG. 6 Another example of a regulating circuit 200 according to an embodiment is shown in FIG. 6 .
  • FIG. 6 is a diagram illustrating another example of a regulating circuit design in an electronic device according to an exemplary embodiment.
  • the regulating circuit 400 includes a plurality of control circuits (eg, a first control circuit 400A and a second control circuit 400B), and a plurality of control circuits 400A. , 400B) may represent an example in which a pair of a reference LDO and at least one auxiliary LDO is coupled in parallel (or electrically connected), respectively.
  • a control circuit eg, control circuit 400
  • a reference LDO eg, first LDO 410
  • at least one auxiliary LDO eg, as illustrated in FIG. 4 or FIG. 5
  • An example of additionally connecting the structure of the second LDO 420 in parallel may be shown.
  • the first LDO 410 and the second LDO 420 are the first LDO 410 and the second LDO 420 as described in the description with reference to FIGS. 4 and 5 . can respond to
  • the regulating circuit 200 is a first group including a first control circuit 400A, a first LDO 410 and a second LDO 420 connected to the first control circuit 400A. and a circuit design including a second group including a second control circuit 400B, a third LDO 630 and a fourth LDO 640 connected to the second control circuit 400B.
  • the first control circuit 400A is configured to form an independent control loop for each of the plurality of LDOs 410 and 420 connected in parallel. , 420) can be controlled.
  • the first control circuit 400A controls the plurality of LDOs 410 and 420 to form one control loop by grouping the plurality of LDOs 410 and 420 connected in parallel.
  • the second control circuit 400B is configured to form an independent control loop for each of the plurality of LDOs 630 and 640 connected in parallel to each of the plurality of LDOs 630 and 640 . , 640) can be controlled.
  • the second control circuit 400B controls the plurality of LDOs 630 and 640 to form one control loop by grouping the plurality of LDOs 630 and 640 connected in parallel.
  • each of the first control circuit 400A and the second control circuit 400B operates at least one LDO among a plurality of LDOs connected in parallel based on the power required by the system (eg, a hardware element). Switching of a plurality of LDOs may be controlled to do so.
  • the first control circuit 400A is a first operation mode signal or a plurality of LDOs 410 and 420 for a first operation mode for allowing each LDO of the plurality of LDOs 410 and 420 to operate independently. It is possible to provide a second operation mode signal for a second operation mode that allows each LDO of the LDOs to operate simultaneously.
  • the first operation mode signal and the second operation mode signal may be provided to the plurality of LDOs 410 and 420 as a mode setting signal (or control signal) from the first control circuit 400A.
  • the first operation mode signal and the second operation mode signal of the first control circuit 400A are connected to the switch circuits corresponding to the plurality of LDOs 410 and 420 through the first control line 430A, respectively. 413, 423).
  • the second control circuit 400B is a first operation mode signal or a plurality of LDOs 630 and 640 for a first operation mode for allowing each LDO of the plurality of LDOs 630 and 640 to operate independently. It is possible to provide a second operation mode signal for a second operation mode that allows each LDO of the LDOs to operate simultaneously.
  • the first operation mode signal and the second operation mode signal may be provided to the plurality of LDOs 630 and 640 as a mode setting signal (or control signal) from the second control circuit 400B.
  • the first operation mode signal and the second operation mode signal of the second control circuit 400B are connected to the switch circuits corresponding to the plurality of LDOs 630 and 640 through the second control line 430B, respectively. 633, 643).
  • the first LDO 410 may indicate a reference LDO of the first group
  • the second LDO 420 may indicate at least one auxiliary LDO of the first group.
  • the first LDO 410 and the second LDO 420 may respectively correspond to the first LDO 410 and the second LDO 420 as described in the description with reference to FIG. 4 .
  • the third LDO 630 may indicate a reference LDO of the second group
  • the fourth LDO 640 may indicate at least one auxiliary LDO of the second group.
  • the third LDO 630 and the fourth LDO 640 are configured (or respectively) corresponding to the first LDO 410 and the second LDO 420 as described in the description with reference to FIG. 4 . design) may be included.
  • the third LDO 630 may include a configuration corresponding to the first LDO 410
  • the fourth LDO 640 may include a configuration corresponding to the second LDO 420 .
  • the third LDO 630 of the second group includes a pass transistor 411 , an error amplifier (EA1) 412 , a switch circuit 413 , and as described in the description with reference to FIG. 4 . It may include a pass transistor 631 , an error amplifier (EA3) 632 , a switch circuit 633 , and a compensation circuit (ZF3) 634 respectively corresponding to the compensation circuits ZF1 and 414 .
  • the fourth LDO 640 of the second group includes a pass transistor 421 , an error amplifier (EA2) 422 , a switch circuit 423 , and as described in the description with reference to FIG. 4 . It may include a pass transistor 641, an error amplifier (EA4) 642, a switch circuit 643, and compensation circuits ZF4, ZF41 and 644 corresponding to the compensation circuits ZF2 and ZF21 and 424, respectively. have.
  • the regulating circuit 200 illustrated in FIG. 6 may perform substantially similar or the same operation as the regulating circuit 200 of FIGS. 4 and/or 5, and the overlapping description is omit
  • the first LDO 410 and the second LDO 420 of the first group, and the third LDO 630 and the fourth LDO 640 of the second group, respectively, have a first operation mode and In the second operation mode, an input voltage may be commonly provided through one designated power line 450 , and an output voltage may be generated by regulating the input voltage alone or in association.
  • the regulating circuit 200 is a first group, and the first operation mode signal or the second operation mode signal is transmitted from the first control circuit 400A through the control line 430A through the mode setting signal (or control signal).
  • the regulating circuit 200 is in the second group, and the first operation mode signal or the second operation mode signal is the mode setting signal (or the second operation mode signal) from the second control circuit 400B through the control line 430B. control signal).
  • the first LDO 410 and the second LDO 420 of the first group may be configured by the first LDO ( ) based on the second operation mode signal of the first control circuit 400A of the first group.
  • the pass transistor 411 of the first LDO 410 and the second LDO 420 through the first connection line 440A between the pass transistor 411 of the 410 and the switch circuit 423 of the second LDO 420 ) of the error amplifier (EA2) 422 can be switched to connect.
  • the switch circuit 413 of the first LDO 410 and the switch circuit 423 of the second LDO 420 are based on the second operation mode signal of the first control circuit 400A Accordingly, the first LDO 410 and the second LDO 420 may be interlocked (or connected) to switch the first LDO 410 and the second LDO 420 to operate as one LDO.
  • the third LDO 630 and the fourth LDO 640 of the second group based on the second operation mode signal of the second control circuit 400B of the second group, the third LDO ( The pass transistor 631 and the fourth LDO 640 of the third LDO 630 through the second connection line 440B between the pass transistor 631 of the 630 and the switch circuit 643 of the fourth LDO 640 ) of the error amplifier (EA4) 642 can be switched to connect.
  • the switch circuit 633 of the third LDO 630 and the switch circuit 643 of the second LDO 640 are based on the second operation mode signal of the second control circuit 400B. Accordingly, the third LDO 630 and the fourth LDO 640 may be interlocked (or connected) to switch the third LDO 630 and the second LDO 640 to operate as one LDO.
  • the regulating circuit 200 may operate as a pair system.
  • it includes a plurality of control circuits (eg, the first control circuit 400A and the second control circuit 400B), and includes a reference LDO and at least one auxiliary LDO for each of the plurality of control circuits 400A and 400B.
  • Each pair may be coupled (or electrically coupled) in parallel.
  • the structures of the control circuit 400, the reference LDO, and the at least one auxiliary LDO are additionally connected in parallel as illustrated in FIG. 4 or 5, so that the parallel connection of the LDOs for each group You can control the following actions.
  • the regulating circuit 200 includes a first control circuit 400A, a first group including a first LDO 410 and a second LDO 420 connected to the first control circuit 400A. And, when implemented as a pair system, such as a second group including the second control circuit 400B, the third LDO 630 and the fourth LDO 640 connected to the second control circuit 400B, the first The first control circuit 400A of the group and the second control circuit 400B of the second group have the same operation mode (eg, 'first operation mode' or 'second operation mode') for each reference LDO and at least one auxiliary LDO. 2 operation mode').
  • operation mode eg, 'first operation mode' or 'second operation mode'
  • the first control circuit 400A of the first group and the second control circuit 400B of the second group have different operation modes (eg, for each reference LDO and at least one auxiliary LDO) 'first operation mode and second operation mode' or 'second operation mode and first operation mode').
  • auxiliary LDOs eg, second LDO 420 and fourth LDO
  • reference LDOs eg, first LDO 410 and third LDO 630
  • 640 is illustrated as an example in which each LDO is implemented, the present invention is not limited thereto.
  • the auxiliary LDO in each group may be implemented as a plurality of auxiliary LDOs including at least one additional LDO, as illustrated in FIG. 5 .
  • at least one additional LDO may be sequentially connected in parallel after the second LDO 420 in the first group, and at least one additional LDO may be sequentially connected in parallel after the fourth LDO 640 in the second group.
  • the regulating circuit 200 of the electronic device 101 includes a plurality of parallel connectable low drop outs (LDOs) (eg, the first LDO 410 of FIG. 4 ). , a second LDO (420), and control circuitry (control circuitry 400 of FIG. 4) operatively coupled to the plurality of LDOs (410, 420), the control circuit (400) Forms one control loop related to the control of the plurality of parallel-connected LDOs 410 and 420, and forms at least one of the parallel-connected plurality of LDOs 410 and 420 based on the power required in the system.
  • the plurality of LDOs 410 and 420 may be controlled so that one LDO operates.
  • the plurality of LDOs 410 and 420 include a first LDO (eg, the first LDO 410 of FIG. 4 ) that provides a first output for driving the system, and the At least one second LDO electrically connected in parallel to the first LDO 410 and providing a second output for driving the system (eg, the second LDO 420 of FIG. 4 or 5 or FIG. 6 ) of the n-th LDO 530).
  • a first LDO eg, the first LDO 410 of FIG. 4
  • the At least one second LDO electrically connected in parallel to the first LDO 410 and providing a second output for driving the system (eg, the second LDO 420 of FIG. 4 or 5 or FIG. 6 ) of the n-th LDO 530).
  • the plurality of LDOs 410 and 420 may be electrically connected to the first LDO 410 and the second LDO 420 when the first LDO 410 and the second LDO 420 are electrically connected in parallel.
  • a corresponding system may be driven by the third output of which the current capacity is increased according to the connection of the second LDO 420 .
  • the input of the plurality of LDOs 410 and 420 uses one input in common
  • the output of the plurality of LDOs 410 and 420 is the output of the plurality of LDOs 410 , 420), or may be controlled to use one output in common when connected in parallel.
  • the first LDO 410 and the second LDO 420 form an independent control loop in the first operation mode under the control of the control circuit 400 and are independent It may be set to output power to each system corresponding to .
  • the first LDO 410 and the second LDO 420 form one control loop in the second operation mode under the control of the control circuit 400, and correspond It can be set to output one power with increased current capacity to one system.
  • control circuit 400 controls the plurality of LDOs 410 and 420 to form an independent control loop for each of the plurality of LDOs 410 and 420 connected in parallel, or , or to form one control loop by the plurality of LDOs 410 and 420 connected in parallel, it may be configured to control the plurality of LDOs 410 and 420 .
  • control circuit 400 may include a first operation mode signal for a first operation mode in which each LDO of the plurality of LDOs 410 and 420 connected in parallel operates independently, or the It may be configured to provide a second operation mode signal for a second operation mode in which each LDO of the plurality of LDOs 410 and 420 operates simultaneously.
  • the first operation mode signal and the second operation mode signal are transmitted from the control circuit 400 through one control line (eg, the control line 430 of FIG. 4 ).
  • the LDOs 410 and 420 may be configured to be provided to a switch circuit (eg, the switch circuits 413 and 423 of FIG. 4 ) respectively.
  • the first LDO 410 is a reference LDO for parallel connection between the plurality of LDOs 410 and 420 , and a first pass transistor (eg, the pass transistor of FIG. 4 ) 411 ), a first error amp (eg, error amplifier 412 of FIG. 4 ), a first switch (eg, switch circuit 413 of FIG. 4 ), and a first compensation circuit (eg: compensation circuit 414 of FIG. 4).
  • a first pass transistor eg, the pass transistor of FIG. 4
  • a first error amp eg, error amplifier 412 of FIG. 4
  • a first switch eg, switch circuit 413 of FIG. 4
  • a first compensation circuit eg: compensation circuit 414 of FIG. 4
  • the second LDO 420 is an auxiliary LDO connected in parallel to the reference LDO and operated alone or in conjunction with the reference LDO, and a second pass transistor (eg, in FIG. 4 ). pass transistor 421), a second error amplifier (eg, the error amplifier 422 of FIG. 4 ), a second switch (eg, the first switch SW1 of FIG. 4 ), and a third switch (eg, the error amplifier 422 of FIG. 4 ) a second switch SW2), a second compensation circuit (eg, the first compensation circuit ZF2 of FIG. 4 ), and a third compensation circuit (eg, the second compensation circuit ZF21 of FIG. 4 ).
  • a second error amplifier eg, the error amplifier 422 of FIG. 4
  • a second switch eg, the first switch SW1 of FIG. 4
  • a third switch eg, the error amplifier 422 of FIG. 4
  • a second switch SW2 eg, the first compensation circuit ZF2 of FIG. 4
  • a third compensation circuit
  • the first LDO 410 in the first operation mode controlled by the control circuit 400 , is configured to perform the first pass transistor and the first switch based on the switching of the first switch. It may be configured to connect between the first error amplifiers and connect the first compensation circuit related to the single operation of the first LDO 410 to operate independently.
  • the second LDO 420 is based on the switching of the second switch, and the second LDO 420 is The second compensation circuit related to a single operation of
  • the first LDO 410 in the second operation mode controlled by the control circuit 400 , is configured to perform the second operation of the first LDO based on the switching of the first switch. It may be controlled to connect between the one pass transistor and the second error amplifier of the second LDO.
  • the second LDO 420 performs an interlocking operation of the second LDO based on the switching of the second switch.
  • control to connect the third compensation circuit related to can be
  • the first LDO 410 and the second LDO 420 are connected to be set to operate as one LDO.
  • the first LDO 410 receives an input voltage through a designated power line in the second operation mode, and connects the first switch to the second LDO 420 . switching, and regulating by interworking between the first LDO 410 and the second LDO 420 by the second error amplifier of the second LDO 420 based on the switching of the first switch, It is set to generate a second output different from the first output, and the second output may include an output having an increased current capacity than the first output.
  • connection between the first pass transistor and the first error amplifier or between the first pass transistor and the second error amplifier is connected to a gate driver of the first pass transistor and the It may include a connection between the first error amplifier or the second error amplifier.
  • the second LDO 420 may be configured to include a plurality of LDOs sequentially connected in parallel to the first LDO 410 .
  • control circuit 400 includes a first control circuit (eg, the first control circuit 400A of FIG. 6 ) and a second control circuit (eg, the second control circuit (eg) of FIG. 6 ) 400B)).
  • the first control circuit 400A is connected to a first basic LDO and at least one first auxiliary LDO connected in parallel to the first basic LDO, the first basic LDO and the first basic LDO It may be configured to control an operation mode of the at least one first auxiliary LDO.
  • the second control circuit 400B is connected to a second basic LDO and at least one second auxiliary LDO connected in parallel to the second basic LDO, the second basic LDO and the second basic LDO It may be configured to control an operation mode of the at least one second auxiliary LDO.
  • operations performed by the electronic device 101 to be described below are performed by a processor (eg, the processor 120 of FIG. 1 ) including at least one processing circuitry of the electronic device 101 . ) or the control circuit 400 of FIG. 2 ).
  • the operations performed by the electronic device 101 may be stored in the memory 130 and, when executed, may be executed by instructions that cause the processor 120 to operate.
  • FIG. 7 is a flowchart illustrating a method of operating an electronic device according to various embodiments of the present disclosure
  • the control circuit 400 of the regulating circuit 200 may detect activation of at least one LDO in the circuit.
  • the control circuit 400 may detect LDO activation based on a supply voltage request signal to a system (eg, a hardware device).
  • the control circuit 400 may determine whether a plurality of LDOs connected in parallel operate in conjunction or operate alone, based on the activation of the LDOs.
  • the power required by the system may be provided by a single operation of a corresponding one of a plurality of LDOs connected in parallel according to the power required by the system.
  • the power required by the system may be provided through an interlocking operation of a plurality of corresponding parallel-connected LDOs.
  • control circuit 400 may set a compensation circuit related to the use of the independently operated corresponding LDO. .
  • the control circuit 400 may control switching to connect between the pass transistor of the corresponding LDO and the error amplifier.
  • the control circuit 400 provides a first operation mode signal to a switch circuit of a plurality of LDOs connected in parallel, and each LDO of the plurality of LDOs operates independently based on switching to the first operation mode. can do it
  • the control circuit 400 may control switching for connection of a pass transistor of the corresponding LDO.
  • the control circuit 400 may connect the pass transistor of the corresponding LDO and the error amplifier based on the switching control using the first operation mode signal.
  • the LDO can connect between the gate driver of the pass transistor and the error amplifier.
  • control circuit 400 may activate the corresponding LDO.
  • control circuit 400 generates an output voltage by regulating the input voltage by operating the corresponding LDO in the first operation mode based on the connection control corresponding to the corresponding LDO, and generating the output voltage may operate to provide a corresponding system.
  • the control circuit 400 sets a compensation circuit related to the use of the plurality of parallel-connected LDOs.
  • the control circuit 400 may control a connection between a pass transistor of a reference LDO of the plurality of LDOs and an error amplifier of at least one auxiliary LDO connected in parallel to the reference LDO.
  • the control circuit 400 provides the second operation mode signal to the switch circuit of the plurality of LDOs, and based on each LDO of the plurality of LDOs connected to the second operation mode, the plurality of LDOs are interlocked to form one You can make it work as an LDO.
  • the control circuit 400 may control switching for a pass transistor connection between the reference LDO and the auxiliary LDO.
  • the control circuit 400 may connect a pass transistor of a reference LDO and an error amplifier of at least one auxiliary LDO in the plurality of LDOs based on control using the second operation mode signal.
  • the plurality of LDOs may connect a gate driver of a pass transistor of a reference LDO and an error amplifier of at least one auxiliary LDO.
  • the control circuit 400 may activate a plurality of LDOs.
  • the control circuit 400 generates an output voltage by regulating the input voltage by operating the plurality of LDOs in the second operation mode based on the connection control of the plurality of LDOs, and the generated output voltage may operate to provide a corresponding system.
  • the control circuit 400 may operate to provide a voltage by combining (or connecting) the outputs of the plurality of LDOs connected in parallel to increase the current capacity of the plurality of LDOs.
  • the control circuit 400 separates the outputs of a plurality of LDOs connected in parallel to provide a voltage with a current capacity satisfied by each of the plurality of LDOs, and according to the separation of the outputs of the plurality of LDOs, a power rail can operate to increase the number of For example, in FIGS. 4 and/or 5 , the first LDO 410 and the second LDO 420 are connected in parallel to increase the current capacity, or the first LDO 410 and the second LDO 420 are connected in parallel. Separation can reduce the current capacity and increase the power rail.
  • control circuit 400 may simultaneously control pass transistors respectively corresponding to at least two LDOs connected in parallel.
  • the stability of the LDO operation may be improved by changing the respective compensation circuits.
  • the operation method performed by the regulating circuit 200 of the electronic device 101 includes at least one low drop out (LDO) in the regulating circuit 200 (eg, : The operation of detecting the activation of the first LDO 410 and the second LDO 420 of FIG.
  • LDO low drop out
  • the operation in the second operation mode may include operating the plurality of LDOs as one LDO.
  • the operation in the second operation mode includes an operation of driving a corresponding system with an output with increased current capacity based on the parallel connection of the plurality of LDOs 410 and 420 . can do.
  • detecting the activation may include operating based on a supply voltage request signal to the system.

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Abstract

Selon un mode de réalisation, la présente invention porte sur un circuit de régulation comprenant un montage en parallèle d'une pluralité de régulateurs linéaires, dans un dispositif électronique, et sur un procédé de fonctionnement du circuit de régulation. Le circuit de régulation du dispositif électronique selon un mode de réalisation de la présente invention comprend : une pluralité de régulateurs à faible chute de tension (LDO) qui peuvent être connectés en parallèle ; et une circuiterie de commande connectée fonctionnellement à la pluralité de LDO, la circuiterie de commande pouvant former une boucle de commande relative à la commande de la pluralité de LDO connectés en parallèle, et commander la pluralité de LDO de telle sorte qu'au moins un LDO de la pluralité de LDO connectés en parallèle fonctionne sur la base d'une puissance requise par le système. Divers modes de réalisation sont possibles.
PCT/KR2022/002328 2021-03-26 2022-02-17 Circuit de régulation comprenant une pluralité de régulateurs linéaires et son procédé de fonctionnement WO2022203207A1 (fr)

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KR1020210039806A KR20220134306A (ko) 2021-03-26 2021-03-26 복수의 리니어 레귤레이터를 포함하는 레귤레이팅 회로 및 그의 동작 방법
KR10-2021-0039806 2021-03-26

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115963888A (zh) * 2023-03-16 2023-04-14 杭州朗迅科技股份有限公司 一种恒流控制装置及恒流控制方法
CN116418230A (zh) * 2023-06-12 2023-07-11 上海海栎创科技股份有限公司 一种宽范围滤波电容ldo结构、系统及使用方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20130027808A (ko) * 2011-09-08 2013-03-18 삼성전자주식회사 전력 제어 장치 및 방법
KR20150027413A (ko) * 2013-09-02 2015-03-12 삼성전자주식회사 프로세서 내에 집적되는 온도 센서, 이의 동작 방법 및 상기 온도 센서를 포함하는 장치
KR20190140386A (ko) * 2018-06-11 2019-12-19 에스케이하이닉스 주식회사 디지털 ldo 레귤레이터 및 그의 동작 방법
KR20190142724A (ko) * 2018-06-18 2019-12-27 아날로그 디바이시즈 글로벌 언리미티드 컴퍼니 병렬 선형 전압 레귤레이터 간의 무손실 전류 밸런싱 및 공유
KR20200006749A (ko) * 2018-07-11 2020-01-21 고려대학교 산학협력단 이중모드 ldo 레귤레이터 및 그 동작 방법

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20130027808A (ko) * 2011-09-08 2013-03-18 삼성전자주식회사 전력 제어 장치 및 방법
KR20150027413A (ko) * 2013-09-02 2015-03-12 삼성전자주식회사 프로세서 내에 집적되는 온도 센서, 이의 동작 방법 및 상기 온도 센서를 포함하는 장치
KR20190140386A (ko) * 2018-06-11 2019-12-19 에스케이하이닉스 주식회사 디지털 ldo 레귤레이터 및 그의 동작 방법
KR20190142724A (ko) * 2018-06-18 2019-12-27 아날로그 디바이시즈 글로벌 언리미티드 컴퍼니 병렬 선형 전압 레귤레이터 간의 무손실 전류 밸런싱 및 공유
KR20200006749A (ko) * 2018-07-11 2020-01-21 고려대학교 산학협력단 이중모드 ldo 레귤레이터 및 그 동작 방법

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115963888A (zh) * 2023-03-16 2023-04-14 杭州朗迅科技股份有限公司 一种恒流控制装置及恒流控制方法
CN115963888B (zh) * 2023-03-16 2023-05-12 杭州朗迅科技股份有限公司 一种恒流控制装置及恒流控制方法
CN116418230A (zh) * 2023-06-12 2023-07-11 上海海栎创科技股份有限公司 一种宽范围滤波电容ldo结构、系统及使用方法
CN116418230B (zh) * 2023-06-12 2023-09-12 上海海栎创科技股份有限公司 一种宽范围滤波电容ldo结构、系统及使用方法

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