WO2022198972A1 - 一种服务器启动过程中的故障定位方法、系统及装置 - Google Patents

一种服务器启动过程中的故障定位方法、系统及装置 Download PDF

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Publication number
WO2022198972A1
WO2022198972A1 PCT/CN2021/121421 CN2021121421W WO2022198972A1 WO 2022198972 A1 WO2022198972 A1 WO 2022198972A1 CN 2021121421 W CN2021121421 W CN 2021121421W WO 2022198972 A1 WO2022198972 A1 WO 2022198972A1
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power supply
server
bios
abnormal
chip
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PCT/CN2021/121421
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English (en)
French (fr)
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韩红瑞
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山东英信计算机技术有限公司
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Priority to US18/036,573 priority Critical patent/US20240012706A1/en
Publication of WO2022198972A1 publication Critical patent/WO2022198972A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
    • G06F11/0709—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment in a distributed system consisting of a plurality of standalone computer nodes, e.g. clusters, client-server systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/079—Root cause analysis, i.e. error or fault diagnosis
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0751—Error or fault detection not based on redundancy
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0766—Error or fault reporting or storing
    • G06F11/0775—Content or structure details of the error report, e.g. specific table structure, specific error fields
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0793—Remedial or corrective actions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/14—Error detection or correction of the data by redundancy in operation
    • G06F11/1402—Saving, restoring, recovering or retrying
    • G06F11/1415—Saving, restoring, recovering or retrying at system level
    • G06F11/1417—Boot up procedures
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2284—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing by power-on test, e.g. power-on self test [POST]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/3051—Monitoring arrangements for monitoring the configuration of the computing system or of the computing system component, e.g. monitoring the presence of processing resources, peripherals, I/O links, software programs
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/3055—Monitoring arrangements for monitoring the status of the computing system or of the computing system component, e.g. monitoring if the computing system is on, off, available, not available
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/3065—Monitoring arrangements determined by the means or processing involved in reporting the monitored data

Definitions

  • the present application relates to the field of server operation and maintenance, and in particular, to a method, system and device for locating faults during server startup.
  • the purpose of the present application is to provide a method, system and device for locating faults in the process of starting a server, which performs fault monitoring at each stage in the process of starting a server, which is helpful for locating faults in the process of starting a server.
  • the present application provides a fault location method during server startup, including:
  • the startup process of the server When the startup process of the server enters the target stage, monitor the current startup process of the server according to the fault monitoring policy corresponding to the target stage, and obtain the fault monitoring result corresponding to the target stage; wherein, the target stage is the server any stage of the entire startup process;
  • the fault location of the server is performed according to the obtained fault monitoring result.
  • the entire startup process of the server is divided into a process of multiple stages, including:
  • the entire startup process of the server is divided into a power-on mode entry stage, a hardware power-on stage, a BIOS self-check stage, a BIOS running stage, and an OS startup stage.
  • the server includes a CPLD for receiving a button signal of the power button and transparently transmitting the button signal to the ME unit; and a CPLD for returning a power-on start signal to the CPLD after receiving the button signal to complete the ME unit of the power-up mode entry phase;
  • the process of setting a fault monitoring strategy for the power-on mode entry stage includes:
  • the server further comprises a memory chip connected to the ME unit through a channel switching device and used for storing the ME image file;
  • the method for locating faults in the server startup process further includes:
  • the power supply system of the server includes a PSU and a plurality of VR power supply chips connected to the PSU and used for correspondingly supplying power to each component of the server;
  • the CPLD is also used to send the main power enable signal to the PSU after receiving the power-on start signal, and to sequentially send the chip enable signal to a plurality of VR power supply chips after receiving the PG signal returned by the PSU, And after receiving the PG signals returned by all VR power supply chips, send out a power supply normal signal to complete the hardware power-on stage; the CPLD is also used to return the PG when the PSU or any VR power supply chip is not on time after the version update. When the signal is received, the abnormal situation is recorded to its own status register, and the VR power supply chip and PSU that have been powered on are controlled in turn to power off;
  • the process of setting a fault monitoring strategy for the hardware power-on phase includes:
  • the power supply normal signal is not sent, then determine that the power-on of the mainboard hardware of the server is abnormal, and judge whether the CPLD has an abnormal recording function according to the version number of the CPLD;
  • If there is no abnormal recording function read the status registers of the PSU and VR power supply chips to locate the abnormal situation of the PSU or VR power supply chip, and when the VR power supply chip has abnormal conditions, according to the abnormal VR power supply chip
  • the register status analysis of abnormal VR power supply chip failure causes.
  • the process of analyzing the fault cause of the abnormal VR power supply chip according to the register state of the abnormal VR power supply chip includes:
  • the abnormal VR power supply chip If it is determined that the abnormal VR power supply chip has input undervoltage according to the register state of the abnormal VR power supply chip, query whether the voltage of the previous VR power supply chip of the abnormal VR power supply chip is normal. The link between the upper-level VR power supply chips is faulty;
  • next-level circuit is a VR power supply chip
  • next-level circuit is a direct component and the direct component cannot be accessed, it is determined that the direct component needs to be replaced, and the location or number of the direct component is recorded.
  • the CPU of the server is used to start working after the CPLD sends a power supply normal signal, and start the BIOS; the BIOS is used to perform a program self-check after self-starting, and send a self-check signal after the program self-check is completed. to complete the BIOS self-test phase;
  • the process of setting a fault monitoring strategy for the BIOS self-check stage includes:
  • the storage chip is also used to store the BIOS image file
  • the method for locating faults in the server startup process further includes:
  • the verification fails, it is determined that the BIOS image file in the storage chip is damaged, and the storage chip is rewritten according to the BIOS image file backed up by the system, and the system is restarted.
  • the BIOS is further configured to enter the running phase after the self-checking of its own program is completed, and send a power-on completion signal after the running is completed to complete the BIOS running phase;
  • the process of setting a fault monitoring strategy for the BIOS running stage includes:
  • BIOS fault register data If not, determine that the BIOS is running abnormally, and read the POST fault code and/or BIOS fault register data corresponding to the BIOS, so as to perform the BIOS operation according to the POST fault code and/or the BIOS fault register data fault location.
  • the BIOS is also used to start booting the OS after its own operation is completed;
  • the OS is used to send a start-up completion signal after the ipmitool driver installed by itself is loaded to complete the OS start-up phase;
  • the process of setting a fault monitoring strategy for the OS startup phase includes:
  • the server further includes an interface for modifying the preset time T4.
  • the BIOS is also used to start booting the OS after its own operation is completed;
  • the process of setting a fault monitoring strategy for the OS startup phase includes:
  • the present application also provides a fault location system during server startup, including:
  • the preset module is used to divide the entire startup process of the server into multiple stages in advance, and set a fault monitoring strategy for each stage accordingly;
  • a monitoring module configured to monitor the current startup process of the server according to the fault monitoring strategy corresponding to the target stage when the startup process of the server enters the target stage, and obtain the failure monitoring result corresponding to the target stage;
  • the target stage is any stage of the entire startup process of the server;
  • a locating module configured to locate the fault of the server according to the obtained fault monitoring result when the server fails to start.
  • the present application also provides a fault locating device during server startup, including:
  • the processor is configured to implement the steps of any of the above-mentioned methods for locating faults in a server startup process when the computer program is executed.
  • the present application provides a method for locating faults in a server startup process.
  • the entire server startup process is divided into multiple stages in advance, and a fault monitoring strategy is set for each stage accordingly; when the server startup process enters the target stage, The current startup process of the server is monitored according to the fault monitoring policy corresponding to the target stage, and the fault monitoring result corresponding to the target stage is obtained; when the server fails to start, the fault location of the server is performed according to the obtained fault monitoring result. It can be seen that the present application performs fault monitoring at each stage in the server startup process, which is helpful for fault location in the server startup process.
  • the present application also provides a system and device for locating faults during server startup, which have the same beneficial effects as the above-mentioned method for locating faults.
  • FIG. 1 is a flowchart of a method for locating faults in a server startup process according to an embodiment of the present application
  • FIG. 2 is a schematic structural diagram of a server according to an embodiment of the present application.
  • FIG. 3 is a division diagram of a complete startup process of a server according to an embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of a fault location system during server startup according to an embodiment of the present application.
  • the core of the present application is to provide a method, system and device for locating faults in a server startup process, which performs fault monitoring at each stage in the server startup process, which is helpful for fault location in the server startup process.
  • FIG. 1 is a flowchart of a method for locating a fault in a server startup process according to an embodiment of the present application.
  • the fault location method during the server startup process includes:
  • Step S1 The entire startup process of the server is divided into a plurality of stages in advance, and a fault monitoring strategy is correspondingly set for each stage.
  • the present application divides the entire startup process of the server into multiple stages in advance, and correspondingly sets a fault monitoring strategy for each stage of the entire startup process of the server, so as to perform fault monitoring on the entire startup process of the server subsequently.
  • Step S2 When the startup process of the server enters the target stage, monitor the current startup process of the server according to the fault monitoring policy corresponding to the target stage, and obtain the fault monitoring result corresponding to the target stage.
  • target stage of the present application is any stage divided into the entire startup process of the server.
  • the present application needs to monitor the current startup process of the server according to the fault monitoring policy corresponding to the target stage, so as to obtain the fault monitoring result corresponding to the target stage, so as to locate the fault of the server subsequently.
  • Step S3 When the server fails to start, perform fault location of the server according to the obtained fault monitoring result.
  • the present application can locate the fault of the server according to the fault monitoring result obtained in step S2, so as to clarify the stage, location and cause of the fault. Since the present application performs fault monitoring at each stage in the server startup process, the server has a better fault location effect.
  • the present application provides a method for locating faults in a server startup process.
  • the entire server startup process is divided into multiple stages in advance, and a fault monitoring strategy is set for each stage accordingly; when the server startup process enters the target stage, The current startup process of the server is monitored according to the fault monitoring policy corresponding to the target stage, and the fault monitoring result corresponding to the target stage is obtained; when the server fails to start, the fault location of the server is performed according to the obtained fault monitoring result. It can be seen that the present application performs fault monitoring at each stage in the server startup process, which is helpful for fault location in the server startup process.
  • FIG. 2 is a schematic structural diagram of a server provided by an embodiment of the present application
  • FIG. 3 is a division diagram of a complete startup process of a server provided by an embodiment of the present application.
  • the entire startup process of the server is divided into multiple stages, including:
  • the entire startup process of the server is divided into a power-on mode entry stage, a hardware power-on stage, a BIOS self-check stage, a BIOS running stage, and an OS startup stage.
  • this application can divide the entire startup process of the server into a power-on mode entry stage, a hardware power-on stage, a BIOS (Basic Input Output System, Basic Input Output System) self-check stage, a BIOS running stage, and an OS (Operating System, Operating system) startup stage, or the application may also divide the entire startup process of the server according to other division forms, which is not specifically limited in this application, and depends on the actual situation.
  • BIOS Basic Input Output System
  • BIOS Basic Input Output System
  • OS Operating System
  • the server includes a CPLD for receiving the button signal of the power button and transparently transmitting the button signal to the ME unit; and also includes a CPLD for returning the power-on start signal to the CPLD after receiving the button signal To complete the ME unit entering the power-up mode;
  • the process of setting the fault monitoring strategy for the power-on mode entry stage includes:
  • the power-on mode of the server enters the stage: when the power button (power button) of the server is pressed or the server receives a remotely sent power-on command, the signal level of the power button changes, and the button signal of the power button is
  • the CPLD Compact Programmable Logic Device
  • the ME Management Engine
  • the ME unit After receiving the key signal, the ME unit returns the power-on start signal to the CPLD to complete the power-on mode entry stage, and then enters the hardware power-on stage.
  • Start timing when receiving the key signal and judge whether the ME unit sends a power-on start signal when the timing time reaches the preset time T0 (such as 5s); if the ME unit sends a power-on start signal within the specified time T0, it is determined that the ME unit The operation is normal; if the ME unit does not send a power-on start signal within the specified time T0, it is preliminarily determined that the ME unit fails to operate, and then the status of the ME unit is read again. If the ME unit cannot be connected or the state is abnormal, it can be directly judged as the ME unit Unit failure, so as to make it clear that the failure cause of the abnormal system startup is the ME unit failure, and the log can be recorded and reported to the operation and maintenance system.
  • T0 such as 5s
  • the server further includes a memory chip connected to the ME unit through the channel switching device and used for storing the ME image file;
  • the method for locating faults during server startup also includes:
  • the server of the present application also includes a memory chip (such as a Flash chip), the memory chip is connected to the ME unit through a channel switching device (such as a switch), and the channel switching device connects the ME unit and the memory chip by default, and the memory chip stores the ME unit.
  • the reason for the failure of the ME unit may be that the memory chip is abnormal, the surrounding circuit of the memory chip is abnormal, the memory chip is missing the ME image file, the ME image file in the memory chip is damaged, the ME unit itself is faulty, etc., so that the power-on start signal cannot be given. As a result, the system cannot enter the power-on mode.
  • the reason for the failure of the ME unit to operate is analyzed as follows: first read the operating status of the ME unit, if the operating status of the ME unit can be read, it means that the ME unit has no abnormality in external communication, and the abnormality of the memory chip and the storage can be ruled out. If the surrounding circuit of the chip is abnormal and the memory chip is missing the ME image file, if the read operating state of the ME unit is abnormal, it is determined that the ME unit is operating abnormally; if the operating state of the ME unit cannot be read, then There may be abnormal memory chips, abnormal circuits around the memory chips, missing ME image files in the memory chips, damage to the ME image files in the memory chips, or the ME unit hangs.
  • the further analysis is as follows: 1) Read the power supply of the memory chips first. Check whether the voltage is normal. If the power supply voltage is normal, it is determined that the surrounding circuit of the memory chip is normal; if the power supply voltage is abnormal, it is determined that the surrounding circuit of the memory chip is abnormal, and it is determined that the server motherboard is faulty. 2) If the power supply voltage is normal, establish communication with the memory chip through the control channel switching device to access the memory chip. If the access is normal, it is determined that the memory chip is normal; Report the alarm and explicitly replace the motherboard. 3) If the memory chip is normal, judge whether the ME image file in the memory chip can be read. If the ME image file in the memory chip cannot be read, record the reason for the abnormal booting this time that the memory chip lacks the ME image file.
  • the comparison passes, and it is determined that the ME image file in the storage chip is not damaged; if the verification values are inconsistent, the comparison fails, and it is determined that the ME image file in the storage chip is damaged, record the relevant logs, and use the ME image backed up by the system. Rewrite the file to the memory chip, and restart the system to see if it can start normally. If it can start normally, it is just to verify that the reason for the abnormality of the last boot is that the ME image file in the memory chip is damaged. 5) If the system is still abnormal after restarting, it is determined that the ME unit itself is faulty, and an alarm is reported to replace the relevant components of the ME unit/or replace the main board.
  • the power supply system of the server includes a PSU and a plurality of VR power supply chips connected to the PSU and used for correspondingly supplying power to each component of the server;
  • the CPLD is also used to send the main power enable signal to the PSU after receiving the power-on start signal, and send the chip enable signal to multiple VR power supply chips in turn after receiving the PG signal returned by the PSU, and after receiving all VR power supply chips.
  • the power supply is normal signal to complete the hardware power-on stage;
  • CPLD is also used to record the abnormal situation to its own state when the PSU or any VR power supply chip fails to return the PG signal on time after the version update. register, and control the power-on VR power supply chip and PSU in turn to power off;
  • the process of setting the fault monitoring strategy for the hardware power-on phase includes:
  • the power supply normal signal is not sent, it is determined that the mainboard hardware of the server is powered on abnormally, and according to the version number of the CPLD, it is judged whether the CPLD has the abnormal recording function;
  • If it does not have the abnormal recording function read the status registers of the PSU and VR power supply chips to locate the abnormal situation of the PSU or VR power supply chip, and when the VR power supply chip has abnormal conditions, analyze the register state of the abnormal VR power supply chip according to the abnormal situation. The fault reason of the abnormal VR power supply chip.
  • the hardware power-on stage of the server after receiving the power-on start signal sent by the ME unit, the CPLD first sends the main power enable (Enable, En for short) signal to the PSU (Power supply unit, power supply unit), and then Wait for the PG (Power Good) signal returned by the PSU. If the PSU is powered on normally, the PG signal will be returned to the CPLD. If an abnormality occurs during the PSU power-on process, the PG signal will not be returned to the CPLD.
  • the main power enable Enable, En for short
  • PSU Power supply unit, power supply unit
  • PG Power Good
  • the CPLD After the PSU is powered on normally, the CPLD starts the power-on action of the next power supply, that is, sends the chip enable signal to multiple VR (Voltage Regulated, voltage regulation) power supply chips in turn, so that each VR power supply chip adjusts the output voltage of the PSU after adjusting the output voltage of the PSU. Correspondingly, it provides power to the CPU (central processing unit), memory, hard disk and other components of the system, and then waits for the PG signal returned by each VR power supply chip. If the VR power supply chip is powered on normally, it returns the PG signal to the CPLD. If an abnormality occurs during the power-up process, the PG signal will not be returned to the CPLD. After receiving the PG signals returned by all VR power supply chips, the CPLD sends out a power normal signal (Power OK signal) to complete the hardware power-on stage, and then enters the BIOS self-check stage.
  • Power OK signal power normal signal
  • the old version of CPLD does not have the abnormal recording function
  • the new version of the CPLD has the abnormal recording function: when the PSU or any VR power supply chip fails to return the PG signal on time, the abnormal situation is correspondingly recorded in its own status register. At this time, the CPLD can control the powered-on VR power supply chip and the PSU in turn to perform the power-off operation, which means that the system cannot be powered on.
  • the present application starts timing when the ME unit sends a power-on start signal, and determines whether the CPLD sends a power supply normal signal when the timing time reaches a preset time T1 (eg 10s); The hardware is powered on normally; if the power is normal signal is not sent, it is determined that the hardware of the mainboard of the server is powered on abnormally.
  • T1 preset time
  • the present application judges whether the CPLD has the abnormal recording function according to the version number of the CPLD; if the CPLD has the abnormal recording function, the status register of the CPLD is read to locate The abnormal situation of the PSU or VR power supply chip, that is, it is determined whether the PSU has a power-on abnormality, or which VR power supply chip has a power-on abnormality, and when the VR power supply chip has an abnormal situation, the I2C (Inter-Integrated Circuit) Synchronous serial bus) to read the status register of the abnormal VR power supply chip to analyze the fault cause of the abnormal VR power supply chip according to the register state of the abnormal VR power supply chip; if the CPLD does not have the abnormal recording function, directly read the PSU and The status register of the VR power supply chip is used to locate the abnormal condition of the PSU or VR power supply chip, and when the VR power supply chip is abnormal, analyze the fault cause of the abnormal VR power supply chip
  • the process of analyzing the fault cause of the abnormal VR power supply chip according to the register state of the abnormal VR power supply chip includes:
  • the abnormal VR power supply chip If it is determined that the abnormal VR power supply chip has input undervoltage according to the register state of the abnormal VR power supply chip, query whether the voltage of the previous VR power supply chip of the abnormal VR power supply chip is normal. The link between the upper-level VR power supply chips is faulty;
  • next-level circuit is a VR power supply chip
  • next-level circuit is a direct component and the direct component cannot be accessed, it is determined that the direct component needs to be replaced, and the location or number of the direct component is recorded.
  • the present application can obtain the specific abnormal conditions of the chip according to the register state of the abnormal VR power supply chip, such as OCP (overcurrent protection), OVP (overvoltage protection), Phase Fault (short circuit fault), input undervoltage and other abnormal conditions .
  • OCP overcurrent protection
  • OVP overvoltage protection
  • Phase Fault short circuit fault
  • the abnormal VR power supply chip has OCP, and the next-level circuit of the abnormal VR power supply chip is the VR power supply chip, check whether the next-level VR power supply chip can be accessed normally or whether the working state is abnormal. If it cannot be accessed normally or there is a short circuit In this case, it is determined that the motherboard needs to be replaced. At this time, relevant logs can be recorded and the fault point and cause of the fault can be reported to clarify the fault of the motherboard.
  • the abnormal VR power supply chip has OCP, and the next-level circuit of the abnormal VR power supply chip is a direct component (such as a memory stick), and the direct component cannot be accessed, it is determined that the direct component needs to be replaced, and relevant logs can be recorded at this time. And report the point of failure and the cause of the failure, and clarify the location or number of the replacement parts. For other situations that cannot be directly identified, you can also record relevant logs and report the fault point and cause for the reference of operation and maintenance personnel.
  • a direct component such as a memory stick
  • the CPU of the server is used to start working after the CPLD sends out a power supply normal signal, and start the BIOS; the BIOS is used to perform a program self-check after the self-starting, and send a self-check signal after the program self-check is completed. to complete the BIOS self-test phase;
  • the process of setting a fault monitoring strategy for the BIOS self-check phase includes:
  • the BIOS self-checking stage of the server the CPU of the server releases the reset (reset) signal after the CPLD sends out the power supply normal signal and starts to work, and the BIOS starts.
  • the BIOS performs a program self-check after the self-starting, and sends out a self-check signal (Selftest signal) after the program self-check is completed, so as to complete the BIOS self-check stage, and then enter the BIOS running stage.
  • Selftest signal self-check signal
  • the present application starts timing when the CPLD sends a power supply normal signal, and determines whether the BIOS sends a self-check signal when the timing time reaches a preset time T2 (such as 20s); if the BIOS sends a self-check signal on time, the program of the BIOS is determined. Complete and credible; if the BIOS does not send a self-check signal on time, it is determined that there is a problem with the BIOS program and the system cannot start normally. At this time, the BIOS program needs to be reprogrammed, that is, the motherboard needs to be replaced.
  • T2 such as 20s
  • the storage chip is also used to store the BIOS image file
  • the method for locating faults during server startup also includes:
  • the storage chip is rewritten according to the BIOS image file backed up by the system, and the system is restarted.
  • BIOS image file is also stored in the memory chip of the present application.
  • BIOS program problems may be caused by missing BIOS image file, damaged BIOS image file, or abnormal hang of BIOS program.
  • the BIOS image file needs to be re-programmed to quickly restore system operation and reduce time and cost waste caused by customers replacing motherboards. .
  • the analysis of the causes of the problems in the BIOS program is as follows: 1) First read the POST (self-test) code data of the historical BIOS, if the POST code data of the historical BIOS is read, then determine the BIOS program according to the POST code data Self-check the cause of the fault, such as CPU fault, memory fault, etc., and perform related fault location and report an alarm.
  • the POST code data of the historical BIOS cannot be read, it means that there is an abnormality in the initial stage of the program, which may be related to the hardware. 2) If the POST code data of the historical BIOS cannot be read, judge whether the power supply circuit related to the program self-check of the BIOS is abnormal in power supply, such as the power supply status of the CPU and other components. component problems and report the cause of the failure. 3) If there is no power supply abnormality, establish communication with the memory chip through the control channel switching device to determine whether the BIOS image file in the memory chip can be read; if the BIOS image file in the memory chip cannot be read, determine the storage chip. The chip is missing the BIOS image file, and judges whether there is a backup BIOS image file in the system database.
  • BIOS image file in the system database If there is a backup BIOS image file in the system database, it will directly write it to the memory chip, record the refresh log, and restart the system. If the system can pass the BIOS self-check stage after restarting, verify that the cause of the failure is that the memory chip is missing the BIOS image file, and record the relevant logs. If there is no backup BIOS image file in the system database, report an alarm to the operation and maintenance system, and arrange for the operation and maintenance personnel to burn the BIOS image file. 4) If the BIOS image file in the memory chip can be read, perform data verification on the BIOS image file in the memory chip, calculate the relevant check value, and compare it with the check value of the BIOS image file backed up by the system.
  • the comparison passes, and it is determined that the BIOS image file in the storage chip is not damaged; if the check values are inconsistent, the comparison fails, and it is determined that the BIOS image file in the storage chip is damaged, records the relevant logs, and automatically takes a re-flash backup.
  • the BIOS image file is transferred to the storage chip to automatically restore the image, record the log and restart the system. If the system can pass the BIOS self-check stage after restarting, it is just to verify that the cause of the failure is that the BIOS image file in the storage chip is damaged. 5) If the system still fails to pass the BIOS self-check stage after restarting, report the fault to update the latest BIOS image file or replace the motherboard.
  • BIOS image file in the memory chip If the BIOS image file in the memory chip is not damaged, record the mark to restart and retry the operation. If the restart is normal, clear the recorded mark. If the machine cannot be turned on after several restarts, notify manual failure analysis. Replace the mainboard/CPU/memory of the system to perform minimal recovery, record and report related alarms.
  • the BIOS is further configured to enter the running phase after the self-check of its own program is completed, and send a power-on completion signal after the running is completed to complete the BIOS running phase;
  • the process of setting a fault monitoring strategy for the BIOS running phase includes:
  • BIOS fault code and/or BIOS fault register data corresponding to the BIOS is read, so as to locate the BIOS fault according to the POST fault code and/or the BIOS fault register data.
  • the BIOS running stage of the server the BIOS enters the running stage after the self-check of its own program is completed, and sends a boot completion signal (BOOT COMPLETE signal) after the running is completed to complete the BIOS running stage, and then enters the OS startup stage.
  • a boot completion signal BOOT COMPLETE signal
  • the BIOS initializes the system during the running phase, and there are exceptions and hangs for various reasons, which in turn lead to startup failure, and the startup completion signal will not be issued at this time.
  • the self-check signal sent by the BIOS is actually the first signal sent by the BIOS after completing the initialization of the direct communication link with the BMC (Baseboard Management Controller) in the server, representing the BIOS and the BMC.
  • BMC Baseboard Management Controller
  • BIOS initializes peripherals
  • BIOS can change the related peripherals and status.
  • BIOS fault register data saved by the BMC can be used for more accurate fault location.
  • the present application starts timing when the BIOS sends a self-check signal, and determines whether the BIOS sends a boot completion signal when the timing time reaches a preset time T3 (such as 300s); if the BIOS sends a boot completion signal on time, it is determined that the BIOS is running normally ; If the BIOS does not send the boot completion signal on time, it is determined that the BIOS is running abnormally, and then the POST fault code and/or BIOS fault register data corresponding to the BIOS is read to locate the fault stage of the BIOS according to the POST fault code and/or the BIOS fault register data. and the cause of the fault, report the alarm after locating it, and replace the relevant parts during operation and maintenance.
  • T3 such as 300s
  • the present application can subdivide the BIOS operation stage, including the SEC (Security Verification) stage, the PEI (EFI Pre-Initialization) stage, the DXE (Driver Execution Environment) stage, the BDS (Boot Device Selection) stage, and the TSL stage. Judgments are made according to the conditions of each stage of the BIOS operation.
  • SEC Security Verification
  • PEI EFI Pre-Initialization
  • DXE Driver Execution Environment
  • BDS Battery Selection
  • Timing if the corresponding completion signal is received within the timing of the corresponding stage, it is determined that this stage is running normally, otherwise it is determined that this stage is running abnormally, so as to more detailed and accurate judgment of the fault location, and to speed up the judgment of the fault (without waiting for the timeout of T3 , some devices may actually start for more than ten minutes). It should be noted that the timing time of the above-mentioned phases can be configured according to the actual configuration of the device.
  • this application can record the relevant signs to restart the device. If the equipment returns to normal after restarting, or the specific cause is located, the signs will be eliminated; The alarm is reported to the operation and maintenance system, and the operation and maintenance system is notified to check and replace the CPU/memory and other components in turn to minimize fault location.
  • the BIOS is also used to start booting the OS after its own operation is completed; the OS is used to send a startup completion signal after the ipmitool driver installed by itself is loaded to complete the OS startup phase;
  • the process of setting a fault monitoring strategy for the OS startup phase includes:
  • the BIOS starts to boot the OS after its own operation is completed, and the OS startup abnormality belongs to the category of the operating system.
  • the present application cannot actively detect and track the state of the OS.
  • the method is that the OS sends a startup completion signal (startup OK signal) after the driver of the installed ipmitool (a command-line ipmi platform management tool that can be used in the Linux system) is loaded, so as to judge the OS startup completion according to the startup completion signal. , the entire startup process of the server is over.
  • the present application starts timing when the BIOS sends a boot completion signal, and determines whether the OS sends a signal when the timing time reaches the preset time T4 (T4 is reasonably set based on the system function configuration).
  • Startup completion signal if the OS issues a startup completion signal on time, it is determined that the OS startup is successful; if the OS fails to issue a startup completion signal on time, it is determined that the OS startup is abnormal, records the relevant logs, and reports the OS startup exception, requesting to check the OS startup exception record.
  • the server further includes an interface for modifying the preset time T4.
  • the server design of the present application can modify the interface of the preset time T4, so that the interface can be modified according to the The actual configuration of the system defines the size of T4.
  • BIOS is further configured to start booting the OS after its own operation is completed
  • the process of setting a fault monitoring strategy for the OS startup phase includes:
  • the second fault monitoring strategy in the OS startup phase after the OS is started, monitor the system log records transmitted by the system serial port, and determine whether the system log records have error information within the preset monitoring time; If an error message is recorded in the system log, it is determined that the OS is successfully started; if an error message is detected in the system log, it is determined that the OS startup is abnormal, and the fault is located according to the detected error message and historical system log records, and the abnormality of the OS is detected. Report the situation to the police, and the operation and maintenance personnel will deal with it.
  • the fault location method in the server startup process of the present application can all be implemented by the BMC of the server.
  • the BMC interacts with the PSU, CPLD, and ME units through the I2C bus; the BMC switches the control of the device through the channel.
  • the line control channel switching device switches the channel, so that the BMC interacts with the memory chip through the SPI (Serial Peripheral Interface, serial peripheral interface) bus.
  • SPI Serial Peripheral Interface, serial peripheral interface
  • FIG. 4 is a schematic structural diagram of a fault location system during server startup according to an embodiment of the present application.
  • the fault location system during the startup of the server includes:
  • the preset module 1 is used to divide the entire startup process of the server into multiple stages in advance, and set a fault monitoring strategy for each stage accordingly;
  • the monitoring module 2 is used to monitor the current startup process of the server according to the fault monitoring strategy corresponding to the target stage when the startup process of the server enters the target stage, and obtain the fault monitoring result corresponding to the target stage; wherein, the target stage is any stage;
  • the locating module 3 is used for locating the fault of the server according to the obtained fault monitoring result when the server fails to start.
  • the present application also provides a fault location device during server startup, including:
  • the processor is configured to implement the steps of any of the above-mentioned methods for locating faults in the server startup process when executing the computer program.

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Abstract

一种服务器启动过程中的故障定位方法、系统及装置，预先将服务器的整个启动过程划分为多个阶段，并相应为每个阶段设定故障监控策略（S1）；在服务器的启动过程进入目标阶段时，按照目标阶段对应的故障监控策略监控服务器当前的启动过程，得到目标阶段对应的故障监控结果(S2)；在服务器启动失败时，根据得到的故障监控结果进行服务器的故障定位(S3)。该方法对服务器启动过程中的各个阶段都进行了故障监控，有助于服务器启动过程的故障定位。

Description

一种服务器启动过程中的故障定位方法、系统及装置
本申请要求在2021年3月26日提交中国专利局、申请号为202110326285.8、发明名称为“一种服务器启动过程中的故障定位方法、系统及装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及服务器运维领域，特别是涉及一种服务器启动过程中的故障定位方法、系统及装置。
背景技术
随着数据中心的规模越来越大，千万台级别的服务器给运维工作带来巨大的挑战，智能运维被越来越多的提出。目前，服务器启动异常在每个数据中心都存在，由于服务器的整个启动过程包含的阶段较多，现有的服务器启动过程中的故障监控方案大都是局部阶段的故障监控，无法完整监控到服务器的整个启动过程，导致故障定位效果较差。
因此，如何提供一种解决上述技术问题的方案是本领域的技术人员目前需要解决的问题。
发明内容
本申请的目的是提供一种服务器启动过程中的故障定位方法、系统及装置，对服务器启动过程中的各个阶段都进行了故障监控，有助于服务器启动过程的故障定位。
为解决上述技术问题，本申请提供了一种服务器启动过程中的故障定位方法，包括：
预先将服务器的整个启动过程划分为多个阶段，并相应为每个阶段设定故障监控策略；
在所述服务器的启动过程进入目标阶段时，按照所述目标阶段对应的故障监控策略监控所述服务器当前的启动过程，得到所述目标阶段对应的故障监控结果；其中，所述目标阶段为服务器的整个启动过程划分的任一阶段；
在所述服务器启动失败时，根据得到的故障监控结果进行所述服务器的故障定位。
优选地，将服务器的整个启动过程划分为多个阶段的过程，包括：
将服务器的整个启动过程划分为上电模式进入阶段、硬件上电阶段、BIOS自检阶段、BIOS运行阶段及OS启动阶段。
优选地，所述服务器包括用于接收电源按键的按键信号，并将所述按键信号透传至ME单元的CPLD；还包括用于在接收到所述按键信号后，返回上电启动信号至CPLD以完成所述上电模式进入阶段的ME单元；
相应的，为所述上电模式进入阶段设定故障监控策略的过程，包括：
从所述CPLD接收到所述按键信号时开始计时，判断在计时时间到达预设时间T0时，所述ME单元是否发出上电启动信号；
若是，则确定所述ME单元运行正常；
若否，则确定所述ME单元运行失败。
优选地，所述服务器还包括通过通道切换器件与所述ME单元连接、用于存储ME镜像文件的存储芯片；
所述服务器启动过程中的故障定位方法还包括：
在确定所述ME单元运行失败后，判断是否可获取到所述ME单元的运行状态；
若可获取到，则在所述运行状态存在异常时确定所述ME单元存在运行异常的情况；
若不可获取到，则判断所述存储芯片的供电电压是否正常；
若供电电压异常，则确定所述存储芯片的周围电路异常；
若供电电压正常，则确定所述存储芯片的周围电路正常，并通过控制所述通道切换器件与所述存储芯片建立通信，判断是否可正常访问到所述存储芯片；
若不可正常访问到，则确定所述存储芯片异常；
若可正常访问到，则确定所述存储芯片正常，并判断是否可读取到所述存储芯片内的ME镜像文件；
若不可读取到，则确定所述存储芯片缺失所述ME镜像文件；
若可读取到，则对所述存储芯片内的ME镜像文件进行数据校验，若校验失败，则确定所述存储芯片内的ME镜像文件损坏，并根据系统备份的ME镜像文件重新刷写所述存储芯片，并重启系统；
若系统重启后依旧异常，则确定所述ME单元自身故障。
优选地，所述服务器的供电系统包括PSU及与所述PSU连接、用于对应为所述服务器的各部件供电的多个VR供电芯片；
且所述CPLD还用于在接收到上电启动信号后发送主电使能信号至所述PSU，并在接收到所述PSU返回的PG信号后依次发送芯片使能信号至多个VR供电芯片，且在接收到所有VR供电芯片返回的PG信号后发出电源正常信号以完成所述硬件上电阶段；所述CPLD在版本更新后还用于在所述PSU或任一VR供电芯片未按时返回PG信号时，相应记录此异常情况到自身的状态寄存器，并依次控制已上电的VR供电芯片及PSU进行下电操作；
相应的，为所述硬件上电阶段设定故障监控策略的过程，包括：
从所述ME单元发出上电启动信号时开始计时，判断在计时时间到达预设时间T1时，所述CPLD是否发出电源正常信号；
若发出电源正常信号，则确定所述服务器的主板硬件上电正常；
若未发出电源正常信号，则确定所述服务器的主板硬件上电异常，并根据所述CPLD的版本号判断所述CPLD是否具有异常记录功能；
若具有异常记录功能，则读取所述CPLD的状态寄存器，以定位所述PSU或VR供电芯片的异常情况，并在VR供电芯片有异常情况时，根据异常的VR供电芯片的寄存器状态分析异常的VR供电芯片的故障原因；
若不具有异常记录功能，则读取所述PSU和VR供电芯片的状态寄存器，以定位所述PSU或VR供电芯片的异常情况，并在VR供电芯片有异常情况时，根据异常的VR供电芯片的寄存器状态分析异常的VR供电芯片的故障原因。
优选地，根据异常的VR供电芯片的寄存器状态分析异常的VR供电芯片的故障原因的过程，包括：
若根据异常的VR供电芯片的寄存器状态确定异常的VR供电芯片存在短路故障，则确定异常的VR供电芯片的MOS管损坏；
若根据异常的VR供电芯片的寄存器状态确定异常的VR供电芯片存在输入欠压，则查询异常的VR供电芯片的上一级VR供电芯片的电压是否正常，若是，则确定异常的VR供电芯片和上一级VR供电芯片之间的链路存在故障；
若根据异常的VR供电芯片的寄存器状态确定异常的VR供电芯片存在OCP，则查询异常的VR供电芯片的下一级电路；
若下一级电路为VR供电芯片，则检测下一级VR供电芯片是否能够正常访问或者工作状态是否异常，若无法正常访问或者出现短路情况，则确定主板需要更换；
若下一级电路为直接部件，且该直接部件无法访问，则确定该直接部件需要更换，并对该直接部件的位置或编号进行记录。
优选地，所述服务器的CPU用于在所述CPLD发出电源正常信号后开始工作，启动BIOS；所述BIOS用于在自身启动后进行程序自检，并在程序自检完成后发出自检信号以完成所述BIOS自检阶段；
相应的，为所述BIOS自检阶段设定故障监控策略的过程，包括：
从所述CPLD发出电源正常信号时开始计时，判断在计时时间到达预设时间T2时，所述BIOS是否发出自检信号；
若是，则确定所述BIOS的程序完整可信；
若否，则确定所述BIOS的程序存在问题。
优选地，所述存储芯片还用于存储BIOS镜像文件；
所述服务器启动过程中的故障定位方法还包括：
在确定所述BIOS的程序存在问题后，判断是否可获取到BIOS的POST代码数据；
若可获取到，则根据所述POST代码数据确定所述BIOS的程序自检故障原因；
若不可获取到，则判断与所述BIOS的程序自检相关的供电电路是否供电异常；
若供电异常，则对所述供电电路的供电异常进行故障原因分析；
若供电正常，则通过控制所述通道切换器件与所述存储芯片建立通信，判断是否可读取到所述存储芯片内的BIOS镜像文件；
若不可读取到，则确定所述存储芯片缺失所述BIOS镜像文件；
若可读取到，则对所述存储芯片内的BIOS镜像文件进行数据校验，并判断是否校验成功；
若校验成功，则进行系统重启操作，并在重启多次都无法开机后通知人工进行故障分析；
若校验失败，则确定所述存储芯片内的BIOS镜像文件损坏，并根据系统备份的BIOS镜像文件重新刷写所述存储芯片，并重启系统。
优选地，所述BIOS还用于在自身程序自检完成后进入运行阶段，并在运行完成后发出开机完成信号以完成所述BIOS运行阶段；
相应的，为所述BIOS运行阶段设定故障监控策略的过程，包括：
从所述BIOS发出自检信号时开始计时，判断在计时时间到达预设时间T3时，所述BIOS是否发出开机完成信号；
若是，则确定所述BIOS运行正常；
若否，则确定所述BIOS运行异常，并读取所述BIOS对应的POST故障码和/或BIOS故障寄存器数据，以根据所述POST故障码和/或所述BIOS故障寄存器数据进行所述BIOS的故障定位。
优选地，所述BIOS还用于在自身运行完成后开始引导OS启动；所述OS用于在自身安装的ipmitool驱动加载完毕后发出启动完成信号以完成所述OS启动阶段；
相应的，为所述OS启动阶段设定故障监控策略的过程，包括：
从所述BIOS发出开机完成信号时开始计时，判断在计时时间到达预设时间T4时，所述OS是否发出启动完成信号；
若是，则确定所述OS启动成功；
若否，则确定所述OS启动异常。
优选地，所述服务器还包括用于修改预设时间T4的接口。
优选地，所述BIOS还用于在自身运行完成后开始引导OS启动；
相应的，为所述OS启动阶段设定故障监控策略的过程，包括：
在所述OS启动后，监听系统串口传输的系统日志记录，并判断在预设监听时间内是否监听到所述系统日志记录有错误信息；
若否，则确定所述OS启动成功；
若是，则确定所述OS启动异常，并根据所述错误信息及历史系统日志记录进行故障定位。
为解决上述技术问题，本申请还提供了一种服务器启动过程中的故障定位系统，包括：
预设模块，用于预先将服务器的整个启动过程划分为多个阶段，并相应为每个阶段设定故障监控策略；
监控模块，用于在所述服务器的启动过程进入目标阶段时，按照所述目标阶段对应的故障监控策略监控所述服务器当前的启动过程，得到所述目标阶段对应的故障监控结果；其中，所述目标阶段为服务器的整个启动过程划分的任一阶段；
定位模块，用于在所述服务器启动失败时，根据得到的故障监控结果进行所述服务器的故障定位。
为解决上述技术问题，本申请还提供了一种服务器启动过程中的故障定位装置，包括：
存储器，用于存储计算机程序；
处理器，用于在执行所述计算机程序时实现上述任一种服务器启动过程中的故障定位方法的步骤。
本申请提供了一种服务器启动过程中的故障定位方法，预先将服务器的整个启动过程划分为多个阶段，并相应为每个阶段设定故障监控策略；在服务器的启动过程进入目标阶段时，按照目标阶段对应的故障监控策略监控服务器当前的启动过程，得到目标阶段对应的故障监控结果；在服务器启动失败时，根据得到的故障监控结果进行服务器的故障定位。可见，本申请对服务器启动过程中的各个阶段都进行了故障监控，有助于服务器启动过程的故障定位。
本申请还提供了一种服务器启动过程中的故障定位系统及装置，与上述故障定位方法具有相同的有益效果。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对现有技术和实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例提供的一种服务器启动过程中的故障定位方法的流程图；
图2为本申请实施例提供的一种服务器的结构示意图；
图3为本申请实施例提供的一种服务器完整开机启动过程的划分图；
图4为本申请实施例提供的一种服务器启动过程中的故障定位系统的结构示意图。
具体实施方式
本申请的核心是提供一种服务器启动过程中的故障定位方法、系统及装置，对服务器启动过程中的各个阶段都进行了故障监控，有助于服务器启动过程的故障定位。
为使本申请实施例的目的、技术方案和优点更加清楚，下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
请参照图1，图1为本申请实施例提供的一种服务器启动过程中的故障定位方法的流程图。
该服务器启动过程中的故障定位方法包括：
步骤S1：预先将服务器的整个启动过程划分为多个阶段，并相应为每个阶段设定故障监控策略。
具体地，本申请提前将服务器的整个启动过程划分为多个阶段，并相应为服务器的整个启动过程划分的每个阶段设定故障监控策略，以为后续对服务器的整个启动过程进行故障监控。
步骤S2：在服务器的启动过程进入目标阶段时，按照目标阶段对应的故障监控策略监控服务器当前的启动过程，得到目标阶段对应的故障监控结果。
需要说明的是，本申请的目标阶段为服务器的整个启动过程划分的任一阶段。
具体地，本申请在服务器的启动过程进入目标阶段时，需按照目标阶段对应的故障监控策略监控服务器当前的启动过程，从而得到目标阶段对应的故障监控结果，以为后续进行服务器的故障定位。
步骤S3：在服务器启动失败时，根据得到的故障监控结果进行服务器的故障定位。
具体地，本申请在服务器启动失败时，可根据步骤S2得到的故障监控结果进行服务器的故障定位，从而明确出现故障阶段、位置及原因。由于本申请对服务器启动过程中的各个阶段都进行了故障监控，所以服务器的故障定位效果较好。
本申请提供了一种服务器启动过程中的故障定位方法，预先将服务器的整个启动过程划分为多个阶段，并相应为每个阶段设定故障监控策略；在服务器的启动过程进入目标阶段时，按照目标阶段对应的故障监控策略监控服务器当前的启动过程，得到目标阶段对应的故障监控结果；在服务器启动失败时，根据得到的故障监控结果进行服务器的故障定位。可见，本申请对服务器启动过程中的各个阶段都进行了故障监控，有助于服务器启动过程的故障定位。
在上述实施例的基础上：
请参照图2及图3，图2为本申请实施例提供的一种服务器的结构示意图；图3为本申请实施例提供的一种服务器完整开机启动过程的划分图。
作为一种可选的实施例，将服务器的整个启动过程划分为多个阶段的过程，包括：
将服务器的整个启动过程划分为上电模式进入阶段、硬件上电阶段、BIOS自检阶段、BIOS运行阶段及OS启动阶段。
具体地，本申请可将服务器的整个启动过程划分为上电模式进入阶段、硬件上电阶段、BIOS(Basic Input Output System，基本输入输出系统)自检阶段、BIOS运行阶段及OS(Operating System，操作系统)启动阶段，或者本申请也可将服务器的整个启动过程按照其它划分形式进行划分，本申请在此不做特别的限定，根据实际情况而定。
作为一种可选的实施例，服务器包括用于接收电源按键的按键信号，并将按键信号透传至ME单元的CPLD；还包括用于在接收到按键信号后，返回上电启动信号至CPLD以完成上电模式进入阶段的ME单元；
相应的，为上电模式进入阶段设定故障监控策略的过程，包括：
从CPLD接收到按键信号时开始计时，判断在计时时间到达预设时间T0时，ME单元是否发出上电启动信号；
若是，则确定ME单元运行正常；
若否，则确定ME单元运行失败。
具体地，服务器的上电模式进入阶段：当服务器的powerbutton(电源按键)被按下或者服务器接收到远程发送的开机指令时，电源按键的信号电平发生变化，此时电源按键的按键信号被送到服务器的CPLD(Complex Programmable Logic Device，复杂可编程逻辑器件)，然后被透传到服务器的ME(Management Engine，管理引擎)单元。ME单元在接收到按键信号后，返回上电启动信号至CPLD，以完成上电模式进入阶段，而后进入硬件上电阶段。
基于此，考虑到若ME单元(Management Engine，管理引擎)异常，则ME单元不会发出上电启动信号，对应现象就是系统无法进入后续硬件上电阶段，系统不会开机，所以本申请从CPLD接收到按键信号时开始计时，判断在计时时间到达预设时间T0(如5s)时，ME单元是否发出上电启动信号；若ME单元在规定时间T0内发出上电启动信号，则确定ME单元运行正常；若ME单元在规定时间T0内未发出上电启动信号，则初步判定ME单元运行失败，然后再次读取ME单元的状态，若ME单元无法连接或者状态异常，则可 直接判断为ME单元故障，从而明确系统启动异常的故障原因为ME单元故障，可记录日志并上报运维系统。
作为一种可选的实施例，服务器还包括通过通道切换器件与ME单元连接、用于存储ME镜像文件的存储芯片；
服务器启动过程中的故障定位方法还包括：
在确定ME单元运行失败后，判断是否可获取到ME单元的运行状态；
若可获取到，则在运行状态存在异常时确定ME单元存在运行异常的情况；
若不可获取到，则判断存储芯片的供电电压是否正常；
若供电电压异常，则确定存储芯片的周围电路异常；
若供电电压正常，则确定存储芯片的周围电路正常，并通过控制通道切换器件与存储芯片建立通信，判断是否可正常访问到存储芯片；
若不可正常访问到，则确定存储芯片异常；
若可正常访问到，则确定存储芯片正常，并判断是否可读取到存储芯片内的ME镜像文件；
若不可读取到，则确定存储芯片缺失ME镜像文件；
若可读取到，则对存储芯片内的ME镜像文件进行数据校验，若校验失败，则确定存储芯片内的ME镜像文件损坏，并根据系统备份的ME镜像文件重新刷写存储芯片，并重启系统；
若系统重启后依旧异常，则确定ME单元自身故障。
进一步地，本申请的服务器还包括存储芯片(如Flash芯片)，存储芯片通过通道切换器件(如切换开关)与ME单元连接，通道切换器件默认连通ME单元与存储芯片，存储芯片中存储有ME镜像文件，供ME单元读取运行。ME单元运行失败的原因可能是存储芯片异常、存储芯片的周围电路异常、存储芯片缺失ME镜像文件、存储芯片内ME镜像文件损坏、ME单元自身故障等情况，导致无法给出上电启动信号，进而系统无法进入上电模式。基于此，对ME单元运行失败的原因分析为：先读取ME单元的运行状态，若能够读取到ME单元的运行状态，说明ME单元与外部通信无异常，则可排除存储芯片异常、存储芯片的周围电路异常和存储芯片缺失ME镜像文件的情况，若读取 到的ME单元的运行状态存在异常，则确定ME单元存在运行异常的情况；若无法读取到ME单元的运行状态，则可能存在存储芯片异常、存储芯片的周围电路异常、存储芯片缺失ME镜像文件、存储芯片内ME镜像文件损坏或ME单元挂死的情况，对此进一步分析为：1)先读取存储芯片的供电电压是否正常，如果供电电压正常，则确定存储芯片的周围电路正常；如果供电电压异常，则确定存储芯片的周围电路异常，判定为服务器主板故障，上报告警并明确更换主板。2)如果供电电压正常，则通过控制通道切换器件与存储芯片建立通信，以访问存储芯片，如果访问正常，则确定存储芯片正常，如果无法访问，则确定存储芯片异常，判定为主板故障，上报告警并明确更换主板。3)如果存储芯片正常，判断是否可读取到存储芯片内的ME镜像文件，如果读取不到存储芯片内的ME镜像文件，则记录本次开机异常的原因为存储芯片缺失ME镜像文件，并判定系统数据库中是否有ME镜像文件，如果数据库中有ME镜像文件，则将ME镜像文件写入存储芯片中，并在写入成功后重启系统；如果数据库中没有ME镜像文件，则上报告警需要运维重新刷新存储芯片。4)如果读取到存储芯片内的ME镜像文件，则对其内ME镜像文件进行数据校验，计算相关的校验值，并与系统备份的ME镜像文件的校验值进行对比，如果校验值一致则对比通过，判定为存储芯片内的ME镜像文件未损坏；如果校验值不一致则对比失败，判定为存储芯片内的ME镜像文件损坏，记录相关日志，并根据系统备份的ME镜像文件重新刷写存储芯片，并重启系统看是否能正常启动，如果能正常启动，则正好验证上次开机异常的原因为存储芯片内的ME镜像文件损坏。5)如果系统重启后依旧异常，则判定为ME单元自身故障，并上报告警，更换ME单元的相关部件/或更换主板。
需要说明的是，上述操作的顺序可独立进行或者打乱顺序都在本申请保护范围内。
作为一种可选的实施例，服务器的供电系统包括PSU及与PSU连接、用于对应为服务器的各部件供电的多个VR供电芯片；
且CPLD还用于在接收到上电启动信号后发送主电使能信号至PSU，并在接收到PSU返回的PG信号后依次发送芯片使能信号至多个VR供电芯片，且在接收到所有VR供电芯片返回的PG信号后发出电源正常信号以完成硬件 上电阶段；CPLD在版本更新后还用于在PSU或任一VR供电芯片未按时返回PG信号时，相应记录此异常情况到自身的状态寄存器，并依次控制已上电的VR供电芯片及PSU进行下电操作；
相应的，为硬件上电阶段设定故障监控策略的过程，包括：
从ME单元发出上电启动信号时开始计时，判断在计时时间到达预设时间T1时，CPLD是否发出电源正常信号；
若发出电源正常信号，则确定服务器的主板硬件上电正常；
若未发出电源正常信号，则确定服务器的主板硬件上电异常，并根据CPLD的版本号判断CPLD是否具有异常记录功能；
若具有异常记录功能，则读取CPLD的状态寄存器，以定位PSU或VR供电芯片的异常情况，并在VR供电芯片有异常情况时，根据异常的VR供电芯片的寄存器状态分析异常的VR供电芯片的故障原因；
若不具有异常记录功能，则读取PSU和VR供电芯片的状态寄存器，以定位PSU或VR供电芯片的异常情况，并在VR供电芯片有异常情况时，根据异常的VR供电芯片的寄存器状态分析异常的VR供电芯片的故障原因。
具体地，服务器的硬件上电阶段：CPLD在接收到ME单元发送的上电启动信号后，先给PSU(Power supply unit，电源供应单元)发送主电使能(Enable，简称En)信号，然后等待PSU返回的PG(Power Good，电源正常)信号，如果PSU上电正常，则返回PG信号至CPLD，如果PSU上电过程中出现异常，则不返回PG信号至CPLD。PSU上电正常后，CPLD开启下一路电的上电动作，即依次发送芯片使能信号至多个VR(Voltage Regulated，电压调节)供电芯片，以使各VR供电芯片将PSU的输出电压进行调整后相应为系统的CPU(中央处理器)、内存、硬盘等部件提供电能，然后等待各VR供电芯片返回的PG信号，如果VR供电芯片上电正常，则返回PG信号至CPLD，如果VR供电芯片上电过程中出现异常，则不返回PG信号至CPLD。CPLD在接收到所有VR供电芯片返回的PG信号后发出电源正常信号(Power OK信号)，以完成硬件上电阶段，而后进入BIOS自检阶段。
需要说明的是，旧版本的CPLD不具有异常记录功能，新版本的CPLD具有异常记录功能：在PSU或任一VR供电芯片未按时返回PG信号时，相应 记录此异常情况到自身的状态寄存器，此时CPLD可依次控制已上电的VR供电芯片及PSU进行下电操作，表现为系统无法上电开机。
基于此，本申请从ME单元发出上电启动信号时开始计时，判断在计时时间到达预设时间T1(如10s)时，CPLD是否发出电源正常信号；若发出电源正常信号，则确定服务器的主板硬件上电正常；若未发出电源正常信号，则确定服务器的主板硬件上电异常。
为了进一步定位异常点，本申请在确定服务器的主板硬件上电异常后，还根据CPLD的版本号判断CPLD是否具有异常记录功能；若CPLD具有异常记录功能，则读取CPLD的状态寄存器，以定位PSU或VR供电芯片的异常情况，即确定是PSU存在上电异常，还是哪个VR供电芯片存在上电异常，并在VR供电芯片有异常情况时，可通过I2C(Inter-Integrated Circuit，双向二线制同步串行总线)读取异常的VR供电芯片的状态寄存器，以根据异常的VR供电芯片的寄存器状态分析异常的VR供电芯片的故障原因；若CPLD不具有异常记录功能，则直接读取PSU和VR供电芯片的状态寄存器，以定位PSU或VR供电芯片的异常情况，并在VR供电芯片有异常情况时，再根据异常的VR供电芯片的寄存器状态分析异常的VR供电芯片的故障原因。此外，本申请如果定位到PSU上电异常，还可根据PSU的寄存器状态明确系统是否需要更换PSU。
作为一种可选的实施例，根据异常的VR供电芯片的寄存器状态分析异常的VR供电芯片的故障原因的过程，包括：
若根据异常的VR供电芯片的寄存器状态确定异常的VR供电芯片存在短路故障，则确定异常的VR供电芯片的MOS管损坏；
若根据异常的VR供电芯片的寄存器状态确定异常的VR供电芯片存在输入欠压，则查询异常的VR供电芯片的上一级VR供电芯片的电压是否正常，若是，则确定异常的VR供电芯片和上一级VR供电芯片之间的链路存在故障；
若根据异常的VR供电芯片的寄存器状态确定异常的VR供电芯片存在OCP，则查询异常的VR供电芯片的下一级电路；
若下一级电路为VR供电芯片，则检测下一级VR供电芯片是否能够正常访问或者工作状态是否异常，若无法正常访问或者出现短路情况，则确定主板需要更换；
若下一级电路为直接部件，且该直接部件无法访问，则确定该直接部件需要更换，并对该直接部件的位置或编号进行记录。
具体地，本申请根据异常的VR供电芯片的寄存器状态可得到芯片的具体异常情况，如OCP(过流保护)、OVP(过压保护)、Phase Fault(短路故障)、输入欠压等异常情况。如果异常的VR供电芯片存在短路故障，则认为是异常的VR供电芯片的MOS管损坏，需要更换主板，此时可记录相关日志并上报故障点和故障原因，明确主板故障。如果异常的VR供电芯片存在输入欠压，则查询异常的VR供电芯片的上一级VR供电芯片的电压是否正常，如果电压正常，则认为异常的VR供电芯片和上一级VR供电芯片之间的链路存在故障，需要更换主板，此时可记录相关日志并上报故障点和故障原因，明确主板故障。如果异常的VR供电芯片存在OCP，且异常的VR供电芯片的下一级电路为VR供电芯片，则检测下一级VR供电芯片是否能够正常访问或者工作状态是否异常，若无法正常访问或者出现短路情况，则确定主板需要更换，此时可记录相关日志并上报故障点和故障原因，明确主板故障。如果异常的VR供电芯片存在OCP，且异常的VR供电芯片的下一级电路为直接部件(如内存条)，且该直接部件无法访问，则确定该直接部件需要更换，此时可记录相关日志并上报故障点和故障原因，明确更换部件的位置或编号。其余无法直接明确的情况，也可记录相关日志并上报故障点和故障原因，供运维人员参考。
需要说明的是，上述操作的顺序可独立进行或者打乱顺序都在本申请保护范围内。
作为一种可选的实施例，服务器的CPU用于在CPLD发出电源正常信号后开始工作，启动BIOS；BIOS用于在自身启动后进行程序自检，并在程序自检完成后发出自检信号以完成BIOS自检阶段；
相应的，为BIOS自检阶段设定故障监控策略的过程，包括：
从CPLD发出电源正常信号时开始计时，判断在计时时间到达预设时间T2时，BIOS是否发出自检信号；
若是，则确定BIOS的程序完整可信；
若否，则确定BIOS的程序存在问题。
具体地，服务器的BIOS自检阶段：服务器的CPU在CPLD发出电源正常信号后释放reset(重置)信号开始工作，BIOS启动。BIOS在自身启动后进行程序自检，并在程序自检完成后发出自检信号(Selftest信号)，以完成BIOS自检阶段，而后进入BIOS运行阶段。需要说明的是，当BIOS程序缺失或者损坏时，BIOS程序自检不通过，不会发出自检信号，系统无法正常启动。
基于此，本申请从CPLD发出电源正常信号时开始计时，判断在计时时间到达预设时间T2(如20s)时，BIOS是否发出自检信号；若BIOS按时发出自检信号，则确定BIOS的程序完整可信；若BIOS未按时发出自检信号，则确定BIOS的程序存在问题，系统无法正常启动，此时需要重新烧写BIOS程序，即需要更换主板。
作为一种可选的实施例，存储芯片还用于存储BIOS镜像文件；
服务器启动过程中的故障定位方法还包括：
在确定BIOS的程序存在问题后，判断是否可获取到BIOS的POST代码数据；
若可获取到，则根据POST代码数据确定BIOS的程序自检故障原因；
若不可获取到，则判断与BIOS的程序自检相关的供电电路是否供电异常；
若供电异常，则对供电电路的供电异常进行故障原因分析；
若供电正常，则通过控制通道切换器件与存储芯片建立通信，判断是否可读取到存储芯片内的BIOS镜像文件；
若不可读取到，则确定存储芯片缺失BIOS镜像文件；
若可读取到，则对存储芯片内的BIOS镜像文件进行数据校验，并判断是否校验成功；
若校验成功，则进行系统重启操作，并在重启多次都无法开机后通知人工进行故障分析；
若校验失败，则确定存储芯片内的BIOS镜像文件损坏，并根据系统备份的BIOS镜像文件重新刷写存储芯片，并重启系统。
进一步地，本申请的存储芯片内还存储有BIOS镜像文件。BIOS的程序存在问题的原因可能是BIOS镜像文件缺失、BIOS镜像文件损坏、BIOS程序异常挂死，一般需要重新烧写BIOS镜像文件，快速恢复系统运行，减少客户更换主板造成的时间浪费和成本浪费。基于此，对BIOS的程序存在问题的原因分析为：1)首先读取历史BIOS的POST(自检)代码数据，如果读取到历史BIOS的POST代码数据，则根据POST代码数据确定BIOS的程序自检故障原因，如CPU故障、内存故障等，并进行相关故障定位和上报告警处理。如果读取不到历史BIOS的POST代码数据，则说明程序起始阶段就出现异常，可能跟硬件相关。2)如果读取不到历史BIOS的POST代码数据，则判断与BIOS的程序自检相关的供电电路是否供电异常，如CPU等部件的供电状态，如果出现供电异常，则进一步判断是主板问题还是部件的问题，并上报故障原因。3)如果未出现供电异常，则通过控制通道切换器件与存储芯片建立通信，判断是否可读取到存储芯片内的BIOS镜像文件；如果读取不到存储芯片内的BIOS镜像文件，则确定存储芯片缺失BIOS镜像文件，并判断系统数据库中是否有备份的BIOS镜像文件，如果系统数据库中有备份的BIOS镜像文件，则直接将其写入到存储芯片中，并记录刷新日志，并重启系统，若系统重启后能够通过BIOS自检阶段，则验证故障原因就是存储芯片缺失BIOS镜像文件，并记录相关日志。如果系统数据库中没有备份的BIOS镜像文件，则上报告警到运维系统，安排运维人员烧写BIOS镜像文件。4)如果可读取到存储芯片内的BIOS镜像文件，则对其内BIOS镜像文件进行数据校验，计算相关的校验值，并与系统备份的BIOS镜像文件的校验值进行对比，如果校验值一致则对比通过，判定为存储芯片内的BIOS镜像文件未损坏；如果校验值不一致则对比失败，判定为存储芯片内的BIOS镜像文件损坏，记录相关日志，并自动采取重刷备份的BIOS镜像文件到存储芯片中的方式自动恢复镜像，并记录日志和重启系统，如果系统重启后能够通过BIOS自检阶段，则正好验证故障原因就是存储芯片内的BIOS镜像文件损坏。5)如果系统重启后依旧无法通过BIOS自检阶段，则上报故障更新最新的BIOS镜像文件或者更换主板。6)如果存储芯片内的BIOS镜像文件未损坏，则记录标记进行重启重试操作，如果重启正常，则清除记录的标记，如果重启多次都无法开机，则通知人工进行故 障分析，如尝试依次更换系统的主板/CPU/内存进行最小范围恢复，记录并上报相关告警。
需要说明的是，上述操作的顺序可独立进行或者打乱顺序都在本申请保护范围内。
作为一种可选的实施例，BIOS还用于在自身程序自检完成后进入运行阶段，并在运行完成后发出开机完成信号以完成BIOS运行阶段；
相应的，为BIOS运行阶段设定故障监控策略的过程，包括：
从BIOS发出自检信号时开始计时，判断在计时时间到达预设时间T3时，BIOS是否发出开机完成信号；
若是，则确定BIOS运行正常；
若否，则确定BIOS运行异常，并读取BIOS对应的POST故障码和/或BIOS故障寄存器数据，以根据POST故障码和/或BIOS故障寄存器数据进行BIOS的故障定位。
具体地，服务器的BIOS运行阶段：BIOS在自身程序自检完成后进入运行阶段，并在运行完成后发出开机完成信号(BOOT COMPLETE信号)，以完成BIOS运行阶段，而后进入OS启动阶段。需要说明的是，BIOS在运行阶段是对系统进行初始化，存在各种原因的异常和挂起，进而导致启动失败，此时不会发出开机完成信号。还需要说明的是，BIOS发出的自检信号实际是BIOS完成与服务器内BMC(Baseboard Management Controller，基板管理控制器)的直接通信链路的初始化后发送的第一个信号，代表着BIOS和BMC直接可以正常通信了，则以此为开始依据，后面可以增加各种交互信号和状态通知，如BIOS在初始化外设时，如果出现外设异常导致程序异常，则BIOS可将相关外设和状态进行记录并发送到BMC，由BMC保存到预留的BIOS故障寄存器；再如BIOS的TSL(操作系统加载前期)阶段中，如果发现系统硬盘缺失、OS启动块MBR(Master Boot Record，主引导记录)损坏或者MBR加载失败等异常，BIOS上报给BMC，由BMC保存到预留的BIOS故障寄存器，从而可将BMC保存的BIOS故障寄存器数据用于更加精确的故障定位。
基于此，本申请从BIOS发出自检信号时开始计时，判断在计时时间到达预设时间T3(如300s)时，BIOS是否发出开机完成信号；若BIOS按时发出 开机完成信号，则确定BIOS运行正常；若BIOS未按时发出开机完成信号，则确定BIOS运行异常，然后读取BIOS对应的POST故障码和/或BIOS故障寄存器数据，以根据POST故障码和/或BIOS故障寄存器数据定位BIOS的故障阶段和故障原因，定位出来后上报告警，运维更换相关部件。
更具体地，本申请可将BIOS运行阶段再次划分，包括SEC(安全验证)阶段、PEI(EFI前期初始化)阶段、DXE(驱动执行环境)阶段、BDS(启动设备选择)阶段、TSL阶段，以根据BIOS运行的各个阶段的情况进行分别判断。当BIOS进入每个阶段时发出一个开始信号，当顺利执行完此阶段时再发出一个完成信号，同时增加如图3所示的T3-1、T3-2、T3-3、T3-4的阶段计时，若在对应阶段计时内接收到对应的完成信号，则确定此阶段运行正常，否则确定此阶段运行异常，从而更加细化和精确判断故障位置，同时加快故障的判断(不用等待T3的超时，有的设备启动实际可能十几分钟)。需要说明的是，上述阶段计时时间可根据设备的实际配置进行时间配置。
另外，对于未知或无法明确的故障，本申请可记录相关标志重启设备，如果重启后恢复正常，或者定位出具体原因，则消除标志；如果重启多次后依旧存在未知或无法明确的故障，则上报告警到运维系统，通知运维依次检查更换CPU/内存等部件进行最小化故障定位。
作为一种可选的实施例，BIOS还用于在自身运行完成后开始引导OS启动；OS用于在自身安装的ipmitool驱动加载完毕后发出启动完成信号以完成OS启动阶段；
相应的，为OS启动阶段设定故障监控策略的过程，包括：
从BIOS发出开机完成信号时开始计时，判断在计时时间到达预设时间T4时，OS是否发出启动完成信号；
若是，则确定OS启动成功；
若否，则确定OS启动异常。
具体地，服务器的OS启动阶段：BIOS在自身运行完成后开始引导OS启动，OS启动异常属于操作系统范畴，根据系统安全的原则，本申请无法主动探测和跟踪OS的状态，因此本申请采用的方式是OS在自身安装的ipmitool(一种可用在linux系统下的命令行方式的ipmi平台管理工具)驱动加载完毕 后发出启动完成信号(启动OK信号)，以根据启动完成信号来判断OS启动完成，至此服务器的整个启动过程结束。
基于此，OS启动阶段的第一种故障监控策略：本申请从BIOS发出开机完成信号时开始计时，判断在计时时间到达预设时间T4(T4基于系统功能配置合理设定)时，OS是否发出启动完成信号；若OS按时发出启动完成信号，则确定OS启动成功；若OS未按时发出启动完成信号，则确定OS启动异常，记录相关日志，并上报OS启动异常，请求检查OS启动异常记录。
作为一种可选的实施例，服务器还包括用于修改预设时间T4的接口。
具体地，考虑到OS的启动时间跟系统的配置相关性很大，导致不同配置的系统，OS的启动时间差异很大，所以本申请的服务器设计可修改预设时间T4的接口，从而可根据系统的实际配置定义T4的大小。
作为一种可选的实施例，BIOS还用于在自身运行完成后开始引导OS启动；
相应的，为OS启动阶段设定故障监控策略的过程，包括：
在OS启动后，监听系统串口传输的系统日志记录，并判断在预设监听时间内是否监听到系统日志记录有错误信息；
若否，则确定OS启动成功；
若是，则确定OS启动异常，并根据错误信息及历史系统日志记录进行故障定位。
具体地，OS启动阶段的第二种故障监控策略：在OS启动后，监听系统串口传输的系统日志记录，并判断在预设监听时间内是否监听到系统日志记录有错误信息；若没有监听到系统日志记录有错误信息，则确定OS启动成功；若监听到系统日志记录有错误信息，则确定OS启动异常，并根据监听到的错误信息及历史系统日志记录进行故障定位，且对OS异常的情况进行上报告警，运维人员进行处理。
综上，本申请的服务器启动过程中的故障定位方法可均由服务器的BMC实现，其中，如图2所示，BMC与PSU、CPLD、ME单元通过I2C总线交互；BMC通过通道切换器件的控制线控制通道切换器件切换通道，以使BMC通过SPI(Serial Peripheral Interface，串行外设接口)总线与存储芯片交互。
请参照图4，图4为本申请实施例提供的一种服务器启动过程中的故障定位系统的结构示意图。
该服务器启动过程中的故障定位系统包括：
预设模块1，用于预先将服务器的整个启动过程划分为多个阶段，并相应为每个阶段设定故障监控策略；
监控模块2，用于在服务器的启动过程进入目标阶段时，按照目标阶段对应的故障监控策略监控服务器当前的启动过程，得到目标阶段对应的故障监控结果；其中，目标阶段为任一阶段；
定位模块3，用于在服务器启动失败时，根据得到的故障监控结果进行服务器的故障定位。
本申请提供的故障定位系统的介绍请参考上述故障定位方法的实施例，本申请在此不再赘述。
本申请还提供了一种服务器启动过程中的故障定位装置，包括：
存储器，用于存储计算机程序；
处理器，用于在执行计算机程序时实现上述任一种服务器启动过程中的故障定位方法的步骤。
本申请提供的故障定位装置的介绍请参考上述故障定位方法的实施例，本申请在此不再赘述。
还需要说明的是，在本说明书中，诸如第一和第二等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来，而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。而且，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者设备所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括所述要素的过程、方法、物品或者设备中还存在另外的相同要素。
对所公开的实施例的上述说明，使本领域专业技术人员能够实现或使用本申请。对这些实施例的多种修改对本领域的专业技术人员来说将是显而易见的，本文中所定义的一般原理可以在不脱离本申请的精神或范围的情况下，在其他实施例中实现。因此，本申请将不会被限制于本文所示的这些实施例，而是要符合与本文所公开的原理和新颖特点相一致的最宽的范围。

Claims (14)

  1. 一种服务器启动过程中的故障定位方法，其特征在于，包括：
    预先将服务器的整个启动过程划分为多个阶段，并相应为每个阶段设定故障监控策略；
    在所述服务器的启动过程进入目标阶段时，按照所述目标阶段对应的故障监控策略监控所述服务器当前的启动过程，得到所述目标阶段对应的故障监控结果；其中，所述目标阶段为服务器的整个启动过程划分的任一阶段；
    在所述服务器启动失败时，根据得到的故障监控结果进行所述服务器的故障定位。
  2. 如权利要求1所述的服务器启动过程中的故障定位方法，其特征在于，将服务器的整个启动过程划分为多个阶段的过程，包括：
    将服务器的整个启动过程划分为上电模式进入阶段、硬件上电阶段、BIOS自检阶段、BIOS运行阶段及OS启动阶段。
  3. 如权利要求2所述的服务器启动过程中的故障定位方法，其特征在于，所述服务器包括用于接收电源按键的按键信号，并将所述按键信号透传至ME单元的CPLD；还包括用于在接收到所述按键信号后，返回上电启动信号至CPLD以完成所述上电模式进入阶段的ME单元；
    相应的，为所述上电模式进入阶段设定故障监控策略的过程，包括：
    从所述CPLD接收到所述按键信号时开始计时，判断在计时时间到达预设时间T0时，所述ME单元是否发出上电启动信号；
    若是，则确定所述ME单元运行正常；
    若否，则确定所述ME单元运行失败。
  4. 如权利要求3所述的服务器启动过程中的故障定位方法，其特征在于，所述服务器还包括通过通道切换器件与所述ME单元连接、用于存储ME镜像文件的存储芯片；
    所述服务器启动过程中的故障定位方法还包括：
    在确定所述ME单元运行失败后，判断是否可获取到所述ME单元的运行状态；
    若可获取到，则在所述运行状态存在异常时确定所述ME单元存在运行异常的情况；
    若不可获取到，则判断所述存储芯片的供电电压是否正常；
    若供电电压异常，则确定所述存储芯片的周围电路异常；
    若供电电压正常，则确定所述存储芯片的周围电路正常，并通过控制所述通道切换器件与所述存储芯片建立通信，判断是否可正常访问到所述存储芯片；
    若不可正常访问到，则确定所述存储芯片异常；
    若可正常访问到，则确定所述存储芯片正常，并判断是否可读取到所述存储芯片内的ME镜像文件；
    若不可读取到，则确定所述存储芯片缺失所述ME镜像文件；
    若可读取到，则对所述存储芯片内的ME镜像文件进行数据校验，若校验失败，则确定所述存储芯片内的ME镜像文件损坏，并根据系统备份的ME镜像文件重新刷写所述存储芯片，并重启系统；
    若系统重启后依旧异常，则确定所述ME单元自身故障。
  5. 如权利要求4所述的服务器启动过程中的故障定位方法，其特征在于，所述服务器的供电系统包括PSU及与所述PSU连接、用于对应为所述服务器的各部件供电的多个VR供电芯片；
    且所述CPLD还用于在接收到上电启动信号后发送主电使能信号至所述PSU，并在接收到所述PSU返回的PG信号后依次发送芯片使能信号至多个VR供电芯片，且在接收到所有VR供电芯片返回的PG信号后发出电源正常信号以完成所述硬件上电阶段；所述CPLD在版本更新后还用于在所述PSU或任一VR供电芯片未按时返回PG信号时，相应记录此异常情况到自身的状态寄存器，并依次控制已上电的VR供电芯片及PSU进行下电操作；
    相应的，为所述硬件上电阶段设定故障监控策略的过程，包括：
    从所述ME单元发出上电启动信号时开始计时，判断在计时时间到达预设时间T1时，所述CPLD是否发出电源正常信号；
    若发出电源正常信号，则确定所述服务器的主板硬件上电正常；
    若未发出电源正常信号，则确定所述服务器的主板硬件上电异常，并根据所述CPLD的版本号判断所述CPLD是否具有异常记录功能；
    若具有异常记录功能，则读取所述CPLD的状态寄存器，以定位所述PSU或VR供电芯片的异常情况，并在VR供电芯片有异常情况时，根据异常的VR供电芯片的寄存器状态分析异常的VR供电芯片的故障原因；
    若不具有异常记录功能，则读取所述PSU和VR供电芯片的状态寄存器，以定位所述PSU或VR供电芯片的异常情况，并在VR供电芯片有异常情况时，根据异常的VR供电芯片的寄存器状态分析异常的VR供电芯片的故障原因。
  6. 如权利要求5所述的服务器启动过程中的故障定位方法，其特征在于，根据异常的VR供电芯片的寄存器状态分析异常的VR供电芯片的故障原因的过程，包括：
    若根据异常的VR供电芯片的寄存器状态确定异常的VR供电芯片存在短路故障，则确定异常的VR供电芯片的MOS管损坏；
    若根据异常的VR供电芯片的寄存器状态确定异常的VR供电芯片存在输入欠压，则查询异常的VR供电芯片的上一级VR供电芯片的电压是否正常，若是，则确定异常的VR供电芯片和上一级VR供电芯片之间的链路存在故障；
    若根据异常的VR供电芯片的寄存器状态确定异常的VR供电芯片存在OCP，则查询异常的VR供电芯片的下一级电路；
    若下一级电路为VR供电芯片，则检测下一级VR供电芯片是否能够正常访问或者工作状态是否异常，若无法正常访问或者出现短路情况，则确定主板需要更换；
    若下一级电路为直接部件，且该直接部件无法访问，则确定该直接部件需要更换，并对该直接部件的位置或编号进行记录。
  7. 如权利要求5所述的服务器启动过程中的故障定位方法，其特征在于，所述服务器的CPU用于在所述CPLD发出电源正常信号后开始工作，启动BIOS；所述BIOS用于在自身启动后进行程序自检，并在程序自检完成后发出自检信号以完成所述BIOS自检阶段；
    相应的，为所述BIOS自检阶段设定故障监控策略的过程，包括：
    从所述CPLD发出电源正常信号时开始计时，判断在计时时间到达预设时间T2时，所述BIOS是否发出自检信号；
    若是，则确定所述BIOS的程序完整可信；
    若否，则确定所述BIOS的程序存在问题。
  8. 如权利要求7所述的服务器启动过程中的故障定位方法，其特征在于，所述存储芯片还用于存储BIOS镜像文件；
    所述服务器启动过程中的故障定位方法还包括：
    在确定所述BIOS的程序存在问题后，判断是否可获取到BIOS的POST代码数据；
    若可获取到，则根据所述POST代码数据确定所述BIOS的程序自检故障原因；
    若不可获取到，则判断与所述BIOS的程序自检相关的供电电路是否供电异常；
    若供电异常，则对所述供电电路的供电异常进行故障原因分析；
    若供电正常，则通过控制所述通道切换器件与所述存储芯片建立通信，判断是否可读取到所述存储芯片内的BIOS镜像文件；
    若不可读取到，则确定所述存储芯片缺失所述BIOS镜像文件；
    若可读取到，则对所述存储芯片内的BIOS镜像文件进行数据校验，并判断是否校验成功；
    若校验成功，则进行系统重启操作，并在重启多次都无法开机后通知人工进行故障分析；
    若校验失败，则确定所述存储芯片内的BIOS镜像文件损坏，并根据系统备份的BIOS镜像文件重新刷写所述存储芯片，并重启系统。
  9. 如权利要求7所述的服务器启动过程中的故障定位方法，其特征在于，所述BIOS还用于在自身程序自检完成后进入运行阶段，并在运行完成后发出开机完成信号以完成所述BIOS运行阶段；
    相应的，为所述BIOS运行阶段设定故障监控策略的过程，包括：
    从所述BIOS发出自检信号时开始计时，判断在计时时间到达预设时间T3时，所述BIOS是否发出开机完成信号；
    若是，则确定所述BIOS运行正常；
    若否，则确定所述BIOS运行异常，并读取所述BIOS对应的POST故障码和/或BIOS故障寄存器数据，以根据所述POST故障码和/或所述BIOS故障寄存器数据进行所述BIOS的故障定位。
  10. 如权利要求9所述的服务器启动过程中的故障定位方法，其特征在于，所述BIOS还用于在自身运行完成后开始引导OS启动；所述OS用于在自身安装的ipmitool驱动加载完毕后发出启动完成信号以完成所述OS启动阶段；
    相应的，为所述OS启动阶段设定故障监控策略的过程，包括：
    从所述BIOS发出开机完成信号时开始计时，判断在计时时间到达预设时间T4时，所述OS是否发出启动完成信号；
    若是，则确定所述OS启动成功；
    若否，则确定所述OS启动异常。
  11. 如权利要求10所述的服务器启动过程中的故障定位方法，其特征在于，所述服务器还包括用于修改预设时间T4的接口。
  12. 如权利要求9所述的服务器启动过程中的故障定位方法，其特征在于，所述BIOS还用于在自身运行完成后开始引导OS启动；
    相应的，为所述OS启动阶段设定故障监控策略的过程，包括：
    在所述OS启动后，监听系统串口传输的系统日志记录，并判断在预设监听时间内是否监听到所述系统日志记录有错误信息；
    若否，则确定所述OS启动成功；
    若是，则确定所述OS启动异常，并根据所述错误信息及历史系统日志记录进行故障定位。
  13. 一种服务器启动过程中的故障定位系统，其特征在于，包括：
    预设模块，用于预先将服务器的整个启动过程划分为多个阶段，并相应为每个阶段设定故障监控策略；
    监控模块，用于在所述服务器的启动过程进入目标阶段时，按照所述目标阶段对应的故障监控策略监控所述服务器当前的启动过程，得到所述目标阶段对应的故障监控结果；其中，所述目标阶段为服务器的整个启动过程划分的任一阶段；
    定位模块，用于在所述服务器启动失败时，根据得到的故障监控结果进行所述服务器的故障定位。
  14. 一种服务器启动过程中的故障定位装置，其特征在于，包括：
    存储器，用于存储计算机程序；
    处理器，用于在执行所述计算机程序时实现如权利要求1-12任一项所述的服务器启动过程中的故障定位方法的步骤。
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CN115543694A (zh) * 2022-11-29 2022-12-30 苏州浪潮智能科技有限公司 Flash器件切换方法、装置、计算机设备和存储介质
CN116991637A (zh) * 2023-09-26 2023-11-03 苏州元脑智能科技有限公司 嵌入式系统的运行控制方法及装置、电子设备及存储介质
CN116991637B (zh) * 2023-09-26 2024-02-02 苏州元脑智能科技有限公司 嵌入式系统的运行控制方法及装置、电子设备及存储介质
CN117008704A (zh) * 2023-09-27 2023-11-07 天固信息安全系统(深圳)有限公司 基于ec或cpld的控制方法、装置、存储介质和电子设备
CN117008704B (zh) * 2023-09-27 2023-12-01 天固信息安全系统(深圳)有限公司 基于ec或cpld的控制方法、装置、存储介质和电子设备
CN117032813A (zh) * 2023-10-10 2023-11-10 浪潮(山东)计算机科技有限公司 双基本输入输出系统闪存的切换判定方法及装置
CN117032813B (zh) * 2023-10-10 2024-02-09 浪潮(山东)计算机科技有限公司 双基本输入输出系统闪存的切换判定方法及装置
CN117317418A (zh) * 2023-11-29 2023-12-29 珠海智锐科技有限公司 一种bms管理系统的电池控制方法
CN117317418B (zh) * 2023-11-29 2024-02-13 珠海智锐科技有限公司 一种bms管理系统的电池控制方法

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