WO2022198601A1 - 数据写入方法、片上系统芯片及计算机可读存储介质 - Google Patents

数据写入方法、片上系统芯片及计算机可读存储介质 Download PDF

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WO2022198601A1
WO2022198601A1 PCT/CN2021/083105 CN2021083105W WO2022198601A1 WO 2022198601 A1 WO2022198601 A1 WO 2022198601A1 CN 2021083105 W CN2021083105 W CN 2021083105W WO 2022198601 A1 WO2022198601 A1 WO 2022198601A1
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data unit
data
address information
block
information corresponding
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PCT/CN2021/083105
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English (en)
French (fr)
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龙帆
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深圳市汇顶科技股份有限公司
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Priority to PCT/CN2021/083105 priority Critical patent/WO2022198601A1/zh
Publication of WO2022198601A1 publication Critical patent/WO2022198601A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

Definitions

  • the present application relates to the field of chips, and more particularly, to a data writing method, a system-on-chip and a computer-readable storage medium.
  • Pseudo static random access memory adopts a self-refresh (Self refresh) mechanism, which can periodically refresh internal data without additional refresh circuits. Avoid data loss.
  • the maximum pull-down time of the chip select signal CS Chip select
  • the maximum pull-down time of the chip select signal CS is limited due to the self-refresh mechanism of the PSRAM. , which limits the data throughput of the PSRAM accessed each time, so that the MCU/SOC cannot access the PSRAM with the largest possible payload at a time like accessing the flash memory device, which greatly limits the access efficiency to the PSRAM. .
  • the embodiments of the present application provide a data writing method, a system-on-chip SOC chip, and a computer-readable storage medium, which effectively improve the access efficiency to the PSRAM without using an IP controller.
  • a first aspect provides a method for writing data, comprising: determining at least one data unit of data to be written into the PSRAM and the data according to the amount of data written in a single frame of a pseudo static random access memory (PSRAM)
  • PSRAM pseudo static random access memory
  • the instruction address information corresponding to the unit wherein the amount of data written in a single frame is the amount of data written within the time when the chip select signal corresponding to the PSRAM is at a low level; according to the instruction address information corresponding to the data unit and
  • the data unit generates at least one block, the at least one block forms a block chain table, and the block includes pointer information, instruction address information corresponding to the data unit and/or the data unit, the pointer information It is used to indicate the next block to be sent of the block when the block chain table is transmitted; through the direct memory access DMA controller, based on the block chain table, the instruction address information corresponding to the data unit and the data cells are sent to the PSRAM.
  • PSRAM pseudo static random access memory
  • a DMA controller with hardware circuit support is introduced in the process of writing PSRAM by software, and the software layer divides and determines the data to be sent at one time through software instructions into at least one data unit and an instruction corresponding to the data unit. address information, the instruction address information corresponding to the data unit and the data unit generate at least one block, each block includes pointer information, instruction address information corresponding to the data unit and/or the data unit, the At least one block forms a block chain list in an orderly manner through the pointer information, and sends the data to the PSRAM in the form of a block chain list through the DMA controller, which saves the time that the software layer consumes software instructions to indicate multiple segmentation, configuration, and data transmission. , which effectively improves the access efficiency to the PSRAM and realizes high-speed writing to the PSRAM.
  • a block is a block containing the data unit.
  • the block further includes: configuration information, where the configuration information is used to instruct the DMA controller to transmit instructions required for the block.
  • each block has its corresponding configuration information, that is to say, the configuration information of each block may be different, and the DMA controller can transmit the blocks through different configurations, which improves the access to PSRAM flexibility and freedom.
  • the instruction includes at least one of a transmission direction instruction, a transmission channel instruction, a transmission speed instruction, and a transmission data width instruction for the DMA controller to transmit the block.
  • the configuration information configures the multiple transmission instructions required for transmitting each block, so that the DMA controller can transmit data of different data sizes, different transmission directions, and different transmission paths at different transmission speeds, thereby further improving the data Transmission flexibility.
  • the generating at least one block according to the instruction address information corresponding to the data unit and the data unit includes: generating according to the instruction address information corresponding to the data unit and the data unit A block, the block includes the configuration information, the pointer information, the instruction address information corresponding to the data unit, and the data unit.
  • the software layer processes the data into blocks, it can be stored in the cache space in the memory that matches the data format of the block, that is, the instructions corresponding to the data units can be opened in the memory
  • the new cache space in which the address information matches the data unit stores the instruction address information corresponding to the data unit and the data unit before data transmission.
  • the generating at least one block according to the instruction address information corresponding to the data unit and the data unit includes: the generating according to the instruction address information corresponding to the data unit and the data unit Generate a first block and a second block, where the first block includes configuration information of the first block, pointer information of the first block, and instruction address information corresponding to the data unit, and the The second block includes configuration information of the second block, pointer information of the second block, and the data unit.
  • the instruction address information and the data unit corresponding to the data unit are configured into the first block and the second block, respectively, so that the DMA controller does not need to divide the area with a special data width in the process of sending data to the PSRAM.
  • the block is stored in the newly opened new cache space, which can directly write the block into the existing cache space of the MCU/SOC memory, saving memory and software instructions for transferring data from the new cache space, further improving the access to PSRAM efficiency.
  • the method further includes: determining the instruction address information corresponding to the data unit sent by the DMA controller and the data volume of the data unit, when the data volume is equal to preset data When the amount is, the chip select signal is pulled high, wherein the preset data amount is a threshold determined according to the instruction address information corresponding to the data unit and the data unit.
  • the chip select signal is controlled not to be pulled high before the amount of transmitted data does not reach the threshold, so as to avoid the accidental pull-up of the chip select signal before data transmission is completed, ensure normal data transmission, and improve access program stability.
  • the preset data amount is equal to the instruction address information corresponding to the data unit and the data amount of the data unit.
  • the instruction address information corresponding to the data unit and the chip select signal will not be pulled high before the data unit is sent, so that the data can be transmitted normally.
  • the command address information and the data unit corresponding to the data unit are respectively configured as the first block and the second block, it can be ensured that the chip select signal is pulled high after the second block is sent.
  • the chip select signal is pulled high after the first block is sent, so that the first block and the second block cannot be sent continuously, and the command address information and data unit corresponding to the data unit cannot be written continuously. , which eventually leads to the problem of data writing errors.
  • the pull-down time of the chip select signal is maximized to improve the efficiency of data transmission, thereby improving the access efficiency to the PSRAM.
  • the sending the instruction address information corresponding to the data unit and the data unit to the PSRAM through the direct memory access DMA controller based on the block chain table includes: The DMA controller writes the instruction address information corresponding to the data unit and the data unit into the cache, and sends the instruction address information corresponding to the data unit and the data unit to the PSRAM through the cache.
  • the speed of data transmission can be controlled, and the data transmission speed is too fast to cause sticky packets, that is, the next block to be sent can be avoided when the block has not been sent.
  • the block enters the cache, and the chip select signal is not pulled high after the block is sent to cause abnormal circuit, which further ensures the normal transmission of data, improves the stability of the program when accessing the PSRAM and the reliability of operation in complex environments. sex.
  • the method further includes: controlling the first writing speed to be no greater than the sending speed of the cache, controlling the second writing speed to be no greater than the sending speed, and the first writing speed is the speed at which the DMA controller writes the instruction address information corresponding to the data unit to the cache, and the second writing speed is the speed at which the DMA controller writes the data unit to the cache,
  • the sending speed is the instruction address information corresponding to the data unit and the speed at which the data unit is sent from the cache to the PSRAM.
  • the first speed and the second speed may be equal, that is, when the command address information corresponding to the data unit and the data unit generate a block, the first speed and the second speed If the speed is equal to and smaller than the sending speed, the instruction address information corresponding to the data unit and the data unit are sent to the cache in sequence.
  • the instruction address information corresponding to the data unit and the data unit respectively generate the first block and the second block, the first speed and the second speed are both lower than the sending speed, The instruction address information corresponding to the data unit and the data unit are sequentially sent to the cache at the first speed and the second speed respectively.
  • the filling speed of the blocks in the cache can be controlled, and the occurrence of excessive writing speed can be effectively avoided. sticking phenomenon. For example, when the instruction address information corresponding to the data unit in the first block has not been sent from the cache, the second block has been written into the cache, and the sticky packet will result in the completion of sending the information in the first block The post-chip select signal cannot be released normally, which in turn causes the circuit to work abnormally.
  • the method further includes: determining the instruction address information corresponding to the data unit and the data amount of the data unit sent by the DMA controller; controlling the first writing speed to be no greater than all the sending speed of the cache, the second writing speed is controlled to be no greater than the sending speed, and the first writing speed is the speed at which the DMA controller writes the instruction address information corresponding to the data unit to the cache,
  • the second writing speed is the speed at which the DMA controller writes the data unit to the cache
  • the sending speed is the instruction address information corresponding to the data unit and the data unit being sent by the cache speed to the PSRAM; when the amount of data sent at the sending speed is equal to a preset amount of data, pull up the chip select signal, where the preset amount of data is based on the amount of data corresponding to the data unit
  • the instruction address information and the threshold determined by the data unit when the amount of data sent at the sending speed is equal to a preset amount of data, pull up the chip select signal, where the preset amount of data is based on the amount of data
  • the embodiments of the present application ensure the normal pull-up of the chip select signal by controlling the filling speed of the block in the cache and the pull-up condition of the chip-select signal, which can further improve the stability of the program when accessing the PSRAM in a complex environment, and ensure that the Access programs run safely and efficiently in complex environments.
  • the method further includes: after the instruction address information corresponding to the data unit and the data unit are sent by the DMA controller, receiving write-back information sent by the DMA controller , the write-back information is used to indicate that the instruction address information corresponding to the data unit and the data unit are sent, and the write-back information includes the instruction address information corresponding to the data unit and the status information and / or location information.
  • the DMA controller by receiving the write-back information sent by the DMA controller, the DMA controller performs the write-back operation after writing the block and before writing the next block to be sent, and the software layer receives the write-back information.
  • the write-back information sent by the DMA controller can consume some software instructions, increase the time interval between the block and the next block to be sent in the process of transmitting the block chain list, and avoid the phenomenon of data sticking. The security and stability of accessing PSRAM are further improved.
  • a system-on-a-chip SOC chip characterized in that it includes:
  • a processor configured to determine at least one data unit of data to be written into the PSRAM and instruction address information corresponding to the data unit according to the amount of data written in a single frame of the pseudo-static random access memory PSRAM, wherein the single-frame write
  • the amount of input data is the amount of data written within the time of the low level of the chip select signal corresponding to the PSRAM; at least one block is generated according to the instruction address information corresponding to the data unit and the data unit, and the at least one block is The block forms a block chain list, and the block includes pointer information, instruction address information corresponding to the data unit and/or the data unit, and the pointer information is used to indicate the block when the block chain list is transmitted. the next block to be sent;
  • the DMA controller is configured to send the instruction address information corresponding to the data unit and the data unit to the PSRAM based on the block chain table.
  • the block further includes: configuration information, where the configuration information is used to instruct the DMA controller to transmit instructions required for the block.
  • the instruction includes at least one of a transmission direction instruction, a transmission channel instruction, a transmission speed instruction, and a transmission data width instruction for the DMA controller to transmit the block.
  • the processor is configured to: generate a block according to the instruction address information corresponding to the data unit and the data unit, and the block includes the configuration information, the pointer information, The instruction address information corresponding to the data unit and the data unit.
  • the processor is configured to: generate a first block and a second block according to the instruction address information corresponding to the data unit and the data unit, where the first block includes the The configuration information of the first block, the pointer information of the first block, the instruction address information corresponding to the data unit, the second block includes the configuration information of the second block, the second block The pointer information of the block, the data unit.
  • the processor is further configured to: determine the instruction address information corresponding to the data unit and the data amount of the data unit sent by the DMA controller, when the data amount is equal to a predetermined amount When the data amount is set, the chip select signal is pulled high, wherein the preset data amount is a threshold determined according to the instruction address information corresponding to the data unit and the data unit.
  • the preset data amount is equal to the instruction address information corresponding to the data unit and the data amount of the data unit.
  • the chip further includes:
  • the DMA controller is used to write the instruction address information corresponding to the data unit and the data unit into the cache, and the cache is used to write the instruction address information corresponding to the data unit written by the DMA controller and the data unit is sent to the PSRAM.
  • the processor is further configured to: control the first writing speed to be no greater than the sending speed of the cache, control the second writing speed to be no greater than the sending speed, and the first writing speed
  • the input speed is the speed at which the DMA controller writes the instruction address information corresponding to the data unit to the cache
  • the second write speed is the speed at which the DMA controller writes the data unit to the cache.
  • the sending speed is the instruction address information corresponding to the data unit and the speed at which the data unit is sent from the cache to the PSRAM.
  • the chip further includes: a cache; the processor is further configured to: determine the instruction address information corresponding to the data unit and the data amount of the data unit sent by the DMA controller ; Control the first write speed to be no greater than the sending speed of the cache, control the second write speed to be no greater than the sending speed, and the first write speed is the DMA controller writing the cache to the cache.
  • the speed of the instruction address information corresponding to the data unit, the second writing speed is the speed at which the DMA controller writes the data unit to the cache
  • the sending speed is the instruction address information corresponding to the data unit and the speed at which the data unit is sent to the PSRAM by the cache; when the amount of data sent at the sending speed is equal to the preset amount of data, the high-level state of the chip select signal is maintained, wherein,
  • the preset data amount is a threshold determined according to the instruction address information corresponding to the data unit and the data unit.
  • the processor is further configured to: after sending the instruction address information corresponding to the data unit and the data unit through the DMA controller, receive a reply sent by the DMA controller Write information, the write-back information is used to indicate the instruction address information corresponding to the data unit and the completion of sending the data unit, and the write-back information includes the instruction address information corresponding to the data unit and the state of the data unit information and/or location information.
  • a third aspect provides a computer-readable storage medium, where computer-executable instructions are stored in the computer-readable storage medium, and when the computer-executable instructions are executed by a processor, are used to implement any possible implementation of the first aspect method of writing data in the manner described.
  • the data to be sent is determined as a block chain list, and sent to the PSRAM through the DMA controller, which greatly saves the time and time required for the software layer to repeatedly process and configure the data to be sent.
  • Software instructions improve the writing efficiency of PSRAM devices and enable them to reach the IP controller level.
  • FIG. 1 is a schematic structural diagram of a main control chip and an external device according to an embodiment of the present application.
  • FIG. 2 is a schematic diagram of a PSRAM access timing sequence according to an embodiment of the present application.
  • FIG. 3 is a flowchart of data writing by a software writing controller according to an embodiment of the present application.
  • FIG. 4 is a schematic diagram of a timing frame of data written by a software write controller according to an embodiment of the present application.
  • FIG. 5 is a logical schematic diagram of writing data by a software write controller according to an embodiment of the present application.
  • FIG. 6 is a flowchart of a data writing method according to an embodiment of the present application.
  • FIG. 7 is a schematic diagram of a timing frame according to an embodiment of the present application.
  • FIG. 8 is a schematic diagram of a block chain table according to an embodiment of the present application.
  • FIG. 9 is a schematic diagram of another block chain table according to an embodiment of the present application.
  • FIG. 10 is a schematic diagram of another block chain table according to an embodiment of the present application.
  • FIG. 11 is a schematic diagram of a relationship between a block and a chip select signal according to an embodiment of the present application.
  • FIG. 12 is a schematic diagram of a first-in, first-out cache according to an embodiment of the present application.
  • FIG. 13 is a schematic diagram of an SOC chip according to an embodiment of the present application.
  • FIG. 14 is a schematic diagram of another SOC chip according to an embodiment of the present application.
  • FIG. 15 is a schematic diagram of a software writing controller according to an embodiment of the present application.
  • FIG. 16 is another logical schematic diagram of writing data by a software controller according to an embodiment of the present application.
  • CPU central processing unit
  • memory controller memory controller
  • I/O input/output
  • SOC System on chip
  • FIG. 1 is a schematic structural diagram of a main control chip and an external device according to an embodiment of the present application.
  • the main control chip 100 is composed of a software layer 101 and a hardware layer 102.
  • the software layer 101 can control each hardware of the hardware layer 102 to implement different functions through software instructions.
  • a processor can control the main control chip to perform various read and write operations.
  • the software layer 101 includes various types of controllers, logic circuits, etc.
  • the hardware layer 102 includes at least one microprocessor (Micro processing unit, MPU) or digital signal processor (Digital signal processor, DSP), memory, Hardware circuits, interface management modules for managing different physical interfaces, converters for converting digital signals and analog signals, oscillators for providing clock signals (Clock signal, CLK), etc.
  • MPU microprocessor
  • DSP digital signal processor
  • the memory can be one or more read-only Memory (Read-only memory, ROM), random access memory (Random access memory, RAM), flash memory, etc.
  • Main control chips such as MCU/SOC can realize multi-functional integration through the synchronous design of software layer and hardware layer.
  • the main control chip 100 can externally connect multiple storage devices 103, 104, etc.
  • These external storage devices can be static random access memory (Static random access memory, SRAM), Dynamic random access memory (Dynamic random access memory, DRAM) or pseudo static random access memory (Pseudo static random access memory, PSRAM) and so on.
  • SRAM static random access memory
  • DRAM Dynamic random access memory
  • PSRAM pseudo static random access memory
  • PSRAM is a kind of memory that adopts DRAM technology to realize the function and effect similar to SRAM. It has the advantages of simple interface and large storage capacity. In the current smart wearable market, PSRAM has become an ideal choice for expanding the RAM storage space and resource data cache of MCU/SOC, and is one of the common external devices for MCU/SOC.
  • PSRAM adopts a self-refresh mechanism. Unlike DRAM devices, which require additional refresh circuits to control memory cells to refresh data regularly, PSRAM will periodically refresh data to avoid data loss. This also causes the MCU/SOC to access the PSRAM during the access cycle.
  • the longest pull-down time of the chip select signal CS (Chip select) cannot exceed the PSRAM self-refresh time, and the CS signal is longer than the longest pull-down time without releasing the CS signal. It will cause the PSRAM self-refresh circuit to work abnormally, resulting in errors in accessing data.
  • the MCU/SOC accesses the PSRAM, it cannot use the largest possible payload for access at a time, but is limited by the longest pull-down time of the CS signal, and completes data transmission through multiple accesses.
  • the earth limits the access efficiency of MCU/SOC to PSRAM.
  • FIG. 2 is a schematic diagram of a PSRAM access timing sequence according to an embodiment of the present application.
  • the PSRAM supports SPI and QSPI interfaces.
  • a write access cycle of MCU/SOC to PSRAM starts from the CS signal is pulled low and ends when the CS signal is pulled high.
  • the write controller of the MCU/SOC controls the hardware layer to write data into the PSRAM by sending a timing frame.
  • a timing frame sent to the PSRAM usually consists of 3 parts: a 1-byte instruction (Instruction) part, a 3-byte address (Address) part and a several-byte data (Data) part.
  • the instruction part of 1 byte and the address part of 3 bytes are the necessary overhead for PSRAM write access.
  • the time consumption of writing the timing frame to PSRAM cannot exceed the longest pull-down time of the CS signal, otherwise the PSRAM The self-refresh mechanism will cause access errors.
  • IP write controller which can be directly integrated into the MCU/SOC.
  • IP write controller In addition to the general write controller function, It also has a control circuit specially designed for the longest CS signal pull-down time corresponding to the PSRAM, which can automatically divide the data, construct the timing frame, and send it inside the IP write controller, without wasting additional software instructions in the software layer.
  • the software layer only needs to write the registers in the MCU/SOC memory exposed by the controller to perform the relevant configuration. The work efficiency is high, but it requires additional R&D design or purchase authorization, and the cost is high.
  • the other type is the software write controller, which can be based on the existing structure and functions on the MCU/SOC, through the software layer design, in a software-controlled way to reduce the amount of data written each time according to the longest CS signal pull-down time.
  • FIG. 3 is a flowchart of data writing by a software write controller according to an embodiment of the present application, and the process is executed by the software write controller of the MCU/SOC:
  • S301 perform register configuration according to the access sequence of the PSRAM.
  • the access timing of the PSRAM will be provided by the manufacturer when the PSRAM leaves the factory, and the register configuration includes instruction-related, address-related, timing-related, and data-related register configurations.
  • the register configuration includes at least: setting the access instruction in the instruction register, setting the width of the access instruction in the instruction width register, setting the sending mode of the access instruction in the instruction mode bit register, setting the address width register in the address width register. Width, the transmission mode of the access address is set in the address mode bit register, the number of clock signals is set in the timing (Dummy) number register, and the transmission mode of the data is set in the data mode register.
  • the transmission mode includes single-line mode or multi-line mode.
  • the timing frame includes an instruction, an address, a timing sequence, and data of a certain length, wherein the data length is calculated by the software layer according to the longest CS signal pull-down time.
  • FIG. 4 is a schematic diagram of a timing frame of data written by a software write controller according to an embodiment of the present application.
  • the method of implementing PSRAM write access by the software write controller requires dividing data, constructing timing frames and sending timing frames through software instructions, plus the consumption of software instructions such as system scheduling, and Compared with the IP write controller, it will waste more time, making the time interval T too long, generally at the level of tens of microseconds. Compared with the effective write time (8 ⁇ s), the waste of timing resources accounts for an excessively large proportion, which is serious. Affects the access rate of PSRAM.
  • the for/while logic is used to execute the PSRAM write process, and when the maximum operating frequency SCLK of the serial interface is 48MHz and the four-wire mode is adopted, the data payload is 128 bytes.
  • the CS signal is pulled low for 6.5 ⁇ s-6.8 ⁇ s, that is, the effective time to transmit data is 6.5 ⁇ s-6.8 ⁇ s; the time interval between timing frames is about 70 ⁇ s, That is, the time to wait for the data to be divided and constructed into a timing frame is 70 ⁇ s, and the time interval is extremely unstable.
  • the ratio of valid time to invalid time is 6.8 ⁇ s:70 ⁇ s, that is, 0.097 :1, the timing resources are wasted seriously.
  • this application designs a data writing method, which is applied to the MCU/SOC chip, which can reduce the time.
  • the interval T makes the access efficiency of the software write controller to the PSRAM reach the level of the IP write controller.
  • the embodiments of the present application take an SOC chip supporting a QSPI interface as an example, and it should be understood that the methods described in the embodiments of the present application are also applicable to other MCU/SOC chips supporting SPI and QSPI interfaces.
  • the "pulling up the chip selection signal” in the embodiment of the present application means “releasing the chip selection signal”. After the chip selection signal is pulled up, the high level state of the chip selection signal will be maintained until the chip selection signal is pulled down, and "the chip selection signal is pulled down”. After that, the chip select signal will be maintained at a low level until the chip select signal is pulled high.
  • FIG. 6 is a flowchart of a data writing method according to an embodiment of the present application.
  • S601. Determine at least one data unit of data to be written into the PSRAM and instruction address information corresponding to the data unit according to the amount of data written in a single frame of the PSRAM, where the amount of data written in a single frame is the amount of the data to be written in the PSRAM.
  • S602 generate at least one block according to the instruction address information corresponding to the data unit and the data unit, and the at least one block forms a block chain list;
  • S603 Send the instruction address information corresponding to the data unit and the data unit through the DMA controller based on the block chain table.
  • the software write controller determines the amount of data written in a single frame of the PSRAM according to the pull-down time of the CS signal, the operating frequency of the serial interface, and the operating mode of the serial interface.
  • the maximum operating frequency of the serial interface is related to the crystal frequency of the hardware, and the operating mode of the serial interface is used to determine the number of data bits transmitted by each clock signal.
  • the amount of data written in a single frame is the amount of data written within the time when the chip select signal corresponding to the PSRAM is at a low level, that is, the maximum amount of data that can be written by the PSRAM within the time when the CS signal is pulled low.
  • the time that the CS signal is pulled low is the time that the SOC maintains the low level of the CS signal.
  • the amount of data written in a single frame of PSRAM can be determined by the following algorithm:
  • PLAYLOAD is the amount of data written in one frame of PSRAM
  • SCLK is the maximum operating frequency of the serial interface
  • MODE_BITS is the number of data bits transmitted by each clock signal in the working mode of a serial interface
  • t_CEM is the CS signal pull-down time
  • 1000000u is 1000000 ⁇ s
  • 1/1000000u is 1MHz.
  • the operating frequency of a SOC's QSPI is 48MHz
  • the 4-wire operating mode MODE_BITS is 4
  • the typical CS signal pull-down time is 8 ⁇ s
  • the amount of written data in a single frame of this PSRAM is 48*(4/ 8)*8, that is, 192 bytes. It should be understood that, in practical application, taking into account the security redundancy of data, an actual write data volume smaller than 192 bytes will be used.
  • the above-mentioned code for determining the amount of data written in a single frame of the PSRAM is only one of the determination methods. Any modification of the above-mentioned code, or the longest CS signal pull-down time, the maximum operating frequency of the serial interface, the serial The code or combination of codes that determines the amount of data written in a single frame of the PSRAM by the working mode of the row interface can be substituted for the above code.
  • the amount of data written in a single frame of PSRAM can also be determined by the following code:
  • PSRAM_SAFE_tCEM_US 8u/*Typical tCEM is 8us*/
  • the software write controller determines that at least one data unit to be written into the PSRAM data corresponds to the data unit according to the amount of data written in a single frame of the pseudo static random access memory PSRAM.
  • the instruction address information includes:
  • the data volume of each data part is the write data volume of a single frame of PSRAM, and the n data parts are configured as n data units and their corresponding command address information , where the instruction address information includes instruction information and address information.
  • the instruction information of keeping n timing frame information is the same, and the data width is 1 byte; the address information of n timing frame information is updated, and the data width is 3 bytes.
  • the address information includes start address information and buffer address information, and updating the address information means updating the address offsets and buffer offsets of n timing frames.
  • the software writing controller after determining the data unit and its corresponding instruction address information, the software writing controller generates at least one block, the at least one block forms a block chain list, and the block includes pointer information, all The instruction address information corresponding to the data unit and/or the data unit, and the pointer information is used to indicate the next block to be sent of the block when the block chain list is transmitted.
  • Direct memory access is an interface technology in which external devices directly exchange data with the system memory without passing through the central processing unit (CPU).
  • the DMA controller directly transmits and receives data through the bus.
  • the linked list is one of the functions of the DMA controller in the MCU/SOC device.
  • data is transmitted in units of blocks, and the arrows in the figure show the order in which the information is sent.
  • the pointer information may link a plurality of blocks in a sequential order so that the DMA controller sequentially transmits the plurality of blocks in the linking order.
  • the DMA controller automatically loads the data of the next block to be sent of the block in the block chain list according to the pointer information of the block and sends it until the pointer information of the chain list is empty.
  • the block includes configuration information, pointer information, instruction address information corresponding to the data unit and/or the data unit, and the configuration information is used to instruct the DMA controller to transmit the required information for the block. instruction.
  • each block has configuration information, and the DMA controller can transmit blocks through different configurations, which improves the flexibility and freedom of data transmission.
  • the configuration information includes at least one of a transmission direction instruction, a transmission channel instruction, a transmission speed instruction, and a transmission data width instruction for the DMA controller to transmit the block.
  • the DMA controller can transmit data of different data sizes, different transmission directions, and different transmission paths at different transmission speeds by configuring the multiple transmission instructions required for transmitting each block through the configuration information, which further improves the software writing ability. Flexibility of controller data transfer.
  • the configuration information further includes: the number of DMAs, a bus burst (Burst) behavior, a buffer address, a write target address, a buffer data width, and the like.
  • configuring the number of DMAs and the bus burst behavior enables the software write controller to select multiple DMA controllers to transmit data according to the data to be sent, determine the number of times of each DMA transfer, configure the buffer address, write target
  • the address and buffer data width enable the software write controller to send blocks to different buffer areas, dynamically adjust the data transmission route, and further improve the flexibility of data transmission.
  • the software write controller sends the instruction address information corresponding to the data unit and the data unit to the PSRAM through the DMA controller based on the block chain table.
  • the software layer configures the data to be sent into blocks, and the DMA controller sends the data to be sent in the MCU/SOC memory in the form of blocks.
  • the DMA controller sends blocks according to the block chain list based on hardware circuits, and does not require too many software instructions.
  • the time interval between sending each block is much smaller than the time interval between sending each timing frame T.
  • a DMA controller with hardware circuit support is introduced in the process of software writing PSRAM, and the software writing controller divides and determines the data to be sent at one time based on the processor into at least one data unit corresponding to the data unit.
  • the instruction address information, the instruction address information corresponding to the data unit and the data unit generate at least one block, each block includes pointer information, the instruction address information corresponding to the data unit and/or the data unit,
  • the at least one block is formed into a block chain list in an orderly manner through the pointer information, and the data is sent to the PSRAM in the form of a block chain list through the DMA controller, which saves the software writing controller from consuming software instruction instructions for multiple segmentation, configuration,
  • the time for sending data effectively improves the access efficiency of the software write controller to the PSRAM, and realizes the high-speed writing of the PSRAM.
  • the next block containing the instruction address information corresponding to the data unit is to be sent.
  • the block is the block containing the data unit, and the DMA controller sequentially sends the block containing the instruction address information corresponding to the data unit and the block containing the data unit to the PSRAM.
  • the software writing controller generates a block according to the instruction address information corresponding to the data unit and the data unit, and the block includes the configuration information, The pointer information, the instruction address information corresponding to the data unit, and the data unit.
  • the DMA controller can transmit the blocks in the form of a block chain list, and the software layer does not need to consume software instructions to send data, which improves the The working efficiency of the software write controller.
  • the blocks can be stored in the memory, that is to say, the instruction address information corresponding to the data unit can be opened up in the memory and the data unit matching the data unit.
  • the new cache space stores the instruction address information corresponding to the data unit and the data unit before data transmission.
  • the 4-byte instruction address information is the necessary overhead for writing data into the PSRAM
  • the data width of the new cache space is the sum of the number of bytes of the data unit and the number of bytes of the instruction address information corresponding to the data unit.
  • FIG. 10 it is a schematic diagram of another block chain table in this embodiment of the present application.
  • the software write controller generates a first block and a second block according to the instruction address information corresponding to the data unit and the data unit, and the first block includes the configuration information of the first block, the data
  • the instruction address information corresponding to the unit, the pointer information of the first block, and the second block includes the configuration information of the second block, the data unit, and the pointer information of the second block. That is, when the software writing controller generates a block corresponding to a data unit and its corresponding instruction address information, it generates a first block and a second block respectively with one instruction address information and corresponding data.
  • the instruction address information and the corresponding data are configured as the corresponding first block and the second block, and the data can be directly stored in the existing cache space of the MCU/SOC memory, without the need for the block to have a special data width
  • FIG. 11 is a schematic diagram of a relationship between a block and a chip select signal according to an embodiment of the present application, showing an ideal state in which data is sent to the PSRAM by using a DMA controller, that is, the command address information corresponding to the data unit and the start of the data unit Before sending, the CS signal is pulled low, and after the command address information corresponding to the data unit and the data unit are sent, the CS signal is pulled high. That is, the CS signal is pulled low before the first block is sent, and the CS signal is pulled high after the second block is sent.
  • the DMA controller cannot send the instruction address information and data units corresponding to the data units to the cache in time, especially the instruction address information and data corresponding to the data units.
  • the units are configured as the first block and the second block, it may happen that the cache releases the CS signal unexpectedly after sending the first block, resulting in that the data in the second block to be sent lacks instruction address information and cannot be written. In the case of PSRAM, data errors are caused.
  • the method further includes determining the instruction address information corresponding to the data unit sent by the DMA controller and the data volume of the data unit, when the data volume is equal to a preset value.
  • the chip select signal is pulled high, wherein the preset data amount is a threshold determined according to the instruction address information corresponding to the data unit and the data unit.
  • a counter can be set at the QSPI interface to count the amount of data flowing out of the QSPI.
  • the CS signal is not pulled high, the CS signal always maintains the pull-down state of the low level, and the data is written into the PSRAM from the MCU/SOC; when the count value of the counter is When the corresponding data amount reaches the preset data amount, the CS signal is pulled high, and the low level is no longer maintained.
  • the chip selection signal is controlled not to be pulled high before the amount of transmitted data does not reach the threshold, so as to avoid the accidental pull-up of the chip selection signal before the data transmission is completed, ensure the normal transmission of data, and improve the software Write the stability of the controller operation.
  • the preset data amount is equal to the instruction address information corresponding to the data unit and the data amount of the data unit.
  • the counter value increases by 1 every time data flows from QSPI to PSRAM.
  • the chip select signal always maintains a low level state.
  • the chip select signal is released and pulled high, and the low level is no longer maintained.
  • the pre-designed value of the counter is in beats, and is obtained by configuring the instruction address information corresponding to the data unit and the data amount of the data unit, and the data amount corresponding to the pre-designed value is the preset data amount. That is, the data amount corresponding to the pre-designed value of the counter is equal to the instruction address information corresponding to the data unit and the data amount of the data unit.
  • the bus data width HSIZE is different
  • the data amount corresponding to the counter beats is also different. For example: when the bus width is 8 bits (bit), the unit of 1-beat data is byte; when the bus width is 16-bit, the unit of 1-beat data is half-word; when the bus width is 32-bit, the unit of 1-beat data is word.
  • the sending the data unit and the instruction address information corresponding to the data unit to the PSRAM based on the block chain table through the direct memory access to the DMA controller includes: sending the data through the DMA.
  • the instruction address information corresponding to the unit and the data unit are written into the cache, and the instruction address information corresponding to the data unit and the data unit are sent to the PSRAM through the cache.
  • the SOC sends data to the PSRAM through the QSPI interface
  • the data to be written is processed into blocks by the software layer
  • it is first written into the cache by the DMA controller from the memory of the SOC, for example, the first-in-first-out cache area (First input first output, FIFO), and then sent by the FIFO to the external PSRAM through the QSPI interface, the data in the FIFO will be automatically sent according to the order.
  • FIFO First input first output
  • FIG. 12 it is a schematic diagram of a first-in, first-out cache according to an embodiment of the present application, and the data width of the cache is 32 bits.
  • the speed of data transmission can be controlled to avoid sticky packets caused by too fast speed, that is, the next block to be sent when the block transmission is not completed It enters the cache, resulting in the situation that the chip select signal is not pulled high after the block is sent, resulting in a circuit abnormality. Controlling the speed of data transmission can further ensure the normal transmission of data, improve the stability of the software writing controller and the reliability of operation in complex environments.
  • the method further includes: controlling the first writing speed to be no greater than the sending speed of the cache, controlling the second writing speed to be no greater than the sending speed, and the first writing speed
  • the speed is the speed at which the DMA controller writes the instruction address information corresponding to the data unit to the cache
  • the second writing speed is the speed at which the DMA controller writes the data unit to the cache
  • the sending speed is the instruction address information corresponding to the data unit and the speed at which the data unit is sent from the cache to the PSRAM.
  • the first speed and the second speed can be equal, that is, when the command address information corresponding to the data unit and the data unit generate a block, the first speed and the second speed are equal and both are smaller than the sending speed, and the command corresponding to the data unit
  • the address information and the data unit as a whole are sent to the buffer one after another.
  • the first speed and the second speed are both lower than the transmission speed, and the command address information corresponding to the data unit and the data unit respectively start with the first block and the second block.
  • the speed and the second speed are sent to the buffer one after another.
  • the software write controller controls the block writing speed to be no greater than the sending speed, wherein the writing speed can be used according to the data width of the block and the DMA controller.
  • the bus width can be adjusted.
  • the filling speed of the block in the cache can be controlled to effectively avoid writing The sticking phenomenon caused by too fast speed.
  • the second block has been written into the FIFO, which is a sticky packet. Sticky packets will cause the software layer to mistakenly think that the sending of the command address information in the first block has not been completed after the sending of the command address information in the first block is completed, and the CS signal cannot be released normally, resulting in abnormal circuit operation.
  • the writing speed By controlling the writing speed not to be greater than the sending speed, it can be ensured that the next block to be sent will enter the cache only after the transmission of the data and/or command address information in the block is completed.
  • the signal can be pulled high, effectively avoiding sticky packets and further improving the performance of the software writing controller.
  • the first writing speed and the second writing speed by configuring the first writing speed and the second writing speed to be equal to the sending speed, it can not only ensure that the next block to be sent will enter the cache after the block transmission is completed, but also avoid writing
  • the time sequence waste caused by the slow input speed further improves the work efficiency of the PSRAM software writing controller.
  • the PSRAM software write controller may be configured with reference to the data transmission width and write speed with appropriate speed determined in Table 1.
  • MSIZE is the number of beats that the DMA controller writes data to the FIFO once in the Burst mode, which represents the amount of data that the DMA controller writes to the FIFO once.
  • the method further includes: determining the instruction address information corresponding to the data unit sent by the DMA controller and the data amount of the data unit; controlling the first writing speed to be no greater than The sending speed of the cache, the second writing speed is controlled to be no greater than the sending speed, and the first writing speed is the speed at which the DMA controller writes the instruction address information corresponding to the data unit to the cache , the second writing speed is the speed at which the DMA controller writes the data unit to the cache, and the sending speed is the instruction address information corresponding to the data unit and the data unit being stored in the cache
  • the speed of sending to the PSRAM when the amount of data sent at the sending speed is equal to a preset amount of data, pull up the chip select signal, where the preset amount of data is based on the corresponding data unit The instruction address information and the threshold determined by the data unit.
  • the normal pull-up of the chip-select signal can be ensured, which can further improve the working stability of the software writing controller in a complex environment, and ensure the Software write controllers operate safely and efficiently in complex environments.
  • the write-back information sent by the DMA controller is received, and the write-back information It is used to indicate that the instruction address information corresponding to the data unit and the data unit have been sent, and the write-back information includes the instruction address information corresponding to the data unit and the write status information and/or location information of the data unit.
  • the status information is used to inform the SOC that the block writing is completed, and the location information is used to inform the position where the block is written.
  • the DMA controller After the DMA controller sends the block to the PSRAM and before sending the next block to be sent, the DMA controller performs a write-back operation, and the software layer receives the write-back information sent by the DMA controller.
  • the software layer The DMA controller consumes some software instructions by sending write-back information by receiving the DMA controller, that is, after the DMA controller sends a block, it takes about a few nanoseconds to perform the write-back operation, which can appropriately increase the block-to-block distance. time interval, further avoiding the sticking phenomenon, improving the security and stability of the software writing controller, and optimizing the working performance of the software writing controller.
  • the embodiment of the present application also provides an SOC chip 1300, as shown in FIG. 13, including:
  • the processor 1301 is configured to determine at least one data unit of data to be written into the PSRAM and instruction address information corresponding to the data unit according to the amount of data written in a single frame of the pseudo-static random access memory PSRAM, wherein the single frame
  • the amount of written data is the amount of data written within the time when the chip select signal corresponding to the PSRAM is at a low level; at least one block is generated according to the instruction address information corresponding to the data unit and the data unit, and the at least one block is generated.
  • a block forms a block chain list, and the block includes pointer information, instruction address information corresponding to the data unit and/or the data unit, and the pointer information is used to indicate the block chain list when the block chain table is transmitted. the next block to be sent of the block;
  • the DMA controller 1302 is configured to send the instruction address information corresponding to the data unit and the data unit to the PSRAM based on the block chain table.
  • the block further includes: configuration information, where the configuration information is used to instruct the DMA controller to transmit instructions required for the block.
  • the instruction includes at least one of a transmission direction instruction, a transmission channel instruction, a transmission speed instruction, and a transmission data width instruction for the DMA controller to transmit the block.
  • the software write controller of the software layer divides the data to be written into the PSRAM at one time and determines it into at least one data unit and the instruction address information corresponding to the data unit.
  • the instruction address information corresponding to the data unit and the data unit generate at least one block, and the at least one block forms a block chain list in an orderly manner through the pointer information.
  • the DMA controller with hardware circuit support sends data to the PSRAM in the form of a block chain list, which saves the software write controller consuming software instructions to instruct multiple times of splitting, configuring, and sending data, and effectively improves software write control.
  • the access efficiency of the device to the PSRAM is realized, and the high-speed writing of the PSRAM is realized.
  • the processor 1301 is further configured to: generate a block according to the instruction address information corresponding to the data unit and the data unit, and the block includes the configuration information, the pointer information, the data unit corresponding to the instruction address information and the data unit.
  • the processor 1301 is further configured to: generate a first block and a second block according to the instruction address information corresponding to the data unit and the data unit, where the first block includes the first block
  • the configuration information of the first block, the pointer information of the first block, the instruction address information corresponding to the data unit, the second block includes the configuration information of the second block, the pointer information of the second block, the data unit.
  • the processor 1301 is further configured to: determine the instruction address information corresponding to the data unit sent by the DMA controller and the data volume of the data unit, and when the data volume is greater than a preset data volume, pull The chip select signal is high, wherein the preset data amount is a threshold determined according to the instruction address information corresponding to the data unit and the data unit.
  • the preset data amount is equal to the instruction address information corresponding to the data unit and the data amount of the data unit.
  • the SOC chip 1400 includes:
  • a processor 1401 configured to perform the functions performed by the above-mentioned processor
  • the DMA controller 1402 is used to perform the function performed by the above-mentioned DMA controller; the DMA controller is used to write the instruction address information corresponding to the data unit and the data unit into the cache;
  • the cache 1403 is configured to send the instruction address information corresponding to the data unit and the data unit sent by the DMA controller to the PSRAM.
  • the processor 1401 is further configured to: control the first writing speed to be no greater than the sending speed of the cache, control the second writing speed to be no greater than the sending speed, and the first writing speed is all The speed at which the DMA controller writes the instruction address information corresponding to the data unit to the cache, the second write speed is the speed at which the DMA controller writes the data unit to the cache, and the second write speed is the speed at which the DMA controller writes the data unit to the cache.
  • the sending speed is the instruction address information corresponding to the data unit and the speed at which the data unit is sent from the cache to the PSRAM.
  • the processor 1401 is further configured to: after the DMA controller sends the data unit and the instruction address information corresponding to the data unit, receive the write-back information sent by the DMA controller, the The write-back information is used to indicate that the instruction address information corresponding to the data unit and the sending of the data unit are completed, and the write-back information includes the instruction address information corresponding to the data unit and the status information and/or position of the data unit information.
  • An embodiment of the present application further provides a software writing controller, which is used to execute the data writing method described in any one of the embodiments of the present application.
  • the software writing controller 1500 belongs to the software layer and executes software functions based on the hardware functions of the SOC chip, as shown in FIG. 15 , including:
  • a processing module 1501 configured to determine at least one data unit of data to be written into the PSRAM and instruction address information corresponding to the data unit according to the amount of data written in a single frame of the pseudo-static random access memory PSRAM, wherein the single frame
  • the amount of written data is the amount of data written within the time when the chip select signal corresponding to the PSRAM is at a low level; at least one block is generated according to the instruction address information corresponding to the data unit and the data unit, and the at least one block is generated.
  • a block forms a block chain list, and the block includes pointer information, instruction address information corresponding to the data unit and/or the data unit, and the pointer information is used to indicate the block chain list when the block chain table is transmitted. the next block to be sent of the block;
  • the writing module 1502 is configured to access the DMA controller through direct memory, and send the instruction address information corresponding to the data unit and the data unit to the PSRAM based on the block chain table.
  • the block further includes: configuration information, where the configuration information is used to instruct the DMA controller to transmit instructions required for the block.
  • the instruction includes at least one of a transmission direction instruction, a transmission channel instruction, a transmission speed instruction, and a transmission data width instruction for the DMA controller to transmit the block.
  • the processing module 1501 is configured to generate a block according to the instruction address information corresponding to the data unit and the data unit, and the block includes the configuration information, the pointer information, The instruction address information corresponding to the data unit and the data unit.
  • the processing module 1501 is configured to generate a first block and a second block according to the instruction address information corresponding to the data unit and the data unit, where the first block includes the The configuration information of the first block, the pointer information of the first block, the instruction address information corresponding to the data unit, the second block includes the configuration information of the second block, the Pointer information, the data unit.
  • the processing module 1501 is further configured to: determine the instruction address information corresponding to the data unit sent by the DMA controller and the data volume of the data unit, and when the data volume is equal to the preset data volume, pull The chip select signal is high, wherein the preset data amount is a threshold determined according to the instruction address information corresponding to the data unit and the data unit.
  • the preset data amount is equal to the instruction address information corresponding to the data unit and the data amount of the data unit.
  • the writing module 1502 is further configured to: write the instruction address information corresponding to the data unit and the data unit into a cache through the DMA, and write the data unit through the cache The instruction address information corresponding to the data unit and the data unit are sent to the PSRAM.
  • the processing module 1501 is further configured to: control the first writing speed to be no greater than the sending speed of the cache, control the second writing speed to be no greater than the sending speed, and the first writing speed is all The speed at which the DMA controller writes the instruction address information corresponding to the data unit to the cache, the second write speed is the speed at which the DMA controller writes the data unit to the cache, and the second write speed is the speed at which the DMA controller writes the data unit to the cache.
  • the sending speed is the instruction address information corresponding to the data unit and the speed at which the data unit is sent from the cache to the PSRAM.
  • the writing module 1502 is further configured to: determine the instruction address information corresponding to the data unit sent by the DMA controller and the data amount of the data unit; control the first writing speed not to be greater than the The sending speed of the cache, the second writing speed is controlled to be no greater than the sending speed, and the first writing speed is the speed at which the DMA controller writes the instruction address information corresponding to the data unit to the cache, so The second writing speed is the speed at which the DMA controller writes the data unit to the cache, and the sending speed is the instruction address information corresponding to the data unit and the data unit being sent to the cache by the cache.
  • the speed of the PSRAM when the amount of data sent at the transmission speed is equal to a preset amount of data, maintain the high-level state of the chip select signal, wherein the preset amount of data is based on the data
  • the writing module 1502 is further configured to: after the DMA controller sends the data unit and the instruction address information corresponding to the data unit, receive the write-back information sent by the DMA controller,
  • the write-back information is used to indicate that the instruction address information corresponding to the data unit and the sending of the data unit are completed, and the write-back information includes the instruction address information corresponding to the data unit and the status information of the data unit and/or location information.
  • Embodiments of the present application further provide a computer-readable storage medium, where computer-executable instructions are stored in the computer-readable storage medium, and when the computer-executable instructions are executed by a processor, are used to implement any possibility in the embodiments of the present application The data writing method described in the implementation manner.
  • the program can be stored in a computer-readable storage medium.
  • the storage medium includes: ROM, RAM, magnetic disk or optical disk and other media that can store program codes.
  • the software layer and the software writing controller described in the embodiments of the present application may be understood as computer-executable instructions in the computer-readable storage medium for executing the data writing method described in the embodiments of the present application.
  • the PSRAM write access process is performed using the write method described in this application, and the instruction address information corresponding to the data unit and the data unit are respectively configured as the first area. block and the second block, neither the first writing speed nor the second writing speed is greater than the sending speed, and the amount of data sent at the sending speed during transmission is equal to the preset
  • the chip select signal is pulled high, and after the instruction address information corresponding to the data unit and the data unit are sent through the DMA controller, the write-back information sent by the DMA controller is received.
  • the serial interface maximum operating frequency SCLK is 48MHz
  • the data payload is 128 bytes in four-wire mode.
  • the CS signal is pulled low for 6.5 ⁇ s-6.8 ⁇ s.
  • the time interval between blocks in the embodiment of the present application is 180ns, and the time interval is stable, not affected by system scheduling, and the ratio of valid time to invalid time is 6.8*1000:180, that is, 37.8: 1.
  • the work efficiency of the software write controller is greatly improved.
  • the software write controller access supports QSPI
  • the writing speed of the software writing controller provided by the embodiment of the present application reaches four times that of the ordinary software writing controller.
  • a write speed test and a stability test are performed on the PSRAM software write controller provided in the embodiment of the present application.
  • SCLK 48MHz
  • quad mode data payload is 128 bytes or 64 bytes.
  • the RAM is the random access memory in the main control chip. It can be seen from Table 2 that the PSRAM software writing controller provided by the embodiment of the present application greatly improves the writing speed, and achieves a working efficiency several times that of a common software writing controller.
  • Test conditions The data payload is 128 bytes or 64 bytes, and the number of writes and readbacks per round is 100,000 times.
  • the present application provides a data writing method, which is applied to an SOC/MCU chip connected to a PSRAM, which can effectively improve the writing speed of the software write controller accessing the PSRAM, realize high-speed writing to the PSRAM, and can Stable and cyclic work in complex environments, without adding an additional IP write controller in the SOC/MCU chip, through the software layer design, combined with the existing hardware circuits in the SOC/MCU chip, the software write controller can achieve IP controller performance.

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Abstract

一种数据写入的方法，包括：根据伪静态随机存储器PSRAM的单帧写入数据量确定拟写入所述PSRAM的数据的至少一个数据单元和所述数据单元对应的指令地址信息，其中，所述单帧写入数据量为所述PSRAM对应的片选信号的低电平的时间内写入的数据量；根据所述数据单元对应的指令地址信息和所述数据单元生成至少一个区块，所述至少一个区块形成区块链表，所述区块包括指针信息、所述数据单元对应的指令地址信息和/或所述数据单元，所述指针信息用于指示传输所述区块链表时所述区块的下一个待发送区块；通过DMA控制器，基于所述区块链表将所述数据单元对应的指令地址信息和所述数据单元发送给所述PSRAM。能够有效提升访问PSRAM的效率，实现对PSRAM的高速写入。

Description

数据写入方法、片上系统芯片及计算机可读存储介质 技术领域
本申请涉及芯片领域，并且更具体地，涉及一种数据写入方法、片上系统芯片及计算机可读存储介质。
背景技术
与动态随机存储器(Dynamic random access memory,DRAM)相比，伪静态随机存储器(Pseudo static random access memory,PSRAM)采用自刷新(Self refresh)机制，不需要额外的刷新电路即可定时刷新内部数据，避免数据丢失。
微控制器(Micro control unit,MCU)或片上系统(System on chip,SOC)类主控芯片访问PSRAM时，由于PSRAM的自刷新机制限制了片选信号CS(Chip select)的最长拉低时间，从而限制了PSRAM每次被访问的数据吞吐量，导致MCU/SOC在访问PSRAM时无法像访问闪存设备一样可以采用单次尽可能大的有效负载进行访问，极大地限制了对PSRAM的访问效率。
发明内容
本申请实施例提供了一种数据写入方法、片上系统SOC芯片及计算机可读存储介质，在不采用IP控制器的情况下，有效提升了对PSRAM的访问效率。
第一方面，提供一种数据写入的方法，其特征在于，包括：根据伪静态随机存储器PSRAM的单帧写入数据量确定拟写入所述PSRAM的数据的至少一个数据单元和所述数据单元对应的指令地址信息，其中，所述单帧写入数据量为所述PSRAM对应的片选信号的低电平的时间内写入的数据量；根据所述数据单元对应的指令地址信息和所述数据单元生成至少一个区块，所述至少一个区块形成区块链表，所述区块包括指针信息、所述数据单元对应的指令地址信息和/或所述数据单元，所述指针信息用于指示传输所述区块链表时所述区块的下一个待发送区块；通过直接存储器访问DMA控制器，基于所述区块链表将所述数据单元对应的指令地址信息和所述数据单元发送给所述PSRAM。
本申请实施例在软件写PSRAM的过程中引入具有硬件电路支持的 DMA控制器，由软件层通过软件指令将拟发送数据一次性切分并确定成至少一个数据单元和所述数据单元对应的指令地址信息，所述数据单元对应的指令地址信息与所述数据单元生成至少一个区块，每个区块包括指针信息、所述数据单元对应的指令地址信息和/或所述数据单元，所述至少一个区块通过指针信息有序地组成区块链表，通过DMA控制器以区块链表的形式将数据发送给PSRAM，节省了软件层消耗软件指令指示多次切分、配置、发送数据的时间，有效提升了对PSRAM的访问效率，实现了对PSRAM的高速写入。
应理解，若所述数据单元对应的指令地址信息与所述数据单元分别生成不同区块进行传输，在区块链表中，包含所述数据单元对应的指令地址信息的区块的下一个待发送区块即为包含所述数据单元的区块。
在一种可能的实施方式中，所述区块还包括：配置信息，所述配置信息用于指示所述DMA控制器传输所述区块所需的指令。
本申请实施例中，每一个区块都具有与其对应的配置信息，也就是说，每一个区块的配置信息可以不同，DMA控制器能够通过不同的配置传输所述区块，提高了访问PSRAM的灵活度与自由度。
在一种可能的实施方式中，所述指令包括所述DMA控制器传输所述区块的传输方向指令、传输通道指令、传输速度指令、传输数据宽度指令中的至少一个。
本申请实施例中，通过配置信息配置传输每个区块所需的多个传输指令，DMA控制器能够以不同的传输速度传输不同数据大小、不同传输方向、不同传输途径的数据，进一步提高数据传输的灵活性。
在一种可能的实施方式中，所述根据所述数据单元对应的指令地址信息和所述数据单元生成至少一个区块，包括：根据所述数据单元对应的指令地址信息和所述数据单元生成一个区块，所述区块包括所述配置信息、所述指针信息、所述数据单元对应的指令地址信息和所述数据单元。
应理解，软件层将数据处理成区块后可将其存储于内存中与所述区块的数据格式匹配的缓存空间中，也就是说，可以在内存中开辟与所述数据单元对应的指令地址信息和所述数据单元匹配的新的缓存空间，在数据传输之前存放所述数据单元对应的指令地址信息和所述数据单元。
在一种可能的实施方式中，所述根据所述数据单元对应的指令地址信息 和所述数据单元生成至少一个区块包括：所述根据所述数据单元对应的指令地址信息和所述数据单元生成第一区块和第二区块，所述第一区块包括所述第一区块的配置信息、所述第一区块的指针信息、所述数据单元对应的指令地址信息，所述第二区块包括所述第二区块的配置信息、所述第二区块的指针信息、所述数据单元。
本申请实施例将数据单元对应的指令地址信息和数据单元分别配置成第一区块和第二区块，使得DMA控制器在发送数据给PSRAM的过程中，不需要将具有特殊数据宽度的区块存入额外开辟的新的缓存空间，能直接将区块写入MCU/SOC内存现有的缓存空间中，节省了内存以及从新的缓存空间搬运数据的软件指令，进一步提高了对PSRAM的访问效率。
在一种可能的实施方式中，所述方法还包括：确定所述DMA控制器发送的所述数据单元对应的指令地址信息和所述数据单元的数据量，当所述数据量等于预设数据量时，拉高所述片选信号，其中，所述预设数据量为根据所述数据单元对应的指令地址信息和所述数据单元确定的阈值。
本申请实施例通过控制片选信号在传输的数据量未达阈值前片选信号不会拉高，避免数据传输还未完成片选信号意外被拉高的情况，保证数据的正常传输，提高访问程序的稳定性。
在一种可能的实施方式中，所述预设数据量与所述数据单元对应的指令地址信息和所述数据单元的数据量相等。
本申请实施例中，控制在数据单元对应的指令地址信息和数据单元发送完成前片选信号不会被拉高，使得数据能够正常传输。在数据单元对应的指令地址信息和数据单元分别被配置成第一区块与第二区块的情况下，能够保证片选信号在第二区块发送完成后被拉高，一方面，避免了在区块发送过程中，第一区块发送完成后片选信号被拉高导致第一区块和第二区块不能被连续发送，数据单元对应的指令地址信息与数据单元不能被连续写入，最终导致数据写入错误的问题，另一方面，最大程度利用片选信号的拉低时间，提高数据传输的效率，从而提升对PSRAM的访问效率。
在一种可能的实施方式中，所述通过直接存储器访问DMA控制器，基于所述区块链表将所述数据单元对应的指令地址信息和所述数据单元发送给所述PSRAM包括：通过所述DMA控制器将所述数据单元对应的指令地址信息和所述数据单元写入缓存，通过所述缓存将所述数据单元对应的指令 地址信息和所述数据单元发给所述PSRAM。
本申请实施例通过在DMA控制器与PSRAM之间设置缓存，能够控制数据传输的速度，避免数据传输速度过快导致粘包，即避免在所述区块未发送完成时所述下一个待发送区块就进入了缓存，所述区块发送完成后片选信号没有被拉高造成电路异常的情况，进一步保证了数据正常传输，提升访问PSRAM时程序的稳定性以及在复杂环境下运行的可靠性。
在一种可能的实施方式中，所述方法还包括：控制第一写入速度不大于所述缓存的发送速度，控制第二写入速度不大于所述发送速度，所述第一写入速度为所述DMA控制器向所述缓存写入所述数据单元对应的指令地址信息的速度，所述第二写入速度为所述DMA控制器向所述缓存写入所述数据单元的速度，所述发送速度为所述数据单元对应的指令地址信息和所述数据单元被所述缓存发送给所述PSRAM的速度。
应理解，所述第一速度与所述第二速度可以相等，即当所述数据单元对应的指令地址信息和所述数据单元生成一个区块时，所述第一速度与所述第二速度相等且均小于所述发送速度，所述数据单元对应的指令地址信息与所述数据单元先后被发送至缓存。当所述数据单元对应的指令地址信息和所述数据单元分别生成所述第一区块和所诉第二区块时，所述第一速度与所述第二速度均小于所述发送速度，所述数据单元对应的指令地址信息与所述数据单元分别以所述第一速度和所述第二速度先后被发送至缓存。
本申请实施例通过控制区块被写入缓存的速度不大于区块中的信息和/或数据被发送出缓存发送速度，可以控制缓存中区块的填充速度，有效避免写入速度过快产生的粘包现象。例如，在第一区块中的所述数据单元对应的指令地址信息尚未从缓存中被发出时，第二区块已经被写入缓存，粘包将导致在第一区块中的信息发送完成后片选信号无法正常释放，进而导致电路工作异常。通过控制写入速度不大于发送速度，能够保证所述区块传输完成后所述下一个待发送区块才进入缓存，保证所述区块传输完成后片选信号能够被拉高，有效避免数据粘包，进一步提升访问PSRAM的效率。
在一种可能的实施方式中，所述方法还包括：确定所述DMA控制器发送的所述数据单元对应的指令地址信息和所述数据单元的数据量；控制第一写入速度不大于所述缓存的发送速度，控制第二写入速度不大于所述发送速度，所述第一写入速度为所述DMA控制器向所述缓存写入所述数据单元对 应的指令地址信息的速度，所述第二写入速度为所述DMA控制器向所述缓存写入所述数据单元的速度，所述发送速度为所述数据单元对应的指令地址信息和所述数据单元被所述缓存发送给所述PSRAM的速度；当以所述发送速度发送的所述数据量等于预设数据量时，拉高所述片选信号，其中，所述预设数据量为根据所述数据单元对应的指令地址信息和所述数据单元确定的阈值。
本申请实施例通过控制区块在缓存中的填充速度以及控制片选信号的拉高条件，保证片选信号的正常拉高，能够进一步提升复杂环境下对PSRAM进行访问时程序的稳定性，保证访问程序在复杂环境下安全高效地运行。
在一种可能的实施方式中，所述方法还包括：在通过所述DMA控制器发送所述数据单元对应的指令地址信息和所述数据单元后，接收所述DMA控制器发送的回写信息，所述回写信息用于指示所述数据单元对应的指令地址信息和所述数据单元发送完成，所述回写信息包括所述数据单元对应的指令地址信息和所述数据单元的状态信息和/或位置信息。
本申请实施例中通过接收DMA控制器发送的回写信息，使得DMA控制器在写入所述区块后，写入所述下一个待发送区块前，执行回写操作，软件层通过接收所述DMA控制器发送的回写信息能够消耗一些软件指令，增大传输区块链表的过程中所述区块与所述下一个待发送区块之间的时间间隔，避免数据粘包现象，进一步提高了访问PSRAM的安全性与稳定性。
第二方面，提供一种片上系统SOC芯片，其特征在于，包括：
处理器，用于根据伪静态随机存储器PSRAM的单帧写入数据量确定拟写入所述PSRAM的数据的至少一个数据单元和所述数据单元对应的指令地址信息，其中，所述单帧写入数据量为所述PSRAM对应的片选信号的低电平的时间内写入的数据量；根据所述数据单元对应的指令地址信息和所述数据单元生成至少一个区块，所述至少一个区块形成区块链表，所述区块包括指针信息、所述数据单元对应的指令地址信息和/或所述数据单元，所述指针信息用于指示传输所述区块链表时所述区块的下一个待发送区块；
DMA控制器，用于基于所述区块链表将所述数据单元对应的指令地址信息和所述数据单元发送给所述PSRAM。
在一种可能的实施方式中，所述区块还包括：配置信息，所述配置信息 用于指示所述DMA控制器传输所述区块所需的指令。
在一种可能的实施方式中，所述指令包括所述DMA控制器传输所述区块的传输方向指令、传输通道指令、传输速度指令、传输数据宽度指令中的至少一个。
在一种可能的实施方式中，所述处理器用于：根据所述数据单元对应的指令地址信息和所述数据单元生成一个区块，所述区块包括所述配置信息、所述指针信息、所述数据单元对应的所述指令地址信息和所述数据单元。
在一种可能的实施方式中，所述处理器用于：根据所述数据单元对应的指令地址信息和所述数据单元生成第一区块和第二区块，所述第一区块包括所述第一区块的配置信息、所述第一区块的指针信息、所述数据单元对应的指令地址信息，所述第二区块包括所述第二区块的配置信息、所述第二区块的指针信息、所述数据单元。
在一种可能的实施方式中，所述处理器还用于：确定所述DMA控制器发送的所述数据单元对应的指令地址信息和所述数据单元的数据量，当所述数据量等于预设数据量时，拉高所述片选信号，其中，所述预设数据量为根据所述数据单元对应的指令地址信息和所述数据单元确定的阈值。
在一种可能的实施方式中，所述预设数据量与所述数据单元对应的指令地址信息和所述数据单元的数据量相等。
在一种可能的实施方式中，所述芯片还包括：
缓存；
所述DMA控制器用于将所述数据单元对应的指令地址信息和所述数据单元写入所述缓存，所述缓存用于将所述DMA控制器写入的所述数据单元对应的指令地址信息和所述数据单元发送给所述PSRAM。
在一种可能的实施方式中，所述处理器还用于：控制第一写入速度不大于所述缓存的发送速度，控制第二写入速度不大于所述发送速度，所述第一写入速度为所述DMA控制器向所述缓存写入所述数据单元对应的指令地址信息的速度，所述第二写入速度为所述DMA控制器向所述缓存写入所述数据单元的速度，所述发送速度为所述数据单元对应的指令地址信息和所述数据单元被所述缓存发送给所述PSRAM的速度。
在一种可能的实施方式中，所述芯片还包括：缓存；所述处理器还用于：确定所述DMA控制器发送的所述数据单元对应的指令地址信息和所述数据 单元的数据量；控制第一写入速度不大于所述缓存的发送速度，控制第二写入速度不大于所述发送速度，所述第一写入速度为所述DMA控制器向所述缓存写入所述数据单元对应的指令地址信息的速度，所述第二写入速度为所述DMA控制器向所述缓存写入所述数据单元的速度，所述发送速度为所述数据单元对应的指令地址信息和所述数据单元被所述缓存发送给所述PSRAM的速度；当以所述发送速度发送的所述数据量等于预设数据量时，维持所述片选信号的高电平状态，其中，所述预设数据量为根据所述数据单元对应的指令地址信息和所述数据单元确定的阈值。
在一种可能的实施方式中，所述处理器还用于：在通过所述DMA控制器发送所述数据单元对应的指令地址信息和所述数据单元后，接收所述DMA控制器发送的回写信息，所述回写信息用于指示所述数据单元对应的指令地址信息和所述数据单元发送完成，所述回写信息包括所述数据单元对应的指令地址信息和所述数据单元的状态信息和/或位置信息。
第三方面，提供一种计算机可读存储介质，所述计算机可读存储介质中存储有计算机执行指令，所述计算机执行指令被处理器执行时用于实现第一方面中任一种可能的实现方式所述的数据写入的方法。
综上，本申请实施例所述的方案，基于处理器将拟发送的数据确定为区块链表，通过DMA控制器发送给PSRAM，极大地节省了软件层重复处理和配置拟发送数据的时间与软件指令，提升了对PSRAM设备的写入效率，能够使其达到IP控制器级别。
附图说明
图1是本申请实施例的一种主控芯片与外接设备的架构示意图。
图2是本申请实施例的一个PSRAM访问时序示意图。
图3是本申请实施例的一个软件写控制器写入数据的流程图。
图4是本申请实施例的一个软件写控制器写入数据的时序帧示意图。
图5是本申请实施例的一个软件写控制器写入数据的逻辑示意图。
图6是本申请实施例的一种数据写入的方法的流程图。
图7是本申请实施例的时序帧示意图。
图8是本申请实施例的一种区块链表示意图。
图9是本申请实施例的又一种区块链表示意图。
图10是本申请实施例的另一种区块链表示意图。
图11是本申请实施例一种区块与片选信号的关系的示意图。
图12是本申请实施例的一种先进先出缓存示意图。
图13是本申请实施例的一种SOC芯片的示意图。
图14是本申请实施例的另一种SOC芯片的示意图。
图15是本申请实施例的一种软件写控制器的示意图。
图16是本申请实施例的一个软件控制器写入数据的又一逻辑示意图。
具体实施方式
下面将结合附图，对本申请的技术方案进行清楚、完整地描述。应当理解，此处所描述的具体实施例仅用以解释本申请，并不用于限定本申请。
在以下描述中，列出了许多特定细节，诸如特定类型的处理器核系统配置、特定硬件结构、特定架构和微架构细节、特定寄存器配置、特定指令类型、特定系统组件、特定测量/高度、特定处理器流水线级和操作等等的示例，以便提供本申请的透彻理解。然而，将对本领域技术人员明显的是无需采用这些特定细节来实践本申请。在其他情况下，未详细描述公知的组件或方法，诸如特定或替代处理器架构、用于所描述的算法的特定逻辑电路/代码、特定固件代码、特定互连操作、特定逻辑配置、特定制造技术和材料、特定编译器实现方式、特定算法代码表达、特定断电和门控技术/逻辑以及计算机系统的其他特定操作细节，以便避免不必要地混淆本申请。
随着计算机系统架构的发展，诸如中央处理单元(Central processing unit,CPU)、存储器控制器、输入/输出(I/O)中枢等系统组件不再以分立的形式外部互连，而是集成至微控制器(Micro control unit,MCU)和片上系统(System on chip,SOC)类的主控芯片上，MCU/SOC通过串行接口或并行接口连接外围设备进行访问。
图1是本申请实施例的一种主控芯片与外接设备的架构示意图。主控芯片100由软件层101与硬件层102构成，软件层101可通过软件指令控制硬件层102的各个硬件实现不同的功能，例如，可以通过处理器控制主控芯片进行各种读写操作。其中，软件层101包括实现不同功能的各类控制器、逻辑电路等，硬件层102包括至少一个微处理器(Micro processing unit,MPU)或数字信号处理器(Digital signal processor,DSP)、存储器、硬件电路、管理不同 物理接口的接口管理模块、用于转换数字信号与模拟信号的转换器、用于提供时钟信号(Clock signal,CLK)的振荡器等，其中存储器可以是一个或多个只读存储器(Read-only memory,ROM)、随机存储器(Random access memory,RAM)、闪存等。MCU/SOC等主控芯片可通过软件层与硬件层的同步设计，实现多功能的集成。另外，由于存储器的存储空间有限，主控芯片100可通过硬件层的串/并行接口外接多个存储设备103、104等，这些外接存储设备可以是静态随机存储器(Static random access memory,SRAM)、动态随机存储器(Dynamic random access memory,DRAM)或伪静态随机存储器(Pseudo static random access memory,PSRAM)等。
PSRAM是一种采用DRAM的工艺技术，实现类似于SRAM的功能效果的存储器，具有接口简单、存储容量大等优点。在目前的智能穿戴市场，PSRAM已成为扩展MCU/SOC的RAM存储空间及资源数据缓存的理想选择，是MCU/SOC的常见外接设备之一。
传统PSRAM采用并行接口控制，MCU/SOC等主控芯片访问PSRAM时需消耗较多的管脚资源，近年来一些PSRAM厂商推出了支持单线串行外围设备接口(Serial peripheral interface,SPI)、四线串行外围设备接口(Quad serial peripheral interface,QSPI)的串行PSRAM，进一步扩展了PSRAM的应用前景。
PSRAM采用自刷新机制，不像DRAM设备需要额外的刷新电路来控制内存单元定期刷新数据，PSRAM内部会进行数据的定时刷新，避免数据丢失。这也导致MCU/SOC在访问PSRAM的访问周期中，片选信号CS(Chip select)的最长拉低时间不能超过PSRAM的自刷新时间，超过CS信号的最长拉低时间而不释放CS信号会造成PSRAM自刷新电路工作异常，从而导致访问数据出错。故MCU/SOC在访问PSRAM时无法像直接访问闪存一样，单次采用尽可能大的有效负载进行访问，而是受限于CS信号的最长拉低时间，通过多次访问完成数据传输，极大地限制了MCU/SOC对PSRAM的访问效率。
MCU/SOC等主控芯片在向PSRAM等外接存储设备中写入数据时由软件层的写控制器控制硬件层来实现。图2是本申请实施例的一个PSRAM访问时序示意图，所述PSRAM支持SPI、QSPI接口。MCU/SOC对PSRAM的一个写入访问周期从CS信号拉低开始，到CS信号拉高结束，在此期间 MCU/SOC的写控制器控制硬件层以发送时序帧的方式将数据写入PSRAM。向PSRAM发送的一个时序帧通常由3部分组成：1个字节的指令(Instruction)部分、3个字节的地址(Address)部分以及若干字节的数据(Data)部分。其中，1个字节的指令部分与3个字节的地址部分为PSRAM写入访问时的必要开销，将时序帧写入PSRAM的时间消耗不能超过CS信号的最长拉低时间，否则PSRAM的自刷新机制将会导致访问错误。
目前，实现MCU/SOC向PSRAM中写入数据的写控制器有两类：一类是知识产权IP写控制器，可直接被集成至MCU/SOC上，除了具备通用的写控制器功能外，还具有专门针对PSRAM对应的最长CS信号拉低时间而设计的控制电路，能够在IP写控制器内部自动对数据进行切分、构建时序帧、以及发送，无需浪费软件层额外的软件指令，软件层只需通过IP写控制器暴露的MCU/SOC内存中的寄存器进行相关配置即可，工作效率较高，但需要额外研发设计或购买授权，且成本高昂。
另一类是软件写控制器，可基于MCU/SOC上现有的结构和功能，通过软件层设计，以软件控制的方式根据最长CS信号拉低时间降低每次写入的数据量，多次切分、配置以及发送数据，不需要在MCU/SOC中增加额外的IP写控制器，基于现有的数据写入方案，例如，闪存设备的数据写入方案，就能实现对PSRAM的数据写入。具体来说，图3是本申请实施例的一个软件写控制器写入数据的流程图，所述流程由MCU/SOC的软件写控制器执行：
S301，根据PSRAM的访问时序，进行寄存器配置。
具体地，PSRAM的访问时序在PSRAM出厂时会由生产商提供，寄存器配置包括指令相关、地址相关、时序相关、数据相关的寄存器配置。
示例性地，寄存器配置至少包括：在指令寄存器中设置访问指令、在指令宽度寄存器中设置访问指令的宽度、在指令模式位寄存器中设置访问指令的发送模式、在地址宽度寄存器中设置访问地址的宽度、在地址模式位寄存器中设置访问地址的发送模式、在时序(Dummy)数量寄存器中设置时钟信号的数量、在数据模式寄存器中设置数据的发送模式。其中发送模式有单线模式或多线模式。
S302，根据访问时序，构建时序帧。
具体地，时序帧包含指令、地址、时序以及一定长度的数据，其中数据长度由软件层根据最长CS信号拉低时间计算得到。
S303，将构建好的时序帧发送给PSRAM。
S304，判断拟发送数据是否发送完成。若是，执行S305；若否，执行S301。
S305，结束写入操作。
目前，业内主流的PSRAM供应商生产的PSRAM的最长CS信号拉低时间均以8μs作为标准，时序帧与时序帧之间采用for/while逻辑连接，发送时序帧所占用的时序资源为有效写入时间，每次发送时序帧之间的时间间隔为T。图4是本申请实施例的一个软件写控制器写入数据的时序帧示意图。但当需要写入的数据量较大时，软件写控制器实现PSRAM写入访问的方法需要通过软件指令切分数据、构建时序帧以及发送时序帧，加上系统调度等软件指令的消耗，与IP写控制器相比，会浪费较多的时间，使得时间间隔T过长，一般在几十微秒的级别，相较于有效写入时间(8μs)，时序资源浪费占比过大，严重影响PSRAM的访问速率。
示例性地，如图5所示，使用for/while逻辑执行PSRAM写入流程，在串行接口最大工作频率SCLK为48MHz、采用四线模式的情况下，数据有效负载为128字节。在逻辑控制器中运行上述访问流程，CS信号拉低时间为6.5μs-6.8μs，即能够传输数据的有效时间为6.5μs-6.8μs；时序帧与时序帧之间的时间间隔约为70μs，即等待数据被切分、被构建成时序帧的时间为70μs，且时间间隔极不稳定，当有系统调度时，将远大于70μs，有效时间与无效时间的比值为6.8μs:70μs，即0.097:1，时序资源浪费严重。
有鉴于此，本申请基于MCU/SOC主控芯片已有的功能与结构，在不额外设置IP控制器的情况下，设计了一种数据写入方法，应用于MCU/SOC芯片，能够减少时间间隔T，使软件写控制器的对PSRAM的访问效率达到IP写控制器的级别。
本申请实施例以支持QSPI接口的SOC芯片作为示例，应理解，本申请实施例所述的方法同样也适用于支持SPI、QSPI接口的其他MCU/SOC芯片。
本申请实施例所述“拉高片选信号”即“释放片选信号”，拉高片选信号后将维持片选信号高电平状态直至拉低片选信号，“拉低片选信号”后将维持片选信号低电平状态直至拉高片选信号。
图6是本申请实施例的一种数据写入方法的流程图。
S601，根据PSRAM的单帧写入数据量，确定拟写入所述PSRAM的数据的至少一个数据单元和所述数据单元对应的指令地址信息，其中，所述单帧写入数据量为所述PSRAM对应的片选信号的低电平的时间内写入的数据量；
S602，根据所述数据单元对应的指令地址信息和所述数据单元生成至少一个区块，所述至少一个区块形成区块链表；
S603，通过DMA控制器基于所述区块链表发送所述数据单元对应的指令地址信息及所述数据单元。
在执行S601之前，软件写控制器根据CS信号拉低时间、串行接口的工作频率、串行接口的工作模式确定PSRAM单帧的写入数据量。串行接口的最大工作频率与硬件的晶振频率有关，串行接口的工作模式用于确定每个时钟信号传输的数据比特位数。单帧写入数据量为所述PSRAM对应的片选信号的低电平的时间内写入的数据量，也就是PSRAM在CS信号被拉低的时间内能够被写入的最大数据量。CS信号被拉低的时间即是SOC维持CS信号所需的低电平的时间。
作为一种可能的实现方式，PSRAM单帧的写入数据量可用以下算法确定：
#define PLAYLOAD(SCLK,MODE_BITS,t_CEM)＝(SCLK/1000000u)*(MODE_BITS/8)*t_CEM
其中，PLAYLOAD为PSRAM一帧写入数据量，SCLK为串行接口的最大工作频率，MODE_BITS为某串行接口的工作模式下每个时钟信号传输的数据比特位数，t_CEM为CS信号拉低时间，1000000u即1000000μs，1/1000000u即1MHz。例如，一种SOC的QSPI的工作频率为48MHz，采用4线工作模式MODE_BITS为4，典型的CS信号拉低时间为8μs，则理论上此PSRAM单帧的写入数据量为48*(4/8)*8，即192字节。应理解，实际应用时，考虑到数据的安全冗余量，会采用小于192字节的实际写入数据量。
应理解，上述用于确定PSRAM单帧的写入数据量的代码只是其中一种确定方式，任何上述代码的变形，或能够利用最长CS信号拉低时间、串行接口的最大工作频率、串行接口的工作模式确定PSRAM单帧的写入数据量的代码或代码的组合均可替代上述代码。
作为一种可能的实现方式，PSRAM单帧的写入数据量也可用以下代码确定：
#define CLK_FREQ_1MHz 1000000u
#define PSRAM_SAFE_tCEM_US 8u/*Typical tCEM is 8us*/
#define QSPI_LANES 4u/*Quad mode:4lanes*/
#define PSRAM_MAX_PAYLOAD(qclk)
((PSRAM_SAFE_tCEM_US*qclk*QSPI_LANES)/(8u*CLK_FREQ_1MHz))/*qclk unit is MHz*/
示例性地，在S601中，如图7所示，软件写控制器根据伪静态随机存储器PSRAM的单帧写入数据量确定拟写入所述PSRAM数据的至少一个数据单元和所述数据单元对应的指令地址信息包括：
将具有一定宽度的拟发送数据分为n个数据部分，每个数据部分的数据量为PSRAM单帧的写入数据量，n个数据部分被配置为n个数据单元和其对应的指令地址信息，其中指令地址信息包括指令信息、地址信息。保持n个时序帧信息的指令信息相同，数据宽度为1个字节；更新n个时序帧信息的地址信息，数据宽度为3个字节。具体来说，地址信息包括起始地址信息以及缓冲区地址信息，更新地址信息即更新n个时序帧的地址偏移以及缓冲区偏移。
具体地，在S602中，在确定数据单元及其对应的指令地址信息后，软件写控制器生成至少一个区块，所述至少一个区块形成区块链表，所述区块包括指针信息、所述数据单元对应的指令地址信息和/或所述数据单元，所述指针信息用于指示传输所述区块链表时所述区块的下一个待发送区块。
直接内存访问(Direct memory access,DMA)是外部设备不通过中央系统处理器(Central processing unit,CPU)而直接与系统内存交换数据的接口技术，DMA控制器直接通过总线进行数据的收发，区块链表是MCU/SOC设备中DMA控制器具有的功能之一。如图8所示，在区块链表中数据以区块为单位被传输，图中箭头所示为信息的发送顺序。所述指针信息可链接具有先后顺序的多个区块使得DMA控制器按链接顺序依次发送多个区块。DMA控制器在所述区块数据发送完成后，根据所述区块的指针信息自动加载区块链表中所述区块的下一个待发送区块的数据并发送，直到链表指针信息为空。
可选地，区块包括配置信息、指针信息、所述数据单元对应的指令地址 信息和/或所述数据单元，所述配置信息用于指示所述DMA控制器传输所述区块所需的指令。
本实施例中，每一个区块都具有配置信息，DMA控制器能够通过不同的配置传输区块，提高了数据传输的灵活度与自由度。
可选地，所述配置信息包括所述DMA控制器传输所述区块的传输方向指令、传输通道指令、传输速度指令、传输数据宽度指令中的至少一个。
本实施例中，通过配置信息配置传输每个区块所需的多个传输指令，DMA控制器能够以不同的传输速度传输不同数据大小、不同传输方向、不同传输途径的数据，进一步提高软件写控制器数据传输的灵活性。
可选地，所述配置信息还包括：DMA个数、总线突发(Burst)行为、缓冲区地址、写入目标地址、缓冲区数据宽度等。
本实施例中，配置DMA个数以及总线Burst行为使得软件写控制器能够根据拟发送数据的情况选择多个DMA控制器传输数据，决定每个DMA传输的次数，配置缓冲区地址、写入目标地址以及缓冲区数据宽度使得软件写控制器能够将区块发送至不同的缓存区域中，动态调整数据传输的路线，进一步提升数据传输的灵活性。
在S603中，软件写控制器通过DMA控制器基于区块链表将所述数据单元对应的指令地址信息和所述数据单元发送给所述PSRAM。
与直接由软件写控制器发送时序帧相比，由软件层将拟发送数据配置成区块，由DMA控制器将MCU/SOC内存中的拟发送数据以区块的形式进行链式发送，由于DMA控制器根据区块链表发送区块基于硬件电路进行，不需要过多的软件指令，数据传输过程中，发送每个区块之间的时间间隔远小于发送每个时序帧之间的时间间隔T。
本申请实施例在软件写PSRAM的过程中引入具有硬件电路支持的DMA控制器，由软件写控制器基于处理器将拟发送数据一次性切分并确定成至少一个数据单元和所述数据单元对应的指令地址信息，所述数据单元对应的指令地址信息与所述数据单元生成至少一个区块，每个区块包括指针信息、所述数据单元对应的指令地址信息和/或所述数据单元，所述至少一个区块通过指针信息有序地组成区块链表，通过DMA控制器以区块链表的形式将数据发送给PSRAM，节省了软件写控制器消耗软件指令指示多次切分、配置、发送数据的时间，有效提升了软件写控制器对PSRAM的访问效率， 实现了PSRAM的高速写入。
应理解，若所述数据单元对应的指令地址信息与所述数据单元分别生成不同区块进行传输，在区块链表中，包含所述数据单元对应的指令地址信息的区块的下一个待发送区块即为包含所述数据单元的区块，DMA控制器依次将包含所述数据单元对应的指令地址信息的区块、包含所述数据单元的区块发送给PSRAM。
可选地，在一个实施例中，如图9所示，软件写控制器根据所述数据单元对应的指令地址信息和所述数据单元生成一个区块，所述区块包括所述配置信息、所述指针信息、所述数据单元对应的所述指令地址信息和所述数据单元。
本实施例中，通过将数据单元对应的所述指令地址信息和数据单元配置成区块，使得DMA控制器能够以区块链表形式传输区块，不需要软件层消耗软件指令发送数据，提升了软件写控制器的工作效率。
应理解，软件写控制器将数据处理成区块后，可以将区块存放于内存中，也就是说，可以在内存中开辟与所述数据单元对应的指令地址信息和所述数据单元匹配的新的缓存空间，在数据传输之前存储所述数据单元对应的指令地址信息和所述数据单元。
具体地，由于4字节的指令地址信息是向PSRAM中写入数据的必要开销，考虑到地址信息的连续性以及数据宽度，在配置好区块信息后，在MCU/SOC内存中采用新的缓存空间存放拟发送的数据，新的缓存空间的数据宽度为数据单元的字节数与数据单元对应的指令地址信息的字节数之和。
可选地，在一个实施例中，如图10所示，是本申请实施例的另一种区块链表示意图。软件写控制器根据所述数据单元对应的指令地址信息和所述数据单元生成第一区块和第二区块，所述第一区块包括所述第一区块的配置信息、所述数据单元对应的指令地址信息、所述第一区块的指针信息，第二区块包括所述第二区块的配置信息、所述数据单元、所述第二区块的指针信息。即软件写控制器在生成数据单元及其对应的指令地址信息相应的区块时，将一个指令地址信息与相应的数据分别生成为第一区块和第二区块。
将指令地址信息与相应的数据分别配置为对应的第一区块和第二区块，能将数据直接存入MCU/SOC内存已有的缓存空间中，不需要因区块具有特殊的数据宽度而为其开辟新的缓存空间，节省了内存空间以及从新的缓存空 间搬运数据的软件指令，能够灵活构建区块链表，降低了软件指令的复杂度，提高了软件写控制器的工作效率。
图11是本申请实施例一种区块与片选信号的关系的示意图，展示了利用DMA控制器向PSRAM发送数据的一种理想状态，即数据单元对应的指令地址信息和所述数据单元开始发送前，CS信号拉低，数据单元对应的指令地址信息和所述数据单元发送完成后，CS信号拉高。即在第一区块发送之前CS信号拉低，在第二区块发送完成后CS信号拉高。
在软件的实际运行过程中，存在其他外接设备占用总线，致使DMA控制器不能及时将数据单元对应的指令地址信息和数据单元发送至缓存的情况，特别是在数据单元对应的指令地址信息和数据单元被分别配置成第一区块和第二区块时，可能出现缓存发送完第一区块后意外释放CS信号导致待发送的第二区块中的数据缺乏指令地址信息而不能被写入PSRAM的情况，造成数据错误。
可选地，在一个实施例中，所述方法还包括，确定所述DMA控制器发送的所述数据单元对应的指令地址信息和所述数据单元的数据量，当所述数据量等于预设数据量时，拉高所述片选信号，其中，所述预设数据量为根据所述数据单元对应的指令地址信息和所述数据单元确定的阈值。
为了保证DMA控制器向PSRAM发送数据时，在区块发送完成前，CS信号不被释放，一直维持低电平，可在QSPI接口处设置计数器，用于对从QSPI流出的数据量计数。当计数器的计数值对应的数据量未达到预设数据量时，不拉高CS信号，CS信号一直维持低电平的拉低状态，数据从MCU/SOC被写入PSRAM；当计数器的计数值对应的数据量达到预设数据量时，拉高CS信号，不再维持低电平，一个周期的写入操作结束，计数器复位重新开始计数。
本申请实施例通过控制片选信号在传输的数据量未达阈值前片选信号不会拉高，避免数据传输还未完成片选信号意外被拉高的情况，保证数据的正常传输，提高软件写控制器运行的稳定性。
可选地，在一个实施例中，所述预设数据量与所述数据单元对应的指令地址信息和所述数据单元的数据量相等。
具体地，当数据写入开启后，每从QSPI向PSRAM流出一拍数据，计数器数值增加1，当计数器计数值未达到预设计数值时，片选信号一直维持 低电平状态，当计数器计数值等于预设阈值时，片选信号被释放拉高，不再维持低电平，一个周期的写入操作结束，计数器复位重新开始计数。
具体地，计数器的预设计数值以拍为单位，通过数据单元对应的指令地址信息和数据单元的数据量配置得到，预设计数值对应的数据量为预设数据量。即计数器的预设计数值所对应的数据量与数据单元对应的指令地址信息和数据单元的数据量相等。当总线数据宽度HSIZE不同时，计数器拍数对应的数据量也不同。例如：总线宽度为8比特(bit)时，1拍数据的单位为字节；总线宽度为16bit时，1拍数据的单位为半字；总线宽度为32bit时，1拍数据的单位为字。
本实施例中，通过在QSPI接口处设置计数器，能够保证在数据单元对应的指令地址信息和数据单元发送完成前，CS信号不会被拉高，从而使得数据能够正常传输。在第一区块与第二区块的情况下，能够保证CS信号在第二区块发送完成后才会被拉高，一方面，避免了区块发送过程中第一区块发送后片选信号可能被拉高，导致数据单元对应的指令地址信息与数据单元不能被连续写入，最终导致数据写入错误的问题，另一方面，最大程度利用片选信号的拉低时间，提高了区块传输的安全性和稳定性，有效提升了PSRAM软件写控制器的工作性能。
可选地，所述通过直接存储器访问DMA控制器，基于所述区块链表将所述数据单元和所述数据单元对应的指令地址信息发送给所述PSRAM包括：通过所述DMA将所述数据单元对应的指令地址信息和所述数据单元写入缓存，通过缓存将所述数据单元对应的指令地址信息和所述数据单元发给所述PSRAM。
从硬件层来看，在SOC通过QSPI接口向PSRAM发送数据时，拟写入数据被软件层处理成区块后，首先从SOC的内存被DMA控制器写入缓存，例如，先进先出缓存区(First input first output,FIFO)，再被FIFO经过QSPI接口发送到外接的PSRAM，在FIFO中的数据将根据先后顺序被自动发送。FIFO的存在使得数据从软件层到外设之间有了缓冲，能够帮助控制数据的传输速度。如图12所示，是本申请实施例的一种先进先出缓存示意图，缓存的数据宽度为32bit。
本实施例中，通过在DMA控制器与PSRAM之间设置缓存，能够控制数据传输的速度，避免速度过快导致粘包，即在所述区块发送未完成时所述 下一个待发送区块就进入了缓存，导致所述区块发送完成后片选信号没有被拉高从而造成电路异常的情况。控制数据传输的速度能够进一步保证数据的正常传输，提升了软件写控制器的稳定性以及在复杂环境下运行的可靠性。
可选地，在一个实施例中，所述方法还包括：控制第一写入速度不大于所述缓存的发送速度，控制第二写入速度不大于所述发送速度，所述第一写入速度为所述DMA控制器向所述缓存写入所述数据单元对应的指令地址信息的速度，所述第二写入速度为所述DMA控制器向所述缓存写入所述数据单元的速度，所述发送速度为所述数据单元对应的指令地址信息和所述数据单元被所述缓存发送给所述PSRAM的速度。
应理解，第一速度与第二速度可以相等，即当数据单元对应的指令地址信息和数据单元生成一个区块时，第一速度与第二速度相等且均小于发送速度，数据单元对应的指令地址信息与数据单元作为一个整体先后被发送至缓存。当数据单元对应的指令地址信息和数据单元分别生成第一区块和第二区块时，第一速度与第二速度均小于发送速度，数据单元对应的指令地址信息与数据单元分别以第一速度和第二速度先后被发送至缓存。
具体地，以图12所示的FIFO为例，在缓存中，软件写控制器控制区块的写入速度不大于发送速度，其中，写入速度可以根据区块的数据宽度、DMA控制器使用的总线宽度进行调整。
在本实施例中，通过控制区块被写入缓存的速度不大于区块中的数据和/或指令地址信息被发送出缓存发送速度，可以控制缓存中区块的填充速度，有效避免写入速度过快产生的粘包现象。例如在第一区块中的指令地址信息尚未从FIFO中被发出时，第二区块已经被写入FIFO，此时即为粘包。粘包将导致在第一区块中的指令地址信息发送完成后，软件层误认为指令地址信息发送未完成，无法正常释放CS信号，导致电路工作异常。通过控制写入速度不大于发送速度，能够保证所述区块中的数据和/或指令地址信息传输完成后所述下一个待发送区块才进入缓存，保证所述区块传输完成后片选信号能够被拉高，有效避免粘包，进一步提升软件写控制器的性能。
在本实施例中，通过配置第一写入速度和第二写入速度与发送速度相等，既能够保证所述区块传输完成后所述下一个待发送区块才进入缓存，也可避免写入速度偏慢造成的时序浪费，进一步提高了PSRAM软件写控制器的工作效率。
在一种可能的实现方式中，PSRAM软件写控制器可以参考表1确定的速度合适的数据传输宽度和写入速度进行配置。
表1
Figure PCTCN2021083105-appb-000001
表1中，MSIZE为DMA控制器在Burst模式下单次向FIFO写入数据的拍数，代表DMA控制器单次向FIFO写入数据的数据量。
可选地，在一个实施例中，所述方法还包括：确定所述DMA控制器发送的所述数据单元对应的指令地址信息和所述数据单元的数据量；控制第一写入速度不大于所述缓存的发送速度，控制第二写入速度不大于所述发送速度，所述第一写入速度为所述DMA控制器向所述缓存写入所述数据单元对应的指令地址信息的速度，所述第二写入速度为所述DMA控制器向所述缓存写入所述数据单元的速度，所述发送速度为所述数据单元对应的指令地址信息和所述数据单元被所述缓存发送给所述PSRAM的速度；当以所述发送速度发送的所述数据量等于预设数据量时，拉高所述片选信号，其中，所述预设数据量为根据所述数据单元对应的指令地址信息和所述数据单元确定的阈值。
本实施例中，通过同时控制区块在缓存中的填充速度以及片选信号的拉高条件，保证片选信号的正常拉高，能够进一步提升复杂环境下软件写控制器工作的稳定性，保证软件写控制器在复杂环境下安全高效地运行。
可选地，在一个实施例中，在所述DMA控制器发送所述数据单元对应的指令地址信息和所述数据单元后，接收所述DMA控制器发送的回写信息，所述回写信息用于指示所述数据单元对应的指令地址信息和所述数据单元发送完成，所述回写信息包括所述数据单元对应的指令地址信息和所述数据单元的写入状态信息和/或位置信息，所述状态信息用于告知SOC区块写入完成，所述位置信息用于告知区块被写入的位置。
具体地，在DMA控制器向PSRAM发完所述区块后，发送所述下一个待发送区块前，DMA控制器执行回写操作，软件层接收DMA控制器发送的回写信息。
在本实施例中，由于区块链表中区块与区块之间几乎没有时间间隔，在传输过程中，除了通过控制缓存中区块的填充速度避免粘包，还能够设计回写，软件层通过接收DMA控制器通过发送回写信息消耗一些软件指令，即DMA控制器每发送一个区块后，需要消耗约几纳秒的时间执行回写操作，能够适当增大区块与区块之间的时间间隔，进一步避免粘包现象，提升了软件写控制器的安全性、稳定性，优化了软件写控制器的工作性能。
本申请实施例还提供一种SOC芯片1300，如图13所示，包括：
处理器1301，用于根据伪静态随机存储器PSRAM的单帧写入数据量确定拟写入所述PSRAM的数据的至少一个数据单元和所述数据单元对应的指令地址信息，其中，所述单帧写入数据量为所述PSRAM对应的片选信号的低电平的时间内写入的数据量；根据所述数据单元对应的指令地址信息和所述数据单元生成至少一个区块，所述至少一个区块形成区块链表，所述区块包括指针信息、所述数据单元对应的指令地址信息和/或所述数据单元，所述指针信息用于指示传输所述区块链表时所述区块的下一个待发送区块；
DMA控制器1302，用于基于所述区块链表将所述数据单元对应的指令地址信息和所述数据单元发送给所述PSRAM。
可选地，所述区块还包括：配置信息，所述配置信息用于指示所述DMA控制器传输所述区块所需的指令。
可选地，所述指令包括所述DMA控制器传输所述区块的传输方向指令、传输通道指令、传输速度指令、传输数据宽度指令中的至少一个。
本实施例中，软件层的软件写控制器基于硬件层的处理器1301将拟写入PSRAM的数据一次性切分并确定成至少一个数据单元和所述数据单元对应的指令地址信息，所述数据单元对应的指令地址信息与所述数据单元生成至少一个区块，所述至少一个区块通过指针信息有序地组成区块链表。通过具有硬件电路支持的DMA控制器以区块链表的的形式将数据发送给PSRAM，节省了软件写控制器消耗软件指令指示多次切分、配置、发送数据的时间，有效提升了软件写控制器对PSRAM的访问效率，实现了PSRAM的高速写入。
可选地，处理器1301还用于：根据所述数据单元对应的指令地址信息和所述数据单元生成一个区块，所述区块包括所述配置信息、所述指针信息、所述数据单元对应的所述指令地址信息和所述数据单元。
可选地，处理器1301还用于：根据所述数据单元对应的指令地址信息和所述数据单元生成第一区块和第二区块，所述第一区块包括所述第一区块的配置信息、所述第一区块的指针信息、所述数据单元对应的指令地址信息，第二区块包括所述第二区块的配置信息、所述第二区块的指针信息、所述数据单元。
可选地，处理器1301还用于：确定所述DMA控制器发送的所述数据单元对应的指令地址信息和所述数据单元的数据量，当所述数据量大于预设数据量时，拉高所述片选信号，其中，所述预设数据量为根据所述数据单元对应的指令地址信息和所述数据单元确定的阈值。
可选地，所述预设数据量与所述数据单元对应的指令地址信息和所述数据单元的数据量相等。
可选地，在一个实施例中，如图14所示，SOC芯片1400，包括：
处理器1401，用于执行上述处理器执行的功能；
DMA控制器1402，用于执行上述DMA控制器执行的功能；所述DMA控制器用于将所述数据单元对应的指令地址信息和所述数据单元写入所述缓存；
缓存1403，用于将所述DMA控制器发送的所述数据单元对应的指令地址信息和所述数据单元发送给所述PSRAM。
可选地，所述处理器1401还用于：控制第一写入速度不大于所述缓存的发送速度，控制第二写入速度不大于所述发送速度，所述第一写入速度为所述DMA控制器向所述缓存写入所述数据单元对应的指令地址信息的速度，所述第二写入速度为所述DMA控制器向所述缓存写入所述数据单元的速度，所述发送速度为所述数据单元对应的指令地址信息和所述数据单元被所述缓存发送给所述PSRAM的速度。
可选地，所述处理器1401还用于：在所述DMA控制器发送所述数据单元和所述数据单元对应的指令地址信息后，接收所述DMA控制器发送的回写信息，所述回写信息用于指示所述数据单元对应的指令地址信息和所述数据单元发送完成，所述回写信息包括所述数据单元对应的指令地址信息和 所述数据单元的状态信息和/或位置信息。
本申请实施例还提供一种软件写控制器，用于执行本申请实施例任一实施例所述的数据写入方法。
示例性地，软件写控制器1500，属于软件层，基于SOC芯片的硬件功能执行软件功能，如图15所示，包括：
处理模块1501，用于根据伪静态随机存储器PSRAM的单帧写入数据量确定拟写入所述PSRAM的数据的至少一个数据单元和所述数据单元对应的指令地址信息，其中，所述单帧写入数据量为所述PSRAM对应的片选信号的低电平的时间内写入的数据量；根据所述数据单元对应的指令地址信息和所述数据单元生成至少一个区块，所述至少一个区块形成区块链表，所述区块包括指针信息、所述数据单元对应的指令地址信息和/或所述数据单元，所述指针信息用于指示传输所述区块链表时所述区块的下一个待发送区块；
写入模块1502，用于通过直接存储器访问DMA控制器，基于所述区块链表将所述数据单元对应的指令地址信息和所述数据单元发送给所述PSRAM。
可选地，在一个实施例中，所述区块还包括：配置信息，所述配置信息用于指示所述DMA控制器传输所述区块所需的指令。
可选地，在一个实施例中，所述指令包括所述DMA控制器传输所述区块的传输方向指令、传输通道指令、传输速度指令、传输数据宽度指令中的至少一个。
可选地，在一个实施例中，处理模块1501用于根据所述数据单元对应的指令地址信息和所述数据单元生成一个区块，所述区块包括所述配置信息、所述指针信息、所述数据单元对应的所述指令地址信息和所述数据单元。
可选地，在一个实施例中，处理模块1501用于根据所述数据单元对应的指令地址信息和所述数据单元生成第一区块和第二区块，所述第一区块包括所述第一区块的配置信息、所述第一区块的指针信息、所述数据单元对应的指令地址信息，第二区块包括所述第二区块的配置信息、所述第二区块的指针信息、所述数据单元。
可选地，处理模块1501还用于：确定所述DMA控制器发送的所述数据单元对应的指令地址信息和所述数据单元的数据量，当所述数据量等于预设数据量时，拉高所述片选信号，其中，所述预设数据量为根据所述数据单 元对应的指令地址信息和所述数据单元确定的阈值。
可选地，所述预设数据量与所述数据单元对应的指令地址信息和所述数据单元的数据量相等。
可选地，在一个实施例中，所述写入模块1502还用于：通过所述DMA将所述数据单元对应的指令地址信息和所述数据单元写入缓存，通过所述缓存将所述数据单元对应的指令地址信息和所述数据单元发给所述PSRAM。
可选地，所述处理模块1501还用于：控制第一写入速度不大于所述缓存的发送速度，控制第二写入速度不大于所述发送速度，所述第一写入速度为所述DMA控制器向所述缓存写入所述数据单元对应的指令地址信息的速度，所述第二写入速度为所述DMA控制器向所述缓存写入所述数据单元的速度，所述发送速度为所述数据单元对应的指令地址信息和所述数据单元被所述缓存发送给所述PSRAM的速度。
可选地，所述写入模块1502还用于：确定所述DMA控制器发送的所述数据单元对应的指令地址信息和所述数据单元的数据量；控制第一写入速度不大于所述缓存的发送速度，控制第二写入速度不大于所述发送速度，所述第一写入速度为所述DMA控制器向所述缓存写入所述数据单元对应的指令地址信息的速度，所述第二写入速度为所述DMA控制器向所述缓存写入所述数据单元的速度，所述发送速度为所述数据单元对应的指令地址信息和所述数据单元被所述缓存发送给所述PSRAM的速度；当以所述发送速度发送的所述数据量等于预设数据量时，维持所述片选信号的高电平状态，其中，所述预设数据量为根据所述数据单元对应的指令地址信息和所述数据单元确定的阈值。
可选地，所述写入模块1502还用于：在所述DMA控制器发送所述数据单元和所述数据单元对应的指令地址信息后，接收所述DMA控制器发送的回写信息，所述回写信息用于指示所述数据单元对应的指令地址信息和所述数据单元发送完成，所述回写信息包括所述数据单元对应的指令地址信息和所述数据单元的状态信息和/或位置信息。
本申请实施例还提供一种计算机可读存储介质，所述计算机可读存储介质中存储有计算机执行指令，所述计算机执行指令被处理器执行时用于实现本申请实施例中任一种可能的实现方式所述的数据写入方法。
应理解，实现上述各方法实施例的全部或部分步骤可以通过程序指令相 关的硬件来完成。所述程序可以存储于计算机可读取存储介质中。该程序在执行时，执行包括上述各方法实施例的步骤；所述存储介质包括：ROM、RAM、磁碟或者光盘等各种可以存储程序代码的介质。
应理解，本申请实施例所述软件层、软件写控制器可理解为用于执行本申请实施例所述的数据写入方法的计算机可读存储介质中的计算机执行指令。
示例性地，如图16所示，使用本申请所述的写入方法执行PSRAM写入访问流程，并将所述数据单元对应的指令地址信息和所述数据单元分别配置成所述第一区块和所述第二区块，所述第一写入速度与所述第二写入速度均不大于所述发送速度，传输过程中当以所述发送速度发送的所述数据量等于预设数据量时，拉高所述片选信号，在通过所述DMA控制器发送所述数据单元对应的指令地址信息和所述数据单元后，接收所述DMA控制器发送的回写信息。
在串行接口最大工作频率SCLK为48MHz、采用四线模式的情况下，数据有效负载为128字节。在逻辑控制器中运行上述访问流程，CS信号拉低时间为6.5μs-6.8μs，相比于图5所示的普通软件写控制器的逻辑运行结果，时序帧与时序帧之间的时间间隔约为180ns，即本申请实施例中区块与区块的时间间隔为180ns，且时间间隔稳定，不受系统调度的影响，有效时间与无效时间的比值为6.8*1000:180，即37.8:1，相比于使用for/while逻辑执行PSRAM写入访问流程时的0.098:1，极大地提高了软件写控制器的工作效率。
示例性地，在串行接口最大工作频率SCLK为48MHz、采用四线模式的情况下，每个时钟信号的字节数为4，数据有效负载为128字节时，软件写控制器访问支持QSPI接口外接设备，单位时间(秒，Sec)携带比特数的理论极限值为：48*4/8＝24*10 6Byte＝24*10 6/(1024*1024)＝22.8MB，即理论速度为22.8MB/Sec。
本申请实施例所述的PSRAM软件写控制器在指令地址信息占用4字节，数据有效负载为128字节时，对有效负载的最大访问速度V 1＝22.8*(128/(4+128))＝22.1MB/Sec，CS信号拉低时间tCEM＝(4+128)(48*4/8)＝5.5μs。
使用for/while逻辑的普通软件写控制器在相同条件下，按典型时序帧时 间间隔15μs计算，对有效负载的最大访问速度V 2＝22.8*((5.5*128/132)/(5.5+15))＝5.93MB/Sec。
在相同条件下，本申请实施例提供的软件写控制器的写入速度达到了普通软件写控制器的4倍。
示例性地，对本申请实施例提供的PSRAM软件写控制器进行写入速度测试与稳定性测试。
(1)写入速度测试
测试条件：SCLK为48MHz、四线模式，数据有效负载为128字节或64字节。
PSRAM软件写控制器写入访问速度平均值测试结果如表2所示：
表2
Figure PCTCN2021083105-appb-000002
其中，RAM为主控芯片中的随机存储器。由表2可以看到，本申请实施例提供的PSRAM软件写控制器极大地提升了写入速度，达到了数倍于普通软件写控制器的工作效率。
(2)稳定性测试
测试条件：数据有效负载为128字节或64字节，每轮次写入以及回读的次数均为100000次。
PSRAM软件写控制器稳定性测试结果如表3所示：
表3
Figure PCTCN2021083105-appb-000003
比较本申请实施例提供的PSRAM软件写控制器的写入值与回读值是否 相等，对其进行稳定性测试发现，其具有优异的稳定性。
综上所述，本申请提供了一种数据写入的方法，应用于外接PSRAM的SOC/MCU芯片，能够有效提升软件写控制器访问PSRAM的写入速度，实现对PSRAM的高速写，并能在复杂环境下稳定循环工作，不需要在SOC/MCU芯片中额外增设IP写控制器的情况下，通过软件层设计、结合SOC/MCU芯片中现有的硬件电路，使软件写控制器能够达到IP控制器性能。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到各种等效的修改或替换，这些修改或替换都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以权利要求的保护范围为准。

Claims (23)

  1. 一种数据写入的方法，其特征在于，包括：
    根据伪静态随机存储器PSRAM的单帧写入数据量确定拟写入所述PSRAM的数据的至少一个数据单元和所述数据单元对应的指令地址信息，其中，所述单帧写入数据量为所述PSRAM对应的片选信号的低电平的时间内写入的数据量；
    根据所述数据单元对应的指令地址信息和所述数据单元生成至少一个区块，所述至少一个区块形成区块链表，所述区块包括指针信息、所述数据单元对应的指令地址信息和/或所述数据单元，所述指针信息用于指示传输所述区块链表时所述区块的下一个待发送区块；
    通过DMA控制器，基于所述区块链表将所述数据单元对应的指令地址信息和所述数据单元发送给所述PSRAM。
  2. 根据权利要求1所述的方法，其特征在于，所述区块还包括：配置信息，所述配置信息用于指示所述DMA控制器传输所述区块所需的指令。
  3. 根据权利要求2所述的方法，其特征在于，所述指令包括所述DMA控制器传输所述区块的传输方向指令、传输通道指令、传输速度指令、传输数据宽度指令中的至少一个。
  4. 根据权利要求2所述的方法，其特征在于，所述根据所述数据单元对应的指令地址信息和所述数据单元生成至少一个区块，包括：
    根据所述数据单元对应的指令地址信息和所述数据单元生成一个区块，所述区块包括所述配置信息、所述指针信息、所述数据单元对应的指令地址信息和所述数据单元。
  5. 根据权利要求2所述的方法，其特征在于，所述根据所述数据单元对应的指令地址信息和所述数据单元生成至少一个区块包括：
    根据所述数据单元对应的指令地址信息和所述数据单元生成第一区块和第二区块，所述第一区块包括所述第一区块的配置信息、所述第一区块的指针信息、所述数据单元对应的指令地址信息，所述第二区块包括所述第二区块的配置信息、所述第二区块的指针信息、所述数据单元。
  6. 根据权利要求1至5中任一项所述的方法，其特征在于，所述方法还包括：
    确定所述DMA控制器发送的所述数据单元对应的指令地址信息和所述 数据单元的数据量，
    当所述数据量等于预设数据量时，拉高所述片选信号，其中，所述预设数据量为根据所述数据单元对应的指令地址信息和所述数据单元确定的阈值。
  7. 根据权利要求6所述的方法，其特征在于，所述预设数据量与所述数据单元对应的指令地址信息和所述数据单元的数据量相等。
  8. 根据权利要求1至5中任一项所述的方法，其特征在于，所述通过DMA控制器，基于所述区块链表将所述数据单元对应的指令地址信息和所述数据单元发送给所述PSRAM包括：
    通过所述DMA控制器将所述数据单元对应的指令地址信息和所述数据单元写入缓存，通过所述缓存将所述数据单元对应的指令地址信息和所述数据单元发给所述PSRAM。
  9. 根据权利要求8所述的方法，其特征在于，所述方法还包括：
    控制第一写入速度不大于所述缓存的发送速度，控制第二写入速度不大于所述发送速度，所述第一写入速度为所述DMA控制器向所述缓存写入所述数据单元对应的指令地址信息的速度，所述第二写入速度为所述DMA控制器向所述缓存写入所述数据单元的速度，所述发送速度为所述数据单元对应的指令地址信息和所述数据单元被所述缓存发送给所述PSRAM的速度。
  10. 根据权利要求1至5中任一项所述的方法，其特征在于，所述方法还包括：
    确定所述DMA控制器发送的所述数据单元对应的指令地址信息和所述数据单元的数据量；
    控制第一写入速度不大于所述缓存的发送速度，控制第二写入速度不大于所述发送速度，所述第一写入速度为所述DMA控制器向所述缓存写入所述数据单元对应的指令地址信息的速度，所述第二写入速度为所述DMA控制器向所述缓存写入所述数据单元的速度，所述发送速度为所述数据单元对应的指令地址信息和所述数据单元被所述缓存发送给所述PSRAM的速度；
    当以所述发送速度发送的所述数据量等于预设数据量时，拉高所述片选信号，其中，所述预设数据量为根据所述数据单元对应的指令地址信息和所述数据单元确定的阈值。
  11. 根据权利要求1至5中任一项所述的方法，其特征在于，所述方法 还包括：
    在通过所述DMA控制器发送所述数据单元对应的指令地址信息和所述数据单元后，接收所述DMA控制器发送的回写信息，所述回写信息用于指示所述数据单元对应的指令地址信息和所述数据单元发送完成，所述回写信息包括所述数据单元对应的指令地址信息和所述数据单元的状态信息和/或位置信息。
  12. 一种片上系统SOC芯片，其特征在于，包括：
    处理器，用于根据伪静态随机存储器PSRAM的单帧写入数据量确定拟写入所述PSRAM的数据的至少一个数据单元和所述数据单元对应的指令地址信息，其中，所述单帧写入数据量为所述PSRAM对应的片选信号的低电平的时间内写入的数据量；根据所述数据单元对应的指令地址信息和所述数据单元生成至少一个区块，所述至少一个区块形成区块链表，所述区块包括指针信息、所述数据单元对应的指令地址信息和/或所述数据单元，所述指针信息用于指示传输所述区块链表时所述区块的下一个待发送区块；
    DMA控制器，用于基于所述区块链表将所述数据单元对应的指令地址信息和所述数据单元发送给所述PSRAM。
  13. 根据权利要求12所述的芯片，其特征在于，所述区块还包括：配置信息，所述配置信息用于指示所述DMA控制器传输所述区块所需的指令。
  14. 根据权利要求13所述的芯片，其特征在于，所述指令包括所述DMA控制器传输所述区块的传输方向指令、传输通道指令、传输速度指令、传输数据宽度指令中的至少一个。
  15. 根据权利要求13所述的芯片，其特征在于，所述处理器用于：
    根据所述数据单元对应的指令地址信息和所述数据单元生成一个区块，所述区块包括所述配置信息、所述指针信息、所述数据单元对应的所述指令地址信息和所述数据单元。
  16. 根据权利要求13所述的芯片，其特征在于，所述处理器用于：
    根据所述数据单元对应的指令地址信息和所述数据单元生成第一区块和第二区块，所述第一区块包括所述第一区块的配置信息、所述第一区块的指针信息、所述数据单元对应的指令地址信息，所述第二区块包括所述第二区块的配置信息、所述第二区块的指针信息、所述数据单元。
  17. 根据权利要求12至16中任一项所述的芯片，其特征在于，所述处 理器还用于：
    确定所述DMA控制器发送的所述数据单元对应的指令地址信息和所述数据单元的数据量，
    当所述数据量等于预设数据量时，拉高所述片选信号，其中，所述预设数据量为根据所述数据单元对应的指令地址信息和所述数据单元确定的阈值。
  18. 根据权利要求17所述的芯片，其特征在于，所述预设数据量与所述数据单元对应的指令地址信息和所述数据单元的数据量相等。
  19. 根据权利要求12至16中任一项所述的芯片，其特征在于，所述芯片还包括：
    缓存；
    所述DMA控制器用于将所述数据单元对应的指令地址信息和所述数据单元写入所述缓存，所述缓存用于将所述DMA控制器写入的所述数据单元对应的指令地址信息和所述数据单元发送给所述PSRAM。
  20. 根据权利要求19所述的芯片，其特征在于，所述处理器还用于：
    控制第一写入速度不大于所述缓存的发送速度，控制第二写入速度不大于所述发送速度，所述第一写入速度为所述DMA控制器向所述缓存写入所述数据单元对应的指令地址信息的速度，所述第二写入速度为所述DMA控制器向所述缓存写入所述数据单元的速度，所述发送速度为所述数据单元对应的指令地址信息和所述数据单元被所述缓存发送给所述PSRAM的速度。
  21. 根据权利要求12至16中任一项所述的芯片，其特征在于，所述芯片还包括：
    缓存；
    所述处理器还用于：
    确定所述DMA控制器发送的所述数据单元对应的指令地址信息和所述数据单元的数据量；
    控制第一写入速度不大于所述缓存的发送速度，控制第二写入速度不大于所述发送速度，所述第一写入速度为所述DMA控制器向所述缓存写入所述数据单元对应的指令地址信息的速度，所述第二写入速度为所述DMA控制器向所述缓存写入所述数据单元的速度，所述发送速度为所述数据单元对应的指令地址信息和所述数据单元被所述缓存发送给所述PSRAM的速度；
    当以所述发送速度发送的所述数据量等于预设数据量时，拉高所述片选信号，其中，所述预设数据量为根据所述数据单元对应的指令地址信息和所述数据单元确定的阈值。
  22. 根据权利要求12至16中任一项所述的芯片，其特征在于，所述处理器还用于：
    在通过所述DMA控制器发送所述数据单元对应的指令地址信息和所述数据单元后，接收所述DMA控制器发送的回写信息，所述回写信息用于指示所述数据单元对应的指令地址信息和所述数据单元发送完成，所述回写信息包括所述数据单元对应的指令地址信息和所述数据单元的状态信息和/或位置信息。
  23. 一种计算机可读存储介质，其特征在于，所述计算机可读存储介质中存储有计算机执行指令，所述计算机执行指令被处理器执行时用于实现权利要求1至11中任一项所述的数据写入的方法。
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CN115952105A (zh) * 2022-12-05 2023-04-11 深圳市朗宇芯科技有限公司 一种基于数据缓存的数据传输方法、装置及存储介质
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