WO2022198496A1 - 显示面板和制备的方法、显示装置 - Google Patents

显示面板和制备的方法、显示装置 Download PDF

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Publication number
WO2022198496A1
WO2022198496A1 PCT/CN2021/082705 CN2021082705W WO2022198496A1 WO 2022198496 A1 WO2022198496 A1 WO 2022198496A1 CN 2021082705 W CN2021082705 W CN 2021082705W WO 2022198496 A1 WO2022198496 A1 WO 2022198496A1
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Prior art keywords
light
transistor
node
signal terminal
pull
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PCT/CN2021/082705
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English (en)
French (fr)
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WO2022198496A8 (zh
Inventor
李永谦
冯雪欢
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京东方科技集团股份有限公司
合肥京东方卓印科技有限公司
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Application filed by 京东方科技集团股份有限公司, 合肥京东方卓印科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2021/082705 priority Critical patent/WO2022198496A1/zh
Priority to CN202180000579.XA priority patent/CN115428164A/zh
Publication of WO2022198496A1 publication Critical patent/WO2022198496A1/zh
Publication of WO2022198496A8 publication Critical patent/WO2022198496A8/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details

Definitions

  • the present application relates to the field of display technology, and in particular, to a display panel, a method for manufacturing the same, and a display device.
  • gate driving circuits are an important part of the display devices.
  • the gate driving circuit may include a multi-stage cascaded shift register, and the shift register generates a scan signal to scan each row of sub-pixels in the display device, thereby realizing the display of the picture.
  • OLEDs organic light emitting diodes
  • the present application seeks to alleviate or solve at least one of the above-mentioned problems to at least some extent.
  • the gate drive circuits are usually arranged on both sides of the display panel, which makes it difficult to achieve ultra-narrow bezels or even no bezels. Rectangular shape, which makes it difficult to achieve narrow bezels with traditional design methods.
  • TFT thin film transistor
  • the present application proposes a display panel.
  • the display area of the display panel includes a plurality of pixel areas and a plurality of gate driving circuit areas, the gate driving circuit areas are located between two adjacent pixel areas, and the display panel includes: a substrate; a backplane a circuit layer, the backplane circuit layer is located on the substrate, and the backplane circuit layer is in the gate drive circuit region, and has a plurality of thin film transistors; a plurality of light-emitting elements, the plurality of light-emitting elements are located in The backplane circuit layer is located on the side away from the substrate and is located in the area where the pixel area is located, the display panel has a light-shielding hole, the light-shielding hole is filled with a metal layer, and the light-shielding hole and the metal The position of the orthographic projection of the layer on the substrate is configured to block light impinging on the active layer of the thin film transistor.
  • the light-shielding hole and the metal layer of the display panel can alleviate or even avoid the influence of the light emission of the light-emitting element on the TFT in the gate driving circuit area, thereby further improving the service life of the display panel on the premise of realizing a narrow frame.
  • the light-shielding hole and the metal layer are located on a side of the backplane circuit layer away from the substrate. Therefore, the active layer of the thin film transistor can be better protected to prevent negative drift.
  • the pixel region and the gate driving circuit region are disposed adjacent to each other, the light-emitting element is located in the pixel region, and a pixel defining structure is formed between the adjacent light-emitting elements, The light-shielding hole is formed on the pixel defining structure. Thereby, the light-shielding hole and the metal layer can be easily provided.
  • the metal layer includes a cathode metal. Thereby, the light-shielding hole and the metal layer can be easily provided.
  • a plurality of the light-shielding holes are included, and each of the pixel regions and the thin film transistors in the gate driving circuit region has the light-shielding holes. Therefore, the protection of the light-shielding hole to the active layer of the thin film transistor can be further improved.
  • the thin film transistor in the gate driving circuit region includes: an active layer; a gate electrode and a gate insulating layer, the gate electrode and the gate insulating layer are located in the active layer and away from the substrate one side; source-drain electrodes, the source-drain electrodes are located on the side of the active layer away from the substrate, an interlayer dielectric layer is spaced between the source-drain electrodes and the gate, and the source-drain electrodes are
  • the drain electrode is connected to the active layer through a through hole passing through the interlayer dielectric layer, the orthographic projection of the light-shielding hole on the substrate, and the through hole of the interlayer dielectric layer on the substrate. There is no overlapping area between orthographic projections. Therefore, the protection of the light-shielding hole to the active layer of the thin film transistor can be further improved.
  • the pixel region further includes a pixel light-emitting sub-region and a pixel circuit sub-region, the light-emitting element is located in the pixel light-emitting region, and the pixel light-emitting sub-region and the pixel circuit sub-region are located along the first direction, and the light-shielding hole extends along the first direction. Therefore, the protection of the light-shielding hole to the active layer of the thin film transistor can be further improved.
  • the length of the light-shielding holes along the first direction is consistent with the length of the transistor group, so The plurality of thin film transistors in the transistor group are arranged between the two light-shielding holes along the first direction.
  • the protection of the light-shielding hole to the active layer of the thin film transistor can be further improved.
  • the pixel regions are arranged in an array on the substrate, each of the pixel regions includes at least two sub-pixels, and each row of the pixel regions and at least two of the gate driving circuit regions Correspondingly, each of the gate driving circuit regions is located between two adjacent pixel regions, the gate driving circuit includes a plurality of shift registers connected in cascade, and each shift register is associated with a row of the The sub-pixels are electrically connected; each of the shift registers includes a plurality of transistor groups, and each of the transistor groups includes at least one of the thin film transistors.
  • the depth of the light-shielding hole is 1-3 micrometers, and the width of the light-shielding hole is 3-10 micrometers. Therefore, the protection of the light-shielding hole to the active layer of the thin film transistor can be further improved.
  • the present application proposes a method for preparing the aforementioned display panel, the method comprising: forming a backplane circuit layer on a substrate, and configuring the gate driving circuit in the display panel forming a plurality of thin film transistors in the area; forming a plurality of light-emitting elements on the side of the backplane circuit layer away from the substrate, and placing the light-emitting elements in the pixel area; and the method includes forming light-shielding holes and The operation of the metal layer, and filling the metal layer into the light-shielding hole, the light-shielding hole and the position of the orthographic projection of the metal layer on the substrate are configured to block the light irradiation of the light-emitting element to the active layer of the thin film transistor.
  • the aforementioned display panel can be easily obtained.
  • forming the light-shielding hole and the metal layer includes: before forming the light-emitting element, forming a pixel-defining structure between a plurality of the light-emitting elements in advance, and forming a pixel-defining structure on the pixel-defining structure the light-shielding hole; when forming the light-emitting element, the metal layer is formed by using a cathode metal. Thereby, the light-shielding hole and the metal layer can be easily formed.
  • the present application provides a display device.
  • the display device includes the aforementioned display panel. Therefore, the display device has at least one of the advantages of narrow frame and long service life.
  • FIG. 1 shows a schematic structural diagram of a display panel according to an example of the present application
  • Fig. 2 shows the cross-sectional structure schematic diagram of the display panel along the A-A' direction in Fig. 1;
  • FIG. 3 shows a schematic structural diagram of a display panel according to an example of the present application
  • FIG. 4 shows a schematic circuit diagram of a pixel circuit according to an example of the present application
  • FIG. 5 shows a schematic circuit diagram of a gate driving circuit according to an example of the present application
  • FIG. 6 shows a schematic circuit diagram of a gate driving circuit according to another example of the present application.
  • FIG. 7 shows a schematic circuit diagram of a gate driving circuit according to yet another example of the present application.
  • FIG. 8 shows a schematic circuit diagram of a gate driving circuit according to yet another example of the present application.
  • FIG. 9 shows a flowchart of a method of manufacturing a display panel according to an example of the present application.
  • the present application proposes a display panel.
  • the display area of the display surface 1000 includes a plurality of pixel areas 1100 and a plurality of gate driving circuit areas 1200 , and the gate driving circuit area 1200 is located between two adjacent pixel areas 1100 between.
  • the substrate 100 has a backplane circuit layer, and the backplane circuit layer has a plurality of thin film transistors in the gate driving circuit region.
  • a plurality of light emitting elements (only one is shown in FIG. 2 ) 800 are located on the side of the backplane circuit layer away from the substrate 100 and located in the area where the pixel area is located.
  • the light-shielding hole see 1220 in FIG.
  • the light-shielding hole and the position of the orthographic projection of the metal layer on the substrate are configured to shield the light irradiating to the active layer of the thin film transistor.
  • Light Therefore, the light-shielding holes and the metal layer of the display panel can alleviate or even avoid the influence of the light-emitting elements, etc., on the TFT in the gate driving circuit area, thereby further improving the service life of the display panel on the premise of realizing a narrow frame. .
  • a gate driving circuit in order to narrow the border of the display panel, may be disposed between two adjacent pixel regions in the display region.
  • the gate driving circuit has a relatively complex structure, in order to reduce its occupied area, a plurality of thin film transistors in the gate driving circuit are collectively arranged and arranged as a transistor group 1210, which is adjacent to the pixel area.
  • This design can better achieve the effect of narrowing the frame, but at the same time, if the light-shielding hole and the metal layer are not provided at this time, the light emitted by the pixel light-emitting sub-region 1110 in the pixel region will be more easily irradiated to the active components of the transistor group.
  • the light-shielding hole and the metal layer With the setting of the light-shielding hole and the metal layer, the light emitted by the pixel light-emitting sub-region can be better shielded, preventing the active layer from being irradiated, and then reducing or even avoiding the negative drift caused by the illumination, so as to realize the extension of the The effect of the lifespan of the display panel.
  • the specific positions of the light-shielding hole and the metal layer in the cross-sectional direction of the display panel are not particularly limited, as long as light-shielding can be achieved.
  • the light-shielding hole and the metal layer 50 may be located on the side of the backplane circuit layer away from the substrate, that is, the side of the thin film transistor away from the substrate 100 . Therefore, the active layer of the thin film transistor can be better protected to prevent negative drift.
  • the pixel-defining structures 600 there are pixel defining structures 600 between adjacent light emitting elements 800 , and light-shielding holes may be formed on the pixel defining structures.
  • Metal layer 50 includes cathode metal.
  • the light-shielding holes and the metal layer can be easily arranged: on the one hand, the arrangement of the light-shielding holes and the metal layer 50 here will not affect the change of the various laminated structures in the circuit layer of the backplane and the etching pattern of the metal.
  • the pixel-defining structure has a relatively large thickness due to the need to isolate the light-emitting layers of two adjacent light-emitting elements, which facilitates the preparation of light-shielding holes.
  • the pixel defining structure 600 itself has an opening for accommodating the light-emitting element 800, so the light-shielding hole can be formed simultaneously with the opening.
  • the metal layer 50 filled in the light-shielding hole can be formed by using the cathode metal of the light-emitting element 800 .
  • the display panel may include a plurality of the light-shielding holes.
  • the light-shielding holes may be provided between each pixel area and the thin film transistors in the gate driving circuit area.
  • each gate driving circuit region may have two light-shielding holes 1220 to isolate the light emission of the two adjacent pixel regions 1100 . Therefore, the protection of the light-shielding hole to the active layer of the thin film transistor can be further improved.
  • the specific number and structure of the thin film transistors in the gate driving circuit region are not particularly limited, and those skilled in the art can design according to actual needs.
  • the thin film transistor may include an active layer 10, a gate electrode 21 and a gate insulating layer 700, and the gate electrode and the gate insulating layer are located on a side of the active layer 10 away from the substrate 100;
  • the source and drain electrodes can be located on the side of the active layer 10 away from the substrate 100, an interlayer dielectric layer 300 is spaced between the source and drain electrodes and the gate electrode, and the source and drain electrodes pass through the through layer
  • the through holes of the intermediate dielectric layer 300 are connected to the active layer 10 .
  • the aforementioned thin film transistor is only an example of the present invention, and should not be construed as a limitation on the specific structure of the thin film transistor.
  • the backplane circuit layer may include the buffer layer 200 on the substrate 100 , various hierarchical structures of the aforementioned thin film transistors, and structures such as the passivation layer 400 and the planarization layer 500 .
  • the position of the light shielding hole can be arranged as close to the pixel area as possible. Therefore, the protection of the active layer of the thin film transistor by the light-shielding hole can be further improved: at this time, the light-shielding hole and the metal layer 50 filled therein can better protect the channel region between the source and the drain.
  • the light emitted by the light-emitting element 800 and the like can be better shielded by the metal layer 50 (refer to the directions indicated by the arrows in FIG. 2 ).
  • the pixel region further includes a pixel light-emitting sub-region 1110 and a pixel circuit sub-region 1120, the light-emitting element is located in the pixel light-emitting sub-region, the pixel light-emitting sub-region and the pixel circuit sub-region 1120
  • the sub-regions are arranged along a first direction, and the light-shielding holes 1220 extend along the first direction.
  • the protection of the active layer of the thin film transistor by the light-shielding hole can be further improved: as mentioned above, in order to save the occupied area of the gate driving circuit, the plurality of thin film transistors in the transistor group 1210 are mostly arranged in sequence, such as Also arranged along the first direction. At this time, the arrangement of the light-shielding holes 1220 along the first direction can save the occupied area on the one hand, and can better shield the transistor group on the other hand.
  • the pixel circuit in the pixel sub-light-emitting region may also have a plurality of thin film transistors and capacitor structures, and the active layer 10 of the plurality of thin film transistors may be formed by a whole layer of semiconductor material through a patterning process.
  • the gate layer 20 can be formed by a whole layer of metal material through a patterning process to form a plurality of metal blocks and metal traces to serve as the gate of the thin film transistor and traces such as gate lines, and form a capacitor structure with other metal layers.
  • the source-drain layer 30 can also be used to form source-drain electrodes and data traces.
  • the plurality of signal lines 40 can be formed of gate metal or source-drain metal through a patterning process. It is necessary to form metal traces for electrical connection, and the source and drain of the thin film transistor and the active layer can be realized by means of via holes. connect.
  • the depth and width of the light-shielding holes are not particularly limited, for example, in some examples, the light-shielding holes may have a depth of 1-3 micrometers and a width of the light-shielding holes may be 3-10 micrometers.
  • the depth of the light-shielding hole is the extending depth along the direction perpendicular to the plane of the substrate 100 , and the width is the dimension of the light-shielding hole perpendicular to the first direction on the plane of the substrate 100 .
  • the specific shape and size of the light-shielding hole are not particularly limited, and those skilled in the art can select according to the actual situation.
  • the light-shielding hole may be a through hole that penetrates the pixel-defining structure, or may be a blind hole that does not completely penetrate the pixel-defining structure.
  • the orthographic projection of the light-shielding hole on the substrate 100 may be a strip shape, a circular hole or other shapes, as long as the metal layer filled in the light-shielding hole can block the light irradiated to the active layer.
  • the specific structure of the metal layer 50 is not particularly limited.
  • the metal layer 50 when the metal layer 50 is formed of cathode metal, the metal layer 50 may be connected to the cathode 830 of the light-emitting element 80 (this structure is not shown in the figure), or may have the structure shown in FIG. 2 , that is, The metal layer 50 is not connected to the cathode 830 .
  • the light-emitting element 800 includes an anode 810, a cathode 830 and a light-emitting layer 820 interposed therebetween.
  • the structure of the light emitting element 800 is not limited thereto, and may also have structures including, but not limited to, an electron transport layer, an electron blocking layer, a hole transport layer, and a hole blocking layer.
  • the length of the light-shielding hole along the first direction is the same as the length of the transistor group 1210 , which means that the lengths of the two are approximately the same, but not completely equal. That is, the length of the light-shielding hole may be approximately the same as the length of the transistor group, so as to achieve a better shielding effect.
  • the length of the light-shielding hole may be slightly shorter than the length of the transistor group, or may be longer than the length of the transistor group. Those skilled in the art can adjust the location and length of the light-shielding holes according to the specific locations of the multiple active layers in the transistor group.
  • pixel regions are arranged in an array on the substrate, each of the pixel regions includes at least two sub-pixels, and each row of the pixel regions corresponds to at least two of the gate driving circuit regions,
  • Each of the gate driving circuit regions is located between two adjacent pixel regions, the gate driving circuit includes a plurality of shift registers connected in cascade, each of the shift registers is associated with a row of the sub-pixels electrically connected;
  • each of the shift registers includes a plurality of transistor groups, each of the transistor groups including at least one of the thin film transistors.
  • the pixel circuit sub-region 1100 may have pixel circuits. Each sub-pixel corresponds to one pixel circuit, and the structure of the pixel circuit is not particularly limited.
  • the pixel circuit is used to control the light-emitting elements in the pixel light-emitting sub-region, such as turning them on and off, and adjusting the light-emitting brightness.
  • the specific pixel circuit structure can be selected and set according to actual needs.
  • the structure of the pixel circuit may include structures such as “2T1C”, “6T1C”, “7T1C”, “6T2C” or “7T2C”, “T” is a thin film transistor, and the number in front of “T” indicates the number of thin film transistors , "C” is the storage capacitor, and the number in front of "C” indicates the number of storage capacitors.
  • a pixel circuit may include a switching transistor and a driving transistor.
  • the pixel circuit may have a structure as shown in FIG. 4 .
  • the stability of the thin film transistors and light-emitting devices (OLEDs) in the pixel circuit may decrease (for example, the threshold voltage of the driving transistor shifts), which affects the display effect of the display panel. circuit to compensate.
  • a pixel compensation circuit may be provided in the sub-pixel to internally compensate the sub-pixel by the pixel compensation circuit.
  • the driving transistor or light-emitting device can be measured by the thin film transistor inside the sub-pixel, and the measured data can be transmitted to an external sensing circuit, so as to use the external sensing circuit to calculate the driving voltage value to be compensated and perform external compensation.
  • the control electrode (gate) of the switching transistor T1 is used as an example.
  • the control electrode (gate) of the switching transistor T1 is electrically connected to the first gate signal terminal G1
  • the first pole (one of the source and drain) of the switching transistor T1 is electrically connected to the data signal terminal Data
  • the second pole (the other one of the source and drain) of the switching transistor T1 ) is electrically connected to the first node G.
  • the switching transistor T1 may transmit the data signal received at the data signal terminal Data to the first node G in response to the first gate signal received at the first gate signal terminal G1, that is, the switching transistor T1 is turned on.
  • the data signal may specifically include a detection data signal and a display data signal.
  • the control electrode of the driving transistor T2 is electrically connected to the first node G
  • the first electrode of the driving transistor T2 is electrically connected to the fourth voltage signal terminal ELVDD
  • the second electrode of the driving transistor T2 is electrically connected to the second node S.
  • the driving transistor T2 is turned on under the control of the voltage of the node G, and can transmit the fourth voltage signal received at the fourth voltage signal terminal ELVDD to the second node S.
  • the first end of the storage capacitor Cst is electrically connected to the first node G, and the second end is electrically connected to the second node S. Therefore, in the process of charging the first node G, the switching transistor T1 can simultaneously charge the storage capacitor Cst.
  • the anode of the light emitting device (OLED) is electrically connected to the second node S, and the cathode is electrically connected to the fifth voltage signal terminal ELVSS, so that the fourth voltage signal from the second node S and the fifth voltage signal terminal ELVSS can transmit Lighting is performed under the cooperation of the fifth voltage signals.
  • the control electrode of the sensing transistor T3 is electrically connected to the second gate signal terminal G2, the first electrode is electrically connected to the second node S, and the second electrode is electrically connected to the sensing signal terminal Sense.
  • the sensing transistor T3 may detect the electrical characteristic of the driving transistor T2 to achieve external compensation in response to the second gate signal received at the second gate signal terminal G2.
  • the electrical characteristic may include one or both of a threshold voltage and carrier mobility of the drive transistor T2.
  • the sensing signal terminal Sense can provide a reset signal or obtain a sensing signal, wherein the reset signal is used to reset the second node S, and the obtained sensing signal is used to obtain the threshold voltage of the driving transistor T2.
  • the first gate signal received at the first gate signal terminal G1 and the second gate signal received at the second gate signal terminal G2 by each subpixel may be the same.
  • a plurality of pixel circuits in the same row of sub-pixels can be electrically connected with two gate lines (formed by the gate layer 20 as shown in FIG. 3 ), and the two gate lines transmit the same electrical signals.
  • multiple pixel circuits in the same row of sub-pixels may be electrically connected to one gate line.
  • the display phase of a frame may include a display period and a blanking period that are performed in sequence.
  • the working process of the sub-pixel may include, for example, a reset phase, a data writing phase, and a light-emitting phase.
  • the thin film transistors are all N-type transistors as an example for description:
  • the level of the second gate signal provided by the second gate signal terminal G2 is high, and the sensing signal terminal Sense provides a reset signal (for example, the level of the reset signal is low) level).
  • the sensing transistor T3 is turned on under the control of the second gate signal, receives the reset signal, and transmits the reset signal to the second node S to reset the second node S.
  • the level of the first gate signal provided by the first gate signal terminal G1 is high level
  • the level of the display data signal provided by the data signal terminal Data is high level.
  • the switch transistor T1 is turned on under the control of the first gate signal, receives the display data signal, transmits the display data signal to the first node G, and charges the storage capacitor Cst at the same time.
  • the level of the first gate signal provided by the first gate signal terminal G1 is low level
  • the level of the second gate signal provided by the second gate signal terminal G2 is low level
  • the level of the fourth voltage signal provided by the fourth voltage signal terminal ELVDD is a high level.
  • the switching transistor T1 is turned off under the control of the first gate signal
  • the sensing transistor T3 is turned off under the control of the second gate signal.
  • the storage capacitor Cst starts to discharge, so that the voltage of the first node G remains at a high level.
  • the driving transistor T2 is turned on under the control of the voltage of the first node G, receives the fourth voltage signal, and transmits the fourth voltage signal to the second node S, so that the light-emitting device is connected to the fourth voltage signal and the fifth voltage signal terminal Lighting is performed under the cooperation of the fifth voltage signal transmitted by the ELVSS.
  • the working process of the sub-pixels in the blanking period in a frame display stage may include: a first stage and a second stage.
  • the level of the first gate signal provided by the first gate signal terminal G1 and the level of the second gate signal provided by the second gate signal terminal G2 are both high levels, and the data signal terminal
  • the level of the detected data signal provided by Data is a high level.
  • the switching transistor T1 is turned on under the control of the first gate signal, receives the detection data signal, and transmits the detection data signal to the first node G to charge the first node G.
  • the sensing transistor T3 is turned on under the control of the second gate signal, the receiving sensing signal terminal Sense provides a reset signal, and transmits the reset signal to the second node S.
  • the sensing signal terminal Sense is in a floating state.
  • the driving transistor T2 is turned on under the control of the voltage of the first node G, receives the fourth voltage signal provided by the fourth voltage signal terminal ELVDD, and transmits the fourth voltage signal to the second node S, to the second node S Charging is performed so that the voltage of the second node S increases until the driving transistor T2 is turned off. At this time, the voltage difference Vgs between the first node G and the second node S is equal to the threshold voltage Vth of the driving transistor T2.
  • the sensing signal terminal Sense Since the sensing transistor T3 is in an on state and the sensing signal terminal Sense is in a floating state, during the process of charging the second node S by the driving transistor T2, the sensing signal terminal Sense is also charged at the same time.
  • the threshold voltage Vth of the driving transistor T2 By sampling the voltage of the sensing signal terminal Sense (that is, obtaining the sensing signal), the threshold voltage Vth of the driving transistor T2 can be calculated according to the relationship between the voltage of the sensing signal terminal Sense and the level of the detection data signal. . After the threshold voltage Vth of the driving transistor T2 is obtained by calculation, the threshold voltage Vth can be compensated into the display data signal of the display period in the next frame display stage, so as to complete the external compensation for the sub-pixels.
  • the gate driving circuit may include a multi-stage cascaded shift register 1230 , and one stage of the shift register may be electrically connected to a plurality of pixel circuits in a row of sub-pixels.
  • the first gate signal transmitted by the first gate signal terminal G1 and the second gate signal transmitted by the second gate signal terminal G2 may both be provided by the gate driving circuit, and the gate
  • Each stage of the shift register 1230 in the driving circuit can be electrically connected to the first gate signal terminal G1 through the first gate line, and the first gate signal is transmitted to the first gate signal terminal G1 through the first gate line, and the first gate signal is transmitted through the first gate line.
  • the second gate line is electrically connected to the second gate signal terminal G2, and the second gate signal is transmitted to the second gate signal terminal G2 through the second gate line.
  • the structure of the above-mentioned shift register 1230 is not particularly limited, and can be selected and set according to actual needs.
  • the structure of the shift register of the two structures is schematically described below, but it cannot be understood as a limitation on the shift register 1230:
  • the shift register 1230 may include: a first input circuit 3101 , an anti-leakage circuit 3102 , an output circuit 3103 , a control circuit 3104 , a first reset circuit 3105 , and a second reset circuit 3106 , a third reset circuit 3107 , a fourth reset circuit 3108 and a fifth reset circuit 3109 .
  • the first input circuit 3101 is electrically connected to the input signal terminal (abbreviated as Iput in the drawings and hereinafter), the pull-up node Q ⁇ N> and the leakage prevention node OFF ⁇ N>. .
  • the first input circuit 3101 can transmit the input signal to the pull-up node Q ⁇ N> based on the input signal received at the input signal terminal Iput during the display period in the one-frame display stage.
  • N is a positive integer, expressed as the number of rows of sub-pixels.
  • the first input circuit 3101 can be turned on under the action of the input signal, and transmit the input signal to the pull-up node Q ⁇ N>, to the pull-up node Q ⁇ N> is charged, causing the voltage of the pull-up node Q ⁇ N> to rise.
  • the first input circuit 3101 may specifically include a first transistor M1 and a second transistor M2.
  • the control pole of the first transistor M1 is electrically connected to the input signal terminal Iput
  • the first pole of the first transistor M1 is electrically connected to the input signal terminal Iput
  • the second pole of the first transistor M1 is electrically connected to the first pole and the second pole of the second transistor M2.
  • An anti-leakage node OFF1 is electrically connected.
  • the control electrode of the second transistor M2 is electrically connected to the input signal terminal Iput
  • the second electrode of the second transistor M2 is electrically connected to the first pull-up node Q1.
  • the first transistor M1 and the second transistor M2 can be simultaneously turned on under the action of the input signal.
  • the first transistor M1 can receive the input signal transmitted by the input signal terminal Iput, and transmit the received input signal to the first electrode of the second transistor M2 and the leakage prevention node OFF ⁇ N>.
  • the second transistor M2 may transmit the received input signal to the pull-up node Q ⁇ N>, charge the pull-up node Q ⁇ N>, and increase the voltage of the pull-up node Q ⁇ N>.
  • the leakage prevention circuit 3102 may be electrically connected to the pull-up node Q ⁇ N>, the first voltage signal terminal VDD, and the leakage prevention node OFF ⁇ N>.
  • the anti-leakage circuit 3102 can transmit the first voltage signal transmitted from the first voltage signal terminal VDD to the anti-leakage node OFF ⁇ N> under the control of the voltage of the pull-up node Q ⁇ N> to prevent the pull-up of the node Q ⁇ N> leakage: Specifically, leakage of the pull-up node Q ⁇ N> through the first input circuit 3101 can be avoided, so that the pull-up node Q ⁇ N> can maintain a relatively high and relatively stable voltage.
  • the first voltage signal may be a constant high voltage signal.
  • the leakage prevention circuit 3102 can be turned on under the control of the voltage of the pull-up node Q ⁇ N>, and receives and transmits the first voltage signal to the anti-leakage circuit 3102.
  • the leakage node OFF ⁇ N> increases the voltage of the leakage prevention node OFF ⁇ N>.
  • the anti-leakage circuit 3102 may specifically include a third transistor M3, the control electrode of the third transistor M3 is electrically connected to the pull-up node Q ⁇ N>, the first electrode of the third transistor M3 is electrically connected to the first voltage signal terminal VDD, and the third transistor M3 is electrically connected to the pull-up node Q ⁇ N>.
  • the second pole of the transistor M3 is electrically connected to the leakage prevention node OFF ⁇ N>. Therefore, when the voltage of the pull-up node Q ⁇ N> is at a high level, the third transistor M3 can be turned on under the control of the voltage of the pull-up node Q ⁇ N>, and transmits the first voltage signal to the anti-
  • the leakage node OFF ⁇ N> increases the voltage of the leakage prevention node OFF ⁇ N>, and makes the voltage difference between the control electrode and the first electrode of the second transistor M2 less than zero, ensuring that the second transistor M2 is completely or relatively Completely cut off.
  • the output circuit 3103 is connected to the pull-up node Q ⁇ N>, the first clock signal terminal CLKE_1 and the first output signal terminal Output1 ⁇ N> (abbreviated as Oput1 in the drawings and below). ⁇ N>) electrical connection.
  • the output circuit 3103 can transmit the first clock signal received at the first clock signal terminal CLKE_1 to the first output signal under the control of the voltage of the pull-up node Q ⁇ N> during the display period in the one-frame display stage. terminal Oput1 ⁇ N>.
  • the output circuit 3103 may also be electrically connected to the third clock signal terminal CLKD_1 and the shift signal terminal CR ⁇ N>, for example.
  • the output circuit 3103 can also transmit the third clock signal received at the third clock signal terminal CLKD_1 to the shifter under the control of the voltage of the pull-up node Q ⁇ N> during the display period in the one-frame display stage.
  • the exemplary output circuit 3103 may also be electrically connected to the fourth clock signal terminal CLKF_1 and the second output signal terminal Output2 ⁇ N> (abbreviated as Oput2 ⁇ N> in the drawings and below). During the blanking period in the one-frame display phase, the output circuit 3103 can transmit the fourth clock signal received at the fourth clock signal terminal CLKF_1 to the second output signal under the control of the voltage of the pull-up node Q ⁇ N> terminal Oput2 ⁇ N>.
  • the output circuit 3103 may be turned on under the control of the voltage of the pull-up node Q ⁇ N>, and the output circuit 3103 may be turned on under the control of the voltage of the pull-up node Q ⁇ N>, and will
  • the third clock signal is used as a shift signal and is output from the shift signal terminal CR ⁇ N>; the first clock signal received at the first clock signal terminal CLKE_1 is used as the first output signal, which is output from the first output signal terminal Oput1 ⁇ N > output.
  • the output circuit 3103 can be turned on under the control of the voltage of the pull-up node Q ⁇ N>, and will be turned on in the first
  • the fourth clock signal received at the four clock signal terminal CLKF_1 is used as the second output signal, and is output from the second output signal terminal Oput2 ⁇ N>.
  • the first output signal terminal Oput1 ⁇ N> can be electrically connected to the first gate line, and the first output signal output by the first output signal terminal Oput1 ⁇ N> can be used as the first gate signal, which is sequentially passed through the first gate line.
  • the line and the first gate signal terminal G1 are transmitted to the pixel circuit 12 .
  • the second output signal terminal Oput2 ⁇ N> can be electrically connected to the second gate line, and the second output signal output by the second output signal terminal Oput2 ⁇ N> can be used as the second gate signal, which is sequentially passed through the second gate line and the second gate line.
  • the gate signal terminal G2 is transmitted to the pixel circuit.
  • the output circuit 3103 may include a fourth transistor M4 , a fifth transistor M5 , a sixth transistor M6 , a first capacitor C1 and a second capacitor C2 .
  • the control pole of the fourth transistor M4 is electrically connected to the pull-up node Q ⁇ N>
  • the first pole of the fourth transistor M4 is electrically connected to the third clock signal terminal CLKD_1
  • the second pole of the fourth transistor M4 is electrically connected to the shift signal terminal CR ⁇ N> Electrical connection.
  • the fourth transistor M4 may be at the high of the pull-up node Q ⁇ N> It is turned on under the control of the voltage, transmits the third clock signal to the shift signal terminal CR ⁇ N>, and outputs the third clock signal as the shift signal from the shift signal terminal CR ⁇ N>.
  • the control pole of the fifth transistor M5 is electrically connected to the pull-up node Q ⁇ N>, the first pole of the fifth transistor M5 is electrically connected to the first clock signal terminal CLKE_1, and the second pole of the fifth transistor M5 is electrically connected to the first output signal terminal Oput1 ⁇ N> is electrically connected.
  • the first terminal of the first capacitor C1 is electrically connected to the pull-up node Q ⁇ N>, and the second terminal of the first capacitor C1 is electrically connected to the first output signal terminal Oput1 ⁇ N>.
  • the first capacitor C1 is charged while the first input circuit 3101 is turned on so that the voltage of the pull-up node Q ⁇ N> rises.
  • the first capacitor C1 can be discharged, so that the pull-up node Q ⁇ N> is kept at a high level, so that the fifth transistor M5 can be kept on, and the first clock
  • the signal is transmitted to the first output signal terminal Oput1 ⁇ N>, and the first clock signal is output from the first output signal terminal Oput1 ⁇ N> as the first output signal.
  • control pole of the sixth transistor M6 is electrically connected to the pull-up node Q ⁇ N>
  • first pole of the sixth transistor M6 is electrically connected to the fourth clock signal terminal CLKF_1
  • second pole of the sixth transistor M6 is electrically connected to the fourth clock signal terminal CLKF_1.
  • the two output signal terminals Oput2 ⁇ N> are electrically connected.
  • the first terminal of the second capacitor C2 is electrically connected to the pull-up node Q ⁇ N>, and the second terminal of the second capacitor C2 is electrically connected to the second output signal terminal Oput2 ⁇ N>.
  • the second capacitor C2 is charged while the voltage of the pull-up node Q ⁇ N> rises.
  • the second capacitor C2 can be discharged, so that the pull-up node Q ⁇ N> is kept at a high level, so that the sixth transistor M6 can be kept in an on state to transmit the fourth clock signal to the second output signal terminal Oput2 ⁇ N>, and the fourth clock signal is output from the second output signal terminal Oput2 ⁇ N> as a second output signal.
  • the shift signal terminal CR ⁇ N> in the Nth stage shift register can be shifted, for example, with the N+1th stage
  • the input signal terminal Iput in the register is electrically connected, and the shift signal output by the shift signal terminal CR ⁇ N> of the Nth stage shift register is used as the input signal in the N+1th stage shift register 21 .
  • the cascade relationship of the multi-stage shift registers is not limited to this, and those skilled in the art can design according to the actual situation.
  • the input signal terminal Iput of a part of the shift register 1230 may also be electrically connected to the start signal terminal STU, that is, the start signal transmitted by the start signal terminal STU is received as the input signal.
  • the part of the shift register may be the first-stage shift register in the gate driving circuit, or may be the first-stage shift register and the second-stage shift register, or the like.
  • the number of shift registers electrically connected to the start signal end STU is not limited, and those skilled in the art can select and set according to actual needs.
  • the control circuit 3104 is electrically connected to the pull-up node Q ⁇ N>, the sixth voltage signal terminal VDD_A, the pull-down node QB_A and the second voltage signal terminal VGL1 .
  • the control circuit 3104 is configured to control the voltage of the pull-down node QB_A under the control of the voltage of the pull-up node Q ⁇ N> and the sixth voltage signal transmitted by the sixth voltage signal terminal VDD_A.
  • the level of the sixth voltage signal may, for example, be unchanged during the display phase of one frame.
  • the second voltage signal terminal VGL1 may be configured to transmit a DC low-level signal (eg, lower than or equal to the low-level portion of the clock signal).
  • the second voltage signal terminal VGL1 can be grounded, for example.
  • the control circuit 3104 can transmit the second voltage signal transmitted by the second voltage signal terminal VGL1 to the pull-down node QB_A, and pull the voltage of the pull-down node QB_A down to low voltage.
  • the control circuit 3104 can transmit the sixth voltage signal transmitted by the sixth voltage signal terminal VDD_A to the pull-down node QB_A, and pull the voltage of the pull-down node QB_A to high level.
  • the control circuit 3104 may include: a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, and a tenth transistor M10.
  • the control pole of the seventh transistor M7 is electrically connected to the sixth voltage signal terminal VDD_A
  • the first pole of the seventh transistor M7 is electrically connected to the sixth voltage signal terminal VDD_A
  • the second pole of the seventh transistor M7 is electrically connected to the control pole of the eighth transistor M8
  • the electrode is electrically connected to the first electrode of the ninth transistor M9.
  • the first electrode of the eighth transistor M8 is electrically connected to the sixth voltage signal terminal VDD_A
  • the second electrode of the eighth transistor M8 is electrically connected to the pull-down node QB_A and the first electrode of the tenth transistor M10 .
  • the control electrode of the ninth transistor M9 is electrically connected to the pull-up node Q ⁇ N>, and the second electrode of the ninth transistor M9 is electrically connected to the second voltage signal terminal VGL1.
  • the control electrode of the tenth transistor M10 is electrically connected to the pull-up node Q ⁇ N>, and the second electrode of the tenth transistor M10 is electrically connected to the second voltage signal terminal VGL1.
  • the seventh transistor M7 can be turned on under the action of the sixth voltage signal to receive and transmit the sixth voltage
  • the signal is sent to the control electrode of the eighth transistor M8 and the first electrode of the ninth transistor M9.
  • the eighth transistor M8 can be turned on under the action of the sixth voltage signal, and receives and transmits the sixth voltage signal to the pull-down node QB_A and the first pole of the tenth transistor M10.
  • the ninth transistor M9 and the tenth transistor M10 may be turned on under the control of the voltage of the pull-up node Q ⁇ N>, and the ninth transistor M9 may turn on
  • the second voltage signal transmitted by the second voltage signal terminal VGL1 is transmitted to the control electrode of the eighth transistor M8, so that the eighth transistor M8 is turned off, and the tenth transistor M10 can transmit the second voltage signal to the pull-down node QB_A, and the pull-down node The voltage of QB_A is pulled low.
  • the ninth transistor M9 and the tenth transistor M10 may be turned off under the control of the voltage of the pull-up node Q ⁇ N>, and the eighth transistor M8 may turn off
  • the received sixth voltage signal is transmitted to the pull-down node QB_A, and the voltage of the pull-down node QB_A is pulled up to a high level.
  • the first reset circuit 3105 is electrically connected to the pull-down node QB_A, the pull-up node Q ⁇ N>, the second voltage signal terminal VGL1 and the leakage prevention node OFF ⁇ N>.
  • the first reset circuit 3105 can reset the pull-up node Q ⁇ N> under the control of the voltage of the pull-down node QB_A:
  • the first reset circuit 3105 When the voltage of the pull-down node QB_A is at a high level, the first reset circuit 3105 can be turned on under the action of the voltage of the pull-down node QB_A, and transmit the second voltage signal transmitted by the second voltage signal terminal VGL1 to the pull-up node Q ⁇ N>, pull-down reset for pull-up node Q ⁇ N>.
  • the first reset circuit 3105 may include: an eleventh transistor M11 and a twelfth transistor M12.
  • the control electrode of the eleventh transistor M11 is electrically connected to the pull-down node QB_A, the first electrode of the eleventh transistor M11 is electrically connected to the pull-up node Q ⁇ N>, and the second electrode of the eleventh transistor M11 is electrically connected to the twelfth transistor M12
  • the first pole and the anti-leakage node OFF ⁇ N> are electrically connected.
  • the control electrode of the twelfth transistor M12 is electrically connected to the pull-down node QB_A, and the second electrode of the twelfth transistor M12 is electrically connected to the second voltage signal terminal VGL1.
  • the eleventh transistor M11 and the twelfth transistor M12 may be simultaneously turned on under the action of the voltage of the pull-down node QB_A, and the twelfth transistor M12 may transmit the second voltage signal
  • the second voltage signal transmitted from the terminal VGL1 is transmitted to the anti-leakage node OFF ⁇ N>, and the eleventh transistor M11 can transmit the second voltage signal from the anti-leakage node OFF ⁇ N> to the pull-up node Q ⁇ N>. Pull node Q ⁇ N> to reset.
  • the third transistor M3 When the potential of the pull-up node Q ⁇ N> is at a high potential and the first reset circuit 3105 is in an inactive state, the third transistor M3 can be turned on under the control of the voltage of the pull-up node Q ⁇ N>, The first voltage signal is transmitted to the leakage prevention node OFF ⁇ N>, so that the voltage of the leakage prevention node OFF ⁇ N> is increased, so that the voltage difference between the control electrode and the second electrode of the eleventh transistor M11 is less than zero, It is ensured that the eleventh transistor M11 is completely or more completely turned off. Therefore, the leakage of the pull-up node Q ⁇ N> through the first reset circuit 3105 can be avoided, so that the pull-up node Q ⁇ N> can maintain a relatively high and stable voltage.
  • the second reset circuit 3106 may be electrically connected to the display reset signal terminal STD, the pull-up node Q ⁇ N>, the second voltage signal terminal VGL1 and the leakage prevention node OFF ⁇ N>.
  • the second reset circuit 3106 can reset the pull-up node Q ⁇ N> under the control of the display reset signal transmitted from the display reset signal terminal STD:
  • the second reset circuit 3106 When the level of the display reset signal is high, the second reset circuit 3106 can be turned on under the action of the display reset signal to transmit the second voltage signal transmitted from the second voltage signal terminal VGL1 to the pull-up node Q ⁇ N>, pull-down reset is performed on the pull-up node Q ⁇ N>.
  • the second reset circuit 3106 may include a thirteenth transistor M13 and a fourteenth transistor M14.
  • the control electrode of the thirteenth transistor M13 is electrically connected to the display reset signal terminal STD
  • the first electrode of the thirteenth transistor M13 is electrically connected to the pull-up node Q ⁇ N>
  • the second electrode of the thirteenth transistor M13 is electrically connected to the fourteenth transistor M13.
  • the first electrode of the transistor M14 is electrically connected to the leakage prevention node OFF ⁇ N>.
  • the control electrode of the fourteenth transistor M14 is electrically connected to the display reset signal terminal STD, and the second electrode of the fourteenth transistor M14 is electrically connected to the second voltage signal terminal VGL1.
  • the thirteenth transistor M13 and the fourteenth transistor M14 can be turned on at the same time under the action of the display reset signal, and the fourteenth transistor M14 can connect the second voltage signal terminal VGL1
  • the transmitted second voltage signal is transmitted to the anti-leakage node OFF ⁇ N>, and the thirteenth transistor M13 can transmit the second voltage signal from the anti-leakage node OFF ⁇ N> to the pull-up node Q ⁇ N>, to the pull-up node.
  • Q ⁇ N> is reset.
  • the third transistor M3 can be controlled by the voltage of the pull-up node Q ⁇ N> is turned on, and the first voltage signal is transmitted to the leakage prevention node OFF ⁇ N>, so that the voltage of the leakage prevention node OFF ⁇ N> increases, thereby making the voltage difference between the control electrode and the second electrode of the thirteenth transistor M13 Less than zero ensures that the thirteenth transistor M13 is completely or more completely turned off. In this way, leakage of the pull-up node Q ⁇ N> through the second reset circuit 3106 can be avoided, so that the pull-up node Q ⁇ N> can maintain a relatively high and stable voltage.
  • the display reset signal terminal STD of the Nth stage shift register 1230 can be, for example, connected with the shift signal terminal CR of the N+4th stage shift register.
  • N> is electrically connected, so that the shift signal output by the shift signal terminal CR ⁇ N> of the N+4th stage shift register is used as the display reset signal of the Nth stage shift register.
  • the third reset circuit 3107 may be electrically connected to the global reset signal terminal TRST, the pull-up node Q ⁇ N>, the second voltage signal terminal VGL1 and the leakage prevention node OFF ⁇ N>. . Therefore, the third reset circuit 3107 can reset the pull-up node Q ⁇ N> under the control of the global reset signal transmitted from the global reset signal terminal TRST:
  • the third reset circuit 3107 can be turned on under the action of the global reset signal, and transmit the second voltage signal transmitted by the second voltage signal terminal VGL1 to the pull-up Node Q ⁇ N>, pull-down reset is performed on the pull-up node Q ⁇ N>.
  • the third reset circuit 3107 may include: a fifteenth transistor M15 and a sixteenth transistor M16.
  • the control electrode of the fifteenth transistor M15 is electrically connected to the global reset signal terminal TRST, the first electrode of the fifteenth transistor M15 is electrically connected to the pull-up node Q ⁇ N>, the second electrode of the fifteenth transistor M15 is electrically connected to the sixteenth transistor M15 The first electrode of the transistor M16 is electrically connected to the leakage prevention node OFF ⁇ N>.
  • the control electrode of the sixteenth transistor M16 is electrically connected to the global reset signal terminal TRST, and the second electrode of the sixteenth transistor M16 is electrically connected to the second voltage signal terminal VGL1.
  • the fifteenth transistor M15 and the sixteenth transistor M16 can be turned on simultaneously under the action of the global reset signal, and the sixteenth transistor M16 can connect the second voltage signal terminal VGL1
  • the transmitted second voltage signal is transmitted to the anti-leakage node OFF ⁇ N>, and the fifteenth transistor M15 can transmit the fifth voltage signal from the anti-leakage node OFF ⁇ N> to the pull-up node Q ⁇ N>, to the pull-up node.
  • Q ⁇ N> is reset.
  • the third transistor M3 can be controlled by the voltage of the pull-up node Q ⁇ N> is turned on, and the first voltage signal is transmitted to the leakage prevention node OFF ⁇ N>, so that the voltage of the leakage prevention node OFF ⁇ N> increases, thereby making the voltage difference between the control electrode and the second electrode of the fifteenth transistor M15 Less than zero ensures that the fifteenth transistor M15 is completely or more completely turned off. In this way, leakage of the pull-up node Q ⁇ N> through the third reset circuit 3107 can be avoided, so that the pull-up node Q ⁇ N> can maintain a relatively high and stable voltage.
  • the fourth reset circuit 3108 may be connected to the pull-down node QB_A, the shift signal terminal CR ⁇ N>, the first output signal terminal Oput1 ⁇ N>, the second output signal terminal Oput2 ⁇ N>, The second voltage signal terminal VGL1 and the third voltage signal terminal VGL2 are electrically connected.
  • the fourth reset circuit 3108 can reset the shift signal terminal CR ⁇ N>, the first output signal terminal Oput1 ⁇ N> and the second output signal terminal Oput2 ⁇ N> under the control of the voltage of the pull-down node QB_A.
  • the third voltage signal terminal VGL2 is configured to transmit a DC low-level signal (eg, lower than or equal to the low-level portion of the clock signal).
  • the third voltage signal terminal VGL2 can be grounded, for example.
  • the low-level signals transmitted by the second voltage signal terminal VGL1 and the third voltage signal terminal VGL2 may be equal or unequal.
  • the fourth reset circuit 3108 can be turned on under the action of the voltage of the pull-down node QB_A to transmit the second voltage signal transmitted by the second voltage signal terminal VGL1 to the shift signal terminal CR ⁇ N>, pull-down reset is performed on the shift signal terminal CR ⁇ N>, and the third voltage signal transmitted by the third voltage signal terminal VGL2 is transmitted to the first output signal terminal Oput1 ⁇ N>.
  • the first output signal terminal Oput1 ⁇ N> is pulled down to reset, the third voltage signal transmitted by the third voltage signal terminal VGL2 is transmitted to the second output signal terminal Oput2 ⁇ N>, and the second output signal terminal Oput2 ⁇ N> is subjected to pull-down reset. Pull down to reset.
  • the fourth reset circuit 3108 may include: a seventeenth transistor M17, an eighteenth transistor M18 and a nineteenth transistor M19.
  • the control electrode of the seventeenth transistor M17 is electrically connected to the pull-down node QB_A
  • the first electrode of the seventeenth transistor M17 is electrically connected to the shift signal terminal CR ⁇ N>
  • the second electrode of the seventeenth transistor M17 is electrically connected to the second voltage signal
  • the terminal VGL1 is electrically connected.
  • the seventeenth transistor M17 can be turned on under the action of the voltage of the pull-down node QB_A to transmit the second voltage signal transmitted from the second voltage signal terminal VGL1 to the shift
  • the signal terminal CR ⁇ N> performs pull-down reset on the shift signal terminal CR ⁇ N>.
  • the control electrode of the eighteenth transistor M18 is electrically connected to the pull-down node QB_A, the first electrode of the eighteenth transistor M18 is electrically connected to the first output signal terminal Oput1 ⁇ N>, and the second electrode of the eighteenth transistor M18 is electrically connected to the third voltage
  • the signal terminal VGL2 is electrically connected.
  • the eighteenth transistor M18 can be turned on under the action of the voltage of the pull-down node QB_A to transmit the third voltage signal transmitted from the third voltage signal terminal VGL2 to the first
  • the output signal terminal Oput1 ⁇ N> performs pull-down reset on the first output signal terminal Oput1 ⁇ N>.
  • the control electrode of the nineteenth transistor M19 is electrically connected to the pull-down node QB_A
  • the first electrode of the nineteenth transistor M19 is electrically connected to the second output signal terminal Oput2 ⁇ N>
  • the second electrode of the nineteenth transistor M19 is electrically connected to the third voltage
  • the signal terminal VGL2 is electrically connected.
  • the nineteenth transistor M19 can be turned on under the action of the voltage of the pull-down node QB_A, and transmits the third voltage signal transmitted from the third voltage signal terminal VGL2 to the second
  • the output signal terminal Oput2 ⁇ N> performs pull-down reset on the second output signal terminal Oput2 ⁇ N>.
  • the fifth reset circuit 3109 is electrically connected to the input signal terminal Iput, the pull-down node QB_A and the second voltage signal terminal VGL1.
  • the fifth reset circuit 3109 can reset the pull-down node QB_A under the control of the input signal transmitted by the input signal terminal Iput:
  • the fifth reset circuit 3109 can be turned on under the action of the input signal, and transmit the second voltage signal transmitted by the second voltage signal terminal VGL1 to the pull-down node QB_A , perform pull-down reset on pull-down node QB_A.
  • the fifth reset circuit 3109 may include: a twentieth transistor M20.
  • the control electrode of the twentieth transistor M20 is electrically connected to the input signal terminal Iput, the first electrode of the twentieth transistor M20 is electrically connected to the pull-down node QB_A, and the second electrode of the twentieth transistor M20 is electrically connected to the second voltage signal terminal VGL1 .
  • the twentieth transistor M20 can be turned on under the action of the input signal, and transmits the second voltage signal transmitted by the second voltage signal terminal VGL1 to the pull-down node QB_A. Pull down node QB_A for pull down reset.
  • the gate drive circuit may also include a plurality of blanking input circuits 3200 .
  • a blanking input circuit may be electrically connected to the adjacent at least two-stage shift registers. In other words, at least two shift registers can share a blanking input circuit.
  • the blanking input circuit can control the corresponding shift register to input a blanking control signal to the pixel circuit of the corresponding row during the blanking period of a frame display stage, so that the pixel circuit obtains the sensing signal:
  • the blanking input circuit 3200 may include, for example, a selection control circuit 3201 , a second input circuit 3202 and at least two transmission circuits 3203 .
  • the selection control circuit 3201 is electrically connected to the selection control signal terminal OE, the shift signal terminal CR ⁇ N>, the second voltage signal terminal VGL1 and the first blanking node H, and controls the selection control signal transmitted at the selection control signal terminal OE Next, the shift signal received at the shift signal terminal CR ⁇ N> is transmitted to the first blanking node H.
  • the selection control circuit 3201 when the level of the selection control signal is high, the selection control circuit 3201 can be turned on under the control of the selection control signal, and transmit the received shift signal to the first blanking node H , the first blanking node H is charged, so that the voltage of the first blanking node H increases.
  • the waveform timing of the selection control signal can be the same as the waveform timing of the input signal, so that the selection control circuit 3201 is turned on.
  • the selection control circuit 3201 may include: a twenty-first transistor M21, a twenty-second transistor M22, and a third capacitor C3.
  • the control pole of the twenty-first transistor M21 is electrically connected to the selection control signal terminal OE, the first pole of the twenty-first transistor M21 is electrically connected to the shift signal terminal CR ⁇ N>, and the second pole of the twenty-first transistor M21 It is electrically connected to the first pole of the twenty-second transistor M22.
  • the control electrode of the twenty-second transistor M22 is electrically connected to the selection control signal terminal OE, and the second electrode of the twenty-second transistor M22 is electrically connected to the first blanking node H.
  • the twenty-first transistor M21 and the twenty-second transistor M22 can be turned on at the same time under the action of the selection control signal, and the second transistor M21 can be turned on at the same time.
  • the eleventh transistor M21 can transmit the shift signal transmitted by the shift signal terminal CR ⁇ N> to the first pole of the twenty-second transistor M22, and the twenty-second transistor M22 can receive and transmit the shift signal to the first terminal.
  • the hidden node H charges the first blanking node H.
  • the first terminal of the third capacitor C3 is electrically connected to the first blanking node H, and the second terminal of the third capacitor C3 is electrically connected to the second voltage signal terminal VGL1.
  • the third capacitor C3 is also charged. In this way, when the selection control circuit 3201 is turned off, the third capacitor C3 can be used to discharge, so that the first blanking node H is kept at a high level.
  • the selection control circuit 3201 may further include, for example, a twenty-third transistor M23.
  • the control pole of the twenty-third transistor M23 is electrically connected to the first blanking node H
  • the first pole of the twenty-third transistor M23 is electrically connected to the first voltage signal terminal VDD
  • the second pole of the twenty-third transistor M23 is electrically connected to The first electrode of the twenty-second transistor M22 is electrically connected.
  • the twenty-third transistor M23 can be at the first blanking node It is turned on under the control of the voltage of H, and the first voltage signal transmitted by the first voltage signal terminal VDD is transmitted to the first pole of the twenty-second transistor M22, so that the voltage of the first pole of the twenty-second transistor M22 rises high, so that the voltage difference between the control electrode and the first electrode of the twenty-second transistor M22 is less than zero, ensuring that the twenty-second transistor M22 is completely or relatively completely turned off. In this way, leakage of the first blanking node H through the twenty-second transistor M22 can be avoided, so that the first blanking node H can maintain a relatively high and stable voltage.
  • the second input circuit 3202 is electrically connected to the first blanking node H, the second blanking node N, and the second clock signal terminal CLKA or the first voltage signal terminal VDD, so as to be at the first blanking node Under the control of the voltage of H, the second clock signal received at the second clock signal terminal CLKA or the first voltage signal received at the first voltage signal terminal VDD is transmitted to the second blanking node N.
  • the second input circuit 3202 can be turned on under the control of the voltage of the first blanking node H to receive the second clock
  • the second clock signal transmitted by the signal terminal CLKA is transmitted to the second blanking node N.
  • the second input circuit 3202 may include: a twenty-fourth transistor M24.
  • the control electrode of the twenty-fourth transistor M24 is electrically connected to the first blanking node H
  • the first electrode of the twenty-fourth transistor M24 is electrically connected to the second clock signal terminal CLKA or the first voltage signal terminal VDD
  • the twenty-fourth transistor M24 is electrically connected to the second clock signal terminal CLKA or the first voltage signal terminal VDD.
  • the second pole of the transistor M24 is electrically connected to the second blanking node N.
  • the twenty-fourth transistor M24 may be turned on under the control of the voltage of the first blanking node H, and will receive the signal received at the fourth clock signal terminal CLKA.
  • the fourth clock signal or the first voltage signal received at the first voltage signal terminal VDD is transmitted to the second blanking node N.
  • the above-mentioned at least two transmission circuits 3203 may be electrically connected to the at least two shift registers in a one-to-one correspondence.
  • a transmission circuit 3203 is electrically connected to the second blanking node N, the second clock signal terminal CLKA, and the pull-up node Q ⁇ N> of the first-stage shift register.
  • the transmission circuit 3202 is configured to, under the control of the second clock signal transmitted by the second clock signal terminal CLKA, transmit the second clock signal or the first voltage signal received at the second blanking node N to the pull-up Node Q ⁇ N>.
  • the transmission circuit 3202 can be turned on under the control of the second clock signal, and the second blanking node
  • the second clock signal or the first voltage signal is received at N, and the received second clock signal or the first voltage signal is transmitted to the pull-up node Q ⁇ N>, so that the voltage of the pull-up node Q ⁇ N> is increased, and then the The output circuit 3103 is turned on, so that the second output signal terminal Oput2 ⁇ N> of the output circuit 3103 outputs the second output signal.
  • the transmission circuit 3203 may include: a twenty-fifth transistor M25 and a twenty-sixth transistor M26.
  • the control pole of the twenty-fifth transistor M25 is electrically connected to the second clock signal terminal CLKA, the first pole of the twenty-fifth transistor M25 is electrically connected to the second blanking node N, and the second pole of the twenty-fifth transistor M25 is electrically connected to the second blanking node N.
  • the first pole of the twenty-sixth transistor M26 is electrically connected.
  • the control electrode of the twenty-sixth transistor M26 is electrically connected to the second clock signal terminal CLKA, and the second electrode of the twenty-sixth transistor M26 is electrically connected to the pull-up node Q ⁇ N>.
  • the twenty-fifth transistor M25 and the twenty-sixth transistor M26 can be under the action of the second clock signal Turned on at the same time, the twenty-fifth transistor M25 can transmit the second clock signal or the first voltage signal from the second blanking node N to the first pole of the twenty-sixth transistor M26, and the twenty-sixth transistor M26 can receive And transmit the second clock signal or the first voltage signal to the pull-up node Q ⁇ N> to charge the pull-up node Q ⁇ N>.
  • the sixth transistor M6 in the output circuit 3103 can be turned on under the control of the voltage of the pull-up node Q ⁇ N>, receives the fourth clock signal, and uses the fourth clock signal as the second output signal from the second output signal terminal Oput2 ⁇ N> output.
  • the first pole of the twenty-sixth transistor M26 may be electrically connected to the leakage prevention node OFF ⁇ N> and the second pole of the twenty-fifth transistor M25
  • the third transistor M3 can be controlled by the voltage of the pull-up node Q ⁇ N> is turned on, and the first voltage signal is transmitted to the leakage prevention node OFF ⁇ N>, so that the voltage of the leakage prevention node OFF ⁇ N> is increased, thereby making the voltage between the control electrode and the first electrode of the twenty-sixth transistor M26 The difference is less than zero, ensuring that the twenty-sixth transistor M26 is completely or more completely turned off. In this way, leakage of the pull-up node Q ⁇ N> through the transmission circuit 3203 can be avoided, so that the pull-
  • the shift register may further include a sixth reset circuit 3110 .
  • the sixth reset circuit 3110 is electrically connected to the second clock signal terminal CLKA, the first blanking node H, the pull-down node QB_A and the second voltage signal terminal VGL1, so that in the blanking period of a frame display stage, the second clock Under the joint control of the second clock signal transmitted by the signal terminal CLKA and the voltage of the first blanking node H, the pull-down node QB_A is reset.
  • the sixth reset circuit 3110 may The second clock signal is turned on under the joint control of the voltage of the first blanking node H, and the second voltage signal transmitted by the second voltage signal terminal VGL1 is transmitted to the pull-down node QB_A, and the pull-down node QB_A is pulled-down reset.
  • the sixth reset circuit 3110 may include: a thirty-second transistor M32 and a thirty-third transistor M33.
  • the control pole of the thirty-second transistor M32 is electrically connected to the second clock signal terminal CLKA, the first pole of the thirty-second transistor M32 is electrically connected to the pull-down node QB_A, and the second pole of the thirty-second transistor M32 is electrically connected to the thirtieth
  • the first electrodes of the three transistors M33 are electrically connected.
  • the control electrode of the thirty-third transistor M33 is electrically connected to the first blanking node H, and the second electrode of the thirty-third transistor M33 is electrically connected to the second voltage signal terminal VGL1.
  • the thirty-third transistor M33 may be turned on under the control of the voltage of the first blanking node H turn on, transmit the second voltage signal to the first pole of the thirty-third transistor M33, the thirty-second transistor M32 can be turned on under the control of the second clock signal, and transmit the second voltage signal from the thirty-third transistor M33
  • the first pole of is transmitted to the pull-down node QB_A, and pull-down reset is performed on the pull-down node QB_A.
  • N is represented as a positive odd number.
  • the output circuit 3103 in the next-stage shift register may not have the fourth transistor M4 and is not electrically connected to the third clock signal terminal CLKD_1.
  • the shift signal terminal CR ⁇ N> in the Nth stage shift register can be electrically connected to the input signal terminal Iput in the N+2th stage and the N+3th stage shift register, thereby shifting the Nth stage
  • the shift signal output by the shift signal terminal CR ⁇ N> of the bit register is used as the input signal in the N+2-th and N+3-th shift registers.
  • the display reset signal terminal STD of the Nth and N+1th shift registers can be electrically connected to, for example, the shift signal terminal CR ⁇ N+4> of the N+4th shift register, so that the N+4th
  • the shift signal output by the shift signal terminal CR ⁇ N+4> of the stage shift register is used as the display reset signal of the Nth and N+1th shift registers.
  • the shift signal terminal CR ⁇ N> in the first stage shift register may be electrically connected to the input signal terminal Iput in the third stage and the fourth stage shift register.
  • the shift signal terminal CR ⁇ N> in the fifth-stage shift register may be electrically connected to the display reset signal terminal STD in the first-stage and second-stage shift registers. Therefore, the structure of the gate driving circuit can be simplified, and the space ratio of the gate driving circuit in the display panel can be reduced.
  • the cascade relationship of the multi-stage shift registers may not be limited to the foregoing description, and those skilled in the art can make changes according to the situation.
  • the shift register 1230a of the previous stage (ie, the Nth stage) in the adjacent two-stage shift registers may be referred to as the first scanning unit, and the latter stage (ie, the Nth stage)
  • the (N+1)th stage) shift register 1230b may be referred to as a second scanning unit 21b.
  • the pull-up node Q ⁇ N> in the first scan unit 21a may be referred to as the first pull-up node Q ⁇ N>
  • the pull-up node Q ⁇ N> in the second scan unit 21b may be referred to as the second pull-up node Q ⁇ N+1>.
  • the pull-down node QB_A in the first scanning unit 21a is referred to as the first pull-down node QB_A
  • the pull-down node QB_A in the second scanning unit 21b is referred to as the second pull-down node QB_B
  • the leakage prevention in the first scanning unit 21a The node OFF ⁇ N> is referred to as the first anti-leakage node OFF ⁇ N>, and the anti-leakage node OFF ⁇ N> in the second scanning unit 21b is referred to as the second anti-leakage node OFF ⁇ N+1>;
  • the first clock signal CLKE_1 in 21b is called the fifth clock signal CLKE_2, and the fourth clock signal CLKF_1 in the second scanning unit 21b is called the sixth clock signal CLKF_2;
  • the first output signal terminal Oput1 in the first scanning unit 21a ⁇ N> is called the first sub output signal terminal Oput1 ⁇ N>, the second output signal terminal Oput2 ⁇ N
  • the first output signal terminal Oput1 ⁇ N> in the unit 21b is referred to as the third sub output signal terminal Oput1 ⁇ N+1>
  • the second output signal terminal Oput2 ⁇ N> in the second scanning unit 21b is referred to as the fourth sub Output signal terminal Oput2 ⁇ N+1>.
  • the control circuit 3104 in the second scanning unit 21b may be electrically connected to the seventh voltage signal terminal VDD_B, and the sixth voltage signal terminal VDD_A is replaced by the seventh voltage signal terminal VDD_B.
  • the sixth voltage signal transmitted by the sixth voltage signal terminal VDD_A and the seventh voltage signal transmitted by the seventh voltage signal terminal VDD_B are mutually inverse signals.
  • the first reset circuit 3105 in the first scan unit 21a may also be electrically connected to the second pull-down node QB_B.
  • the first reset circuit 3105 can reset the first pull-up node Q ⁇ N> under the control of the voltage of the second pull-down node QB_B:
  • the first reset circuit 3105 when the voltage of the second pull-down node QB_B is at a high level, the first reset circuit 3105 can be turned on under the action of the voltage of the second pull-down node QB_B, and the first reset circuit 3105 can be turned on under the action of the voltage of the second pull-down node QB_B.
  • the two voltage signals are transmitted to the first pull-up node Q ⁇ N>, and the pull-down reset is performed on the first pull-up node Q ⁇ N>.
  • the first reset circuit 3105 in the first scanning unit 21a may further include: a twenty-seventh transistor M27 and a twenty-eighth transistor M28.
  • the control electrode of the twenty-seventh transistor M27 is electrically connected to the second pull-down node QB_B, and the first electrode of the twenty-seventh transistor M27 is electrically connected to the first pull-up node Q ⁇ N>.
  • the second pole of the twenty-seventh transistor M27 is electrically connected to the first pole of the twenty-eighth transistor M28 and the first anti-leakage node OFF ⁇ N>.
  • the control electrode of the twenty-eighth transistor M28 is electrically connected to the second pull-down node QB_B, and the second electrode of the twenty-eighth transistor M28 is electrically connected to the second voltage signal terminal VGL1.
  • the twenty-seventh transistor M27 and the twenty-eighth transistor M28 can be simultaneously turned on under the action of the voltage of the second pull-down node QB_B, and the twenty-eighth transistor M28 can be turned on at the same time.
  • M28 may transmit the second voltage signal transmitted from the second voltage signal terminal VGL1 to the first leakage prevention node OFF ⁇ N>
  • the twenty-seventh transistor M27 may transmit the second voltage from the first leakage prevention node OFF ⁇ N>
  • the signal is transmitted to the first pull-up node Q ⁇ N> to reset the first pull-up node Q ⁇ N>.
  • the first reset circuit 3105 in the second scan unit 21b may also be electrically connected to the first pull-down node QB_A.
  • the first reset circuit 3105 is further configured to reset the second pull-up node Q ⁇ N+1> under the control of the voltage of the first pull-down node QB_A.
  • the first reset circuit 3105 can be turned on under the action of the voltage of the first pull-down node QB_A, and the second voltage signal terminal VGL1 transmits The second voltage signal is transmitted to the second pull-up node Q ⁇ N+1>, and the pull-down reset is performed on the second pull-up node Q ⁇ N+1>.
  • the first reset circuit 3105 in the second scanning unit 21b may further include: a twenty-seventh transistor M27 and a twenty-eighth transistor M28.
  • the control electrode of the twenty-seventh transistor M27 is electrically connected to the first pull-down node QB_A, and the first electrode of the twenty-seventh transistor M27 is electrically connected to the second pull-up node Q ⁇ N+1> is electrically connected, and the second pole of the twenty-seventh transistor M27 is electrically connected to the first pole of the twenty-eighth transistor M28 and the second anti-leakage node OFF ⁇ N+1>.
  • the control electrode of the twenty-eighth transistor M28 is electrically connected to the first pull-down node QB_A, and the second electrode of the twenty-eighth transistor M28 is electrically connected to the second voltage signal terminal VGL1.
  • the twenty-seventh transistor M27 and the twenty-eighth transistor M28 may be simultaneously turned on under the action of the voltage of the first pull-down node QB_A, and the twenty-seventh transistor M27 and the twenty-eighth transistor M28 may be turned on at the same time under the action of the voltage of the first pull-down node QB_A.
  • the eight transistors M28 can transmit the second voltage signal transmitted from the second voltage signal terminal VGL1 to the second anti-leakage node OFF ⁇ N+1>, and the twenty-seventh transistor M27 can transmit the second voltage signal from the second anti-leakage node OFF ⁇ N+
  • the second voltage signal of 1> is transmitted to the second pull-up node Q ⁇ N+1> to reset the second pull-up node Q ⁇ N+1>.
  • the fourth reset circuit 3108 in the first scan unit 21a may also be electrically connected to the second pull-down node QB_B. Therefore, the fourth reset circuit 3108 can control the shift signal terminal CR ⁇ N>, the first sub-output signal terminal Oput1 ⁇ N> and the second sub-output signal terminal Oput2 under the control of the voltage of the second pull-down node QB_B ⁇ N> Perform reset: when the voltage of the second pull-down node QB_B is at a high level, the fourth reset circuit 3108 can be turned on under the action of the voltage of the second pull-down node QB_B, and the second voltage signal terminal VGL1 is turned on.
  • the transmitted second voltage signal is transmitted to the shift signal terminal CR ⁇ N>, the pull-down reset is performed on the shift signal terminal CR ⁇ N>, and the third voltage signal transmitted by the third voltage signal terminal VGL2 is transmitted to the first substation.
  • the output signal terminal Oput1 ⁇ N> and the second sub-output signal terminal Oput2 ⁇ N> perform pull-down reset on the first sub-output signal terminal Oput1 ⁇ N> and the second sub-output signal terminal Oput2 ⁇ N>.
  • the fourth reset circuit 3108 in the first scanning unit 21a may further include: a twenty-ninth transistor M29, a thirtieth transistor M30 and a thirty-first transistor M31.
  • the control pole of the twenty-ninth transistor M29 is electrically connected to the second pull-down node QB_B, the first pole of the twenty-ninth transistor M29 is electrically connected to the shift signal terminal CR ⁇ N>, and the second pole of the twenty-ninth transistor M29 It is electrically connected to the second voltage signal terminal VGL1.
  • the twenty-ninth transistor M29 can be turned on under the action of the voltage of the second pull-down node QB_B, and transmits the voltage transmitted by the second voltage signal terminal VGL1.
  • the second voltage signal is transmitted to the shift signal terminal CR ⁇ N>, and pull-down reset is performed on the shift signal terminal CR ⁇ N>.
  • the control electrode of the thirtieth transistor M30 is electrically connected to the second pull-down node QB_B, the first electrode of the thirtieth transistor M30 is electrically connected to the first sub-output signal terminal Oput1 ⁇ N>, and the second electrode of the thirtieth transistor M30 is electrically connected to The third voltage signal terminal VGL2 is electrically connected.
  • the thirtieth transistor M30 When the voltage of the second pull-down node QB_B is at a high level, the thirtieth transistor M30 may be turned on under the action of the voltage of the second pull-down node QB_B, and the third voltage signal transmitted by the third voltage signal terminal VGL2 It is transmitted to the first sub-output signal terminal Oput1 ⁇ N>, and the pull-down reset is performed on the first sub-output signal terminal Oput1 ⁇ N>.
  • the control electrode of the thirty-first transistor M31 is electrically connected to the second pull-down node QB_B, the first electrode of the thirty-first transistor M31 is electrically connected to the second sub-output signal terminal Oput2 ⁇ N>, and the first electrode of the thirty-first transistor M31 is electrically connected to the second sub-output signal terminal Oput2 ⁇ N>.
  • the diode is electrically connected to the third voltage signal terminal VGL2.
  • the thirty-first transistor M31 may be turned on under the action of the voltage of the second pull-down node QB_B, and the third voltage transmitted by the third voltage signal terminal VGL2 The signal is transmitted to the second sub-output signal terminal Oput2 ⁇ N>, and the pull-down reset is performed on the second sub-output signal terminal Oput2 ⁇ N>.
  • the fourth reset circuit 3108 in the second scan unit 21b may also be electrically connected to the first pull-down node QB_A. That is, the fourth reset circuit 3108 can reset the third sub-output signal terminal Oput1 ⁇ N+1> and the fourth sub-output signal terminal Oput2 ⁇ N+1> under the control of the voltage of the first pull-down node QB_A:
  • the fourth reset circuit 3108 can be turned on under the action of the voltage of the first pull-down node QB_A, and the third voltage signal transmitted by the third voltage signal terminal VGL2 is turned on.
  • the voltage signal is transmitted to the third sub-output signal terminal Oput1 ⁇ N+1>
  • the pull-down reset is performed on the third sub-output signal terminal Oput1 ⁇ N+1>
  • the third voltage signal transmitted by the third voltage signal terminal VGL2 is transmitted to
  • the fourth sub-output signal terminal Oput2 ⁇ N+1> performs pull-down reset on the fourth sub-output signal terminal Oput2 ⁇ N+1>.
  • the fourth reset circuit 3108 may further include: a thirtieth transistor M30 and a thirty-first transistor M31.
  • control electrode of the thirtieth transistor M30 is electrically connected to the first pull-down node QB_A
  • the first electrode of the thirtieth transistor M30 is electrically connected to the third sub-output signal terminal Oput1 ⁇ N+1>
  • the thirtieth transistor M30 is electrically connected to the third sub-output signal terminal Oput1 ⁇ N+1>.
  • the second pole of M30 is electrically connected to the third voltage signal terminal VGL2.
  • the thirtieth transistor M30 When the voltage of the first pull-down node QB_A is at a high level, the thirtieth transistor M30 may be turned on under the action of the voltage of the first pull-down node QB_A, and the third voltage signal terminal VGL2 transmits the third The voltage signal is transmitted to the third sub-output signal terminal Oput1 ⁇ N+1>, and pull-down reset is performed on the third sub-output signal terminal Oput1 ⁇ N+1>.
  • the control electrode of the thirty-first transistor M31 is electrically connected to the first pull-down node QB_A, the first electrode of the thirty-first transistor M31 is electrically connected to the fourth sub output signal terminal Oput2 ⁇ N+1>, and the thirty-first transistor M31 is electrically connected to the fourth sub-output signal terminal Oput2 ⁇ N+1>.
  • the second pole of M31 is electrically connected to the third voltage signal terminal VGL2.
  • the thirty-first transistor M31 may be turned on under the action of the voltage of the first pull-down node QB_A, and the third voltage signal terminal VGL2 transmits the The three voltage signals are transmitted to the fourth sub-output signal terminal Oput2 ⁇ N+1>, and the pull-down reset is performed on the fourth sub-output signal terminal Oput2 ⁇ N+1>.
  • the shift register 1230 may include: a first input circuit 3101, an anti-leakage circuit 3102, an output circuit 3103, a control circuit 3104, a first reset circuit 3105, a second reset circuit circuit 3106 , third reset circuit 3107 , fourth reset circuit 3108 and fifth reset circuit 3109 .
  • the structures of the reset circuit 3108 and the fifth reset circuit 3109 may be the same as the corresponding circuit structures shown in FIG. 6 , and the structures and functions of the same circuits will not be repeated here.
  • the output circuit 3103 shown in FIG. 8 is electrically connected to the pull-up node Q ⁇ N>, the first clock signal terminal CLKE_1 and the first output signal terminal Oput1 ⁇ N>, in a During the display period in the frame display stage, under the control of the voltage of the pull-up node Q ⁇ N>, the first clock signal received at the first clock signal terminal CLKE_1 is transmitted to the first output signal terminal Oput1 ⁇ N>; During the blanking period in the display stage of one frame, under the control of the voltage of the pull-up node Q ⁇ N>, the first clock signal received at the first clock signal terminal CLKE_1 is transmitted to the first output signal terminal Oput1 ⁇ N> .
  • the output circuit 3103 may also be electrically connected to the third clock signal terminal CLKD_1 and the shift signal terminal CR ⁇ N>.
  • the third clock signal received at the third clock signal terminal CLKD_1 can be transmitted to the shift signal terminal CR ⁇ under the control of the voltage of the pull-up node Q ⁇ N> during the display period in the one frame display stage N>.
  • the output circuit 3103 can be turned on under the control of the voltage of the pull-up node Q ⁇ N> to turn the voltage of the pull-up node Q ⁇ N> on.
  • the third clock signal received at the third clock signal terminal CLKD_1 is used as a shift signal and output from the shift signal terminal CR ⁇ N>; the first clock signal received at the first clock signal terminal CLKE_1 is used as an output signal (also That is, the first gate signal received by the pixel circuit) is output from the first output signal terminal Oput1 ⁇ N>.
  • the output circuit 3103 can be turned on under the control of the voltage of the pull-up node Q ⁇ N>, and will be turned on in the first
  • the first clock signal received at the clock signal terminal CLKE_1 is used as an output signal (ie, the second gate signal received by the pixel circuit), and is output from the first output signal terminal Oput1 ⁇ N>.
  • the first output signal terminal Oput1 ⁇ N> of the shift register 1230 can be electrically connected to both the first gate line and the second gate line, so as to facilitate the display period in one frame display period , the first output signal terminal Oput1 ⁇ N> of the shift register can transmit the first gate signal to the pixel circuit through the first gate line and the first gate signal terminal G1 in turn, and the blanking period in a frame display stage , the first output signal terminal Oput1 ⁇ N> can transmit the second gate signal to the pixel circuit through the second gate line and the second gate signal terminal G2 in sequence.
  • the first output signal terminal Oput1 ⁇ N> of the shift register can be electrically connected to the first gate signal terminal G1 and the second gate signal terminal G2 respectively through a gate line, so as to facilitate the display stage of one frame During the display period, the first output signal terminal Oput1 ⁇ N> can transmit the first gate signal to the pixel circuit 12 through the gate line and the first gate signal terminal G1 in turn, and blanking in one frame display period During the period, the first output signal terminal Oput1 ⁇ N> of the shift register can transmit the second gate signal to the pixel circuit through the gate line and the second gate signal terminal G2 in sequence.
  • the output circuit 3103 may include a fourth transistor M4, a fifth transistor M5, and a first capacitor C1.
  • the control electrode of the fourth transistor M4 is electrically connected to the pull-up node Q ⁇ N>, and the first electrode of the fourth transistor M4 is electrically connected to the pull-up node Q ⁇ N>.
  • the third clock signal terminal CLKD_1 is electrically connected, and the second pole of the fourth transistor M4 is electrically connected to the shift signal terminal CR ⁇ N>.
  • the fourth transistor M4 can be at the pull-up node Q ⁇ N> > is turned on under the control of the high voltage of >, transmits the third clock signal to the shift signal terminal CR ⁇ N>, and outputs the third clock signal as the shift signal from the shift signal terminal CR ⁇ N>.
  • the control pole of the fifth transistor M5 is electrically connected to the pull-up node Q ⁇ N>, the first pole of the fifth transistor M5 is electrically connected to the first clock signal terminal CLKE_1, and the second pole of the fifth transistor M5 is electrically connected to the first output signal terminal Oput1 ⁇ N> is electrically connected.
  • the first terminal of the first capacitor C1 is electrically connected to the pull-up node Q ⁇ N>, and the second terminal of the first capacitor C1 is electrically connected to the first output signal terminal Oput1 ⁇ N>.
  • the first capacitor C1 is charged while the first input circuit 3101 is turned on so that the voltage of the pull-up node Q ⁇ N> rises.
  • the first capacitor C1 can be discharged, so that the pull-up node Q ⁇ N> is kept at a high level, so that the fifth transistor M5 can be kept on, and the first clock
  • the signal is transmitted to the first output signal terminal Oput1 ⁇ N>, and the first clock signal is output from the first output signal terminal Oput1 ⁇ N> as an output signal (ie, the first gate signal received by the pixel circuit).
  • the first capacitor C1 is charged while the voltage of the pull-up node Q ⁇ N> rises.
  • the first capacitor C1 can be discharged, so that the pull-up node Q ⁇ N> is kept at a high level, so that the fifth transistor M6 can be kept in an on state, and the first clock signal can be transmitted to the first output signal terminal Oput1 ⁇ N>, and output the first clock signal as an output signal (ie, the second gate signal received by the pixel circuit) from the first output signal terminal Oput1 ⁇ N>.
  • the fourth reset circuit 3108 is electrically connected to the pull-down node QB_A, the shift signal terminal CR ⁇ N>, the first output signal terminal Oput1 ⁇ N>, the second voltage signal terminal VGL1 and the third voltage signal terminal VGL2.
  • the fourth reset circuit 3108 is configured to reset the shift signal terminal CR ⁇ N> and the first output signal terminal Oput1 ⁇ N> under the control of the voltage of the pull-down node QB_A.
  • the fourth reset circuit 3108 can be turned on under the action of the voltage of the pull-down node QB_A to transmit the second voltage signal transmitted by the second voltage signal terminal VGL1 to the shift signal terminal CR ⁇ N>, pull-down reset is performed on the shift signal terminal CR ⁇ N>, and the third voltage signal transmitted by the third voltage signal terminal VGL2 is transmitted to the first output signal terminal Oput1 ⁇ N>.
  • the first output signal terminal Oput1 ⁇ N> performs pull-down reset.
  • the fourth reset circuit 3108 may include a seventeenth transistor M17 and an eighteenth transistor M18.
  • the control electrode of the seventeenth transistor M17 is electrically connected to the pull-down node QB_A
  • the first electrode of the seventeenth transistor M17 is electrically connected to the shift signal terminal CR ⁇ N>
  • the second electrode of the seventeenth transistor M17 is electrically connected to the second voltage signal
  • the terminal VGL1 is electrically connected.
  • the seventeenth transistor M17 can be turned on under the action of the voltage of the pull-down node QB_A to transmit the second voltage signal transmitted from the second voltage signal terminal VGL1 to the shift
  • the signal terminal CR ⁇ N> performs pull-down reset on the shift signal terminal CR ⁇ N>.
  • the control electrode of the eighteenth transistor M18 is electrically connected to the pull-down node QB_A, the first electrode of the eighteenth transistor M18 is electrically connected to the first output signal terminal Oput1 ⁇ N>, and the second electrode of the eighteenth transistor M18 is electrically connected to the third voltage
  • the signal terminal VGL2 is electrically connected.
  • the eighteenth transistor M18 can be turned on under the action of the voltage of the pull-down node QB_A to transmit the third voltage signal transmitted from the third voltage signal terminal VGL2 to the first
  • the output signal terminal Oput1 ⁇ N> performs pull-down reset on the first output signal terminal Oput1 ⁇ N>.
  • the gate drive circuit may further include a plurality of blanking input circuits 3200 .
  • one blanking input circuit can be electrically connected to the adjacent at least two-stage shift registers.
  • the blanking input circuit 3200 can control the corresponding shift register to input a blanking control signal to the pixel circuit of the corresponding row during the blanking period of the display stage of one frame, so that the pixel circuit 12 obtains the sensing signal.
  • the blanking input circuit 3200 may include, for example, a selection control circuit 3201 , a second input circuit 3202 and at least two transmission circuits 3203 .
  • the selection control circuit 3201, the second input circuit 3202 and the at least two transmission circuits 3203 shown in FIG. 8 may have structures and functions consistent with the corresponding structures shown in FIG. 6, and will not be repeated here. Repeat.
  • the above-mentioned at least two transmission circuits 3203 may be electrically connected to at least two shift registers in a one-to-one correspondence.
  • a transmission circuit 3203 is electrically connected to the second blanking node N, the second clock signal terminal CLKA, and the pull-up node Q ⁇ N> of the first-stage shift register. Under the control of the second clock signal transmitted by the signal terminal CLKA, the second clock signal or the first voltage signal received at the second blanking node N is transmitted to the pull-up node Q ⁇ N>.
  • the transmission circuit 3202 can control the second clock signal under the control of the second clock signal. turn on, and receive the second clock signal or the first voltage signal from the second blanking node N, and transmit the received second clock signal or the first voltage signal to the pull-up node Q ⁇ N>, so that the pull-up node
  • the voltage of Q ⁇ N> increases, which in turn enables the output circuit 3103 to be turned on, so that the output signal terminal of the output circuit 3103 outputs Oput ⁇ N> to output the output signal.
  • the transmission circuit 3203 may include: a twenty-fifth transistor M25, the control pole of the twenty-fifth transistor M25 is electrically connected to the second clock signal terminal CLKA, and the first pole of the twenty-fifth transistor M25 is electrically connected to the second blanking node N connected, the second pole of the twenty-fifth transistor M25 is electrically connected to the pull-up node Q ⁇ N>.
  • the twenty-fifth transistor M25 can function as the second clock signal.
  • the twenty-fifth transistor M25 When turned on, the twenty-fifth transistor M25 can transmit the second clock signal or the first voltage signal from the second blanking node N to the pull-up node Q ⁇ N> to charge the pull-up node Q ⁇ N>.
  • the fifth transistor M5 in the output circuit 3103 can be turned on under the control of the voltage of the pull-up node Q ⁇ N>, receives the first clock signal, and uses the first clock signal as an output signal from the first output signal terminal Oput1 ⁇ N> output.
  • the shift register may further include a sixth reset circuit 3110 .
  • the sixth reset circuit 3110 is electrically connected to the second clock signal terminal CLKA, the first blanking node H, the pull-down node QB_A, and the second voltage signal terminal VGL1.
  • the second clock signal terminal is Under the joint control of the second clock signal transmitted by CLKA and the voltage of the first blanking node H, the pull-down node QB_A is reset.
  • the sixth reset circuit 3110 it can be turned on under the joint control of the second clock signal and the voltage of the first blanking node H, and the second voltage signal transmitted by the second voltage signal terminal VGL1 is transmitted to the pull-down node QB_A to perform pull-down reset on the pull-down node QB_A.
  • the sixth reset circuit 3110 may include: a thirty-second transistor M32 and a thirty-third transistor M33.
  • control pole of the thirty-second transistor M32 is electrically connected to the first blanking node H
  • first pole of the thirty-second transistor M32 is electrically connected to the pull-down node QB_A
  • second pole of the thirty-second transistor M32 is electrically connected to the pull-down node QB_A
  • the first pole of the thirty-third transistor M33 is electrically connected.
  • the control electrode of the thirty-third transistor M33 is electrically connected to the second clock signal terminal CLKA, and the second electrode of the thirty-third transistor M33 is electrically connected to the second voltage signal terminal VGL1.
  • the thirty-third transistor M33 may be turned on under the control of the second clock signal to turn the first blanking node H to a high level.
  • the second voltage signal is transmitted to the first pole of the thirty-third transistor M33, the thirty-second transistor M32 can be turned on under the control of the voltage of the first blanking node H, and the second voltage signal is transmitted from the thirty-third transistor M33
  • the first pole of is transmitted to the pull-down node QB_A, and pull-down reset is performed on the pull-down node QB_A.
  • N is represented as a positive odd number.
  • the output circuit 3103 in the next-stage shift register may not have the fourth transistor M4 and is not electrically connected to the third clock signal terminal CLKD_1 .
  • the cascading relationship of the multi-stage shift registers may be the same as the cascading relationship of the multi-stage shift registers in the above examples, which will not be repeated here.
  • the shift register of the previous stage (that is, the Nth stage) can be called the first scanning unit 21a
  • the shift register of the next stage (that is, the N+1th stage) can be shifted
  • the register is referred to as the second scanning unit 21b.
  • the pull-up node Q ⁇ N> in the first scan unit 21a may be referred to as the first pull-up node Q ⁇ N>
  • the pull-up node Q ⁇ N> in the second scan unit 21b may be referred to as the second pull-up node Q ⁇ N> Pull up node Q ⁇ N+1>.
  • the pull-down node QB_A in the first scan unit 21a may be referred to as the first pull-down node QB_A
  • the pull-down node QB_A in the second scan unit 21b may be referred to as the second pull-down node QB_B
  • the anti-leakage node OFF ⁇ N> in the first scanning unit 21a may be referred to as the first anti-leakage node OFF ⁇ N>
  • the anti-leakage node OFF ⁇ N> in the second scanning unit 21b may be referred to as the second anti-leakage node OFF ⁇ N+1>
  • the first clock signal CLKE_1 in the second scanning unit 21b may be referred to as the fifth clock signal CLKE_2.
  • the first output signal terminal Oput1 ⁇ N> in the first scanning unit 21a may be referred to as the first sub-output signal terminal Oput1 ⁇ N>
  • the first output signal terminal Oput1 ⁇ N> in the second scanning unit 21b may be referred to as The second sub output signal terminal Oput1 ⁇ N+1>.
  • the control circuit 3104 in the second scanning unit 21b may be electrically connected to the seventh voltage signal terminal VDD_B, and the sixth voltage signal terminal VDD_A is replaced by the seventh voltage signal terminal VDD_B.
  • the sixth voltage signal transmitted by the sixth voltage signal terminal VDD_A and the seventh voltage signal transmitted by the seventh voltage signal terminal VDD_B are mutually inverse signals.
  • the structure and function of the first reset circuit 3105 in the first scanning unit 21a in this example may be the same as the structure and function of the first reset circuit 3105 in the first scanning unit 21a in some of the above examples.
  • the second scanning unit The structure and function of the first reset circuit 3105 in 21b may be the same as those of the first reset circuit 3105 in the second scanning unit 21b in some of the above examples. The structures and functions of the same circuits will not be repeated here.
  • the fourth reset circuit 3108 in the first scanning unit 21a may also be electrically connected to the second pull-down node QB_B.
  • the fourth reset circuit 3108 is further configured to reset the shift signal terminal CR ⁇ N> and the first sub-output signal terminal Oput1 ⁇ N> under the control of the voltage of the second pull-down node QB_B.
  • the fourth reset circuit 3108 can be turned on under the action of the voltage of the second pull-down node QB_B, and the second voltage signal transmitted by the second voltage signal terminal VGL1 is turned on.
  • the fourth reset circuit 3108 in the first scanning unit 21a may further include: a twenty-ninth transistor M29 and a thirtieth transistor M30.
  • the control pole of the twenty-ninth transistor M29 is electrically connected to the second pull-down node QB_B, the first pole of the twenty-ninth transistor M29 is electrically connected to the shift signal terminal CR ⁇ N>, and the second pole of the twenty-ninth transistor M29 It is electrically connected to the second voltage signal terminal VGL1.
  • the twenty-ninth transistor M29 can be turned on under the action of the voltage of the second pull-down node QB_B, to convert the second voltage transmitted by the second voltage signal terminal VGL1
  • the signal is transmitted to the shift signal terminal CR ⁇ N>, and the pull-down reset is performed on the shift signal terminal CR ⁇ N>.
  • the control electrode of the thirtieth transistor M30 is electrically connected to the second pull-down node QB_B, the first electrode of the thirtieth transistor M30 is electrically connected to the first sub-output signal terminal Oput1 ⁇ N>, and the second electrode of the thirtieth transistor M30 is electrically connected to The third voltage signal terminal VGL2 is electrically connected.
  • the thirtieth transistor M30 When the voltage of the second pull-down node QB_B is at a high level, the thirtieth transistor M30 may be turned on under the action of the voltage of the second pull-down node QB_B, and the third voltage signal transmitted by the third voltage signal terminal VGL2 It is transmitted to the first sub-output signal terminal Oput1 ⁇ N>, and the pull-down reset is performed on the first sub-output signal terminal Oput1 ⁇ N>.
  • the fourth reset circuit 3108 in the second scanning unit 21b may also be electrically connected to the first pull-down node QB_A, and under the control of the voltage of the first pull-down node QB_A, the second sub-output signal terminal Oput1 ⁇ N+ 1> Perform a reset.
  • the fourth reset circuit 3108 can be turned on under the action of the voltage of the first pull-down node QB_A, and the third voltage signal terminal VGL2 is turned on.
  • the transmitted third voltage signal is transmitted to the second sub-output signal terminal Oput1 ⁇ N+1>, and pull-down reset is performed on the second sub-output signal terminal Oput1 ⁇ N+1>.
  • the fourth reset circuit 3108 in the second scanning unit 21b may further include: a thirtieth transistor M30.
  • the control electrode of the thirtieth transistor M30 is electrically connected to the first pull-down node QB_A, the first electrode of the thirtieth transistor M30 is electrically connected to the second sub-output signal terminal Oput2 ⁇ N+1>, and the The diode is electrically connected to the third voltage signal terminal VGL2.
  • the thirtieth transistor M30 When the voltage of the first pull-down node QB_A is at a high level, the thirtieth transistor M30 may be turned on under the action of the voltage of the first pull-down node QB_A, and the third voltage signal terminal VGL2 transmits the third The voltage signal is transmitted to the second sub-output signal terminal Oput1 ⁇ N+1>, and the pull-down reset is performed on the second sub-output signal terminal Oput1 ⁇ N+1>.
  • the gate driving circuit may further include a plurality of control signal lines 33 extending in the second direction (perpendicular to the extending direction of the light-shielding holes shown in FIG. 1 and FIG. 3 ).
  • the first-stage shift register is electrically connected to at least a part of the plurality of control signal lines 33, and provides output signals to a plurality of pixel circuits in a corresponding row under the control of at least a part of the control signal lines 33 connected thereto.
  • the bit register is electrically connected to the pixel circuits of the first row of sub-pixels, the second row of sub-pixels, the third row of sub-pixels, and the sixth row of sub-pixels in the display panel.
  • RS1, RS3, and RS5 can be respectively electrically connected to the first gate signal terminal G1 in the pixel circuit of the corresponding row through the first sub-output signal terminal Oput1 ⁇ N>, and can be electrically connected to the corresponding row of pixel circuits through the second sub-output signal terminal Oput2 ⁇ N>.
  • the second gate signal terminal G2 in the row pixel circuit is electrically connected.
  • RS2, RS4, and RS6 can be electrically connected to the first gate signal terminal G1 in the pixel circuit of the corresponding row through the third sub-output signal terminal Oput1 ⁇ N+1>, respectively, and the fourth sub-output signal terminal Oput2 ⁇ N+1> It is electrically connected to the second gate signal terminal G2 in the pixel circuit of the corresponding row.
  • RS1, RS3, and RS5 may be referred to as the first scanning unit 21a, respectively
  • RS2, RS4, and RS6 may be referred to as the second scanning unit 21b, respectively.
  • the above-mentioned plurality of control signal lines 33 may include a first clock signal line CLK_1 , a second clock signal line CLK_2 and a third clock signal line CLK_3 .
  • the third clock signal terminal CLKD_1 in the first-stage shift register is electrically connected to the first clock signal line CLK_1 to receive the third clock signal.
  • the third clock signal terminal CLKD_1 in the third stage shift register is electrically connected to the second clock signal line CLK_2 to receive the third clock signal.
  • the third clock signal terminal CLKD_1 in the fifth stage shift register is electrically connected to the third clock signal line CLK_3 to receive the third clock signal.
  • the above-mentioned plurality of control signal lines 33 may further include a fourth clock signal line CLK_4, a fifth clock signal line CLK_5, a sixth clock signal line CLK_6, a seventh clock signal line CLK_7, an eighth clock signal line CLK_8, and a ninth clock signal line CLK_9, tenth clock signal line CLK_10, eleventh clock signal line CLK_11, twelfth clock signal line CLK_12, thirteenth clock signal line CLK_13, fourteenth clock signal line CLK_14 and fifteenth clock signal line CLK_15.
  • the first clock signal terminal CLKE_1 in the first-stage shift register is electrically connected to the fourth clock signal line CLK_4 to receive the first clock signal
  • the fourth clock signal terminal CLKF_1 is electrically connected to the fifth clock signal line CLK_5, to receive the fourth clock signal
  • the fifth clock signal terminal CLKE_2 in the second stage shift register is electrically connected to the sixth clock signal line CLK_6 to receive the fifth clock signal
  • the sixth clock signal terminal CLKE_2 is electrically connected to the seventh clock signal line CLK_7 to receive the fifth clock signal Six clock signals.
  • the first clock signal terminal CLKE_1 in the third-stage shift register is electrically connected to the eighth clock signal line CLK_8 to receive the first clock signal
  • the fourth clock signal terminal CLKF_1 is electrically connected to the ninth clock signal line CLK_9 to receive the first clock signal Four clock signals.
  • the fifth clock signal terminal CLKE_2 in the fourth stage shift register is electrically connected to the tenth clock signal line CLK_10 to receive the fifth clock signal
  • the sixth clock signal terminal CLKE_2 is electrically connected to the eleventh clock signal line CLK_11 to receive the sixth clock signal.
  • the first clock signal terminal CLKE_1 in the fifth stage shift register is electrically connected to the twelfth clock signal line CLK_12 to receive the first clock signal
  • the fourth clock signal terminal CLKF_1 is electrically connected to the thirteenth clock signal line CLK_13 to receive the first clock signal.
  • a fourth clock signal is received.
  • the fifth clock signal terminal CLKE_2 in the sixth-stage shift register is electrically connected to the fourteenth clock signal line CLK_14 to receive the fifth clock signal
  • the sixth clock signal terminal CLKE_2 is electrically connected to the fifteenth clock signal line CLK_15 to receive the fifth clock signal.
  • a sixth clock signal is received.
  • the above-mentioned plurality of control signal lines 33 may further include a sixteenth clock signal line CLK_16.
  • the global reset signal terminal TRST in each stage of the shift register is electrically connected to the sixteenth clock signal line CLK_16 to receive the global reset signal.
  • the above-mentioned plurality of control signal lines 33 may further include a seventeenth clock signal line CLK_17 and an eighteenth clock signal line CLK_18.
  • the selection control signal terminal OE of each blanking input circuit is electrically connected to the seventeenth clock signal line CLK_17 to receive the selection control signal.
  • the second clock signal terminal CLKA of each blanking input unit is electrically connected to the eighteenth clock signal line CLK_18 to receive the second clock signal.
  • the above-mentioned plurality of control signal lines 33 may further include a nineteenth clock signal line CLK_19 and a twentieth clock signal line CLK_20.
  • the sixth voltage signal terminal VDD_A in the first stage shift register, the sixth voltage signal terminal VDD_A in the third stage shift register 21 and the sixth voltage signal terminal VDD_A in the fifth stage shift register are all the same as the nineteenth voltage signal terminal VDD_A.
  • the clock signal line CLK_19 is electrically connected to receive the sixth voltage signal.
  • the seventh voltage signal terminal VDD_B in the second stage shift register, the seventh voltage signal terminal VDD_B in the fourth stage shift register and the seventh voltage signal terminal VDD_B in the sixth stage shift register are all connected to the twentieth clock
  • the signal line CLK_20 is electrically connected to receive the seventh voltage signal.
  • the above-mentioned plurality of control signal lines 33 may further include a twenty-first clock signal line CLK_21.
  • the input signal terminal Iput in the first-stage shift register and the input signal terminal Iput in the second-stage shift register may both be electrically connected to the twenty-first clock signal line CLK_21 to receive the start signal as the input signal.
  • the above-mentioned plurality of control signal lines 33 may further include a twenty-second clock signal line CLK_22.
  • the display reset signal terminals STD of the last four-stage shift registers in the gate driving circuit may all be electrically connected to the twenty-second clock signal line CLK_22 to receive the display reset signal.
  • the shift signal terminal CR ⁇ N> in the Nth stage shift register may be It is electrically connected to the input signal terminal Iput in the N+2 stage and the N+3 stage shift register, and then the shift signal output by the shift signal terminal CR ⁇ N> of the Nth stage shift register is used as the Nth stage.
  • the display reset signal terminal STD of the Nth and N+1st shift registers may be, for example, connected with the shift signal of the N+4th shift register 21 .
  • the terminal CR ⁇ N+4> is electrically connected, and then the shift signal output by the shift signal terminal CR ⁇ N+4> of the N+4th stage shift register is used as the Nth stage and the N+1th shift register. display reset signal.
  • first pull-up node, second pull-up node, first pull-down node, and second pull-down node do not refer to actual components, but refer to the circuit diagram.
  • the junctions of the relevant electrical connections, that is, the nodes are nodes equivalent to the junctions of the relevant electrical connections in the circuit diagram.
  • the term “pull-up” means charging a node or an electrode of a transistor such that the absolute value of the level of the node or electrode is raised, thereby enabling operation (eg, turning on) of the corresponding transistor.
  • pulseling down means discharging a node or an electrode of a transistor such that the absolute value of the level of the node or electrode is lowered, thereby enabling operation (eg, turn-off) of the corresponding transistor.
  • the present application proposes a method for manufacturing the aforementioned display panel. Referring to Figure 9, the method includes:
  • an operation of forming a backplane circuit on the substrate may be performed in this step.
  • the structure of the backplane circuit, the structure of the pixel circuit and the gate driving circuit have been described in detail above, and will not be repeated here.
  • this step may include multiple operations of depositing materials and performing a patterning process to form structures constituting transistors, capacitors and signal lines.
  • a plurality of light-emitting elements are provided in this step.
  • the plurality of light emitting elements may be OLEDs.
  • the method further includes an operation of forming a light-shielding hole and a metal layer, and filling the metal layer into the light-shielding hole, the light-shielding hole and the position of the orthographic projection of the metal layer on the substrate are configured to be configurable
  • the light of the light-emitting element is blocked from being irradiated to the active layer of the thin film transistor. Thereby, the aforementioned display panel can be easily obtained.
  • the above-mentioned forming the light-shielding hole and the metal layer may include: before forming the light-emitting element, pre-positioning between a plurality of the light-emitting elements forming a pixel-defining structure, and forming the light-shielding hole on the pixel-defining structure; when forming the light-emitting element, the metal layer is formed by using a cathode metal. Thereby, the light-shielding hole and the metal layer can be easily formed.
  • the present application provides a display device.
  • the display device includes the aforementioned display panel. Therefore, the display device has at least one of the advantages of narrow frame and long service life.

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Abstract

提出了显示面板和制备的方法、显示装置。该显示面板的显示区包括多个像素区和多个栅极驱动电路区，所述栅极驱动电路区位于相邻的两个所述像素区之间，所述显示面板包括：基板；背板电路层，所述背板电路层位于所述基板上，且所述背板电路层在所述栅极驱动电路区内，具有多个薄膜晶体管；多个发光元件，所述多个发光元件位于所述背板电路层远离所述基板的一侧，并位于所述像素区所在区域内，所述显示面板具有遮光孔，所述遮光孔内填充有金属层，所述遮光孔以及所述金属层在所述基板上的正投影的位置被配置为可遮挡照射至所述薄膜晶体管的有源层光。

Description

显示面板和制备的方法、显示装置 技术领域
本申请涉及显示技术领域，具体地，涉及显示面板和制备的方法、显示装置。
背景技术
在显示领域，特别是基于有机发光二极管(OLED)的显示装置中，栅极驱动电路为显示装置中的重要组成部分。栅极驱动电路可以包括多级级联的移位寄存器，移位寄存器产生扫描信号，对显示装置中的各行子像素进行扫描，从而实现画面的显示。随着大尺寸、窄边框的显示装置的盛行，越来越多的显示装置采取将栅极驱动电路设置在显示面板上的策略，以窄化显示装置的边框。
因此，目前的显示面板和制备的方法、显示装置仍有待改进。
发明内容
本申请旨在至少一定程度上缓解或解决上述提及问题中至少一个。
发明人发现，在一部分显示装置中，特别是大尺寸OLED显示中，栅极驱动电路通常设置在显示面板的两侧，这样难以实现超窄边框甚至无边框，且目前很多显示面板都设计为非矩形形状，这就使得传统的设计方式很难实现窄边框。特别是栅极驱动电路中的薄膜晶体管(TFT)设计在显示区(AA区)时会受到邻近像素发光区发出的光干扰使得TFT负漂，影响面板寿命。
有鉴于此，在本申请的一个方面，本申请提出了一种显示面板。该显示面板的显示区包括多个像素区和多个栅极驱动电路区，所述栅极驱动电路区位于相邻的两个所述像素区之间，所述显示面板包括：基板；背板电路层，所述背板电路层位于所述基板上，且所述背板电路层在所述栅极驱动电路区内，具有多个薄膜晶体管；多个发光元件，所述多个发光元件位于所述背板电路层远离所述基板的一侧，并位于所述像素区所在区域内，所述显示面板具有遮光孔，所述遮光孔内填充有金属层，所述遮光孔以及所述金属层在所述基板上的正投影的位置被配置为可遮挡照射至所述薄膜晶体管的有源层的光。由此，该显示面板的遮光孔以及金属层可缓解甚至避免发光元件的发光对栅极驱动电路区内TFT的影响，进而可以在实现窄边框的前提下，进一步提高该显示面板的使用寿命。
在本申请的一些示例中，所述遮光孔以及所述金属层位于所述背板电路层远离所述基板的一侧。由此，可更好地对薄膜晶体管的有源层进行保护，防止发生负漂。
在本申请的一些示例中，所述像素区和所述栅极驱动电路区相邻设置，所述发光元件 位于所述像素区内，且相邻的所述发光元件之间具有像素界定结构，所述遮光孔形成在所述像素界定结构上。由此，可简便地设置遮光孔和金属层。
在本申请的一些示例中，所述金属层包括阴极金属。由此，可简便地设置遮光孔和金属层。
在本申请的一些示例中，包括多个所述遮光孔，每个所述像素区以及所述栅极驱动电路区内的薄膜晶体管之间，均具有所述遮光孔。由此，可进一步提高遮光孔对薄膜晶体管有源层的保护。
在本申请的一些示例中，所述栅极驱动电路区内的薄膜晶体管包括：有源层；栅极以及栅绝缘层，所述栅极以及栅绝缘层位于所述有源层远离所述基板的一侧；源漏电极，所述源漏电极位于所述有源层远离所述基板的一侧，所述源漏电极以及所述栅极之间间隔有层间介质层，且所述源漏电极通过贯穿所述层间介质层的通孔与所述有源层相连，所述遮光孔在所述基板上的正投影，和所述层间介质层的通孔在所述基板上的正投影之间无重叠区域。由此，可进一步提高遮光孔对薄膜晶体管有源层的保护。
在本申请的一些示例中，所述像素区进一步包括像素发光子区和像素电路子区，所述发光元件位于所述像素发光区内，所述像素发光子区和像素电路子区沿第一方向排布，且所述遮光孔沿所述第一方向延伸。由此，可进一步提高遮光孔对薄膜晶体管有源层的保护。
在本申请的一些示例中，相邻的两个所述像素区之间具有两个所述遮光孔，所述遮光孔沿所述第一方向的长度与所述晶体管组的长度相一致，所述晶体管组内的多个薄膜晶体管沿所述第一方向排布于两个所述遮光孔之间。可进一步提高遮光孔对薄膜晶体管有源层的保护。
在本申请的一些示例中，所述像素区在所述基板上阵列排布，每个所述像素区至少包括两个子像素，每行所述像素区与至少两个所述栅极驱动电路区对应，每个所述栅极驱动电路区位于相邻两个所述像素区之间，所述栅极驱动电路包括级联的多个移位寄存器，每个所述移位寄存器与一行所述子像素电连接；每个所述移位寄存器包括多个晶体管组，每个所述晶体管组包括至少一个所述薄膜晶体管。
在本申请的一些示例中，所述遮光孔的深度为1-3微米，所述遮光孔的宽度为3-10微米。由此，可进一步提高遮光孔对薄膜晶体管有源层的保护。
在本申请的另一方面，本申请提出了一种制备前面所说的显示面板方法，该方法包括：在基板上形成背板电路层，并在所述显示面板中的所述栅极驱动电路区内形成多个薄膜晶体管；在所述背板电路层远离所述基板的一侧形成多个发光元件，并令所述发光元件位于所述像素区内；且所述方法包括形成遮光孔和金属层的操作，并令所述金属层填充至所述遮光孔内，所述遮光孔以及所述金属层在所述基板上的正投影的位置被配置为可遮挡所述 发光元件的光照射至所述薄膜晶体管的有源层。由此，可简便地获得前述的显示面板。
在本申请的一些示例中，形成所述遮光孔和金属层包括：形成所述发光元件之前，预先在多个所述发光元件之间处形成像素界定结构，并在所述像素界定结构上形成所述遮光孔；形成所述发光元件时，利用阴极金属形成所述金属层。由此，可简便地形成遮光孔和金属层。
在本申请的又一方面，本申请提出了一种显示装置。该显示装置包括了前面所述的显示面板。由此，该显示装置具有边框较窄、使用寿命较长等优点的至少之一。
附图说明
本申请的上述和/或附加的方面和优点从结合下面附图对实施例的描述中将变得明显和容易理解，其中：
图1显示了根据本申请一个示例的显示面板的结构示意图；
图2显示了沿图1中A-A’方向的显示面板的剖面结构示意图；
图3显示了根据本申请一个示例的显示面板的结构示意图；
图4显示了根据本申请一个示例的像素电路的电路示意图；
图5显示了根据本申请一个示例的栅极驱动电路的电路示意图；
图6显示了根据本申请另一个示例的栅极驱动电路的电路示意图；
图7显示了根据本申请又一个示例的栅极驱动电路的电路示意图；
图8显示了根据本申请又一个示例的栅极驱动电路的电路示意图；
图9显示了根据本申请一个示例的制备显示面板的方法的流程图。
具体实施方式
下面详细描述本申请的实施例，所述实施例的示例在附图中示出，其中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。下面通过参考附图描述的实施例是示例性的，仅用于解释本申请，而不能理解为对本申请的限制。
在本申请的一个方面，本申请提出了一种显示面板。参考图1以及图2，该显示面1000的显示区包括多个像素区1100和多个栅极驱动电路区1200，所述栅极驱动电路区1200位于相邻的两个所述像素区1100之间。基板100上具有背板电路层，且所述背板电路层在所述栅极驱动电路区内，具有多个薄膜晶体管。多个发光元件(图2中仅示出了一个)800位于所述背板电路层远离所述基板100的一侧，并位于像素区所在区域内。遮光孔(见图1中的1220)内填充有金属层50，遮光孔以及所述金属层在所述基板上的正投影的位置被配置为可遮挡照射至所述薄膜晶体管的有源层的光。由此，该显示面板的遮光孔以及金属层 可缓解甚至避免发光元件等的发光对栅极驱动电路区内TFT的影响，进而可以在实现窄边框的前提下，进一步提高该显示面板的使用寿命。
为方便理解，下面首先对该显示面板可实现上述有益效果的原理进行简单说明：
根据本申请的一些示例，为了窄化该显示面板的边框，可将栅极驱动电路设置在显示区中相邻的两个像素区之间。但由于栅极驱动电路具有较为复杂的结构，为了降低其占用面积，将栅极驱动电路中的多个薄膜晶体管集中排布并设置为晶体管组1210，令其与像素区相邻。该设计可较好的实现窄化边框的效果，但同时此时如不设置遮光孔和金属层，则像素区中的像素发光子区1110发出的光将较容易地照射至晶体管组的有源层，造成薄膜晶体管的负漂。同过遮光孔和金属层的设置，可较好地将像素发光子区所发出的光进行遮挡，防止照射至有源层，进而可缓解甚至避免由于光照而发生的负漂，从而实现延长该显示面板的使用寿命的效果。
在本申请的一些示例中，遮光孔以及金属层在该显示面板中剖面方向(即垂直与基板100所在平面的方向)上的具体位置不受特别限制，只要可以实现遮光即可。例如，参考图2，遮光孔和金属层50可以位于背板电路层远离基板的一侧，即位于薄膜晶体管远离基板100的一侧。由此，可更好地对薄膜晶体管的有源层进行保护，防止发生负漂。
具体地，如图2中所示出的，相邻的发光元件800之间具有像素界定结构600，遮光孔可以形成在所述像素界定结构上。金属层50包括阴极金属。由此，可简便地设置遮光孔和金属层：一方面，此处遮光孔和金属层50的设置不会影响背板电路层中各个层叠结构以及金属的刻蚀图样的改变。另一方面，像素界定结构由于需要隔离相邻的两个发光元件的发光层等结构，因此具有相对较大的厚度，便于遮光孔的制备。并且，像素界定结构600自身即具有开口用于容纳发光元件800，因此遮光孔可以和开口同步形成。而填充在遮光孔中的金属层50则可采用发光元件800的阴极金属形成。
在本申请的一些示例中，该显示面板可以包括多个所述遮光孔。参考图1，每个像素区以及所述栅极驱动电路区内的薄膜晶体管之间，均可以具有所述遮光孔。例如，当栅极驱动电路包括晶体管组1210时，每个栅极驱动电路区可具有两个遮光孔1220，以隔离与其相邻的两个像素区1100的发光。由此，可进一步提高遮光孔对薄膜晶体管有源层的保护。
在本申请的一些示例中，所栅极驱动电路区内的薄膜晶体管的具体数量以及结构不受特别限制，本领域技术人员可以根据实际需要进行设计。例如，在本申请的一些示例中，薄膜晶体管可以包括有源层10，栅极21以及栅绝缘层700，栅极以及栅绝缘层位于所述有源层10远离所述基板100的一侧；源漏电极(源极31和漏极32)可位于有源层10远离所述基板100的一侧，源漏电极以及栅极之间间隔有层间介质层300，且源漏电极通过贯穿层间介质层300的通孔与有源层10相连。
此处需要特别说明的是，前述的薄膜晶体管仅为本发明的一个示例，而不能够理解为对薄膜晶体管的具体结构的限定。例如，背板电路层可以包括基板100之上的缓冲层200，前述薄膜晶体管的各个层级结构，以及钝化层400、平坦化层500等结构。
根据本申请的一些示例，遮光孔在基板上的正投影，与贯穿层间介质层300的通孔在基板上的正投影之间可以无重叠区域。也即是说，遮光孔的位置可以尽可能地靠近像素区设置。由此，可进一步提高遮光孔对薄膜晶体管有源层的保护：此时，遮光孔和填充于其中的金属层50可以更好地保护源漏极之间的沟道区。发光元件800等发出的光可被金属层50更好地进行遮挡(参考图2中箭头所示出的方向)。
在本申请的一些示例中，参考图1和图3，像素区进一步包括像素发光子区1110和像素电路子区1120，发光元件位于所述像素发光区内，所述像素发光子区和像素电路子区沿第一方向排布，且遮光孔1220沿所述第一方向延伸。由此，可进一步提高遮光孔对薄膜晶体管有源层的保护：如前所述，为了节省栅极驱动电路的占用面积，其中的晶体管组1210中的多个薄膜晶体管多为依次排列的，如也沿着第一方向排布。此时，遮光孔1220沿着第一方向排布一方面可以节省占用面积，另一方面可更好地对晶体管组进行遮挡。像素子发光区中的像素电路也可具有多个薄膜晶体管和电容结构，多个薄膜晶体管的有源层10可由一整层半导体材料通过构图工艺形成。类似地，栅极层20可由一整层金属材料通过构图工艺形成多个金属块以及金属走线，以充当薄膜晶体管的栅极，以及栅线等走线，并和其他金属层形成电容结构。源漏极层30也可用于形成源漏电极和数据走线。多条信号线40可以由栅极金属或是源漏极金属通过构图工艺形成，需要形成电连接的金属走线，以及薄膜晶体管的源漏极和有源层之间可以通过过孔的方式实现连接。
在本申请的一些示例中，相邻的两个像素区1100之间具有两个遮光孔。该遮光孔沿所述第一方向的长度与晶体管组1210的长度相一致。也即是说，可进一步提高遮光孔对薄膜晶体管有源层的保护。根据本申请的一些示例，遮光孔的深度以及宽度不受特别限制，例如在一些示例中，遮光孔的深度可以为1-3微米，遮光孔的宽度为3-10微米。其中，遮光孔的深度为沿着垂直于基板100所在平面方向上的延伸深度，宽度为在基板100所在平面上，遮光孔垂直于第一方向的尺寸。
在本申请中，遮光孔的具体形状和尺寸不受特别限制，本领域技术人员可根据实际情况进行选择。例如，遮光孔可以为贯穿像素界定结构的通孔，也可为不完全贯穿像素界定结构的盲孔。遮光孔在基板100上的正投影可以为条形、圆孔或其他形状，只要能够令填充在遮光孔内的金属层遮挡照射至有源层的光即可。
类似地，金属层50的具体结构也不受特别限制。例如，当金属层50是由阴极金属形成时，金属层50可以与发光元件80的阴极830相连(图中未示出此种结构)，也可具有如 图2中所示出的结构，即金属层50与阴极830不相连。本领域技术人员能够理解的是，此处仅示出了发光元件800的一种情况，即发光元件800包括阳极810，阴极830以及夹设与其中的发光层820。在本申请的另一些示例中，发光元件800的结构不限于此，还可具有包括但不限于电子传输层、电子阻挡层、空穴传输层以及空穴阻挡层等结构。
此处需要特别说明的是，遮光孔沿所述第一方向的长度与晶体管组1210的长度相一致，表示的含义为二者的长度大致一致，而并非长度完全相等。即遮光孔的长度可以和晶体管组延伸的长度大致相同，从而实现更好的遮挡效果。遮光孔的长度可以较晶体管组的长度稍短，也可以较晶体管组的长度长。本领域技术人员可以根据晶体管组中多个有源层的具体位置，调节遮光孔的设置位置和长度。
在本申请的一些示例中，像素区在所述基板上阵列排布，每个所述像素区至少包括两个子像素，每行所述像素区与至少两个所述栅极驱动电路区对应，每个所述栅极驱动电路区位于相邻两个所述像素区之间，所述栅极驱动电路包括级联的多个移位寄存器，每个所述移位寄存器与一行所述子像素电连接；每个所述移位寄存器包括多个晶体管组，每个所述晶体管组包括至少一个所述薄膜晶体管。
下面结合本申请的一些示例，对栅极驱动电路的具体结构以及工作原理进行简单说明：
参考图1以及图3以及图4，像素电路子区1100中可具有像素电路。每个子像素对应一个像素电路，像素电路的结构不受特别限制，像素电路用于控制像素发光子区中的发光元件的发光，例如控制其打开和关闭，并调节发光亮度。具体的像素电路结构可以根据实际需要选择设置。例如，像素电路的结构可以包括“2T1C”、“6T1C”、“7T1C”、“6T2C”或“7T2C”等结构，“T”为薄膜晶体管，位于“T”前面的数字表示为薄膜晶体管的数量，“C”为存储电容器，位于“C”前面的数字表示为存储电容器的数量。通常情况下像素电路可以包括一个开关晶体管和一个驱动晶体管。在本申请的一个示例中，像素电路可以具有如图4所示出的结构。
在显示面板使用的过程中，像素电路中的薄膜晶体管及发光器件(OLED)的稳定性可能会下降(例如驱动晶体管的阈值电压漂移)，影响显示面板的显示效果，因此需要对子像素的像素电路进行补偿。补偿的方式可以包括多种，可以根据实际需要选择设置。例如，可以在子像素中设置像素补偿电路，以利用该像素补偿电路对子像素进行内部补偿。又如，可以通过子像素内部的薄膜晶体管对驱动晶体管或发光器件进行测定，并将测定到的数据传输到外部感应电路，以利用该外部感应电路计算需要补偿的驱动电压值并进行外部补偿。
以采用外部补偿的方式，且像素电路采用3T1C(包括开关晶体管T1、驱动晶体管T2、感测晶体管T3和存储电容器Cst)的结构为例，在一些示例中，开关晶体管T1的控制极(栅极)与第一栅极信号端G1电连接，开关晶体管T1的第一极(源漏极中的一个)与数据信 号端Data电连接，开关晶体管T1的第二极(源漏极中另的一个)与第一节点G电连接。此时开关晶体管T1可响应于在第一栅极信号端G1处接收的第一栅极信号，即开关晶体管T1打开将在数据信号端Data处接收的数据信号传输至第一节点G。数据信号具体可包括检测数据信号和显示数据信号。驱动晶体管T2的控制极与第一节点G电连接，驱动晶体管T2的第一极与第四电压信号端ELVDD电连接，驱动晶体管T2的第二极与第二节点S电连接。进而驱动晶体管T2在节点G的电压的控制下打开，可将在第四电压信号端ELVDD处接收的第四电压信号传输至第二节点S。存储电容器Cst的第一端与第一节点G电连接，第二端与第二节点S电连接。由此，开关晶体管T1在对第一节点G进行充电的过程中，同时可以对存储电容器Cst进行充电。发光器件(OLED)的阳极与第二节点S电连接，阴极与第五电压信号端ELVSS电连接，从而可在来自第二节点S处的第四电压信号和第五电压信号端ELVSS所传输的第五电压信号的相互配合下进行发光。
感测晶体管T3的控制极与第二栅极信号端G2电连接，第一极与第二节点S电连接，第二极与感测信号端Sense电连接。感测晶体管T3可以响应于在第二栅极信号端G2处接收的第二栅极信号，检测驱动晶体管T2的电特性以实现外部补偿。根据本申请的一些示例，该电特性可以包括驱动晶体管T2的阈值电压和载流子迁移率中的一个或两个。感测信号端Sense可以提供复位信号或获取感测信号，其中复位信号用于对第二节点S进行复位，获取感测信号用于获取驱动晶体管T2的阈值电压。
在一些示例中，每个子像素在第一栅极信号端G1处接收的第一栅极信号与在第二栅极信号端G2处接收的第二栅极信号可以是相同的。具体地，同一行子像素中的多个像素电路可以与两条栅线(如图3中所示出的栅极层20形成的)电连接，两条栅线传递的电信号相同。或者，同一行子像素中的多个像素电路可以与一条栅线电连接。
在本申请的一些实例中，一帧的显示阶段可以包括依次进行的显示时段和消隐时段。具体地，在一帧显示阶段中的显示时段，子像素的工作过程例如可以包括复位阶段、数据写入阶段和发光阶段。下面，以薄膜晶体管均为N型晶体管为例进行说明：
在复位阶段中，参考图4，第二栅极信号端G2所提供的第二栅极信号的电平为高电平，感测信号端Sense提供复位信号(该复位信号的电平例如为低电平)。感测晶体管T3在第二栅极信号的控制下导通，接收复位信号，并将该复位信号传输至第二节点S，对第二节点S进行复位。在数据写入阶段中，第一栅极信号端G1所提供的第一栅极信号的电平为高电平，数据信号端Data所提供的显示数据信号的电平为高电平。开关晶体管T1在第一栅极信号的控制下导通，接收显示数据信号，并将该显示数据信号传输至第一节点G，同时对存储电容器Cst进行充电。在发光阶段中，第一栅极信号端G1所提供的第一栅极信号的电平为低电平，第二栅极信号端G2所提供的第二栅极信号的电平为低电平，第四电压信号端 ELVDD所提供的第四电压信号的电平为高电平。开关晶体管T1在第一栅极信号的控制下关断，感测晶体管T3在第二栅极信号的控制下关断。存储电容器Cst开始放电，使得第一节点G的电压保持为高电平。驱动晶体管T2在第一节点G的电压的控制下导通，接收第四电压信号，并将该第四电压信号传输至第二节点S，使得发光器件在第四电压信号和第五电压信号端ELVSS所传输的第五电压信号的相互配合下进行发光。
在一帧显示阶段中的消隐时段子像素的工作过程可以包括：第一阶段和第二阶段。在第一阶段中，第一栅极信号端G1所提供的第一栅极信号的电平和第二栅极信号端G2所提供的第二栅极信号的电平均为高电平，数据信号端Data所提供的检测数据信号的电平为高电平。开关晶体管T1在第一栅极信号的控制下导通，接收检测数据信号，并将该检测数据信号传输至第一节点G，对第一节点G进行充电。感测晶体管T3在第二栅极信号的控制下导通，接收感测信号端Sense提供复位信号，并将该复位信号传输至第二节点S。在第二阶段中，感测信号端Sense处于悬浮状态。驱动晶体管T2在第一节点G的电压的控制下导通，接收第四电压信号端ELVDD所提供的第四电压信号，并将该第四电压信号传输至第二节点S，对第二节点S进行充电，使得第二节点S的电压升高，直至驱动晶体管T2截止。此时，第一节点G和第二节点S之间的电压差Vgs等于驱动晶体管T2的阈值电压Vth。由于感测晶体管T3处于导通状态、且感测信号端Sense处于悬浮状态，因此，在驱动晶体管T2对第二节点S进行充电的过程中，同时还会对感测信号端Sense进行充电。通过对感测信号端Sense进行电压取样(也即获取感测信号)，便可以根据感测信号端Sense的电压和检测数据信号的电平之间的关系，计算得到驱动晶体管T2的阈值电压Vth。在计算得到驱动晶体管T2的阈值电压Vth之后，便可以将该阈值电压Vth补偿进下一帧显示阶段中显示时段的显示数据信号中，完成对子像素的外部补偿。
在一些示例中，参考图5以及图6，栅极驱动电路可以包括多级级联的移位寄存器1230，一级移位寄存器可以与一行子像素中的多个像素电路电连接。在一帧的显示阶段中，第一栅极信号端G1所传输的第一栅极信号和第二栅极信号端G2所传输的第二栅极信号可以均由栅极驱动电路提供，栅极驱动电路中的每级移位寄存器1230可以通过第一栅线与第一栅极信号端G1电连接，通过该第一栅线向第一栅极信号端G1传输第一栅极信号，并通过第二栅线与第二栅极信号端G2电连接，通过该第二栅线向第二栅极信号端G2传输第二栅极信号。
上述移位寄存器1230的结构不受特别限制，可以根据实际需要选择设置。下面对两种结构的移位寄存器的结构进行示意性说明，但不能理解为对移位寄存器1230的限制：
在一些示例中，如图5和图6所示，移位寄存器1230可以包括：第一输入电路3101、防漏电电路3102、输出电路3103、控制电路3104、第一复位电路3105、第二复位电路3106、 第三复位电路3107、第四复位电路3108及第五复位电路3109。
示例性的，如图5和图6所示，第一输入电路3101与输入信号端(附图以及下文均简写为Iput)、上拉节点Q<N>及防漏电节点OFF<N>电连接。第一输入电路3101可在一帧显示阶段中的显示时段，基于输入信号端Iput处接收的输入信号，将输入信号传输至上拉节点Q<N>。其中N为正整数，表示为子像素的行数。更具体地，在输入信号的电平为高电平的情况下，第一输入电路3101可以在输入信号的作用下导通，并将输入信号传输至上拉节点Q<N>，对上拉节点Q<N>进行充电，使得上拉节点Q<N>的电压升高。第一输入电路3101具体可以包括第一晶体管M1和第二晶体管M2。第一晶体管M1的控制极与输入信号端Iput电连接，第一晶体管M1的第一极与输入信号端Iput电连接，第一晶体管M1的第二极与第二晶体管M2的第一极及第一防漏电节点OFF1电连接。第二晶体管M2的控制极与输入信号端Iput电连接，第二晶体管M2的第二极与第一上拉节点Q1电连接。
由此，在输入信号端Iput所传输的输入信号的电平为高电平的情况下，第一晶体管M1和第二晶体管M2可以在该输入信号的作用下同时导通。第一晶体管M1可以接收输入信号端Iput所传输的输入信号，并将所接收的输入信号传输至第二晶体管M2的第一极及防漏电节点OFF<N>。第二晶体管M2可以将所接收的输入信号传输至上拉节点Q<N>，对上拉节点Q<N>进行充电，使得上拉节点Q<N>的电压升高。
根据本申请的一些示例，防漏电电路3102可以与上拉节点Q<N>、第一电压信号端VDD及防漏电节点OFF<N>电连接。防漏电电路3102可在上拉节点Q<N>的电压的控制下，将第一电压信号端VDD所传输的第一电压信号传输至防漏电节点OFF<N>，以防止上拉节点Q<N>漏电：具体地，可以避免上拉节点Q<N>通过第一输入电路3101发生漏电，使得上拉节点Q<N>能够保持有一个较高的、较为稳定的电压。第一电压信号可以为恒定高电压信号。
例如，在上拉节点Q<N>的电压为高电平的情况下，防漏电电路3102可以在上拉节点Q<N>的电压的控制下导通，接收并传输第一电压信号至防漏电节点OFF<N>，使得防漏电节点OFF<N>的电压升高。防漏电电路3102具体可以包括第三晶体管M3，第三晶体管M3的控制极与上拉节点Q<N>电连接，第三晶体管M3的第一极与第一电压信号端VDD电连接，第三晶体管M3的第二极与防漏电节点OFF<N>电连接。由此，在上拉节点Q<N>的电压为高电平的情况下，第三晶体管M3可以在上拉节点Q<N>的电压的控制下导通，将第一电压信号传输至防漏电节点OFF<N>，使得防漏电节点OFF<N>的电压升高，并使得第二晶体管M2的控制极与第一极之间的压差小于零，确保第二晶体管M2被完全或较为完全地截止。
示例性的，如图5和图6所示，输出电路3103与上拉节点Q<N>、第一时钟信号端CLKE_1及第一输出信号端Output1<N>(附图以及下文均简写为Oput1<N>)电连接。其中， 输出电路3103可在一帧显示阶段中的显示时段，在上拉节点Q<N>的电压的控制下将在第一时钟信号端CLKE_1处接收的第一时钟信号传输至第一输出信号端Oput1<N>。
当然，如图5所示，输出电路3103例如还可以与第三时钟信号端CLKD_1及移位信号端CR<N>电连接。其中，输出电路3103还可在一帧显示阶段中的显示时段，在上拉节点Q<N>的电压的控制下，将在第三时钟信号端CLKD_1处接收的第三时钟信号传输至移位信号端CR<N>。
当然，示例性地输出电路3103还可以与第四时钟信号端CLKF_1及第二输出信号端Output2<N>(附图以及下文均简写为Oput2<N>)电连接。在一帧显示阶段中的消隐时段，输出电路3103在上拉节点Q<N>的电压的控制下，可以将在第四时钟信号端CLKF_1处接收的第四时钟信号传输至第二输出信号端Oput2<N>。具体地，在上拉节点Q<N>的电压升高的情况下，输出电路3103可以在上拉节点Q<N>的电压的控制下导通，将在第三时钟信号端CLKD_1处接收的第三时钟信号作为移位信号，从移位信号端CR<N>输出；将在第一时钟信号端CLKE_1处接收的第一时钟信号作为第一输出信号，从第一输出信号端Oput1<N>输出。在一帧显示阶段中的消隐时段，在上拉节点Q<N>的电压升高的情况下，输出电路3103可以在上拉节点Q<N>的电压的控制下导通，将在第四时钟信号端CLKF_1处接收的第四时钟信号作为第二输出信号，从第二输出信号端Oput2<N>输出。更具体地，第一输出信号端Oput1<N>可以与第一栅线电连接，第一输出信号端Oput1<N>输出的第一输出信号可以作为第一栅极信号，依次经第一栅线及第一栅极信号端G1传输至像素电路12。第二输出信号端Oput2<N>可以与第二栅线电连接，第二输出信号端Oput2<N>输出的第二输出信号可以作为第二栅极信号，依次经第二栅线及第二栅极信号端G2传输至像素电路。
根据本申请的一些示例，参考图6，输出电路3103可以包括第四晶体管M4、第五晶体管M5、第六晶体管M6、第一电容器C1和第二电容器C2。第四晶体管M4的控制极与上拉节点Q<N>电连接，第四晶体管M4的第一极与第三时钟信号端CLKD_1电连接，第四晶体管M4的第二极与移位信号端CR<N>电连接。
在一帧显示阶段中的显示时段，在第一输入电路3101导通，使得上拉节点Q<N>的电压升高的情况下，第四晶体管M4可以在上拉节点Q<N>的高电压的控制下导通，将第三时钟信号传输至移位信号端CR<N>，并将该第三时钟信号作为移位信号从移位信号端CR<N>输出。第五晶体管M5的控制极与上拉节点Q<N>电连接，第五晶体管M5的第一极与第一时钟信号端CLKE_1电连接，第五晶体管M5的第二极与第一输出信号端Oput1<N>电连接。第一电容器C1的第一端与上拉节点Q<N>电连接，第一电容器C1的第二端与第一输出信号端Oput1<N>电连接。
在一帧显示阶段中的显示时段，在第一输入电路3101导通、使得上拉节点Q<N>的电压升高的同时，对第一电容器C1进行充电。在第一输入电路3101关断的情况下，第一电容器C1可以进行放电，使得上拉节点Q<N>保持为高电平，进而使得第五晶体管M5可以保持导通状态，将第一时钟信号传输至第一输出信号端Oput1<N>，并将该第一时钟信号作为第一输出信号从第一输出信号端Oput1<N>输出。
示例性地，第六晶体管M6的控制极与上拉节点Q<N>电连接，第六晶体管M6的第一极与第四时钟信号端CLKF_1电连接，第六晶体管M6的第二极与第二输出信号端Oput2<N>电连接。第二电容器C2的第一端与上拉节点Q<N>电连接，第二电容器C2的第二端与第二输出信号端Oput2<N>电连接。在一帧显示阶段中的消隐时段，在上拉节点Q<N>的电压升高的同时，会对第二电容器C2进行充电。在相应的阶段，第二电容器C2可以进行放电，使得上拉节点Q<N>保持为高电平，进而使得第六晶体管M6可以保持导通状态，将第四时钟信号传输至第二输出信号端Oput2<N>，并将该第四时钟信号作为第二输出信号从第二输出信号端Oput2<N>输出。
根据本申请的一些示例，在将多级移位寄存器1230级联构成栅极驱动电路后，第N级移位寄存器中的移位信号端CR<N>例如可以与第N+1级移位寄存器中的输入信号端Iput电连接，进而将第N级移位寄存器的移位信号端CR<N>所输出的移位信号作为第N+1级移位寄存器21中的输入信号。当然，多级移位寄存器级联的关系并不局限于此，本领域技术人员可根据实际情况进行设计。
根据本申请的另一些示例，一部分移位寄存器1230的输入信号端Iput还可以与起始信号端STU电连接，即接收该起始信号端STU所传输的起始信号作为输入信号。具体地，该部分移位寄存器可以为栅极驱动电路中的第一级移位寄存器，或者可以为第一级移位寄存器和第二级移位寄存器等。与起始信号端STU电连接的移位寄存器的数量不做限定，本领域技术人员可以根据实际需要选择设置。
示例性的，如图5和图6所示，控制电路3104与上拉节点Q<N>、第六电压信号端VDD_A、下拉节点QB_A及第二电压信号端VGL1电连接。其中，控制电路3104被配置为，在上拉节点Q<N>的电压和第六电压信号端VDD_A所传输的第六电压信号的控制下，对下拉节点QB_A的电压进行控制。第六电压信号的电平在一帧的显示阶段内例如可以不变。第二电压信号端VGL1可以被配置为传输直流低电平信号(例如低于或等于时钟信号的低电平部分)。该第二电压信号端VGL1例如可以接地。
具体地，在上拉节点Q<N>的电压升高的情况下，控制电路3104可以将第二电压信号端VGL1所传输的第二电压信号传输至下拉节点QB_A，将下拉节点QB_A的电压拉低至低电压。在上拉节点Q<N>的电压为低电压的情况下，控制电路3104可以将第六电压信号 端VDD_A所传输的第六电压信号传输至下拉节点QB_A，将下拉节点QB_A的电压拉高至高电平。控制电路3104可以包括：第七晶体管M7、第八晶体管M8、第九晶体管M9和第十晶体管M10。第七晶体管M7的控制极与第六电压信号端VDD_A电连接，第七晶体管M7的第一极与第六电压信号端VDD_A电连接，第七晶体管M7的第二极与第八晶体管M8的控制极及第九晶体管M9的第一极电连接。第八晶体管M8的第一极与第六电压信号端VDD_A电连接，第八晶体管M8的第二极与下拉节点QB_A及第十晶体管M10的第一极电连接。第九晶体管M9的控制极与上拉节点Q<N>电连接，第九晶体管M9的第二极与第二电压信号端VGL1电连接。第十晶体管M10的控制极与上拉节点Q<N>电连接，第十晶体管M10的第二极与第二电压信号端VGL1电连接。
由此，在第六电压信号端VDD_A所传输的第六电压信号的电平为高电平的情况下，第七晶体管M7可以在第六电压信号的作用下导通，接收并传输第六电压信号至第八晶体管M8的控制极及第九晶体管M9的第一极。第八晶体管M8可以在第六电压信号的作用下导通，接收并传输第六电压信号至下拉节点QB_A及第十晶体管M10的第一极。
在上拉节点Q<N>的电压为高电平的情况下，第九晶体管M9和第十晶体管M10可以在上拉节点Q<N>的电压的控制下导通，第九晶体管M9可以将第二电压信号端VGL1所传输的第二电压信号传输至第八晶体管M8的控制极，使得第八晶体管M8关断，第十晶体管M10可以将第二电压信号传输至下拉节点QB_A，将下拉节点QB_A的电压拉低至低电平。
在上拉节点Q<N>的电压为低电平的情况下，第九晶体管M9和第十晶体管M10可以在上拉节点Q<N>的电压的控制下关断，第八晶体管M8可以将所接收的第六电压信号传输至下拉节点QB_A，将下拉节点QB_A的电压拉高至高电平。
根据本申请的一些示例，第一复位电路3105与下拉节点QB_A、上拉节点Q<N>、第二电压信号端VGL1及防漏电节点OFF<N>电连接。其中，第一复位电路3105可在下拉节点QB_A的电压的控制下，对上拉节点Q<N>进行复位：
在下拉节点QB_A的电压为高电平的情况下，第一复位电路3105可以在下拉节点QB_A的电压的作用下导通，将第二电压信号端VGL1所传输的第二电压信号传输至上拉节点Q<N>，对上拉节点Q<N>进行下拉复位。具体而言，第一复位电路3105可以包括：第十一晶体管M11和第十二晶体管M12。第十一晶体管M11的控制极与下拉节点QB_A电连接，第十一晶体管M11的第一极与上拉节点Q<N>电连接，第十一晶体管M11的第二极与第十二晶体管M12的第一极及防漏电节点OFF<N>电连接。第十二晶体管M12的控制极与下拉节点QB_A电连接，第十二晶体管M12的第二极与第二电压信号端VGL1电连接。
在下拉节点QB_A的电压为高电平的情况下，第十一晶体管M11和第十二晶体管M12可以在下拉节点QB_A的电压的作用下同时导通，第十二晶体管M12可以将第二电压信号 端VGL1所传输的第二电压信号传输至防漏电节点OFF<N>，第十一晶体管M11可以将来自防漏电节点OFF<N>的第二电压信号传输至上拉节点Q<N>，对上拉节点Q<N>进行复位。
在上拉节点Q<N>的电位为高电位、且第一复位电路3105处于未工作的状态的情况下，第三晶体管M3可以在上拉节点Q<N>的电压的控制下导通，将第一电压信号传输至防漏电节点OFF<N>，使得防漏电节点OFF<N>的电压升高，进而使得第十一晶体管M11的控制极与第二极之间的压差小于零，确保第十一晶体管M11被完全或较为完全地截止。由此，可避免上拉节点Q<N>通过第一复位电路3105发生漏电，使得上拉节点Q<N>能够保持有一个较高的、较为稳定的电压。
如图5和图6所示，第二复位电路3106可以与显示复位信号端STD、上拉节点Q<N>、第二电压信号端VGL1及防漏电节点OFF<N>电连接。由此，第二复位电路3106可在显示复位信号端STD所传输的显示复位信号的控制下，对上拉节点Q<N>进行复位：
在显示复位信号的电平为高电平的情况下，第二复位电路3106可以在显示复位信号的作用下导通，将第二电压信号端VGL1所传输的第二电压信号传输至上拉节点Q<N>，对上拉节点Q<N>进行下拉复位。第二复位电路3106可以包括第十三晶体管M13和第十四晶体管M14。第十三晶体管M13的控制极与显示复位信号端STD电连接，第十三晶体管M13的第一极与上拉节点Q<N>电连接，第十三晶体管M13的第二极与第十四晶体管M14的第一极及防漏电节点OFF<N>电连接。第十四晶体管M14的控制极与显示复位信号端STD电连接，第十四晶体管M14的第二极与第二电压信号端VGL1电连接。
在显示复位信号的电压为高电平的情况下，第十三晶体管M13和第十四晶体管M14可以在显示复位信号的作用下同时导通，第十四晶体管M14可以将第二电压信号端VGL1所传输的第二电压信号传输至防漏电节点OFF<N>，第十三晶体管M13可以将来自防漏电节点OFF<N>的第二电压信号传输至上拉节点Q<N>，对上拉节点Q<N>进行复位。
具体地，在上拉节点Q<N>的电位为高电位、且第二复位电路3106处于未工作的状态的情况下，第三晶体管M3可以在上拉节点Q<N>的电压的控制下导通，将第一电压信号传输至防漏电节点OFF<N>，使得防漏电节点OFF<N>的电压升高，进而使得第十三晶体管M13的控制极与第二极之间的压差小于零，确保第十三晶体管M13被完全或较为完全地截止。这样可以避免上拉节点Q<N>通过第二复位电路3106发生漏电，使得上拉节点Q<N>能够保持有一个较高的、较为稳定的电压。
类似地，在将多级移位寄存器级联构成栅极驱动电路后，第N级移位寄存器1230的显示复位信号端STD例如可以与第N+4级移位寄存器的移位信号端CR<N>电连接，进而将该第N+4级移位寄存器的移位信号端CR<N>所输出的移位信号作为第N级移位寄存器的显示复位信号。
示例性的，如图5和图6所示，第三复位电路3107可以与全局复位信号端TRST、上拉节点Q<N>、第二电压信号端VGL1及防漏电节点OFF<N>电连接。由此第三复位电路3107可在全局复位信号端TRST所传输的全局复位信号的控制下，对上拉节点Q<N>进行复位：
例如，在全局复位信号的电平为高电平的情况下，第三复位电路3107可以在全局复位信号的作用下导通，将第二电压信号端VGL1所传输的第二电压信号传输至上拉节点Q<N>，对上拉节点Q<N>进行下拉复位。具体地，第三复位电路3107可以包括：第十五晶体管M15和第十六晶体管M16。第十五晶体管M15的控制极与全局复位信号端TRST电连接，第十五晶体管M15的第一极与上拉节点Q<N>电连接，第十五晶体管M15的第二极与第十六晶体管M16的第一极及防漏电节点OFF<N>电连接。第十六晶体管M16的控制极与全局复位信号端TRST电连接，第十六晶体管M16的第二极与第二电压信号端VGL1电连接。
在全局复位信号的电压为高电平的情况下，第十五晶体管M15和第十六晶体管M16可以在全局复位信号的作用下同时导通，第十六晶体管M16可以将第二电压信号端VGL1所传输的第二电压信号传输至防漏电节点OFF<N>，第十五晶体管M15可以将来自防漏电节点OFF<N>的第五电压信号传输至上拉节点Q<N>，对上拉节点Q<N>进行复位。
此处，在上拉节点Q<N>的电位为高电位、且第三复位电路3107处于未工作的状态的情况下，第三晶体管M3可以在上拉节点Q<N>的电压的控制下导通，将第一电压信号传输至防漏电节点OFF<N>，使得防漏电节点OFF<N>的电压升高，进而使得第十五晶体管M15的控制极与第二极之间的压差小于零，确保第十五晶体管M15被完全或较为完全地截止。这样可以避免上拉节点Q<N>通过第三复位电路3107发生漏电，使得上拉节点Q<N>能够保持有一个较高的、较为稳定的电压。
示例性的，如图6所示，第四复位电路3108可以与下拉节点QB_A、移位信号端CR<N>、第一输出信号端Oput1<N>、第二输出信号端Oput2<N>、第二电压信号端VGL1及第三电压信号端VGL2电连接。第四复位电路3108可以在下拉节点QB_A的电压的控制下，对移位信号端CR<N>、第一输出信号端Oput1<N>及第二输出信号端Oput2<N>进行复位。
在本申请的一些实例中，第三电压信号端VGL2被配置为传输直流低电平信号(例如低于或等于时钟信号的低电平部分)。该第三电压信号端VGL2例如可以接地。第二电压信号端VGL1和第三电压信号端VGL2所传输的低电平信号的可以相等，也可以不相等。
具体地，在下拉节点QB_A的电压为高电平的情况下，第四复位电路3108可以在下拉节点QB_A的电压的作用下导通，将第二电压信号端VGL1所传输的第二电压信号传输至移位信号端CR<N>，对移位信号端CR<N>进行下拉复位，将第三电压信号端VGL2所传输 的第三电压信号传输至第一输出信号端Oput1<N>，对第一输出信号端Oput1<N>进行下拉复位，将第三电压信号端VGL2所传输的第三电压信号传输至第二输出信号端Oput2<N>，对第二输出信号端Oput2<N>进行下拉复位。
更具体地，第四复位电路3108可以包括：第十七晶体管M17、第十八晶体管M18和第十九晶体管M19。第十七晶体管M17的控制极与下拉节点QB_A电连接，第十七晶体管M17的第一极与移位信号端CR<N>电连接，第十七晶体管M17的第二极与第二电压信号端VGL1电连接。
在下拉节点QB_A的电压为高电平的情况下，第十七晶体管M17可以在下拉节点QB_A的电压的作用下导通，将第二电压信号端VGL1所传输的第二电压信号传输至移位信号端CR<N>，对移位信号端CR<N>进行下拉复位。第十八晶体管M18的控制极与下拉节点QB_A电连接，第十八晶体管M18的第一极与第一输出信号端Oput1<N>电连接，第十八晶体管M18的第二极与第三电压信号端VGL2电连接。在下拉节点QB_A的电压为高电平的情况下，第十八晶体管M18可以在下拉节点QB_A的电压的作用下导通，将第三电压信号端VGL2所传输的第三电压信号传输至第一输出信号端Oput1<N>，对第一输出信号端Oput1<N>进行下拉复位。第十九晶体管M19的控制极与下拉节点QB_A电连接，第十九晶体管M19的第一极与第二输出信号端Oput2<N>电连接，第十九晶体管M19的第二极与第三电压信号端VGL2电连接。在下拉节点QB_A的电压为高电平的情况下，第十九晶体管M19可以在下拉节点QB_A的电压的作用下导通，将第三电压信号端VGL2所传输的第三电压信号传输至第二输出信号端Oput2<N>，对第二输出信号端Oput2<N>进行下拉复位。
示例性的，如图5和图6所示，第五复位电路3109与输入信号端Iput、下拉节点QB_A及第二电压信号端VGL1电连接。第五复位电路3109可以在输入信号端Iput所传输的输入信号的控制下，对下拉节点QB_A进行复位：
例如，在输入信号的电平为高电平的情况下，第五复位电路3109可以在输入信号的作用下导通，将第二电压信号端VGL1所传输的第二电压信号传输至下拉节点QB_A，对下拉节点QB_A进行下拉复位。具体地，第五复位电路3109可以包括：第二十晶体管M20。
第二十晶体管M20的控制极与输入信号端Iput电连接，第二十晶体管M20的第一极与下拉节点QB_A电连接，第二十晶体管M20的第二极与第二电压信号端VGL1电连接。在输入信号的电平为高电平的情况下，第二十晶体管M20可以在输入信号的作用下导通，将第二电压信号端VGL1所传输的第二电压信号传输至下拉节点QB_A，对下拉节点QB_A进行下拉复位。
在本申请的一些示例中，参考图6，栅极驱动电路还可以包括多个消隐输入电路3200。一个消隐输入电路可以与相邻的至少两级移位寄存器电连接。换句话说，可令至少两级移 位寄存器共用一个消隐输入电路。消隐输入电路可以在一帧显示阶段的消隐时段，控制相应的移位寄存器向相应行的像素电路输入消隐控制信号，使得该像素电路获取感测信号：
具体地，如图6所示，消隐输入电路3200例如可以包括选择控制电路3201、第二输入电路3202及至少两个传输电路3203。选择控制电路3201与选择控制信号端OE、移位信号端CR<N>、第二电压信号端VGL1及第一消隐节点H电连接，在选择控制信号端OE所传输的选择控制信号的控制下，将在移位信号端CR<N>处接收的移位信号传输至第一消隐节点H。
具体地，在选择控制信号的电平为高电平的情况下，选择控制电路3201可以在该选择控制信号的控制下导通，并将所接收的移位信号传输至第一消隐节点H，对第一消隐节点H进行充电，使得第一消隐节点H的电压升高。在一帧显示阶段的消隐时段，在需要获取感测信号的情况下，可以使得选择控制信号的波形时序和输入信号的波形时序相同，进而使得选择控制电路3201导通。具体地，选择控制电路3201可以包括：第二十一晶体管M21、第二十二晶体管M22和第三电容器C3。第二十一晶体管M21的控制极与选择控制信号端OE电连接，第二十一晶体管M21的第一极与移位信号端CR<N>电连接，第二十一晶体管M21的第二极与第二十二晶体管M22的第一极电连接。第二十二晶体管M22的控制极与选择控制信号端OE电连接，第二十二晶体管M22的第二极与第一消隐节点H电连接。
在选择控制信号端OE所传输的选择控制信号的电平为高电平的情况下，第二十一晶体管M21、第二十二晶体管M22可以在选择控制信号的作用下同时导通，第二十一晶体管M21可以将移位信号端CR<N>所传输的移位信号传输至第二十二晶体管M22的第一极，第二十二晶体管M22可以接收并传输移位信号至第一消隐节点H，对第一消隐节点H进行充电。第三电容器C3的第一端与第一消隐节点H电连接，第三电容器C3的第二端与第二电压信号端VGL1电连接。在选择控制电路3201对第一消隐节点H进行充电的过程中，还会对第三电容器C3进行充电。这样可以在选择控制电路3201关断的情况下，利用第三电容器C3放电，使得第一消隐节点H保持高电平。
具体地，选择控制电路3201例如还可以包括：第二十三晶体管M23。第二十三晶体管M23的控制极与第一消隐节点H电连接，第二十三晶体管M23的第一极与第一电压信号端VDD电连接，第二十三晶体管M23的第二极与第二十二晶体管M22的第一极电连接。由此，在第一消隐节点H的电压为高电平、且第二十一晶体管M21和第二十二晶体管M22未工作的情况下，第二十三晶体管M23可以在第一消隐节点H的电压的控制下导通，将第一电压信号端VDD所传输的第一电压信号传输至第二十二晶体管M22的第一极，使得第二十二晶体管M22的第一极的电压升高，进而使得第二十二晶体管M22的控制极与第一极之间的压差小于零，确保第二十二晶体管M22被完全或较为完全地截止。这样可以避免第 一消隐节点H通过第二十二晶体管M22发生漏电，使得第一消隐节点H能够保持有一个较高的、较为稳定的电压。
根据本发明的一些示例，第二输入电路3202与第一消隐节点H、第二消隐节点N及第二时钟信号端CLKA或第一电压信号端VDD电连接，以在第一消隐节点H的电压的控制下，将在第二时钟信号端CLKA处接收的第二时钟信号或在第一电压信号端VDD处接收的第一电压信号传输至第二消隐节点N。
例如，在选择控制电路3201导通、使得第一消隐节点H的电压升高的情况下，第二输入电路3202可以在第一消隐节点H的电压的控制下导通，接收第二时钟信号端CLKA所传输的第二时钟信号，并将该第二时钟信号传输至第二消隐节点N。具体地，第二输入电路3202可以包括：第二十四晶体管M24。第二十四晶体管M24的控制极与第一消隐节点H电连接，第二十四晶体管M24的第一极与第二时钟信号端CLKA或第一电压信号端VDD电连接，第二十四晶体管M24的第二极与第二消隐节点N电连接。
在第一消隐节点H的电压为高电平的情况下，第二十四晶体管M24可以在第一消隐节点H的电压的控制下导通，将在第四时钟信号端CLKA处接收的第四时钟信号或在第一电压信号端VDD处接收的第一电压信号传输至第二消隐节点N。
示例性的，上述至少两个传输电路3203可以与至少两个移位寄存器一一对应地电连接。一个传输电路3203与第二消隐节点N、第二时钟信号端CLKA及一级移位寄存器的上拉节点Q<N>电连接。其中，传输电路3202被配置为，在第二时钟信号端CLKA所传输的第二时钟信号的控制下，将在第二消隐节点N处接收的第二时钟信号或第一电压信号传输至上拉节点Q<N>。
例如，在第二时钟信号端CLKA所传输的第二时钟信号的电平为高电平的情况下，传输电路3202可以在该第二时钟信号的控制下导通，并从第二消隐节点N处接收第二时钟信号或第一电压信号，将所接收的第二时钟信号或第一电压信号传输至上拉节点Q<N>，使得上拉节点Q<N>的电压升高，进而可以使得输出电路3103导通，使得输出电路3103的第二输出信号端Oput2<N>输出第二输出信号。具体地，传输电路3203可以包括：第二十五晶体管M25和第二十六晶体管M26。第二十五晶体管M25的控制极与第二时钟信号端CLKA电连接，第二十五晶体管M25的第一极与第二消隐节点N电连接，第二十五晶体管M25的第二极与第二十六晶体管M26的第一极电连接。第二十六晶体管M26的控制极与第二时钟信号端CLKA电连接，第二十六晶体管M26的第二极与上拉节点Q<N>电连接。
由此，在第二时钟信号端CLKA所传输的第二时钟信号的电平为高电平的情况下，第二十五晶体管M25和第二十六晶体管M26可以在第二时钟信号的作用下同时导通，第二十五晶体管M25可以将来自第二消隐节点N的第二时钟信号或第一电压信号传输至第二十六 晶体管M26的第一极，第二十六晶体管M26可以接收并传输第二时钟信号或第一电压信号至上拉节点Q<N>，对上拉节点Q<N>进行充电。输出电路3103中的第六晶体管M6可以在上拉节点Q<N>的电压的控制下导通，接收第四时钟信号，并将该第四时钟信号作为第二输出信号从第二输出信号端Oput2<N>输出。
在传输电路3203还与防漏电节点OFF<N>电连接的情况下，第二十六晶体管M26的第一极可以与防漏电节点OFF<N>及第二十五晶体管M25的第二极电连接，此时，在上拉节点Q<N>的电位为高电位、且传输电路3203处于未工作的状态的情况下，第三晶体管M3可以在上拉节点Q<N>的电压的控制下导通，将第一电压信号传输至防漏电节点OFF<N>，使得防漏电节点OFF<N>的电压升高，进而使得第二十六晶体管M26的控制极与第一极之间的压差小于零，确保第二十六晶体管M26被完全或较为完全地截止。这样可以避免上拉节点Q<N>通过传输电路3203发生漏电，使得上拉节点Q<N>能够保持有一个较高的、较为稳定的电压。
根据本申请的一些示例，在栅极驱动电路还包括消隐输入电路的情况下，移位寄存器还可以包括第六复位电路3110。第六复位电路3110与第二时钟信号端CLKA、第一消隐节点H、下拉节点QB_A及第二电压信号端VGL1电连接，进而可以在一帧显示阶段的消隐时段中，在第二时钟信号端CLKA所传输的第二时钟信号及第一消隐节点H的电压的共同控制下，对下拉节点QB_A进行复位。
例如，在一帧显示阶段的消隐时段中，在第二时钟信号的电平为高电平、且第一消隐节点H的电压为高电平的情况下，第六复位电路3110可以在第二时钟信号及第一消隐节点H的电压的共同控制下导通，将第二电压信号端VGL1所传输的第二电压信号传输至下拉节点QB_A，对下拉节点QB_A进行下拉复位。具体地，第六复位电路3110可以包括：第三十二晶体管M32和第三十三晶体管M33。第三十二晶体管M32的控制极与第二时钟信号端CLKA电连接，第三十二晶体管M32的第一极与下拉节点QB_A电连接，第三十二晶体管M32的第二极与第三十三晶体管M33的第一极电连接。第三十三晶体管M33的控制极与第一消隐节点H电连接，第三十三晶体管M33的第二极与第二电压信号端VGL1电连接。
在第二时钟信号的电平为高电平、且第一消隐节点H的电压为高电平的情况下，第三十三晶体管M33可以在第一消隐节点H的电压的控制下导通，将第二电压信号传输至第三十三晶体管M33的第一极，第三十二晶体管M32可以在第二时钟信号的控制下导通，将第二电压信号从第三十三晶体管M33的第一极传输至下拉节点QB_A，对下拉节点QB_A进行下拉复位。
下面，以相邻的两级移位寄存器共用一个消隐输入电路3200为例，对栅极驱动电路的结构进行示意性说明：在以下说明中，N表示为正奇数。
如图6所示，相邻的两级移位寄存器中，后一级移位寄存器中的输出电路3103中可以未设置第四晶体管M4，且未与第三时钟信号端CLKD_1电连接。此时，第N级移位寄存器中的移位信号端CR<N>可以与第N+2级及第N+3级移位寄存器中的输入信号端Iput电连接，进而将第N级移位寄存器的移位信号端CR<N>所输出的移位信号作为第N+2级及第N+3级移位寄存器中的输入信号。第N级和第N+1级移位寄存器的显示复位信号端STD例如可以与第N+4级移位寄存器的移位信号端CR<N+4>电连接，进而将该第N+4级移位寄存器的移位信号端CR<N+4>所输出的移位信号作为第N级和第N+1移位寄存器的显示复位信号。
例如，第一级移位寄存器中的移位信号端CR<N>可以与第三级及第四级移位寄存器中的输入信号端Iput电连接。第五级移位寄存器中的移位信号端CR<N>可以与第一级及第二级移位寄存器中的显示复位信号端STD电连接。由此，可有利于简化栅极驱动电路的结构，减少栅极驱动电路在显示面板中的空间占比。当然，多级移位寄存器的级联关系可不限于前述的描述，本领域技术人员可根据情况进行改动。
在本申请的一些示例中，参考图6，相邻的两级移位寄存器中的前一级(也即第N级)移位寄存器1230a可称为第一扫描单元，后一级(也即第N+1级)移位寄存器1230b可称为第二扫描单元21b。第一扫描单元21a中的上拉节点Q<N>可称为第一上拉节点Q<N>，第二扫描单元21b中的上拉节点Q<N>称为第二上拉节点Q<N+1>。类似地，把第一扫描单元21a中的下拉节点QB_A称为第一下拉节点QB_A，第二扫描单元21b中的下拉节点QB_A称为第二下拉节点QB_B；第一扫描单元21a中的防漏电节点OFF<N>称为第一防漏电节点OFF<N>，把第二扫描单元21b中的防漏电节点OFF<N>称为第二防漏电节点OFF<N+1>；第二扫描单元21b中的第一时钟信号CLKE_1称为第五时钟信号CLKE_2，把第二扫描单元21b中的第四时钟信号CLKF_1称为第六时钟信号CLKF_2；第一扫描单元21a中的第一输出信号端Oput1<N>称为第一子输出信号端Oput1<N>，把第一扫描单元21a中的第二输出信号端Oput2<N>称为第二子输出信号端Oput2<N>，把第二扫描单元21b中的第一输出信号端Oput1<N>称为第三子输出信号端Oput1<N+1>，把第二扫描单元21b中的第二输出信号端Oput2<N>称为第四子输出信号端Oput2<N+1>。
参考图6，第二扫描单元21b中的控制电路3104可以和第七电压信号端VDD_B电连接，利用第七电压信号端VDD_B代替第六电压信号端VDD_A。其中，在一帧的显示阶段中，第六电压信号端VDD_A所传输的第六电压信号和第七电压信号端VDD_B所传输的第七电压信号互为反相信号。
根据本申请的一些示例，参考图6，第一扫描单元21a中的第一复位电路3105还可以与第二下拉节点QB_B电连接。该第一复位电路3105可在第二下拉节点QB_B的电压的控 制下，对第一上拉节点Q<N>进行复位：
具体地，在第二下拉节点QB_B的电压为高电平的情况下，第一复位电路3105可以在第二下拉节点QB_B的电压的作用下导通，将第二电压信号端VGL1所传输的第二电压信号传输至第一上拉节点Q<N>，对第一上拉节点Q<N>进行下拉复位。第一扫描单元21a中的第一复位电路3105还可以包括：第二十七晶体管M27和第二十八晶体管M28。
更具体地，第一扫描单元21a中，第二十七晶体管M27的控制极与第二下拉节点QB_B电连接，第二十七晶体管M27的第一极与第一上拉节点Q<N>电连接，第二十七晶体管M27的第二极与第二十八晶体管M28的第一极及第一防漏电节点OFF<N>电连接。第二十八晶体管M28的控制极与第二下拉节点QB_B电连接，第二十八晶体管M28的第二极与第二电压信号端VGL1电连接。
在第二下拉节点QB_B的电压为高电平的情况下，第二十七晶体管M27和第二十八晶体管M28可以在第二下拉节点QB_B的电压的作用下同时导通，第二十八晶体管M28可以将第二电压信号端VGL1所传输的第二电压信号传输至第一防漏电节点OFF<N>，第二十七晶体管M27可以将来自第一防漏电节点OFF<N>的第二电压信号传输至第一上拉节点Q<N>，对第一上拉节点Q<N>进行复位。
在本申请的一些示例中，参考图6，第二扫描单元21b中的第一复位电路3105还可以与第一下拉节点QB_A电连接。其中，该第一复位电路3105还被配置为，在第一下拉节点QB_A的电压的控制下，对第二上拉节点Q<N+1>进行复位。具体的，在第一下拉节点QB_A的电压为高电平的情况下，第一复位电路3105可以在第一下拉节点QB_A的电压的作用下导通，将第二电压信号端VGL1所传输的第二电压信号传输至第二上拉节点Q<N+1>，对第二上拉节点Q<N+1>进行下拉复位。更具体地，第二扫描单元21b中的第一复位电路3105还可以包括：第二十七晶体管M27和第二十八晶体管M28。
也即是说，此时第二扫描单元21b中，第二十七晶体管M27的控制极与第一下拉节点QB_A电连接，第二十七晶体管M27的第一极与第二上拉节点Q<N+1>电连接，第二十七晶体管M27的第二极与第二十八晶体管M28的第一极及第二防漏电节点OFF<N+1>电连接。第二十八晶体管M28的控制极与第一下拉节点QB_A电连接，第二十八晶体管M28的第二极与第二电压信号端VGL1电连接。
在第一下拉节点QB_A的电压为高电平的情况下，第二十七晶体管M27和第二十八晶体管M28可以在第一下拉节点QB_A的电压的作用下同时导通，第二十八晶体管M28可以将第二电压信号端VGL1所传输的第二电压信号传输至第二防漏电节点OFF<N+1>，第二十七晶体管M27可以将来自第二防漏电节点OFF<N+1>的第二电压信号传输至第二上拉节点Q<N+1>，对第二上拉节点Q<N+1>进行复位。
在本申请的另一些示例中，第一扫描单元21a中的第四复位电路3108还可以与第二下拉节点QB_B电连接。由此，该第四复位电路3108可在第二下拉节点QB_B的电压的控制下，对移位信号端CR<N>、第一子输出信号端Oput1<N>及第二子输出信号端Oput2<N>进行复位：在第二下拉节点QB_B的电压为高电平的情况下，第四复位电路3108可以在第二下拉节点QB_B的电压的作用下导通，将第二电压信号端VGL1所传输的第二电压信号传输至移位信号端CR<N>，对移位信号端CR<N>进行下拉复位，并将第三电压信号端VGL2所传输的第三电压信号传输至第一子输出信号端Oput1<N>和第二子输出信号端Oput2<N>，对第一子输出信号端Oput1<N>和第二子输出信号端Oput2<N>进行下拉复位。
具体的，第一扫描单元21a中的第四复位电路3108还可以包括：第二十九晶体管M29、第三十晶体管M30和第三十一晶体管M31。第二十九晶体管M29的控制极与第二下拉节点QB_B电连接，第二十九晶体管M29的第一极与移位信号端CR<N>电连接，第二十九晶体管M29的第二极与第二电压信号端VGL1电连接。由此，在第二下拉节点QB_B的电压为高电平的情况下，第二十九晶体管M29可以在第二下拉节点QB_B的电压的作用下导通，将第二电压信号端VGL1所传输的第二电压信号传输至移位信号端CR<N>，对移位信号端CR<N>进行下拉复位。
第三十晶体管M30的控制极与第二下拉节点QB_B电连接，第三十晶体管M30的第一极与第一子输出信号端Oput1<N>电连接，第三十晶体管M30的第二极与第三电压信号端VGL2电连接。在第二下拉节点QB_B的电压为高电平的情况下，第三十晶体管M30可以在第二下拉节点QB_B的电压的作用下导通，将第三电压信号端VGL2所传输的第三电压信号传输至第一子输出信号端Oput1<N>，对第一子输出信号端Oput1<N>进行下拉复位。
第三十一晶体管M31的控制极与第二下拉节点QB_B电连接，第三十一晶体管M31的第一极与第二子输出信号端Oput2<N>电连接，第三十一晶体管M31的第二极与第三电压信号端VGL2电连接。在第二下拉节点QB_B的电压为高电平的情况下，第三十一晶体管M31可以在第二下拉节点QB_B的电压的作用下导通，将第三电压信号端VGL2所传输的第三电压信号传输至第二子输出信号端Oput2<N>，对第二子输出信号端Oput2<N>进行下拉复位。
根据本申请的一些示例，第二扫描单元21b中的第四复位电路3108还可以与第一下拉节点QB_A电连接。即该第四复位电路3108可在第一下拉节点QB_A的电压的控制下，对第三子输出信号端Oput1<N+1>及第四子输出信号端Oput2<N+1>进行复位：
在第一下拉节点QB_A的电压为高电平的情况下，第四复位电路3108可以在第一下拉节点QB_A的电压的作用下导通，将第三电压信号端VGL2所传输的第三电压信号传输至第三子输出信号端Oput1<N+1>，对第三子输出信号端Oput1<N+1>进行下拉复位，将第三 电压信号端VGL2所传输的第三电压信号传输至第四子输出信号端Oput2<N+1>，对第四子输出信号端Oput2<N+1>进行下拉复位。具体地，第四复位电路3108还可以包括：第三十晶体管M30和第三十一晶体管M31。
此时，第三十晶体管M30的控制极与第一下拉节点QB_A电连接，第三十晶体管M30的第一极与第三子输出信号端Oput1<N+1>电连接，第三十晶体管M30的第二极与第三电压信号端VGL2电连接。在第一下拉节点QB_A的电压为高电平的情况下，第三十晶体管M30可以在第一下拉节点QB_A的电压的作用下导通，将第三电压信号端VGL2所传输的第三电压信号传输至第三子输出信号端Oput1<N+1>，对第三子输出信号端Oput1<N+1>进行下拉复位。
第三十一晶体管M31的控制极与第一下拉节点QB_A电连接，第三十一晶体管M31的第一极与第四子输出信号端Oput2<N+1>电连接，第三十一晶体管M31的第二极与第三电压信号端VGL2电连接。在第一下拉节点QB_A的电压为高电平的情况下，第三十一晶体管M31可以在第一下拉节点QB_A的电压的作用下导通，将第三电压信号端VGL2所传输的第三电压信号传输至第四子输出信号端Oput2<N+1>，对第四子输出信号端Oput2<N+1>进行下拉复位。
在另一些示例中，如图5和图8所示，移位寄存器1230可以包括：第一输入电路3101、防漏电电路3102、输出电路3103、控制电路3104、第一复位电路3105、第二复位电路3106、第三复位电路3107、第四复位电路3108及第五复位电路3109。具体地，此处图8中示出的第一输入电路3101、防漏电电路3102、输出电路3103、控制电路3104、第一复位电路3105、第二复位电路3106、第三复位电路3107、第四复位电路3108及第五复位电路3109结构，可以与图6中示出的相应的电路结构相同，对于相同的电路的结构及作用，此处不再赘述。
与前述的示例有所不同的是，如图8中示出的输出电路3103与上拉节点Q<N>、第一时钟信号端CLKE_1及第一输出信号端Oput1<N>电连接，在一帧显示阶段中的显示时段，在上拉节点Q<N>的电压的控制下，将在第一时钟信号端CLKE_1处接收的第一时钟信号传输至第一输出信号端Oput1<N>；在一帧显示阶段中的消隐时段，在上拉节点Q<N>的电压的控制下，将在第一时钟信号端CLKE_1处接收的第一时钟信号传输至第一输出信号端Oput1<N>。
或者，输出电路3103例如还可以与第三时钟信号端CLKD_1及移位信号端CR<N>电连接。由此可在一帧显示阶段中的显示时段，在上拉节点Q<N>的电压的控制下，将在第三时钟信号端CLKD_1处接收的第三时钟信号传输至移位信号端CR<N>。具体地，在一帧显示阶段中的显示时段，在上拉节点Q<N>的电压升高的情况下，输出电路3103可以在上拉 节点Q<N>的电压的控制下导通，将在第三时钟信号端CLKD_1处接收的第三时钟信号作为移位信号，从移位信号端CR<N>输出；将在第一时钟信号端CLKE_1处接收的第一时钟信号作为输出信号(也即像素电路接收的第一栅极信号)，从第一输出信号端Oput1<N>输出。在一帧显示阶段中的消隐时段，在上拉节点Q<N>的电压升高的情况下，输出电路3103可以在上拉节点Q<N>的电压的控制下导通，将在第一时钟信号端CLKE_1处接收的第一时钟信号作为输出信号(也即像素电路接收的第二栅极信号)，从第一输出信号端Oput1<N>输出。
在此示例中，移位寄存器1230的第一输出信号端Oput1<N>既可以与第一栅线电连接，又可以与第二栅线电连接，以便于在一帧显示阶段中的显示时段，移位寄存器的第一输出信号端Oput1<N>可以依次经第一栅线及第一栅极信号端G1向像素电路传输第一栅极信号，并在一帧显示阶段中的消隐时段，的第一输出信号端Oput1<N>可以依次经第二栅线及第二栅极信号端G2向像素电路传输第二栅极信号。在又一些示例中移位寄存器的第一输出信号端Oput1<N>可以通过一条栅线分别与第一栅极信号端G1及第二栅极信号端G2电连接，以便于在一帧显示阶段中的显示时段，的第一输出信号端Oput1<N>可以依次经该栅线及第一栅极信号端G1向像素电路12传输第一栅极信号，并在一帧显示阶段中的消隐时段，移位寄存器的第一输出信号端Oput1<N>可以依次经该栅线及第二栅极信号端G2向像素电路传输第二栅极信号。
具体地，输出电路3103可以包括第四晶体管M4、第五晶体管M5和第一电容器C1，第四晶体管M4的控制极与上拉节点Q<N>电连接，第四晶体管M4的第一极与第三时钟信号端CLKD_1电连接，第四晶体管M4的第二极与移位信号端CR<N>电连接。由此，在一帧显示阶段中的显示时段，在第一输入电路3101导通，使得上拉节点Q<N>的电压升高的情况下，第四晶体管M4可以在上拉节点Q<N>的高电压的控制下导通，将第三时钟信号传输至移位信号端CR<N>，并将该第三时钟信号作为移位信号从移位信号端CR<N>输出。第五晶体管M5的控制极与上拉节点Q<N>电连接，第五晶体管M5的第一极与第一时钟信号端CLKE_1电连接，第五晶体管M5的第二极与第一输出信号端Oput1<N>电连接。第一电容器C1的第一端与上拉节点Q<N>电连接，第一电容器C1的第二端与第一输出信号端Oput1<N>电连接。
在一帧显示阶段中的显示时段，在第一输入电路3101导通、使得上拉节点Q<N>的电压升高的同时，对第一电容器C1进行充电。在第一输入电路3101关断的情况下，第一电容器C1可以进行放电，使得上拉节点Q<N>保持为高电平，进而使得第五晶体管M5可以保持导通状态，将第一时钟信号传输至第一输出信号端Oput1<N>，并将该第一时钟信号作为输出信号(也即像素电路接收的第一栅极信号)从第一输出信号端Oput1<N>输出。
在一帧显示阶段中的消隐时段，在上拉节点Q<N>的电压升高的同时，会对第一电容器C1进行充电。在相应的阶段，第一电容器C1可以进行放电，使得上拉节点Q<N>保持为高电平，进而使得第五晶体管M6可以保持导通状态，将第一时钟信号传输至第一输出信号端Oput1<N>，并将该第一时钟信号作为输出信号(也即像素电路接收的第二栅极信号)从第一输出信号端Oput1<N>输出。
参考图8，第四复位电路3108与下拉节点QB_A、移位信号端CR<N>、第一输出信号端Oput1<N>、第二电压信号端VGL1及第三电压信号端VGL2电连接。其中，第四复位电路3108被配置为，在下拉节点QB_A的电压的控制下，对移位信号端CR<N>及第一输出信号端Oput1<N>进行复位。具体地，在下拉节点QB_A的电压为高电平的情况下，第四复位电路3108可以在下拉节点QB_A的电压的作用下导通，将第二电压信号端VGL1所传输的第二电压信号传输至移位信号端CR<N>，对移位信号端CR<N>进行下拉复位，将第三电压信号端VGL2所传输的第三电压信号传输至第一输出信号端Oput1<N>，对第一输出信号端Oput1<N>进行下拉复位。
例如，第四复位电路3108可以包括：第十七晶体管M17、和第十八晶体管M18。第十七晶体管M17的控制极与下拉节点QB_A电连接，第十七晶体管M17的第一极与移位信号端CR<N>电连接，第十七晶体管M17的第二极与第二电压信号端VGL1电连接。在下拉节点QB_A的电压为高电平的情况下，第十七晶体管M17可以在下拉节点QB_A的电压的作用下导通，将第二电压信号端VGL1所传输的第二电压信号传输至移位信号端CR<N>，对移位信号端CR<N>进行下拉复位。第十八晶体管M18的控制极与下拉节点QB_A电连接，第十八晶体管M18的第一极与第一输出信号端Oput1<N>电连接，第十八晶体管M18的第二极与第三电压信号端VGL2电连接。在下拉节点QB_A的电压为高电平的情况下，第十八晶体管M18可以在下拉节点QB_A的电压的作用下导通，将第三电压信号端VGL2所传输的第三电压信号传输至第一输出信号端Oput1<N>，对第一输出信号端Oput1<N>进行下拉复位。
类似地，如图8所示，栅极驱动电路还可以包括多个消隐输入电路3200。其中，一个消隐输入电路可以与相邻的至少两级移位寄存器电连接。消隐输入电路3200可在一帧显示阶段的消隐时段，控制相应的移位寄存器向相应行的像素电路输入消隐控制信号，使得该像素电路12获取感测信号。具体的，消隐输入电路3200例如可以包括：选择控制电路3201、第二输入电路3202及至少两个传输电路3203。类似地，图8中所使出的选择控制电路3201、第二输入电路3202及至少两个传输电路3203可具有与图6中所示出的相应结构相一致的结构和作用，在此不再赘述。
具体地，如图8中所示出的结构中，上述至少两个传输电路3203可以与至少两个移位 寄存器一一对应地电连接。一个传输电路3203与第二消隐节点N、第二时钟信号端CLKA及一级移位寄存器的上拉节点Q<N>电连接，在一帧显示阶段中的消隐时段，在第二时钟信号端CLKA所传输的第二时钟信号的控制下，将在第二消隐节点N处接收的第二时钟信号或第一电压信号传输至上拉节点Q<N>。
例如，在一帧显示阶段中的消隐时段，在第二时钟信号端CLKA所传输的第二时钟信号的电平为高电平的情况下，传输电路3202可以在该第二时钟信号的控制下导通，并从第二消隐节点N处接收第二时钟信号或第一电压信号，将所接收的第二时钟信号或第一电压信号传输至上拉节点Q<N>，使得上拉节点Q<N>的电压升高，进而可以使得输出电路3103导通，使得输出电路3103的输出信号端输Oput<N>出输出信号。传输电路3203可以包括：第二十五晶体管M25，第二十五晶体管M25的控制极与第二时钟信号端CLKA电连接，第二十五晶体管M25的第一极与第二消隐节点N电连接，第二十五晶体管M25的第二极与上拉节点Q<N>电连接。在一帧显示阶段中的消隐时段，在第二时钟信号端CLKA所传输的第二时钟信号的电平为高电平的情况下，第二十五晶体管M25可以在第二时钟信号的作用下导通，第二十五晶体管M25可以将来自第二消隐节点N的第二时钟信号或第一电压信号传输至上拉节点Q<N>，对上拉节点Q<N>进行充电。输出电路3103中的第五晶体管M5可以在上拉节点Q<N>的电压的控制下导通，接收第一时钟信号，并将该第一时钟信号作为输出信号从第一输出信号端Oput1<N>输出。
类似地，在栅极驱动电路还包括消隐输入电路的情况下，移位寄存器还可以包括第六复位电路3110。第六复位电路3110与第二时钟信号端CLKA、第一消隐节点H、下拉节点QB_A及第二电压信号端VGL1电连接，在一帧显示阶段的消隐时段中，在第二时钟信号端CLKA所传输的第二时钟信号及第一消隐节点H的电压的共同控制下，对下拉节点QB_A进行复位。具体而言，在一帧显示阶段的消隐时段中，在第二时钟信号的电平为高电平、且第一消隐节点H的电压为高电平的情况下，第六复位电路3110可以在第二时钟信号及第一消隐节点H的电压的共同控制下导通，将第二电压信号端VGL1所传输的第二电压信号传输至下拉节点QB_A，对下拉节点QB_A进行下拉复位。第六复位电路3110可以包括：第三十二晶体管M32和第三十三晶体管M33。
具体的，第三十二晶体管M32的控制极与第一消隐节点H电连接，第三十二晶体管M32的第一极与下拉节点QB_A电连接，第三十二晶体管M32的第二极与第三十三晶体管M33的第一极电连接。第三十三晶体管M33的控制极与第二时钟信号端CLKA电连接，第三十三晶体管M33的第二极与第二电压信号端VGL1电连接。在第二时钟信号的电平为高电平、且第一消隐节点H的电压为高电平的情况下，第三十三晶体管M33可以在第二时钟信号的控制下导通，将第二电压信号传输至第三十三晶体管M33的第一极，第三十二晶体 管M32可以在第一消隐节点H的电压的控制下导通，将第二电压信号从第三十三晶体管M33的第一极传输至下拉节点QB_A，对下拉节点QB_A进行下拉复位。
下面以相邻的两级移位寄存器共用一个消隐输入电路为例，对栅极驱动电路的结构进行示意性说明。在下述说明中，N表示为正奇数。
如图8所示，相邻的两级移位寄存器中，后一级移位寄存器中的输出电路3103中可以未设置第四晶体管M4，且未与第三时钟信号端电连接CLKD_1。此时多级移位寄存器的级联关系与上述一些示例中多级移位寄存器的级联关系可以相同，此处不再赘述。
例如，可以把相邻的两级移位寄存器中，前一级(也即第N级)移位寄存器称为第一扫描单元21a，把后一级(也即第N+1级)移位寄存器称为第二扫描单元21b。类似地，可以把第一扫描单元21a中的上拉节点Q<N>称为第一上拉节点Q<N>，把第二扫描单元21b中的上拉节点Q<N>称为第二上拉节点Q<N+1>。可以把第一扫描单元21a中的下拉节点QB_A称为第一下拉节点QB_A，把第二扫描单元21b中的下拉节点QB_A称为第二下拉节点QB_B。可以把第一扫描单元21a中的防漏电节点OFF<N>称为第一防漏电节点OFF<N>，把第二扫描单元21b中的防漏电节点OFF<N>称为第二防漏电节点OFF<N+1>。可以把第二扫描单元21b中的第一时钟信号CLKE_1称为第五时钟信号CLKE_2。可以把第一扫描单元21a中的第一输出信号端Oput1<N>称为第一子输出信号端Oput1<N>，把第二扫描单元21b中的第一输出信号端Oput1<N>称为第二子输出信号端Oput1<N+1>。
参考图8，第二扫描单元21b中的控制电路3104可以和第七电压信号端VDD_B电连接，利用第七电压信号端VDD_B代替第六电压信号端VDD_A。在一帧的显示阶段中，第六电压信号端VDD_A所传输的第六电压信号和第七电压信号端VDD_B所传输的第七电压信号互为反相信号。本示例中第一扫描单元21a中的第一复位电路3105的结构及作用与上述一些示例中第一扫描单元21a中的第一复位电路3105的结构及作用可以相同，本示例中第二扫描单元21b中的第一复位电路3105的结构及作用与上述一些示例中第二扫描单元21b中的第一复位电路3105的结构及作用可以相同。对于相同的电路的结构及作用，此处不再赘述。
具体的，第一扫描单元21a中的第四复位电路3108还可以与第二下拉节点QB_B电连接。其中，该第四复位电路3108还被配置为，在第二下拉节点QB_B的电压的控制下，对移位信号端CR<N>及第一子输出信号端Oput1<N>进行复位。在第二下拉节点QB_B的电压为高电平的情况下，第四复位电路3108可以在第二下拉节点QB_B的电压的作用下导通，将第二电压信号端VGL1所传输的第二电压信号传输至移位信号端CR<N>，对移位信号端CR<N>进行下拉复位，并将第三电压信号端VGL2所传输的第三电压信号传输至第一子输出信号端Oput1<N>，对第一子输出信号端Oput1<N>进行下拉复位。第一扫描单元21a中 的第四复位电路3108还可以包括：第二十九晶体管M29和第三十晶体管M30。第二十九晶体管M29的控制极与第二下拉节点QB_B电连接，第二十九晶体管M29的第一极与移位信号端CR<N>电连接，第二十九晶体管M29的第二极与第二电压信号端VGL1电连接。在第二下拉节点QB_B的电压为高电平的情况下，第二十九晶体管M29可以在第二下拉节点QB_B的电压的作用下导通，将第二电压信号端VGL1所传输的第二电压信号传输至移位信号端CR<N>，对移位信号端CR<N>进行下拉复位。第三十晶体管M30的控制极与第二下拉节点QB_B电连接，第三十晶体管M30的第一极与第一子输出信号端Oput1<N>电连接，第三十晶体管M30的第二极与第三电压信号端VGL2电连接。在第二下拉节点QB_B的电压为高电平的情况下，第三十晶体管M30可以在第二下拉节点QB_B的电压的作用下导通，将第三电压信号端VGL2所传输的第三电压信号传输至第一子输出信号端Oput1<N>，对第一子输出信号端Oput1<N>进行下拉复位。
例如，第二扫描单元21b中的第四复位电路3108还可以与第一下拉节点QB_A电连接，在第一下拉节点QB_A的电压的控制下，对第二子输出信号端Oput1<N+1>进行复位。
具体而言，在第一下拉节点QB_A的电压为高电平的情况下，第四复位电路3108可以在第一下拉节点QB_A的电压的作用下导通，将第三电压信号端VGL2所传输的第三电压信号传输至第二子输出信号端Oput1<N+1>，对第二子输出信号端Oput1<N+1>进行下拉复位。第二扫描单元21b中的第四复位电路3108还可以包括：第三十晶体管M30。第三十晶体管M30的控制极与第一下拉节点QB_A电连接，第三十晶体管M30的第一极与第二子输出信号端Oput2<N+1>电连接，第三十晶体管M30的第二极与第三电压信号端VGL2电连接。在第一下拉节点QB_A的电压为高电平的情况下，第三十晶体管M30可以在第一下拉节点QB_A的电压的作用下导通，将第三电压信号端VGL2所传输的第三电压信号传输至第二子输出信号端Oput1<N+1>，对第二子输出信号端Oput1<N+1>进行下拉复位。
下面，以第一种示例中(如图6中示出的)所示的移位寄存器的结构为例，对栅极驱动电路的结构进行进一步的说明：
参考图7，栅极驱动电路还可以包括沿第二方向(垂直于图1以及图3中所示出的遮光孔延伸方向)延伸的多条控制信号线33。其中，一级移位寄存器与该多条控制信号线33中的至少一部分电连接，在与其连接的至少一部分控制信号线33的控制下，向相应一行的多个像素电路提供输出信号。
具体地，参考图7，其中所示中所示的RS1、RS2、RS3……RS6分别表示第一级移位寄存器、第二级移位寄存器、第三级移位寄存器……第六级移位寄存器，并分别与显示面板中第一行子像素的像素电路、第二行子像素的像素电路、第三行子像素的像素电路……第六行子像素的像素电路电连接。
其中，RS1、RS3、RS5可以分别通过第一子输出信号端Oput1<N>与相应行像素电路中的第一栅极信号端G1电连接，通过第二子输出信号端Oput2<N>与相应行像素电路中的第二栅极信号端G2电连接。RS2、RS4、RS6可以分别通过第三子输出信号端Oput1<N+1>与相应行像素电路中的第一栅极信号端G1电连接，通过第四子输出信号端Oput2<N+1>与相应行像素电路中的第二栅极信号端G2电连接。换句话说，RS1、RS3、RS5可以分别称为第一扫描单元21a，RS2、RS4、RS6可以分别称为第二扫描单元21b。
在一些示例中，上述多条控制信号线33可以包括第一时钟信号线CLK_1、第二时钟信号线CLK_2和第三时钟信号线CLK_3。第一级移位寄存器中的第三时钟信号端CLKD_1与第一时钟信号线CLK_1电连接，以接收第三时钟信号。第三级移位寄存器中的第三时钟信号端CLKD_1与第二时钟信号线CLK_2电连接，以接收第三时钟信号。第五级移位寄存器中的第三时钟信号端CLKD_1与第三时钟信号线CLK_3电连接，以接收第三时钟信号。
上述多条控制信号线33还可以包括第四时钟信号线CLK_4、第五时钟信号线CLK_5、第六时钟信号线CLK_6、第七时钟信号线CLK_7、第八时钟信号线CLK_8、第九时钟信号线CLK_9、第十时钟信号线CLK_10、第十一时钟信号线CLK_11、第十二时钟信号线CLK_12、第十三时钟信号线CLK_13、第十四时钟信号线CLK_14和第十五时钟信号线CLK_15。
具体的，第一级移位寄存器中的第一时钟信号端CLKE_1与第四时钟信号线CLK_4电连接，以接收第一时钟信号，第四时钟信号端CLKF_1与第五时钟信号线CLK_5电连接，以接收第四时钟信号。第二级移位寄存器中的第五时钟信号端CLKE_2与第六时钟信号线CLK_6电连接，以接收第五时钟信号，第六时钟信号端CLKE_2与第七时钟信号线CLK_7电连接，以接收第六时钟信号。第三级移位寄存器中的第一时钟信号端CLKE_1与第八时钟信号线CLK_8电连接，以接收第一时钟信号，第四时钟信号端CLKF_1与第九时钟信号线CLK_9电连接，以接收第四时钟信号。第四级移位寄存器中的第五时钟信号端CLKE_2与第十时钟信号线CLK_10电连接，以接收第五时钟信号，第六时钟信号端CLKE_2与第十一时钟信号线CLK_11电连接，以接收第六时钟信号。第五级移位寄存器中的第一时钟信号端CLKE_1与第十二时钟信号线CLK_12电连接，以接收第一时钟信号，第四时钟信号端CLKF_1与第十三时钟信号线CLK_13电连接，以接收第四时钟信号。第六级移位寄存器中的第五时钟信号端CLKE_2与第十四时钟信号线CLK_14电连接，以接收第五时钟信号，第六时钟信号端CLKE_2与第十五时钟信号线CLK_15电连接，以接收第六时钟信号。
在另一些示例中，上述多条控制信号线33还可以包括第十六时钟信号线CLK_16。每一级移位寄存器中的全局复位信号端TRST均与第十六时钟信号线CLK_16电连接，以接收 全局复位信号。
在另一些示例中，上述多条控制信号线33还可以包括第十七时钟信号线CLK_17和第十八时钟信号线CLK_18。每个消隐输入电路的选择控制信号端OE均与第十七时钟信号线CLK_17电连接，以接收选择控制信号。每个消隐输入单元的第二时钟信号端CLKA均与第十八时钟信号线CLK_18电连接，以接收第二时钟信号。
在一些示例中，上述多条控制信号线33还可以包括第十九时钟信号线CLK_19和第二十时钟信号线CLK_20。第一级移位寄存器中的第六电压信号端VDD_A、第三级移位寄存器21中的第六电压信号端VDD_A和第五级移位寄存器中的第六电压信号端VDD_A均与第十九时钟信号线CLK_19电连接，以接收第六电压信号。第二级移位寄存器中的第七电压信号端VDD_B、第四级移位寄存器中的第七电压信号端VDD_B和第六级移位寄存器中的第七电压信号端VDD_B均与第二十时钟信号线CLK_20电连接，以接收第七电压信号。
在一些示例中，上述多条控制信号线33还可以包括第二十一时钟信号线CLK_21。第一级移位寄存器中的输入信号端Iput和第二级移位寄存器中的输入信号端Iput可以均与第二十一时钟信号线CLK_21电连接，以接收起始信号作为输入信号。
上述多条控制信号线33还可以包括第二十二时钟信号线CLK_22。栅极驱动电路中的最后四级移位寄存器的显示复位信号端STD可以均与第二十二时钟信号线CLK_22电连接，以接收显示复位信号。
示例性的，栅极驱动电路中，除了第一级移位寄存器和第二级移位寄存器以外的其他级移位寄存器中，第N级移位寄存器中的移位信号端CR<N>可以与第N+2级及第N+3级移位寄存器中的输入信号端Iput电连接，进而将第N级移位寄存器的移位信号端CR<N>所输出的移位信号作为第N+2级及第N+3级移位寄存器中的输入信号。除了最后四级移位寄存器以外的其他级移位寄存器中，第N级和第N+1级移位寄存器的显示复位信号端STD例如可以与第N+4级移位寄存器21的移位信号端CR<N+4>电连接，进而将该第N+4级移位寄存器的移位信号端CR<N+4>所输出的移位信号作为第N级和第N+1移位寄存器的显示复位信号。
此处需要特别说明的是，在本申请中，术语第一上拉节点、第二上拉节点、第一下拉节点和第二下拉节点等节点并非表示实际存在的部件，而是表示电路图中相关电连接的汇合点，也就是说，这些节点是由电路图中相关电连接的汇合点等效而成的节点。术语“上拉”表示对一个节点或一个晶体管的一个电极进行充电，以使得该节点或该电极的电平的绝对值升高，从而实现相应晶体管的操作(例如导通)。术语“下拉”表示对一个节点或一个晶体管的一个电极进行放电，以使得该节点或该电极的电平的绝对值降低，从而实现相应晶体管的操作(例如截止)。
在本申请的另一方面，本申请提出了一种制备前面所说的显示面板方法。参考图9，该该方法包括：
S100：在基板上形成背板电路层，并在所述显示面板中的所述栅极驱动电路区内形成多个薄膜晶体管
根据本申请的示例，在该步骤中可进行在基板上形成背板电路的操作。关于背板电路的结构，像素电路以及栅极驱动电路的结构，前面已经进行了详细的描述，在此不再赘述。
总的来说，该步骤中可以包括多个沉积材料并进行构图工艺的操作，以形成构成晶体管、电容和信号线的结构。
S200：在所述背板电路层远离所述基板的一侧形成多个发光元件，并令所述发光元件位于所述像素区内
根据本申请的示例，在该步骤中设置多个发光元件。该多个发光原件可以为OLED。
该方法还包括形成遮光孔和金属层的操作，并令所述金属层填充至所述遮光孔内，所述遮光孔以及所述金属层在所述基板上的正投影的位置被配置为可遮挡所述发光元件的光照射至所述薄膜晶体管的有源层。由此，可简便地获得前述的显示面板。
在本申请的一些示例中，以遮光孔形成在像素界定结构上为例，上述形成所述遮光孔和金属层可以包括：形成所述发光元件之前，预先在多个所述发光元件之间处形成像素界定结构，并在所述像素界定结构上形成所述遮光孔；形成所述发光元件时，利用阴极金属形成所述金属层。由此，可简便地形成遮光孔和金属层。
在本申请的又一方面，本申请提出了一种显示装置。该显示装置包括了前面所述的显示面板。由此，该显示装置具有边框较窄、使用寿命较长等优点的至少之一。
在本说明书的描述中，参考术语“一个实施例”、“另一个实施例”等的描述意指结合该实施例描述的具体特征、结构、材料或者特点包含于本申请的至少一个实施例中。在本说明书中，对上述术语的示意性表述不必须针对的是相同的实施例或示例。而且，描述的具体特征、结构、材料或者特点可以在任一个或多个实施例或示例中以合适的方式结合。此外，在不相互矛盾的情况下，本领域的技术人员可以将本说明书中描述的不同实施例或示例以及不同实施例或示例的特征进行结合和组合。
尽管上面已经示出和描述了本申请的实施例，可以理解的是，上述实施例是示例性的，不能理解为对本申请的限制，本领域的普通技术人员在本申请的范围内可以对上述实施例进行变化、修改、替换和变型。

Claims (13)

  1. 一种显示面板，所述显示面板的显示区包括多个像素区和多个栅极驱动电路区，所述栅极驱动电路区位于相邻的两个所述像素区之间，所述显示面板包括：
    基板；
    背板电路层，所述背板电路层位于所述基板上，且所述背板电路层在所述栅极驱动电路区内，具有多个薄膜晶体管；
    多个发光元件，所述多个发光元件位于所述背板电路层远离所述基板的一侧，并位于所述像素区所在区域内，
    所述显示面板具有遮光孔孔，所述遮光孔内填充有金属层，所述遮光孔以及所述金属层在所述基板上的正投影的位置被配置为可遮挡照射至所述薄膜晶体管的有源层的光。
  2. 根据权利要求1所述的显示面板，所述遮光孔以及所述金属层位于所述背板电路层远离所述基板的一侧。
  3. 根据权利要求2所述的显示面板，所述像素区和所述栅极驱动电路区相邻设置，所述发光元件位于所述像素区内，且相邻的所述发光元件之间具有像素界定结构，所述遮光孔形成在所述像素界定结构上。
  4. 根据权利要求3所述的显示面板，所述金属层包括阴极金属。
  5. 根据权利要求1所述的显示面板，包括多个所述遮光孔，每个所述像素区以及所述栅极驱动电路区内的薄膜晶体管之间，均具有所述遮光孔。
  6. 根据权利要求1所述的显示面板，所述栅极驱动电路区内的薄膜晶体管包括：
    有源层；
    栅极以及栅绝缘层，所述栅极以及栅绝缘层位于所述有源层远离所述基板的一侧；
    源漏电极，所述源漏电极位于所述有源层远离所述基板的一侧，所述源漏电极以及所述栅极之间间隔有层间介质层，且所述源漏电极通过贯穿所述层间介质层的通孔与所述有源层相连，
    所述遮光孔在所述基板上的正投影，和所述层间介质层的通孔在所述基板上的正投影之间无重叠区域。
  7. 根据权利要求1-6任一项所述的显示面板，所述像素区进一步包括像素发光子区和像素电路子区，所述发光元件位于所述像素发光区内，所述像素发光子区和像素电路子区沿第一方向排布，且所述遮光孔沿所述第一方向延伸。
  8. 根据权利要求7所述的显示面板，相邻的两个所述像素区之间具有两个所述遮光孔，所述栅极驱动电路包括晶体管组，所述遮光孔沿所述第一方向的长度与所述晶体管组的长 度相一致，所述晶体管组内的多个薄膜晶体管沿所述第一方向排布于两个所述遮光孔之间。
  9. 根据权利要求1-6任一项所述的显示面板，所述像素区在所述基板上阵列排布，每个所述像素区至少包括两个子像素，每行所述像素区与至少两个所述栅极驱动电路区对应，每个所述栅极驱动电路区位于相邻两个所述像素区之间，所述栅极驱动电路包括级联的多个移位寄存器，每个所述移位寄存器与一行所述子像素电连接；每个所述移位寄存器包括多个晶体管组，每个所述晶体管组包括至少一个所述薄膜晶体管。
  10. 根据权利要求1-6任一项所述的显示面板，所述遮光孔的深度为1-3微米，所述遮光孔的宽度为3-10微米。
  11. 一种制备权利要求1-10任一项所述的显示面板方法，包括：
    在基板上形成背板电路层，并在所述显示面板中的所述栅极驱动电路区内形成多个薄膜晶体管；
    在所述背板电路层远离所述基板的一侧形成多个发光元件，并令所述发光元件位于所述像素区内；
    且所述方法包括形成遮光孔和金属层的操作，并令所述金属层填充至所述遮光孔内，所述遮光孔以及所述金属层在所述基板上的正投影的位置被配置为可遮挡所述发光元件的光照射至所述薄膜晶体管的有源层。
  12. 根据权利要求11的方法，形成所述遮光孔和金属层包括：
    形成所述发光元件之前，预先在多个所述发光元件之间处形成像素界定结构，并在所述像素界定结构上形成所述遮光孔；
    形成所述发光元件时，利用阴极金属形成所述金属层。
  13. 一种显示装置，其特征在于，包括权利要求1-10任一项所述的显示面板。
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CN109742113A (zh) * 2019-01-08 2019-05-10 京东方科技集团股份有限公司 一种阵列基板、其制备方法及相关装置

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