WO2022193774A1 - Armature d'encapsulation pour puce, procédé de traitement, et produit associé - Google Patents

Armature d'encapsulation pour puce, procédé de traitement, et produit associé Download PDF

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Publication number
WO2022193774A1
WO2022193774A1 PCT/CN2021/141281 CN2021141281W WO2022193774A1 WO 2022193774 A1 WO2022193774 A1 WO 2022193774A1 CN 2021141281 W CN2021141281 W CN 2021141281W WO 2022193774 A1 WO2022193774 A1 WO 2022193774A1
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Prior art keywords
chip
soc
receiving area
package
memory
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PCT/CN2021/141281
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English (en)
Chinese (zh)
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郑帅
陈帅
庄云良
高崧
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上海寒武纪信息科技有限公司
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Publication of WO2022193774A1 publication Critical patent/WO2022193774A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00

Definitions

  • the present disclosure relates generally to the field of circuits, and more particularly, to the field of packaging and fabrication of chips.
  • AI Artificial Intelligence
  • Training refers to sending massive amounts of data to the server and repeatedly adjusting the AI algorithm to make it master specific functions. This process requires extremely high computational performance, precision, and versatility. Therefore, the most advanced process nodes are usually used in cloud training, and the system-on-chip (referred to as "SOC”) chip and the The interconnection between multiple High Bandwidth Memory (“HBM”) chips.
  • SOC system-on-chip
  • HBM High Bandwidth Memory
  • Inference refers to the direct application of the trained model.
  • the parameters of the model have been solidified, and massive data calculations are not required.
  • the requirements for computing performance, accuracy, and versatility are not so strict. Therefore, it is not necessary to use very expensive HBM chips in the cloud inference process, but the packaged SOC chips are usually completed on a printed circuit board (Printed Circuit Board, referred to as "PCB") to synchronize with multiple double rates.
  • PCB printed Circuit Board
  • DDR Random access memory
  • the cloud training SOC chip and the inference SOC chip need to be connected to different types of memory chips, so cloud training and inference cannot share the same SOC chip.
  • the cost of SOC chip casting is getting higher and higher, which means that the economic benefits brought by sharing the same SOC chip are becoming more and more significant. Therefore, how to realize the interconnection between the same SOC chip and different types of memory chips, so as to reduce the cost of SOC chip casting and improve economic benefits, has become an urgent technical problem to be solved.
  • the present disclosure provides a packaging frame for chips, a processing method and related products, so as to realize the interconnection of the same SoC with different types of memory chips.
  • the present disclosure provides a packaging frame for a chip, comprising: a packaging substrate; a first SoC accommodating area disposed on the packaging substrate for accommodating the first SoC; An input/output chip is disposed on the packaging substrate; wherein, the input/output chip and the chip accommodating area are connected through the packaging substrate.
  • the present disclosure provides a packaged device, comprising: the package frame as described above; a first system-on-chip, which is disposed in the chip receiving area to communicate with the input through the package substrate Output chip connection.
  • the present disclosure provides an integrated circuit device, comprising: a packaged device as described above; a printed circuit board; a second memory chip disposed on the printed circuit board and provided by The printed circuit board is connected with the packaged device, thereby realizing the connection between the second memory chip and the first SoC.
  • the present disclosure provides an electronic device and a board, comprising: the above-mentioned packaging frame or the above-mentioned packaging device, or the above-mentioned integrated circuit device.
  • the present disclosure provides a method of processing a package frame for a chip, comprising: providing a package substrate having a first receiving area and a second receiving area thereon, and the first receiving area and the second accommodating area is connected via the package substrate, wherein the first accommodating area is used for accommodating the first SoC; providing input and output chips; setting the input and output chips to the second accommodating a placement area, so that the input and output chips are connected to the first placement area through the package substrate.
  • the present disclosure provides a method of processing a packaged device, comprising: providing a package substrate having a first receiving area and a second receiving area thereon, and the first receiving area and the second receiving area a placement area is connected via the package substrate; a first system-on-chip is provided; an input-output chip is provided; the first system-on-chip is provided to the first placement area, and the input-output chip is provided to the The second accommodating area is used to connect the I/O chip with the first SoC through the package substrate.
  • the present disclosure provides a method for processing an integrated circuit device, comprising: the method for processing a packaged device as described above; providing a printed circuit board having a fourth receiving area and a fifth receiving area thereon, And the fourth accommodating area and the fifth accommodating area are connected via a printed circuit board; a second memory chip is provided; the packaged device is set to the fourth accommodating area, and the second memory chip is set to the The fifth accommodating area is used to connect the second memory chip with the package device through a printed circuit board.
  • a first SoC for connecting a first memory chip eg, high-bandwidth memory
  • a second memory chip eg, double-rate synchronous dynamic random access memory
  • the connection realizes the interconnection between the same SoC and different types of memory chips, thereby reducing the cost of casting the SoC and improving the economic benefits of the product.
  • the first SoC can be connected to more second memory chips, thereby expanding the storage capacity and making full use of the transmission bandwidth.
  • FIG. 1-1 and FIG. 1-2 are schematic diagrams illustrating multiple structures of an integrated circuit device in an artificial intelligence training scenario according to an embodiment of the present disclosure
  • FIG. 2 is a schematic structural diagram illustrating an integrated circuit device in an artificial intelligence inference scenario according to an embodiment of the present disclosure
  • 3-1 and 3-2 are schematic diagrams illustrating a plurality of structures of a package frame for a chip according to an embodiment of the present disclosure
  • FIG. 4 is a schematic structural diagram illustrating a packaged device according to an embodiment of the present disclosure.
  • 5-1 and 5-2 are schematic diagrams illustrating a plurality of structures of an integrated circuit device according to an embodiment of the present disclosure
  • FIG. 6 is a flowchart illustrating a method of processing a packaging frame for a chip according to an embodiment of the present disclosure
  • FIG. 7 is a flowchart illustrating a method of processing a packaged device according to an embodiment of the present disclosure.
  • FIG. 8 is a flowchart illustrating a method of manufacturing an integrated circuit device according to an embodiment of the present disclosure.
  • PCB Printed Circuit Board
  • High Bandwidth Memory with higher speed and higher bandwidth, is suitable for application scenarios with high memory bandwidth requirements, such as cloud AI processing.
  • FIG. 1-1 shows a schematic structural diagram of an integrated circuit device 100 in an artificial intelligence training scenario according to an embodiment of the present disclosure.
  • the integrated circuit device 100 may include a printed circuit board, a package substrate may be provided on the printed circuit board, and a first system-on-chip may be further provided on the package substrate Chip 101 and the first memory chip.
  • the first SoC 101 is a type of SoC that can be used to connect with the first memory chip.
  • the first system-on-chip 101 may be communicatively connected to the first memory chip through package substrate traces.
  • the first memory chip may be used to provide high-speed storage for the system-on-chip, eg, may be a high-bandwidth memory chip.
  • the first memory chip can be used to provide high-speed storage for the first system-on-chip 101 to support the storage and operation of massive data in the artificial intelligence training process.
  • PHY represents the interconnect interface on the chip for data transfer between the chip and other circuit structures.
  • the PHY may be the interface of the first system-on-chip 101 to the first memory chip.
  • the data bus represents the wiring connected between the chips and is used to transmit data information. As shown in FIG. 1-1 , the data bus may connect the first SoC 101 with the first memory chip through a PHY interface.
  • the package substrate is the carrier of the chip package, which can be used to provide functions such as electrical connection, protection, support, and assembly for the chip.
  • the package substrate may be used to implement the connection of the first SoC 101 to the first memory chip, and to implement the connection of the first SoC 101 and the first memory chip to the PCB underlying the package substrate.
  • the first SoC 101 can be communicatively connected to the first memory chip through the routing of the packaging substrate, that is, the data bus laid in the packaging substrate.
  • first memory chips are shown in FIG. 1-1 , this is only an exemplary representation, and those skilled in the art can select any desired number of first memory chips according to actual needs.
  • FIG. 1-2 illustrate yet another schematic structural diagram of an integrated circuit device 100 in an artificial intelligence training scenario according to an embodiment of the present disclosure.
  • the package substrate may include a package substrate and a package interposer.
  • the package substrate (Package Substrate Plate, referred to as "PKG") is used to carry and protect the chip and realize the connection between the chip and the underlying circuit structure.
  • the package substrate can be used to carry the first SoC 101 and the first memory chip, and realize the connection between the first SoC 101 and the first memory chip and the PCB under the package substrate.
  • the packaging interposer can be disposed on the above-mentioned packaging substrate or in the packaging substrate, and is used to realize interconnection between a plurality of chips, and can serve as a bridge connecting the chips and the packaging substrate.
  • the packaging interposer may be, for example, a silicon interposer (Si interposer) or a redistribution interposer (Redistribution Layer Interposer, referred to as "RDL Interposer").
  • RDL Interposer redistribution Layer Interposer
  • the first SoC 101 may be communicatively connected to the first memory chip through the package interposer traces (ie, data buses disposed in the package interposer).
  • FIG. 1-2 exemplarily shows that the package interposer is disposed on the surface of the package substrate and covers the area where the first SoC 101 and the first memory chip are mapped on the surface of the package substrate , but in other embodiments, the package interposer may only cover the data bus area connecting the first SoC 101 and the first memory chip. In addition, the package interposer can also be embedded or embedded within the package substrate.
  • a recess may be provided on the package substrate, the recess having a shape and size adapted to the package interposer, the package interposer may then be provided in the recess, and the first SoC 101 and the third A memory chip is disposed on the package interposer, or a local area of the first SoC 101 and the first memory chip, such as an area where the interconnect interface of the chip is located, may be disposed on the package interposer, so as to realize the package interposer
  • the communicable connection with the first SoC 101 and the first memory chip, and further by routing or laying lines in the package interposer, the communicable connection between the first SoC 101 and the first memory chip can be achieved connect.
  • a memory chip that provides high-speed storage ie, the first memory chip
  • COWOS Chip-on-Wafer- on-Substrate packaging technology
  • FIG. 2 is a schematic structural diagram illustrating an integrated circuit device 200 in an artificial intelligence inference scenario according to an embodiment of the present disclosure.
  • the integrated circuit device 200 may include a printed circuit board, a package substrate and a second memory chip may be provided on the printed circuit board, and a first memory chip may be provided on the package substrate Two SoCs 201 on a chip.
  • the second SoC 201 may be a SoC for connecting with the second memory chip.
  • the second SoC 201 can be communicatively connected to the second memory chip through PCB traces without requiring a communicative connection through a costly package interposer.
  • the bandwidth of the second memory chip can generally be lower than that of the first memory chip.
  • Low Power Double Data Rate SDRAM referred to as "LPDDR”
  • GDDR double data rate synchronous dynamic random access memory for graphics
  • the pin size and spacing of the second memory chip are larger than those of the first memory chip, so the connection between the second SoC 201 and the second memory chip can be performed through a PCB routing process.
  • I&F stands for the interface between packaged system-on-chip and memory chip interconnects. In FIG. 2 , I&F refers to an interface connected to the second memory chip after the first SoC 201 is packaged.
  • a very expensive memory chip for high-speed storage ie, the first memory chip shown in FIGS. 1-1 and 1-2 .
  • a second memory chip may be provided, and the second memory chip and the packaged second SoC 201 may be connected through PCB traces.
  • SoCs need to be connected to different types of memory chips, so the same SoC cannot be shared.
  • the cost of SoC casting is getting higher and higher, which means that the economic benefits brought by sharing the same SoC are becoming more and more significant.
  • FIG. 3-1 is a schematic structural diagram illustrating a package frame 300 for a chip according to an embodiment of the present disclosure.
  • a package frame 300 for chips is provided.
  • the package frame 300 includes a package substrate; a first SoC accommodating area 301 disposed on the package substrate for accommodating the first SoC 101; and an I/O chip disposed on the package substrate wherein, the input and output chips and the first on-chip system chip accommodating area are connected through the packaging substrate.
  • I/O chip An input and output chip (INPUT/OUTPUT chip, referred to as "I/O chip") is a data transfer chip.
  • the I/O chip may be used to implement data communication or transmission between the first SoC 101 and the second memory chip.
  • FIG. 5-1 and FIG. 5-2 please refer to the description below in conjunction with FIG. 5-1 and FIG. 5-2 .
  • the I/O chip is disposed on the package substrate. More specifically, the I/O chip can be connected to the package substrate by pins such as soldering.
  • the first system-on-chip 101 can be used to connect with the first memory chip. Therefore, by integrating the packaging frame 100 of the input and output chips, it is possible to realize the connection between the same SoC (ie the first SoC 101 ) and different types of memory chips (ie the first memory chip and the second memory chip). It avoids the increase in the cost of chip casting caused by the need to design different SoCs in order to adapt to different application scenarios (such as cloud inference and training).
  • the multiple I/O chips are disposed around the first SoC accommodating area 301 to facilitate communication with multiple interfaces of the SoC.
  • the number of I/O chips can be four, which can be symmetrically arranged on both sides of the first SoC storage area 301, and the two I/O chips on the same side can be respectively They are located at both ends of the accommodating area 301 to maximize the space between the two I/O chips on the same side, which is convenient for wiring, and can be used for connecting with more second memory chips.
  • the number and arrangement of the I/O chips may not be limited to the above-described manner, but may be specifically designed according to the bandwidth and the size and shape of the product space.
  • the number of I/O chips may be only 2, which are located on both sides of the first SoC accommodating area 301, or 6, with 3 on each side.
  • the I/O chips are not limited to be arranged only on both sides of the first SoC accommodating area 301 , but may be evenly distributed around the first SoC accommodating area 301 .
  • the I/O chip may be quadrilateral. And each side can be provided with a connection interface, and the following layout can be performed: one of the sides or one interface (the side or interface close to the first SoC accommodating area 301 ) is used to connect to the first SoC In the accommodating area 301, the other three sides or the three interfaces are used for connecting the second memory chip.
  • Such a layout design allows one I/O chip to be used for interconnecting with multiple second memory chips, which helps the I/O chip to connect more second memory chips, so as to make full use of the first SoC transmission bandwidth.
  • the I/O chip may be rectangular.
  • the PHY x32/PHY x64 in the figure represent the interfaces on the I/O chip for connecting the 32-bit/64-bit second memory chip, respectively.
  • One side where the long side of the I/O chip is located is provided with an interface for connecting to the first SoC accommodating area 301, and the opposite side is provided with an interface for connecting with a 64-bit second memory chip, and the sides where the two short sides are located are respectively Interfaces for connecting 32-bit and 64-bit second memory chips are provided.
  • one I/O chip can be interconnected with the first SoC accommodating area 301 through the chip interface on one side, and then can be connected with multiple 32-bit or 64-bit chips through the chip interface on the other side.
  • the second memory chips are interconnected, and finally the first SoC accommodating area 301 is interconnected with a plurality of second memory chips.
  • the wiring yield or the process feasibility can be placed close to the accommodating area 301, which helps to reduce the delay, reduce the area occupied by the wiring area, and reduce the cost.
  • the first SoC accommodating area 301 refers to an area for accommodating the first SoC 101 .
  • the accommodating area 301 can be connected to the first SoC 101 by setting pins adapted to the first SoC.
  • By setting the accommodating area 301 it is helpful to flexibly adapt to different application requirements; and it is convenient for streamlined production, only the SoC can be packaged after being placed in this area to complete the pin connection, which improves the production efficiency.
  • the accommodating area 301 can be set in a square shape. However, in other embodiments, the accommodating area may also be in other shapes, such as a rectangle, a circle, and the like.
  • the packaging frame 300 can be designed for the classification of SoCs of different sizes or shapes, so as to ensure that the shape and size of the accommodating area 301 can be as close as possible to the shape and size of the SOC chip to be packaged while mass production is possible. Close to 1:1, thereby reducing costs and improving packaging efficiency.
  • the package substrate can be used to carry I/O chips and chips to be placed in the first SoC accommodating area 301, and can also be used to implement the first SoC accommodating area 301 and I/O chips.
  • 3-2 is another structural schematic diagram illustrating a package frame for a chip according to an embodiment of the present disclosure.
  • the package substrate may include a package substrate and a package interposer, the interposer may be disposed on the package substrate or in the package substrate, and the I/O chip and the first SoC accommodating area 301 may be Connect through the package interposer.
  • the package interposer may be a silicon interposer.
  • the package interposer has a small size and can only cover the wiring or data bus area between the accommodating area 301 and the I/O chip, thus effectively reducing the cost of the package interposer.
  • the package interposer can be embedded or embedded in the package substrate. As shown in FIG. 3-2, by embedding a small piece of package interposer in the package substrate, the space between the accommodating area 301 and the I/O chip can be realized. At the same time, the contact surface between the package substrate and the chip to be packaged can be made flat, thereby helping to reduce the complexity of the package and ensure the structural stability of the entire package frame.
  • each I/O chip and the routing area of the accommodating area 301 can be provided with a package interposer as shown in Figure 3-2 (only one place is shown in Figure 3-2, and the other three places are not shown) , so as to realize the interconnection between each I/O chip and the accommodating area 301 .
  • the encapsulation interposer may also be an RDL Interposer.
  • the package interposer can also be provided to cover the entire receiving area 301 and the I/O chip.
  • the package interposer may also be disposed on the package substrate.
  • FIG. 4 is a schematic structural diagram illustrating a packaged device 400 according to an embodiment of the present disclosure.
  • the packaged device 400 may include the package frame 300 for chips as described above; and the first SoC 101 disposed in the first SoC accommodating area 301 to pass the package The substrate is connected to the I/O chip.
  • the first SoC 101 is a type of SoC that can be used to connect with the first memory chip. As shown in FIG. 4 , the first SoC 101 can be used to realize communicable connection with the I/O chip through the wiring of the package substrate, and then through the I/O chip, other circuit structures other than the package device 400 can be further realized (eg a second memory chip) to connect. In addition to realizing the connection between the first SoC 101 and the I/O chip, the package substrate can also be used to carry the I/O chip and the first SoC 101, and to realize the first SoC 101 and I/O chips are connected to other circuit structures (such as PCB) on the lower layer of the packaged device.
  • other circuit structures such as PCB
  • the detailed description of the role, specific settings, quantity, shape, interface layout, etc. of the I/O chip shown in Figure 4 is the same as the description corresponding to the I/O chip in Figure 3-1 and Figure 3-2 above. or similar, and will not be repeated here.
  • the detailed description of the connection between the first SoC 101 and the I/O chip is the same as the content of the connection between the first SoC accommodating area 301 and the I/O chip described above in conjunction with FIGS. 3-1 and 3-2 or similar, and will not be repeated here.
  • FIG. 5-1 is a schematic structural diagram illustrating an integrated circuit device 500 according to an embodiment of the present disclosure.
  • an integrated circuit device 500 including: the packaged device 400 as described above (ie, the structure in the dashed box in FIG. 5-1); a printed circuit board; and a second memory chip , which is arranged on the printed circuit board, and is connected to the package device 400 through the printed circuit board, thereby realizing the connection between the second memory chip and the first SoC 101 .
  • the second memory chip may be communicatively connected to the packaged device 400 through printed circuit board wiring, that is, a data bus laid in the printed circuit board.
  • the bandwidth of the second memory chip is lower than that of the first memory chip, for example, it may be a DDR, LPDDR, or GDDR chip.
  • the first system-on-chip 101 of the present disclosure can be used to connect the first memory chip, so the pin spacing and size of its interface should first be adapted to the pin spacing and size of the first memory chip.
  • the first SoC 101 of this type or type can also be used to connect with the second memory chip. Due to the difference in the pitch and size of the two pins, it requires a very fine process to complete.
  • the first SoC 101 can be connected to the second memory chip through a package interposer process, but since the interface (pin) (not shown in the figure) of the second memory chip basically occupies the second memory chip Therefore, it is usually necessary to place the entire second memory chip on the package interposer. This solution will greatly increase the size of the package interposer, resulting in an increase in the packaging cost, which in turn leads to a very high cost of the entire chip product.
  • the present invention realizes the interconnection between the first SoC 101 and the I/O chip at a relatively low packaging cost by introducing the packaging scheme of the I/O chip, and then through the common The interconnection with the second memory chip can be realized by the PCB routing process, thereby reducing the cost of the entire product.
  • the plurality of second memory chips may be connected to the first SoC 101 through the I/O chip. More specifically, the number of second memory chips may be greater than the number of I/O chips.
  • I&F stands for the interface to the memory chip interconnection on a packaged system-on-chip.
  • I&F x32/x64 represent the interfaces on the packaged device 400 that are interconnected with the 32-bit/64-bit second memory chip, respectively.
  • each I/O chip can be provided with 4 interconnection interfaces (PHYs), one of which is used to connect to the first SoC 101, and the other three interfaces are used to connect to the second memory chip. More specifically, each I/O chip is used to connect the three interfaces of the second memory chip, and may specifically include two 32-bit interfaces and one 64-bit interface, which can be used to respectively connect two 32-bit interfaces. Two memory chips and one 64-bit second memory chip, or can be used to connect a 32-bit second memory chip and two 64-bit second memory chips respectively by cooperating with other I/O chips . In addition, the I/O chip and the second memory chip can be placed adjacent to each other to facilitate communicative connections with shorter traces, reducing cost and reducing latency.
  • PHYs interconnection interfaces
  • the number of I/O chips may be four, and the number of second memory chips may be six.
  • I/O chips are respectively disposed on both sides of the first SoC 101, and are formed into a packaged device 400 with the first SoC 101 through, for example, a Chiplet packaging scheme.
  • Six second memory chips are respectively disposed in the package Both sides of the device 400 or the package substrate, and may be disposed adjacent to the I/O chip, and the interconnection with the packaged device 400 is completed on the printed circuit board.
  • each I/O chip is communicably connected to two second memory chips, and each I/O chip has an interface that is in an idle state.
  • 5-2 is another schematic structural diagram illustrating an integrated circuit device 500 according to an embodiment of the present disclosure.
  • the number of second memory chips can be set to 10, which are fully connected to the 4 interfaces of the I/O chip, so that there are no idle interfaces on the I/O chip, and the interface utilization rate reaches 100%. .
  • Such a design is conducive to expanding storage capacity and making full use of transmission bandwidth.
  • the present disclosure also discloses an electronic device including the above-mentioned package frame 300 or package device 400 or integrated circuit device 500 .
  • the present disclosure also discloses a board including the above-mentioned package frame 300 or package device 400 or integrated circuit device 500 .
  • FIG. 6 is a flowchart illustrating a method 600 of processing a packaging frame for a chip according to an embodiment of the present disclosure.
  • the method 600 provides a package substrate having a first receiving area and a second receiving area thereon, and the first receiving area and the second receiving area are connected via the packaging substrate,
  • the first accommodating area is used for accommodating the first SoC 101; as shown in FIG. 3 , those skilled in the art can understand that the first and second accommodating areas here may be the same as the first SoC, respectively. 101 and I/O chips are sized and pinned to match.
  • method 600 provides an I/O chip.
  • the method 600 arranges the I/O chip provided in the above-mentioned operation 602 to the second receiving area described in the above-mentioned operation 601 so as to be connected with the first receiving area through the package substrate.
  • the I/O chip may be disposed to the second receiving area by, for example, soldering.
  • FIG. 7 is a flowchart illustrating a method 700 of processing a packaged device according to an embodiment of the present disclosure.
  • the method 700 provides a packaging substrate having a first receiving area and a second receiving area thereon, and the first receiving area and the second receiving area are connected via the packaging substrate;
  • the first and second accommodating areas here can be adapted to the size and pins of the first SoC 101 and the I/O chip.
  • method 700 provides a first system-on-chip 101 and an I/O chip.
  • the method 700 sets the first SoC 101 provided in the foregoing operation 702 to the first receptacle described in the foregoing operation 701, and sets the I/O chip provided in the foregoing operation 702 to the foregoing operation
  • the second accommodating area described in 701 is used to realize the interconnection between the first SoC 101 and the I/O chip through the packaging substrate.
  • FIG. 8 is a flowchart illustrating a method 800 of manufacturing an integrated circuit device according to an embodiment of the present disclosure.
  • method 800 includes various operations in method 700 described above, in addition to operations 704 , 705 and 706 .
  • method 800 provides a printed circuit board having fourth and fifth receiving areas thereon, and the fourth and fifth receiving areas are connected via the printed circuit board.
  • the fourth and fifth receiving areas here can be adapted to the dimensions and pins of the packaged device 400 and the second memory chip.
  • method 800 provides a second memory chip.
  • the method 800 sets the packaged device 400 obtained by the processing method 700 into the fourth receiving area described in the aforementioned operation 704, and sets the second memory chip provided in the aforementioned operation 705 into the aforementioned operation 704.
  • the fifth accommodating area thereby realizing the interconnection of the packaged device 400 and the second memory chip through the printed circuit board.
  • FIGS. 6-8 are only an example, and any method for forming the product of the present disclosure by using discrete devices falls within the protection scope of the present disclosure.
  • the electronic devices or devices of the present disclosure may include servers, cloud servers, server clusters, data processing devices, robots, computers, printers, scanners, tablet computers, smart terminals, PC equipment, IoT terminals, mobile Terminals, mobile phones, driving recorders, navigators, sensors, cameras, cameras, video cameras, projectors, watches, headphones, mobile storage, wearable devices, visual terminals, autonomous driving terminals, vehicles, home appliances, and/or medical equipment.
  • the vehicles include airplanes, ships and/or vehicles;
  • the household appliances include televisions, air conditioners, microwave ovens, refrigerators, rice cookers, humidifiers, washing machines, electric lamps, gas stoves, and range hoods;
  • the medical equipment includes nuclear magnetic resonance instruments, B-ultrasound and/or electrocardiograph.
  • the electronic equipment or device of the present disclosure can also be applied to the Internet, Internet of Things, data center, energy, transportation, public management, manufacturing, education, power grid, telecommunications, finance, retail, construction site, medical care and other fields. Further, the electronic device or device of the present disclosure can also be used in application scenarios related to artificial intelligence, big data and/or cloud computing, such as cloud, edge terminal, terminal, etc.
  • the electronic device or device with high computing power according to the solution of the present disclosure can be applied to a cloud device (eg, a cloud server), while the electronic device or device with low power consumption can be applied to a terminal device and/or Edge devices (such as smartphones or cameras).
  • the hardware information of the cloud device and the hardware information of the terminal device and/or the edge device are compatible with each other, so that the hardware resources of the cloud device can be retrieved from the hardware information of the terminal device and/or the edge device according to the hardware information of the terminal device and/or the edge device. Match the appropriate hardware resources to simulate the hardware resources of terminal devices and/or edge devices, so as to complete the unified management, scheduling and collaborative work of device-cloud integration or cloud-edge-device integration.
  • the present disclosure expresses some methods and their embodiments as a series of actions and their combinations, but those skilled in the art can understand that the solutions of the present disclosure are not limited by the order of the described actions. limit. Accordingly, those of ordinary skill in the art will appreciate that certain operations may be performed in other orders or concurrently, given the disclosure or teachings of this disclosure. Further, those skilled in the art can understand that the embodiments described in the present disclosure may be regarded as optional embodiments, that is, the actions or modules involved therein are not necessarily necessary for the realization of one or some solutions of the present disclosure. In addition, according to different solutions, the present disclosure also has different emphases in the description of some embodiments. In view of this, those skilled in the art can understand the parts that are not described in detail in a certain embodiment of the present disclosure, and can also refer to the related descriptions of other embodiments.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
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  • Semiconductor Integrated Circuits (AREA)

Abstract

L'invention concerne une armature d'encapsulation pour puce, un procédé de traitement, et un produit associé. Dans un scénario d'entraînement d'intelligence artificielle, un appareil de circuit intégré peut comprendre une carte de circuit imprimé. Un substrat d'encapsulation peut être disposé sur la carte de circuit imprimé, et une première puce de système sur puce et une première puce de mémoire peuvent en outre être disposées sur le substrat d'encapsulation. La première puce de système sur puce peut être connectée communicativement à la première puce de mémoire au moyen du substrat d'encapsulation.
PCT/CN2021/141281 2021-03-19 2021-12-24 Armature d'encapsulation pour puce, procédé de traitement, et produit associé WO2022193774A1 (fr)

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CN202110296746.1A CN115117045A (zh) 2021-03-19 2021-03-19 用于芯片的封装框架，加工方法及相关产品

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CN101849227A (zh) * 2005-01-25 2010-09-29 透明信息技术有限公司 在单片构造的硅芯片上采用多个图形核心的图形处理和显示系统
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CN105573919A (zh) * 2014-10-29 2016-05-11 三星电子株式会社 存储器系统、存取存储器芯片的方法和移动电子装置
CN209168091U (zh) * 2019-01-08 2019-07-26 深圳市信步科技有限公司 双层板结构的工控主板
US20200355880A1 (en) * 2016-07-14 2020-11-12 Ayar Labs, Inc. Chip-to-Chip Optical Data Communication System
CN215451412U (zh) * 2021-03-19 2022-01-07 上海寒武纪信息科技有限公司 用于芯片的封装框架、封装器件、集成电路装置、电子设备及板卡

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Publication number Priority date Publication date Assignee Title
CN101849227A (zh) * 2005-01-25 2010-09-29 透明信息技术有限公司 在单片构造的硅芯片上采用多个图形核心的图形处理和显示系统
US20140365813A1 (en) * 2011-12-29 2014-12-11 Leong Hock Sim Watchdogable register-based i/o
CN105573919A (zh) * 2014-10-29 2016-05-11 三星电子株式会社 存储器系统、存取存储器芯片的方法和移动电子装置
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CN209168091U (zh) * 2019-01-08 2019-07-26 深圳市信步科技有限公司 双层板结构的工控主板
CN215451412U (zh) * 2021-03-19 2022-01-07 上海寒武纪信息科技有限公司 用于芯片的封装框架、封装器件、集成电路装置、电子设备及板卡

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