WO2022180762A1 - Dispositif d'amplification différentielle - Google Patents

Dispositif d'amplification différentielle Download PDF

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Publication number
WO2022180762A1
WO2022180762A1 PCT/JP2021/007243 JP2021007243W WO2022180762A1 WO 2022180762 A1 WO2022180762 A1 WO 2022180762A1 JP 2021007243 W JP2021007243 W JP 2021007243W WO 2022180762 A1 WO2022180762 A1 WO 2022180762A1
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Prior art keywords
terminal
signal
transistor
harmonic
resonator
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PCT/JP2021/007243
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English (en)
Japanese (ja)
Inventor
英悟 桑田
拓真 鳥居
実人 木村
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三菱電機株式会社
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Priority to JP2022555616A priority Critical patent/JP7286031B2/ja
Priority to PCT/JP2021/007243 priority patent/WO2022180762A1/fr
Publication of WO2022180762A1 publication Critical patent/WO2022180762A1/fr

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/08—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements
    • H03F1/14—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements by use of neutralising means
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/34—Negative-feedback-circuit arrangements with or without positive feedback
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/34—DC amplifiers in which all stages are DC-coupled
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/68—Combinations of amplifiers, e.g. multi-channel amplifiers for stereophonics

Definitions

  • the present disclosure relates to a differential amplifier device.
  • Patent Document 1 discloses a differential amplifier device that includes a first transistor and a second transistor.
  • the first transistor has a first terminal and a second terminal, amplifies a first signal applied to the first terminal, and outputs the amplified first signal to the second terminal.
  • the second transistor has a third terminal and a fourth terminal, and outputs a second signal when a second signal that is a differential signal from the first signal is applied to the third terminal. It amplifies the second signal and outputs the amplified second signal to the fourth terminal.
  • the differential amplifier device includes a first impedance circuit and a second impedance circuit.
  • the first impedance circuit is a feedback path connecting the second terminal and the third terminal to give the fundamental wave included in the first signal output to the second terminal to the third terminal.
  • the second impedance circuit is a feedback path connecting the fourth terminal and the first terminal in order to apply to the first terminal the fundamental wave contained in the second signal output to the fourth terminal. is inserted in
  • Each of the first impedance circuit and the second impedance circuit is a circuit in which a capacitor and a resistor are connected in series.
  • the present disclosure has been made to solve the above problems, and aims to obtain a differential amplifier device capable of canceling out harmonics contained in each of a first signal and a second signal. aim.
  • a differential amplifier has a first terminal and a second terminal, amplifies a first signal applied to the first terminal, and transmits the amplified first signal to a second A first transistor outputting to a terminal, a third terminal, and a fourth terminal are provided.
  • a second transistor that amplifies the signal of No. 2 and outputs the amplified second signal to a fourth terminal;
  • a first resonator that extracts a harmonic contained in the second signal and a reverse-phase harmonic and outputs the reverse-phase harmonic to a third terminal; 2 extracting the harmonic contained in the first signal applied to the first terminal and the opposite phase harmonic and outputting the opposite phase harmonic to the first terminal; and a resonator.
  • harmonics contained in each of the first signal and the second signal can be canceled.
  • FIG. 1 is a configuration diagram showing a differential amplifier device according to Embodiment 1;
  • FIG. 2 is a circuit diagram showing an equivalent circuit of a first transistor 1-1 and an equivalent circuit of an output side of a second transistor 1-2;
  • FIG. 3 is a circuit diagram showing the circuit diagram shown in FIG. 2 using impedances Z 1 and Z 2 ;
  • FIG. 4 is an explanatory diagram showing a second resonator 2-2 implemented by a second inductor 3-2 and a second capacitor 4-2;
  • the impedance of each of the capacitor 13 and the second resonator 2-2 when the frequency is 10 [GHz] and the impedance of each of the capacitor 13 and the second resonator 2-2 when the frequency is 20 [GHz] is a Smith chart showing the impedance of FIG.
  • FIG. 3 is a configuration diagram showing a differential amplifier device mounted with a second inductor 3-2 and a second capacitor 4-2 capable of mutually canceling a harmonic signal 2fo 1 and a harmonic signal 2fo 2 ; .
  • FIG. 10 is a waveform diagram showing voltage swings at the first terminal 1-1a when a secondary harmonic is superimposed on the fundamental wave;
  • FIG. 4 is a waveform diagram showing the voltage swing at the first terminal 1-1a when a voltage amplitude greater than the amplitude of the gate voltage that can be used to amplify the analog signal is applied to the gate terminal;
  • FIG. 10 is an explanatory diagram showing the result of FFT calculation of the attenuation ratio of the amplitude of the fundamental wave signal when the voltage ratio between the voltage of the fundamental wave and the voltage of the second harmonic wave is varied;
  • FIG. 1 is a configuration diagram showing a differential amplifier device according to Embodiment 1.
  • the differential amplifier shown in FIG. 1 comprises a first transistor 1-1, a second transistor 1-2, a first resonator 2-1 and a second resonator 2-2.
  • the first transistor 1-1 has a first terminal 1-1a and a second terminal 1-1b.
  • the first terminal 1-1a is, for example, the gate terminal of the first transistor 1-1 and is supplied with the first signal.
  • the second terminal 1-1b is, for example, the drain terminal of the first transistor 1-1, and outputs the first signal amplified by the first transistor 1-1.
  • the source terminal of the first transistor 1-1 is grounded.
  • the first transistor 1-1 amplifies the first signal applied to the first terminal 1-1a and outputs the amplified first signal to the second terminal 1-1b.
  • the second transistor 1-2 has a third terminal 1-2a and a fourth terminal 1-2b.
  • the third terminal 1-2a is, for example, the gate terminal of the second transistor 1-2, and receives a second signal that is a differential signal from the first signal.
  • the fourth terminal 1-2b is, for example, the drain terminal of the second transistor 1-2, and outputs the second signal amplified by the second transistor 1-2.
  • the source terminal of the second transistor 1-2 is grounded.
  • the second transistor 1-2 amplifies the second signal applied to the third terminal 1-2a and outputs the amplified second signal to the fourth terminal 1-2b.
  • each of the first transistor 1-1 and the second transistor 1-2 is a source-grounded transistor.
  • each of the first transistor 1-1 and the second transistor 1-2 may be, for example, a drain-grounded transistor.
  • the first resonator 2-1 comprises a first inductor 3-1 and a first capacitor 4-1.
  • the first resonator 2-1 converts the first signal output to the second terminal 1-1b to the harmonic contained in the second signal applied to the third terminal 1-2a. Extract the out-of-phase harmonics.
  • the first resonator 2-1 outputs the extracted reverse-phase harmonics to the third terminal 1-2a.
  • the second resonator 2-2 comprises a second inductor 3-2 and a second capacitor 4-2.
  • the second resonator 2-2 extracts harmonics contained in the first signal applied to the first terminal 1-1a from the second signal output to the fourth terminal 1-2b. Extract the out-of-phase harmonics.
  • the second resonator 2-2 outputs the extracted reversed-phase harmonics to the first terminal 1-1a.
  • Respective resonance frequencies of the first resonator 2-1 and the second resonator 2-2 are obtained by a first signal applied to the first terminal 1-1a and a signal applied to the third terminal 1-2a. higher than the frequency of the second harmonic contained in each of the second signals.
  • the respective impedances of the first resonator 2-1 and the second resonator 2-2 are equivalent to the respective impedances of the first transistor 1-1 and the second transistor 1-2 at the second harmonic frequency.
  • Matches the feedback capacitance is not limited to cases in which the impedance and the equivalent feedback capacitance are exactly the same, but a concept that includes cases in which the impedance and the equivalent feedback capacitance are different within a range that poses no practical problems. is.
  • FIG. 2 is a circuit diagram showing an equivalent circuit of the first transistor 1-1 and an equivalent circuit of the output side of the second transistor 1-2.
  • the first transistor 1-1 is represented by capacitor 11, parasitic resistance 12, capacitor 13, current source 14-1 and capacitor 15-1.
  • a capacitor 11 has the input capacitance Cgs of the first transistor 1-1. One end of the capacitor 11 is connected to the first terminal 1-1a, and the other end of the capacitor 11 is connected to one end of the parasitic resistor 12. As shown in FIG.
  • the parasitic resistance 12 has the input parasitic resistance value Ri of the first transistor 1-1. One end of the parasitic resistance 12 is connected to the other end of the capacitor 11, and the other end of the parasitic resistance 12 is connected to the ground.
  • a capacitor 13 has a feedback capacitance Cgd of the first transistor 1-1. One end of the capacitor 13 is connected to the first terminal 1-1a, and the other end of the capacitor 13 is connected to the second terminal 1-1b.
  • a capacitor 15-1 has the output capacitance Cds 1 of the first transistor 1-1. One end of the capacitor 15-1 is connected to the second terminal 1-1b, and the other end of the capacitor 15-1 is connected to the ground.
  • a capacitor 15-2 has the output capacitance Cds 2 of the second transistor 1-2.
  • the output capacitance Cds2 of the second transistor 1-2 is the same as the output capacitance Cds1 of the first transistor 1-1.
  • One end of the capacitor 15-2 is connected to the fourth terminal 1-2b, and the other end of the capacitor 15-2 is connected to the ground.
  • the second resonator 2-2 has an impedance Z matrix2 .
  • the impedance Z matrix2 of the second resonator 2-2 is the same as the impedance Z matrix1 of the first resonator 2-1.
  • the input circuit 21 has a load impedance Zimn . One end of the input circuit 21 is connected to the first terminal 1-1a of the first transistor 1-1, and the other end of the input circuit 21 is connected to the ground.
  • the output circuit 22-1 has a load impedance Zomn1 .
  • One end of the output circuit 22-1 is connected to the second terminal 1-1b of the first transistor 1-1, and the other end of the output circuit 22-1 is connected to the ground.
  • the output circuit 22-2 has a load impedance Zomn2 .
  • the load impedance Z omn2 of the output circuit 22-2 is the same as the load impedance Z omn1 of the output circuit 22-1.
  • One end of the output circuit 22-2 is connected to the fourth terminal 1-2b of the second transistor 1-2, and the other end of the output circuit 22-2 is connected to the ground.
  • the first transistor 1-1 and the second transistor 1-2 have the same characteristics, and the load impedance Z omn1 of the output circuit 22-1 and the load impedance Z omn2 of the output circuit 22-2 have the same load impedance. is. Therefore, the impedance Z1 looking into the output side from the second terminal 1-1b of the first transistor 1-1 and the impedance Z1 looking into the output side from the fourth terminal 1-2b of the second transistor 1-2 are becomes equal to the impedance Z2 .
  • FIG. 3 is a circuit diagram showing the circuit diagram shown in FIG. 2 using impedances Z 1 and Z 2 .
  • 30-1 indicates a load impedance Z1 looking into the output side from the second terminal 1-1b of the first transistor 1-1.
  • 30-2 denotes a load impedance Z2 looking into the output side from the fourth terminal 1-2b of the second transistor 1-2.
  • a harmonic signal 2fo1 generated by the current source 14-1 of the first transistor 1-1 is injected into the first terminal 1-1a through the capacitor 13 having the feedback capacitance Cgd.
  • a harmonic signal 2fo2 generated by the current source 14-2 of the second transistor 1-2 is injected into the first terminal 1-1a through the second resonator 2-2. Since the first transistor 1-1 and the second transistor 1-2 operate in opposite phases, the harmonic signal 2fo1 and the harmonic signal 2fo2 have an opposite phase relationship.
  • the impedance Z1 and the impedance Z2 are equal , and the amount of phase rotation and the amount of amplitude attenuation due to the feedback capacitance Cgd of the capacitor 13 and the amount of phase rotation and the amount of amplitude attenuation due to the second resonator 2-2 are If each of the quantities are equal, the harmonic signal 2fo 1 and the harmonic signal 2fo 2 cancel each other.
  • the frequencies of the harmonic signals 2fo 1 and 2fo 2 are set to , the capacitor 13 and the second resonator 2-2 must have the same impedance.
  • the second resonator 2-2 When the second resonator 2-2 is realized by a second inductor 3-2 and a second capacitor 4-2, as shown in FIG. 4, the second inductor 3-2 and the second capacitor
  • the combined impedance with 4-2 is represented by the following equation (1).
  • ⁇ is the harmonic angular frequency, which is the frequency of the harmonic signals 2fo 1 and 2fo 2 multiplied by 2 ⁇ .
  • L FB is the inductance of the second inductor 3-2
  • C FB is the capacitance of the second capacitor 4-2.
  • FIG. 4 is an explanatory diagram showing the second resonator 2-2 implemented by the second inductor 3-2 and the second capacitor 4-2.
  • FIG. 5 shows the respective impedances of the capacitor 13 and the second resonator 2-2 when the frequency is 10 [GHz], and the impedances of the capacitor 13 and the second resonator 2 when the frequency is 20 [GHz].
  • 2 is a Smith chart showing the respective impedances at -2; When the frequency is 20 [GHz], as shown in FIG. 5, the impedance of the capacitor 13 and the impedance Z matrix 2 of the second resonator 2-2 are equal, and the high harmonic The wave signal 2fo 1 and the harmonic signal 2fo 2 cancel each other.
  • FIG. 6 is a configuration diagram showing a differential amplifier capable of mutually canceling the harmonic signal 2fo1 and the harmonic signal 2fo2 .
  • the first resonator 2-1 comprises a first series circuit in which a first inductor 3-1 and a first capacitor 4-1 are connected in series. One end of the first series circuit is connected to the third terminal 1-2a, and the other end of the first series circuit is connected to the second terminal 1-1b.
  • the second resonator 2-2 comprises a second series circuit in which a second inductor 3-2 and a second capacitor 4-2 are connected in series. One end of the second series circuit is connected to the first terminal 1-1a, and the other end of the second series circuit is connected to the fourth terminal 1-2b.
  • the two harmonic signals cancel each other out. That is, the combined impedance of the first inductor 3-1 and the first capacitor 4-1 included in the first resonator 2-1 has the feedback capacitance of the second transistor 1-2. If the impedance of the capacitor is equal, the two harmonic signals cancel each other at the third terminal 1-2a.
  • the first resonator 2-1 includes a first series circuit in which a first inductor 3-1 and a first capacitor 4-1 are connected in series. ing.
  • the first resonator 2-1 only needs to be able to output to the third terminal 1-2a a harmonic that is in phase opposite to the harmonic contained in the second signal applied to the third terminal 1-2a.
  • the first inductor 3-1 and the first capacitor 4-1 may be connected in parallel.
  • the second resonator 2-2 has a second series circuit in which the second inductor 3-2 and the second capacitor 4-2 are connected in series. ing.
  • the second resonator 2-2 only needs to be able to output to the first terminal 1-1a a harmonic that is in phase opposite to the harmonic contained in the first signal applied to the first terminal 1-1a.
  • the second inductor 3-2 and the second capacitor 4-2 may be connected in parallel.
  • each of the first transistor 1-1 and the second transistor 1-2 is a field effect transistor.
  • the voltage swing across the capacitor 11 having the input capacitance Cgs is converted into the current swing of the current source 14-1.
  • FIG. 7 is a waveform diagram showing the voltage swing of the first terminal 1-1a when the second harmonic is superimposed on the fundamental wave.
  • the horizontal axis is the time
  • the vertical axis is the voltage of the first terminal 1-1a.
  • V1 shows the voltage waveform under ideal conditions in which the second harmonic is not superimposed on the fundamental wave. Under ideal conditions, the voltage ratio between the voltage of the fundamental wave and the voltage of the second harmonic is 1:0.
  • V2 indicates a voltage waveform when the voltage ratio of the voltage of the fundamental wave and the voltage of the second harmonic wave is 1:1.1.
  • V3 shows the voltage waveform when the voltage ratio of the voltage of the fundamental wave and the voltage of the second harmonic wave is 1:1.2.
  • the voltage swing of the first terminal 1-1a increases as the voltage of the second harmonic superimposed on the fundamental wave increases.
  • the current flowing through the field effect transistor reaches the maximum current when the voltage applied to the gate terminal reaches a certain voltage. do. Once the current through the field effect transistor reaches the maximum current, any further increase in the voltage applied to the gate terminal does not increase the current through the field effect transistor above the maximum current. Therefore, the amplitude of the current output from the drain terminal of the field effect transistor does not increase.
  • the field effect transistor is realized by a compound semiconductor, the gate terminal is formed by a Schottky junction, and thus includes a forward diode. Therefore, even if a voltage higher than about 1 [V] is applied to the gate terminal, the drain current hardly increases.
  • the drain current becomes 0 when the voltage applied to the gate terminal reaches a certain voltage, and the field effect transistor The amplitude of the current output from the drain terminal stops increasing.
  • FIG. 8 is a waveform diagram showing the voltage swing at the first terminal 1-1a when a voltage amplitude larger than the amplitude of the gate voltage that can be used to amplify the analog signal is applied to the gate terminal.
  • the horizontal axis is the time
  • the vertical axis is the voltage of the first terminal 1-1a.
  • V1 is the same voltage waveform as V1 shown in FIG. 7 , which is the voltage waveform under ideal conditions.
  • the maximum amplitude of the voltage waveform under ideal conditions is the same as the maximum amplitude of the gate voltage that can be used to amplify analog signals.
  • V2 is a voltage waveform when the voltage ratio of the voltage of the fundamental wave and the voltage of the second harmonic wave is 1:1.1.
  • V3 is a voltage waveform when the voltage ratio of the voltage of the fundamental wave and the voltage of the second harmonic wave is 1:1.2.
  • a voltage amplitude larger than the maximum amplitude of the gate voltage that can be used to amplify the analog signal is clipped to the maximum amplitude.
  • the secondary harmonic is superimposed on the fundamental wave, resulting in a voltage larger than the maximum amplitude of the gate voltage that can be used to amplify the analog signal.
  • the voltage amplitude is clipped to the maximum amplitude and reduced.
  • the drain current of the first transistor 1-1 decreases, and the gain and output power of the fundamental wave in the first transistor 1-1 decrease.
  • the efficiency of the first transistor 1-1 is obtained by dividing the output power by the power consumption, and therefore decreases as the output power decreases.
  • FIG. 9 is an explanatory diagram showing the result of FFT (Fast Fourier Transform) calculation of the attenuation ratio of the amplitude of the fundamental wave signal when the voltage ratio between the voltage of the fundamental wave and the voltage of the second harmonic is varied. .
  • FFT Fast Fourier Transform
  • the first terminal 1-1a and the second terminal 1-1b are provided, and the first signal applied to the first terminal 1-a is amplified. 1 signal to the second terminal 1-1b, the third terminal 1-2a and the fourth terminal 1-2b, and the first signal and the differential
  • a second signal which is a signal
  • the second signal is amplified and the amplified second signal is output to the fourth terminal 1-2b.
  • a differential amplifier is configured to include transistors 1-2. Further, the differential amplifier device converts the first signal output to the second terminal 1-1b into the second signal supplied to the third terminal 1-2a, which is in phase with the harmonic contained in the second signal.
  • the differential amplifier can cancel harmonics contained in each of the first signal and the second signal.
  • the present disclosure is suitable for differential amplifiers.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Amplifiers (AREA)

Abstract

La présente divulgation concerne un dispositif d'amplification différentielle qui est configuré pour comprendre : un premier transistor (1-1) qui a une première borne (1-1a) et une deuxième borne (1-1b), amplifie un premier signal fourni à la première borne (1-a), et délivre le premier signal amplifié à la deuxième borne (1-1b) ; et un deuxième transistor (1-2) qui a une troisième borne (1-2a) et une quatrième borne (1-2b), amplifie un deuxième signal en tant que signal indiquant un différentiel avec le premier signal lorsque le deuxième signal est fourni à la troisième borne (1-2a), et délivre le deuxième signal amplifié à la quatrième borne (1-2b). En outre, le dispositif d'amplification différentielle comporte : un premier résonateur (2-1) qui extrait, de la première sortie de signal à la deuxième borne (1-1b), une harmonique dans une phase inverse à une harmonique contenue dans le deuxième signal fourni à la troisième borne (1-2a) et délivre l'harmonique en phase inverse à la troisième borne (1-2a) ; et un deuxième résonateur (2-2) qui extrait, du deuxième signal délivré à la quatrième borne (1-2b), une harmonique dans une phase inverse à une harmonique contenue dans le premier signal fourni à la première borne (1-1a) et délivre l'harmonique en phase inverse à la première borne (1-1a).
PCT/JP2021/007243 2021-02-26 2021-02-26 Dispositif d'amplification différentielle WO2022180762A1 (fr)

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JP2022555616A JP7286031B2 (ja) 2021-02-26 2021-02-26 差動増幅装置
PCT/JP2021/007243 WO2022180762A1 (fr) 2021-02-26 2021-02-26 Dispositif d'amplification différentielle

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PCT/JP2021/007243 WO2022180762A1 (fr) 2021-02-26 2021-02-26 Dispositif d'amplification différentielle

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JP2005012770A (ja) * 2003-05-22 2005-01-13 Matsushita Electric Ind Co Ltd 高周波差動回路、差動増幅器、差動ミキサ、差動発振器、およびそれらを用いた無線回路
JP2006148190A (ja) * 2004-11-16 2006-06-08 Sharp Corp 差動増幅回路
JP2006521748A (ja) * 2003-03-28 2006-09-21 コーニンクレッカ　フィリップス　エレクトロニクス　エヌ　ヴィ 増幅器における帰還キャパシタンスの中和
JP2012191600A (ja) * 2011-02-24 2012-10-04 Fujitsu Ltd 増幅回路
US20170005630A1 (en) * 2015-07-01 2017-01-05 Sunrise Micro Devices, Inc. Scaleable rf tuned low noise amplifier
JP2017163197A (ja) * 2016-03-07 2017-09-14 パナソニック株式会社 電力増幅回路

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Publication number Priority date Publication date Assignee Title
JP2007336048A (ja) 2006-06-13 2007-12-27 Nec Electronics Corp 高周波用電力増幅器
JP2018160882A (ja) 2017-03-21 2018-10-11 パナソニック株式会社 電力増幅分配回路及び多段型の電力増幅分配回路
KR102595794B1 (ko) 2018-08-31 2023-10-30 삼성전자주식회사 송신 장치에서 전력을 증폭하기 위한 장치 및 방법

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006521748A (ja) * 2003-03-28 2006-09-21 コーニンクレッカ　フィリップス　エレクトロニクス　エヌ　ヴィ 増幅器における帰還キャパシタンスの中和
JP2005012770A (ja) * 2003-05-22 2005-01-13 Matsushita Electric Ind Co Ltd 高周波差動回路、差動増幅器、差動ミキサ、差動発振器、およびそれらを用いた無線回路
JP2006148190A (ja) * 2004-11-16 2006-06-08 Sharp Corp 差動増幅回路
JP2012191600A (ja) * 2011-02-24 2012-10-04 Fujitsu Ltd 増幅回路
US20170005630A1 (en) * 2015-07-01 2017-01-05 Sunrise Micro Devices, Inc. Scaleable rf tuned low noise amplifier
JP2017163197A (ja) * 2016-03-07 2017-09-14 パナソニック株式会社 電力増幅回路

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JPWO2022180762A1 (fr) 2022-09-01

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