WO2022177504A1 - Semiconductor apparatus and method for fabricating thereof - Google Patents

Semiconductor apparatus and method for fabricating thereof Download PDF

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Publication number
WO2022177504A1
WO2022177504A1 PCT/SG2022/050005 SG2022050005W WO2022177504A1 WO 2022177504 A1 WO2022177504 A1 WO 2022177504A1 SG 2022050005 W SG2022050005 W SG 2022050005W WO 2022177504 A1 WO2022177504 A1 WO 2022177504A1
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Prior art keywords
film
deposited
semiconductor apparatus
gate
ohmic contact
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PCT/SG2022/050005
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French (fr)
Inventor
Yuan Gao
Chengyu HU
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Igss-Gan Pte Ltd
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Publication of WO2022177504A1 publication Critical patent/WO2022177504A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/8258—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using a combination of technologies covered by H01L21/8206, H01L21/8213, H01L21/822, H01L21/8252, H01L21/8254 or H01L21/8256
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0922—Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds

Definitions

  • the disclosures made herein relate generally to a semiconductor apparatus, and more particularly to relates to a method for manufacturing a semiconductor apparatus (e.g., gate formation of gate Gallium nitride high- electron-mobility transistor (GaN HEMT) device or the like).
  • a semiconductor apparatus e.g., gate formation of gate Gallium nitride high- electron-mobility transistor (GaN HEMT) device or the like.
  • Gallium nitride (GaN) semiconductor devices are recognized as the next generation of semiconductor devices suitable for power applications.
  • GaN semiconductor devices In order to realize the advantage of the GaN semiconductor device, one of the key factor is device fabrication cost.
  • An Si CMOS fully compatible GaN device fabrication process can enable fast adoption of existing Si CMOS fabrication (Fab), which can bring down the fabrication cost significantly.
  • Figure 1 illustrates a cross-sectional view of a conventional Gallium Nitride (GaN) Metal-Insulator-Semiconductor High Electron Mobility Transistor (MISHEMT) device (1000a), in accordance with prior art.
  • GaN Gallium Nitride
  • MISHEMT Metal-Insulator-Semiconductor High Electron Mobility Transistor
  • FIG. 2a to Figure 2c illustrate an example fabrication process of a conventional GaN MISHEMT device (1000b), in accordance with prior art.
  • the conventional GaN MISHEMT (1000a) operates based on a conductive two dimensional electron gas (2DEG) layer (106), which can be modulated by a gate metal contact (114).
  • the 2DEG layer (106) is formed between two epitaxy grown nitride layers (e.g., GaN layer and AlGaN layer) (102 and 104), which have different bandgaps. These two consecutively grown nitride layers (102 and 104) introduce polarization at the interface, which contributes to the formation of the 2DEG layer (106) near the interface of the two layers (102 and 104), specifically in the layer with the narrower band gap.
  • an external voltage applied on a gate will modulate the band gap bent between two different nitride layers (102 and 104), hence modulating on/off of the 2DEG layer (106), so as to control HEMT transistor turn on or turn off.
  • a gate In the conventional GaN MISHEMT transistor (1000a or 100b), a gate
  • (116) is formed by various metal material as shown in the figure 1. Normally, a metal film re-forms or changes the property when undergo a high temperature (> 600C) thermal process, hence typical GaN MISHEMT process forms an ohmic contact (112) first before forming the transistor gate (116). This will limit the selection of the gate insulator film (110), due to ohmic contact cannot undergo high temperature insulator film deposition.
  • a conventional GaN MISHEMT fabrication sequence is illustrated. After an isolation region (108) is formed, a gate insulator film (110) have to be deposited first, followed by a formation of the ohmic contact metal (112). Then, a dielectric film (114) is deposited to isolate the ohmic contact metal (112) and subsequent gate metal (116), after that, a high selectivity etching (between the gate insulator film (110) and the dielectric film (114)) process is needed to etch away the gate metal (114) and stop on gate insulator film (110). Subsequently, proper cleaning is needed to minimize etch damage to the gate insulator film (110) before depositing the gate metal material (114).
  • the present invention relates to a semiconductor apparatus.
  • the semiconductor apparatus comprises a Gallium nitride (GaN) buffer and an Aluminium gallium nitride (AlGaN) barrier.
  • a two-dimensional electron gas (2DEG) is formed between the GaN buffer and the AlGaN barrier.
  • An isolation region is formed on at least one side portion of the 2DEG, the GaN buffer and the AlGaN barrier.
  • a dielectric film is deposited on a portion of the isolation region and a portion of the AlGaN barrier.
  • a gate insulation film is deposited on the dielectric film.
  • a heavy doped poly silicon (Si) film is deposited on the gate insulation film.
  • the dielectric film is deposited again on the gate insulation film and the heavy doped poly Si film followed by an ohmic contact opening to etch away the dielectric film and the gate insulation film to expose an ohmic contact area.
  • At least one ohmic contact metal is deposited and patterned on a portion of the AlGaN barrier.
  • the at least one ohmic contact metal is deposited and patterned on at least one of a portion of the dielectric film and a portion of the gate insulation film.
  • the heavy doped Poly Si film enables gate formation in the semiconductor apparatus before an ohmic contact formation process.
  • the gate insulator film and the heavy doped Poly Si film are deposited after the dielectric film is etched away in a gate region of the semiconductor apparatus. In an embodiment, the gate insulator film and the highly doped Poly Si layer are deposited consecutively, so as to ensure a good interface quality between the gate insulator film and the highly doped poly Si layer.
  • the semiconductor apparatus comprises a Gallium nitride high-electron-mobility transistor (GaN HEMT) device and a Gallium Nitride (GaN) Metal-Insulator-Semiconductor High Electron Mobility Transistor (MISHEMT) device.
  • GaN HEMT Gallium nitride high-electron-mobility transistor
  • GaN Gallium Nitride
  • MISHEMT Metal-Insulator-Semiconductor High Electron Mobility Transistor
  • the semiconductor apparatus is compatible with an Si CMOS process.
  • the present invention relates to a method for fabricating a semiconductor apparatus.
  • the method includes providing the GaN buffer and an AlGaN barrier. Further, the method includes forming a 2DEG between the GaN buffer and the AlGaN barrier. Further, the method includes forming an isolation region on at least one side portion of the 2DEG, the GaN buffer and the AlGaN barrier. Further, the method includes depositing a dielectric film on a portion of the isolation region and a portion of the AlGaN barrier. Further, the method includes depositing a gate insulation film on the dielectric film. Further, the method includes depositing a heavy doped poly Si film deposited on the gate insulation film.
  • the dielectric film is deposited again on the gate insulation film and the heavy doped poly Si film followed by an ohmic contact opening to etch away the dielectric film and the gate insulation film to expose an ohmic contact area. Further, the method includes depositing at least one ohmic contact metal and patterning on a portion of the AlGaN barrier. The at least one ohmic contact metal is deposited and patterned on at least one of a portion of the dielectric film and a portion of the gate insulation film.
  • Figure 1 illustrates a cross-sectional view of a conventional GaN MISHEMT device, in accordance with prior art.
  • Figure 2a to Figure 2c illustrate an example fabrication process of a conventional GaN MISHEMT device, in accordance with prior art.
  • Figure 3a to Figure 3d illustrate an example fabrication process of a GaN MISHEMT device, in accordance with one embodiment of the present invention.
  • Figure 4 is an example flow chart illustrating a method for fabricating a
  • GaN MISHEMT device GaN MISHEMT device, according to one embodiment of the present invention.
  • the embodiment herein is to provide a semiconductor apparatus comprising a GaN buffer and an AlGaN barrier.
  • a 2DEG is formed between the GaN buffer and the AlGaN barrier.
  • An isolation region is formed on at least one side portion of the 2DEG, the GaN buffer and the AlGaN barrier.
  • a dielectric film is deposited on a portion of the isolation region and a portion of the AlGaN barrier.
  • a gate insulation film is deposited on the dielectric film.
  • a heavy doped poly silicon (Si) film is deposited on the gate insulation film. The dielectric film is deposited again on the gate insulation film and the heavy doped poly Si film followed by an ohmic contact opening to etch away the dielectric film and the gate insulation film to expose an ohmic contact area.
  • At least one ohmic contact metal is deposited and patterned on a portion of the AlGaN barrier.
  • the at least one ohmic contact metal is deposited and patterned on at least one of a portion of the dielectric film and a portion of the gate insulation film.
  • a metal film is used to form a transistor gate in a Gallium Nitride (GaN) Metal-Insulator-Semiconductor High Electron Mobility Transistor (MISHEMT).
  • GaN Gallium Nitride
  • MISHEMT Metal-Insulator-Semiconductor High Electron Mobility Transistor
  • a gate metal is normally formed after source/drain ohmic contact formation due to the concern of high temperature anneal process for ohmic contact formation.
  • a special gate metal material is needed, which may not be Si CMOS fab compatible.
  • An Si CMOS Fab proven material - Poly Si can be used for GaN MISHEMT gate formation, the Poly Si can be heavily doped to low sheet resistance, which has similar work function as a metal material.
  • the proposed method will make GaN MISHEMT process fully compatible with the Si CMOS process.
  • the gate formation of the semiconductor apparatus can be easily enabled, which helps to minimize high selectivity etch process requirement, improves gate leakage performance and enhances device reliability.
  • the proposed method process is fully compatible with the standard Si CMOS process.
  • FIG 3a to Figure 3d illustrate an example fabrication process of a semiconductor apparatus (3000), in accordance with one embodiment of the present invention.
  • the semiconductor apparatus (3000) can be a Gallium nitride high-electron-mobility transistor (GaN HEMT) device and a GaN MISHEMT device.
  • GaN HEMT Gallium nitride high-electron-mobility transistor
  • the semiconductor apparatus (3000) includes a 2DEG (106) formed between the GaN buffer (102) and the AlGaN barrier (104).
  • An isolation region (108) is formed on at least one side portion of the 2DEG (106), the GaN buffer (102) and the AlGaN barrier (104).
  • a dielectric film (114) is deposited on a portion of the isolation region (108) and a portion of the AlGaN barrier (104).
  • a gate insulation film (110) is deposited on the dielectric film (114).
  • a heavy doped poly silicon (Si) film (118) is deposited on the gate insulation film (110).
  • the dielectric film (114) is deposited again on the gate insulation film (110) and the heavy doped poly Si film (118) followed by an ohmic contact opening to etch away the dielectric film (114) and the gate insulation film (110) to expose an ohmic contact area.
  • the heavy doped Poly Si film (118) enables gate formation in the semiconductor apparatus (3000) before an ohmic contact formation process.
  • the gate insulator film (110) and the heavy doped Poly Si film (118) are deposited after the dielectric film (114) is etched away in a gate region of the semiconductor apparatus (3000).
  • At least one ohmic contact metal (112) is deposited and patterned on a portion of the AlGaN barrier (104).
  • the at least one ohmic contact metal (112) is deposited and patterned on at least one of a portion of the dielectric film (114) and a portion of the gate insulation film (110).
  • the gate insulator film (110) and the highly doped Poly Si layer (118) are deposited consecutively, so as to ensure a good interface quality between the gate insulator film (110) and the highly doped poly Si layer (118).
  • the fabrication of the semiconductor apparatus (3000) is compatible with an Si CMOS process.
  • the gate formation of the semiconductor apparatus (3000) can be easily enabled, which helps to minimize high selectivity etch process requirement, improves gate leakage performance and enhances device reliability.
  • the proposed method can be used to eliminate a high selectivity (between the gate insulator film (110) and the dielectric film (114)) etch challenge and potential plasma etch damage to the gate insulator film (110), which improves gate leakage performance and device reliability.
  • Figure 4 is an example flow chart (S4000) illustrating a method for fabricating the GaN MISHEMT device, according to one embodiment of the present invention.
  • the method includes providing the GaN buffer (102) and the AlGaN barrier (104).
  • the method includes forming the 2DEG (106) between the GaN buffer (102) and the AlGaN barrier (104).
  • the method includes forming the isolation region (108) on at least one side portion of the 2DEG (106), the GaN buffer (102) and the AlGaN barrier (104).
  • the method includes depositing the dielectric film (114) on the portion of the isolation region (108) and the portion of the AlGaN barrier (104).
  • the method includes depositing the gate insulation film (110) on the dielectric film (114).
  • the method includes depositing the heavy doped poly Si film (118) deposited on the gate insulation film (110).
  • the dielectric film (114) is deposited again on the gate insulation film (110) and the heavy doped poly Si film (118) followed by an ohmic contact opening to etch away the dielectric film (114) and the gate insulation film (110) to expose an ohmic contact area.
  • the method includes depositing at least one ohmic contact metal (112) and patterning on a portion of the AlGaN barrier (104).
  • the at least one ohmic contact metal (112) is deposited and patterned on at least one of a portion of the dielectric film (114) and a portion of the gate insulation film (110).
  • a metal film is used to form a transistor gate in a Gallium Nitride (GaN) Metal-Insulator-Semiconductor High Electron Mobility Transistor (MISHEMT).
  • GaN Gallium Nitride
  • MISHEMT Metal-Insulator-Semiconductor High Electron Mobility Transistor
  • a gate metal is normally formed after source/drain ohmic contact formation due to the concern of high temperature anneal process for ohmic contact formation.
  • a special gate metal material is needed, which may not be Si CMOS fab compatible.
  • An Si CMOS Fab proven material - Poly Si can be used for GaN MISHEMT gate formation, the Poly Si can be heavily doped to low sheet resistance, which has similar work function as a metal material.
  • the proposed method will make the GaN MISHEMT process fully compatible with the Si CMOS process.
  • the gate formation of the semiconductor apparatus can be easily enabled, which helps to minimize high selectivity etch process requirement, improves gate leakage performance and enhances device reliability.
  • the proposed method can be used to eliminate a high selectivity (between the gate insulator film (110) and the dielectric film (114)) etch challenge and potential plasma etch damage to gate insulator film (110), which will improve gate leakage performance and device reliability.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The present invention relates to a semiconductor apparatus (3000). A semiconductor apparatus (3000) comprising a heavy doped poly Si film (118) deposited on a gate insulation film (110). A dielectric film (114) is deposited on the gate insulation film (110) and the heavy doped poly Si film (118) followed by an ohmic contact opening to etch away the dielectric film (114) and the gate insulation film (110) to expose an ohmic contact area. At least one ohmic contact metal (112) is deposited and patterned on a portion of the AlGaN barrier (104). The at least one ohmic contact metal (112) is deposited and patterned on at least one of a portion of the dielectric film (114) and a portion of the gate insulation film (110).

Description

SEMICONDUCTOR APPARATUS AND METHOD FOR FABRICATING
THEREOF
FIELD OF THE INVENTION The disclosures made herein relate generally to a semiconductor apparatus, and more particularly to relates to a method for manufacturing a semiconductor apparatus (e.g., gate formation of gate Gallium nitride high- electron-mobility transistor (GaN HEMT) device or the like). BACKGROUND OF THE INVENTION
Ascribed to the capability of carrying large current and supporting high voltages, Gallium nitride (GaN) semiconductor devices are recognized as the next generation of semiconductor devices suitable for power applications. In order to realize the advantage of the GaN semiconductor device, one of the key factor is device fabrication cost. An Si CMOS fully compatible GaN device fabrication process can enable fast adoption of existing Si CMOS fabrication (Fab), which can bring down the fabrication cost significantly.
Figure 1 illustrates a cross-sectional view of a conventional Gallium Nitride (GaN) Metal-Insulator-Semiconductor High Electron Mobility Transistor (MISHEMT) device (1000a), in accordance with prior art.
Figure 2a to Figure 2c illustrate an example fabrication process of a conventional GaN MISHEMT device (1000b), in accordance with prior art.
Referring to the Figure 1, the conventional GaN MISHEMT (1000a) operates based on a conductive two dimensional electron gas (2DEG) layer (106), which can be modulated by a gate metal contact (114). The 2DEG layer (106) is formed between two epitaxy grown nitride layers (e.g., GaN layer and AlGaN layer) (102 and 104), which have different bandgaps. These two consecutively grown nitride layers (102 and 104) introduce polarization at the interface, which contributes to the formation of the 2DEG layer (106) near the interface of the two layers (102 and 104), specifically in the layer with the narrower band gap.
Further, an external voltage applied on a gate will modulate the band gap bent between two different nitride layers (102 and 104), hence modulating on/off of the 2DEG layer (106), so as to control HEMT transistor turn on or turn off. In the conventional GaN MISHEMT transistor (1000a or 100b), a gate
(116) is formed by various metal material as shown in the figure 1. Normally, a metal film re-forms or changes the property when undergo a high temperature (> 600C) thermal process, hence typical GaN MISHEMT process forms an ohmic contact (112) first before forming the transistor gate (116). This will limit the selection of the gate insulator film (110), due to ohmic contact cannot undergo high temperature insulator film deposition.
Referring to Figure 2a to Figure 2c, a conventional GaN MISHEMT fabrication sequence is illustrated. After an isolation region (108) is formed, a gate insulator film (110) have to be deposited first, followed by a formation of the ohmic contact metal (112). Then, a dielectric film (114) is deposited to isolate the ohmic contact metal (112) and subsequent gate metal (116), after that, a high selectivity etching (between the gate insulator film (110) and the dielectric film (114)) process is needed to etch away the gate metal (114) and stop on gate insulator film (110). Subsequently, proper cleaning is needed to minimize etch damage to the gate insulator film (110) before depositing the gate metal material (114).
SUMMARY OF THE INVENTION The present invention relates to a semiconductor apparatus. The semiconductor apparatus comprises a Gallium nitride (GaN) buffer and an Aluminium gallium nitride (AlGaN) barrier. A two-dimensional electron gas (2DEG) is formed between the GaN buffer and the AlGaN barrier. An isolation region is formed on at least one side portion of the 2DEG, the GaN buffer and the AlGaN barrier. A dielectric film is deposited on a portion of the isolation region and a portion of the AlGaN barrier. A gate insulation film is deposited on the dielectric film. A heavy doped poly silicon (Si) film is deposited on the gate insulation film. The dielectric film is deposited again on the gate insulation film and the heavy doped poly Si film followed by an ohmic contact opening to etch away the dielectric film and the gate insulation film to expose an ohmic contact area. At least one ohmic contact metal is deposited and patterned on a portion of the AlGaN barrier. The at least one ohmic contact metal is deposited and patterned on at least one of a portion of the dielectric film and a portion of the gate insulation film. In an embodiment, the heavy doped Poly Si film enables gate formation in the semiconductor apparatus before an ohmic contact formation process.
In an embodiment, the gate insulator film and the heavy doped Poly Si film are deposited after the dielectric film is etched away in a gate region of the semiconductor apparatus. In an embodiment, the gate insulator film and the highly doped Poly Si layer are deposited consecutively, so as to ensure a good interface quality between the gate insulator film and the highly doped poly Si layer.
In an embodiment, the semiconductor apparatus comprises a Gallium nitride high-electron-mobility transistor (GaN HEMT) device and a Gallium Nitride (GaN) Metal-Insulator-Semiconductor High Electron Mobility Transistor (MISHEMT) device.
In an embodiment, the semiconductor apparatus is compatible with an Si CMOS process. The present invention relates to a method for fabricating a semiconductor apparatus. The method includes providing the GaN buffer and an AlGaN barrier. Further, the method includes forming a 2DEG between the GaN buffer and the AlGaN barrier. Further, the method includes forming an isolation region on at least one side portion of the 2DEG, the GaN buffer and the AlGaN barrier. Further, the method includes depositing a dielectric film on a portion of the isolation region and a portion of the AlGaN barrier. Further, the method includes depositing a gate insulation film on the dielectric film. Further, the method includes depositing a heavy doped poly Si film deposited on the gate insulation film. The dielectric film is deposited again on the gate insulation film and the heavy doped poly Si film followed by an ohmic contact opening to etch away the dielectric film and the gate insulation film to expose an ohmic contact area. Further, the method includes depositing at least one ohmic contact metal and patterning on a portion of the AlGaN barrier. The at least one ohmic contact metal is deposited and patterned on at least one of a portion of the dielectric film and a portion of the gate insulation film.
BRIEF DESCRIPTION OF THE ACCOMPANYING DRAWINGS The present invention will be fully understood from the detailed description given herein below and the accompanying drawings which are given by way of illustration only, and thus are not limitative of the present invention, wherein:
Figure 1 illustrates a cross-sectional view of a conventional GaN MISHEMT device, in accordance with prior art.
Figure 2a to Figure 2c illustrate an example fabrication process of a conventional GaN MISHEMT device, in accordance with prior art.
Figure 3a to Figure 3d illustrate an example fabrication process of a GaN MISHEMT device, in accordance with one embodiment of the present invention. Figure 4 is an example flow chart illustrating a method for fabricating a
GaN MISHEMT device, according to one embodiment of the present invention.
DETAILED DESCRIPTION OF THE INVENTION Detailed description of preferred embodiments of the present invention is disclosed herein. It should be understood, however, that the embodiments are merely exemplary of the present invention, which may be embodied in various forms. Therefore, the details disclosed herein are not to be interpreted as limiting, but merely as the basis for the claims and for teaching one skilled in the art of the invention. The numerical data or ranges used in the specification are not to be construed as limiting. The following detailed description of the preferred embodiments will now be described in accordance with the attached drawings, either individually or in combination.
Accordingly, the embodiment herein is to provide a semiconductor apparatus comprising a GaN buffer and an AlGaN barrier. A 2DEG is formed between the GaN buffer and the AlGaN barrier. An isolation region is formed on at least one side portion of the 2DEG, the GaN buffer and the AlGaN barrier. A dielectric film is deposited on a portion of the isolation region and a portion of the AlGaN barrier. A gate insulation film is deposited on the dielectric film. A heavy doped poly silicon (Si) film is deposited on the gate insulation film. The dielectric film is deposited again on the gate insulation film and the heavy doped poly Si film followed by an ohmic contact opening to etch away the dielectric film and the gate insulation film to expose an ohmic contact area. At least one ohmic contact metal is deposited and patterned on a portion of the AlGaN barrier. The at least one ohmic contact metal is deposited and patterned on at least one of a portion of the dielectric film and a portion of the gate insulation film.
In the conventional methods, a metal film is used to form a transistor gate in a Gallium Nitride (GaN) Metal-Insulator-Semiconductor High Electron Mobility Transistor (MISHEMT). A gate metal is normally formed after source/drain ohmic contact formation due to the concern of high temperature anneal process for ohmic contact formation. In order to do a gate metal-first process, a special gate metal material is needed, which may not be Si CMOS fab compatible. An Si CMOS Fab proven material - Poly Si can be used for GaN MISHEMT gate formation, the Poly Si can be heavily doped to low sheet resistance, which has similar work function as a metal material. Hence, the proposed method will make GaN MISHEMT process fully compatible with the Si CMOS process.
Based on the proposed method, the gate formation of the semiconductor apparatus can be easily enabled, which helps to minimize high selectivity etch process requirement, improves gate leakage performance and enhances device reliability. The proposed method process is fully compatible with the standard Si CMOS process.
Referring now to the drawings and more particularly to Figure 3a through Figure 4, where similar reference characters denote corresponding features consistently throughout the figures, there are shown preferred embodiments.
Figure 3a to Figure 3d illustrate an example fabrication process of a semiconductor apparatus (3000), in accordance with one embodiment of the present invention. The semiconductor apparatus (3000) can be a Gallium nitride high-electron-mobility transistor (GaN HEMT) device and a GaN MISHEMT device.
Referring to Figure 3a to Figure 3d, the semiconductor apparatus (3000) includes a 2DEG (106) formed between the GaN buffer (102) and the AlGaN barrier (104). An isolation region (108) is formed on at least one side portion of the 2DEG (106), the GaN buffer (102) and the AlGaN barrier (104). A dielectric film (114) is deposited on a portion of the isolation region (108) and a portion of the AlGaN barrier (104). A gate insulation film (110) is deposited on the dielectric film (114). A heavy doped poly silicon (Si) film (118) is deposited on the gate insulation film (110). The dielectric film (114) is deposited again on the gate insulation film (110) and the heavy doped poly Si film (118) followed by an ohmic contact opening to etch away the dielectric film (114) and the gate insulation film (110) to expose an ohmic contact area. In an embodiment, the heavy doped Poly Si film (118) enables gate formation in the semiconductor apparatus (3000) before an ohmic contact formation process. The gate insulator film (110) and the heavy doped Poly Si film (118) are deposited after the dielectric film (114) is etched away in a gate region of the semiconductor apparatus (3000).
At least one ohmic contact metal (112) is deposited and patterned on a portion of the AlGaN barrier (104). The at least one ohmic contact metal (112) is deposited and patterned on at least one of a portion of the dielectric film (114) and a portion of the gate insulation film (110). The gate insulator film (110) and the highly doped Poly Si layer (118) are deposited consecutively, so as to ensure a good interface quality between the gate insulator film (110) and the highly doped poly Si layer (118). The fabrication of the semiconductor apparatus (3000) is compatible with an Si CMOS process. Based on the proposed method, the gate formation of the semiconductor apparatus (3000) can be easily enabled, which helps to minimize high selectivity etch process requirement, improves gate leakage performance and enhances device reliability. The proposed method can be used to eliminate a high selectivity (between the gate insulator film (110) and the dielectric film (114)) etch challenge and potential plasma etch damage to the gate insulator film (110), which improves gate leakage performance and device reliability.
Figure 4 is an example flow chart (S4000) illustrating a method for fabricating the GaN MISHEMT device, according to one embodiment of the present invention. At S402, the method includes providing the GaN buffer (102) and the AlGaN barrier (104). At S404, the method includes forming the 2DEG (106) between the GaN buffer (102) and the AlGaN barrier (104). At S406, the method includes forming the isolation region (108) on at least one side portion of the 2DEG (106), the GaN buffer (102) and the AlGaN barrier (104). At S408, the method includes depositing the dielectric film (114) on the portion of the isolation region (108) and the portion of the AlGaN barrier (104).
At S410, the method includes depositing the gate insulation film (110) on the dielectric film (114). At S412, the method includes depositing the heavy doped poly Si film (118) deposited on the gate insulation film (110). The dielectric film (114) is deposited again on the gate insulation film (110) and the heavy doped poly Si film (118) followed by an ohmic contact opening to etch away the dielectric film (114) and the gate insulation film (110) to expose an ohmic contact area. At S412, the method includes depositing at least one ohmic contact metal (112) and patterning on a portion of the AlGaN barrier (104). The at least one ohmic contact metal (112) is deposited and patterned on at least one of a portion of the dielectric film (114) and a portion of the gate insulation film (110).
In the conventional methods, a metal film is used to form a transistor gate in a Gallium Nitride (GaN) Metal-Insulator-Semiconductor High Electron Mobility Transistor (MISHEMT). A gate metal is normally formed after source/drain ohmic contact formation due to the concern of high temperature anneal process for ohmic contact formation. In order to do a gate metal-first process, a special gate metal material is needed, which may not be Si CMOS fab compatible. An Si CMOS Fab proven material - Poly Si can be used for GaN MISHEMT gate formation, the Poly Si can be heavily doped to low sheet resistance, which has similar work function as a metal material. Hence, the proposed method will make the GaN MISHEMT process fully compatible with the Si CMOS process. Based on the proposed method, the gate formation of the semiconductor apparatus can be easily enabled, which helps to minimize high selectivity etch process requirement, improves gate leakage performance and enhances device reliability.
The proposed method can be used to eliminate a high selectivity (between the gate insulator film (110) and the dielectric film (114)) etch challenge and potential plasma etch damage to gate insulator film (110), which will improve gate leakage performance and device reliability.
The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting. As used herein, the singular forms "a", "an" and "the" may be intended to include the plural forms as well, unless the context clearly indicates otherwise. The terms "comprises", "comprising", “including” and “having” are inclusive and therefore specify the presence of stated features, integers, steps, operations, elements and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and/or groups thereof. The method steps, processes and operations described herein are not to be construed as necessarily requiring their performance in the particular order discussed or illustrated, unless specifically identified as an order of performance. It is also to be understood that additional or alternative steps may be employed. The use of the expression “at least” or “at least one” suggests the use of one or more elements, as the use may be in one of the embodiments to achieve one or more of the desired objects or results.

Claims

CLAIMS We claim:
1. A semiconductor apparatus (3000), comprises: i. a Gallium nitride (GaN) buffer (102); ii. an Aluminum gallium nitride (AlGaN) barrier (104); iii. a two-dimensional electron gas (2DEG) (106) formed between the GaN buffer (102) and the AlGaN barrier (104); iv. an isolation region (108) formed on at least one side portion of the
2DEG (106), the GaN buffer (102) and the AlGaN barrier (104); characterized in that: v. a dielectric film (114) deposited on a portion of the isolation region (108) and a portion of the AlGaN barrier (104); vi. a gate insulation film (110) deposited on the dielectric film (114); vii. a heavy doped poly silicon (Si) film (118) deposited on the gate insulation film (110), wherein the dielectric film (114) is deposited again on the gate insulation film (110) and the heavy doped poly Si film (118) followed by an ohmic contact opening to etch away the dielectric film (114) and the gate insulation film (110) to expose an ohmic contact area; and viii. at least one ohmic contact metal (112) deposited and patterned on a portion of the AlGaN barrier (104), wherein at least one ohmic contact metal (112) is deposited and patterned on at least one of a portion of the dielectric film (114) and a portion of the gate insulation film (110).
2. The semiconductor apparatus (3000) as claimed in claim 1, wherein the heavy doped Poly Si film (118) enables gate formation in the semiconductor apparatus (3000) before an ohmic contact formation process.
3. The semiconductor apparatus (3000) as claimed in claim 1, wherein the gate insulator film (110) and the heavy doped Poly Si film (118) are deposited after the dielectric film (114) is etched away in a gate region of the semiconductor apparatus (3000).
4. The semiconductor apparatus (3000) as claimed in claim 1, wherein the gate insulator film (110) and the highly doped Poly Si layer (118) are deposited consecutively.
5. The semiconductor apparatus (3000) as claimed in claim 1, wherein semiconductor apparatus (3000) comprises a Gallium nitride high- electron-mobility transistor (GaN HEMT) device and a Gallium Nitride (GaN) Metal-Insulator-Semiconductor High Electron Mobility Transistor (MISHEMT) device.
6. The semiconductor apparatus (3000) as claimed in claim 1, wherein the fabrication of the semiconductor apparatus (3000) is compatible with a Si CMOS process.
7. A method for fabricating a semiconductor apparatus (3000), comprises: i. providing a Gallium nitride (GaN) buffer (102) and an Aluminum gallium nitride (AlGaN) barrier (104); ii. forming a two-dimensional electron gas (2DEG) (106) between the GaN buffer (102) and the AlGaN barrier (104); iii. forming an isolation region (108) on at least one side portion of the 2DEG (106), the GaN buffer (102) and the AlGaN barrier (104); characterized in that: iv. depositing a dielectric film (114) on a portion of the isolation region (108) and a portion of the AlGaN barrier (104); v. depositing a gate insulation film (110) on the dielectric film (114); vi. a heavy doped poly silicon (Si) film (118) deposited on the gate insulation film (110), wherein the dielectric film (114) is deposited again on the gate insulation film (110) and the heavy doped poly Si film (118) followed by an ohmic contact opening to etch away the dielectric film (114) and the gate insulation film (110) to expose an ohmic contact area; and vii. depositing at least one ohmic contact metal (112) and patterning on a portion of the AlGaN barrier (104), wherein at least one ohmic contact metal (112) is deposited and patterned on at least one of a portion of the dielectric film (114) and a portion of the gate insulation film (110).
8. The method as claimed in claim 7, wherein the heavy doped Poly Si film (118) enables gate formation in the semiconductor apparatus (3000) before an ohmic contact formation process.
9. The method as claimed in claim 7, wherein the gate insulator film (110) and the heavy doped Poly Si film (118) are deposited after the dielectric film (114) is etched away in a gate region of the semiconductor apparatus (3000).
10. The method as claimed in claim 7, wherein the gate insulator film (110) and the highly doped Poly Si layer (118) are deposited consecutively.
11. The method as claimed in claim 7, wherein semiconductor apparatus (3000) comprises a Gallium nitride high-electron-mobility transistor (GaN HEMT) device and a Gallium Nitride (GaN) Metal-Insulator- Semiconductor High Electron Mobility Transistor (MISHEMT) device.
12. The method as claimed in claim 7, wherein the fabrication of the semiconductor apparatus (3000) is compatible with an Si CMOS process.
PCT/SG2022/050005 2021-02-22 2022-01-04 Semiconductor apparatus and method for fabricating thereof WO2022177504A1 (en)

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US20140061659A1 (en) * 2012-09-05 2014-03-06 James A. Teplik GaN Dual Field Plate Device with Single Field Plate Metal
US20140183598A1 (en) * 2012-12-28 2014-07-03 Taiwan Semiconductor Manufacturing Company, Ltd. High electron mobility transistor and method of forming the same
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* Cited by examiner, † Cited by third party
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US20150295076A1 (en) * 2011-06-20 2015-10-15 Imec Cmos compatible method for manufacturing a hemt device and the hemt device thereof
KR20130004707A (en) * 2011-07-04 2013-01-14 삼성전기주식회사 Nitride semiconductor device, manufacturing method thereof and nitride semiconductor power device
US20140061659A1 (en) * 2012-09-05 2014-03-06 James A. Teplik GaN Dual Field Plate Device with Single Field Plate Metal
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