WO2022174421A1 - Method of preparing passivating contacts and method of producing photovoltaic device with n-type polycrystalline silicon passivating contact - Google Patents

Method of preparing passivating contacts and method of producing photovoltaic device with n-type polycrystalline silicon passivating contact Download PDF

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WO2022174421A1
WO2022174421A1 PCT/CN2021/077086 CN2021077086W WO2022174421A1 WO 2022174421 A1 WO2022174421 A1 WO 2022174421A1 CN 2021077086 W CN2021077086 W CN 2021077086W WO 2022174421 A1 WO2022174421 A1 WO 2022174421A1
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layer
silicon layer
phosphorus
doped
polycrystalline silicon
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Xinbo YANG
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Soochow University
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/186—Particular post-treatment for the devices, e.g. annealing, impurity gettering, short-circuit elimination, recrystallisation
    • H01L31/1872—Recrystallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0224—Electrodes
    • H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • H01L31/022441—Electrode arrangements specially adapted for back-contact solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
    • H01L31/072—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type
    • H01L31/0745—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic Table

Definitions

  • the present invention relates to the technical field of passivating contacts, and more particularly to a method for preparing passivating contacts and method for producing a photovoltaic device with n-type polycrystalline silicon passivating contact.
  • High quality passivating contacts effectively passivate the c-Si surface at both contact and non-contact regions, and selectively extract one type of charge carriers (e.g., the holes) , while blocking the opposite type (e.g., the electrons) .
  • effective passivating contacts should also offer a suitably low contact resistivity and enable one-dimensional carrier extraction.
  • passivating contact technology eliminates the classic high temperature doping and contact patterning steps, and significantly reduces carrier recombination losses in both the contact and non-contact regions as well as series resistance, resulting in a high open circuit voltage (V oc ) and fill factor (FF) and a low process complexity as well.
  • Advanced passivating contacts have boosted the power conversion efficiency of c-Si solar cell over 26%, getting close to its theoretical limit.
  • POLO polycrystalline silicon on oxide
  • the thin silicon oxide typically 1-2 nm
  • the thin silicon oxide is grown thermally or chemically, permitting efficient tunneling of charge carriers (electrons or holes) .
  • silicon layer typically 5-300 nm
  • PECVD plasma-enhanced chemical vapor deposition
  • LPCVD low-pressure chemical vapor deposition
  • physical vapor deposition e.g., sputtering, thermal evaporation
  • An excellent surface passivation (typically contact recombination current density J 0c : 5-20 fA/cm 2 ) and a very low contact resistivity (typically ⁇ c : 5-20 m ⁇ . cm 2 ) can be achieved simultaneously after thermal annealing in nitrogen atmosphere (typically 800-1000°C for 30 mins) .
  • the electron or hole selectivity of POLO is determined by the doping elements, for example, phosphorus doping for electron selectivity and boron doping for hole selectivity.
  • Phosphorus-or boron-doping can be achieved in situ during silicon layer deposition by either PECVD or LPCVD, using a doping gas of diborane (boron doping) or phosphine (phosphorus doping) .
  • An alternative method is to introduce the dopant by an extra step after un-doped silicon layer deposition, for example, by thermal diffusion with a dopant gas or ion implantation.
  • the phosphine and diborane gas for common use are expensive and toxic, which requires strict safety control and careful handling for health and safety related concerns. Whereas doping by thermal diffusion or ion implantation involves capital-intensive equipment and complex processing, which inevitably increase the processing cost.
  • the purpose of the present invention is to provide a method of preparing high quality n-type polycrystalline passivating contacts by a simple, low-cost phosphorus acid solution doping, eliminating use of capital-intensive equipment and toxic phosphine gas.
  • a method of preparing passivating contact comprising steps of: growing a tunnel layer on the substrate and depositing an un-doped silicon layer on the tunnel layer; coating the un-doped silicon layer using phosphorus acid solution; performing thermal annealing to activate the phosphorus doping and converting the un-doped silicon layer to a phosphorus doped polycrystalline silicon layer.
  • the phosphorus acid solution is concentrated or diluted phosphorus acid.
  • the coating is direct dipping, spin coating, spraying or brush painting.
  • the tunnel layer is selected from the group consisting of a silicon oxide layer, a silicon nitride layer, a titanium oxide layer, an aluminum oxide layer and any combination thereof.
  • the un-doped silicon layer is deposited by chemical vapor deposition or physical vapor deposition.
  • the thermal annealing is performed in the temperature rangeof 650 °C to 1000 °C in nitrogen or forming gas atmosphere.
  • the forming gas is a mixture of nitrogen and hydrogen.
  • the method further comprises steps of: depositing a dielectric capping layer on the phosphorus doped polycrystalline silicon layer; and performing thermal annealing.
  • the dielectric capping layer is selected from the group consisting of a silicon nitride layer, a titanium oxide layer, an aluminum oxide layer, a silicon oxide layer and any combination thereof.
  • the thermal annealing is performed in the temperature rangeof 200 °C to 500 °C in nitrogen or forming gas atmosphere.
  • the forming gas is a mixture of nitrogen and hydrogen.
  • the invention also provides a method of producing a photovoltaic device with n-type polycrystalline silicon passivating contact, comprising the following steps: growing an un-doped silicon layer on a semiconductor substrate; coating the un-doped silicon layer using phosphorus acid solution; performing thermal annealing to activate phosphorus doping and converting the un-doped silicon layer to a phosphorus doped polycrystalline silicon layer; wherein the semiconductor substrate is a silicon wafer with a dielectric tunnel layer.
  • the invention also provides a method of producing a photovoltaic device with n-type polycrystalline silicon passivating contact, comprising steps of: growing an un-doped silicon layer on a semiconductor substrate; coating the un-doped silicon layer using phosphorus acid solution; performing thermal annealing to activate the phosphorus doping and converting the un-doped silicon layer to a phosphorus doped polycrystalline silicon layer; depositing a dielectric capping layer on the phosphorus doped polycrystalline silicon layer; performing thermal annealing; wherein the semiconductor substrate is a silicon wafer with a dielectric tunnel layer.
  • FIG. 1A is a fabrication sequence of n-type polycrystalline silicon passivating contacts using phosphorus acid solution doping according to an embodiment
  • FIG. 1B is a fabrication sequence of n-type polycrystalline silicon passivating contacts with a dielectric capping layer using phosphorus acid solution doping according to an embodiment
  • FIG. 2 is a graph illustrating the recombination current density (J 0c ) of n-type polycrystalline silicon passivating contacts as a function of thermal annealing temperature in nitrogen atmosphere;
  • FIG. 3 is a graph illustrating the contact resistivity ( ⁇ c ) of n-type polycrystalline silicon passivating contacts as a function of thermal annealing temperature in nitrogen atmosphere;
  • FIG. 4 is a graph illustrating the J 0c and the ⁇ c of n-type polycrystalline silicon passivating contacts as a function of un-doped silicon layer thickness
  • FIG. 5 is a graph illustrating the J 0c of n-type polycrystalline silicon passivating contacts as a function of dipping time in the high concentrated phosphorus acid ( ⁇ 85%) ;
  • FIG. 6 is a graph illustrating the J 0c of n-type polycrystalline silicon passivating contacts as a function of thermal annealing temperature in nitrogen atmosphere.
  • FIG. 7 is a schematic diagrams of the first silicon-based photovoltaic devices featuring an n-type polycrystalline passivating contact prepared by the method described herein at the rear side for electron collection;
  • FIG. 8 is a schematic diagrams of the second silicon-based photovoltaic devices featuring an n-type polycrystalline passivating contact prepared by the method described herein at the rear side for electron collection;
  • FIG. 9 is a schematic diagrams of the third silicon-based photovoltaic devices featuring an n-type polycrystalline passivating contact prepared by the method described herein at the front side for electron collection;
  • FIG. 10 is a schematic diagrams of the fourth silicon-based photovoltaic devices featuring an n-type polycrystalline passivating contact prepared by the method described herein at the front side for electron collection;
  • Figures 11 is a schematic diagram of silicon-based interdigitated back-contact devices featuring an n-type polycrystalline passivating contact prepared by the method described herein for electron collection.
  • FIG. 1A is a fabrication sequence of n-type polycrystalline silicon passivating contacts using phosphorus acid solution doping according to an embodiment.
  • the method of preparing passivating contact comprising steps of: growing a tunnel layer 102 on the substrate 101and depositing an un-doped silicon layer103 on the tunnel layer 102; coating the un-doped silicon layer 103 using phosphorus acid solution 104; performing thermal annealing to activate the phosphorus doping and converting the un-doped silicon layer 103 to a phosphorus doped polycrystalline silicon layer 105.
  • the tunnel layer 102 is grown on the semiconductor substrate 101 embodied as a monocrystalline silicon substrate.
  • the tunnel layer is selected from the group consisting of a silicon oxide layer, a silicon nitride layer, a titanium oxide layer, an aluminum oxide layer and any combination thereof.
  • the tunnel layer 102 may be grown by chemical or thermal oxidation, PECVD or atomic layer deposition (ALD) , featuring a thickness of 1 to 5 nm, preferably to 1-2 nm for effective tunneling of charge carriers.
  • the un-doped silicon layer 103 may be deposited by chemical vapor deposition or physical vapor deposition (e.g., PECVD, LPCVD, APCVD, sputtering) .
  • the thickness of the un-doped silicon layer 103 ranges from 5 to 300 nm, and preferably 20-200 nm.
  • Doping of un-doped silicon layer 103 is achieved by coating the silicon layer with phosphorus acid solution 104, and subsequently a thermal annealing in nitrogen or foaming gas atmosphere is applied.
  • the phosphorus acid solution may be high concentration (up to 85%) or diluted phosphorus acid using various diluents (e.g., water, methyl alcohol, ethyl alcohol, n-butyl alcohol, etc. ) , featuring a typical concentration from 5%to 85%.
  • the phosphorus acid solution coating methods may be direct dipping, spin coating, spraying or brush painting.
  • a thermal annealing is performed to activate the phosphorus doping and convert the un-doped silicon layer 103 to phosphorus doped polycrystalline silicon layer 105.
  • the annealing temperature ranges from 700-1000°C, preferably 800-900°C.
  • the thermal annealing may be conducted in a tube furnace or a rapid thermal annealing furnace.
  • the phosphorus element may diffuse through the tunnel layer 102, resulting in a slight doping of the substrate surface.
  • Figure 1B is a fabrication sequence of n-type polycrystalline silicon passivating contacts using phosphorus acid solution doping according to another embodiment.
  • the method includes extra steps of depositing another dielectric capping layer 106 on phosphorus doped polycrystalline silicon layer 105, and another thermal annealing is performed to favorite the hydrogen diffusion from the dielectric capping layer 106 to the passivating contact, reducing the J 0c of the n-type polycrystalline silicon passivating contact.
  • the dielectric capping layer 106 is selected from the group consisting of a silicon nitride layer, a titanium oxide layer, an aluminum oxide layer, a silicon oxide layer and any combination thereof.
  • the dielectric capping layer 106 may be deposited by PECVD, ALD, APCVD, LPCVD, featuring a typically thickness of 5-200 nm. Subsequently another thermal annealing (typically 200°C-500°C) is applied for hydrogen diffusion from the dielectric capping layer 106 into the phosphorus doped polycrystalline silicon layer 105 and the interface between tunnel layer 102 and semiconductor substrate 101, passivating the defects and achieving a low carrier recombination velocity at the interfaces.
  • PECVD PECVD
  • ALD atomic layer
  • APCVD LPCVD
  • phosphorus acid solution doping for preparing n-type polycrystalline silicon passivating contacts is particularly advantageous because this method is can achieve excellent passivating contact properties (J 0c and ⁇ c ) with a safe, simple and low-cost processing.
  • Figure 2 and 3 are graphs illustrating the J 0c and ⁇ c of n-type polycrystalline silicon passivating contacts as a function of thermal annealing temperature in nitrogen atmosphere.
  • phosphorus acid solution 104 coating on un-doped silicon layer 103 (50 nm) is achieved by directly dipping in high concentrated phosphorus acid ( ⁇ 85%) for 2 mins;
  • the dielectric capping layer 106 is SiNx (75 nm) deposited by PECVD, and subsequently thermal annealing is performed at 420°C for 30 mins in the forming gas atmosphere.
  • Fig. 1 phosphorus acid solution 104 coating on un-doped silicon layer 103 (50 nm) is achieved by directly dipping in high concentrated phosphorus acid ( ⁇ 85%) for 2 mins
  • the dielectric capping layer 106 is SiNx (75 nm) deposited by PECVD, and subsequently thermal annealing is performed at 420°C for 30 mins in the forming gas atmosphere.
  • the n-type polycrystalline silicon passivating contacts consist of a dielectric tunnel layer SiOx (1.5 nm) and a silicon layer (50 nm) doped by phosphorus acid ( ⁇ 85%) dipping for 2 mins.
  • Phosphorus acid doping of the un-doped silicon layer 103 (50 nm) is achieved by directly dipping in high concentrated phosphorus acid ( ⁇ 85%) for 2 mins, and subsequently thermal annealing is performed at different temperatures for 25 mins in the nitrogen atmosphere.
  • a low J 0c of 30 fA/cm 2 and low ⁇ c of 18 m ⁇ . cm 2 are achieved simultaneously with an optimal annealing temperature of 860°C.
  • the J 0c is further reduced to 15 fA/cm 2 .
  • the two key parameters, J 0c and ⁇ c , of the n-type polycrystalline silicon passivating contacts achieved by phosphorus acid solution doping are comparable to that of in situ doping, phosphine gas diffusion, and ion implantation.
  • FIG 4 is a graph illustrating the J 0c and the ⁇ c of n-type polycrystalline silicon passivating contacts as a function of un-doped silicon layer thickness.
  • phosphorus acid solution 104 coating on un-doped silicon layer 103 is achieved by directly dipping in high concentrated phosphorus acid ( ⁇ 85%) for 2 mins. The thermal annealing is performed at 860°C for 25 mins in nitrogen atmosphere. Specifically, all the samples experienced a dipping in high concentrated phosphorus acid (85%) for 2 mins and subsequently thermal annealing at 860°C for 25 mins in nitrogen atmosphere.
  • cm 2 is achieved on the passivating contact with an un-doped silicon layer thickness ⁇ 100 nm, which meets the prerequisite for high-efficiency silicon solar cells. It is also possible to achieve a better J 0c and ⁇ c values on n-type polycrystalline silicon passivating contacts with a thick un-doped silicon layer using a higher annealing temperature.
  • Figure 5 is a graph illustrating the J 0c of n-type polycrystalline silicon passivating contacts as a function of dipping time in the concentrated phosphorus acid (85%) .
  • all the samples consist of a dielectric tunnel layer SiOx (1.5 nm) and a silicon layer (50 nm) , and experienced the same thermal annealing at 860°C for 25 mins in nitrogen atmosphere.
  • all the samples consist of a dielectric tunnel layer SiOx (1.5 nm) and an un-doped silicon layer (50 nm) , and subsequently experienced the same thermal annealing at 860°C for 25 mins in nitrogen atmosphere.
  • a low J 0c ⁇ 35 fA/cm 2 is achieved with a dipping time from 1 to 180 mins, demonstrating a short processing time and high flexibility of the phosphorus acid solution doping process.
  • Figure 6 is a graph illustrating the J 0c of n-type polycrystalline silicon passivating contacts as a function of thermal annealing temperature in nitrogen atmosphere.
  • high concentrated phosphorus acid ⁇ 85%
  • n-butyl alcohol 50%n-butyl alcohol: 50%H 3 PO 4
  • spin coating 4000 RPM for 45s
  • SiNx capping layer is deposited by PECVD and forming gas annealing at 420°C for 30 mins is applied.
  • phosphorus acid doping is performed by spin coating n-butyl alcohol diluted phosphorus acid (50%n-butyl alcohol: 50%H 3 PO 4 ) , and subsequently experienced a thermal annealing at different temperatures for 30mins. A SiNx capping layer and then FGA at 420°C for 30 mins is applied. It can be seen that a low J 0c ⁇ 50 fA/cm 2 is achieved in a wide range of thermal annealing temperature of 800 to 900°C, featuring a very low J 0c of 10 fA/cm 2 with an optimal annealing temperature of 860°C.
  • n-type polycrystalline silicon passivating contacts with good J 0c and ⁇ c can be prepared using phosphorus acid solution dipping, using a board range of annealing temperature, un-doped silicon layer thickness, phosphorus acid coating time and methods.
  • phosphorus acid solution doping for n-type polycrystalline silicon passivating contacts offer significant advantages in terms of simplicity, high safety, and low cost.
  • the invention also provides a method of producing a photovoltaic device with n-type polycrystalline silicon passivating contact, comprising steps of: growing an un-doped silicon layer on a semiconductor substrate; coating the un-doped silicon layer using phosphorus acid solution; performing thermal annealing to activate phosphorus doping and converting the un-doped silicon layer to a phosphorus doped polycrystalline silicon layer; wherein the semiconductor substrate is a silicon wafer with a dielectric tunnel layer.
  • the invention also provides a method of producing a photovoltaic device with n-type polycrystalline silicon passivating contact, comprising steps of: growing an un-doped silicon layer on a semiconductor substrate; coating the un-doped silicon layer using phosphorus acid solution; performing thermal annealing to activate the phosphorus doping and converting the un-doped silicon layer to a phosphorus doped polycrystalline silicon layer; depositing a dielectric capping layer on the phosphorus doped polycrystalline silicon layer; performing thermal annealing; wherein the semiconductor substrate is a silicon wafer with a dielectric tunnel layer.
  • the photovoltaic device illustrated in Figure 7 features passivating contacts on both sides.
  • a phosphorus acid solution doped n-type polycrystalline silicon passivating contact is applied at the rear for electron collection, consists of a first tunnel oxide 701 and a first n-type polycrystalline silicon layer 702, capped with a first rear electrode 703.
  • the front side of the device includes a p-type polycrystalline silicon passivating contact adjacent to a first n-type silicon substrate 704, consists of a first tunnel oxide 705 and a boron doped first polycrystalline silicon layer 706, capped with tin doped indium oxide (ITO) first window layer 707.
  • a first front electrode 708 is directly applied on the oxide (ITO) first window layer 707.
  • the photovoltaic device illustrated in Figure 8 also figures a phosphorus acid solution doped n-type polycrystalline silicon passivating contact (asecond tunnel oxide 801, a second n-type polycrystalline silicon 802) at the rear side for electron collection, which is capped by a second SiNx layer 803.
  • the second tunnel oxide 801 may be SiOx.
  • a second rear electrode 804 is adjacent to the second n-type polycrystalline silicon 802 through the second SiNx layer 803.
  • the front side figures a second boron diffused p+emitter 805 for hole collection on a second n-type silicon substrate 806, which is passivated by a second Al 2 O 3 807 and a second SiNx 808 stack.
  • the second Al 2 O 3 807 may be deposited by ALD or PECVD, with a typically thickness of 5-50 nm, and the second SiNx 808 may be deposited by PECVD, with a typically thickness of 25-75 nm.
  • a second front electrode 809 is applied through Al 2 O 3 /SiNx stack.
  • the photovoltaic device illustrated in Figure 9 includes a phosphorus acid solution doped n-type polycrystalline silicon passivating contact at the front and a boron doped p-type polycrystalline silicon passivating contact at the rear side.
  • p-type silicon substrate 901 is sandwiched between n-type (902 and 903) and p-type (905 and 906) polycrystalline silicon passivating contacts, both capped with ITO layer (a second window layer 907 and a third window layer 908) .
  • a third front electrode 909 and third rear electrode 9010 are applied on ITO directly.
  • the photovoltaic device illustrated in Figure 10 features a third boron diffused p+emitter 1001 at the rear side of a third n-type silicon substrate 1002, which is passivated by a third Al 2 O 3 1003 and a third SiNx 1004 stack.
  • a phosphorus acid solution doped n-type polycrystalline silicon passivating contact is applied at the front side for electron collection, consists of a third tunnel oxide 1005 and a phosphorus doped third polycrystalline silicon layer 1006, capped with an ITO layer 1007.
  • a fourth front electrode 1008 and a fourth rear electrode 1009 are formed on ITO and through Al 2 O 3 /SiNx stack, respectively.
  • the photovoltaic device illustrated in Figure 11 is an interdigitated back-contact silicon device with both n-type and p-type polycrystalline silicon passivating contacts at the rear side.
  • the interdigitated back-contact structure includes a first electrode 1101 directly adjacent to a n-type polycrystalline silicon passivating contact consists of a fifth tunnel oxide 1102 and a fifth n-type polycrystalline silicon layer 1103, and a second electrode 1104 directly adjacent to p-type polycrystalline silicon passivating contact consists of SiOx 1102 and p-type polycrystalline silicon layer 1105.
  • the fifth tunnel oxide may be SiOx.
  • the front side of the device is passivated by a fifth SiNx layer 1106, which is directly adjacent to a fifth n-type silicon substrate 1107.
  • the disclosed phosphorus acid solution doped n-type silicon layer can be used in a wide variety of electronic devices, including bipolar transistors, light emitting diodes, or any other type of electronic device where phosphorus doped silicon layer is desirable.
  • the disclosed embodiments provide a method to prepare n-type polycrystalline silicon passivating contacts using phosphorus acid solution doping and methods for producing photovoltaic devices having an n-type polycrystalline silicon passivating contact. It should be understood that this description is not intended to limit the invention. On the contrary, the exemplary embodiments are intended to cover alternatives, modifications and equivalents, which are included in the spirit and scope of the invention as defined by the appended claims. Further, in the detailed description of the exemplary embodiments, numerous specific details are set forth in order to provide a comprehensive understanding of the claimed invention. However, one skilled in the art would understand that various embodiments may be practiced without such specific details.

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Abstract

A method of preparing passivating contact and method of producing a photovoltaic device with n-type polycrystalline silicon passivating contact are provided, comprising steps of: growing a tunnel layer (102) on a substrate (101) and depositing an un-doped silicon layer (103) on the tunnel layer (102); coating the un-doped silicon layer (103) using phosphorus acid solution (104); and performing thermal annealing to activate the phosphorus doping and converting the un-doped silicon layer (103) to a phosphorus doped polycrystalline silicon layer (105). The method is particularly advantageous in preparing n-type polycrystalline silicon passivating contacts by using phosphoric acid solution (104), and the method can achieve excellent passivating contact performance with a safe, simple and low-cost process.

Description

A Method of Preparing Passivating Contacts and Method of Producing a Photovoltaic Device with N-type Polycrystalline Silicon Passivating Contact FIELD OF THE INVENTION
The present invention relates to the technical field of passivating contacts, and more particularly to a method for preparing passivating contacts and method for producing a photovoltaic device with n-type polycrystalline silicon passivating contact.
DESCRIPTION OF THE RELATED ART
With the increasing electronic quality of silicon wafers, the high carrier recombination losses at the metal-silicon contact regions have been identified as the main limitation for achieving a high efficiency on crystalline silicon (c-Si) solar cells. High quality passivating contacts effectively passivate the c-Si surface at both contact and non-contact regions, and selectively extract one type of charge carriers (e.g., the holes) , while blocking the opposite type (e.g., the electrons) . In the meantime, effective passivating contacts should also offer a suitably low contact resistivity and enable one-dimensional carrier extraction. Therefore, passivating contact technology eliminates the classic high temperature doping and contact patterning steps, and significantly reduces carrier recombination losses in both the contact and non-contact regions as well as series resistance, resulting in a high open circuit voltage (V oc) and fill factor (FF) and a low process complexity as well. Advanced passivating contacts have boosted the power conversion efficiency of c-Si solar cell over 26%, getting close to its theoretical limit.
One of the most successful passivating contact technologies is called polycrystalline silicon on oxide (POLO) , which consists of a stack of thin silicon oxide and doped polycrystalline silicon layer. The thin silicon oxide (typically 1-2 nm) is grown thermally or chemically, permitting efficient tunneling of charge carriers (electrons or holes) . Usually, silicon layer (typically 5-300 nm) is deposited by plasma-enhanced chemical vapor deposition (PECVD) , low-pressure chemical vapor deposition (LPCVD) , or physical vapor deposition (e.g., sputtering, thermal evaporation) . An excellent surface passivation (typically contact recombination current density J 0c: 5-20 fA/cm 2) and a very low contact resistivity (typically ρ c: 5-20 mΩ. cm 2) can be achieved simultaneously after thermal annealing in nitrogen atmosphere (typically 800-1000℃ for 30 mins) . The electron or hole selectivity of POLO is determined by the doping elements, for example, phosphorus doping for electron selectivity and boron doping for hole selectivity. Phosphorus-or boron-doping can be achieved in situ during silicon layer deposition by either PECVD or LPCVD, using a doping gas of diborane (boron doping) or phosphine (phosphorus doping) . An alternative method is to introduce the dopant by an extra step after un-doped silicon layer deposition, for example, by thermal diffusion with a dopant gas or ion implantation. The phosphine and diborane gas for common use are expensive and toxic, which requires strict safety control and careful handling for health and safety related concerns. Whereas doping by thermal diffusion or ion implantation involves capital-intensive equipment and complex processing, which inevitably increase the processing cost.
Therefore, there is a need for preparing high quality passivating contacts with an effective and simple doping method of silicon layer, and hence reduce the processing cost of silicon solar cells with passivating  contacts.
SUMMARY OF THE INVENTION
In view of this, the purpose of the present invention is to provide a method of preparing high quality n-type polycrystalline passivating contacts by a simple, low-cost phosphorus acid solution doping, eliminating use of capital-intensive equipment and toxic phosphine gas.
According to an embodiment, there is a method of preparing passivating contact, comprising steps of: growing a tunnel layer on the substrate and depositing an un-doped silicon layer on the tunnel layer; coating the un-doped silicon layer using phosphorus acid solution; performing thermal annealing to activate the phosphorus doping and converting the un-doped silicon layer to a phosphorus doped polycrystalline silicon layer.
Preferably, the phosphorus acid solution is concentrated or diluted phosphorus acid.
Preferably, the coating is direct dipping, spin coating, spraying or brush painting.
Preferably, the tunnel layer is selected from the group consisting of a silicon oxide layer, a silicon nitride layer, a titanium oxide layer, an aluminum oxide layer and any combination thereof.
Preferably, the un-doped silicon layer is deposited by chemical vapor deposition or physical vapor deposition.
Preferably, the thermal annealing is performed in the temperature rangeof 650 ℃ to 1000 ℃ in nitrogen or forming gas atmosphere.
Preferably, the forming gas is a mixture of nitrogen and hydrogen.
Preferably, the method further comprises steps of: depositing a dielectric capping layer on the phosphorus doped polycrystalline silicon  layer; and performing thermal annealing.
Preferably, the dielectric capping layer is selected from the group consisting of a silicon nitride layer, a titanium oxide layer, an aluminum oxide layer, a silicon oxide layer and any combination thereof.
Preferably, the thermal annealing is performed in the temperature rangeof 200 ℃ to 500 ℃ in nitrogen or forming gas atmosphere.
Preferably, the forming gas is a mixture of nitrogen and hydrogen.
The invention also provides a method of producing a photovoltaic device with n-type polycrystalline silicon passivating contact, comprising the following steps: growing an un-doped silicon layer on a semiconductor substrate; coating the un-doped silicon layer using phosphorus acid solution; performing thermal annealing to activate phosphorus doping and converting the un-doped silicon layer to a phosphorus doped polycrystalline silicon layer; wherein the semiconductor substrate is a silicon wafer with a dielectric tunnel layer.
The invention also provides a method of producing a photovoltaic device with n-type polycrystalline silicon passivating contact, comprising steps of: growing an un-doped silicon layer on a semiconductor substrate; coating the un-doped silicon layer using phosphorus acid solution; performing thermal annealing to activate the phosphorus doping and converting the un-doped silicon layer to a phosphorus doped polycrystalline silicon layer; depositing a dielectric capping layer on the phosphorus doped polycrystalline silicon layer; performing thermal annealing; wherein the semiconductor substrate is a silicon wafer with a dielectric tunnel layer.
BRIEF DESCRIPTION OF THE DRAWINGS
For clearer explanation of the embodiments of the present invention or the technical solutions from the prior art, the drawings needed in description of the embodiments or the prior art will be described briefly in the following. It is apparent that the drawings described below illustrate only the embodiment of the present invention. Other drawings can be achieved based on the presented drawings by a person of ordinary skill in the art without creative efforts.
FIG. 1A is a fabrication sequence of n-type polycrystalline silicon passivating contacts using phosphorus acid solution doping according to an embodiment; and
FIG. 1B is a fabrication sequence of n-type polycrystalline silicon passivating contacts with a dielectric capping layer using phosphorus acid solution doping according to an embodiment; and
FIG. 2 is a graph illustrating the recombination current density (J 0c) of n-type polycrystalline silicon passivating contacts as a function of thermal annealing temperature in nitrogen atmosphere; and
FIG. 3 is a graph illustrating the contact resistivity (ρ c) of n-type polycrystalline silicon passivating contacts as a function of thermal annealing temperature in nitrogen atmosphere; and
FIG. 4 is a graph illustrating the J 0c and the ρ c of n-type polycrystalline silicon passivating contacts as a function of un-doped silicon layer thickness; and
FIG. 5 is a graph illustrating the J 0c of n-type polycrystalline silicon passivating contacts as a function of dipping time in the high concentrated phosphorus acid (～85%) ; and
FIG. 6 is a graph illustrating the J 0c of n-type polycrystalline silicon passivating contacts as a function of thermal annealing temperature in  nitrogen atmosphere; and
FIG. 7 is a schematic diagrams of the first silicon-based photovoltaic devices featuring an n-type polycrystalline passivating contact prepared by the method described herein at the rear side for electron collection; and
FIG. 8 is a schematic diagrams of the second silicon-based photovoltaic devices featuring an n-type polycrystalline passivating contact prepared by the method described herein at the rear side for electron collection; and
FIG. 9 is a schematic diagrams of the third silicon-based photovoltaic devices featuring an n-type polycrystalline passivating contact prepared by the method described herein at the front side for electron collection; and
FIG. 10 is a schematic diagrams of the fourth silicon-based photovoltaic devices featuring an n-type polycrystalline passivating contact prepared by the method described herein at the front side for electron collection; and
Figures 11 is a schematic diagram of silicon-based interdigitated back-contact devices featuring an n-type polycrystalline passivating contact prepared by the method described herein for electron collection.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
The following description of the embodiments refers to the accompanying drawings. The same reference numbers in different drawings identify the same or similar elements. The following detailed description does not limit the invention. Instead, the scope of the invention is defined by the appended claims. The following embodiments are discussed, for simplicity, with regard to the terminology and structure of n-type polycrystalline silicon passivating contact.
Reference throughout the specification to “one embodiment” or “an embodiment” means that a particular feature, structure or characteristic  described in connection with an embodiment is included in at least one embodiment of the subject matter disclosed. Thus, the appearance of the phrases “in one embodiment” or “in an embodiment” in various places throughout the specification is not necessarily referring to the same embodiment. Further, the particular features, structures or characteristics may be combined in any suitable manner in one or more embodiments.
The invention provides a method to prepare n-type polycrystalline silicon passivating contact using phosphorus acid solution doping. Figure 1A is a fabrication sequence of n-type polycrystalline silicon passivating contacts using phosphorus acid solution doping according to an embodiment. The method of preparing passivating contact, comprising steps of: growing a tunnel layer 102 on the substrate 101and depositing an un-doped silicon layer103 on the tunnel layer 102; coating the un-doped silicon layer 103 using phosphorus acid solution 104; performing thermal annealing to activate the phosphorus doping and converting the un-doped silicon layer 103 to a phosphorus doped polycrystalline silicon layer 105.
Wherein the tunnel layer 102 is grown on the semiconductor substrate 101 embodied as a monocrystalline silicon substrate. The tunnel layer is selected from the group consisting of a silicon oxide layer, a silicon nitride layer, a titanium oxide layer, an aluminum oxide layer and any combination thereof. The tunnel layer 102 may be grown by chemical or thermal oxidation, PECVD or atomic layer deposition (ALD) , featuring a thickness of 1 to 5 nm, preferably to 1-2 nm for effective tunneling of charge carriers. The un-doped silicon layer 103, maybe amorphous, microcrystalline or carbonated, may be deposited by chemical vapor deposition or physical vapor deposition (e.g., PECVD, LPCVD, APCVD, sputtering) . The thickness of the un-doped silicon layer 103 ranges from 5 to 300 nm, and preferably  20-200 nm.
Doping of un-doped silicon layer 103 is achieved by coating the silicon layer with phosphorus acid solution 104, and subsequently a thermal annealing in nitrogen or foaming gas atmosphere is applied. The phosphorus acid solution may be high concentration (up to 85%) or diluted phosphorus acid using various diluents (e.g., water, methyl alcohol, ethyl alcohol, n-butyl alcohol, etc. ) , featuring a typical concentration from 5%to 85%. The phosphorus acid solution coating methods may be direct dipping, spin coating, spraying or brush painting. Subsequently, a thermal annealing is performed to activate the phosphorus doping and convert the un-doped silicon layer 103 to phosphorus doped polycrystalline silicon layer 105. The annealing temperature ranges from 700-1000℃, preferably 800-900℃. The thermal annealing may be conducted in a tube furnace or a rapid thermal annealing furnace. During the thermal annealing step, the phosphorus element may diffuse through the tunnel layer 102, resulting in a slight doping of the substrate surface.
In another embodiment, Figure 1B is a fabrication sequence of n-type polycrystalline silicon passivating contacts using phosphorus acid solution doping according to another embodiment. The method includes extra steps of depositing another dielectric capping layer 106 on phosphorus doped polycrystalline silicon layer 105, and another thermal annealing is performed to favorite the hydrogen diffusion from the dielectric capping layer 106 to the passivating contact, reducing the J 0c of the n-type polycrystalline silicon passivating contact. The dielectric capping layer 106 is selected from the group consisting of a silicon nitride layer, a titanium oxide layer, an aluminum oxide layer, a silicon oxide layer and any combination thereof. The dielectric capping layer 106 may be deposited by PECVD, ALD,  APCVD, LPCVD, featuring a typically thickness of 5-200 nm. Subsequently another thermal annealing (typically 200℃-500℃) is applied for hydrogen diffusion from the dielectric capping layer 106 into the phosphorus doped polycrystalline silicon layer 105 and the interface between tunnel layer 102 and semiconductor substrate 101, passivating the defects and achieving a low carrier recombination velocity at the interfaces.
Using phosphorus acid solution doping for preparing n-type polycrystalline silicon passivating contacts is particularly advantageous because this method is can achieve excellent passivating contact properties (J 0c and ρ c) with a safe, simple and low-cost processing.
Specifically, as illustrated in Figure 2 and 3, which are graphs illustrating the J 0c and ρ c of n-type polycrystalline silicon passivating contacts as a function of thermal annealing temperature in nitrogen atmosphere. In the embodiment of Fig. 2, phosphorus acid solution 104 coating on un-doped silicon layer 103 (50 nm) is achieved by directly dipping in high concentrated phosphorus acid (～ 85%) for 2 mins; The dielectric capping layer 106 is SiNx (75 nm) deposited by PECVD, and subsequently thermal annealing is performed at 420℃ for 30 mins in the forming gas atmosphere. In the embodiment of Fig. 3, the n-type polycrystalline silicon passivating contacts consist of a dielectric tunnel layer SiOx (1.5 nm) and a silicon layer (50 nm) doped by phosphorus acid (～85%) dipping for 2 mins. Phosphorus acid doping of the un-doped silicon layer 103 (50 nm) is achieved by directly dipping in high concentrated phosphorus acid (～85%) for 2 mins, and subsequently thermal annealing is performed at different temperatures for 25 mins in the nitrogen atmosphere. A low J 0c of 30 fA/cm 2 and low ρ c of 18 mΩ. cm 2 are achieved simultaneously with an optimal annealing temperature of 860℃. After applying a SiNx  dielectric capping layer 106 (75 nm) and subsequently a forming gas annealing (FGA) at 420℃ for 30 mins, the J 0c is further reduced to 15 fA/cm 2. The two key parameters, J 0c and ρ c, of the n-type polycrystalline silicon passivating contacts achieved by phosphorus acid solution doping are comparable to that of in situ doping, phosphine gas diffusion, and ion implantation.
Additionally, as illustrated in Figure 4, which is a graph illustrating the J 0c and the ρ c of n-type polycrystalline silicon passivating contacts as a function of un-doped silicon layer thickness. In this example, phosphorus acid solution 104 coating on un-doped silicon layer 103 is achieved by directly dipping in high concentrated phosphorus acid (～85%) for 2 mins. The thermal annealing is performed at 860℃ for 25 mins in nitrogen atmosphere. Specifically, all the samples experienced a dipping in high concentrated phosphorus acid (85%) for 2 mins and subsequently thermal annealing at 860℃ for 25 mins in nitrogen atmosphere. A low J 0c (<50 fA/cm 2) and ρ c (<100 mΩ. cm 2) is achieved on the passivating contact with an un-doped silicon layer thickness≤100 nm, which meets the prerequisite for high-efficiency silicon solar cells. It is also possible to achieve a better J 0c and ρ c values on n-type polycrystalline silicon passivating contacts with a thick un-doped silicon layer using a higher annealing temperature.
Moreover, as illustrated in Figure 5, which is a graph illustrating the J 0c of n-type polycrystalline silicon passivating contacts as a function of dipping time in the concentrated phosphorus acid (85%) . In this example, all the samples consist of a dielectric tunnel layer SiOx (1.5 nm) and a silicon layer (50 nm) , and experienced the same thermal annealing at 860℃ for 25 mins in nitrogen atmosphere. Specifically, all the samples consist of a dielectric tunnel layer SiOx (1.5 nm) and an un-doped silicon layer (50 nm) , and  subsequently experienced the same thermal annealing at 860℃ for 25 mins in nitrogen atmosphere. A low J 0c≤35 fA/cm 2 is achieved with a dipping time from 1 to 180 mins, demonstrating a short processing time and high flexibility of the phosphorus acid solution doping process.
Furthermore, as illustrated in Figure 6, which is a graph illustrating the J 0c of n-type polycrystalline silicon passivating contacts as a function of thermal annealing temperature in nitrogen atmosphere. In this embodiment, high concentrated phosphorus acid (～85%) is diluted by n-butyl alcohol (50%n-butyl alcohol: 50%H 3PO 4) , and spin coating (4000 RPM for 45s) is used for the coating process. After thermal annealing at 860℃ for 25 mins in nitrogen atmosphere and hydrofluoric acid dipping, SiNx capping layer is deposited by PECVD and forming gas annealing at 420℃ for 30 mins is applied. Specifically, phosphorus acid doping is performed by spin coating n-butyl alcohol diluted phosphorus acid (50%n-butyl alcohol: 50%H 3PO 4) , and subsequently experienced a thermal annealing at different temperatures for 30mins. A SiNx capping layer and then FGA at 420℃ for 30 mins is applied. It can be seen that a low J 0c<50 fA/cm 2 is achieved in a wide range of thermal annealing temperature of 800 to 900℃, featuring a very low J 0c of 10 fA/cm 2 with an optimal annealing temperature of 860℃.
All the embodiments indicates that high quality n-type polycrystalline silicon passivating contacts with good J 0c and ρ c can be prepared using phosphorus acid solution dipping, using a board range of annealing temperature, un-doped silicon layer thickness, phosphorus acid coating time and methods. Compared to the in-situ doping, diffusion doping and ion implantation, phosphorus acid solution doping for n-type polycrystalline silicon passivating contacts offer significant advantages in terms of simplicity, high safety, and low cost.
The invention also provides a method of producing a photovoltaic device with n-type polycrystalline silicon passivating contact, comprising steps of: growing an un-doped silicon layer on a semiconductor substrate; coating the un-doped silicon layer using phosphorus acid solution; performing thermal annealing to activate phosphorus doping and converting the un-doped silicon layer to a phosphorus doped polycrystalline silicon layer; wherein the semiconductor substrate is a silicon wafer with a dielectric tunnel layer.
The invention also provides a method of producing a photovoltaic device with n-type polycrystalline silicon passivating contact, comprising steps of: growing an un-doped silicon layer on a semiconductor substrate; coating the un-doped silicon layer using phosphorus acid solution; performing thermal annealing to activate the phosphorus doping and converting the un-doped silicon layer to a phosphorus doped polycrystalline silicon layer; depositing a dielectric capping layer on the phosphorus doped polycrystalline silicon layer; performing thermal annealing; wherein the semiconductor substrate is a silicon wafer with a dielectric tunnel layer.
Various configurations of photovoltaic devices with n-type polycrystalline silicon passivating contacts using phosphorus acid solution doping will now be described in Figures 7-11.
The photovoltaic device illustrated in Figure 7 features passivating contacts on both sides. A phosphorus acid solution doped n-type polycrystalline silicon passivating contact is applied at the rear for electron collection, consists of a first tunnel oxide 701 and a first n-type polycrystalline silicon layer 702, capped with a first rear electrode 703. The front side of the device includes a p-type polycrystalline silicon passivating  contact adjacent to a first n-type silicon substrate 704, consists of a first tunnel oxide 705 and a boron doped first polycrystalline silicon layer 706, capped with tin doped indium oxide (ITO) first window layer 707. A first front electrode 708 is directly applied on the oxide (ITO) first window layer 707.
The photovoltaic device illustrated in Figure 8 also figures a phosphorus acid solution doped n-type polycrystalline silicon passivating contact (asecond tunnel oxide 801, a second n-type polycrystalline silicon 802) at the rear side for electron collection, which is capped by a second SiNx layer 803. The second tunnel oxide 801 may be SiOx. A second rear electrode 804 is adjacent to the second n-type polycrystalline silicon 802 through the second SiNx layer 803. The front side figures a second boron diffused p+emitter 805 for hole collection on a second n-type silicon substrate 806, which is passivated by a second Al 2O 3 807 and a second SiNx 808 stack. The second Al 2O 3 807 may be deposited by ALD or PECVD, with a typically thickness of 5-50 nm, and the second SiNx 808 may be deposited by PECVD, with a typically thickness of 25-75 nm. A second front electrode 809 is applied through Al 2O 3/SiNx stack.
The photovoltaic device illustrated in Figure 9 includes a phosphorus acid solution doped n-type polycrystalline silicon passivating contact at the front and a boron doped p-type polycrystalline silicon passivating contact at the rear side. Specifically, p-type silicon substrate 901 is sandwiched between n-type (902 and 903) and p-type (905 and 906) polycrystalline silicon passivating contacts, both capped with ITO layer (a second window layer 907 and a third window layer 908) . A third front electrode 909 and third rear electrode 9010 are applied on ITO directly.
The photovoltaic device illustrated in Figure 10 features a third boron  diffused p+emitter 1001 at the rear side of a third n-type silicon substrate 1002, which is passivated by a third Al 2O 3 1003 and a third SiNx 1004 stack. A phosphorus acid solution doped n-type polycrystalline silicon passivating contact is applied at the front side for electron collection, consists of a third tunnel oxide 1005 and a phosphorus doped third polycrystalline silicon layer 1006, capped with an ITO layer 1007. A fourth front electrode 1008 and a fourth rear electrode 1009 are formed on ITO and through Al 2O 3/SiNx stack, respectively.
The photovoltaic device illustrated in Figure 11 is an interdigitated back-contact silicon device with both n-type and p-type polycrystalline silicon passivating contacts at the rear side. Specifically, the interdigitated back-contact structure includes a first electrode 1101 directly adjacent to a n-type polycrystalline silicon passivating contact consists of a fifth tunnel oxide 1102 and a fifth n-type polycrystalline silicon layer 1103, and a second electrode 1104 directly adjacent to p-type polycrystalline silicon passivating contact consists of SiOx 1102 and p-type polycrystalline silicon layer 1105. the fifth tunnel oxide may be SiOx. The front side of the device is passivated by a fifth SiNx layer 1106, which is directly adjacent to a fifth n-type silicon substrate 1107.
Although the embodiments discussed above involve photovoltaic devices, the disclosed phosphorus acid solution doped n-type silicon layer can be used in a wide variety of electronic devices, including bipolar transistors, light emitting diodes, or any other type of electronic device where phosphorus doped silicon layer is desirable.
The disclosed embodiments provide a method to prepare n-type polycrystalline silicon passivating contacts using phosphorus acid solution doping and methods for producing photovoltaic devices having an n-type  polycrystalline silicon passivating contact. It should be understood that this description is not intended to limit the invention. On the contrary, the exemplary embodiments are intended to cover alternatives, modifications and equivalents, which are included in the spirit and scope of the invention as defined by the appended claims. Further, in the detailed description of the exemplary embodiments, numerous specific details are set forth in order to provide a comprehensive understanding of the claimed invention. However, one skilled in the art would understand that various embodiments may be practiced without such specific details.
Although the features and elements of the present exemplary embodiments are described in the embodiments in particular combinations, each feature or element can be used alone without the other features and elements of the embodiments or in various combinations with or without other features and elements disclosed herein.
This written description uses examples of the subject matter disclosed to enable any person skilled in the art to practice the same, including making and using any devices or systems and performing any incorporated methods. The patentable scope of the subject matter is defined by the claims, and may include other examples that occur to those skilled in the art. Such other examples are intended to be within the scope of the claims.

Claims (13)

  1. A method of preparing passivating contact, comprising steps of:
    growing a tunnel layer on the substrate and depositing an un-doped silicon layer on the tunnel layer;
    coating the un-doped silicon layer using phosphorus acid solution;
    performing thermal annealing to activate the phosphorus doping and converting the un-doped silicon layer to a phosphorus doped polycrystalline silicon layer.
  2. The method of preparing passivating contact according to claim 1, wherein the phosphorus acid solution is concentrated or diluted phosphorus acid.
  3. The method of preparing passivating contact according to claim 1, wherein the coating is direct dipping, spin coating, spraying or brush painting.
  4. The method of preparing passivating contact according to claim 1, wherein the tunnel layer is selected from the group consisting of a silicon oxide layer, asilicon nitride layer, atitanium oxide layer, an aluminum oxide layer and any combination thereof.
  5. The method of preparing passivating contact according to claim 1, wherein the un-doped silicon layer is deposited by chemical vapor deposition or physical vapor deposition.
  6. The method of preparing passivating contact according to claim 1, wherein the thermal annealing is performed in the temperature range of 650 ℃ to 1000 ℃ in nitrogen or forming gas atmosphere.
  7. The method of preparing passivating contact according to claim 6, wherein the forming gas is a mixture of nitrogen and hydrogen.
  8. The method of preparing passivating contact according to claim 1, wherein the method further comprises steps of:
    depositing a dielectric capping layer on the phosphorus doped polycrystalline silicon layer; and
    performing thermal annealing.
  9. The method of preparing passivating contact according to claim 8, wherein the dielectric capping layer is selected from the group consisting of a silicon nitride layer, atitanium oxide layer, an aluminum oxide layer, a silicon oxide layer and any combination thereof.
  10. The method of preparing passivating contact according to claim 8, wherein the thermal annealing is performed in the temperature range of 200 ℃ to 500 ℃ in nitrogen or forming gas atmosphere.
  11. The method of claim 10, wherein the forming gas is a mixture of nitrogen and hydrogen.
  12. A method of producing a photovoltaic device with n-type polycrystalline silicon passivating contact, comprising steps of:
    growing an un-doped silicon layer on a semiconductor substrate;
    coating the un-doped silicon layer using phosphorus acid solution;
    performing thermal annealing to activate phosphorus doping and converting the un-doped silicon layer to a phosphorus doped polycrystalline silicon layer;
    wherein the semiconductor substrate is a silicon wafer with a dielectric  tunnel layer.
  13. A method of producing a photovoltaic device with n-type polycrystalline silicon passivating contact, comprising steps of:
    growing an un-doped silicon layer on a semiconductor substrate;
    coating the un-doped silicon layer using phosphorus acid solution;
    performing thermal annealing to activate the phosphorus doping and converting the un-doped silicon layer to a phosphorus doped polycrystalline silicon layer;
    depositing a dielectric capping layer on the phosphorus doped polycrystalline silicon layer;
    performing thermal annealing;
    wherein the semiconductor substrate is a silicon wafer with a dielectric tunnel layer.
PCT/CN2021/077086 2021-02-20 2021-02-20 Method of preparing passivating contacts and method of producing photovoltaic device with n-type polycrystalline silicon passivating contact WO2022174421A1 (en)

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US20120270359A1 (en) * 2011-04-21 2012-10-25 Applied Materials, Inc. Method of forming p-n junction in solar cell substrate
CN105990121A (en) * 2015-02-02 2016-10-05 中芯国际集成电路制造(上海)有限公司 Formation method of doped polycrystalline silicon layer and formation method of semiconductor device
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