WO2022170816A1 - 一种功率放大器的偏置电路、装置及设备 - Google Patents

一种功率放大器的偏置电路、装置及设备 Download PDF

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Publication number
WO2022170816A1
WO2022170816A1 PCT/CN2021/132876 CN2021132876W WO2022170816A1 WO 2022170816 A1 WO2022170816 A1 WO 2022170816A1 CN 2021132876 W CN2021132876 W CN 2021132876W WO 2022170816 A1 WO2022170816 A1 WO 2022170816A1
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Prior art keywords
circuit
transistor
gate
bias
tube
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PCT/CN2021/132876
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English (en)
French (fr)
Inventor
彭振飞
苏强
倪旭文
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广州慧智微电子股份有限公司
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Publication of WO2022170816A1 publication Critical patent/WO2022170816A1/zh
Priority to US17/929,710 priority Critical patent/US20230006623A1/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/24—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages
    • H03F3/245—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages with semiconductor devices only
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/30—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/30—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters
    • H03F1/301—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters in MOSFET amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/56—Modifications of input or output impedances, not otherwise provided for
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/56—Modifications of input or output impedances, not otherwise provided for
    • H03F1/565—Modifications of input or output impedances, not otherwise provided for using inductive elements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/189—High-frequency amplifiers, e.g. radio frequency amplifiers
    • H03F3/19—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
    • H03F3/193—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only with field-effect devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/18—Indexing scheme relating to amplifiers the bias of the gate of a FET being controlled by a control signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/451—Indexing scheme relating to amplifiers the amplifier being a radio frequency amplifier

Definitions

  • the present application relates to electronic technology, and in particular, to a bias circuit, device and device for a power amplifier.
  • the bias circuit of the RF amplifier is used to provide a stable DC bias for the power tube.
  • the MOS transistor amplifier mainly provides a DC bias voltage for the gate of the MOS transistor.
  • FIG. 1 is a schematic diagram of the composition and structure of a bias circuit of a conventional power amplifier.
  • the bias circuit includes: an M tube and a current source IBIAS; the specific connection method: the drain of the M tube is connected to the current source IBIAS, the source of the M tube is grounded, and the drain of the M tube is short-circuited with the gate ;
  • the grid of the M tube is connected to the grid of the M0 tube of the power amplifier to provide a bias voltage for the grid of the M0 tube;
  • the M0 tube is included in the signal amplification circuit to amplify the input signal; signal amplification
  • the circuit also includes: capacitor C1, capacitor C2, voltage source VCC and inductor L; specific connection method: the gate of the M0 tube is connected to one end of the capacitor C1, and the other end of the capacitor C1 is used as the RF signal input terminal; the drain of the M0 tube passes through
  • the inductor L is connected to the voltage source VCC, and is also connected to one end of the
  • the other end of the capacitor C2 is used as a radio frequency signal output terminal, and the source of the M0 tube is connected to the ground terminal.
  • the nonlinear effect causes the gate-source voltage of the M tube to decrease as the power of the input RF signal increases, that is, the bias provided to the M0 tube The voltage is reduced, which in turn leads to the deterioration of the linearity of the M0 tube.
  • the present application provides a bias circuit, device and equipment for a power amplifier.
  • a bias circuit of a power amplifier comprising: a first partial circuit, a second partial circuit and a power supply;
  • the power supply is connected to the power supply terminal of the first part of the circuit, and is used for supplying power to the first part of the circuit;
  • Two ends of the first part of the circuit are connected in parallel with two ends of the second part of the circuit, and one end after the parallel connection is connected to the gate of the first transistor of the power amplifier in the signal amplification circuit; the first part of the circuit is used to The gate of the first transistor provides a first bias voltage; the second partial circuit is used for providing a second bias voltage to the gate of the first transistor; the first bias voltage and the second bias providing a stable bias voltage for the gate of the first transistor after the voltage is superimposed;
  • the impedance of the bias circuit is within a predetermined impedance range.
  • the first part of the circuit includes: a second transistor, a third transistor, a first resistor and a first capacitor; wherein the drain of the second transistor is connected to the power supply, and the drain of the second transistor is connected to the power supply.
  • the electrode is connected to the gate; the source of the second transistor is connected to one end of the second partial circuit; the gate of the second transistor is connected to the gate of the third transistor through the first resistor, It is also connected to the ground terminal through the first capacitor; the drain of the third transistor is connected to the power supply, the source of the third transistor is connected to the other end of the second partial circuit, and is also connected to the power supply.
  • the gate of the first transistor is connected.
  • the first partial circuit further includes: a second resistor; wherein, the second resistor is a variable resistor; and the first capacitor is connected to the ground terminal through the second resistor.
  • the power supply includes: a current source, a first voltage source and a second voltage source; the first voltage source is connected to the drain of the third transistor; the second voltage source passes through the current source connected to the drain of the second transistor.
  • the bias circuit further includes: a third resistor; the source of the third transistor is connected to the gate of the first transistor through the third resistor.
  • the second part of the circuit includes: a fourth transistor, a fifth transistor, a fourth resistor and a second capacitor; the drain of the fourth transistor is connected to one end of the first part, and the fourth transistor The source of the transistor is grounded; the gate of the fourth transistor is connected to the gate of the fifth transistor, and is also connected to the ground terminal through the second capacitor; the drain of the fifth transistor is connected to the fourth resistor It is connected to the gate of the fifth transistor, and is also connected to the other end of the first part; the source of the fifth transistor is grounded.
  • the fourth resistor is a fixed resistor and the second capacitor is a fixed capacitor; or, the fourth resistor is a variable resistor and the second capacitor is a variable capacitor.
  • the second transistor, the third transistor, the fourth transistor and the fifth transistor are transistors of the same structure.
  • the signal amplifying circuit further includes: a third capacitor, a fourth capacitor, an inductor and a third voltage source; the gate of the first transistor is connected to one end of the third capacitor, and the third capacitor The other end of the first transistor is used as a signal input end; the drain of the first transistor is connected to the third voltage source through the inductance, and is also connected to one end of the fourth capacitor, and the other end of the fourth capacitor is used as a signal output terminal; the source of the first transistor is grounded.
  • a power amplifying apparatus in a second aspect, includes a power amplifier and a bias circuit of any one of the above-mentioned power amplifiers.
  • an electronic device in a third aspect, includes a power amplifying device.
  • the present application discloses a bias circuit for a power amplifier.
  • the circuit includes: a first partial circuit, a second partial circuit and a power supply; the power supply is connected to a power supply terminal of the first partial circuit for supplying power to the first partial circuit; two parts of the first partial circuit The terminal is connected in parallel with both ends of the second part of the circuit, and one end after the parallel connection is connected to the gate of the first transistor of the power amplifier in the signal amplification circuit; the first part of the circuit is used to provide a first bias voltage to the gate of the first transistor; The second part of the circuit is used to provide a second bias voltage to the gate of the first transistor; the first bias voltage and the second bias voltage are superimposed to provide a stable bias voltage to the gate of the first transistor; the bias circuit The impedance is within the preset impedance range.
  • the first partial circuit is used to provide the power amplifier with a first bias voltage
  • the second partial circuit is used to provide the power amplifier with a second bias voltage
  • the second bias voltage can adjust the first bias voltage to provide stability for the power amplifier.
  • the bias voltage and the impedance of the bias circuit are within the preset impedance range, so as to ensure the linearity performance of the power amplifier and reduce the memory effect of the power amplifier.
  • FIG. 1 is a schematic diagram of the composition and structure of a bias circuit of an existing power amplifier
  • FIG. 2 is a schematic diagram of a first composition structure of a bias circuit of a power amplifier in an embodiment of the present application
  • FIG. 3 is a schematic diagram of a second composition structure of a bias circuit of a power amplifier in an embodiment of the present application
  • FIG. 4 is a schematic diagram of the variation of the relationship between radio frequency power and bias voltage in an embodiment of the present application
  • FIG. 5 is a schematic diagram of a comparison result between the impedance of the bias circuit in the embodiment of the present application and the impedance of the existing bias circuit;
  • FIG. 6 is a schematic diagram of a third composition structure of a bias circuit of a power amplifier in an embodiment of the present application.
  • variable resistor 7 is a schematic structural diagram of a variable resistor in an embodiment of the present application.
  • FIG. 8 is a schematic structural diagram of a variable capacitor in an embodiment of the present application.
  • FIG. 9 is a schematic diagram showing the relationship between the RF power and the gain amplitude and the bias voltage, respectively, according to an embodiment of the present application.
  • FIG. 2 is a schematic diagram of the first composition of the bias circuit of the power amplifier in the embodiment of the present application.
  • the bias circuit 11 includes: a part of the circuit 110, the second part of the circuit 111 and the power supply 112;
  • the power supply 112 is connected to the power supply terminal of the first partial circuit 110 for supplying power to the first partial circuit 110;
  • Two ends of the first partial circuit 110 are connected in parallel with two ends of the second partial circuit 111, and one end after parallel connection is connected to the gate of the first transistor of the power amplifier 120 in the signal amplifying circuit 12; the first partial circuit 110 is used for the first transistor
  • the gate of the first transistor provides a first bias voltage;
  • the second partial circuit 111 is used to provide a second bias voltage to the gate of the first transistor;
  • the superposition of the first bias voltage and the second bias voltage is the gate of the first transistor Extremely stable bias voltage;
  • the impedance of the bias circuit 11 is within the preset impedance range.
  • the first partial circuit 110 is used to provide the power amplifier 120 with a first bias voltage
  • the second partial circuit 111 is used to provide the power amplifier 120 with a second bias voltage.
  • the second bias voltage adjusts the first bias voltage, so as to provide a stable bias voltage for the power amplifier 120 , thereby ensuring the linearity performance of the power amplifier 120 .
  • the preset impedance range refers to a range that does not cause deterioration of the linearity of the power amplifier.
  • first part of the circuit 110 and the second part of the circuit 111 also include other matching components, for example, one or more combinations of resistors, capacitors, and transistors.
  • the first partial circuit 110 and the second partial circuit 111 are combined with one or more components to superimpose the first bias voltage of the first partial circuit 110 and the second bias voltage of the second partial circuit 111 to provide the power amplifier with
  • the stable bias voltage and the impedance of the bias circuit 11 are within the preset impedance range, which ensures the linearity of the power amplifier 120, thereby effectively amplifying the input radio frequency signal.
  • the signal amplifying circuit 12 in FIG. 2 includes a power amplifier 120 for amplifying the radio frequency signal input from the signal input end, and outputting the amplified radio frequency signal from the signal output end.
  • the first partial circuit is used to provide the power amplifier with a first bias voltage
  • the second partial circuit is used to provide the power amplifier with a second bias voltage
  • the second bias voltage can adjust the first bias voltage to provide stability for the power amplifier.
  • the bias voltage and the impedance of the bias circuit are within the preset impedance range, so as to ensure the linearity performance of the power amplifier and reduce the memory effect of the power amplifier.
  • FIG. 3 is a schematic diagram of the second composition of the bias circuit of the power amplifier in the embodiment of the application.
  • the bias circuit 11 of the power amplifier includes a first partial circuit 110 , a second partial circuit 111 and a power supply 112 .
  • the power source 112 includes: a current source IBIAS, a first voltage source VCC1 and a second voltage source VCC2.
  • the IBIAS is powered through VCC2.
  • the first partial circuit 110 includes: a second transistor M2, a third transistor M3, a first resistor R1 and a first capacitor C1;
  • the specific connection method is as follows: the drain of the M2 tube is connected to VCC2 through IBIAS, the drain of the M2 tube is connected to the gate; the source of the M2 tube is connected to one end of the second part of the circuit 111 (ie the drain of the M4 tube); M2 The gate of the tube is connected to the gate of the M3 tube through R1, and is also connected to the ground terminal through C1; the drain of the M3 tube is connected to VCC1, and the source of the M3 tube is connected to the other end of the second part of the circuit 111. drain) is connected to the gate of the M1 tube.
  • the M2 tube and the M3 tube form a current mirror structure.
  • R1 and C1 between the M2 and M3 tubes form a low-pass network circuit, which is used to isolate the RF signal to avoid coupling into the bias current circuit, that is, to avoid affecting the M2 tube, thereby ensuring that the gate voltage of the M2 tube remains unchanged. Since the gate voltage of the M2 tube is equal to the gate voltage of the M3 tube, the gate voltage of the M3 tube remains unchanged.
  • the gate and drain of the M2 tube in the first part of the circuit are connected, that is, the M2 tube is a nonlinear component, so the first part of the circuit is a nonlinear circuit. Due to the nonlinearity of the M3 tube in the first part of the circuit and the presence of RF signals on the gate-source voltage of the M3 tube, when the input RF signal power is large, the gate-source voltage of the M3 tube is reduced.
  • the gate-source voltage of the M3 tube is equal to the gate voltage of the M3 tube minus the source voltage.
  • the gate-source voltage of the M3 tube decreases, and the gate voltage of the M3 tube remains unchanged, so the source voltage of the M3 tube increases, that is, the first part of the circuit increases the voltage of the V2 node.
  • the second partial circuit 111 includes: a fourth transistor M4, a fifth transistor M5, a fourth resistor R4 and a second capacitor C2;
  • the specific connection method is as follows: the drain of the M4 tube is connected to one end of the first part of the circuit 110 (that is, the source of the M2 tube), the source of the M4 tube is grounded; the gate of the M4 tube is connected to the gate of the M5 tube, and also through C2 Connected to the ground terminal; the drain of the M5 tube is connected to the gate of the M5 tube through R4, and is also connected to the other end of the first partial circuit 110 (ie, the source of the M3 tube); the source of the M5 tube is grounded.
  • the M4 tube and the M5 tube form a current mirror structure.
  • R4 and C2 form a low-pass network circuit, which is used to reduce the gate voltage of the M5 tube.
  • the drain of the M5 tube is connected to the gate through R4, that is, the M5 tube is connected by a diode and is a nonlinear component, so the nonlinear effect causes the gate-source voltage of the M5 tube to decrease with the increase of the power of the input RF signal. Since the gate voltage of the M5 tube is equal to the drain voltage and the source voltage is equal to zero, the gate voltage of the M5 tube (ie the V1 node voltage) decreases, that is, the second part of the circuit reduces the V2 node voltage.
  • the V2 node can present a stable DC bias after superposition. set voltage.
  • FIG. 4 is a schematic diagram of the relationship between the RF power and the bias voltage in the embodiment of the application.
  • the bias voltage of the V2 node increases high; when the M5 tube works alone, the bias voltage of the V2 node decreases; when the M3 tube and the M5 tube work together, the V2 node presents a stable DC bias voltage.
  • the M2 tube, M3 tube, M4 tube and M5 tube form a closed loop to achieve a lower output impedance.
  • FIG. 5 is a schematic diagram showing the result of comparing the impedance of the bias circuit in the embodiment of the present application with the impedance of the existing bias circuit. As shown in FIG. 5 , the impedance of the bias circuit in the present application is lower than that of the existing bias circuit (ie, FIG. 1 ). impedance of the circuit.
  • the bias circuit further includes: a third resistor R3;
  • the source of the M3 tube is connected to the gate of the M1 tube through R3
  • the drain of the M5 tube is connected to the gate of the M1 tube through R3.
  • R3 is used to adjust the impedance frequency characteristics of the gate node of the M1 tube, so that the M1 tube has the best linearity.
  • R3 usually takes a value of more than ten ohms.
  • the signal amplifying circuit 12 further includes: a third capacitor C3, a fourth capacitor C4, an inductor L and a third voltage source VCC3;
  • the specific connection method is as follows: the gate of M1 is connected to one end of C3, and the other end of C3 is used as a signal input end; the drain of M1 is connected to VCC2 through L, and is also connected to one end of C4, and the other end of C4 is used as a signal output terminal; the source of the M1 tube is grounded.
  • the M2 tube, the M3 tube, the M4 tube and the M5 tube mentioned above are transistors of the same structure.
  • the M1 tube, the M2 tube, the M3 tube, the M4 tube and the M5 tube may be transistors of the same structure, or may not be transistors of the same structure.
  • the present application also provides a specific circuit structure diagram for the first structural schematic diagram of the bias circuit of the power amplifier in FIG. 2
  • FIG. 6 is the third structural schematic diagram of the bias circuit of the power amplifier in the embodiment of the application.
  • the bias circuit 11 of the power amplifier includes a first partial circuit 110 , a second partial circuit 111 and a power supply 112 .
  • the power source 112 includes: a current source IBIAS, a first voltage source VCC1 and a second voltage source VCC2.
  • the IBIAS is powered through VCC2.
  • the first partial circuit 110 includes: a second transistor M2, a third transistor M3, a first resistor R1, a first capacitor C1 and a second resistor R2; wherein, R2 is a variable resistor.
  • the specific connection method is as follows: the drain of the M2 tube is connected to VCC2 through IBIAS, the drain of the M2 tube is connected to the gate; the source of the M2 tube is connected to one end of the second part of the circuit 111 (ie the drain of the M4 tube); M2 The gate of the tube is connected to the gate of the M3 tube through R1, and is also connected to the ground terminal through C1 and R2 in series; the drain of the M3 tube is connected to VCC1, and the source of the M3 tube is connected to the other end of the second part of the circuit 111 ( That is, the drain of the M5 tube) is connected to the gate of the M1 tube.
  • FIG. 7 is a schematic structural diagram of a variable resistor in an embodiment of the present application.
  • the variable resistor includes n resistors r and n switches S.
  • the specific connection method is: after r1 and S1 are connected in series, they are connected in parallel at both ends of r2 and S2 after being connected in series, and so on, and then connected in parallel at both ends after rn and Sn are connected in series.
  • variable resistor R2 is connected in series with C1 to control the strength of the effect of increasing the voltage of the V2 node on the M3 tube. For example, if R2 is increased, the effect of increasing the bias voltage of the V2 node will be weakened.
  • the second partial circuit 111 includes: a fourth transistor M4, a fifth transistor M5, a fourth resistor R4 and a second capacitor C2; wherein, R4 is a variable resistor, and C2 is a variable capacitor.
  • the specific connection method is as follows: the drain of the M4 tube is connected to one end of the first part of the circuit 110 (that is, the source of the M2 tube), the source of the M4 tube is grounded; the gate of the M4 tube is connected to the gate of the M5 tube, and also through C2 Connected to the ground terminal; the drain of the M5 tube is connected to the gate of the M5 tube through R4, and is also connected to the other end of the first partial circuit 110 (ie, the source of the M3 tube); the source of the M5 tube is grounded.
  • Fig. 8 is a schematic structural diagram of a variable capacitor in an embodiment of the application.
  • the variable capacitor includes n capacitors c and n switches S.
  • the specific connection method is: after c1 and S1 are connected in series, they are connected in parallel at both ends of c2 and S2 after being connected in series, and so on, and then connected in parallel at both ends after cn and Sn are connected in series.
  • R4 is a variable resistor
  • C2 is a variable capacitor.
  • the bias voltage can be controlled to increase or decrease. In this way, more optimal linearity characteristics can be achieved in the power amplifier by selecting appropriate bias voltage characteristics.
  • the bias circuit further includes: a third resistor R3;
  • the source of the M3 tube is connected to the gate of the M1 tube through R3
  • the drain of the M5 tube is connected to the gate of the M1 tube through R3.
  • R3 is used to adjust the impedance frequency characteristics of the gate node of the M1 tube, so that the M1 tube has the best linearity.
  • R3 usually takes a value of more than ten ohms.
  • the signal amplifying circuit 12 further includes: a third capacitor C3, a fourth capacitor C4, an inductor L and a third voltage source VCC3;
  • the specific connection method is as follows: the gate of M1 is connected to one end of C3, and the other end of C3 is used as a signal input end; the drain of M1 is connected to VCC2 through L, and is also connected to one end of C4, and the other end of C4 is used as a signal output terminal; the source of the M1 tube is grounded.
  • FIG. 9 is a schematic diagram showing the relationship between the RF power and the gain amplitude and the bias voltage, respectively, in the embodiment of the application.
  • the abscissa is the RF power
  • the upper curve represents the RF power and the gain amplitude of the power amplifier (that is, AMAM).
  • the relationship between the 1dB power compression point P1dB can be obtained from the AMAM curve, and P1dB is used as a measure of the linearity of the power amplifier.
  • the dotted line (ie conventional bias) refers to the fixed resistors and capacitors set in the bias circuit (ie R4 and C2 in the circuit in Figure 3), and the solid line (ie the optimal bias) refers to the settings in the bias circuit Variable resistors and capacitors (ie, R2, R4, and C2 in the circuit of Figure 6).
  • the lower part shows the relationship between RF power and bias voltage.
  • the dotted line refers to the fixed resistance and capacitance set in the bias circuit (that is, the conventional bias)
  • the solid line refers to the variable resistance and capacitance set in the bias circuit (that is, the optimal bias).
  • variable resistors and capacitors are mainly to increase the flexibility of debugging the linear power of the bias circuit.
  • the resistor and capacitor values with better linearity can be selected by means of digital control.
  • the power amplifier can work at different frequencies, and the optimal linearity resistance and capacitance values are different at each frequency.
  • different resistance and capacitance values are set at different frequencies, so that the power amplifier has Optimum linearity performance.
  • the embodiment of the present application further discloses a power amplifying device, the power amplifying device includes: a power amplifier and a bias circuit of any one of the power amplifiers in the above-mentioned embodiments.
  • the embodiment of the present application further discloses an electronic device, and the electronic device includes: the power amplifying device in the above-mentioned embodiment of the present application.
  • the present application discloses a bias circuit, device and equipment for a power amplifier.
  • the circuit includes: a first partial circuit, a second partial circuit and a power supply; the power supply is connected to the power supply terminal of the first partial circuit; both ends of the first partial circuit are connected to the second partial circuit The two ends are connected in parallel, and the connected end is connected to the gate of the first transistor of the power amplifier; the first part of the circuit and the second part of the circuit respectively provide the first bias voltage and the second bias voltage to the gate of the first transistor, and provide the Stable bias voltage; bias circuit impedance within preset impedance range.
  • the first partial circuit is used to provide the power amplifier with a first bias voltage
  • the second partial circuit is used to provide the power amplifier with a second bias voltage
  • the second bias voltage can adjust the first bias voltage to provide stability for the power amplifier.
  • the bias voltage and the impedance of the bias circuit are within the preset impedance range, so as to ensure the linearity performance of the power amplifier and reduce the memory effect of the power amplifier.

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Abstract

本申请公开一种功率放大器的偏置电路、装置及设备，该电路包括：第一部分电路、第二部分电路和电源；电源与第一部分电路电源端相连；第一部分电路两端与第二部分电路两端并联，并联后一端与功率放大器的第一晶体管的栅极相连；第一部分电路、第二部分电路分别对第一晶体管栅极提供第一偏置电压和第二偏置电压，叠加后提供稳定偏置电压；偏置电路阻抗位于预设阻抗范围。如此，利用第一部分电路为功率放大器提供第一偏置电压，第二部分电路为功率放大器提供第二偏置电压，第二偏置电压能够对第一偏置电压进行调整，为功率放大器提供稳定偏置电压，且偏置电路阻抗位于预设阻抗范围，保证功率放大器线性度性能，及降低功率放大器记忆效应。

Description

一种功率放大器的偏置电路、装置及设备
相关申请的交叉引用
本申请基于申请号为202110182211.1，申请日为2021年02月09日，申请名称为“一种功率放大器的偏置电路、装置及设备”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此以引入方式并入本申请。
技术领域
本申请涉及电子技术，尤其涉及一种功率放大器的偏置电路、装置及设备。
背景技术
射频放大器的偏置电路用于为功率管提供稳定的直流偏置，对于MOS晶体管放大器，主要是为MOS晶体管的栅极提供直流偏置电压。
图1为现有的功率放大器的偏置电路的组成结构示意图。如图1所示，偏置电路包括：M管和电流源IBIAS；具体连接方式：M管的漏极与电流源IBIAS相连，M管的源极接地，M管的漏极与栅极短接；M管的栅极与功率放大器之M0管的栅极相连，用于为M0管的栅极提供偏置电压；M0管是包括在信号放大电路中，用于对输入信号的放大；信号放大电路还包括：电容C1、电容C2、电压源VCC和电感L；具体连接方式：M0管的栅极与电容C1的一端相连，电容C1的另一端作为射频信号输入端；M0管的漏极通过电感L与电压源VCC相连，还与电容C2的一端相连，电容C2的另一端作为射频信号输出端，M0管的源极与接地端相连。基于上述偏置电路，由于M管为二极管连接，二极管为非线性元器件，故非线性效应导 致M管的栅源电压随输入射频信号的功率增大而降低，即提供给M0管的偏置电压降低，进而导致M0管的线性度变差。
发明内容
为解决上述技术问题，本申请提供一种功率放大器的偏置电路、装置及设备。
本申请的技术方案是这样实现的：
第一方面，提供了一种功率放大器的偏置电路，所述偏置电路包括：第一部分电路、第二部分电路和电源；
所述电源与所述第一部分电路的电源端相连，用于为所述第一部分电路供电；
所述第一部分电路的两端与所述第二部分电路的两端并联，并联后的一端与信号放大电路中功率放大器的第一晶体管的栅极相连；所述第一部分电路用于对所述第一晶体管的栅极提供第一偏置电压；所述第二部分电路用于对所述第一晶体管的栅极提供第二偏置电压；所述第一偏置电压和所述第二偏置电压叠加后为所述第一晶体管的栅极提供稳定的偏置电压；
所述偏置电路的阻抗位于预设阻抗范围。
上述方案中，所述第一部分电路包括：第二晶体管、第三晶体管、第一电阻和第一电容；其中，所述第二晶体管的漏极与所述电源相连，所述第二晶体管的漏极与栅极相连；所述第二晶体管的源极与所述第二部分电路的一端相连；所述第二晶体管的栅极通过所述第一电阻与所述第三晶体管的栅极相连，还通过所述第一电容与接地端相连；所述第三晶体管的漏极与所述电源相连，所述第三晶体管的源极与所述第二部分电路的另一端相连，还与所述第一晶体管的栅极相连。
上述方案中，所述第一部分电路还包括：第二电阻；其中，所述第二电阻为可变电阻；所述第一电容通过所述第二电阻与接地端相连。
上述方案中，所述电源包括：电流源、第一电压源和第二电压源；所述第一电压源与所述第三晶体管的漏极相连；所述第二电压源通过所述电流源与所述第二晶体管的漏极相连。
上述方案中，所述偏置电路还包括：第三电阻；所述第三晶体管的源极通过所述第三电阻与所述第一晶体管的栅极相连。
上述方案中，所述第二部分电路包括：第四晶体管、第五晶体管、第四电阻和第二电容；所述第四晶体管的漏极与所述第一部分的一端相连，所述第四晶体管的源极接地；所述第四晶体管的栅极与所述第五晶体管的栅极相连，还通过所述第二电容与接地端相连；所述第五晶体管的漏极通过所述第四电阻与所述第五晶体管的栅极相连，还与所述第一部分的另一端相连；所述第五晶体管的源极接地。
上述方案中，所述第四电阻为固定电阻及所述第二电容为固定电容；或者，所述第四电阻为可变电阻及所述第二电容为可变电容。
上述方案中，所述第二晶体管、所述第三晶体管、所述第四晶体管和所述第五晶体管为相同结构的晶体管。
上述方案中，所述信号放大电路还包括：第三电容、第四电容、电感和第三电压源；所述第一晶体管的栅极与所述第三电容的一端相连，所述第三电容的另一端作为信号输入端；所述第一晶体管的漏极通过所述电感与所述第三电压源相连，还与所述第四电容的一端相连，所述第四电容的另一端作为信号输出端；所述第一晶体管的源极接地。
第二方面，提供了一种功率放大装置，所述功率放大装置包括功率放大器和上述任意一项功率放大器的偏置电路。
第三方面，提供了一种电子设备，所述电子设备包括功率放大装置。
本申请公开一种功率放大器的偏置电路，该电路包括：第一部分电路、第二部分电路和电源；电源与第一部分电路的电源端相连，用于为第一部 分电路供电；第一部分电路的两端与第二部分电路的两端并联，并联后的一端与信号放大电路中功率放大器的第一晶体管的栅极相连；第一部分电路用于对第一晶体管的栅极提供第一偏置电压；第二部分电路用于对第一晶体管的栅极提供第二偏置电压；第一偏置电压和第二偏置电压叠加后为第一晶体管的栅极提供稳定的偏置电压；偏置电路的阻抗位于预设阻抗范围。如此，利用第一部分电路为功率放大器提供第一偏置电压，第二部分电路为功率放大器提供第二偏置电压，第二偏置电压能够对第一偏置电压进行调整，为功率放大器提供稳定偏置电压，且偏置电路阻抗位于预设阻抗范围，保证功率放大器线性度性能，及降低功率放大器记忆效应。
附图说明
图1为现有的功率放大器的偏置电路的组成结构示意图；
图2为本申请实施例中功率放大器的偏置电路的第一组成结构示意图；
图3为本申请实施例中功率放大器的偏置电路的第二组成结构示意图；
图4为本申请实施例中射频功率与偏置电压的关系变化示意图；
图5为本申请实施例中偏置电路的阻抗与现有偏置电路的阻抗比较结果示意图；
图6为本申请实施例中功率放大器的偏置电路的第三组成结构示意图；
图7为本申请实施例中可变电阻的结构示意图；
图8为本申请实施例中可变电容的结构示意图；
图9为本申请实施例中射频功率分别于增益幅度及偏置电压的关系变化示意图。
具体实施方式
为了能够更加详尽地了解本申请实施例的特点与技术内容，下面结合附图对本申请实施例的实现进行详细阐述，所附附图仅供参考说明之用， 并非用来限定本申请实施例。
本申请实施例提供了一种功率放大器的偏置电路，图2为本申请实施例中功率放大器的偏置电路的第一组成结构示意图，如图2所示，该偏置电路11包括：第一部分电路110、第二部分电路111和电源112；
电源112与第一部分电路110的电源端相连，用于为第一部分电路110供电；
第一部分电路110的两端与第二部分电路111的两端并联，并联后的一端与信号放大电路12中功率放大器120的第一晶体管的栅极相连；第一部分电路110用于对第一晶体管的栅极提供第一偏置电压；第二部分电路111用于对第一晶体管的栅极提供第二偏置电压；第一偏置电压和第二偏置电压叠加后为第一晶体管的栅极提供稳定的偏置电压；
且偏置电路11的阻抗位于预设阻抗范围。
需要说明的是，第一部分电路110用于对功率放大器120提供第一偏置电压，第二部分电路111用于对功率放大器120提供第二偏置电压。当输入功率放大器120的射频信号的功率增大时，会导致第一偏置电压升高，第二偏置电压降低，或者，第一偏置电压降低，第二偏置电压升高，通过第二偏置电压对第一偏置电压进行调节，使得为功率放大器120提供稳定的偏置电压，进而保证功率放大器120的线性度性能。
需要说明的是，预设阻抗范围指的是不会导致功率放大器的线性度变差的范围。这里，预设阻抗范围可以为小于图1中偏置电路的阻抗Z1，即Z1＝1/gm，其中，gm为M管的跨导。当偏置电路的阻抗较低时，可保证功率放大器线性度性能。
需要说明的是，第一部分电路110和第二部分电路111中还包括其他匹配元器件，例如，电阻、电容、晶体管的一种或者多种组合。通过一种或者多种元器件组合的第一部分电路110和第二部分电路111，将第一部分电 路110的第一偏置电压和第二部分电路111的第二偏置电压叠加后为功率放大器提供稳定的偏置电压，且偏置电路11的阻抗位于预设阻抗范围，保证了功率放大器120的线性度，进而对输入的射频信号进行有效放大。
另外，图2的信号放大电路12中包括功率放大器120，用于对信号输入端输入的射频信号进行放大，从信号输出端输出放大后的射频信号。
如此，利用第一部分电路为功率放大器提供第一偏置电压，第二部分电路为功率放大器提供第二偏置电压，第二偏置电压能够对第一偏置电压进行调整，为功率放大器提供稳定偏置电压，且偏置电路阻抗位于预设阻抗范围，保证功率放大器线性度性能，及降低功率放大器记忆效应。
针对图2功率放大器的偏置电路的第一组成结构示意图，本申请提供了一种具体的电路结构图，图3为本申请实施例中功率放大器的偏置电路的第二组成结构示意图。
如图3所示，功率放大器的偏置电路11包括第一部分电路110、第二部分电路111和电源112。
电源112包括：电流源IBIAS、第一电压源VCC1和第二电压源VCC2。这里，通过VCC2对IBIAS供电。
第一部分电路110包括：第二晶体管M2、第三晶体管M3、第一电阻R1和第一电容C1；
具体连接方式为：M2管的漏极通过IBIAS与VCC2相连，M2管的漏极与栅极相连；M2管的源极与第二部分电路111的一端(即M4管的漏极)相连；M2管的栅极通过R1与M3管的栅极相连，还通过C1与接地端相连；M3管的漏极与VCC1相连，M3管的源极与第二部分电路111的另一端(即M5管的漏极)相连，还与M1管的栅极相连。
需要说明的是，M2管和M3管组成电流镜结构。位于M2管和M3管之间的R1和C1组成低通网络电路，用于隔离射频信号避免耦合到偏置电 流电路中，即避免影响到M2管，进而保证M2管的栅极电压不变。由于M2管的栅极电压等于M3管的栅极电压，故M3管的栅极电压保持不变。
需要说明的是，第一部分电路中M2管的栅极和漏极相连，即M2管为非线性元器件，故第一部分电路为非线性电路。由于第一部分电路中M3管的非线性且M3管的栅源电压上存在射频信号，当输入的射频信号功率较大时，导致M3管的栅源电压降低。
这里，M3管的栅源电压等于M3管的栅极电压减去源极电压。M3管的栅源电压降低，M3管的栅极电压保持不变，故M3管的源极电压升高，即第一部分电路使得V2节点的电压升高。
第二部分电路111包括：第四晶体管M4、第五晶体管M5、第四电阻R4和第二电容C2；
具体连接方式为：M4管的漏极与第一部分电路110的一端(即M2管的源极)相连，M4管的源极接地；M4管的栅极与M5管的栅极相连，还通过C2与接地端相连；M5管的漏极通过R4与M5管的栅极相连，还与第一部分电路110的另一端(即M3管的源极)相连；M5管的源极接地。
需要说明的是，M4管和M5管组成电流镜结构。R4和C2组成低通网络电路，用于降低M5管的栅极电压。具体的，M5管的漏极通过R4与栅极相连，即M5管为二极管连接且为非线性元器件，故非线性效应导致M5管的栅源电压随输入射频信号的功率增大而降低。由于M5管的栅极电压等于漏极电压，且源极电压等于零，故M5管的栅极电压(即V1节点电压)降低，即第二部分电路使得V2节点的电压降低。
这里，由于第一部分电路使得V2节点的电压升高，第二部分电路使得V2节点的电压降低，若设计成两个部分电路的电压升降影响幅度相等，则叠加后V2节点可呈现稳定的直流偏置电压。
基于上述阐述，图4为本申请实施例中射频功率与偏置电压的关系变 化示意图，如图4所示，随着射频功率的增大，M3管单独作用时，V2节点的偏置电压升高；M5管单独作用时，V2节点的偏置电压降低；M3管和M5管共同作用时，V2节点呈现稳定的直流偏置电压。
另外，M2管、M3管、M4管和M5管构成一个闭合环路实现了较低的输出阻抗，V2节点的阻抗(即偏置电路的阻抗)为：Z2＝1/(gm3+gm5)(1+A)，其中，gm3为M3管的跨导，gm5为M5管的跨导，A为环路增益典型值约为100。
图5为本申请实施例中偏置电路的阻抗与现有偏置电路的阻抗比较结果示意图，如图5所示，本申请中偏置电路的阻抗低于现有(即图1)偏置电路的阻抗。
偏置电路还包括：第三电阻R3；
这里，M3管的源极通过R3与M1管的栅极相连，M5管的漏极通过R3与M1管的栅极相连。
需要说明的是，增加R3是用于调整M1管的栅极节点的阻抗频率特性，使得M1管具有最佳线性度。这里，R3通常取值为十几欧姆。
信号放大电路12还包括：第三电容C3、第四电容C4、电感L和第三电压源VCC3；
具体连接方式为：M1管的栅极与C3的一端相连，C3的另一端作为信号输入端；M1管的漏极通过L与VCC2相连，还与C4的一端相连，C4的另一端作为信号输出端；M1管的源极接地。
这里，需要说明的是，上述提及的M2管、M3管、M4管和M5管为相同结构的晶体管。另外，M1管与M2管、M3管、M4管和M5管可以是同一结构的晶体管，也可以不是同一结构的晶体管。
针对图2功率放大器的偏置电路的第一组成结构示意图，本申请还提供了一种具体的电路结构图，图6为本申请实施例中功率放大器的偏置电 路的第三组成结构示意图。
如图6所示，功率放大器的偏置电路11包括第一部分电路110、第二部分电路111和电源112。
电源112包括：电流源IBIAS、第一电压源VCC1和第二电压源VCC2。这里，通过VCC2对IBIAS供电。
第一部分电路110包括：第二晶体管M2、第三晶体管M3、第一电阻R1、第一电容C1和第二电阻R2；其中，R2为可变电阻。
具体连接方式为：M2管的漏极通过IBIAS与VCC2相连，M2管的漏极与栅极相连；M2管的源极与第二部分电路111的一端(即M4管的漏极)相连；M2管的栅极通过R1与M3管的栅极相连，还通过C1与R2串联后与接地端相连；M3管的漏极与VCC1相连，M3管的源极与第二部分电路111的另一端(即M5管的漏极)相连，还与M1管的栅极相连。
图7为本申请实施例中可变电阻的结构示意图，如图7所示，该可变电阻中包括n个电阻r和n个开关S。具体连接方式为：r1与S1串联后，并联在r2与S2串联后的两端，依次类推，再并联在rn与Sn串联后的两端。
需要说明的是，在C1上串联可变电阻R2，可以控制M3管上V2节点电压升高的效果强弱，例如，增大R2，V2节点的偏置电压升高的效果将减弱。
第二部分电路111包括：第四晶体管M4、第五晶体管M5、第四电阻R4和第二电容C2；其中，R4为可变电阻，C2为可变电容。
具体连接方式为：M4管的漏极与第一部分电路110的一端(即M2管的源极)相连，M4管的源极接地；M4管的栅极与M5管的栅极相连，还通过C2与接地端相连；M5管的漏极通过R4与M5管的栅极相连，还与第一部分电路110的另一端(即M3管的源极)相连；M5管的源极接地。
图8为本申请实施例中可变电容的结构示意图，如图8所示，该可变 电容中包括n个电容c和n个开关S。具体连接方式为：c1与S1串联后，并联在c2与S2串联后的两端，依次类推，再并联在cn与Sn串联后的两端。
需要说明的是，R4为可变电阻，C2为可变电容，通过改变R4大小和C2大小，控制M5管上V2节点电压降低的效果强弱，例如，增大R4，增大C2，V2节点的偏置电压降低的效果将减弱。
基于上述实施例，通过调整R2、R4和C2的大小，可以实现随着射频信号功率增大，偏置电压可控的升高或降低。这样，在功率放大器中通过选择合适的偏置电压特性可以实现较优化的线性特性。
偏置电路还包括：第三电阻R3；
这里，M3管的源极通过R3与M1管的栅极相连，M5管的漏极通过R3与M1管的栅极相连。
需要说明的是，增加R3是用于调整M1管的栅极节点的阻抗频率特性，使得M1管具有最佳线性度。这里，R3通常取值为十几欧姆。
信号放大电路12还包括：第三电容C3、第四电容C4、电感L和第三电压源VCC3；
具体连接方式为：M1管的栅极与C3的一端相连，C3的另一端作为信号输入端；M1管的漏极通过L与VCC2相连，还与C4的一端相连，C4的另一端作为信号输出端；M1管的源极接地。
图9为本申请实施例中射频功率分别于增益幅度及偏置电压的关系变化示意图，如图9所示，横坐标为射频功率，上面曲线表示射频功率与功率放大器的增益幅度(即AMAM)之间的关系，从AMAM曲线上可以得到1dB功率压缩点P1dB，P1dB作为功率放大器线性度的衡量指标。其中，虚线(即常规偏置)指的是偏置电路中设置固定的电阻和电容(即图3电路中R4和C2)，实线(即较优偏置)指的是偏置电路中设置可变电阻和电 容(即图6电路中R2、R4和C2)。下面部分表示射频功率与偏置电压之间的关系。其中，虚线指的是偏置电路中设置固定的电阻和电容(即常规偏置)，实线指的是偏置电路中设置可变电阻和电容(即较优偏置)。
从图9可以看出，常规偏置下，随着射频功率增大，偏置电压不变，AMAM减小。较优偏置下，通过对偏置电路中可变电阻和电容的调节，随着射频功率增大，偏置电压增大，AMAM也随之升高，进而增大功率放大器的线性度。
另外，设置可变电阻、电容主要是增加对偏置电路线性功率的调试的灵活性，可以在功率放大器制作完成后通过数字控制的方式选取线性度较好的电阻和电容值。例如，功率放大器可以工作在不同频率，各个频率下线性度最优的电阻和电容值不相同，如通过使用可变电阻和电容，在不同频率下设置不同的电阻和电容值，使得功率放大器具有最优的线性度性能。
本申请实施例还公开一种功率放大装置，该功率放大装置包括：功率放大器和上述实施例中任意一项功率放大器的偏置电路。
本申请实施例还公开一种电子设备，该电子设备包括：本申请上述实施例中功率放大装置。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。
工业实用性
本申请公开一种功率放大器的偏置电路、装置及设备，该电路包括：第一部分电路、第二部分电路和电源；电源与第一部分电路电源端相连；第一部分电路两端与第二部分电路两端并联，并联后一端与功率放大器的第一晶体管的栅极相连；第一部分电路、第二部分电路分别对第一晶体管 栅极提供第一偏置电压和第二偏置电压，叠加后提供稳定偏置电压；偏置电路阻抗位于预设阻抗范围。如此，利用第一部分电路为功率放大器提供第一偏置电压，第二部分电路为功率放大器提供第二偏置电压，第二偏置电压能够对第一偏置电压进行调整，为功率放大器提供稳定偏置电压，且偏置电路阻抗位于预设阻抗范围，保证功率放大器线性度性能，及降低功率放大器记忆效应。

Claims (10)

  1. 一种功率放大器的偏置电路，其中，所述偏置电路包括：第一部分电路、第二部分电路和电源；
    所述电源与所述第一部分电路的电源端相连，用于为所述第一部分电路供电；
    所述第一部分电路的两端与所述第二部分电路的两端并联，并联后的一端与信号放大电路中功率放大器的第一晶体管的栅极相连；所述第一部分电路用于对所述第一晶体管的栅极提供第一偏置电压；所述第二部分电路用于对所述第一晶体管的栅极提供第二偏置电压；所述第一偏置电压和所述第二偏置电压叠加后为所述第一晶体管的栅极提供稳定的偏置电压；
    所述偏置电路的阻抗位于预设阻抗范围。
  2. 根据权利要求1所述的电路，其中，
    所述第一部分电路包括：第二晶体管、第三晶体管、第一电阻和第一电容；
    其中，所述第二晶体管的漏极与所述电源相连，所述第二晶体管的漏极与栅极相连；所述第二晶体管的源极与所述第二部分电路的一端相连；所述第二晶体管的栅极通过所述第一电阻与所述第三晶体管的栅极相连，还通过所述第一电容与接地端相连；
    所述第三晶体管的漏极与所述电源相连，所述第三晶体管的源极与所述第二部分电路的另一端相连，还与所述第一晶体管的栅极相连。
  3. 根据权利要求2所述的电路，其中，
    所述第一部分电路还包括：第二电阻；其中，所述第二电阻为可变电阻；
    所述第一电容通过所述第二电阻与接地端相连。
  4. 根据权利要求2所述的电路，其中，
    所述电源包括：电流源、第一电压源和第二电压源；
    所述第一电压源与所述第三晶体管的漏极相连；
    所述第二电压源通过所述电流源与所述第二晶体管的漏极相连。
  5. 根据权利要求2所述的电路，其中，
    所述偏置电路还包括：第三电阻；
    所述第三晶体管的源极通过所述第三电阻与所述第一晶体管的栅极相连。
  6. 根据权利要求1所述的电路，其中，
    所述第二部分电路包括：第四晶体管、第五晶体管、第四电阻和第二电容；
    所述第四晶体管的漏极与所述第一部分电路的一端相连，所述第四晶体管的源极接地；所述第四晶体管的栅极与所述第五晶体管的栅极相连，还通过所述第二电容与接地端相连；
    所述第五晶体管的漏极通过所述第四电阻与所述第五晶体管的栅极相连，还与所述第一部分电路的另一端相连；所述第五晶体管的源极接地。
  7. 根据权利要求6所述的电路，其中，
    所述第四电阻为固定电阻及所述第二电容为固定电容；
    或者，所述第四电阻为可变电阻及所述第二电容为可变电容。
  8. 根据权利要求1所述的电路，其中，
    所述信号放大电路还包括：第三电容、第四电容、电感和第三电压源；
    所述第一晶体管的栅极与所述第三电容的一端相连，所述第三电容的另一端作为信号输入端；所述第一晶体管的漏极通过所述电感与所述第三电压源相连，还与所述第四电容的一端相连，所述第四电容的另一端作为信号输出端；所述第一晶体管的源极接地。
  9. 一种功率放大装置，其中，所述功率放大装置包括：功率放大器和 权利要求1至8中任意一项所述的功率放大器的偏置电路。
  10. 一种电子设备，其中，所述电子设备包括：
    权利要求9中所述的功率放大装置。
PCT/CN2021/132876 2021-02-09 2021-11-24 一种功率放大器的偏置电路、装置及设备 WO2022170816A1 (zh)

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