WO2022170809A1 - 一种适用于多精度计算的可重构浮点乘加运算单元及方法 - Google Patents

一种适用于多精度计算的可重构浮点乘加运算单元及方法 Download PDF

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WO2022170809A1
WO2022170809A1 PCT/CN2021/131745 CN2021131745W WO2022170809A1 WO 2022170809 A1 WO2022170809 A1 WO 2022170809A1 CN 2021131745 W CN2021131745 W CN 2021131745W WO 2022170809 A1 WO2022170809 A1 WO 2022170809A1
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floating
point
operated
precision
unit
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毛伟
余浩
谢歆昂
李凯
李博宇
杜来民
代柳瑶
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Southern University of Science and Technology
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/57—Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations
    • G06F7/575—Basic arithmetic logic units, i.e. devices selectable to perform either addition, subtraction or one of several logical operations, using, at least partially, the same circuitry
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • the invention relates to the field of digital circuits, in particular to a reconfigurable floating-point multiply-add operation unit and method suitable for multi-precision calculation.
  • the technical problem to be solved by the present invention is to provide a reconfigurable floating-point multiply-add operation unit and method suitable for multi-precision calculation, aiming at solving the problem of supporting multi-precision floating point in the prior art
  • the operation method of the multiplication operation will cause problems such as bit redundancy and low hardware utilization.
  • an embodiment of the present invention provides a reconfigurable floating-point multiply-add operation method suitable for multi-precision computing, wherein the method includes:
  • a shift-add operation is performed on the product, and an operation result generated based on the shift-add operation is used as the result of the multiply-accumulate operation of the floating-point number to be operated.
  • the significant number is divided according to the number of bits of the unit multiplier, and after division, several target segments are generated; including one.
  • the number of called unit multipliers is determined according to the precision of the floating-point number to be operated, a target segment is used as an operand of a unit multiplier, and the unit multiplier is obtained based on the Operand-generated products include:
  • a number of row products are generated after the operands are input to the unit multiplier.
  • the determining the number of unit multipliers to be called according to the precision and logarithm of the floating-point number to be operated includes:
  • n calls n unit multipliers for the floating-point number to be operated
  • n When the floating-point number to be operated is a single-precision floating-point number, n calls 4n unit multipliers for the floating-point number to be operated;
  • n 16n unit multipliers for the floating-point number to be operated
  • n is an integer greater than 0.
  • the generating of several row products after the operand is input to the unit multiplier includes:
  • the operand is input into the unit multiplier, and the operand is encoded by the unsigned bit Booth to generate several row products.
  • the floating-point number to be operated is a double-precision floating-point number
  • before the using a target segment as an operand of a unit multiplier further includes:
  • performing a shift-add operation on the product, and using an operation result generated based on the shift-add operation as the result of the multiply-accumulate operation of the floating-point number to be operated includes:
  • the displacement includes at least one of an internal displacement and an external displacement
  • the calculation method of the internal displacement amount is: taking the sum of the high and low bits of the segment numbers divided based on the floating-point number to be operated as the internal shift amount of the product corresponding to the segment number;
  • the calculation method of the external displacement is as follows: adding the exponent parts of the floating-point numbers to be operated to obtain an exponent sum, and taking the maximum value of all the exponent sums obtained as a reference value; The difference obtains the exponent difference, and the exponent difference is used as the external shift amount of the product corresponding to the floating-point number to be operated.
  • an embodiment of the present invention also provides a reconfigurable floating-point multiply-add operation unit suitable for multi-precision computing, characterized in that the operation unit includes:
  • a division module used to obtain the significant digits of the floating-point number to be operated, and generate several target segments based on the significant digits; the several include one;
  • a unit multiplier used for determining the number of unit multipliers to be called according to the precision of the floating-point number to be operated, taking a target segment as an operand of a unit multiplier, and obtaining the unit multiplier generated based on the operand the product of ;
  • An addition tree configured to perform a shift-add operation on the product, and use an operation result generated based on the shift-add operation as a result of the multiply-accumulate operation of the floating-point number to be operated.
  • the operation unit includes 16n unit multipliers, and n is a non-negative number.
  • the embodiment of the present invention avoids the problem of bit redundancy by adopting a unified mantissa division scheme, improves the hardware utilization rate by adopting a unified unit multiplier, and can also realize the multiply-accumulate operation of half-precision floating-point numbers, single The multiply-accumulate operation of precision floating-point numbers and the multiply-accumulate operation of double-precision floating-point numbers. It solves the problems of bit redundancy and low hardware utilization in the operation method supporting multi-precision floating-point multiplication in the prior art.
  • FIG. 1 is a schematic flowchart of a reconfigurable floating-point multiply-add operation method suitable for multi-precision computing according to an embodiment of the present invention.
  • FIG. 2 is a schematic diagram of a division scheme of significant digits of floating-point numbers of different precisions provided by an embodiment of the present invention.
  • FIG. 3 is a schematic diagram of a working principle of a 14-bit basic multiplier provided by an embodiment of the present invention.
  • FIG. 4 is a calculation diagram of 16 groups of products input to an adder tree when a pair of FP64 is calculated according to an embodiment of the present invention.
  • FIG. 5 is an internal basic block diagram of a reconfigurable floating-point multiply-add operation unit suitable for multi-precision calculation provided by an embodiment of the present invention.
  • FIG. 6 is a reference diagram of a minimum operation unit that can implement mantissa multiply-accumulate operations of three types of floating-point numbers of different precisions provided by an embodiment of the present invention.
  • the architecture is based on a 15-bit multiplier, which is optimized to support FP128-precision floating-point multiplication, but uses When performing floating-point multiplication operations of other precisions, a large amount of bit redundancy and waste of hardware resources will be generated.
  • the fixed-point multiplier has a fixed number of input bits, which cannot meet the requirements of multi-precision computing, and cannot maximize the use of hardware resources for application requirements to improve energy efficiency ratio and throughput; while the existing ones support multi-precision floating-point.
  • the multiplication operation method also has problems such as loss of precision, bit redundancy, and low hardware utilization.
  • the present invention provides a reconfigurable floating-point multiply-add operation method suitable for multi-precision calculation.
  • a reconfigurable floating-point multiply-add operation method suitable for multi-precision calculation.
  • the invention adopts a unified mantissa division scheme to avoid the problem of bit redundancy, adopts a unified unit multiplier to improve the hardware utilization rate, and can also realize the multiply-accumulate operation of half-precision floating-point numbers, the multiply-accumulate operation of single-precision floating-point numbers, and the double-accumulation operation of double-precision floating-point numbers. Multiply-accumulate operation of precision floating-point numbers. It solves the problems of bit redundancy and low hardware utilization in the operation method supporting multi-precision floating-point multiplication in the prior art.
  • the method includes the following steps:
  • Step S100 Obtain the significant digits of the floating-point number to be operated, and generate several target segments based on the significant digits; the several target segments include one.
  • the exponent part of the multiplication result is the sum of the exponent parts of the two floating-point numbers to be multiplied
  • the mantissa part of the multiplication result is the product of the mantissas of the two multiplied floating-point numbers.
  • the present embodiment needs to obtain the significant digits of the floating-point number to be operated, and the significant digits refer to the data that needs to participate in the multiplication operation in the mantissa of the floating-point number to be operated. Only the significant digits that need to participate in the multiplication operation are determined first, Subsequent multiplication operations can be performed. After the significant figures are obtained, this embodiment needs to generate one or more target segments based on the significant figures, and then use the target segments as input data of the unit multiplier.
  • the step S100 includes the following steps:
  • Step S110 adding a 1-bit integer to the mantissa part of the floating-point number to be operated;
  • Step S120 taking the number on the significant digits of the floating-point number obtained after adding as the significant number of the floating-point number to be operated;
  • Step S130 when the number of bits of the significant figure is greater than the number of bits of the unit multiplier, divide the significant number according to the number of bits of the unit multiplier, and generate several target segments after division; The several include one.
  • a 1-bit integer needs to be added to the mantissa part of the floating-point number to be calculated, and then the significant digits of the floating-point number obtained after adding are added.
  • the number is used as the significant figure of the floating point number to be operated on.
  • the significant number of digits is 11; for a single-precision floating point number (floating point 32-bit number, FP32)
  • the mantissa After adding a 1-bit integer to the part, the significand is 24 bits; for a double-precision floating point number (floating point 64-bit number, FP64), after adding a 1-bit integer to the mantissa, the significand is 53 bits.
  • the target segment needs to be obtained according to the significant figures, and the target segment is used as the input data of the subsequent unit multiplier.
  • the significant number may be directly input into the unit multiplier as a target segment.
  • the unit multiplier is a 14-bit basic unit multiplier
  • the significant figures of the 16-bit floating-point numbers have only 11 bits, so there is no need to divide the significant figures of the 16-bit floating-point numbers. Use it directly as a target segment.
  • the significant figure of a 32-bit floating point number is 24 bits, so the significant figure needs to be divided to generate two 12-bit target segments.
  • the significant figure of a 64-bit floating point number is 53 bits, so the significant figure also needs to be divided, and then 4 target segments of 14:13:13:13 are generated.
  • the target segment After the target segment is acquired, the target segment needs to be input into the unit multiplier, so as shown in FIG. 1 , the method further includes the following steps:
  • Step S200 Determine the number of called unit multipliers according to the precision of the floating-point number to be operated, take a target segment as an operand of a unit multiplier, and obtain a product generated by the unit multiplier based on the operand.
  • the number of called unit multiplications needs to be determined according to the precision of the floating-point number to be operated. Then use the obtained target segment as an operand of a unit multiplier. It can be understood that a unit multiplier needs two operands to perform multiplication, one operand is used as a multiplier, and the other operand is used as a multiplicand . The product generated by the unit multiplier based on the operands is then obtained. In multiplication, if the multiplier is a number with two or more digits, when multiplying, each digit of the multiplier must be used to multiply the multiplicand, and the product obtained each time is called the product, or called incomplete. product.
  • the step S200 specifically includes the following steps:
  • Step 210 determining the number of called unit multipliers according to the precision of the floating-point number to be operated
  • Step 220 using a target segment as an operand of a unit multiplier
  • Step 230 Input the operand into the unit multiplier to generate several row products.
  • the determining the number of unit multipliers to call according to the precision and logarithm of the floating-point number to be operated includes: when the to-be-operated floating-point number is When the floating-point number is a half-precision floating-point number, n calls n-unit multipliers for the floating-point number to be operated; when the floating-point number to be operated is a single-precision floating-point number, n calls 4n-unit multipliers for the floating-point number to be operated; When the floating-point number to be operated is a double-precision floating-point number, n calls 16n unit multipliers for the floating-point number to be operated; n is an integer greater than 0.
  • the unit multiplier is a 14-bit basic unit multiplier
  • the unit multiplier when you need to calculate the multiplication and accumulation results of 16 pairs of half-precision floating-point numbers at the same time, you need to call 16 14-bit basic unit multipliers for the following reasons.
  • the embodiment is to divide the significant figures based on the number of bits of the unit multiplier, and the significant figures of the half-precision floating-point numbers can be directly used as a target segment.
  • a pair of half-precision floating-point numbers needs to call a 14-bit basic unit multiplier, and a total of 16 14-bit basic unit multipliers need to be called.
  • a target segment since it is possible to generate target segments with unequal number of bits after the significant digits are divided, in an implementation manner, before using a target segment as an operand of a unit multiplier, it further includes: when the to-be-to-be-multiplier is used When the number of bits of the target segment to which the floating-point number should be operated is not equal, a complementing operation is performed on the target segment with the smallest number of bits, and the complementing operation may be implemented in the form of zero-filling.
  • the unit multiplier is a 14-bit basic unit multiplier
  • the significant figure corresponding to the double-precision floating-point number is 53 bits
  • the four target ends of 14:13:13:13 generated after division need to The 13-bit target segment is zero-padded.
  • a target segment is then used as one operand of a unit multiplier, after which several row products generated by the unit multiplier are taken. Specifically, after the operand is input to the unit multiplier, the unit multiplier encodes the operand through an unsigned bit booth and generates several row products (as shown in FIG. 3 ). .
  • the method further includes the following steps:
  • Step S300 Perform a shift-add operation on the product, and use an operation result generated based on the shift-add operation as a result of the multiply-accumulate operation of the floating-point number to be operated.
  • step S300 specifically includes the following steps:
  • Step S310 inputting the product into a preset addition tree
  • Step S320 calculating the displacement of the product, and performing a shift operation on the product according to the displacement through the addition tree;
  • Step S330 performing a summation operation on the data obtained after the shift operation to obtain a result of the multiply-accumulate operation of the floating-point number to be operated.
  • an addition tree is preset for the scheme of generating the target segment and the usage of the unit multiplier, so as to realize the lossless processing of the data. Specifically, after the product is obtained, the product is input into the addition tree, then the displacement of the product is calculated in the addition tree, and then the product is shifted according to the displacement. .
  • the displacement calculated in the addition tree includes at least one of an internal displacement and an external displacement, that is, it may include only the internal displacement, only the external displacement, or both the internal displacement The final value of the displacement amount needs to be determined according to the precision of the floating point number to be operated and the logarithm of the calculation.
  • the calculation method of the internal displacement amount is to use the sum of the high and low bits of the segment numbers divided based on the floating-point number to be operated as the internal shift amount of the product corresponding to the segment numbers.
  • the calculation method of the external displacement is as follows: adding the exponent parts of the floating-point numbers to be operated to obtain an exponent sum, taking the maximum value of all exponent sums obtained as a reference value, and then adding the reference value to the exponent sum. A difference is obtained to obtain an exponent difference, and finally the exponent difference is used as the external shift amount of the product corresponding to the floating-point number to be operated.
  • 16 14-bit basic unit multipliers need to be called. Since the significant digits of half-precision floating-point numbers are not divided, it is necessary to calculate the multiplication of multiple pairs of floating-point numbers at the same time. The result of multiply-accumulate operation, so in this case, the displacement of the product is only the external displacement.
  • the displacement of the product in this case includes both the internal displacement and the external displacement.
  • the displacement of the product only includes the internal displacement.
  • a 1 ⁇ b 0 results in a displacement of 1 ⁇ 14bit
  • the resulting displacement is 2 ⁇ 14bit ( As shown in Figure 4).
  • the present invention also provides a reconfigurable floating-point multiply-add operation unit suitable for multi-precision calculation.
  • the operation unit includes:
  • a division module 01 is used to obtain the significant figures of the floating-point numbers to be operated, and generate several target segments based on the significant figures; the several include one;
  • Unit multiplier 02 for determining the number of unit multipliers to be called according to the precision of the floating-point number to be operated, taking a target segment as an operand of a unit multiplier, and obtaining the unit multiplier based on the operand the resulting product;
  • the addition tree 03 is configured to perform a shift-add operation on the product, and use the operation result generated based on the shift-add operation as the result of the multiply-accumulate operation of the floating-point number to be operated.
  • the operation unit in order to enable the operation unit to realize the multiply-accumulate operation of half-precision floating-point numbers, single-precision floating-point numbers and double-precision floating-point numbers, the operation unit includes 16n unit multipliers, and n is a non-negative number .
  • each unit multiplier can realize 1 set of half-precision floating-point multiplication operations, so 16 pairs of half-precision can be realized at the same time Multiplication and accumulation of floating-point numbers. Every 4 unit multipliers can realize 1 set of single-precision floating-point multiplication operations, so it can also realize the multiply-accumulate operation of 4 pairs of single-precision floating-point numbers at the same time.
  • the 16 unit multipliers can realize a set of double-precision floating-point multiplication operations, so it can also realize a multiply-accumulate operation of a pair of double-precision floating-point numbers.
  • FIG. 6 is a reference diagram of a minimum operation unit provided by the present invention that can realize the multiply-accumulate operation of three floating-point numbers of different precisions. Therefore, the embodiments of the present invention can at least complete the multiply-accumulate operations of multiple pairs of half-precision floating-point numbers, the multiply-accumulate operations of multiple pairs of single-precision floating-point numbers, or the multiply-accumulate operations of one pair of double-precision floating-point numbers within one clock cycle without limiting hardware resources. Multiply and accumulate operations. Compared with the fixed FP32 and FP64 multiply-add units, the arithmetic unit provided by the present invention can increase the maximum throughput rate by 4 times and 16 times respectively.
  • the present invention discloses a reconfigurable floating-point multiply-add operation unit and method suitable for multi-precision calculation.
  • a reconfigurable floating-point multiply-add operation unit By adopting a unified method to divide the mantissas of floating-point numbers of different precisions, a plurality of bit segments are obtained. , and call different numbers of the same type of unit multipliers to complete the multiplication operation of multiple bit segments in one cycle and output the corresponding product, and then perform the shift and addition operation on the product to obtain the multiplication and accumulation of floating-point numbers. Operation result.
  • the invention adopts a unified mantissa division scheme to avoid the problem of bit redundancy, adopts a unified unit multiplier to improve the hardware utilization rate, and can also realize the multiply-accumulate operation of half-precision floating-point numbers, the multiply-accumulate operation of single-precision floating-point numbers, and the double-accumulation operation of double-precision floating-point numbers. Multiply-accumulate operation of precision floating-point numbers. It solves the problems of bit redundancy and low hardware utilization in the operation method supporting multi-precision floating-point multiplication in the prior art.

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Abstract

本发明公开了一种适用于多精度计算的可重构浮点乘加运算单元及方法，通过采用统一的方法对不同精度的浮点的尾数进行划分，得到多个比特段，并调用不同数量的同一类单元乘法器在一个周期内实现多个比特段的乘法运算并输出对应的乘积，然后对所述乘积进行移位相加操作后即可得到浮点数的乘累加运算结果。本发明采用统一的尾数划分方案避免了比特冗余的问题，采用统一的单元乘法器提高了硬件利用率，还可以实现半精度浮点数的乘累加运算、单精度点积浮点数的乘累加运算和双精度浮点数的乘累加运算。解决了现有技术中支持多精度浮点乘法运算的运算方法会产生比特冗余、硬件利用率低等情况的问题。

Description

一种适用于多精度计算的可重构浮点乘加运算单元及方法 技术领域
本发明涉及数字电路领域，尤其涉及的是一种适用于多精度计算的可重构浮点乘加运算单元及方法。
背景技术
随着科学计算和机器学习训练等的高速发展与广泛应用，能够支持浮点数据处理的乘法单元应运而生。常规定点乘法器的输入比特数固定，不能满足多精度计算的要求，因此出现了支持多精度浮点乘法运算的方法。然而现有的支持多精度浮点乘法运算的运算方法由于需要多种尾数划分方案以及需要将产生的乘积用补零方法分离为两个并行部分，因此存在精度损失以及比特冗余、硬件利用率低等问题。
因此，现有技术还有待改进和发展。
发明内容
本发明要解决的技术问题在于，针对现有技术的上述缺陷，提供一种适用于多精度计算的可重构浮点乘加运算单元及方法，旨在解决现有技术中支持多精度浮点乘法运算的运算方法会产生比特冗余、硬件利用率低等情况的问题。
本发明解决问题所采用的技术方案如下：
第一方面，本发明实施例提供一种适用于多精度计算的可重构浮点乘加运算方法，其中，所述方法包括：
获取待运算浮点数的有效数字，基于所述有效数字生成若干个目标段；所述若干个包括一个；
根据所述待运算浮点数的精度确定调用的单元乘法器的个数，将一个目标段作为一个单元乘法器的操作数，获取所述单元乘法器基于所述操作数生成的乘积；
对所述乘积进行移位相加操作，并将基于所述移位相加操作生成的运算结果作为所述待运算浮点数的乘累加运算的结果。
在一种实施方式中，所述获取待运算浮点数的有效数字，基于所述有效数字生成若干个目标段；所述若干个包括一个，包括：
在所述待运算浮点数的尾数部分添加1比特整数；
将添加完毕以后得到的浮点数的有效位数上的数字作为所述待运算浮点数的有效数字；
当所述有效数字的比特位数大于所述单元乘法器的比特位数时，根据所述单元乘法器的比特位数对所述有效数字进行划分，划分后生成若干个目标段；所述若干个包括一个。
在一种实施方式中，所述根据所述待运算浮点数的精度确定调用的单元乘法器的个数，将一个目标段作为一个单元乘法器的操作数，获取所述单元乘法器基于所述操作数生成的乘积包括：
根据所述待运算浮点数的精度确定调用的单元乘法器的个数；
将一个目标段作为一个单元乘法器的一个操作数；
将所述操作数输入所述单元乘法器后生成若干行乘积。
在一种实施方式中，当所述单元乘法器为14比特乘法器时，所述根据所述待运算浮点数的精度和对数确定调用的单元乘法器的个数包括：
当所述待运算浮点数为半精度浮点数时，n对待运算浮点数调用n个单元乘法器；
当所述待运算浮点数为单精度浮点数时，n对待运算浮点数调用4n个单元乘法器；
当所述待运算浮点数为双精度浮点数时，n对待运算浮点数调用16n个单元乘法器；
n为大于0的整数。
在一种实施方式中，所述将所述操作数输入所述单元乘法器后生成若干行乘积包括：
将所述操作数输入所述单元乘法器中，通过无符号位布斯对所述操作数进行编码后生成若干行乘积。
在一种实施方式中，当所述待运算浮点数为双精度浮点数时，所述将一个目标段作为一个单元乘法器的一个操作数之前还包括：
当所述待运算浮点数应的目标段的比特位数不相等时，对比特位数最小的目标段进行补位操作。
在一种实施方式中，所述对所述乘积进行移位相加操作，并将基于所述移位相加操作生成的运算结果作为所述待运算浮点数的乘累加运算的结果包括：
将所述乘积输入预设的加法树中；
计算所述乘积的位移量，通过所述加法树根据所述位移量对所述乘积进行移位操作；
对所述移位操作后得到的数据进行求和操作后得到所述待运算浮点数的乘累加运算的结果。
在一种实施方式中，所述位移量包括内部位移量以及外部位移量中至少一种位移量；
所述内部位移量的计算方式为：将基于所述待运算浮点数划分出的段数的高低位之和作为所述段数对应的乘积的内部移位量；
所述外部位移量的计算方式为：将所述待运算浮点数的指数部分相加得到指数和，将得到的所有指数和的最大值作为参考值；将所述参考值与所述指数和作差得到指数差，将所述指数差作为所述待运算浮点数对应的乘积的外部移位量。
第二方面，本发明实施例还提供一种适用于多精度计算的可重构浮点乘加运算单元，其特征在于，所述运算单元包括：
划分模块，用于获取待运算浮点数的有效数字，基于所述有效数字生成若干个目标段；所述若干个包括一个；
单元乘法器，用于根据所述待运算浮点数的精度确定调用的单元乘法器的个数，将一个目标段作为一个单元乘法器的操作数，获取所述单元乘法器基于所述操作数生成的乘积；
加法树，用于对所述乘积进行移位相加操作，并将基于所述移位相加操作生成的运算结果作为所述待运算浮点数的乘累加运算的结果。
在一种实施方式中，所述运算单元中包含16n个单元乘法器，n为非负数。
本发明的有益效果：本发明实施例通过采用统一的尾数划分方案避免了比特冗余的问题，采用统一的单元乘法器提高了硬件利用率，还可以实现半精度浮点数的乘累加运算、单精度浮点数的乘累加运算和双精度浮点数的乘累加运算。解决了现有技术中支持多精度浮点乘法运算的运算方法会产生比特冗余、硬件利用率低等情况的问题。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明中记载的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本发明实施例提供的一种适用于多精度计算的可重构浮点乘加运算方法的流程示意图。
图2是本发明实施例提供的不同精度的浮点数的有效数字的划分方案的示意图。
图3是本发明实施例提供的14比特基本乘法器的工作原理示意图。
图4是本发明实施例提供的计算一对FP64时，16组乘积输入加法器树的计算图。
图5是本发明实施例提供的一种适用于多精度计算的可重构浮点乘加运算单元的内部基本模块图。
图6是本发明实施例提供的可以实现3种不同精度的浮点数的尾数乘累加运算的最小运算单元的参考图。
具体实施方式
为使本发明的目的、技术方案及优点更加清楚、明确，以下参照附图并举实施例对本发明进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本发明，并不用于限定本发明。
需要说明，若本发明实施例中有涉及方向性指示(诸如上、下、左、右、前、后……)，则该方向性指示仅用于解释在某一特定姿态(如附图所示)下各部件之间的相对位置关系、运动情况等，如果该特定姿态发生改变时，则该方向性指示也相应地随之改变。
随着科学计算和机器学习训练等的高速发展与广泛应用，能够支持浮点数据处理的乘法单元应运而生。常规定点乘法器的输入比特数固定，不能满足多精度计算的要求，无法针对应用需求，最大化的利用硬件资源从而提高能效比和吞吐率。因此产生了多精度浮点乘法运算的方法。然而部分现有的支持多精度浮点乘法运算的方法在实现多精度乘法时，需要将产生的乘积用补零方法分离为两个并行部分，进而导致系统模块的利用率降低；还有部分现有的支持多精度浮点乘法运算的方法在实现多精度乘法时，需要采用不同的尾数划分方案，如使架构基于15位乘法器，其优化用以支持FP128精度的浮点乘法运算，但用于其他精度的浮点乘法运算时，将会产生了大量的比特冗余和硬件资源浪费。简言之，常规定点乘法器的输入比特数固定，不能满足多精度计算的要求，无法针对应用需求，最大化的利用硬件资源从而提高能效比和吞吐率；而现有的支持多精度浮点乘法运算的运算方法又存在精度损失以及比特冗余、硬件利用率低等问题。
基于现有技术的上述缺陷，本发明提供一种适用于多精度计算的可重构浮点乘加运算方法，通过采用统一的方法对不同精度的浮点的尾数进行划分，得到多个比特段，并调用不同数量的同一类单元乘法器实现多个比特段的乘法运算在一个周期内完成并输出对应的乘积，然后对所述乘积进行移位相加操作后即可得到浮点的尾数相乘的运算结果。本发明采用统一的尾数划分方案避免了比特冗余的问题，采用统一的单元乘法器提高了硬件利用率，还可以实现半精度浮点数的乘累加运算、单精度浮点数的乘累加运算 和双精度浮点数的乘累加运算。解决了现有技术中支持多精度浮点乘法运算的运算方法会产生比特冗余、硬件利用率低等情况的问题。
如图1所示，所述方法包括如下步骤：
步骤S100、获取待运算浮点数的有效数字，基于所述有效数字生成若干个目标段；所述若干个包括一个。
在浮点数的乘法运算中，乘法运算结果的指数部分为相乘的两个浮点数的指数部分之和，乘法运算结果的尾数部分为相乘的两个浮点数的尾数之积。本实施例主要是针对浮点数的乘法运算中生成乘法运算结果的尾数部分，即相乘的两个浮点数的尾数之积的方法进行优化。具体地，首先本实施例需要获取待运算浮点数的有效数字，所述有效数字指的是待运算浮点数的尾数中需要参与乘法运算的数据，只有首先确定了需要参与乘法运算的有效数字，才能进行后续的乘法运算。获取到所述有效数字以后，本实施例需要基于所述有效数字生成一个或者多个目标段，然后再将所述目标段作为单元乘法器的输入数据。
所述步骤S100包括如下步骤：
步骤S110、在所述待运算浮点数的尾数部分添加1比特整数；
步骤S120、将添加完毕以后得到的浮点数的有效位数上的数字作为所述待运算浮点数的有效数字；
步骤S130、当所述有效数字的比特位数大于所述单元乘法器的比特位数时，根据所述单元乘法器的比特位数对所述有效数字进行划分，划分后生成若干个目标段；所述若干个包括一个。
具体地，为了获取到所述待运算浮点数的有效数字，本实施例首先需要在所述待运算浮点数的尾数部分添加1比特整数，然后将添加完毕以后得到的浮点数的有效位上的数字作为所述待运算浮点数的有效数字。举例说明，对于半精度浮点数(浮点16比特，FP16)的尾数部分加上1比特整数后，其有效位数为11位；对于单精度浮点数(浮点32 比特数，FP32)的尾数部分加上1比特整数后，其有效位数为24位；对于双精度浮点数(浮点64比特数，FP64)的尾数部分加上1比特整数后，其有效位数为53位。获取到有效数字以后，本实施例还需要根据所述有效数字得到目标段，并将所述目标段作为后续单元乘法器的输入数据。
具体地，本实施例需要比较所述有效数字的比特位数与所述单元乘法器的比特位数，并最终判断应该对所述有效数字进行何种处理，进而生成目标段。当所述有效数字的比特位数小于或者等于所述单元乘法器的比特位数时，可以直接将所述有效数字作为目标段输入所述单元乘法器中。举例说明，如图2所示，当所述单元乘法器为14位基本单元乘法器时，16比特浮点数的有效数字只有11位，因此不需要对16比特浮点数的有效数字进行划分，可以直接将其作为一个目标段。
当所述有效数字的比特位数大于所述单元乘法器的比特位数时，很明显无法将所述有效数字直接输入所述单元乘法器中，因此需要对所述有效数字进行划分，再将划分后生成的若干个目标段输入单元乘法器中。举例说明，当所述单元乘法器为14位基本单元乘法器时，32比特浮点数的有效数字为24位，因此需要对该有效数字进行划分，生成2个12比特的目标段。同理可得，64比特浮点数的有效数字为53位，因此也需要对该有效数字进行划分，进而生成14：13：13：13的4个目标段。
获取到目标段以后，需要将所述目标段输入单元乘法器，因此如图1所示，所述方法还包括如下步骤：
步骤S200、根据所述待运算浮点数的精度确定调用的单元乘法器的个数，将一个目标段作为一个单元乘法器的操作数，获取所述单元乘法器基于所述操作数生成的乘积。
本实施例首先需要根据所述待运算浮点数的精度确定调用的单位乘法的个数。然后将得到的一个目标段作为一个单元乘法器的一个操作数，可以理解的是一个单元乘法器需要两个操作数才能进行乘法运算，一个操作数作为乘数，另一个操作数作为被乘数。然后获取所述单元乘法器基于所述操作数生成的乘积。在乘法中，如果乘数是两位或两 位以上的数，乘的时候，就要用乘数的每一位去乘被乘数，每次乘得的积，叫做乘积，或叫做不完全积。
所述步骤S200具体包括如下步骤：
步骤210、根据所述待运算浮点数的精度确定调用的单元乘法器的个数；
步骤220、将一个目标段作为一个单元乘法器的一个操作数；
步骤230、将所述操作数输入所述单元乘法器后生成若干行乘积。
本实施例中首先需要确定调用的单元乘法器的个数。在一种实现方式中，当所述单元乘法器为14比特乘法器时，所述根据所述待运算浮点数的精度和对数确定调用的单元乘法器的个数包括：当所述待运算浮点数为半精度浮点数时，n对待运算浮点数调用n个单元乘法器；当所述待运算浮点数为单精度浮点数时，n对待运算浮点数调用4n个单元乘法器；当所述待运算浮点数为双精度浮点数时，n对待运算浮点数调用16n个单元乘法器；n为大于0的整数。
举例说明，假设所述单元乘法器为14比特基本单元乘法器，当需要同时计算16对半精度浮点数的乘累加运算结果时，需要调用16个14比特基本单元乘法器，理由如下，因为本实施例是基于单元乘法器的比特位数对所述有效数字进行划分，半精度浮点数的有效数字可以直接作为一个目标段，因此同时计算16对半精度浮点数的乘累加运算结果时，每一对半精度浮点数需要调用1个14比特基本单元乘法器，一共需要调用16个14比特基本单元乘法器。同理，当需要同时计算4对单精度浮点数的乘累加运算结果时，也需要调用16个14比特基本单元乘法器。因为单精度浮点数的有效数字需要划分后才能输入单元乘法器中，其划分结果是生成2个目标段，则1对单精度浮点数对应的4个目标段之间有2*2＝4种乘法组合方式，即需要4个单元乘法器，则4对单精度浮点数的乘累加运算就需要4*4＝16个单元乘法器。同理当需要同时计算1对双精度浮点数的乘累加运算结果时，也需要调用16个14比特基本单元乘法器，理由如下，因为双精度浮点数的有效数字划分后生成4个目标段，则1对双精度浮点数对应的8个目标段之间有4*4＝16种乘法组 合方式，因此一共需要16个14比特基本单元乘法器。
此外，由于对有效数字进行划分后有可能生成比特位数不相等的目标段，因此在一种实现方式中，将一个目标段作为一个单元乘法器的一个操作数之前还包括：当所述待运算浮点数应的目标段的比特位数不相等时，对比特位数最小的目标段进行补位操作，所述补位操作可以以补零的方式实现。举例说明，当所述单元乘法器为14比特基本单元乘法器时，双精度浮点数对应的有效数字为53位，划分后生成的14：13：13：13的4个目标端，则需要对13比特的目标段进行补零操作。
然后将一个目标段作为一个单元乘法器的一个操作数，之后获取所述单元乘法器生成的若干行乘积。具体地，所述操作数输入到单元乘法器以后，在所述单元乘法器里会通过无符号位布斯(booth)对所述操作数进行编码后生成若干行乘积(如图3所示)。
获取到乘积以后，为了获得浮点数的乘累加运算的结果，如图1所示，所述方法还包括如下步骤：
步骤S300、对所述乘积进行移位相加操作，并将基于所述移位相加操作生成的运算结果作为所述待运算浮点数的乘累加运算的结果。
本实施例获取到单元乘法器输出的乘积以后，为了获取到准确的乘法运算结果，还需要对得到的乘积进行移位相加操作以后，再将移位相加操作后的运算结果作为所述待运算浮点数的乘累加运算的结果。
在一种实现方式中，所述步骤S300具体包括如下步骤：
步骤S310、将所述乘积输入预设的加法树中；
步骤S320、计算所述乘积的位移量，通过所述加法树根据所述位移量对所述乘积进行移位操作；
步骤S330、对所述移位操作后得到的数据进行求和操作后得到所述待运算浮点数的乘累加运算的结果。
本实施例针对生成目标段的方案以及单元乘法器的使用情况，预先设置了一个加法 树，以实现数据的无损处理。具体地，获取到乘积以后，将所述乘积输入到所述加法树中，然后在所述加法树中计算出所述乘积的位移量，再根据所述位移量对所述乘积进行移位操作。具体地，所述加法树中计算出的位移量包括内部位移量以及外部位移量中至少一种位移量，即可以仅包括内部位移量，也可以仅包括外部位移量，还可以同时包括内部位移量和外部位移量，位移量的最终值需要具体根据待运算浮点数的精度以及计算对数确定。其中，所述内部位移量的计算方式为将基于所述待运算浮点数划分出的段数的高低位之和作为所述段数对应的乘积的内部移位量。所述外部位移量的计算方式为：将所述待运算浮点数的指数部分相加得到指数和，将得到的所有指数和的最大值作为参考值，然后将所述参考值与所述指数和作差得到指数差，最后将所述指数差作为所述待运算浮点数对应的乘积的外部移位量。
简言之，当同时计算多对浮点数的时候，则浮点数本身指数部分的数字需要作为外部位移量。当对所述有效数字进行划分后，由于调用了不同的单元乘法器进行运算，虽然每一个单元乘法器输出乘积的比特位数相同，但是需要将划分出的段数的高低位之和作为内部位移量，并进行相应的高低位移位后再累加才可生成正确的浮点数的乘累加运算结果。
举例说明，同时计算16对半精度浮点数的乘累加运算结果，需要调用16个14比特基本单元乘法器，由于半精度浮点数的有效数字并未进行划分，但是需要同时计算多对浮点数的乘累加运算结果，因此在这种情况下乘积的位移量只有外部位移量，首先查询16对半精度浮点数的16个指数和，将16个指数和中的最大的和作为参考值，将所述参考值分别减去16个不同的指数和，以此得到外部位移量。
当同时计算4对单精度浮点数的乘累加运算结果时，由于单精度浮点数的有效数字是经过划分以后才输入单元乘法器中的，且需要同时计算多对浮点数的乘累加运算结果，因此这种情况下乘积的位移量既包含内部位移量也包含外部位移量。首先查询4对单精度浮点数的4个指数和，将4个指数和中的最大的和作为参考值，然后将所述参考值 分别减去4个不同的指数和，以此得到外部位移量。此外，还需要将基于所述待运算浮点数划分出的段数的高低位之作为所述段数对应的乘积的内部移位量，例如a 0×b 0的段数和位0+0＝0，则内部位移量为0；a 1×b 0的段数和位1+0＝1，则内部位移量为向左移位1×14＝14位；a 3×b 1的段数和位3+1＝4，则内部位移量为向左移位4×14＝56位。
当计算1对双精度浮点数的乘累加运算结果时，由于双精度浮点数的有效数字是经过划分以后才输入单元乘法器中的，但是只需要计算1对浮点数的乘累加运算结果，因此这种情况下乘积的位移量只包含内部位移量，例如a 1×b 0结果移位量为1×14bit、a 1×b 1及a 2×b 0结果移位量均为2×14bit(如图4所示)。
计算出乘积的位移量以后，根据所述位移量对所述乘积进行移位操作，然后对所述移位操作后得到的数据进行求和操作以后，即可得到所述待运算浮点数的乘累加运算的结果。
基于上述实施例，本发明还提供一种适用于多精度计算的可重构浮点乘加运算单元，如图5所示，所述运算单元包括：
划分模块01，用于获取待运算浮点数的有效数字，基于所述有效数字生成若干个目标段；所述若干个包括一个；
单元乘法器02，用于根据所述待运算浮点数的精度确定调用的单元乘法器的个数，将一个目标段作为一个单元乘法器的操作数，获取所述单元乘法器基于所述操作数生成的乘积；
加法树03，用于对所述乘积进行移位相加操作，并将基于所述移位相加操作生成的运算结果作为所述待运算浮点数的乘累加运算的结果。
在一种实现方式中，为了使所述运算单元可以实现半精度浮点数、单精度浮点数以及双精度浮点数的乘累加运算，所述运算单元中包含16n个单元乘法器，n为非负数。举例说明，如图6所示，当所述运算单元中包含16个14比特基本单元乘法器时，每个单元乘法器可以实现1组半精度浮点数乘法运算，因此可以同时实现16对半精度浮点数的乘 累加运算。每4个单元乘法器可以实现1组单精度浮点数乘法运算，因此还可以同时实现4对单精度浮点数的乘累加运算。16个单元乘法器可以实现1组双精度浮点数乘法运算，因此还可以实现1对双精度浮点数的乘累加运算。图6是本发明提供的可以实现3种不同精度的浮点数的乘累加运算的最小运算单元的参考图。因此本发明实施例可在无限制硬件资源的情况下在一个时钟周期内至少完成多对半精度浮点数的乘累加运算、多对单精度浮点数的乘累加运算或者1对双精度浮点数的乘累加运算。与固定的FP32和FP64乘加单元相比，本发明提供的运算单元可分别提高4倍和16倍的最大吞吐率。
综上所述，本发明公开了一种适用于多精度计算的可重构浮点乘加运算单元及方法，通过采用统一的方法对不同精度的浮点的尾数进行划分，得到多个比特段，并调用不同数量的同一类单元乘法器实现多个比特段的乘法运算在一个周期内完成并输出对应的乘积，然后对所述乘积进行移位相加操作后即可得到浮点数的乘累加运算结果。本发明采用统一的尾数划分方案避免了比特冗余的问题，采用统一的单元乘法器提高了硬件利用率，还可以实现半精度浮点数的乘累加运算、单精度浮点数的乘累加运算和双精度浮点数的乘累加运算。解决了现有技术中支持多精度浮点乘法运算的运算方法会产生比特冗余、硬件利用率低等情况的问题。
应当理解的是，本发明的应用不限于上述的举例，对本领域普通技术人员来说，可以根据上述说明加以改进或变换，所有这些改进和变换都应属于本发明所附权利要求的保护范围。

Claims (10)

  1. 一种适用于多精度计算的可重构浮点乘加运算方法，其特征在于，所述方法包括：
    获取待运算浮点数的有效数字，基于所述有效数字生成若干个目标段；所述若干个包括一个；
    根据所述待运算浮点数的精度确定调用的单元乘法器的个数，将一个目标段作为一个单元乘法器的操作数，获取所述单元乘法器基于所述操作数生成的乘积；
    对所述乘积进行移位相加操作，并将基于所述移位相加操作生成的运算结果作为所述待运算浮点数的乘累加运算的结果。
  2. 根据权利要求1所述的一种适用于多精度计算的可重构浮点乘加运算方法，其特征在于，所述获取待运算浮点数的有效数字，基于所述有效数字生成若干个目标段；所述若干个包括一个包括：
    在所述待运算浮点数的尾数部分添加1比特整数；
    将添加完毕以后得到的浮点数的有效位数上的数字作为所述待运算浮点数的有效数字；
    当所述有效数字的比特位数大于所述单元乘法器的比特位数时，根据所述单元乘法器的比特位数对所述有效数字进行划分，划分后生成若干个目标段；所述若干个包括一个。
  3. 根据权利要求1所述的一种适用于多精度计算的可重构浮点乘加运算方法，其特征在于，所述根据所述待运算浮点数的精度确定调用的单元乘法器的个数，将一个目标段作为一个单元乘法器的操作数，获取所述单元乘法器基于所述操作数生成的乘积包括：
    根据所述待运算浮点数的精度确定调用的单元乘法器的个数；
    将一个目标段作为一个单元乘法器的一个操作数；
    将所述操作数输入所述单元乘法器后生成若干行乘积。
  4. 根据权利要求3所述的一种适用于多精度计算的可重构浮点乘加运算方法，其特征在于，当所述单元乘法器为14比特乘法器时，所述根据所述待运算浮点数的精度和对数 确定调用的单元乘法器的个数包括：
    当所述待运算浮点数为半精度浮点数时，n对待运算浮点数调用n个单元乘法器；
    当所述待运算浮点数为单精度浮点数时，n对待运算浮点数调用4n个单元乘法器；
    当所述待运算浮点数为双精度浮点数时，n对待运算浮点数调用16n个单元乘法器；
    n为大于0的整数。
  5. 根据权利要求3所述的一种适用于多精度计算的可重构浮点乘加运算方法，其特征在于，所述将所述操作数输入所述单元乘法器后生成若干行乘积包括：
    将所述操作数输入所述单元乘法器中，通过无符号位布斯对所述操作数进行编码后生成若干行乘积。
  6. 根据权利要求3所述的一种适用于多精度计算的可重构浮点乘加运算方法，其特征在于，当所述待运算浮点数为双精度浮点数时，所述将一个目标段作为一个单元乘法器的一个操作数之前还包括：
    当所述待运算浮点数应的目标段的比特位数不相等时，对比特位数最小的目标段进行补位操作。
  7. 根据权利要求1所述的一种适用于多精度计算的可重构浮点乘加运算方法，其特征在于，所述对所述乘积进行移位相加操作，并将基于所述移位相加操作生成的运算结果作为所述待运算浮点数的乘累加运算的结果包括：
    将所述乘积输入预设的加法树中；
    计算所述乘积的位移量，通过所述加法树根据所述位移量对所述乘积进行移位操作；
    对所述移位操作后得到的数据进行求和操作后得到所述待运算浮点数的乘累加运算的结果。
  8. 根据权利要求7所述的一种适用于多精度计算的可重构浮点乘加运算方法，其特征在于，所述位移量包括内部位移量以及外部位移量中至少一种位移量；
    所述内部位移量的计算方式为：将基于所述待运算浮点数划分出的段数的高低位之和作为所述段数对应的乘积的内部移位量；
    所述外部位移量的计算方式为：将所述待运算浮点数的指数部分相加得到指数和，将得到的所有指数和的最大值作为参考值；将所述参考值与所述指数和作差得到指数差，将所述指数差作为所述待运算浮点数对应的乘积的外部移位量。
  9. 一种适用于多精度计算的可重构浮点乘加运算单元，其特征在于，所述运算单元包括：
    划分模块，用于获取待运算浮点数的有效数字，基于所述有效数字生成若干个目标段；所述若干个包括一个；
    单元乘法器，用于根据所述待运算浮点数的精度确定调用的单元乘法器的个数，将一个目标段作为一个单元乘法器的操作数，获取所述单元乘法器基于所述操作数生成的乘积；
    加法树，用于对所述乘积进行移位相加操作，并将基于所述移位相加操作生成的运算结果作为所述待运算浮点数的乘累加运算的结果。
  10. 根据权利要求9所述的一种适用于多精度计算的可重构浮点乘加运算单元，其特征在于，所述运算单元中包含16n个单元乘法器，n为非负数。
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