Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
  • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/562—Protection against mechanical damage
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
  • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
  • H01L2224/02—Bonding areas; Manufacturing methods related thereto
  • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
  • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
  • H01L2224/081—Disposition
  • H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
  • H01L2224/08135—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
  • H01L2224/08145—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
  • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
  • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
  • H01L2224/80003—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding involving a temporary auxiliary member not forming part of the bonding apparatus
  • H01L2224/80004—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding involving a temporary auxiliary member not forming part of the bonding apparatus being a removable or sacrificial coating
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
  • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
  • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
  • H01L2224/808—Bonding techniques
  • H01L2224/80894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
  • H01L2224/80895—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically conductive surfaces, e.g. copper-copper direct bonding, surface activated bonding
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
  • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
  • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
  • H01L2224/808—Bonding techniques
  • H01L2224/80894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
  • H01L2224/80896—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically insulating surfaces, e.g. oxide or nitride layers
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
  • H01L2224/93—Batch processes
  • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
  • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
  • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
  • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
  • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
  • H01L25/0657—Stacked arrangements of devices
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
  • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/10—Details of semiconductor or other solid state devices to be connected
  • H01L2924/1015—Shape
  • H01L2924/10155—Shape being other than a cuboid
  • H01L2924/10158—Shape being other than a cuboid at the passive surface
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/30—Technical effects
  • H01L2924/35—Mechanical effects
  • H01L2924/351—Thermal stress
  • H01L2924/3511—Warping

Definitions

• the present disclosure relates generally to microelectronic devices including semiconductor devices, transistors, and integrated circuits, including methods of microfabrication.
• transistors have been created in one plane, with wiring/metallization formed above the active device plane, and have thus been characterized as two-dimensional (2D) circuits or 2D fabrication.
• Scaling efforts have greatly increased the number of transistors per unit area in 2D circuits, yet scaling efforts are running into greater challenges as scaling enters single digit nanometer semiconductor device fabrication nodes.
• Semiconductor device fabricators have expressed a desire for three-dimensional (3D) semiconductor circuits in which transistors are stacked on top of each other.
• aspects of the present disclosure provide a method for forming a chiplet onto a
• the method can include providing a first semiconductor structure having a first circuit and a first wiring structure formed on a first side thereof, and attaching the first side of the first semiconductor structure to a carrier substrate.
• the method can further include forming a stress film on a second side of the first semiconductor structure, and separating the carrier substrate from the first semiconductor
• the method can further include cutting the stress film and the first semiconductor structure to define at least one chiplet, and bonding the at least one chiplet to a second semiconductor structure that has a second circuit and a second wiring structure such that the second wiring structure is connected to the first wiring structure.
• the stress film and the first semiconductor structure to define at least one chiplet
• bonding the at least one chiplet to a second semiconductor structure that has a second circuit and a second wiring structure such that the second wiring structure is connected to the first wiring structure.
• the 5 method can further include removing the stress film after the at least one chiplet is bonded to the second semiconductor structure.
• the method can further include patterning the stress film to form a patterned stress film, and cutting the stress film and the first semiconductor structure to define at least one chiplet can include cutting the patterned stress film and the first
• the patterned stress film can be formed via a mask-based lithography tool, ultraviolet (UV) cross-linking or a direct-write lithography tool.
• the patterned stress film can be formed via the direct-write lithography tool using a digital light processing (DLP) chip, a grating light valve or a laser galvanometer.
• the method can further include removing the DLP chip, a grating light valve or a laser galvanometer.
• the first semiconductor structure can further have a first dielectric layer formed on the second side thereof, and forming a stress film on a second side of the first semiconductor structure can include forming a stress film on the first dielectric
• the first semiconductor structure can further have a first substrate formed on the first dielectric layer
• the method can further include, prior to forming a stress film on the first dielectric layer of the first semiconductor structure, removing the first substrate to uncover the first dielectric layer.
• the first side of the first semiconductor structure can be attached
• the carrier substrate 25 to the carrier substrate using an attachment material, and separating the carrier substrate from the first semiconductor structure can include heating the attachment material such that the carrier substrate is separated from the first semiconductor structure.
• aspects of the present disclosure further provide another method for forming a chiplet onto a semiconductor structure.
• the method can include providing a first
• the method can further include forming a stress film on a second side of the first semiconductor structure, and cutting the stress film and the first semiconductor structure to define at least one chiplet.
• the method can further include separating the carrier substrate
• the method can further include patterning the stress film to form
• a patterned stress film, and cutting the stress film and the first semiconductor structure to define at least one chiplet can include cutting the patterned stress film and the first semiconductor structure to define at least one chiplet.
• the patterned stress film can be formed via a mask-based lithography tool, UV cross-linking or a direct-write lithography tool.
• the patterned stress film can be formed via the direct-write
• the first semiconductor structure can further have a first dielectric layer formed on the second side thereof, and forming a stress film on a second side of the first semiconductor structure can include forming a stress film on the first dielectric layer of the first semiconductor structure.
• the first semiconductor structure can be
• the method can further include, prior to forming a stress film on the first dielectric layer of the first semiconductor structure, removing the first substrate to uncover the first dielectric layer.
• the first side of the first semiconductor structure can be attached to the carrier substrate using an attachment material, and cutting the stress film and the first
• 20 semiconductor structure to define at least one chiplet can include cutting the stress film, the first semiconductor structure and the attachment material to define at least one chiplet.
• cutting the stress film, the first semiconductor structure and the attachment material to define at least one chiplet can include cutting the stress film, the first semiconductor structure, the attachment material and a portion of the carrier substrate to define at least one
• the first side of the first semiconductor structure can be attached to the carrier substrate using an attachment material, and separating the carrier substrate from the at least one chiplet can include heating the attachment material such that the carrier substrate is separated from the at least one chiplet.
• the method can further include, prior to separating the carrier substrate from the at least one chiplet, forming a chiplet supporter on the stress film of the at least one chiplet.
• the method can further include removing the chiplet supporter and the stress film after the at least one chiplet is bonded to the second semiconductor structure.
• aspects of the present disclosure provide a method for forming a chiplet onto a semiconductor structure.
• the method can include providing a first semiconductor structure having a first circuit and a first wiring structure formed on a first
• the method can further include forming a composite of a first stress film and a second stress film on a second side of the first semiconductor structure, and separating the carrier substrate from the first semiconductor structure.
• the method can further include cutting the composite of the first stress film and the second stress film and the first
• the method can further include removing the composite of the first stress film and the second stress film after the at least one chiplet is bonded to the second semiconductor structure.
• the first semiconductor structure can further have a first dielectric layer formed on the second side thereof, and forming a composite of a first stress film and a second stress film on a second side of the first semiconductor structure can include forming a composite of a first stress film and a second stress film on the first dielectric layer of the first semiconductor structure.
• the first semiconductor structure can
• the method can further include, prior to forming a composite of a first stress film and the second stress film on the first dielectric layer of the first semiconductor structure, removing the first substrate to uncover the first dielectric layer.
• the first side of the first semiconductor structure can be attached
• the method can further include patterning the first stress film to form a first patterned stress film, and cutting the composite of the first stress film and the
• first patterned stress film can be formed with at least one stress region
• second stress film can be formed with at least one stress region
• the second stress film can be further formed on the first patterned stress film.
• the first patterned stress film can be formed via a mask-based lithography tool, ultraviolet (UV) crosslinking, or a direct-write lithography tool.
• the first patterned stress film can be formed via the direct-write lithography tool using a digital light processing (DLP) chip, a
• the method can further include removing the composite of the first patterned stress film and the second stress film after the at least one chiplet is bonded to the second semiconductor structure.
• aspects of the present disclosure further provide another method for forming a chiplet onto a semiconductor structure.
• the method can include providing a first
• the method can further include forming a composite of a first stress film and a second stress film on a second side of the first semiconductor structure, and cutting the composite of the first stress film and the second stress film and the first semiconductor
• the method can further include separating the carrier substrate from the at least one chiplet, and bonding the at least one chiplet to a second semiconductor structure that has a second circuit and a second wiring structure such that the second wiring structure is connected to the first wiring structure.
• the method can further include patterning the first stress film to
• cutting the composite of the first stress film and the second stress film and the first semiconductor structure to define at least one chiplet can include cutting the composite of the first patterned stress film and the second stress film and the first semiconductor structure to define at least one chiplet.
• the first patterned stress film can be formed with at least one stress region, and the second stress film
• the second stress film can be further formed on the first patterned stress film.
• the first patterned stress film can be formed via a mask-based lithography tool, UV cross-linking or a direct-write lithography tool.
• the first semiconductor structure can further have a first dielectric layer formed on the second side thereof, and forming a composite of a first stress film and a second stress film on a second side of the first semiconductor structure can include forming a composite of a first stress film and a second stress film on the first dielectric layer
• the first semiconductor structure can further have a first substrate formed on the first dielectric layer
• the method can further include, prior to forming a composite of a first stress film and the second stress film on the first dielectric layer of the first semiconductor structure, removing the first substrate to uncover the first dielectric layer.
• the first side of the first semiconductor structure can be attached to the carrier substrate using an attachment material
• cutting the stress film and the first semiconductor structure to define at least one chiplet can include cutting the stress film, the first semiconductor structure and the attachment material to define at least one chiplet. For example, cutting the stress film, the first semiconductor structure and the attachment material
• 15 to define at least one chiplet can include cutting the stress film, the first semiconductor structure, the attachment material and a portion of the carrier substrate to define at least one chiplet.
• FIGs. 1-10 are cross-sectional views illustrating a first exemplary method for
• FIGs. 11-16 are cross-sectional views illustrating a second exemplary method for forming a chiplet onto a semiconductor structure according to some embodiments of the present disclosure.
• FIGs. 17-20 are cross-sectional views illustrating a third exemplary method for forming a chiplet onto a semiconductor structure according to some embodiments of the present disclosure.
• FIG. 21 is a flow chart illustrating a fourth exemplary method for forming a chiplet
• FIG. 22 is a flow chart illustrating a fifth exemplary method for forming a chiplet onto a semiconductor structure according to some embodiments of the present disclosure.
• FIGs. 23-31 are cross-sectional views illustrating a first exemplary method for forming a chiplet onto a semiconductor structure according to some embodiments of the
• FIGs. 32-36 are cross-sectional views illustrating a second exemplary method for forming a chiplet onto a semiconductor structure according to some embodiments of the present disclosure.
• FIGs. 37-39 are cross-sectional views illustrating a third exemplary method for
• FIGs. 40-44 are cross-sectional views illustrating a fourth exemplary method for forming a chiplet onto a semiconductor structure according to some embodiments of the present disclosure
• FIG. 45 is a flow chart illustrating a fifth exemplary method for forming a chiplet onto a semiconductor structure according to some embodiments of the present disclosure.
• FIG. 46 is a flow chart illustrating a sixth exemplary method for forming a chiplet onto a semiconductor structure according to some embodiments of the present disclosure.
• 3D integration i.e., the vertical stacking of multiple devices, aims to overcome scaling limitations experienced in planar devices by increasing transistor density in volume rather than area.
• device stacking has been successfully demonstrated and implemented by the flash memory industry with the adoption of 3D NAND, application to
• Techniques herein include systems and methods to mitigate wafer stress complications from stacked wafers and chiplets.
• Techniques herein can include selective stress (or stressor) film technology and creating relatively thin chiplets to attach or bond to a semiconductor structure, e.g., a wafer or a die.
• One or more stress films can be deposited on a surface (e.g., a back, second or inactive side, or opposite to a front, first, active or working side) of the chiplets.
• a direct-write lithographic exposure tool can be used to write a corrected stress pattern on the
• Chiplets can receive identical or different stress films and identical or different stress-correction patterns for localized stress regions. This enables higher density of 3D chiplets to be stacked because the thickness of the chiplet may be greatly reduced. These techniques also enable higher die yield per wafer because the wafer has less bow or curvature which enables higher precision
• the present invention can be embodied and viewed in many different ways.
• FIGs. 1-10 are cross-sectional views illustrating a first exemplary method for forming a chiplet onto a semiconductor structure according to some embodiments of the present disclosure. As shown in FIG. 1, a first semiconductor structure 100 can be provided.
• the first semiconductor structure 100 can have a first circuit (or a first active circuit) 110 and a first wiring structure 120 formed on a first side 100A (or a front side, an active side or a working side) of the first semiconductor structure 100.
• the first circuit 110 can be formed in bulk silicon 105 of the first semiconductor structure 100.
• the first wiring structure 120 can include vias and copper layers. In an
• the first circuit 110 and the first wiring structure 120 can be used as chiplets.
• a chiplet herein can be a component device or integrated circuit or a portion thereof that is a component of a larger module, assembly, package, or an integrated circuit.
• a chiplet can be cut from a larger device or wafer, e.g., the first semiconductor structure 100.
• a dashed line shown in FIG. 1 can identify an example chiplet.
• the first semiconductor structure 100 can further have a first dielectric layer 130 and a first substrate 140 formed on a second side (or a back side or an inactive side) 100B of the first semiconductor structure 100.
• the first substrate 140 can be a silicon substrate.
• the 5 silicon-on-insulator (SOI) substrate which is composed of the first substrate 140, the first dielectric layer 130 and the bulk silicon 105, can be provided, the first circuit 110 can be formed in the bulk silicon 105 via photolithography, and the first wiring structure 120 can be formed to connect the first circuit 110.
• SOI silicon-on-insulator
• FIG. 1 further shows a carrier substrate 150 for the first semiconductor structure 100
• the carrier substrate 150 can be a silicon wafer.
• the first side 100 A of the first semiconductor structure 100 can be attached to the carrier wafer 150 using an attachment material 210.
• the attachment material 210 can be specified as a glue layer, a bonding layer, a method to bonding wafers that can be removed later, semiconductor to semiconductor with native oxide
• metal to metal metal with oxide coating, metal with SiC coating, metal with SiCN coating, metal with an attachment film comprising semiconductor with a coating consisting of one or more elements, or a combination thereof.
• the first substrate 140 can be removed to uncover the first dielectric layer 130.
• the first semiconductor structure 100 can be planarized via
• CMP chemical-mechanical planarization
• a stress film 410 can be formed on the first dielectric layer 130. Any type of stress (i.e., compressive or tensile) may be induced in bulk silicon 105 by
• the stress film 410 can include silicon nitride, silicon oxide, etc, e.g., SISNA, SiOxNy, Si and SiOi.
• the stress film 410 can also be an ultraviolet (UV) cross-linking stress film that includes a spin-on material, e.g., UV
• the spin-on material can be exposed with a direct write exposure and then baked to complete processing to establish a desired stress pattern and be used for any one of the exemplary methods.
• the stress film 410 can be patterned to form a patterned stress film 510.
• the stress film 410 can be patterned, exposed and developed to remove the reacted (e.g., positive) photoresist layer and form the patterned stress film 510.
• a photomask can be used for forming the patterned stress film
• the stress film 410 e.g., the photoresist layer
• the stress film 410 can be patterned with a direct-write (or maskless) lithography tool, which projects simultaneously or uses a scanning motion to project a stress-modification pattern on the photoresist layer or a layer with photo-reactive agents.
• the patterned photoresist layer can be then developed to create a relief pattern. This relief pattern can serve as a stress film, or be transferred into an
• a digital light processing (DLP) chip can be used.
• a grating light valve or laser galvanometer can be used.
• Direct-write systems are able to use a processing engine to control amount/intensity of light at any given point on a substrate or film to be exposed. Any of various convention light wavelengths can be used based on a photo-reactive agent of a
• corresponding film or the film composition can be selected based on light wavelengths available.
• a lower resolution exposure is sufficient to create desired stress modifications (or the patterned stress film 510).
• Stress-modification patterns (or the patterned stress film 510) herein can make regions of stress induced by stress film (or patterned stress film) vs regions of reduced stress or no stress where the first-write tool has
• the attachment material 210 can be removed to separate the first semiconductor structure 100 from the carrier substrate 150.
• the attachment material 210 can be a glue layer or a bonding layer, and the glue layer or the bonding layer
• the 25 can be heated and vaporized such that the first semiconductor structure 100 can be separated from the carrier substrate 150.
• the first semiconductor structure 100 along with the patterned stress film 510 (or the stress film 410) can be cut via etching, for example, to define a plurality of chiplets 750.
• the patterned stress film 510 (or the stress film 410) is formed
• the first semiconductor structure 100 can allow the first semiconductor structure 100 (and the chiplets 750) to receive identical or different stress films and identical or different stress-correction patterns for localized stress regions and have less complicated wafer stress, the first semiconductor 100 (and the chiplets 750) can have reduced thickness, and higher density of 3D chiplets can be stacked.
• the chiplet 750 can be bonded to a second semiconductor structure 700 that has a second circuit 710 and a second wiring structure 720 that corresponds to the first wiring structure 120 of the first semiconductor structure 100.
• the chiplet 750 can be bonded to the second semiconductor structure 700, with the first wiring structure 120 of the chiplet 750 being connected to the second wiring structure 720 of the second semiconductor structure 700.
• the patterned stress film 510 (or the stress film 410) can be removed to uncover the first dielectric layer 130.
• the patterned stress film 510 (or the stress film 410) can be removed to uncover the first dielectric layer 130.
• the patterned stress film 510 (or the stress film 410) can be removed to uncover the first dielectric layer 130.
• the first dielectric layer 130 can be removed.
• the first dielectric layer 130 can be removed via CMP.
• the patterned stress film 510 (or the stress film 410) and the first dielectric layer 130 can be removed in a
• the chiplet 750 which is bonded to the second semiconductor structure 700, can be very thin.
• FIGs. 11-16 are cross-sectional views illustrating a second exemplary method for forming a chiplet onto a semiconductor structure according to some embodiments of the present disclosure.
• the second exemplary method differs from the first exemplary method in
• both the first substrate 140 and the first dielectric layer 130 are removed, which can enable optimum stress transfer.
• FIG. 11 which follows FIG. 2, the first substrate 140 and the first dielectric layer 130 are removed.
• the first substrate 140 and the first dielectric layer 130 can be removed in a single CMP process, or be removed in two respective CMP
• the stress film 410 can be formed on the second side 100B of the first semiconductor structure 100 and be in direct contact with the bulk silicon 105 of the first semiconductor structure 100.
• a photoresist layer can be deposited on the
• the stress film 410 can be patterned to form the patterned stress film 510.
• the stress film 410 can be patterned, exposed and developed to remove the reacted (e.g., positive) resist layer and form the patterned stress film 510.
• a photomask can be used for forming the patterned stress film 510.
• the stress film 410 e.g., the photoresist layer
• the stress film 410 can be patterned with the direct-write technique.
• a DLP chip can be used.
• a grating light valve or laser galvanometer can be used. Any of various convention light wavelengths can be used based on a photo-reactive agent of a corresponding film (or the film composition
• Stress-modification patterns (or the patterned stress film 510) herein can make regions of stress induced by stress film (or patterned stress film) vs regions of reduced stress or no stress where the first-write tool has removed at least a portion of the stress film that will
• the substrate 10 make the substrate more planar for optimum photolithography precision.
• the pattern is shown as only partially extending through the stress film 410/the patterned stress film 510, it should be appreciated that the pattern may extend completely through in order to further modify the stress characteristics.
• the attachment material 210 can be removed to separate the
• first semiconductor structure 100 from the carrier substrate 150.
• the attachment material 210 can be heated and vaporized such that the first semiconductor structure 100 can be separated from the carrier substrate 150.
• the first semiconductor structure 100 along with the patterned stress film 510 (or the stress film 410) can be cut via etching, for example, to define a
• the chiplet 1550 can be bonded to another semiconductor structure.
• the chiplet 1550 can be bonded to the second semiconductor structure 700, which has the second circuit 710 and the second wiring structure 720, the second wiring structure 720 corresponding to the first wiring structure 120 of the first semiconductor structure 100.
• the chiplet 1550 can be bonded to the second semiconductor structure 700, with the first wiring structure 120 of the chiplet 1550 being connected to the second wiring structure 720 of the second semiconductor structure 700. Then, the patterned stress film 510 (or the stress film 410) can be removed, to provide the structure as shown in FIG. 10. For example, the patterned stress film 510 (or the stress film 410) can be removed
• FIGs. 17-20 are cross-sectional views illustrating a third exemplary method for forming a chiplet onto a semiconductor structure according to some embodiments of the present disclosure.
• the third exemplary method differs from the first and second exemplary methods in that in the third exemplary method the first semiconductor structure 100 along
• the third exemplary method can enable control of cutting the chiplets with a
• the patterned stress film 510 (or the stress film 410) and the first semiconductor structure 100, which includes the first dielectric layer 130, the first circuit 110 and the first wiring structure 120, and the attachment material 210 can be cut sequentially via etching, for example, to define the chiplets 750.
• the cutting process can stop at the carrier substrate 150, as
• the carrier substrate 150 can be etched partially in the cutting process.
• the cutting process can stop at the attachment layer 210.
• FIG. 17 can also follow FIG. 13, and the patterned stress film 510 (or the stress film 410) and the first semiconductor structure 100, which includes the first circuit 110 and the first wiring structure 120 (and, optionally, the attachment material 210 and/or a
• the carrier substrate 150 can be etched sequentially, to define the chiplets 1550.
• chiplet supporters 1810 can be optionally formed on the patterned stress film 510 (or the stress film 410) for each of the chiplets 750 (or chiplets 1550), and the attachment material 210 can be removed via heating, for example, to separate
• the chiplet supporters 1810 can be used for holding the chiplets 750 (or chiplets 1550) in place during subsequent process steps, e.g., the cutting process step.
• the chiplet supporters 1810 can be an adhesive.
• the chiplet supporters 1810 can be formed on the surface of the patterned stress film 510 in a random location for each of the
• the chiplet supporters 1810 can be formed in any shape, e.g., a block, as shown in FIG. 18.
• one or more than one of the chiplets 750 can be bonded to another semiconductor structure.
• the chiplet 750 can be bonded to the second semiconductor structure 700, which has the second circuit
• the chiplet 750 (or chiplet 1550) can be bonded to the second semiconductor structure 700, with the first wiring structure 120 of the chiplet 750 (or chiplet 1550) being connected to the second wiring structure 720 of the second semiconductor
• the chiplet supporter 1810, the patterned stress film 510 (or the stress film 410) and the first dielectric layer 130 can be removed, to provide the structure as shown in FIG. 10.
• the chiplet supporter 1810, the patterned stress film 510 and the first dielectric layer 130 can be removed via CMP in a single process or multiple processes.
• FIG. 21 is a flow chart illustrating a fourth exemplaiy method 2100 for forming a chiplet onto a semiconductor structure according to some embodiments of the present disclosure.
• some of the steps of the fourth exemplary method 2100 shown can be performed concurrently or in a different order than shown, can be substituted by other method steps, or can be omitted. Additional method steps can also be performed as desired.
• the fourth exemplary method 2100 can correspond to the first and second exemplary methods shown in FIGs. 1-16.
• a first semiconductor structure can be provided.
• the first semiconductor structure e.g., the first semiconductor structure 100
• the first semiconductor structure 100 can include a first circuit (e.g., the first circuit 110) and a first wiring structure (e.g., the first wiring
• first semiconductor structure 120 that are formed on a first side of the first semiconductor structure (e.g., the first side 100A) and a first dielectric layer (e.g., the first dielectric layer 130) and a first substrate (e.g., the first substrate 140) that are formed on a second side of the first semiconductor structure (e.g., the second side 100B).
• first side of the first semiconductor structure e.g., the first side 100A
• first dielectric layer e.g., the first dielectric layer 130
• first substrate e.g., the first substrate 140
• the first side of the first semiconductor structure can be attached to a
• the first side 100A of the first semiconductor 100 can be attached to the carrier substrate 150 using the attachment material 210.
• the first substrate (and the first dielectric layer) can be removed.
• the first substrate 140 and the first dielectric layer 130
• CMP CMP
• a stress film can be formed on the second side (or the first dielectric
• the stress film 410 can be formed on the first dielectric layer 130, as shown in FIG. 4.
• the stress film 410 can be formed on the second side 100B of the first semiconductor structure 100, as shown in FIG. 12.
• the stress film can be patterned to form a patterned stress
• the stress film 410 can be patterned with the direct-write to form the patterned stress film 510.
• the first semiconductor structure can be separated from the carrier substrate.
• the attachment layer 210 can be heated and vaporized such that the first semiconductor structure 100 can be separated from the carrier substrate 150.
• the first semiconductor structure along with the patterned stress film can be cut to define a plurality of chiplets.
• the first semiconductor structure 100 along with the patterned stress film 510 (or the stress film 410) can be cut via etching, for example, to define the chiplets 750/1550.
• one or more than one of the chiplets can be bonded to another semiconductor structure.
• the chiplet 750/1550 can be bonded to the second semiconductor structure 700, which has the second circuit 710 and the second wiring structure 720, with the first wiring structure 120 of the chiplet 750/1550 being connected to the second wiring structure 720 of the second semiconductor structure 700.
• the patterned stress film (or the stress film) (and the first dielectric layer) can be removed.
• the patterned stress film 510 (or the stress film 410) (and the first dielectric layer 130) can be removed via CMP.
• FIG. 22 is a flow chart illustrating a fifth exemplary method 2200 for forming a chiplet onto a semiconductor structure according to some embodiments of the present
• the steps of the fifth exemplary method 2200 shown can be performed concurrently or in a different order than shown, can be substituted by other method steps, or can be omitted. Additional method steps can also be performed as desired.
• the fifth exemplary method 2200 can correspond to the third exemplary method shown in FIGs. 17-20.
• the fifth exemplary method 2200 can also include
• the first semiconductor structure along with the patterned stress film can be cut to define a plurality of chiplets.
• the first semiconductor structure 100 along with the patterned stress film 510 (or the stress film 410) can be cut via etching, for example, to form the chiplets 750/1550, with the carrier substrate
• chiplet supporters can be formed on the patterned stress film (or the stress film) for each of the chiplets.
• the chiplet supporters 1810 can be formed on the patterned stress film 510 (or the stress film 410) for each of the chiplets 750
• the chiplets can be separated from the carrier substrate.
• the attachment layer 210 can be heated and vaporized such that the chiplets 750/1550 can be separated from the carrier substrate 150.
• one or more than one of the chiplets can be bonded to another semiconductor structure.
• the chiplet 750/1550 can be bonded to the second semiconductor structure 700, which has the second circuit 710 and the second wiring structure 720, with the first wiring structure 120 of the chiplet 750/1550 being connected to
• the chiplet supporters and the patterned stress film (or the stress film) (and the first dielectric layer) can be removed.
• the chiplet supporters 1810 and the patterned stress film 510 (or the stress film) (and the first dielectric layer 130) can be removed via CMP.
• substrate or “target substrate” as used herein generically refers to an object being processed in accordance with the invention.
• the substrate may include any material portion or structure of a device, particularly a semiconductor or other electronics device, and may, for example, be a base substrate structure, such as a semiconductor wafer, reticle, or a layer on or
• substrate is not limited to any particular base structure, underlying layer or overlying layer, patterned or un-pattemed, but rather, is contemplated to include any such layer or base structure, and any combination of layers and/or base structures.
• the description may reference particular types of substrates, but this is for illustrative memeposes only.
• 3D integration i.e., the vertical stacking of multiple devices, aims to overcome scaling limitations experienced in planar devices by increasing transistor density in volume rather than area.
• Techniques herein can include selective stress (or stressor) film technology and creating relatively thin chiplets to attach or bond to a semiconductor structure, e.g., a wafer or a die.
• One or more stress films can be deposited on a surface (e.g., a back, second or inactive side, or opposite to a front, second, active or working side) of the chiplets.
• a direct-write lithographic exposure tool can be used to write a corrected stress
• Chiplets can receive identical or different stress films and identical or different stresscorrection patterns for localized stress regions. This enables higher density of 3D chiplets to be stacked because the thickness of the chiplet may be greatly reduced. These techniques also enable higher die yield per wafer because the wafer has less bow or curvature which
• FIGs. 23-31 are cross-sectional views illustrating a first exemplary method for forming a chiplet onto a semiconductor structure according to some embodiments of the
• a first semiconductor structure 100 can be provided.
• the first semiconductor structure 100 can have a first circuit (or a first active circuit) 110 and a first wiring structure 120 formed on a first side 100 A (or a front side, an active side or a working side) of the first semiconductor structure 100.
• the first circuit 110 can be formed in bulk silicon 105 of the first semiconductor
• the first wiring structure 120 can include vias and copper layers.
• the first circuit 110 and the first wiring structure 120 can be used as chiplets.
• a chiplet herein can be a component device or integrated circuit or a portion thereof that is a component of a larger module, assembly, package, or an integrated circuit.
• a chiplet can be cut from a larger device or wafer, e.g., the first semiconductor structure 100.
• 15 dashed line shown in FIG. 23 can identify an example chiplet.
• the first semiconductor structure 100 can further have a first dielectric layer 130 and a first substrate 140 formed on a second side (or a back side or an inactive side) 100B of the first semiconductor structure 100.
• the first substrate 140 can be a silicon substrate.
• SOI substrate which is composed of the first substrate 140, the first dielectric layer 130 and the bulk silicon 105, can be provided, the first circuit 110 can be formed in the bulk silicon 105 via photolithography, and the first wiring structure 120 can be formed to connect the first circuit 110.
• FIG. 23 further shows a carrier substrate 150 for the first semiconductor structure
• the carrier substrate 150 can be a silicon wafer.
• the first side 100 A of the first semiconductor structure 100 can be attached to the carrier wafer 150 using an attachment material 210.
• the attachment material 210 can be specified as a glue layer, a bonding layer, a method to bonding wafers that can be removed later, semiconductor to semiconductor with native oxide
• metal to metal metal with oxide coating
• metal with SiC coating metal with SiCN coating
• metal with an attachment film comprising semiconductor with a coating consisting of one or more elements, or a combination thereof.
• the first substrate 140 can be removed to uncover the first dielectric layer 130.
• the first semiconductor structure 100 can be planarized via
• CMP chemical-mechanical planarization
• a first stress film 410 can be formed on the first dielectric
• any type of stress may be induced in the bulk silicon 105 by attaching or forming the first stress film 410 on the first dielectric layer 130.
• a photoresist layer can be applied to or deposited on the first dielectric layer 130 via spin coating to act as the first stress film 410.
• the first stress film 410 can include silicon nitride, silicon oxide, etc, e.g., SisN4, SiOxNy, Si and SiCh.
• 10 film 410 can also be an ultraviolet (UV) cross-linking stress film that includes a spin-on material, e.g., benzocyclobutene (BCB) and other materials with cross-linking properties.
• a spin-on material e.g., benzocyclobutene (BCB) and other materials with cross-linking properties.
• the spin-on material can be exposed with a direct write exposure and then baked to complete processing to establish a desired stress pattern and be used for any one of the exemplary methods.
• the first stress film 410 can be patterned to form a first patterned stress film 510 with stress regions 510A.
• the stress regions 510A can be openings in the first patterned stress film 510.
• the first stress film 410 can be patterned, exposed and developed to remove the reacted (e.g., positive) photoresist layer and form the first patterned stress film 510.
• a photomask can be used to remove the reacted (e.g., positive) photoresist layer and form the first patterned stress film 510.
• the first stress film 410 e.g., the photoresist layer
• the first stress film 410 can be patterned with a direct-write (or maskless) lithography tool, which projects simultaneously or uses a scanning motion to project a stressmodification pattern on the photoresist layer or a layer with photo-reactive agents.
• the patterned photoresist layer can be then developed to create a relief pattern. This relief pattern
• DLP digital light processing
• grating light valve or laser galvanometer can be used.
• Direct-write systems are able to use a processing engine to control amount/intensity of light at any given point on a substrate or film to be exposed Any of various convention light wavelengths can
• Stress-modification patterns (or the first patterned stress film 510) herein can make regions of stress induced by stress film (or patterned stress film) vs regions of reduced stress
• the pattern is shown as only partially extending through the first stress film 410/the first patterned stress film 510, it should be appreciated that the pattern may extend completely through in order to
• FIG. 27 further shows that a second stress film 520 can be deposited and formed within the stress regions 510A of the first patterned stress film 510.
• the stress regions 510A can be openings in the first patterned stress film 510, and the second stress film 520 can fill the openings and be adjacent to the first patterned stress film 510. Therefore, a second stress film 520 can be deposited and formed within the stress regions 510A of the first patterned stress film 510.
• the stress regions 510A can be openings in the first patterned stress film 510
• the second stress film 520 can fill the openings and be adjacent to the first patterned stress film 510. Therefore, a
• the 10 composite of the first patterned stress film 510 and the second stress film 520 can be formed on the first dielectric layer 130.
• CMP can be performed to planarize the second stress film 520.
• the second stress film 520 can be formed only within the stress regions 510A of the first patterned stress film 510, as shown in
• the second stress film 520 can be further formed on the first patterned stress film 510.
• the first stress film 410 is not patterned, and the second stress film 520 can be deposited and formed on the first stress film 410, to form a composite of the first stress film 410 and the second stress film 520.
• the second stress film 520 can be used to add or reduce stress in specific regions of the first
• the second stress film 520 can be either different from or the same as the first stress film 410 (and the first patterned stress film 510) to keep the first semiconductor structure 100 and the chiplets at balanced stress over the entire area.
• the attachment material 210 can be removed to separate the
• FIG. 28 further shows a second semiconductor structure 600 that can be bonded to the first semiconductor structure 100.
• the second semiconductor structure 600 can have a second circuit 610 and a second wiring
• the first semiconductor structure 100 along with the composite of the first patterned stress film 510 and the second stress film 520 (or the composite of the first stress film 410 and the second stress film 520) can be cut via etching
• the composite of the first patterned stress film 510 and the second stress film 520 (or the composite of the first stress film 410 and the second stress film 520) is formed on the first semiconductor structure 100, which can allow the first semiconductor structure 100 (and the chiplets 750) to receive identical or
• the first semiconductor 100 (and the chiplets 750) can have reduced thickness, and higher density of 3D chiplets can be stacked.
• One or more than one of the chiplets 750 can be bonded to another semiconductor structure.
• the chiplet 750 can be bonded to the second semiconductor structure 600, which has
• the chiplet 750 can be bonded to the second semiconductor structure 600, with the first wiring structure 120 of the chiplet 750 being connected to the second wiring structure 620 of the second semiconductor structure 600.
• the composite of the first patterned stress film 510 and the second stress film 520 (or the composite of the first stress film 410 and the second stress film 520) can be removed to uncover the first dielectric layer 130.
• the composite of the first patterned stress film 510 and the second stress film 520 (or the composite of the first stress film 410 and the second stress film 520) can be removed via CMP, which stops at the
• FIG. 31 further shows that the first dielectric layer 130 can be removed.
• the first dielectric layer 130 can be removed via CMP.
• the composite of the first patterned stress film 510 and the second stress film 520 (or the composite of the first stress film 410 and the second stress film 520) and the first dielectric layer 130 can be removed in a single CMP process.
• the chiplet 750 which is bonded to the second semiconductor structure 600, can be very thin.
• FIGs. 32-36 are cross-sectional views illustrating a second exemplary method for forming a chiplet onto a semiconductor structure according to some embodiments of the present disclosure.
• the second exemplary method differs from the first exemplary method in
• both the first substrate 140 and the first dielectric layer 130 are removed, which can enable optimum stress transfer.
• FIG. 32 which follows FIG. 24, the first substrate 140 and the first dielectric layer 130 are removed.
• the first substrate 140 and the first dielectric layer 130 can be removed in a single CMP process, or be removed in two respective CMP
• the first stress film 410 can be formed on the second side 100B of the first semiconductor structure 100 and be in direct contact with the bulk silicon
• a photoresist layer can be deposited on the second side 100B to act as the first stress film 410.
• the first stress film 410 can be patterned to form the first patterned stress film 510 with the stress regions 510A.
• a photomask can be used for forming the first patterned stress film 510.
• the photoresist layer can be patterned with a direct-write lithography tool.
• the patterned photoresist layer can be then developed to create a relief pattern.
• This relief pattern can serve as a stress film, or be transferred into an underlying layer to become the first patterned stress film 510.
• a DLP chip can be used.
• a grating light valve or laser galvanometer can be used.
• FIG. 35 further shows that the second
• 15 stress film 520 can be deposited and formed within the stress regions 510A of the first patterned stress film 510 and on the first patterned stress film 510. Therefore, a composite of the first patterned stress film 510 and the second stress film 520 can be formed on the first dielectric layer 130. After the second stress film 520 is deposited and formed within the stress regions 510A of the first patterned stress film 510 and on the first patterned stress film
• CMP can be performed to planarize the second stress film 520.
• the second stress film 520 can be formed within the stress regions 510A of the first patterned stress film 510 and on the first patterned stress film 510, as shown in FIG. 35.
• the second stress film 520 can be formed only within the stress regions 510A of the first patterned stress film 510.
• the first stress film 410 is not
• the second stress film 520 can be deposited and formed on the first stress film 410, to form a composite of the first stress film 410 and the second stress film 520.
• the attachment material 210 can be removed to separate the first semiconductor structure 100 from the carrier substrate 150.
• the attachment material 210 can be heated and vaporized such that the first semiconductor structure 100 can
• FIG. 35 further shows that the first semiconductor structure 100 along with the composite of the first patterned stress film 510 and the second stress film 520 (or the composite of the first stress film 410 and the second stress film 520) can be cut via etching, for example, to define a plurality of chiplets 1350.
• One or more than one of the chiplets 1350 can be bonded to another semiconductor structure.
• the chiplet 1350 can be bonded to the second semiconductor structure 600, which has the second circuit 610 and the second wiring structure 620 that corresponds to the first wiring structure 120 of the first semiconductor structure 100.
• FIG. 35 further shows that the chiplet 1350 can be bonded to the second semiconductor structure 600, with the first
• the composite of the first patterned stress film 510 and the second stress film 520 (or the composite of the first stress film 410 and the second stress film 520) can be removed.
• the composite of the first patterned stress film 510 and the second stress film 520 can be removed.
• the composite of the first patterned stress film 510 and the second stress film 520 can be removed.
• the second stress film 520 (or the composite of the first stress film 410 and the second stress film 520) can be removed via CMP, which stops at the bulk silicon 105 of the first semiconductor structure 100 where the first circuit 110 is formed. Therefore, the chiplet 1350, which is bonded to the second semiconductor structure 600, can be very thin.
• FIGs. 37-39 are cross-sectional views illustrating a third exemplary method for
• the third exemplary method differs from the first and second exemplary methods in that in the third exemplary method the first semiconductor structure 100 along with the composite of the first patterned stress film 510 and the second stress film 520 (or the composite of the first stress film 410 and the second stress film 520) are cut to define the first semiconductor structure 100 along with the composite of the first patterned stress film 510 and the second stress film 520 (or the composite of the first stress film 410 and the second stress film 520) are cut to define the
• the third exemplary method can enable control of cutting the chiplets with a thicker underlying substrate.
• FIG. 37 which follows FIG. 34, the composite of the first patterned stress film 510 and the second stress film 520 (or the composite of the
• first stress film 410 and the second stress film 520 and the first semiconductor structure 100 which includes the first dielectric layer 130 and the first circuit 110 (and the attachment material 210) can be cut sequentially via etching, for example, to define the chiplets 1350.
• the cutting process can stop at the carrier substrate 150, as shown in FIG. 37.
• the carrier substrate 150 can be etched partially in the cutting
• FIG. 37 can also follow FIG. 27, and the composite of the first patterned stress film 510 and the second stress film 520 (or the composite of the first stress film 410 and the second stress film 520) and the first semiconductor structure 100, which includes the first circuit 110, the first wiring structure 120 and the first dielectric layer 130 (and the attachment
• chiplet supporters 1610 can be optionally formed on the composite of the first patterned stress film 510 and the second stress film 520 (or the
• the attachment material 210 can be removed via heating, for example, to separate the carrier substrate 150 from the chiplets 1350 (or chiplets 750).
• the chiplet supporters 1610 can be formed on the first patterned stress film 510 (or the first stress film 410) and/or the second stress film 520 for each of the chiplets 1350 (or
• FIG. 38 further shows that one or more than one of the chiplets 1350 (or chiplets 750) can be bonded to another semiconductor structure.
• the chiplet 1350 (or chiplet 750) can be bonded to the second semiconductor structure 600, which has the second circuit 610 and the second wiring structure 620, the second wiring structure 620 corresponding to the first wiring structure 120 of the first semiconductor structure 100.
• the chiplet supporters 1610 can be used for holding the chiplets 750 (or chiplets 1350) in place during subsequent process steps, e.g., the cutting process step.
• the chiplet supporters 1610 can be an adhesive.
• the chiplet supporters 1610 can be formed on the surface of the composite of the first patterned stress film 510 and the second stress film 520 (or the composite of the first stress film 410 and the second stress
• the chiplet supporters 1610 can be formed in any shape, e.g., a block, as shown in FIG. 38.
• the chiplet 1350 (or chiplet 750) can be bonded to the second semiconductor structure 600, with the first wiring structure 120 of the chiplet 1350 (or chiplet 750) being connected to the second wiring structure 620 of the second semiconductor
• the chiplet supporter 1810 and the composite of the first patterned stress film 510 and the second stress film 520 (or the composite of the first stress film 410 and the second stress film 520) (and the first dielectric layer 130 for the chiplet 750) can be removed.
• the chiplet supporter 1810, the composite of the first patterned stress film 510 and the second stress film 520 (or the composite of the first stress film 410 and the second stress film 520) can be removed.
• the stress film 520 and the first dielectric layer 130 can be removed via CMP in a single process or multiple processes.
• FIGs. 40-44 are cross-sectional views illustrating a fourth exemplary method for forming a chiplet onto a semiconductor structure according to some embodiments of the present disclosure.
• the fourth exemplary method differs from the first and second exemplary
• a dual stress film stack of two or more layers can be deposited on the second side 100B of the first semiconductor structure 100, omitting the CMP process performed on the second stress film 520.
• a dual stress film stack of two or more layers e.g., a
• composite of a first stress film 1810 and a second stress film 1820 can be deposited and formed on the second side 100B of the first semiconductor structure 100.
• the composite of the first stress film 1810 and the second stress film 1820 can be deposited and formed on the first dielectric layer 130.
• a photoresist layer can be applied to or deposited on the first dielectric layer 130 via
• first stress film 1810 or the second stress film 1820
• first stress film 1810 can include silicon nitride, silicon oxide, etc.
• the first stress film 1810 (or the second stress film 1820) can also be an UV cross linking stress film that includes a spin-on material.
• the dual stress film stack can be patterned.
• the first stress film 1810 can be patterned to form a first patterned stress film 1910 with stress regions 1910A.
• a photomask can be used for forming the first patterned stress film 1910.
• the first stress film 1810 e.g., the photoresist layer
• the first stress film 1810 can be patterned with a direct-write lithography tool.
• the patterned photoresist layer can be then developed to create a relief pattern. This relief pattern can serve
• a stress film 20 as a stress film, or be transferred into an underlying layer to become the first patterned stress film 1910.
• a DLP chip can be used.
• a grating light valve or laser galvanometer can be used. Therefore, a composite of the first patterned stress film 1910 and the second stress film 1820 can be formed on the second side 100B of the first semiconductor structure 100.
• the attachment material 210 can be removed to separate the first semiconductor structure 100 from the carrier substrate 150.
• the attachment material 210 can be heated and vaporized such that the first semiconductor structure 100 can be separated from the carrier substrate 150.
• FIG. 42 further shows that the first semiconductor structure 100 along with the composite of the first patterned stress film 1910
• the second stress film 1820 (or the composite of the first stress film 1810 and the second stress film 1820) can be cut via etching, for example, to define a plurality of chiplets 2050.
• One or more than one of the chiplets 2050 can be bonded to another semiconductor structure.
• the chiplet 2050 can be bonded to the second semiconductor structure 600,
• the first semiconductor structure 100 along with the composite of the first patterned stress film 1910 and the second stress film 1820 (or the composite of the first
• 5 stress film 1810 and the second stress film 1820 can be cut to define the chiplets 2050, and then the attachment material 210 can be removed to separate the carrier substrate 150 from the chiplets 2050.
• the chiplet 2050 can be bonded to the second semiconductor structure 600, with the first wiring structure 120 of the chiplet 2050 being connected to the
• the composite of the first patterned stress film 1910 and the second stress film 1820 can be removed.
• the composite of the first patterned stress film 1910 and the second stress film 1820 (or the composite of the first stress film 1810 and the second stress film 1820) can be removed.
• the composite of the first patterned stress film 1910 and the second stress film 1820 (or the composite of the first stress film 1810 and the second stress film 1820) can be removed.
• the composite of the first patterned stress film 1910 and the second stress film 1820 (or the composite of the first stress film 1810 and the composite of the first stress film 1810 and the
• 15 second stress film 1820 can be removed via CMP, which stops at the bulk silicon 105 of the first semiconductor structure 100 where the first circuit 110 is formed.
• FIG. 45 is a flow chart illustrating a fifth exemplary method 2300 for forming a chiplet onto a semiconductor structure according to some embodiments of the present disclosure. In an embodiment, some of the steps of the fifth exemplary method 2300 shown
• the fifth exemplary method 2300 can correspond to the first, second and fourth exemplary methods shown in FIGs. 23-36 and 40-44.
• a first semiconductor structure can be provided.
• a first semiconductor structure can be provided.
• the first semiconductor structure (e.g., the first semiconductor structure 100) can include a first circuit (e.g., the first circuit 110) and a first wiring structure (e.g., the first wiring structure 120) that are formed on a first side of the first semiconductor structure (e.g., the first side 100A) and a first dielectric layer (e.g., the first dielectric layer 130) and a first substrate (e.g., the first substrate 140) that are formed on a second side of the first semiconductor
• the first side of the first semiconductor structure can be attached to a carrier substrate.
• the first side 100A of the first semiconductor 100 can be attached to the carrier substrate 150 using the attachment material 210.
• the first substrate (and the first dielectric layer) can be removed.
• the first substrate 140 and the first dielectric layer 130
• CMP CMP
• a composite of a first stress film and a second stress film can be formed on the second side (or the first dielectric layer) of the first semiconductor structure.
• the composite of the first stress film 1810 and the second stress film 1820 can be formed on the second side 100B of the first semiconductor structure 100, as shown in FIG. 40.
• the composite of the first stress film 1810 and the second stress film 1820 can be formed on the first dielectric layer 130 of the first semiconductor structure 100.
• the first stress film can be patterned to form a first patterned stress
• the first stress film can be patterned with the direct-write to form the composite of the first patterned stress film 510 and the second stress film 520, as shown in FIG. 27.
• the first stress film can be patterned to form the composite of the first patterned stress film 1910 and the second stress film 1820, as shown in FIG. 41.
• the first semiconductor structure can be separated from the carrier
• the attachment layer 210 can be heated and vaporized such that the first semiconductor structure 100 can be separated from the carrier substrate 150.
• the first semiconductor structure along with the composite of the first patterned stress film and the second stress film can be cut to define a plurality of chiplets.
• the first semiconductor structure along with the composite of the first patterned stress film and the second stress film (or the composite of the first stress film and the second stress film) can be cut to define a plurality of chiplets.
• semiconductor structure 100 along with the composite of the first patterned stress film 1910/510 and the second stress film 1820/520 (or the composite of the first stress film 1810/410 and the second stress film 1820/520) can be cut via etching, for example, to define the chiplets 750/1350/2050.
• step S2380 one or more than one of the chiplets can be bonded to another
• the chiplet 750/1350/2050 can be bonded to the second semiconductor structure 600, which has the second circuit 610 and the second wiring structure 620, with the first wiring structure 120 of the chiplet 750/1350/2050 being connected to the second wiring structure 620 of the second semiconductor structure 600.
• step S2390 the composite of the first patterned stress film and the second stress
• the composite of the first patterned stress film 1910/510 and the second stress film 1820/520 can be removed via CMP.
• FIG. 46 is a flow chart illustrating a sixth exemplary method 2400 for forming a chiplet onto a semiconductor structure according to some embodiments of the present disclosure.
• some of the steps of the sixth exemplary method 2400 shown can be performed concurrently or in a different order than shown, can be substituted by other
• the sixth exemplary method 2400 can correspond to the third exemplaiy method shown in FIGs. 37-39.
• the sixth exemplary method 2400 can also include steps S2310-S2350.
• step S2460 the first semiconductor structure along with the composite of the
• first patterned stress film and the second stress film can be cut to define a plurality of chiplets.
• first semiconductor structure 100 along with the composite of the first patterned stress film 510 and the second stress film 520 can be cut via etching, for example, to define the chiplets 750, with the carrier substrate 150 and the attachment material 210 being kept in place and the
• chiplets 750 being separated from the carrier substrate 150 at a future step at a chiplet level.
• chiplet supporters are formed on the composite of the first patterned stress film and the second stress film (or the composite of the first stress film and the second stress film) for each of the chiplets.
• the chiplet supporters 1610 can be formed on the composite of the first patterned stress film 510 and the second stress
• the chiplets can be separated from the carrier substrate,
• the attachment layer 210 can be heated and vaporized such that the chiplets 750 can be separated from the carrier substrate 150.
• step S2480 one or more than one of the chiplets can be bonded to another
• the chiplet 750 can be bonded to the second semiconductor structure 600, which has the second circuit 610 and the second wiring structure 620, with the first wiring structure 120 of the chiplet 750 being connected to the second wiring structure 620 of the second semiconductor structure 600.
• step S2490 the chiplet supporters and the composite of the first patterned stress
• the chiplet supporters 1610 and the composite of the first patterned stress film 510 and the second stress film 520 (and the first dielectric layer 130) can be removed via CMP.
• any stress combination is possible.
• Stress films can be compressive, tensile, or neutral in different regions on a semiconductor device, a die or a wafer.
• Embodiments herein include two or more compressive or tensile of the same stress type but different stress values (or alternatively they
• Examples herein show two stress films, but more than two stress films can also be used. Multiple types of stress films on a back side of chiplets can provide another degree of freedom in enhancing photolithography.
• substrate or “target substrate” as used herein generically refers to an object being processed in accordance with the invention.
• the substrate may include any material portion or structure of a device, particularly a semiconductor or other electronics device, and may, for example, be a base substrate structure, such as a semiconductor wafer, reticle, or a layer on or overlying a base substrate structure such as a thin film.
• substrate is not limited to any combination of any materials, particularly a semiconductor or other electronics device, and may, for example, be a base substrate structure, such as a semiconductor wafer, reticle, or a layer on or overlying a base substrate structure such as a thin film.
• substrate is not limited to any material portion or structure of a device, particularly a semiconductor or other electronics device, and may, for example, be a base substrate structure, such as a semiconductor wafer, reticle, or a layer on or overlying a base substrate structure such as a thin film.
• substrate is not limited to any material portion or structure of a device,

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• 2022
  • 2022-01-19 KR KR1020237028211A patent/KR20230137370A/ko unknown
  • 2022-01-19 JP JP2023544627A patent/JP2024504999A/ja active Pending
  • 2022-01-19 WO PCT/US2022/012923 patent/WO2022164693A1/en active Application Filing
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