WO2022163212A1 - Power conversion device, and control method - Google Patents

Power conversion device, and control method Download PDF

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Publication number
WO2022163212A1
WO2022163212A1 PCT/JP2021/047138 JP2021047138W WO2022163212A1 WO 2022163212 A1 WO2022163212 A1 WO 2022163212A1 JP 2021047138 W JP2021047138 W JP 2021047138W WO 2022163212 A1 WO2022163212 A1 WO 2022163212A1
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WIPO (PCT)
Prior art keywords
switch element
capacitor
voltage
value
terminal
Prior art date
Application number
PCT/JP2021/047138
Other languages
French (fr)
Japanese (ja)
Inventor
彩 村田
隆章 石井
隆圭 俵木
Original Assignee
オムロン株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by オムロン株式会社 filed Critical オムロン株式会社
Priority to EP21923215.4A priority Critical patent/EP4270766A1/en
Priority to CN202180092333.XA priority patent/CN116802985A/en
Priority to US18/262,671 priority patent/US20240305215A1/en
Publication of WO2022163212A1 publication Critical patent/WO2022163212A1/en

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    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/483Converters with outputs that each can have more than two voltages levels
    • H02M7/4837Flying capacitor converters
    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00Details of apparatus for conversion
    • H02M1/0095Hybrid converter topologies, e.g. NPC mixed with flying capacitor, thyristor converter mixed with MMC or charge pump mixed with buck
    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00Details of apparatus for conversion
    • H02M1/12Arrangements for reducing harmonics from ac input or output
    • H02M1/123Suppression of common mode voltage or current
    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/483Converters with outputs that each can have more than two voltages levels
    • H02M7/4833Capacitor voltage balancing
    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/483Converters with outputs that each can have more than two voltages levels
    • H02M7/487Neutral point clamped inverters

Definitions

  • the present invention relates to a multi-level power converter and control method using flying capacitors.
  • Patent Literatures 1 and 2 propose a multi-level power converter that uses flying capacitors to output voltages at multiple levels.
  • the voltage values of the flying capacitors are balanced at a constant voltage value in an ideal state where there are no variations in the parameters of the various components that make up the circuit.
  • the parameters of various parts that make up the circuit vary, there is a risk that the voltage values of the flying capacitors will vary.
  • the present invention has been made in view of the above circumstances, and its object is to suppress voltage fluctuations due to variations in component parameters and improve stability in a multi-level power converter using flying capacitors. It is to provide technology to improve.
  • One form of the disclosed technology for solving the above problems is a control unit, and based on a control command from the control unit, conductive or open between the drain terminal and the source terminal of the plurality of switch elements, and converts the DC power input to the first input terminal and the second input terminal to the AC power;
  • a power conversion device having a power conversion unit that converts into power and outputs from a first output terminal and a second output terminal, The power conversion unit is a first DC capacitor and a second DC capacitor connected in series between the first input terminal and the second input terminal, wherein one end of the first DC capacitor is connected to the first input terminal; , a DC capacitor circuit in which the other end of the second DC capacitor is connected to the second input terminal; one end at a connection point between a first switch element, a second switch element, a third switch element and a fourth switch element connected in series and a source terminal of the first switch element and a drain terminal of the second switch element; a first capacitor circuit having a first flying capacitor connected at the other end to a connection point between
  • a connection point between the switch element and the drain terminal is connected to a connection point between the first DC capacitor and the second DC capacitor of the DC capacitor circuit;
  • a connection point between the source terminal of the thirteenth switching element and the drain terminal of the fourteenth switching element of the second output circuit is connected to the drain terminal of the fifth switching element of the second capacitor circuit, and the fifteenth
  • a connection point between the source terminal of the switch element and the drain terminal of the sixteenth switch element is connected to the source terminal of the eighth switch element of the second capacitor circuit, and the source terminal of the fourteenth switch element and the fifteenth switch element are connected to the source terminal of the eighth switch element.
  • a connection point between the switch element and the drain terminal is connected to a connection point between the first DC capacitor and the second DC capacitor of the DC capacitor circuit;
  • the control unit Based on the amount of deviation between the detected voltage value of the first flying capacitor and the voltage command value and the amount of deviation between the detected voltage value of the second flying capacitor and the voltage command value, increasing or decreasing the period for charging and discharging the DC capacitor, the second output terminal connected to a connection point between the source terminal of the second switch element of the first capacitor circuit and the drain terminal of the third switch; and the source terminal of the sixth switch element of the second capacitor circuit. and outputting AC power from the first output terminal connected to the connection point of the drain terminal of the seventh switch, It is characterized by
  • the power converter charges and discharges the first DC capacitor dc1 and the second DC capacitor dc2 in accordance with the amount of deviation regarding the voltage (VFC1) of the flying capacitor fc1 and the amount of deviation regarding the voltage (VFC2) of the flying capacitor fc2. can be increased or decreased.
  • the voltages of the first DC capacitor dc1 and the second DC capacitor dc2 can be controlled to be constant, the stability is improved, and the accuracy of the generated AC power can be improved.
  • control unit controls the current polarity of the AC power to be positive, and when the voltage detection value of the first flying capacitor exceeds a first voltage value, the first The closed period of the second switch element (S1) of the one-capacitor circuit is increased, the closed period of the first switch element (S3) is decreased, and the detected voltage value of the first flying capacitor is less than the first voltage value.
  • the closed period of the second switch element (S1) of the first capacitor circuit may be decreased and the closed period of the first switch element (S3) may be increased.
  • the ON period (duty) of the switch elements S1 and S3 of the first flying capacitor circuit 12 is increased or decreased according to the voltage (VFC1) of the flying capacitor fc1. , the voltage control of the flying capacitor fc1 becomes possible, and the accuracy of the AC power can be improved.
  • control unit controls the current polarity of the AC power to be positive, and when the voltage detection value of the second flying capacitor exceeds a first voltage value, the first The closed period of the sixth switch element (S9) of the two-capacitor circuit is decreased, the closed period of the fifth switch element (S11) is increased, and the detected voltage value of the second flying capacitor is less than the first voltage value.
  • the closed period of the sixth switch element (S9) of the second capacitor circuit may be increased and the closed period of the fifth switch element (S11) may be decreased.
  • the ON period (duty) of the switch elements S9 and S11 of the second flying capacitor circuit 13 is increased or decreased according to the voltage (VFC2) of the flying capacitor fc2.
  • the voltage control of the flying capacitor fc2 becomes possible, and the accuracy of the AC power can be improved.
  • control unit controls the current polarity of the AC power to be negative, and when the voltage detection value of the first flying capacitor exceeds a first voltage value, the first The closed period of the second switch element (S1) of the one-capacitor circuit is decreased, the closed period of the first switch element (S3) is increased, and the detected voltage value of the first flying capacitor is less than the first voltage value.
  • the closed period of the second switch element (S1) of the first capacitor circuit may be increased and the closed period of the first switch element (S3) may be decreased.
  • the ON period (duty) of the switch elements S1 and S3 of the first flying capacitor circuit 12 is increased or decreased according to the voltage (VFC1) of the flying capacitor fc1.
  • the voltage of the flying capacitor fc1 can be controlled, and the accuracy of AC power can be improved.
  • control unit controls the current polarity of the AC power to be negative, and when the voltage detection value of the second flying capacitor exceeds a first voltage value, the first The closed period of the sixth switch element (S9) of the two-capacitor circuit is increased, the closed period of the fifth switch element (S11) is decreased, and the detected voltage value of the second flying capacitor is less than the first voltage value.
  • the closed period of the sixth switch element (S9) of the second capacitor circuit may be decreased and the closed period of the fifth switch element (S11) may be increased.
  • the ON period (duty) of the switch elements S9 and S11 of the second flying capacitor circuit 13 is increased or decreased according to the voltage (VFC2) of the flying capacitor fc2.
  • the voltage of the flying capacitor fc2 can be controlled, and the accuracy of AC power can be improved.
  • the control unit controls the voltage detection value of the second flying capacitor and the voltage command value when the voltage polarity of the AC power is positive and the current polarity is positive. is greater than the deviation between the voltage detection value of the first flying capacitor and the voltage command value, when the voltage detection value of the first DC capacitor exceeds the second voltage value, the increasing the closed period of the first switch element (S3) of the first capacitor circuit, and when the voltage detection value of the first DC capacitor is less than the second voltage value, the first switch of the first capacitor circuit; The closing period of the element (S3) may be decreased.
  • the following A switch element (S3) for interlocking and controlling the voltage (VDC1) of the first DC capacitor dc1 can be selected.
  • the voltage value (VDC1) can be controlled by increasing or decreasing the ON period (duty D3) of the switch element S3 of the first flying capacitor circuit 12 according to the voltage value (VDC1) of the first DC capacitor dc1.
  • the control unit controls the voltage detection value of the second flying capacitor and the voltage command value when the voltage polarity of the AC power is positive and the current polarity is positive. If the voltage detection value of the first DC capacitor exceeds the second voltage value on the condition that the deviation amount is smaller than the deviation amount between the voltage detection value of the first flying capacitor and the voltage command value, the increasing the closed period of the fifth switch element (S11) of the second capacitor circuit, and when the voltage detection value of the first DC capacitor is less than the second voltage value, the fifth switch of the second capacitor circuit; The closing period of the element (S11) may be decreased.
  • the following A switch element (S11) for interlocking and controlling the voltage (VDC1) of the first DC capacitor dc1 can be selected.
  • the voltage value (VDC1) can be controlled by increasing or decreasing the ON period (duty D11) of the switch element S11 of the second flying capacitor circuit 13 according to the voltage value (VDC1) of the first DC capacitor dc1.
  • control unit controls the voltage detection value and the voltage command value of the second flying capacitor when the voltage polarity of the AC power is on the negative side and the current polarity is on the negative side. is greater than the deviation between the voltage detection value of the first flying capacitor and the voltage command value, when the voltage detection value of the first DC capacitor exceeds the second voltage value, the increasing the closed period of the first switch element (S3) of the first capacitor circuit, and when the voltage detection value of the first DC capacitor is less than the second voltage value, the first switch of the first capacitor circuit; The closing period of element (S3) may be decreased.
  • a switch element (S3) for interlocking and controlling the voltage (VDC1) of the first DC capacitor dc1 can be selected.
  • the voltage value (VDC1) can be controlled by increasing or decreasing the ON period (duty D3) of the switch element S3 of the first flying capacitor circuit 12 according to the voltage value (VDC1) of the first DC capacitor dc1.
  • the control unit controls the voltage detection value and the voltage command value of the second flying capacitor when the voltage polarity of the AC power is on the negative side and the current polarity is on the negative side. is smaller than the deviation between the voltage detection value of the first flying capacitor and the voltage command value, and when the voltage detection value of the first DC capacitor exceeds the second voltage value, the increasing the closed period of the fifth switch element (S11) of the second capacitor circuit, and when the voltage detection value of the first DC capacitor is less than the second voltage value, the fifth switch of the second capacitor circuit; The closing period of the element (S11) may be decreased.
  • a switch element (S11) for interlocking and controlling the voltage (VDC1) of the first DC capacitor dc1 can be selected.
  • the voltage value (VDC1) can be controlled by increasing or decreasing the ON period (duty D11) of the switch element S11 of the second flying capacitor circuit 13 according to the voltage value (VDC1) of the first DC capacitor dc1.
  • the control unit controls the voltage detection value of the second flying capacitor and the voltage command value when the voltage polarity of the AC power is negative and the current polarity is positive. is greater than the deviation between the voltage detection value of the first flying capacitor and the voltage command value, when the voltage detection value of the first DC capacitor exceeds the second voltage value, the reducing the closed period of the first switch element (S3) of the first capacitor circuit, and when the voltage detection value of the first DC capacitor is less than the second voltage value, the first switch of the first capacitor circuit The closed period of element (S3) may be increased.
  • a switch element (S3) for interlocking and controlling the voltage (VDC1) of the first DC capacitor dc1 can be selected.
  • the voltage value (VDC1) can be controlled by increasing or decreasing the ON period (duty D3) of the switch element S3 of the first flying capacitor circuit 12 according to the voltage value (VDC1) of the first DC capacitor dc1.
  • the control unit controls the voltage detection value of the second flying capacitor and the voltage command value when the voltage polarity of the AC power is negative and the current polarity is positive. is smaller than the deviation between the voltage detection value of the first flying capacitor and the voltage command value, and when the voltage detection value of the first DC capacitor exceeds the second voltage value, the reducing the closed period of the fifth switch element (S11) of the second capacitor circuit, and when the voltage detection value of the first DC capacitor is less than the second voltage value, the fifth switch of the second capacitor circuit The closed period of the element (S11) may be increased.
  • a switch element (S11) for interlocking and controlling the voltage (VDC1) of the first DC capacitor dc1 can be selected.
  • the voltage value (VDC1) can be controlled by increasing or decreasing the ON period (duty D11) of the switch element S11 of the second flying capacitor circuit 13 according to the voltage value (VDC1) of the first DC capacitor dc1.
  • control unit controls the voltage detection value of the second flying capacitor and the voltage command value when the voltage polarity of the AC power is positive and the current polarity is negative. is greater than the deviation between the voltage detection value of the first flying capacitor and the voltage command value, when the voltage detection value of the first DC capacitor exceeds the second voltage value, the reducing the closed period of the first switch element (S3) of the first capacitor circuit, and when the voltage detection value of the first DC capacitor is less than the second voltage value, the first switch of the first capacitor circuit The closed period of element (S3) may be increased.
  • the following A switch element (S3) for interlocking and controlling the voltage (VDC1) of the first DC capacitor dc1 can be selected.
  • the voltage value (VDC1) can be controlled by increasing or decreasing the ON period (duty D3) of the switch element S3 of the first flying capacitor circuit 12 according to the voltage value (VDC1) of the first DC capacitor dc1.
  • the control unit controls the voltage detection value of the second flying capacitor and the voltage command value when the voltage polarity of the AC power is positive and the current polarity is negative. is smaller than the deviation between the voltage detection value of the first flying capacitor and the voltage command value, and when the voltage detection value of the first DC capacitor exceeds the second voltage value, the reducing the closed period of the fifth switch element (S11) of the second capacitor circuit, and when the voltage detection value of the first DC capacitor is less than the second voltage value, the fifth switch of the second capacitor circuit The closed period of the element (S11) may be increased.
  • a switch element (S11) for interlocking and controlling the voltage (VDC1) of the first DC capacitor dc1 can be selected.
  • the voltage value (VDC1) can be controlled by increasing or decreasing the ON period (duty D11) of the switch element S11 of the second flying capacitor circuit 13 according to the voltage value (VDC1) of the first DC capacitor dc1.
  • another aspect of the disclosed technique is a control unit, and based on a control command from the control unit, conductive or open between the drain terminal and the source terminal of the plurality of switch elements, and converts the DC power input to the first input terminal and the second input terminal to the AC power;
  • a control method for a power conversion device having a power conversion unit that converts into power and outputs from a first output terminal and a second output terminal, The power conversion unit is a first DC capacitor and a second DC capacitor connected in series between the first input terminal and the second input terminal, wherein one end of the first DC capacitor is connected to the first input terminal; , a DC capacitor circuit in which the other end of the second DC capacitor is connected to the second input terminal; one end at a connection point between a first switch element, a second switch element, a third switch element and a fourth switch element connected in series and a source terminal of the first switch element and a drain terminal of the second switch element; a first capacitor circuit having a first flying capacitor connected at the other end to a connection point between
  • a connection point between the switch element and the drain terminal is connected to a connection point between the first DC capacitor and the second DC capacitor of the DC capacitor circuit;
  • a connection point between the source terminal of the thirteenth switching element and the drain terminal of the fourteenth switching element of the second output circuit is connected to the drain terminal of the fifth switching element of the second capacitor circuit, and the fifteenth
  • a connection point between the source terminal of the switch element and the drain terminal of the sixteenth switch element is connected to the source terminal of the eighth switch element of the second capacitor circuit, and the source terminal of the fourteenth switch element and the fifteenth switch element are connected to the source terminal of the eighth switch element.
  • a connection point between the switch element and the drain terminal is connected to a connection point between the first DC capacitor and the second DC capacitor of the DC capacitor circuit;
  • the control unit Based on the deviation between the voltage detection value and the voltage command value of the first flying capacitor and the deviation between the voltage detection value and the voltage command value of the second flying capacitor, the first DC capacitor and the second DC capacitor increase or decrease the period of charge and discharge of the second output terminal connected to a connection point between the source terminal of the second switch element of the first capacitor circuit and the drain terminal of the third switch; and the source terminal of the sixth switch element of the second capacitor circuit. and outputting AC power from the first output terminal connected to the connection point of the drain terminal of the seventh switch, carry out
  • the power conversion device is configured such that the first DC capacitor dc1 and the second DC capacitor dc1 and the second DC capacitor dc1 and the second DC capacitor dc1
  • the period for charging and discharging DC capacitor dc2 can be increased or decreased.
  • the stability is improved, and the accuracy of the generated AC power can be improved.
  • the present invention it is possible to provide a technique for suppressing voltage fluctuations due to variations in component parameters and improving stability in a multi-level power converter using flying capacitors.
  • FIG. 4 is a diagram illustrating AC power generated by five levels of potentials according to Example 1 of the present invention; It is a figure explaining the charging/discharging mode in the flying capacitor based on Example 1 of this invention.
  • FIG. 4 is a diagram illustrating charge/discharge states in each capacitor of the power conversion unit according to Example 1 of the present invention;
  • FIG. 4 is a diagram illustrating the influence of switching time lag in Example 1 of the present invention; It is a figure explaining the voltage control of flying capacitor fc1 which concerns on Example 1 of this invention.
  • 4 is a flow chart showing an example of voltage control processing in Embodiment 1 of the present invention
  • 4 is a flow chart showing an example of voltage control processing in Embodiment 1 of the present invention
  • 4 is a flow chart showing an example of voltage control processing in Embodiment 1 of the present invention
  • 5 is a flow chart showing an example of voltage control processing in Embodiment 1 of the present invention
  • It is a figure which shows an example of the simulation result of the control process which concerns on Example 1 of this invention.
  • FIG. 1 is a block diagram showing a schematic configuration of a power converter 1 according to an application example of the present invention.
  • FIG. 1 includes a power conversion unit 10 that converts DC power supplied from a DC power supply V1 into AC power that follows a sinusoidal voltage command value using voltages of multiple levels (five levels in this embodiment).
  • a power converter is exemplified.
  • the power converter 10 includes a DC capacitor circuit 11 , a first flying capacitor circuit 12 , a second flying capacitor circuit 13 , a first output circuit 14 and a second output circuit 15 .
  • the power conversion unit 10 includes a first flying capacitor circuit 12, a second flying capacitor circuit 13, a first output circuit 14, and a second output circuit 15.
  • Neutral-Point-Clamped (hereinafter also referred to as "ANPC system") inverter circuit In the power conversion unit 10 that employs the inverter circuit of the ANPC method, the first DC capacitor dc1 and the second DC capacitor dc2 are controlled to the voltage "2E", and the flying capacitor fc1 and the flying capacitor fc2 are controlled to the voltage "E". , five levels of potentials (4E, 2E, 0, -2E, -4E) are generated.
  • the generated 5-level potential selectively controls opening/closing (on/off) of each switch element constituting the first flying capacitor circuit 12, the second flying capacitor circuit 13, the first output circuit 14, and the second output circuit 15. By doing so, they are output to the output terminals Tp3 and Tp4.
  • the DC capacitor circuit 11 includes a first DC capacitor dc1 and a second DC capacitor dc2 connected in series between the input terminal Tp1 and the input terminal Tp2.
  • One end of the first DC capacitor dc1 is connected to the input terminal Tp1
  • the terminal of the second DC capacitor dc2 opposite to the connection point with the first DC capacitor dc1 is connected to the input terminal Tp2.
  • the first flying capacitor circuit 12 has four switch elements connected in series in the order of switch element S3, switch element S1, switch element S2, and switch element S4. One end is connected to the connection point where the source terminal of the switch element S3 and the drain terminal of the switch element S1 are connected, and the other end is connected to the source terminal of the switch element S2 and the drain terminal of the switch element S4. It has a flying capacitor fc1 connected to a point. A connection point where the source terminal of the switch element S1 and the drain terminal of the switch element S2 are connected is connected to the output terminal Tp4 of the power conversion section 10 .
  • the second flying capacitor circuit 13 has four switch elements connected in series in the order of switch element S11, switch element S9, switch element S10, and switch element S12. One end is connected to the connection point where the source terminal of the switch element S11 and the drain terminal of the switch element S9 are connected, and the other end is connected to the source terminal of the switch element S10 and the drain terminal of the switch element S12. It has a flying capacitor fc2 connected to the point. A connection point where the source terminal of the switch element S9 and the drain terminal of the switch element S10 are connected is connected to the output terminal Tp3 of the power conversion section 10 .
  • the first output circuit 14 has four switch elements in which a switch element S5, a switch element S6, a switch element S7, and a switch element S8 are connected in series in order, and the drain terminal of the switch element S5 is connected to the input terminal Tp1. , the source terminal of the switch element S8 is connected to the input terminal Tp2.
  • the second output circuit 15 has four switch elements in which a switch element S13, a switch element S14, a switch element S15, and a switch element S16 are connected in series in order, and the drain terminal of the switch element S13 is connected to the input terminal Tp1. , the source terminal of the switch element S16 is connected to the input terminal Tp2.
  • connection point between the source terminal of the switch element S6 and the drain terminal of the switch element S7 in the first output circuit 14 is the connection point between the first DC capacitor dc1 and the second DC capacitor dc2 in the DC capacitor circuit 11.
  • connection point of the second output circuit 15 where the source terminal of the switch element S14 and the drain terminal of the switch element S15 are connected is the connection point of the first DC capacitor dc1 and the second DC capacitor dc2 of the DC capacitor circuit 11.
  • the drain terminal of the switch element S3 of the first flying capacitor circuit 12 is connected to the connection point of the first output circuit 14 where the source terminal of the switch element S5 and the drain terminal of the switch element S6 are connected.
  • the source terminal of the switch element S4 of the first flying capacitor circuit 12 is connected to the connection point of the first output circuit 14 where the source terminal of the switch element S7 and the drain terminal of the switch element S8 are connected.
  • the drain terminal of the switch element S11 of the second flying capacitor circuit 13 is connected to the connection point of the second output circuit 15 where the source terminal of the switch element S13 and the drain terminal of the switch element S14 are connected.
  • the source terminal of the switching element S10 of the second flying capacitor circuit 13 is connected to the connection point of the second output circuit 15 where the source terminal of the switching element S15 and the drain terminal of the switching element S16 are connected.
  • the times associated with the switching patterns of FIGS. becomes constant.
  • the voltages of the flying capacitors fc1 and fc2 are "E”
  • the voltages of the first DC capacitor dc1 and the second DC capacitor dc2 are "2E”.
  • the stray capacitances and resistances of the switch elements that make up each circuit vary, resulting in deviations in switching time. If there is a shift in switching time, the voltage output from the power converter 10 may fluctuate.
  • the power conversion device 1 controls switching of switching elements associated with charging and discharging of the flying capacitors fc1 and fc2, the first DC capacitor dc1 and the second DC capacitor dc2. By doing so, voltage fluctuations due to variations in component parameters are suppressed.
  • the control unit 30 of the power conversion device 1 increases or decreases the ON period (duty) of the switch elements S1 and S3 of the first flying capacitor circuit 12 to control the voltage of the flying capacitor fc1.
  • the control unit 30 increases or decreases the duty of the switch elements S9 and S11 of the second flying capacitor circuit 13 to control the voltage of the flying capacitor fc2.
  • the control unit 30 of the power conversion device 1 increases or decreases the duty of the switch element S3 or the switch element S11 based on the voltages of the flying capacitors fc1 and fc2, so that the first DC capacitor dc1 and voltage control of the second DC capacitor dc2.
  • the voltages of the flying capacitors fc1 and fc2, the first DC capacitor dc1 and the second DC capacitor dc2 can be controlled to be constant by switching control of the switch elements, thereby improving stability. , it is possible to increase the accuracy of the generated AC power.
  • FIG. 1 is a block diagram showing a schematic configuration of a power converter 1 according to an embodiment of the invention.
  • the power conversion device 1 includes a photovoltaic power generation device, a storage battery, a fuel cell, etc. in its configuration, and constitutes a power conditioner of a distributed power supply system that is operated in conjunction with a commercial power system.
  • Distributed power sources such as photovoltaic power generation devices, storage batteries, and fuel cells of the distributed power source system are connected to DC/DC converters capable of controlling the output of each distributed power source to form a DC power source V1.
  • the power conversion device 1 converts the DC power supplied from the DC power supply V1 into AC power, and outputs the converted AC power to the load 50 and an interconnected power system.
  • the power conversion device 1 is connected to a DC bus connecting between the power conversion device and the DC/DC converter via input terminals Tp1 and Tp2.
  • the input terminal Tp1 is connected to the positive bus of the DC bus
  • the input terminal Tp2 is connected to the negative bus of the DC bus.
  • the power conversion device 1 includes a power conversion section 10, a filter section 20, and a control section 30 in its configuration.
  • the power conversion unit 10 converts the DC power supplied from the DC power supply V1 into AC power following a sinusoidal voltage command value using voltages of multiple levels (five levels in this embodiment).
  • the AC power converted by power conversion section 10 is output to filter section 20 through output terminals Tp3 and Tp4.
  • the power converter 10 includes a DC capacitor circuit 11 , a first flying capacitor circuit 12 , a second flying capacitor circuit 13 , a first output circuit 14 and a second output circuit 15 .
  • the "DC capacitor circuit 11" corresponds to an example of the "DC capacitor circuit”
  • the "first flying capacitor circuit 12" is the "first capacitor circuit”
  • the "second flying capacitor circuit 13" is the " It corresponds to an example of "second capacitor circuit”.
  • the DC capacitor circuit 11 includes a first DC capacitor dc1 and a second DC capacitor dc2 connected in series between the input terminal Tp1 and the input terminal Tp2.
  • One end of the first DC capacitor dc1 is connected to the input terminal Tp1
  • the terminal of the second DC capacitor dc2 opposite to the connection point with the first DC capacitor dc1 is connected to the input terminal Tp2.
  • the voltage (4E) of the DC power input between the input terminals Tp1 and Tp2 is equally divided by the first DC capacitor dc1 and the second DC capacitor dc2. becomes “2E".
  • the first DC capacitor dc1 and the second DC capacitor dc2 have a snubber function that suppresses a surge voltage generated within the power conversion circuit 10 .
  • the "first DC capacitor dc1" corresponds to an example of the "first DC capacitor”
  • the "second DC capacitor dc2" corresponds to an example of the "second DC capacitor”.
  • the first flying capacitor circuit 12 includes a switch element S1, a switch element S2, a switch element S3, a switch element S4, and a capacitor fc1 (hereinafter also referred to as “flying capacitor fc1").
  • the "switch element S1" corresponds to an example of a “second switch element”
  • the "switch element S2” corresponds to an example of a “third switch element”
  • the "switch element S3" corresponds to a "third switch element”.
  • “switch element S4" corresponds to an example of "fourth switch element”.
  • the "capacitor fc1" in the embodiment corresponds to an example of the "first flying capacitor”.
  • the switch elements S1 to S4 that constitute the first flying capacitor circuit 12 are, for example, N-channel MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) and have diodes connected between the drain terminal and the source terminal. The anode of the diode is connected to the source terminal of the N-channel MOSFET, and the cathode is connected to the drain terminal.
  • the switch elements S1 to S4 constituting the first flying capacitor circuit 12 are connected in series in the order of switch element S3, switch element S1, switch element S2, and switch element S4, as shown in FIG.
  • One end of the flying capacitor fc1 is connected to a connection point where the source terminal of the switching element S3 and the drain terminal of the switching element S1 are connected, and the other end is connected to the source terminal of the switching element S2 and the drain terminal of the switching element S4. is connected to the connection point where and are connected.
  • a connection point where the source terminal of the switch element S1 and the drain terminal of the switch element S2 are connected is connected to the output terminal Tp4 of the power conversion section 10 .
  • the "output terminal Tp4" in this embodiment corresponds to an example of the "second output terminal".
  • the configuration of the second flying capacitor circuit 13 includes a switch element S9, a switch element S10, a switch element S11, a switch element S12, and a capacitor fc2 (hereinafter also referred to as "flying capacitor fc2").
  • the "switch element S9" corresponds to an example of the "sixth switch element”
  • the "switch element S10” corresponds to an example of the “seventh switch element”
  • the "switch element S11” corresponds to the "sixth switch element”.
  • the "switch element S12” corresponds to an example of the "eighth switch element”.
  • the "capacitor fc2" in this embodiment corresponds to an example of the "second flying capacitor”.
  • the switch elements S9 to S12 forming the second flying capacitor circuit 13 are the same as the switch elements forming the first flying capacitor circuit 12 . That is, it is composed of an N-channel MOSFET in which a diode is connected between the drain terminal and the source terminal.
  • the switch elements S9 to S12 constituting the second flying capacitor circuit 13 are connected in series in the order of switch element S11, switch element S9, switch element S10, and switch element S12, as shown in FIG.
  • One end of the flying capacitor fc2 is connected to a connection point where the source terminal of the switching element S11 and the drain terminal of the switching element S9 are connected, and the other end is connected to the source terminal of the switching element S10 and the drain terminal of the switching element S12. is connected to the connection point where and are connected.
  • a connection point where the source terminal of the switch element S9 and the drain terminal of the switch element S10 are connected is connected to the output terminal Tp3 of the power conversion section 10 .
  • the "output terminal Tp3" in this embodiment corresponds to an example of the "first output terminal”.
  • the configuration of the first output circuit 14 includes a switch element S5, a switch element S6, a switch element S7, and a switch element S8.
  • Each of the switch elements S5 to S8 is similar to the switch elements forming the first flying capacitor circuit 12, and has a diode whose anode is connected to the source terminal of an N-channel MOSFET and whose cathode is connected to the drain terminal.
  • the switch elements S5 to S8 are connected in series in the order of switch element S5, switch element S6, switch element S7, and switch element S8, and the drain terminal of switch element S5 is connected to input terminal Tp1.
  • the source terminal of the switch element S8 is connected to the input terminal Tp2.
  • the "switch element S5" corresponds to an example of the "ninth switch element”
  • the "switch element S6” corresponds to an example of the "tenth switch element”
  • the "switch element S7" corresponds to the "first switch element”.
  • 11 switch element and "switch element S8" corresponds to an example of "12th switch element”.
  • the configuration of the second output circuit 15 includes a switch element S13, a switch element S14, a switch element S15, and a switch element S16.
  • Each of the switch elements S13 to S16 is similar to the switch elements forming the first flying capacitor circuit 12, and has a diode whose anode is connected to the source terminal of an N-channel MOSFET and whose cathode is connected to the drain terminal.
  • the switch elements S13 to S16 are connected in series in the order of the switch element S13, the switch element S14, the switch element S15, and the switch element S16, and the drain terminal of the switch element S13 is connected to the input terminal Tp1.
  • the source terminal of the switch element S16 is connected to the input terminal Tp2.
  • the "switch element S13" corresponds to an example of the "thirteenth switch element”
  • the "switch element S14” corresponds to one example of the "fourteenth switch element”
  • the "switch element S15” corresponds to the "thirteenth switch element”.
  • 15 switch elements and the "switch element S16” corresponds to an example of the "sixteenth switch element”.
  • connection point between the source terminal of the switch element S6 and the drain terminal of the switch element S7 in the first output circuit 14 is the connection point between the first DC capacitor dc1 and the second DC capacitor dc2 in the DC capacitor circuit 11. connected to Similarly, the connection point where the source terminal of the switch element S14 and the drain terminal of the switch element S15 of the second output circuit 15 are connected is the first DC capacitor dc1 and the second DC capacitor dc2 of the DC capacitor circuit 11. connected to the connection point with The drain terminal of the switch element S3 of the first flying capacitor circuit 12 is connected to the connection point of the first output circuit 14 where the source terminal of the switch element S5 and the drain terminal of the switch element S6 are connected.
  • the source terminal of the switch element S4 of the first flying capacitor circuit 12 is connected to the connection point of the first output circuit 14 where the source terminal of the switch element S7 and the drain terminal of the switch element S8 are connected.
  • the drain terminal of the switch element S11 of the second flying capacitor circuit 13 is connected to the connection point of the second output circuit 15 where the source terminal of the switch element S13 and the drain terminal of the switch element S14 are connected.
  • the source terminal of the switching element S12 of the second flying capacitor circuit 13 is connected to the connection point of the second output circuit 15 where the source terminal of the switching element S15 and the drain terminal of the switching element S16 are connected.
  • the power conversion unit 10 has the active neutral point by the first flying capacitor circuit 12, the second flying capacitor circuit 13, the first output circuit 14, and the second output circuit 15. It is composed of a clamp type (Advanced Neutral-Point-Clamped, hereinafter also referred to as "ANPC system") inverter circuit.
  • ANPC system Advanced Neutral-Point-Clamped
  • the first DC capacitor dc1 and the second DC capacitor dc2 are set at a voltage of "2E”
  • the flying capacitor fc1 and the flying capacitor fc2 are set at a voltage of "E”.
  • 5 levels of potentials (4E, 2E, 0, -2E, -4E) are generated by controlling the potentials to .
  • the generated 5-level potential is output to the output terminal by selectively controlling the opening/closing of each switch element constituting the first flying capacitor circuit 12, the second flying capacitor circuit 13, the first output circuit 14, and the second output circuit 15. Output to Tp3 and Tp4.
  • the "open" state of each switch element represents the “off” state in which the drain terminal and the source terminal are opened
  • the "closed” state represents the connection between the drain terminal and the source terminal. represents an "on” state in which the current between the
  • the power conversion unit 10 includes a connection point where the source terminal of the switch element S1 of the first flying capacitor circuit 12 and the drain terminal of the switch element S2 are connected, and the switch of the second flying capacitor circuit 13.
  • the connection point where the source terminal of the element S9 and the drain terminal of the switch element S10 are connected the AC power with the generated 5-level potential can be output to the load 50 and the connected power system. Therefore, it flows through the reference potential (GND) between devices such as the load 50 connected to the output side of the power conversion device 1 according to the present embodiment and devices constituting the DC power supply V1 connected through the DC bus. Suppression of common mode becomes possible.
  • the filter section 20 includes an inductor 20a, an inductor 20b, and a capacitor 20c.
  • One end of the inductor 20a is connected to the output terminal Tp4, and the other end is connected to one end of the capacitor 20c.
  • One end of the inductor 20b is connected to the output terminal Tp3, and the other end is connected to the other end of the capacitor 20c.
  • the filter unit 20 reduces harmonic components of the AC power output from the first flying capacitor circuit 12 and the second flying capacitor circuit 13, and transmits the AC power to the load 50 connected to the power conversion device 1 and the interconnection.
  • the filter unit 20 the output current value io and the output voltage value vo (applied voltage of the capacitor 20c) of the AC power generated by the power conversion unit 10 and output to the load 50 side are measured through a current sensor and a voltage sensor, respectively. be.
  • the control unit 30 is a unit including a processor (CPU, etc.), memory, gate driver, communication interface circuit, and the like.
  • the control unit 30 receives outputs from various sensors (voltage sensor, current sensor) provided in the power conversion unit 10, and current sensors and voltage sensors provided in the filter unit 20 and the like. Further, the control unit 30 outputs a control signal for controlling the opening/closing (on/off) of each switch element forming the power conversion unit 10 . Based on the information detected by the various sensors described above, the control unit controls the opening and closing of the switch elements S1 to S16 so that the voltage values of the first DC capacitor dc1 and the second DC capacitor dc2 are set to "2E" and flying.
  • the voltage values of capacitor fc1 and flying capacitor fc2 are controlled to be "E". Similarly, the voltage values clamped in the first DC capacitor dc1, the second DC capacitor dc2, the flying capacitor fc1, and the flying capacitor fc2 are charged and discharged by selectively opening and closing the switch elements S1 to S16, thereby obtaining 5 levels. potentials (4E, 2E, 0, -2E, -4E).
  • the generated 5-level potential is, for example, PWM (Pulse Width Modulation) modulated by a carrier comparison method, and addition and subtraction following the sine wave voltage command value is performed based on the control pattern for selecting the opening and closing of each switch element. and output to output terminals Tp3 and Tp4.
  • FIG. 2 is a diagram for explaining AC power generated by five levels of potential.
  • FIG. 2(1) exemplifies a graph showing an AC power waveform generated by five levels of potential
  • FIG. 2(2) exemplifies a switching pattern when outputting the generated potential 2E.
  • the vertical axis represents the output voltage of the power converter 10
  • the horizontal axis represents the passage of time.
  • An output voltage “Vo” represents an AC voltage input to the filter unit 20
  • an output voltage “Vg” represents an AC voltage input to the load 50 .
  • "m" represents the modulation factor.
  • PWM modulation is performed between potentials “0" and “2E” so that the voltage value follows the sine wave voltage command value.
  • potentials “2E” and “4E” in the section surrounded by circle 1 potentials “0” and “-2E” in the section surrounded by circle 4, and potentials “-2E” and “-4E” in the section surrounded by circle 3.
  • PWM modulation is performed so that the voltage value follows the sinusoidal voltage command value.
  • the control unit 30 outputs to the output terminals Tp3 and Tp4 based on the switching pattern for outputting the AC power generated in each section so that the voltage value follows the sine wave voltage command value.
  • the switching pattern is a combination of switch elements that are conductive or open for outputting the voltage value modulated in each section following the voltage command value of the sine wave.
  • the control unit 30 selects a switching element that opens and closes according to each section and controls conduction or opening of the switching element, thereby controlling charging/discharging of the flying capacitors fc1 and fc2.
  • the energy of the flying capacitors fc1 and fc2 is charged through the energy charged in the first DC capacitor dc1 and the second DC capacitor dc2.
  • the thick solid arrow indicates the path through which the current flows during 2E output.
  • each switch element on the path indicated by the thick solid line arrow is turned on. That is, the drain terminal and the source terminal of the switch element S7 forming the first output circuit 14 are electrically connected. Then, the drain terminals and the source terminals of the switch elements S4 and S1 that constitute the first flying capacitor circuit 12 are electrically connected. Also, the drain terminal and the source terminal of the switch element S16 constituting the second output circuit 15 are electrically connected, and the drain terminal and the source terminal of the switch element S12 and the switch element S9 constituting the second flying capacitor circuit 13 are electrically connected.
  • the control unit 30 shifts the operating voltage of the gate terminal of each switch element to the ON state, and switches the switch element S7, the switch element S4, the switch element S1, the switch element S16, the switch element S12, and the switch element S9. Conduct between the drain terminal and the source terminal. As a result, the energy charged in the flying capacitor fc1 of the first flying capacitor circuit 12 is discharged, and the flying capacitor fc2 of the second flying capacitor circuit 13 is charged with energy. Then, the potential “2E” between the terminals of the second DC capacitor dc2 is applied to the output terminal Tp4 connected to the source terminal of the switch element S1 of the first flying capacitor circuit 12 and the switch element S9 of the second flying capacitor circuit 13.
  • the voltage value of the second DC capacitor dc2 is "VDC2”
  • the energy charged in the flying capacitor fc1 is “VFC1”
  • the energy charged in the flying capacitor fc2 is "VFC2”.
  • the output voltage value 'vo' for the current can be expressed as ⁇ VDC2+VFC1 ⁇ VFC2 ⁇ .
  • FIG. 3 is a diagram for explaining charging and discharging modes in flying capacitors fc1 and fc2.
  • arrows represented by thick solid lines represent paths through which current flows.
  • the first flying capacitor circuit 12 there are two types of current paths for charging and discharging the flying capacitor fc1.
  • the second flying capacitor circuit 13 there are two types of current paths for charging and discharging the flying capacitor fc2. Therefore, in the power converter 10 including the first flying capacitor circuit 12 and the second flying capacitor circuit 13, there are four types of switching patterns shown in FIGS. 3(a) to 3(d).
  • the switching elements S1 to S16 constituting each circuit of the first flying capacitor circuit 12 and the second flying capacitor circuit 13 and the first output circuit 14 and the second output circuit 15 are turned on.
  • a voltage that follows the sinusoidal voltage command value is output.
  • the encircled switching elements represent an ON state in which the drain terminal and the source terminal are electrically connected.
  • the current flows from the power converter 10 side to the load 50, and in FIGS. It becomes a flow toward the conversion unit 10 .
  • the switch element S3 and the switch element S2 of the first flying capacitor circuit 12 are electrically connected between the drain terminal and the source terminal and turned on. Further, the switch element S5 and the switch element S7 of the first output circuit 14 are electrically connected between the drain terminal and the source terminal and turned on.
  • the switch element S11 and the switch element S10 are electrically connected between the drain terminal and the source terminal, and turned on. Also, in the second output circuit 15, the switch element S14 and the switch element S16 are electrically connected between the drain terminal and the source terminal, and are turned on.
  • a directed current path is formed. That is, the switch element S5 ⁇ switch element S3 ⁇ flying capacitor fc1 ⁇ switch element S2 ⁇ load 50 ⁇ switch element S10 ⁇ flying capacitor fc2 ⁇ switch element S11 ⁇ switch element S14. A current path toward the low potential side is formed.
  • the switching pattern charges the flying capacitor fc1 and discharges the flying capacitor fc2.
  • the switch element S1 and the switch element S4 of the first flying capacitor circuit 12 are electrically connected between the drain terminal and the source terminal and turned on. Further, the switch element S5 and the switch element S7 of the first output circuit 14 are electrically connected between the drain terminal and the source terminal and turned on.
  • the switch element S9 and the switch element S12 are electrically connected between the drain terminal and the source terminal, and turned on. Also, in the second output circuit 15, the switch element S14 and the switch element S16 are electrically connected between the drain terminal and the source terminal, and are turned on.
  • a directed current path is formed. That is, from the high potential side of the second DC capacitor dc2 in the route of switch element S7 ⁇ switch element S4 ⁇ flying capacitor fc1 ⁇ switch element S1 ⁇ load 50 ⁇ switch element S9 ⁇ flying capacitor fc2 ⁇ switch element S12 ⁇ switch element S16. A current path toward the low potential side is formed. The switching pattern discharges the flying capacitor fc1 and charges the flying capacitor fc2.
  • the switch element S3 and the switch element S2 of the first flying capacitor circuit 12 are electrically connected between the drain terminal and the source terminal and turned on.
  • the switch element S6 and the switch element S8 of the first output circuit 14 are electrically connected between the drain terminal and the source terminal, and turned on.
  • the switch element S11 and the switch element S10 are electrically connected between the drain terminal and the source terminal, and turned on.
  • the switch element S13 and the switch element S15 are electrically connected between the drain terminal and the source terminal, and are turned on.
  • a current path toward the power converter 10 is formed. That is, from the high potential side of the first DC capacitor dc1 in the route of switch element S13 ⁇ switch element S11 ⁇ flying capacitor fc2 ⁇ switch element S10 ⁇ load 50 ⁇ switch element S2 ⁇ flying capacitor fc1 ⁇ switch element S3 ⁇ switch element S6. A current path toward the low potential side is formed. The switching pattern charges the flying capacitor fc2 and discharges the flying capacitor fc1.
  • the switch element S1 and the switch element S4 of the first flying capacitor circuit 12 are electrically connected between the drain terminal and the source terminal and turned on.
  • the switch element S6 and the switch element S8 of the first output circuit 14 are electrically connected between the drain terminal and the source terminal, and turned on.
  • the switch element S9 and the switch element S12 are electrically connected between the drain terminal and the source terminal, and turned on.
  • the switch element S13 and the switch element S15 are electrically connected between the drain terminal and the source terminal to be turned on.
  • a current path directed to the power conversion unit 10 is formed. That is, from the high potential side of the second DC capacitor dc2 in the route of switch element S15 ⁇ switch element S12 ⁇ flying capacitor fc2 ⁇ switch element S9 ⁇ load 50 ⁇ switch element S1 ⁇ flying capacitor fc1 ⁇ switch element S4 ⁇ switch element S8.
  • a current path toward the low potential side is formed. This switching pattern discharges the flying capacitor fc2 and charges the flying capacitor fc1.
  • FIG. 4 is a diagram for explaining the charging/discharging state of each switching pattern shown in FIG. 3 and each capacitor included in the power converter 10.
  • FIG. Tb1 in FIG. 4 illustrates a table showing the switching patterns (a) to (d) described in FIG. 3 and the charging/discharging states of the flying capacitors fc1 and fc2, the first DC capacitor dc1 and the second DC capacitor dc2. be done.
  • Tb1 in FIG. 4 in the switching pattern of FIG. 3A, the flying capacitor fc1 is charged and the flying capacitor fc2 is discharged. Also, the first DC capacitor dc1 is discharged and the second DC capacitor dc2 is charged.
  • the flying capacitor fc1 is discharged, the flying capacitor fc2 is charged, the first DC capacitor dc1 is charged, and the second DC capacitor dc2 is discharged.
  • the flying capacitor fc1 is discharged, the flying capacitor fc2 is charged, the first DC capacitor dc1 is discharged, and the second DC capacitor dc2 is charged.
  • the flying capacitor fc1 is charged, the flying capacitor fc2 is discharged, the first DC capacitor dc1 is charged, and the second DC capacitor dc2 is discharged.
  • the times associated with the switching patterns of FIGS. Become.
  • the voltages of the flying capacitors fc1 and fc2 are "E”
  • the voltages of the first DC capacitor dc1 and the second DC capacitor dc2 are "2E”.
  • the stray capacitances and resistances of the switch elements that make up each circuit vary, resulting in deviations in switching time.
  • the voltage value of the flying capacitor fc1 (VFC1), the voltage value of the flying capacitor fc2 (VFC2), the voltage value of the first DC capacitor dc1 (VDC1), and the voltage value of the second DC capacitor dc2 (VDC2) are changed from desired values. The further away, the worse the common mode noise, and the closer to the desired value, the more the common mode noise will be reduced.
  • FIG. 5 is a diagram explaining the influence of switching time lag.
  • FIG. 5(1) shows the switching state immediately before outputting 2E explained in FIG. 2(2), and FIG. Represents the state when it is slow.
  • FIG. 5(3) exemplifies a state in which the switching time of the switch element S1 is ideal.
  • the circled switch elements represent the ON state in which the drain terminal and the source terminal are electrically connected, and the thick solid arrow indicates the path through which the current flows. represents
  • the flying capacitor fc1 on the current path is discharged, the flying capacitor fc2 is charged, and the discharge energy of the flying capacitor fc1 and the charging energy of the flying capacitor fc2 are added to 2E clamped by the second DC capacitor dc2 between the terminals of the load.
  • the power conversion device 1 controls the switching of each switch element related to the charging and discharging of the flying capacitors fc1 and fc2, the first DC capacitor dc1 and the second DC capacitor dc2, thereby reducing the voltage caused by the variation in the component parameters. Control fluctuations. Specifically, the control unit 30 of the power conversion device 1 increases or decreases the ON period (duty) of the switch elements S1 and S3 of the first flying capacitor circuit 12 to control the voltage of the flying capacitor fc1. Similarly, the control unit 30 increases or decreases the duty of the switch elements S9 and S11 of the second flying capacitor circuit 13 to control the voltage of the flying capacitor fc2.
  • the control unit 30 of the power conversion device 1 increases or decreases the duty of the switch element S3 or the switch element S11 based on the voltages of the flying capacitors fc1 and fc2, so that the first DC capacitor dc1 and voltage control of the second DC capacitor dc2.
  • the voltages of the flying capacitors fc1 and fc2, the first DC capacitor dc1 and the second DC capacitor dc2 can be controlled to be constant by switching control of the switch elements, thereby improving stability. , it is possible to increase the accuracy of the generated AC power. Voltage control of the flying capacitors fc1 and fc2, the first DC capacitor dc1 and the second DC capacitor dc2 will be described below with reference to FIGS.
  • FIG. 6 is a diagram explaining voltage control of the flying capacitor fc1.
  • the current path in the flying capacitor fc1 is illustrated by a thick solid arrow.
  • a switch element surrounded by a circle represents an ON state in which the drain terminal and the source terminal are electrically connected.
  • the current path shown in (a) of FIG. 6(1) is the current path when the flying capacitor fc1 is charged, and the current path shown in (b) of FIG. 6(1) is the current path when the flying capacitor fc1 is discharged. represents the current path when In the power conversion device 1 of the present embodiment, voltage control is performed by selecting the ON/OFF states of the switch elements S1 to S4 and selecting the current path flowing through the flying capacitor fc1.
  • the drain terminal of the switching element S3 of the first flying capacitor circuit 12 receives the high voltage of the first DC capacitor dc1 through the drain terminal-source terminal of the ON state switching element S5.
  • the potential side is connected.
  • the switch element S3 and the switch element S2 are in the ON state, the drain terminal-source terminal of the switch element S3 ⁇ flying capacitor fc1 ⁇ the drain terminal-source terminal of the switch element S2 are conducted, forming a current path toward the load side. be done.
  • a current flows from the high potential side of the first DC capacitor dc1 to the load side through the drain terminal-source terminal of the ON-state switch element S5, and the flying capacitor fc1 is charged.
  • the low potential side of the first DC capacitor dc1 is connected to the source terminal of the switching element S4 of the first flying capacitor circuit 12 through the drain terminal-source terminal of the ON state switching element S7. Connected.
  • the switch element S4 and the switch element S1 are in the ON state, the drain terminal-source terminal of the switch element S4 ⁇ flying capacitor fc1 ⁇ the drain terminal-source terminal of the switch element S1 are conducted, forming a current path toward the load side. be done.
  • the flying capacitor As shown in (a) and (b) of FIG. 6 (1), by controlling the length of the ON period (duty) of the switch element S3 and the switch element S2, the switch element S4 and the switch element S1, the flying capacitor The period for charging and discharging fc1 can be controlled, and the voltage of the flying capacitor fc1 can be controlled.
  • FIG. 6(2) illustrates a relative timing chart of each switch element related to voltage control of the flying capacitor fc1.
  • the vertical axis of FIG. 6(2) represents the binary (on/off) status of each switch element, and the horizontal axis represents the passage of time.
  • the ON state and OFF state of the switch elements S1 and S2 of the first flying capacitor circuit 12 are complementarily controlled as a pair. That is, when one is on, the other is controlled to be off.
  • switch elements S3 and S4 of the first flying capacitor circuit 12 switch elements S5 and S6 of the first output circuit 14, and switch elements S7 and S8.
  • the upper part shows the on/off state transition of the switch element S1 (upper line S2)
  • the middle part shows the on/off state transition of the switch element S3 (upper line S4)
  • the lower part shows the switch element S5. (Overlined S6) and switch element S7 (overlined S8) ON/OFF state transitions are exemplified.
  • the ON period of the switch element S1 (S2 with the upper line) is also referred to as “duty D1”
  • the ON period of the switch element S3 (S4 with the upper line) is also referred to as the "duty D3".
  • FIG. 1 When the duty D1 of the switch element S1 (S2 with the overlined line) decreases (from the dashed line to the thin dashed line) and the duty D3 of the switch element S3 (S4 with the overlined line) increases (from the dashed line to the thin dashed line), FIG.
  • the charging period shown in (1)(a) becomes relatively longer, and the discharging period shown in FIG. 6(1)(b) becomes relatively shorter. Therefore, the voltage (VFC1) of the flying capacitor fc1 increases.
  • the ON/OFF states of the switch element S5 (overlined S6) and the switch element S7 (overlined S8) of the first output circuit 14 are maintained at a constant status.
  • the duty D1 which is the ON period of the switch element S1 (S2 with the upper line)
  • the duty D3 which is the ON period of the switch element S3 (S4 with the upper line)
  • VFC1 the voltage of the flying capacitor fc1.
  • FIG. 7 is a diagram for explaining voltage control of the flying capacitor fc2.
  • the current path in the flying capacitor fc2 is illustrated by a thick solid arrow.
  • the circled switch element represents an ON state in which the drain terminal and the source terminal are electrically connected, and the current path shown in (a) of FIG. 7(1) is the current path when the flying capacitor fc2 is charged.
  • (b) represents the current path when the flying capacitor fc2 is discharged.
  • voltage control is performed by selecting the ON/OFF states of the switch elements S9 to S12 and selecting the current path flowing through the flying capacitor fc2.
  • the drain terminal of the switch element S11 is connected to the first DC capacitor dc1 through the drain terminal and the source terminal of the switch element S13 in the ON state. is connected to the high potential side of
  • the drain terminal-source terminal of the switch element S11 ⁇ flying capacitor fc2 ⁇ the drain terminal-source terminal of the switch element S10 are conducted, forming a current path toward the load side. be done.
  • a current flows from the high potential side of the first DC capacitor dc1 to the load side through the drain terminal-source terminal of the ON-state switch element S13, and the flying capacitor fc2 is charged.
  • the source terminal of the switch element S12 receives the first direct current through the drain terminal-source terminal of the switch element S15 in the ON state.
  • the low potential side of capacitor dc1 is connected.
  • the switch element S12 and the switch element S9 are in the ON state, the drain terminal-source terminal of the switch element S12 ⁇ flying capacitor fc2 ⁇ drain terminal-source terminal of the switch element S9 are conducted, forming a current path toward the load side. be done.
  • a current flows from the low potential side of the first DC capacitor dc1 to the load side of the flying capacitor fc2 through the drain terminal-source terminal of the ON state switch element S15, and the flying capacitor fc2 is discharged.
  • FIG. 7(2) illustrates a relative timing chart of each switch element related to voltage control of the flying capacitor fc2.
  • the vertical axis of FIG. 7(2) represents the binary (on/off) status of each switch element, and the horizontal axis represents the passage of time.
  • the on-state and off-state of the switch elements S9 and S10 are complementarily controlled as a pair. When the switch element S9 is on, the switch element S10 is controlled to be off.
  • switch elements S11 and S12 of the second flying capacitor circuit 13 switch elements S13 and S14 of the second output circuit 15, and switch elements S15 and S16.
  • FIG. 7B shows the on/off state transition of the switch element S9 (upper line S10), the middle part shows the on/off state transition of the switch element S11 (upper line S12), and the lower part shows the switch element S13. (Overlined S14) and switch element S15 (overlined S16) ON/OFF state transitions are exemplified.
  • the ON period of the switch element S9 (S10 with the upper line) is also referred to as "duty D9”
  • the ON period of the switch element S11 (S12 with the upper line) is also referred to as the "duty D11".
  • FIG. 1 when the duty D9 of the switch element S9 (S10 with the overlined line) decreases (from the dashed line to the thin dashed line) and the duty D11 of the switch element S11 (S12 with the overlined line) increases (from the dashed line to the thin dashed line), FIG. 1)
  • the charging period shown in (a) of FIG. 7 becomes longer, and the discharging period shown in (b) of FIG. 7(1) becomes relatively shorter. Therefore, the voltage (VFC1) of the flying capacitor fc1 increases.
  • the ON/OFF states of the switch element S13 (overlined S14) and the switch element S15 (overlined S16) of the second output circuit 15 are maintained at a constant status.
  • the duty D9 which is the ON period of the switch element S9 (S10 with the upper line)
  • the duty D11 which is the ON period of the switch element S11 (S12 with the upper line)
  • FIG. 8 and 9 are diagrams for explaining voltage control of the first DC capacitor dc1 and the second DC capacitor dc2.
  • (1) also illustrates the current path in the flying capacitor fc1 by a thick solid arrow.
  • a switch element surrounded by a circle represents an ON state in which the drain terminal and the source terminal are electrically connected.
  • FIG. 8(1)(a) illustrates a current path toward the load through the ON-state switch element S3 of the first flying capacitor circuit 12.
  • a current path from the source terminal of the switch element S1 to the load side is formed to flow to the low potential side of the second DC capacitor dc2 via the load.
  • FIG. 8(1) illustrates a current path toward the load side when the switch element S3 of the first flying capacitor circuit 12 is in the OFF state. That is, the drain terminal-source terminal of the ON state switch element S7 connected to the high potential side of the second DC capacitor dc2 ⁇ drain terminal-source terminal of the switch element S4 ⁇ flying capacitor fc1 ⁇ each drain terminal of the switch element S1 ⁇ The source terminal conducts, forming a current path toward the load side. A current path from the source terminal of the switch element S1 to the load side is formed to flow to the low potential side of the second DC capacitor dc2 via the load. Therefore, the second DC capacitor dc2 and the flying capacitor fc1 on the current path are discharged. As described with reference to FIG. 6, the discharge of the flying capacitor fc1 in the OFF state of the switching element S3 of the first flying capacitor circuit 12 affects the voltage control of the flying capacitor fc1.
  • FIG. 8(2) illustrates a relative timing chart of each switch element related to voltage control of the flying capacitor fc1.
  • the vertical axis in FIG. 8(2) represents the binary (on/off) status of each switch element, and the horizontal axis represents the passage of time. and S2, and the ON and OFF states of switch elements S3 and S4 are complementarily controlled as a pair. The same applies to switch elements S5 and S6 and switch elements S7 and S8 of the first output circuit 14.
  • FIG. 8(2) illustrates a relative timing chart of each switch element related to voltage control of the flying capacitor fc1.
  • the vertical axis in FIG. 8(2) represents the binary (on/off) status of each switch element, and the horizontal axis represents the passage of time. and S2, and the ON and OFF states of switch elements S3 and S4 are complementarily controlled as a pair. The same applies to switch elements S5 and S6 and switch elements S7 and S8 of the first output circuit 14.
  • FIG. 8(2) illustrates a relative timing chart of each switch
  • the upper stage shows the on/off state transition of the switch element S1 (overlined S2)
  • the middle stage shows the on/off state transition of the switch element S3 (overlined S4)
  • the lower stage shows the switch
  • the ON/OFF state transitions of element S5 (overlined S6) and switch element S7 (overlined S8) are exemplified.
  • the duty D3 represents the ON period of the switch element S3 (S4 with an overlined line).
  • the discharge period shown in (b) becomes relatively long. That is, since the discharge period of the second DC capacitor dc2 becomes longer, the voltage (Vdc2) of the second DC capacitor dc2 decreases and the voltage (Vdc1) of the first DC capacitor dc1 increases.
  • the discharge period shown in (b) of FIG. 8(1) becomes relatively shorter. That is, since the discharge period of the second DC capacitor dc2 is shortened, the voltage (Vdc2) of the second DC capacitor dc2 increases and the voltage (Vdc1) of the first DC capacitor dc1 decreases. That is, the voltage (Vdc2) of the second DC capacitor dc2 and the voltage (Vdc1 ) becomes controllable.
  • FIG. 9 the current path in the flying capacitor fc2 is illustrated by a thick solid arrow.
  • a switch element surrounded by a circle represents an ON state in which the drain terminal and the source terminal are electrically connected.
  • (a) of FIG. 9(1) illustrates a current path toward the load through the switch element S11 in the ON state of the second flying capacitor circuit 13 . That is, a current path toward the load side is formed through each of the drain terminals and the source terminals of the ON-state switch elements S13, S11, and S9 connected to the high potential side of the first DC capacitor dc1. A current path from the source terminal of the switch element S9 to the load side is formed to flow to the low potential side of the second DC capacitor dc2 via the load.
  • FIG. 9(1) illustrates a current path toward the load side when the switch element S11 of the second flying capacitor circuit 13 is in the OFF state. That is, the drain terminal-source terminal of the ON state switch element S15 connected to the high potential side of the second DC capacitor dc2 ⁇ drain terminal-source terminal of the switch element S12 ⁇ flying capacitor fc2 ⁇ each drain terminal of the switch element S9 ⁇ The source terminal conducts, forming a current path toward the load side. A current path from the source terminal of the switch element S9 to the load side is formed to flow to the low potential side of the second DC capacitor dc2 via the load. Therefore, the second DC capacitor dc2 and the flying capacitor fc2 on the current path are discharged.
  • the discharge of the flying capacitor fc2 in the OFF state of the switch element S11 of the second flying capacitor circuit 13 affects the voltage control of the flying capacitor fc2.
  • FIG. 9(2) illustrates a relative timing chart of each switch element related to voltage control of the flying capacitor fc2.
  • the vertical axis in FIG. 9(2) represents the binary (on/off) status of each switch element, and the horizontal axis represents the passage of time.
  • S10, and the ON and OFF states of switch elements S11 and S12 are complementarily controlled as a pair.
  • the switch elements S13 and S14 and the switch elements S15 and S16 of the second output circuit 15 are the same.
  • the upper stage shows the on/off state transition of the switch element S9 (overlined S10)
  • the middle stage shows the on/off state transition of the switch element S11 (overlined S12)
  • the lower stage shows the switch
  • the on/off state transitions of element S13 (overlined S14) and switch element S15 (overlined S16) are exemplified.
  • the duty D11 represents the ON period of the switch element S11 (S12 with an overlined line).
  • the discharge period shown in (b) is lengthened. That is, since the discharge period of the second DC capacitor dc2 becomes longer, the voltage (Vdc2) of the second DC capacitor dc2 decreases and the voltage (Vdc1) of the first DC capacitor dc1 increases.
  • the discharge period shown in (b) of FIG. 9(1) is shortened. That is, since the discharge period of the second DC capacitor dc2 is shortened, the voltage (Vdc2) of the second DC capacitor dc2 increases and the voltage (Vdc1) of the first DC capacitor dc1 decreases. In FIG. 9 as well, the voltage (Vdc2) of the second DC capacitor dc2 and the voltage of the first DC capacitor dc1 are increased and decreased by relatively increasing and decreasing the length of the duty D11, which is the ON period of the switch element S11 (S12 with an upper line). The voltage (Vdc1) becomes controllable.
  • the duty D3 of the switch element S3 controls either the duty D3 of the switch element S3 or the duty D11 of the switch element S11, the voltage (Vdc1) of the first DC capacitor dc1 and the second DC capacitor dc2 voltage (Vdc2) can be relatively controlled.
  • the duty D3 of the switching element S3 influences the voltage control of the flying capacitor fc1
  • the duty D11 of the switching element S11 influences the voltage control of the flying capacitor fc2.
  • the power converter 1 based on the control voltage (VFC1) of the flying capacitor fc1 and the control voltage (VFC2) of the flying capacitor fc2, the voltage (Vdc1) of the first DC capacitor dc1 and the second A switch element to be controlled for the voltage (Vdc2) of the DC capacitor dc2 is determined.
  • the length of the determined duty period of the switch element is increased or decreased, and the voltage (Vdc1) of the first DC capacitor dc1 and the voltage (Vdc2) of the second DC capacitor dc2 are increased or decreased. controlled.
  • FIG. 10 is a diagram showing an example of the hardware configuration of the control unit 30 of the power converter 1 according to this embodiment.
  • the control unit 30 is a computer including, as constituent elements, a processor 101, a main storage device 102, an auxiliary storage device 103, a communication IF 104, and an input/output IF 105, which are interconnected by a connection bus .
  • the main storage device 102 and the auxiliary storage device 103 are recording media readable by the control unit 30 .
  • a plurality of the above components may be provided, or some of the components may be omitted.
  • the processor 101 is a central processing unit that controls the control unit 30 as a whole.
  • the processor 101 is, for example, a CPU (Central Processing Unit), an MPU (Micro-Processing Unit), a DSP (Digital Signal Processor), or the like.
  • the processor 101 for example, develops a program stored in the auxiliary storage device 103 in a work area of the main storage device 102 so that it can be executed, and controls peripheral devices through execution of the program to perform a function that meets a predetermined purpose. I will provide a.
  • some or all of the functions provided by the processor 101 may be provided by an ASIC (Application Specific Integrated Circuit), a GPU (Graphics Processing Unit), or the like.
  • some or all of the functions may be implemented by FPGAs (Field-Programmable Gate Arrays), dedicated LSIs (large scale integration) such as numerical processors, and other hardware circuits.
  • the main storage device 102 and the auxiliary storage device 103 constitute the memory of the control unit 30 .
  • the main storage device 102 stores programs executed by the processor 101, data processed by the processor, and the like.
  • the main storage device 102 includes flash memory, RAM (Random Access Memory), and ROM (Read Only Memory).
  • the auxiliary storage device 103 is a storage medium that stores programs to be executed by the processor 101 or the like, operation setting information, and the like.
  • the auxiliary storage device 103 includes, for example, a HDD (Hard-disk Drive), SSD (Solid State Drive), EPROM (Erasable Programmable ROM), flash memory, USB memory, SD (Secure Digital) memory card, and the like.
  • Communication IF 104 is a communication interface.
  • the communication IF 104 can adopt an appropriate configuration according to the connection method with the device to be connected. In this embodiment, various control commands to and from the power converter 10 connected via the communication IF 104 are notified. Furthermore, in the present embodiment, output signals of various sensors provided in each part of the power converter 1 connected through the communication IF 104 are acquired.
  • the input/output IF 105 is an interface for inputting/outputting data between an input device and an output device provided in the power converter 1 . It is output to a display device such as an LCD through the input/output IF 105 . Further, an operation instruction is received through the input/output IF 105, and processing intended by the operator is performed based on the operation instruction.
  • 11 to 14 are flowcharts showing an example of voltage control processing provided by the power converter 1 according to this embodiment.
  • 11 to 14 the voltages of the interlocked flying capacitors fc1 and fc2, the first DC capacitor dc1 and the second DC capacitor dc2 are stabilized.
  • the voltage control process according to the present embodiment is based on the polarity of the output voltage (vo; voltage applied to the capacitor 20c) of the AC power output to the load 50, the output current (io), and the output current (io).
  • the processing is performed according to the relative relationship with the polarity of .
  • the relative phase region (region on the time axis) between the output voltage (vo) and the output current (io) of the AC power output to the load 50 side is the first
  • the area is divided into a fourth area.
  • the first region is, for example, classified as a phase region in which the polarity of the output voltage is on the positive side and the polarity of the output current is on the positive side.
  • the second region is classified as a phase region in which, for example, the polarity of the output voltage is negative and the polarity of the output current is negative.
  • phase region in which the polarity of the output voltage is positive and the polarity of the output current is negative is classified as a third region, and the phase in which the polarity of the output voltage is negative and the polarity of the output current is positive is classified as the fourth area.
  • the relative phase region between the output voltage (vo) and the output current (io) of the AC power output to the load 50 side divided into the first region to the fourth region By performing the voltage control process according to , it is possible to improve the stability of the voltage conversion process and improve the accuracy of the AC power.
  • FIG. 11 is a flowchart showing an example of voltage control processing in the first region.
  • the relative phase area between the output voltage (vo) and the output current (io) to be controlled in this flow is illustrated as a hatched rectangular area.
  • the control unit 30 of the power converter 1 acquires the voltage value (VFC1) of the flying capacitor fc1 through the voltage sensor provided in the first flying capacitor circuit 12 .
  • step S101 if the voltage value (VFC1) of the flying capacitor fc1 exceeds the constant value (E) (step S101, ">E"), the process proceeds to step S102, and if it is less than the constant value (E) (step S101, " ⁇ E"), the process proceeds to step S103.
  • step S102 switching control of the first flying capacitor circuit 12 is performed so that the voltage value (VFC1) of the flying capacitor fc1 becomes a constant value (E). Specifically, as described with reference to FIG. 6, the length of the "duty D1" specified by the on/off period of the switch element S1 (overlined S2) is increased, and the length of the switch element S3 (overlined S4) is increased. Decrease the length of "duty D3" specified by the ON/OFF period. With such switching control, the discharge period of the flying capacitor fc1 becomes relatively long, and the voltage value (VFC1) of the flying capacitor fc1 decreases to a constant value (E). After the process of step S102, the process proceeds to step S104.
  • step S103 switching control of the first flying capacitor circuit 12 is performed so that the voltage value (VFC1) of the flying capacitor fc1 becomes a constant value (E).
  • the length of the "duty D1" specified by the ON/OFF period of the switch element S1 (S2 with the overlined line) is reduced, and the length of the "duty D1" of the switch element S3 (S4 with the overlined line) is Increase the length of "duty D3" specified by the ON/OFF period.
  • the discharge period of the flying capacitor fc1 becomes relatively short, and the voltage value (VFC1) of the flying capacitor fc1 increases to a constant value (E).
  • step S105 switching control of the second flying capacitor circuit 13 is performed so that the voltage value (VFC2) of the flying capacitor fc2 becomes a constant value (E). Specifically, the length of the "duty D9" specified by the ON period of the switch element S9 (overlined S10) is reduced, and the "duty D11” specified by the ON period of the switch element S11 (overlined S12) is reduced. increase the length of That is, since the polarity of the current is positive in the first region, the charge/discharge relationship described with reference to FIG. 7 is reversed. By such switching control, the discharge period of the flying capacitor fc2 becomes relatively long, and the voltage value (VFC2) of the flying capacitor fc2 decreases to a constant value (E). After the process of step S105, the process proceeds to step S107.
  • step S106 switching control of the second flying capacitor circuit 13 is performed so that the voltage value (VFC2) of the flying capacitor fc2 becomes a constant value (E). Specifically, the length of the "duty D9" specified by the ON period of the switch element S9 (S10 with the overlined line) is increased, and the "duty D11” specified by the ON period of the switch element S11 (S12 with the overlined line) is increased. decrease the length of By such switching control, the discharge period of the flying capacitor fc2 becomes relatively short, and the voltage value (VFC2) of the flying capacitor fc2 increases to a constant value (E). After the process of step S106, the process proceeds to step S107.
  • step S107 based on the voltage (VFC1) of the flying capacitor fc1 and the voltage (VFC2) of the flying capacitor fc2, the voltage (VDC1) of the first DC capacitor dc1 and the voltage (VDC2) of the second DC capacitor dc2 are interlocked.
  • a switch element to be manipulated to control is determined. Specifically, a sine wave voltage command value that generates AC power using five levels of potential (4E, 2E, 0, ⁇ 2E, ⁇ 4E), and each flying capacitor voltage value for the voltage command value A switch element to be controlled is determined according to the deviation.
  • step S107 the control unit 30 obtains the deviation (absolute value of difference, "
  • step S107 If the deviation amount (
  • step S108 it is determined whether the voltage value of the first DC capacitor dc1 is a constant value (2E).
  • step S109 switching control of the first flying capacitor circuit 12 is performed so that the voltage value (VDC1) of the first DC capacitor dc1 becomes a constant value (2E). Specifically, the length of the "duty D3" specified by the ON period of the switch element S3 (overlined S4) is increased. Through such switching control, the discharge period of the second DC capacitor dc2 becomes relatively short, and the voltage value (VDC1) of the first DC capacitor dc1 decreases to a constant value (2E). After the processing of step S109, the processing of this routine is once terminated.
  • step S110 switching control of the first flying capacitor circuit 12 is performed so that the voltage value (VDC1) of the first DC capacitor dc1 becomes a constant value (2E). Specifically, the length of the "duty D3" specified by the ON period of the switch element S3 (overlined S4) is reduced. By such switching control, the discharge period of the second DC capacitor dc2 becomes relatively long, and the voltage value (VDC1) of the first DC capacitor dc1 increases to a constant value (2E). After the processing of step S110, the processing of this routine is once terminated.
  • step S111 it is determined whether the voltage value of the first DC capacitor dc1 is a constant value (2E).
  • step S112 switching control of the second flying capacitor circuit 13 is performed so that the voltage value (VDC1) of the first DC capacitor dc1 becomes a constant value (2E). Specifically, the length of the "duty D11" specified by the ON period of the switch element S11 (overlined S12) is increased. Through such switching control, the discharge period of the second DC capacitor dc2 becomes relatively short, and the voltage value (VDC1) of the first DC capacitor dc1 decreases to a constant value (2E). After the processing of step S112, the processing of this routine is temporarily terminated.
  • step S113 switching control of the second flying capacitor circuit 13 is performed so that the voltage value (VDC1) of the first DC capacitor dc1 becomes a constant value (2E).
  • the length of the "duty D11" specified by the ON period of the switch element S11 (S12 with an overlined line) is decreased.
  • the discharge period of the second DC capacitor dc2 becomes relatively long, and the voltage value (VDC1) of the first DC capacitor dc1 increases to a constant value (2E).
  • the duty of the switch element S1 (S2 with the upper line) By increasing the length of D1, it is possible to decrease the length of the duty D3 of the switch element S3 (overlined S4).
  • the length of the discharge period of the flying capacitor fc1 can be controlled to be longer, and the voltage value (VFC1) can be reduced to a constant value (E).
  • the length of the duty D1 of the switch element S1 (overlined S2) is can be reduced, and the length of the duty D3 of the switch element S3 (overlined S4) can be increased.
  • the length of the discharge period of the flying capacitor fc1 can be controlled to be shortened, and the voltage value (VFC1) can be increased to a constant value (E).
  • the length of the duty D9 of the switch element S9 (S10 with an upper line) is set to can be reduced, and the length of the duty D11 of the switch element S11 (S12 with an overlined line) can be increased.
  • the length of the discharge period of the flying capacitor fc2 can be controlled to be longer, and the voltage value (VFC2) can be reduced to a constant value (E).
  • the length of the duty D9 of the switch element S9 (S10 with an upper line) is set to can be increased, and the length of the duty D11 of the switch element S11 (overlined S12) can be reduced.
  • the length of the discharge period of the flying capacitor fc2 can be controlled to be shortened, and the voltage value (VFC2) can be increased to a constant value (E).
  • the voltage of the first DC capacitor dc1 ( A switch element for interlocking and controlling VDC1) can be selected.
  • the voltage value (VDC1) of the first DC capacitor dc1 is controlled to a constant value (2E).
  • the voltage value (VDC1) of the first DC capacitor dc1 is set to a constant value (2E).
  • a switch element S11 (overlined S12) can be selected for controlling
  • the voltage value (VDC1) of the first DC capacitor dc1 exceeds a constant value (2E)
  • the length of the duty D3 of the switch element S3 If it is less than a certain value (2E), the length of duty D3 can be decreased.
  • the voltage value (VDC1) of the first DC capacitor dc1 can be controlled to a constant value (2E) based on the length of the duty D3 of the switch element S3 (overlined S4).
  • the length of the duty D11 of the switch element S11 when the voltage value (VDC1) of the first DC capacitor dc1 exceeds a certain value (2E), the length of the duty D11 of the switch element S11 (S12 with an overlined line)
  • the length of the duty D11 can be decreased when the duty D11 is less than a constant value (2E).
  • the voltage value (VDC1) of the first DC capacitor dc1 is set to a constant value (2E) based on the length of the duty D11 of the switch element S11 (S12 with an overlined line). You can control it.
  • FIG. 12 is a flowchart showing an example of voltage control processing in the second area.
  • the relative phase area between the output voltage (vo) and the output current (io) to be controlled in this flow is illustrated as a hatched rectangular area.
  • a voltage value (VFC1) of the flying capacitor fc1 is obtained through a voltage sensor provided in the first flying capacitor circuit 12 .
  • step S122 switching control of the first flying capacitor circuit 12 is performed so that the voltage value (VFC1) of the flying capacitor fc1 becomes a constant value (E). Specifically, as described with reference to FIG. 6, the length of the "duty D1" specified by the ON period of the switch element S1 (S2 with the overlined line) is reduced, and the ON period of the switch element S3 (S4 with the overlined line) is reduced. Increase the length of "duty D3" specified by . With such switching control, the discharge period of the flying capacitor fc1 becomes relatively long, and the voltage value (VFC1) of the flying capacitor fc1 decreases to a constant value (E). After the process of step S122, the process proceeds to step S124.
  • step S123 switching control of the first flying capacitor circuit 12 is performed so that the voltage value (VFC1) of the flying capacitor fc1 becomes a constant value (E).
  • the length of the "duty D1" specified by the ON period of the switch element S1 (S2 with the overlined line) is increased, and the ON period of the switch element S3 (S4 with the overlined line) is increased. Decrease the length of "duty D3" specified by .
  • the discharge period of the flying capacitor fc1 becomes relatively short, and the voltage value (VFC1) of the flying capacitor fc1 increases to a constant value (E).
  • step S124 it is determined whether the voltage value of the flying capacitor fc2 is a constant value (E).
  • a voltage value (VFC2) of the flying capacitor fc2 is acquired through a voltage sensor provided in the second flying capacitor circuit 13 . Then, when the voltage value (VFC2) of the flying capacitor fc2 exceeds the constant value (E) (step S124, ">E"), the process proceeds to step S125, and when it is less than the constant value (E) ( Step S124, " ⁇ E"), and the process proceeds to step S126.
  • step S125 switching control of the second flying capacitor circuit 13 is performed so that the voltage value (VFC2) of the flying capacitor fc2 becomes a constant value (E).
  • the length of the "duty D9" specified by the ON period of the switch element S9 (S10 with the upper line) is increased, and the ON period of the switch element S11 (S12 with the upper line) is increased. Decrease the length of "duty D11" specified by .
  • the discharge period of the flying capacitor fc2 becomes relatively long, and the voltage value (VFC2) of the flying capacitor fc2 decreases to a constant value (E).
  • step S126 switching control of the second flying capacitor circuit 13 is performed so that the voltage value (VFC2) of the flying capacitor fc2 becomes a constant value (E).
  • the length of the "duty D9" specified by the on-period of the switch element S9 (overlined S10) is reduced, and the on-period of the switch element S11 (overlined S12) is reduced.
  • the discharge period of the flying capacitor fc2 becomes relatively short, and the voltage value (VFC2) of the flying capacitor fc2 increases to a constant value (E).
  • step S127 to step S133 the process from step S107 to step S113 shown in the flow of FIG. 11 is executed. That is, the amount of deviation (
  • step S127, “YES” when the deviation amount (
  • the duty of the switching element S1 (S2 with the upper line)
  • the length of D1 can be decreased and the length of duty D3 of switch element S3 (S4 with an overlined line) can be increased.
  • the length of the discharge period of the flying capacitor fc1 can be controlled to be relatively long, and the voltage value (VFC1) can be reduced to a constant value (E).
  • the length of the duty D1 of the switch element S1 (S2 with an upper line) is set to can be increased, and the length of the duty D3 of the switch element S3 (overlined S4) can be reduced.
  • the length of the discharge period of the flying capacitor fc1 can be controlled to be shortened, and the voltage value (VFC1) can be increased to a constant value (E).
  • the length of the duty D9 of the switch element S9 (S10 with an upper line) is set to can be increased, and the length of the duty D11 of the switch element S11 (overlined S12) can be reduced.
  • the length of the discharge period of the flying capacitor fc2 can be controlled to be longer, and the voltage value (VFC2) can be reduced to a constant value (E).
  • the length of the duty D9 of the switch element S9 (S10 with an upper line) is set to can be reduced, and the length of the duty D11 of the switch element S11 (S12 with an overlined line) can be increased.
  • the length of the discharge period of the flying capacitor fc2 can be controlled to be shortened, and the voltage value (VFC2) can be increased to a constant value (E).
  • the voltage (VDC1) of the first DC capacitor dc1 is adjusted according to the deviation amount regarding the voltage (VFC1) of the flying capacitor fc1 and the deviation amount regarding the voltage (VFC2) of the flying capacitor fc2.
  • a switch element for interlocking control can be selected.
  • the voltage value (VDC1) of the first DC capacitor dc1 is controlled to a constant value (2E). can be selected.
  • the voltage value (VDC1) of the first DC capacitor dc1 is set to a constant value (2E).
  • a switch element S11 (overlined S12) can be selected for controlling
  • the length of the duty D3 of the switch element S3 (S4 with an overlined line)
  • the length of the duty D3 can be decreased if it is less than a certain value (2E).
  • the voltage value (VDC1) of the first DC capacitor dc1 can be controlled to a constant value (2E) based on the length of the duty D3 of the switch element S3 (overlined S4).
  • the length of the duty D11 of the switch element S11 when the voltage value (VDC1) of the first DC capacitor dc1 exceeds a constant value (2E), the length of the duty D11 of the switch element S11 (S12 with an overlined line) The length of the duty D11 can be decreased when the duty D11 is less than a constant value (2E). Even in such a switching control form, the voltage value (VDC1) of the first DC capacitor dc1 is set to a constant value (2E) based on the length of the duty D11 of the switch element S11 (S12 with an overlined line). You can control it.
  • FIG. 13 is a flowchart showing an example of voltage control processing in the third area.
  • the relative phase area between the output voltage (vo) and the output current (io) to be controlled in this flow is illustrated as a hatched rectangular area.
  • the processing of steps S121 to S126 shown in the flow of FIG. 12 is executed in the processing of steps S141 to S146 executed after the start of the voltage control processing.
  • step S141 when the voltage value (VFC1) of the flying capacitor fc1 exceeds a certain value (E) (step S141, ">E"), the length of the duty D1 of the switch element S1 (overlined S2) is reduced, The length of the duty D3 of the switch element S3 (overlined S4) is increased (step S142). Further, when the voltage value (VFC1) of the flying capacitor fc1 is less than the constant value (E) (step S141, " ⁇ E"), the length of the duty D1 of the switch element S1 (overlined S2) is increased, The length of duty D3 of switch element S3 (overlined S4) is decreased (step S143).
  • step S142 relatively lengthens the discharge period of the flying capacitor fc1, and decreases the voltage value (VFC1) of the flying capacitor fc1 to a constant value (E). Moreover, the discharge period of the flying capacitor fc1 is relatively shortened by the process of step S143, and the voltage value (VFC1) of the flying capacitor fc1 increases to a constant value (E).
  • step S144 when the voltage value (VFC2) of the flying capacitor fc2 exceeds a certain value (E) (step S144, “>E"), the length of the duty D9 of the switch element S9 (S10 with an overlined line) is increased, The length of the duty D11 of the switch element S11 (overlined S12) is decreased (step S145). Further, when the voltage value (VFC2) of the flying capacitor fc2 is less than the constant value (E) (step S144, " ⁇ E"), the length of the duty D9 of the switch element S9 (S10 with an overlined line) is reduced, The length of duty D11 of switch element S11 (overlined S12) is increased (step S146).
  • step S145 the discharge period of the flying capacitor fc2 becomes relatively long, and the voltage value (VFC2) of the flying capacitor fc2 decreases to a constant value (E). Moreover, the discharge period of the flying capacitor fc2 is relatively shortened by the process of step S146, and the voltage value (VFC2) of the flying capacitor fc2 increases to a constant value (E). After the process of step S146, the process proceeds to step S147.
  • step S147 the process of step S107 shown in the flow of FIG. 11 is executed. That is, the amount of deviation (
  • step S147 if the deviation amount (
  • step S148 it is determined whether the voltage value of the first DC capacitor dc1 is a constant value (2E).
  • a voltage value (VDC1) of the first DC capacitor dc1 is obtained through a voltage sensor provided in the first output circuit 14 . Then, if the voltage value (VDC1) of the first DC capacitor dc1 exceeds the constant value (2E) (step S148, ">2E"), the process proceeds to step S149, and if it is less than the constant value (2E) (step S148, " ⁇ 2E"), the process proceeds to step S150.
  • step S149 switching control of the first flying capacitor circuit 12 is performed so that the voltage value (VDC1) of the first DC capacitor dc1 becomes a constant value (2E). Specifically, as described with reference to FIG. 8, the length of the "duty D3" specified by the on/off period of the switch element S3 (overlined S4) is reduced. Through such switching control, the discharge period of the second DC capacitor dc2 becomes relatively short, and the voltage value (VDC1) of the first DC capacitor dc1 decreases to a constant value (2E). After the process of step S149, the process of this routine is once terminated.
  • step S150 switching control of the first flying capacitor circuit 12 is performed so that the voltage value (VDC1) of the first DC capacitor dc1 becomes a constant value (2E). Specifically, the length of the duty D3 specified by the ON period of the switch element S3 (overlined S4) is increased. By such switching control, the discharge period of the second DC capacitor dc2 becomes relatively long, and the voltage value (VDC1) of the first DC capacitor dc1 increases to a constant value (2E).
  • step S150 the processing of this routine is once terminated.
  • step S151 it is determined whether the voltage value of the first DC capacitor dc1 is a constant value (2E).
  • a voltage value (VDC1) of the first DC capacitor dc1 is obtained through a voltage sensor provided in the first output circuit 14 . Then, if the voltage value (VDC1) of the first DC capacitor dc1 exceeds the constant value (2E) (step S151, ">2E"), the process proceeds to step S152, and if it is less than the constant value (2E) (step S151, " ⁇ 2E"), the process proceeds to step S153.
  • step S152 switching control of the second flying capacitor circuit 13 is performed so that the voltage value (VDC1) of the first DC capacitor dc1 becomes a constant value (2E). Specifically, the length of the duty D11 specified by the ON period of the switch element S11 (overlined S12) is reduced. Through such switching control, the discharge period of the second DC capacitor dc2 becomes relatively short, and the voltage value (VDC1) of the first DC capacitor dc1 decreases to a constant value (2E). After the process of step S152, the process of this routine is temporarily terminated.
  • step S153 switching control of the second flying capacitor circuit 13 is performed so that the voltage value (VDC1) of the first DC capacitor dc1 becomes a constant value (2E).
  • the length of duty D11 specified by the ON period of switch element S11 (overlined S12) is increased.
  • the discharge period of the second DC capacitor dc2 becomes relatively long, and the voltage value (VDC1) of the first DC capacitor dc1 increases to a constant value (2E).
  • the switch element S1 ( The length of the duty D1 of S2) can be decreased, and the length of the duty D3 of the switch element S3 (S4 with an overlined line) can be increased.
  • the voltage value (VFC1) can be decreased to a constant value (E).
  • the voltage value (VFC1) of the flying capacitor fc1 is less than the constant value (E)
  • the length of the duty D1 of the switch element S1 (S2 with the upper line) is increased, and the duty D1 of the switch element S3 (S4 with the upper line) is increased.
  • the length of duty D3 can be reduced.
  • the length of the duty D9 of the switch element S9 (S10 with an overlined line) is increased, and the switch element S11 The length of the duty D11 of (S12 with an overline) can be reduced.
  • the length of the discharge period of the flying capacitor fc2 can be controlled to be relatively long, and the voltage value (VFC2) can be reduced to a constant value (E).
  • the voltage value (VFC2) of the flying capacitor fc2 is less than the constant value (E)
  • the length of the duty D9 of the switch element S9 (S10 with the upper line) is reduced, and the duty D9 of the switch element S11 (S12 with the upper line) is reduced.
  • the length of duty D11 can be increased.
  • the voltage (VDC1) of the first DC capacitor dc1 is adjusted according to the deviation amount regarding the voltage (VFC1) of the flying capacitor fc1 and the deviation amount regarding the voltage (VFC2) of the flying capacitor fc2.
  • a switch element for interlocking control can be selected.
  • the voltage value (VDC1) of the first DC capacitor dc1 is controlled to a constant value (2E). can be selected.
  • the voltage value (VDC1) of the first DC capacitor dc1 is set to a constant value (2E).
  • a switch element S11 (overlined S12) can be selected for controlling
  • the voltage value (VDC1) of the first DC capacitor dc1 exceeds a constant value (2E)
  • the length of the duty D3 of the switch element S3 If it is less than a certain value (2E), the length of duty D3 can be increased.
  • the voltage value (VDC1) of the first DC capacitor dc1 can be controlled to a constant value (2E) based on the length of the duty D3 of the switch element S3 (overlined S4).
  • the voltage value (VDC1) of the first DC capacitor dc1 exceeds a constant value (2E)
  • the length of the duty D11 of the switch element S11 If it is less than a certain value (2E), the length of duty D11 can be increased.
  • the voltage value (VDC1) of the first DC capacitor dc1 is set to a constant value (2E) based on the length of the duty D11 of the switch element S11 (S12 with an overlined line). You can control it.
  • FIG. 14 is a flowchart showing an example of voltage control processing in the fourth area.
  • the relative phase area between the output voltage (vo) and the output current (io) to be controlled in this flow is illustrated as a hatched rectangular area.
  • the processing of steps S161 to S166 executed after the start of the voltage control processing the processing of steps S101 to S106 shown in the flow of FIG. 11 is executed.
  • step S161 when the voltage value (VFC1) of the flying capacitor fc1 exceeds a certain value (E) (step S161, ">E"), the length of the duty D1 of the switch element S1 (overlined S2) is increased, The length of duty D3 of switch element S3 (overlined S4) is decreased (step S162). Further, when the voltage value (VFC1) of the flying capacitor fc1 is less than the constant value (E) (step S161, " ⁇ E"), the length of the duty D1 of the switch element S1 (overlined S2) is reduced, The length of duty D3 of switch element S3 (overlined S4) is increased (step S163).
  • step S162 the discharge period of the flying capacitor fc1 becomes relatively long, and the voltage value (VFC1) of the flying capacitor fc1 decreases to a constant value (E). Moreover, the discharge period of the flying capacitor fc1 is relatively shortened by the process of step S163, and the voltage value (VFC1) of the flying capacitor fc1 increases to a constant value (E).
  • step S164 when the voltage value (VFC2) of the flying capacitor fc2 exceeds a certain value (E) (step S164, ">E"), the length of the duty D9 of the switch element S9 (S10 with an overlined line) is reduced, The length of the duty D11 of the switch element S11 (overlined S12) is increased (step S165). Further, when the voltage value (VFC2) of the flying capacitor fc2 is less than the constant value (E) (step S164, " ⁇ E"), the length of the duty D9 of the switch element S9 (S10 with an overlined line) is increased, The length of duty D11 of switch element S11 (overlined S12) is decreased (step S166).
  • step S165 the discharge period of the flying capacitor fc2 is relatively lengthened, and the voltage value (VFC2) of the flying capacitor fc2 decreases to a constant value (E). Moreover, the discharge period of the flying capacitor fc2 is relatively shortened by the process of step S166, and the voltage value (VFC2) of the flying capacitor fc2 increases to a constant value (E). After the process of step S166, the process proceeds to step S167.
  • step S167 to step S173 the process from step S147 to step S153 shown in the flow of FIG. 13 is executed. That is, the amount of deviation (
  • step S167, “YES” when the deviation amount (
  • the switching element S1 (overlined The length of the duty D1 of S2) can be increased, and the length of the duty D3 of the switch element S3 (overlined S4) can be decreased.
  • the voltage value (VFC1) can be decreased to a constant value (E).
  • the length of the duty D1 of the switch element S1 (S2 with the upper line) is reduced, and the duty D1 of the switch element S3 (S4 with the upper line) is reduced.
  • the length of duty D3 can be increased.
  • the length of the duty D9 of the switch element S9 (S10 with an overlined line) is reduced, and the switch element S11 (Overlined S12) can increase the length of the duty D11.
  • the length of the discharge period of the flying capacitor fc2 can be controlled to be relatively long, and the voltage value (VFC2) can be reduced to a constant value (E).
  • the length of the duty D9 of the switch element S9 (S10 with the upper line) is increased, and the duty D9 of the switch element S11 (S12 with the upper line) is The length of duty D11 can be reduced.
  • the discharge period of the flying capacitor fc2 can be relatively shortened, and the voltage value (VFC2) can be increased to a constant value (E).
  • the voltage (VDC1) of the first DC capacitor dc1 is changed according to the deviation amount regarding the voltage (VFC1) of the flying capacitor fc1 and the deviation amount regarding the voltage (VFC2) of the flying capacitor fc2.
  • a switch element for interlocking control can be selected.
  • the voltage value (VDC1) of the first DC capacitor dc1 is controlled to a constant value (2E). can be selected.
  • the voltage value (VDC1) of the first DC capacitor dc1 is set to a constant value (2E).
  • a switch element S11 (overlined S12) can be selected for controlling
  • the power conversion device 1 sets the length of the duty D3 of the switch element S3 (S4 with an overlined line) to If it is decreased and is less than a constant value (2E), the length of duty D3 can be increased.
  • the voltage value (VDC1) of the first DC capacitor dc1 can be controlled to a constant value (2E) based on the length of the duty D3 of the switch element S3 (overlined S4).
  • the voltage value (VDC1) of the first DC capacitor dc1 exceeds the constant value (2E)
  • the length of the duty D11 of the switch element S11 is reduced, In this case, the length of duty D11 can be increased.
  • the voltage value (VDC1) of the first DC capacitor dc1 is set to a constant value (2E) based on the length of the duty D11 of the switch element S11 (S12 with an overlined line). You can control it.
  • FIG. 15 is a diagram showing simulation results by the voltage control method according to this embodiment.
  • the simulation conditions are an input voltage of "330 V”, an output voltage of "202 V”, an output power of "5500 W", an output frequency of "50 Hz", and a power factor of "1".
  • the first stage of FIG. 15 illustrates a graph representing the transition of the input voltage of the DC power supply V1 over time, and the second stage illustrates a graph representing the transition of the input current of the DC power supply V1.
  • the transition of the inverter output voltage (the voltage between the output terminals Tp3 and Tp4) is shown in the third stage, the transition of the voltage applied to the capacitor 20 is shown in the fourth stage, and the output current (io) is shown in the fifth stage.
  • Graphs showing transitions, transitions of capacitor voltages (VFC1, VFC2) on the sixth stage, transitions of DDV (VDC1, VDC2) on the seventh stage, and transitions of output power on the eighth stage are exemplified.
  • the voltages of the flying capacitors fc1 and fc2 fluctuate over time if the voltage control method of this embodiment is not employed.
  • the voltage value of the flying capacitor fc2 (VFC2_no control) rises over time and changes from around 80V to around 150V.
  • the voltage value of the flying capacitor fc1 (VFC1_no control) drops over time and changes from around 80V to around 30V.
  • the voltage values of the flying capacitors fc1 and fc2 change at roughly constant values as indicated by the dashed lines.
  • the voltages of the first DC capacitor dc1 and the second DC capacitor dc2 also fluctuate over time if the voltage control method of this embodiment is not employed.
  • the voltage value (Vdc1_no control) of the first DC capacitor dc1 indicated by the dashed-dotted line rises over time and changes from around 165V to around 166V.
  • the voltage value of the second DC capacitor dc2 indicated by the two-dot chain line (Vdc2_no control) decreases over time and changes from around 165V to around 164V.
  • the voltage value (with Vdc2_control) of the second DC capacitor dc2 indicated by the dashed line changes at a constant value.
  • the voltage value of the first DC capacitor dc1 (with Vdc1_control) indicated by the solid line also changes at a constant value.
  • processing explained as being performed by one device may be shared and performed by a plurality of devices.
  • processes described as being performed by different devices may be performed by one device.
  • a computer-readable recording medium can record a program that causes an information processing device or other machine or device (hereinafter referred to as a computer or the like) to implement any of the functions described above. By causing a computer or the like to read and execute the program of this recording medium, the function can be provided.
  • a computer-readable recording medium is a recording medium that stores information such as data and programs by electrical, magnetic, optical, mechanical, or chemical action and can be read by a computer, etc.
  • Examples of such recording media that can be removed from a computer or the like include memories such as flexible disks, magneto-optical disks, CD-ROMs, CD-R/Ws, DVDs, Blu-ray disks, DATs, 8 mm tapes, and flash memories.
  • a hard disk, a ROM, and the like as recording media fixed to a computer or the like.
  • a first capacitor circuit (12) having a first flying capacitor (fc1) connected to A fifth switch element (S11), a sixth switch element (S9), a seventh switch element (S10) and an eighth switch element (S12) connected in series, and a source terminal of the fifth switch element (S11)
  • One end is connected to the connection point with the drain terminal of the sixth switch element (S9), and the other end is the connection point between the source terminal of the seventh switch element (S10) and the drain terminal of the eighth switch element (S12).
  • a second capacitor circuit (13) having a second flying capacitor (fc2) connected to A ninth switch element (S5), a tenth switch element (S6), an eleventh switch element (S7) connected in series between the first input terminal (Tp1) and the second input terminal (Tp2), and A twelfth switch element (S8) is provided, the drain terminal of the ninth switch element (S5) is connected to the first input terminal (Tp1), and the source terminal of the twelfth switch element (S8) is connected to the second switch element (S8).
  • a first output circuit (14) connected to the input terminal (Tp2);
  • a 16th switch element (S16) is provided, the drain terminal of the 13th switch element (S13) is connected to the first input terminal (Tp1), and the source terminal of the 16th switch element (S16) is connected to the second input terminal (Tp1).
  • a second output circuit (15) connected to the input terminal (Tp2);
  • a connection point between the source terminal of the ninth switch element (S5) of the first output circuit (14) and the drain terminal of the tenth switch element (S6) is the first switch element of the first capacitor circuit (12).
  • the connection point between the drain terminal of the switch element (S1) and the source terminal of the eleventh switch element (S7) and the drain terminal of the twelfth switch element (S8) is the connection point of the first capacitor circuit (12).
  • connection point between the source terminal of the fourth switch element (S4) and the source terminal of the tenth switch element (S6) and the drain terminal of the eleventh switch element (S7) is the DC capacitor circuit (11 ) is connected to the connection point between the first DC capacitor (dc1) and the second DC capacitor (dc2),
  • the connection point between the source terminal of the thirteenth switch element (S13) of the second output circuit (15) and the drain terminal of the fourteenth switch element (S14) is the fifth switch element of the second capacitor circuit (13).
  • connection point between the source terminal of the fifteenth switch element (S15) and the drain terminal of the sixteenth switch element (S16) is connected to the drain terminal of the switch element (S11), and the connection point of the second capacitor circuit (13) is connected to the drain terminal of the switch element (S11).
  • the connection point between the source terminal of the eighth switch element (S12) and the source terminal of the fourteenth switch element (S14) and the drain terminal of the fifteenth switch element (S15) is the DC capacitor circuit (11 ) is connected to the connection point between the first DC capacitor (dc1) and the second DC capacitor (dc2),
  • the control unit (30) The first increasing or decreasing the period for charging and discharging the DC capacitor (dc1) and the second DC capacitor (dc2); the second output terminal (Tp4) connected to the connection point between the source terminal of the second switch element (S1) of the first capacitor circuit (12) and the drain terminal of the third switch (S2); AC power is output from the first output terminal (Tp3) connected to the connection point between the source terminal of the sixth switch element (S9) and the drain terminal of the seventh switch (S10) of the two-capacitor circuit (13).
  • a power converter (1) characterized by:

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Abstract

A power conversion device comprises: a DC capacitor circuit; a first capacitor circuit that has a first flying capacitor; and a second capacitor circuit that has a second flying capacitor. A control unit increases or reduces the periods pertaining to the charging and discharging of a first DC capacitor and a second DC capacitor on the basis: of a differential between a detected voltage value of the first flying capacitor and a voltage command value; and a differential between a detected voltage value of the second flying capacitor and a voltage command value. AC power is output from: a second output terminal which is connected to a connection point between the source terminal of a second switching element of the first capacitor circuit and the drain terminal of a third switch; and a first output terminal which is connected to a connection point between the source terminal of a sixth switching element of the second capacitor circuit and the drain terminal of a seventh switch.

Description

電力変換装置および制御方法Power conversion device and control method
 本発明は、フライングキャパシタを用いたマルチレベルの電力変換装置および制御方法に関する。 The present invention relates to a multi-level power converter and control method using flying capacitors.
 近年、太陽光発電装置や蓄電池、燃料電池等を構成に含み、商用の電力系統に連系して運用される分散型電源システムが普及してきている。分散型電源システムのパワーコンディショナ(以下、「電力変換装置」ともいう)は、太陽光発電装置や蓄電池、燃料電池等によって得られた直流電力を交流電力に変換し、負荷や連系する電力系統に供給する。このような電力変換装置として、例えば、特許文献1、2においては、フライングキャパシタを用いた複数レベルの電圧を出力するマルチレベルの電力変換装置が提案されている。 In recent years, distributed power supply systems that include solar power generation devices, storage batteries, fuel cells, etc., and are operated in conjunction with commercial power systems have become widespread. Power conditioners (hereinafter also referred to as “power converters”) in distributed power supply systems convert DC power obtained from photovoltaic power generation devices, storage batteries, fuel cells, etc. feed the system. As such a power converter, for example, Patent Literatures 1 and 2 propose a multi-level power converter that uses flying capacitors to output voltages at multiple levels.
特開2020-89240号公報Japanese Patent Application Laid-Open No. 2020-89240 特開2019-57969号公報JP 2019-57969 A
 ところで、フライングキャパシタを用いたマルチレベルの電力変換装置においては、回路を構成する各種の部品パラメータのばらつきが存在しない理想的な状態では、フライングキャパシタの電圧値は一定の電圧値にバランスされる。しかしながら、回路を構成する各種の部品パラメータがばらついた場合には、フライングキャパシタの電圧値がばらついてしまう虞があった。 By the way, in a multi-level power converter using flying capacitors, the voltage values of the flying capacitors are balanced at a constant voltage value in an ideal state where there are no variations in the parameters of the various components that make up the circuit. However, when the parameters of various parts that make up the circuit vary, there is a risk that the voltage values of the flying capacitors will vary.
 本発明は、上記のような事情に鑑みてなされたものであり、その目的は、フランイングキャパシタを用いたマルチレベルの電力変換装置において、部品パラメータのばらつきによる電圧変動を抑制し、安定性を向上させる技術を提供することにある。 The present invention has been made in view of the above circumstances, and its object is to suppress voltage fluctuations due to variations in component parameters and improve stability in a multi-level power converter using flying capacitors. It is to provide technology to improve.
 上記の課題を解決するための開示の技術の一形態は、
 制御部と、前記制御部からの制御指令に基づいて複数のスイッチ素子のドレイン端子とソース端子との間を導通または開放し、第1入力端および第2入力端に入力された直流電力を交流電力に変換して第1出力端子および第2出力端子から出力する電力変換部と、を有する電力変換装置であって、
 前記電力変換部は、
  前記第1入力端と前記第2入力端との間に直列に接続された第1直流キャパシタおよび第2直流キャパシタとを有し、前記第1直流キャパシタの一端が前記第1入力端と接続し、前記第2直流キャパシタの他端が前記第2入力端と接続される直流キャパシタ回路と、
  直列に接続された第1スイッチ素子、第2スイッチ素子、第3スイッチ素子および第4スイッチ素子と、前記第1スイッチ素子のソース端子と前記第2スイッチ素子のドレイン端子との接続点に一端が接続し、他端が前記3スイッチ素子のソース端子と前記第4スイッチ素子のドレイン端子との接続点とに接続された第1フライングキャパシタを有する第1キャパシタ回路と、
  直列に接続された第5スイッチ素子、第6スイッチ素子、第7スイッチ素子および第8スイッチ素子と、前記第5スイッチ素子のソース端子と前記第6スイッチ素子のドレイン端子との接続点に一端が接続し、他端が前記7スイッチ素子のソース端子と前記第8スイッチ素子のドレイン端子との接続点とに接続された第2フライングキャパシタを有する第2キャパシタ回路と、
  前記第1入力端と前記第2入力端との間に直列に接続された第9スイッチ素子、第10スイッチ素子、第11スイッチ素子および第12スイッチ素子を有し、前記第9スイッチ素子のドレイン端子が前記第1入力端に接続され、前記第12スイッチ素子のソース端子が前記第2入力端に接続される第1出力回路と、
  前記第1入力端と前記第2入力端との間に直列に接続された第13スイッチ素子、第14スイッチ素子、第15スイッチ素子および第16スイッチ素子を有し、前記第13スイッチ素子のドレイン端子が前記第1入力端に接続され、前記第16スイッチ素子のソース端子が前記第2入力端に接続される第2出力回路と、を備え、
 前記第1出力回路の前記第9スイッチ素子のソース端子と前記第10スイッチ素子のドレイン端子との接続点は、前記第1キャパシタ回路の前記第1スイッチ素子のドレイン端子と接続し、前記第11スイッチ素子のソース端子と前記第12スイッチ素子のドレイン端子との接続点は、前記第1キャパシタ回路の前記第4スイッチ素子のソース端子に接続され、前記第10スイッチ素子のソース端子と前記第11スイッチ素子のドレイン端子との接続点は、前記直流キャパシタ回路の第1直流キャパシタと第2直流キャパシタとの接続点に接続され、
 前記第2出力回路の前記第13スイッチ素子のソース端子と前記第14スイッチ素子のドレイン端子との接続点は、前記第2キャパシタ回路の前記第5スイッチ素子のドレイン端子と接続し、前記第15スイッチ素子のソース端子と前記第16スイッチ素子のドレイン端子との接続点は、前記第2キャパシタ回路の前記第8スイッチ素子のソース端子と接続し、前記第14スイッチ素子のソース端子と前記第15スイッチ素子のドレイン端子との接続点は、前記直流キャパシタ回路の第1直流キャパシタと第2直流キャパシタとの接続点に接続され、
 前記制御部は、
 前記第1フライングキャパシタの電圧検出値と電圧指令値との偏差量、および、前記第2フライングキャパシタの電圧検出値と電圧指令値との偏差量に基づいて、前記第1直流キャパシタおよび前記第2直流キャパシタの充放電に関する期間を増加または減少させ、
 第1キャパシタ回路の前記第2スイッチ素子のソース端子と前記第3スイッチのドレイン端子との接続点に接続された前記第2出力端子、および、第2キャパシタ回路の前記第6スイッチ素子のソース端子と前記第7スイッチのドレイン端子との接続点に接続された前記第1出力端子から交流電力を出力する、
 ことを特徴とする。
One form of the disclosed technology for solving the above problems is
a control unit, and based on a control command from the control unit, conductive or open between the drain terminal and the source terminal of the plurality of switch elements, and converts the DC power input to the first input terminal and the second input terminal to the AC power; A power conversion device having a power conversion unit that converts into power and outputs from a first output terminal and a second output terminal,
The power conversion unit is
a first DC capacitor and a second DC capacitor connected in series between the first input terminal and the second input terminal, wherein one end of the first DC capacitor is connected to the first input terminal; , a DC capacitor circuit in which the other end of the second DC capacitor is connected to the second input terminal;
one end at a connection point between a first switch element, a second switch element, a third switch element and a fourth switch element connected in series and a source terminal of the first switch element and a drain terminal of the second switch element; a first capacitor circuit having a first flying capacitor connected at the other end to a connection point between the source terminal of the three switch elements and the drain terminal of the fourth switch element;
one end at a connection point between a fifth switching element, a sixth switching element, a seventh switching element and an eighth switching element connected in series and a source terminal of the fifth switching element and a drain terminal of the sixth switching element; a second capacitor circuit having a second flying capacitor connected at the other end to a connection point between the source terminal of the seven switch elements and the drain terminal of the eighth switch element;
a ninth switch element, a tenth switch element, an eleventh switch element, and a twelfth switch element connected in series between the first input terminal and the second input terminal, the drain of the ninth switch element a first output circuit having a terminal connected to the first input terminal and a source terminal of the twelfth switch element connected to the second input terminal;
a thirteenth switch element, a fourteenth switch element, a fifteenth switch element, and a sixteenth switch element connected in series between the first input terminal and the second input terminal, the drain of the thirteenth switch element a second output circuit having a terminal connected to the first input terminal and a source terminal of the sixteenth switch element connected to the second input terminal;
A connection point between the source terminal of the ninth switch element of the first output circuit and the drain terminal of the tenth switch element is connected to the drain terminal of the first switch element of the first capacitor circuit, and the eleventh A connection point between the source terminal of the switch element and the drain terminal of the twelfth switch element is connected to the source terminal of the fourth switch element of the first capacitor circuit, and the source terminal of the tenth switch element and the eleventh switch element are connected to the source terminal of the fourth switch element. a connection point between the switch element and the drain terminal is connected to a connection point between the first DC capacitor and the second DC capacitor of the DC capacitor circuit;
A connection point between the source terminal of the thirteenth switching element and the drain terminal of the fourteenth switching element of the second output circuit is connected to the drain terminal of the fifth switching element of the second capacitor circuit, and the fifteenth A connection point between the source terminal of the switch element and the drain terminal of the sixteenth switch element is connected to the source terminal of the eighth switch element of the second capacitor circuit, and the source terminal of the fourteenth switch element and the fifteenth switch element are connected to the source terminal of the eighth switch element. a connection point between the switch element and the drain terminal is connected to a connection point between the first DC capacitor and the second DC capacitor of the DC capacitor circuit;
The control unit
Based on the amount of deviation between the detected voltage value of the first flying capacitor and the voltage command value and the amount of deviation between the detected voltage value of the second flying capacitor and the voltage command value, increasing or decreasing the period for charging and discharging the DC capacitor,
the second output terminal connected to a connection point between the source terminal of the second switch element of the first capacitor circuit and the drain terminal of the third switch; and the source terminal of the sixth switch element of the second capacitor circuit. and outputting AC power from the first output terminal connected to the connection point of the drain terminal of the seventh switch,
It is characterized by
 これにより、電力変換装置は、フライングキャパシタfc1の電圧(VFC1)に関する偏差量とフライングキャパシタfc2の電圧(VFC2)に関する偏差量とに応じて、第1直流キャパシタdc1および第2直流キャパシタdc2の充放電に関する期間を増加または減少させることができる。この結果、第1直流キャパシタdc1および第2直流キャパシタdc2の電圧が一定に制御できるため安定性が向上し、生成される交流電力の精度を高めることが可能になる。 As a result, the power converter charges and discharges the first DC capacitor dc1 and the second DC capacitor dc2 in accordance with the amount of deviation regarding the voltage (VFC1) of the flying capacitor fc1 and the amount of deviation regarding the voltage (VFC2) of the flying capacitor fc2. can be increased or decreased. As a result, since the voltages of the first DC capacitor dc1 and the second DC capacitor dc2 can be controlled to be constant, the stability is improved, and the accuracy of the generated AC power can be improved.
 また、開示の技術の一形態においては、前記制御部は、前記交流電力の電流極性が正側であり、前記第1フライングキャパシタの電圧検出値が第1電圧値を超える場合には、前記第1キャパシタ回路の前記第2スイッチ素子(S1)の閉期間を増加させ、前記第1スイッチ素子(S3)の閉期間を減少させるとともに、前記第1フライングキャパシタの電圧検出値が第1電圧値未満の場合には、前記第1キャパシタ回路の前記第2スイッチ素子(S1)の閉期間を減少させ、前記第1スイッチ素子(S3)の閉期間を増加させる、ようにしてもよい。これにより、交流電力の電流極性が正側のときに、フライングキャパシタfc1の電圧(VFC1)に応じて、第1フライングキャパシタ回路12のスイッチ素子S1およびS3のオン期間(デューティ)を増加または減少させ、フライングキャパシタfc1の電圧制御が可能になり、交流電力の精度を高めることができる。 Further, in one aspect of the disclosed technique, the control unit controls the current polarity of the AC power to be positive, and when the voltage detection value of the first flying capacitor exceeds a first voltage value, the first The closed period of the second switch element (S1) of the one-capacitor circuit is increased, the closed period of the first switch element (S3) is decreased, and the detected voltage value of the first flying capacitor is less than the first voltage value. In the case of (2), the closed period of the second switch element (S1) of the first capacitor circuit may be decreased and the closed period of the first switch element (S3) may be increased. As a result, when the current polarity of the AC power is on the positive side, the ON period (duty) of the switch elements S1 and S3 of the first flying capacitor circuit 12 is increased or decreased according to the voltage (VFC1) of the flying capacitor fc1. , the voltage control of the flying capacitor fc1 becomes possible, and the accuracy of the AC power can be improved.
 また、開示の技術の一形態においては、前記制御部は、前記交流電力の電流極性が正側であり、前記第2フライングキャパシタの電圧検出値が第1電圧値を超える場合には、前記第2キャパシタ回路の前記第6スイッチ素子(S9)の閉期間を減少させ、前記第5スイッチ素子(S11)の閉期間を増加させるとともに、前記第2フライングキャパシタの電圧検出値が第1電圧値未満の場合には、前記第2キャパシタ回路の前記第6スイッチ素子(S9)の閉期間を増加させ、前記第5スイッチ素子(S11)の閉期間を減少させる、ようにしてもよい。これにより、交流電力の電流極性が正側のときに、フライングキャパシタfc2の電圧(VFC2)に応じて、第2フライングキャパシタ回路13のスイッチ素子S9およびS11のオン期間(デューティ)を増加または減少させ、フライングキャパシタfc2の電圧制御が可能になり、交流電力の精度を高めることができる。 Further, in one aspect of the disclosed technique, the control unit controls the current polarity of the AC power to be positive, and when the voltage detection value of the second flying capacitor exceeds a first voltage value, the first The closed period of the sixth switch element (S9) of the two-capacitor circuit is decreased, the closed period of the fifth switch element (S11) is increased, and the detected voltage value of the second flying capacitor is less than the first voltage value. In the case of , the closed period of the sixth switch element (S9) of the second capacitor circuit may be increased and the closed period of the fifth switch element (S11) may be decreased. As a result, when the current polarity of the AC power is on the positive side, the ON period (duty) of the switch elements S9 and S11 of the second flying capacitor circuit 13 is increased or decreased according to the voltage (VFC2) of the flying capacitor fc2. , the voltage control of the flying capacitor fc2 becomes possible, and the accuracy of the AC power can be improved.
 また、開示の技術の一形態においては、前記制御部は、前記交流電力の電流極性が負側であり、前記第1フライングキャパシタの電圧検出値が第1電圧値を超える場合には、前記第1キャパシタ回路の前記第2スイッチ素子(S1)の閉期間を減少させ、前記第1スイッチ素子(S3)の閉期間を増加させるとともに、前記第1フライングキャパシタの電圧検出値が第1電圧値未満の場合には、前記第1キャパシタ回路の前記第2スイッチ素子(S1)の閉期間を増加させ、前記第1スイッチ素子(S3)の閉期間を減少させる、ようにしてもよい。これにより、交流電力の電流極性が負側であっても、フライングキャパシタfc1の電圧(VFC1)に応じて、第1フライングキャパシタ回路12のスイッチ素子S1およびS3のオン期間(デューティ)を増加または減少させ、フライングキャパシタfc1の電圧制御が可能になり、交流電力の精度を高めることができる。 Further, in one aspect of the disclosed technique, the control unit controls the current polarity of the AC power to be negative, and when the voltage detection value of the first flying capacitor exceeds a first voltage value, the first The closed period of the second switch element (S1) of the one-capacitor circuit is decreased, the closed period of the first switch element (S3) is increased, and the detected voltage value of the first flying capacitor is less than the first voltage value. In the case of (2), the closed period of the second switch element (S1) of the first capacitor circuit may be increased and the closed period of the first switch element (S3) may be decreased. As a result, even if the current polarity of the AC power is negative, the ON period (duty) of the switch elements S1 and S3 of the first flying capacitor circuit 12 is increased or decreased according to the voltage (VFC1) of the flying capacitor fc1. , the voltage of the flying capacitor fc1 can be controlled, and the accuracy of AC power can be improved.
 また、開示の技術の一形態においては、前記制御部は、前記交流電力の電流極性が負側であり、前記第2フライングキャパシタの電圧検出値が第1電圧値を超える場合には、前記第2キャパシタ回路の前記第6スイッチ素子(S9)の閉期間を増加させ、前記第5スイッチ素子(S11)の閉期間を減少させるとともに、前記第2フライングキャパシタの電圧検出値が第1電圧値未満の場合には、前記第2キャパシタ回路の前記第6スイッチ素子(S9)の閉期間を減少させ、前記第5スイッチ素子(S11)の閉期間を増加させる、ようにしてもよい。これにより、交流電力の電流極性が負側であっても、フライングキャパシタfc2の電圧(VFC2)に応じて、第2フライングキャパシタ回路13のスイッチ素子S9およびS11のオン期間(デューティ)を増加または減少させ、フライングキャパシタfc2の電圧制御が可能になり、交流電力の精度を高めることができる。 Further, in one aspect of the disclosed technology, the control unit controls the current polarity of the AC power to be negative, and when the voltage detection value of the second flying capacitor exceeds a first voltage value, the first The closed period of the sixth switch element (S9) of the two-capacitor circuit is increased, the closed period of the fifth switch element (S11) is decreased, and the detected voltage value of the second flying capacitor is less than the first voltage value. In the case of , the closed period of the sixth switch element (S9) of the second capacitor circuit may be decreased and the closed period of the fifth switch element (S11) may be increased. As a result, even if the current polarity of the AC power is negative, the ON period (duty) of the switch elements S9 and S11 of the second flying capacitor circuit 13 is increased or decreased according to the voltage (VFC2) of the flying capacitor fc2. , the voltage of the flying capacitor fc2 can be controlled, and the accuracy of AC power can be improved.
 また、開示の技術の一形態においては、前記制御部は、前記交流電力の電圧極性が正側であり、前記電流極性が正側のときには、前記第2フライングキャパシタの電圧検出値と電圧指令値との偏差量が前記第1フライングキャパシタの電圧検出値と電圧指令値との偏差量より大きいことを条件として、前記第1直流キャパシタの電圧検出値が第2電圧値を超える場合には、前記第1キャパシタ回路の前記第1スイッチ素子(S3)の閉期間を増加させ、前記第1直流キャパシタの電圧検出値が第2電圧値未満の場合には、前記第1キャパシタ回路の前記第1スイッチ素子(S3)の閉期間を減少させるようにしてもよい。これにより、交流電力の電圧極性が正側であり、電流極性が正側のときには、フライングキャパシタfc1の電圧(VFC1)に関する偏差量とフライングキャパシタfc2の電圧(VFC2)に関する偏差量とに応じて、第1直流キャパシタdc1の電圧(VDC1)を連動させて制御するためのスイッチ素子(S3)が選定できる。そして、第1直流キャパシタdc1の電圧値(VDC1)に応じて、第1フライングキャパシタ回路12のスイッチ素子S3のオン期間(デューティD3)を増加または減少させて電圧値(VDC1)が制御できる。 Further, in one aspect of the disclosed technology, the control unit controls the voltage detection value of the second flying capacitor and the voltage command value when the voltage polarity of the AC power is positive and the current polarity is positive. is greater than the deviation between the voltage detection value of the first flying capacitor and the voltage command value, when the voltage detection value of the first DC capacitor exceeds the second voltage value, the increasing the closed period of the first switch element (S3) of the first capacitor circuit, and when the voltage detection value of the first DC capacitor is less than the second voltage value, the first switch of the first capacitor circuit; The closing period of the element (S3) may be decreased. As a result, when the voltage polarity of the AC power is on the positive side and the current polarity is on the positive side, the following A switch element (S3) for interlocking and controlling the voltage (VDC1) of the first DC capacitor dc1 can be selected. The voltage value (VDC1) can be controlled by increasing or decreasing the ON period (duty D3) of the switch element S3 of the first flying capacitor circuit 12 according to the voltage value (VDC1) of the first DC capacitor dc1.
 また、開示の技術の一形態においては、前記制御部は、前記交流電力の電圧極性が正側であり、前記電流極性が正側のときには、前記第2フライングキャパシタの電圧検出値と電圧指令値との偏差量が前記第1フライングキャパシタの電圧検出値と電圧指令値との偏差量より小さいことを条件として、前記第1直流キャパシタの電圧検出値が第2電圧値を超える場合には、前記第2キャパシタ回路の前記第5スイッチ素子(S11)の閉期間を増加させ、前記第1直流キャパシタの電圧検出値が第2電圧値未満の場合には、前記第2キャパシタ回路の前記第5スイッチ素子(S11)の閉期間を減少させる、ようにしてもよい。これにより、交流電力の電圧極性が正側であり、電流極性が正側のときには、フライングキャパシタfc1の電圧(VFC1)に関する偏差量とフライングキャパシタfc2の電圧(VFC2)に関する偏差量とに応じて、第1直流キャパシタdc1の電圧(VDC1)を連動させて制御するためのスイッチ素子(S11)が選定できる。そして、第1直流キャパシタdc1の電圧値(VDC1)に応じて、第2フライングキャパシタ回路13のスイッチ素子S11のオン期間(デューティD11)を増加または減少させて電圧値(VDC1)が制御できる。 Further, in one aspect of the disclosed technique, the control unit controls the voltage detection value of the second flying capacitor and the voltage command value when the voltage polarity of the AC power is positive and the current polarity is positive. If the voltage detection value of the first DC capacitor exceeds the second voltage value on the condition that the deviation amount is smaller than the deviation amount between the voltage detection value of the first flying capacitor and the voltage command value, the increasing the closed period of the fifth switch element (S11) of the second capacitor circuit, and when the voltage detection value of the first DC capacitor is less than the second voltage value, the fifth switch of the second capacitor circuit; The closing period of the element (S11) may be decreased. As a result, when the voltage polarity of the AC power is on the positive side and the current polarity is on the positive side, the following A switch element (S11) for interlocking and controlling the voltage (VDC1) of the first DC capacitor dc1 can be selected. The voltage value (VDC1) can be controlled by increasing or decreasing the ON period (duty D11) of the switch element S11 of the second flying capacitor circuit 13 according to the voltage value (VDC1) of the first DC capacitor dc1.
 また、開示の技術の一形態においては、前記制御部は、前記交流電力の電圧極性が負側であり、前記電流極性が負側のときには、前記第2フライングキャパシタの電圧検出値と電圧指令値との偏差量が前記第1フライングキャパシタの電圧検出値と電圧指令値との偏差量より大きいことを条件として、前記第1直流キャパシタの電圧検出値が第2電圧値を超える場合には、前記第1キャパシタ回路の前記第1スイッチ素子(S3)の閉期間を増加させ、前記第1直流キャパシタの電圧検出値が第2電圧値未満の場合には、前記第1キャパシタ回路の前記第1スイッチ素子(S3)の閉期間を減少させる、ようにしてもよい。これにより、交流電力の電圧極性が負側であり、電流極性が負側のときにおいても、フライングキャパシタfc1の電圧(VFC1)に関する偏差量とフライングキャパシタfc2の電圧(VFC2)に関する偏差量とに応じて、第1直流キャパシタdc1の電圧(VDC1)を連動させて制御するためのスイッチ素子(S3)が選定できる。そして、第1直流キャパシタdc1の電圧値(VDC1)に応じて、第1フライングキャパシタ回路12のスイッチ素子S3のオン期間(デューティD3)を増加または減少させて電圧値(VDC1)が制御できる。 Further, in one aspect of the disclosed technique, the control unit controls the voltage detection value and the voltage command value of the second flying capacitor when the voltage polarity of the AC power is on the negative side and the current polarity is on the negative side. is greater than the deviation between the voltage detection value of the first flying capacitor and the voltage command value, when the voltage detection value of the first DC capacitor exceeds the second voltage value, the increasing the closed period of the first switch element (S3) of the first capacitor circuit, and when the voltage detection value of the first DC capacitor is less than the second voltage value, the first switch of the first capacitor circuit; The closing period of element (S3) may be decreased. As a result, even when the voltage polarity of the AC power is negative and the current polarity is negative, the deviation amount of the voltage (VFC1) of the flying capacitor fc1 and the deviation amount of the voltage (VFC2) of the flying capacitor fc2 Therefore, a switch element (S3) for interlocking and controlling the voltage (VDC1) of the first DC capacitor dc1 can be selected. The voltage value (VDC1) can be controlled by increasing or decreasing the ON period (duty D3) of the switch element S3 of the first flying capacitor circuit 12 according to the voltage value (VDC1) of the first DC capacitor dc1.
 また、開示の技術の一形態においては、前記制御部は、前記交流電力の電圧極性が負側であり、前記電流極性が負側のときには、前記第2フライングキャパシタの電圧検出値と電圧指令値との偏差量が前記第1フライングキャパシタの電圧検出値と電圧指令値との偏差量より小さいことを条件として、前記第1直流キャパシタの電圧検出値が第2電圧値を超える場合には、前記第2キャパシタ回路の前記第5スイッチ素子(S11)の閉期間を増加させ、前記第1直流キャパシタの電圧検出値が第2電圧値未満の場合には、前記第2キャパシタ回路の前記第5スイッチ素子(S11)の閉期間を減少させる、ようにしてもよい。これにより、交流電力の電圧極性が負側であり、電流極性が負側のときにおいても、フライングキャパシタfc1の電圧(VFC1)に関する偏差量とフライングキャパシタfc2の電圧(VFC2)に関する偏差量とに応じて、第1直流キャパシタdc1の電圧(VDC1)を連動させて制御するためのスイッチ素子(S11)が選定できる。そして、第1直流キャパシタdc1の電圧値(VDC1)に応じて、第2フライングキャパシタ回路13のスイッチ素子S11のオン期間(デューティD11)を増加または減少させて電圧値(VDC1)が制御できる。 Further, in one aspect of the disclosed technique, the control unit controls the voltage detection value and the voltage command value of the second flying capacitor when the voltage polarity of the AC power is on the negative side and the current polarity is on the negative side. is smaller than the deviation between the voltage detection value of the first flying capacitor and the voltage command value, and when the voltage detection value of the first DC capacitor exceeds the second voltage value, the increasing the closed period of the fifth switch element (S11) of the second capacitor circuit, and when the voltage detection value of the first DC capacitor is less than the second voltage value, the fifth switch of the second capacitor circuit; The closing period of the element (S11) may be decreased. As a result, even when the voltage polarity of the AC power is negative and the current polarity is negative, the deviation amount of the voltage (VFC1) of the flying capacitor fc1 and the deviation amount of the voltage (VFC2) of the flying capacitor fc2 Thus, a switch element (S11) for interlocking and controlling the voltage (VDC1) of the first DC capacitor dc1 can be selected. The voltage value (VDC1) can be controlled by increasing or decreasing the ON period (duty D11) of the switch element S11 of the second flying capacitor circuit 13 according to the voltage value (VDC1) of the first DC capacitor dc1.
 また、開示の技術の一形態においては、前記制御部は、前記交流電力の電圧極性が負側であり、前記電流極性が正側のときには、前記第2フライングキャパシタの電圧検出値と電圧指令値との偏差量が前記第1フライングキャパシタの電圧検出値と電圧指令値との偏差量より大きいことを条件として、前記第1直流キャパシタの電圧検出値が第2電圧値を超える場合には、前記第1キャパシタ回路の前記第1スイッチ素子(S3)の閉期間を減少させ、前記第1直流キャパシタの電圧検出値が第2電圧値未満の場合には、前記第1キャパシタ回路の前記第1スイッチ素子(S3)の閉期間を増加させる、ようにしてもよい。これにより、交流電力の電圧極性が負側であり、電流極性が正側のときには、フライングキャパシタfc1の電圧(VFC1)に関する偏差量とフライングキャパシタfc2の電圧(VFC2)に関する偏差量とに応じて、第1直流キャパシタdc1の電圧(VDC1)を連動させて制御するためのスイッチ素子(S3)が選定できる。そして、第1直流キャパシタdc1の電圧値(VDC1)に応じて、第1フライングキャパシタ回路12のスイッチ素子S3のオン期間(デューティD3)を増加または減少させて電圧値(VDC1)が制御できる。 Further, in one aspect of the disclosed technique, the control unit controls the voltage detection value of the second flying capacitor and the voltage command value when the voltage polarity of the AC power is negative and the current polarity is positive. is greater than the deviation between the voltage detection value of the first flying capacitor and the voltage command value, when the voltage detection value of the first DC capacitor exceeds the second voltage value, the reducing the closed period of the first switch element (S3) of the first capacitor circuit, and when the voltage detection value of the first DC capacitor is less than the second voltage value, the first switch of the first capacitor circuit The closed period of element (S3) may be increased. As a result, when the voltage polarity of the AC power is negative and the current polarity is positive, according to the amount of deviation regarding the voltage (VFC1) of the flying capacitor fc1 and the amount of deviation regarding the voltage (VFC2) of the flying capacitor fc2, A switch element (S3) for interlocking and controlling the voltage (VDC1) of the first DC capacitor dc1 can be selected. The voltage value (VDC1) can be controlled by increasing or decreasing the ON period (duty D3) of the switch element S3 of the first flying capacitor circuit 12 according to the voltage value (VDC1) of the first DC capacitor dc1.
 また、開示の技術の一形態においては、前記制御部は、前記交流電力の電圧極性が負側であり、前記電流極性が正側のときには、前記第2フライングキャパシタの電圧検出値と電圧指令値との偏差量が前記第1フライングキャパシタの電圧検出値と電圧指令値との偏差量より小さいことを条件として、前記第1直流キャパシタの電圧検出値が第2電圧値を超える場合には、前記第2キャパシタ回路の前記第5スイッチ素子(S11)の閉期間を減少させ、前記第1直流キャパシタの電圧検出値が第2電圧値未満の場合には、前記第2キャパシタ回路の前記第5スイッチ素子(S11)の閉期間を増加させる、ようにしてもよい。これにより、交流電力の電圧極性が負側であり、電流極性が正側のときには、フライングキャパシタfc1の電圧(VFC1)に関する偏差量とフライングキャパシタfc2の電圧(VFC2)に関する偏差量とに応じて、第1直流キャパシタdc1の電圧(VDC1)を連動させて制御するためのスイッチ素子(S11)が選定できる。そして、第1直流キャパシタdc1の電圧値(VDC1)に応じて、第2フライングキャパシタ回路13のスイッチ素子S11のオン期間(デューティD11)を増加または減少させて電圧値(VDC1)が制御できる。 Further, in one aspect of the disclosed technique, the control unit controls the voltage detection value of the second flying capacitor and the voltage command value when the voltage polarity of the AC power is negative and the current polarity is positive. is smaller than the deviation between the voltage detection value of the first flying capacitor and the voltage command value, and when the voltage detection value of the first DC capacitor exceeds the second voltage value, the reducing the closed period of the fifth switch element (S11) of the second capacitor circuit, and when the voltage detection value of the first DC capacitor is less than the second voltage value, the fifth switch of the second capacitor circuit The closed period of the element (S11) may be increased. As a result, when the voltage polarity of the AC power is negative and the current polarity is positive, according to the amount of deviation regarding the voltage (VFC1) of the flying capacitor fc1 and the amount of deviation regarding the voltage (VFC2) of the flying capacitor fc2, A switch element (S11) for interlocking and controlling the voltage (VDC1) of the first DC capacitor dc1 can be selected. The voltage value (VDC1) can be controlled by increasing or decreasing the ON period (duty D11) of the switch element S11 of the second flying capacitor circuit 13 according to the voltage value (VDC1) of the first DC capacitor dc1.
 また、開示の技術の一形態においては、前記制御部は、前記交流電力の電圧極性が正側であり、前記電流極性が負側のときには、前記第2フライングキャパシタの電圧検出値と電圧指令値との偏差量が前記第1フライングキャパシタの電圧検出値と電圧指令値との偏差量より大きいことを条件として、前記第1直流キャパシタの電圧検出値が第2電圧値を超える場合には、前記第1キャパシタ回路の前記第1スイッチ素子(S3)の閉期間を減少させ、前記第1直流キャパシタの電圧検出値が第2電圧値未満の場合には、前記第1キャパシタ回路の前記第1スイッチ素子(S3)の閉期間を増加させる、ようにしてもよい。これにより、交流電力の電圧極性が正側であり、電流極性が負側のときには、フライングキャパシタfc1の電圧(VFC1)に関する偏差量とフライングキャパシタfc2の電圧(VFC2)に関する偏差量とに応じて、第1直流キャパシタdc1の電圧(VDC1)を連動させて制御するためのスイッチ素子(S3)が選定できる。そして、第1直流キャパシタdc1の電圧値(VDC1)に応じて、第1フライングキャパシタ回路12のスイッチ素子S3のオン期間(デューティD3)を増加または減少させて電圧値(VDC1)が制御できる。 Further, in one aspect of the disclosed technique, the control unit controls the voltage detection value of the second flying capacitor and the voltage command value when the voltage polarity of the AC power is positive and the current polarity is negative. is greater than the deviation between the voltage detection value of the first flying capacitor and the voltage command value, when the voltage detection value of the first DC capacitor exceeds the second voltage value, the reducing the closed period of the first switch element (S3) of the first capacitor circuit, and when the voltage detection value of the first DC capacitor is less than the second voltage value, the first switch of the first capacitor circuit The closed period of element (S3) may be increased. Accordingly, when the voltage polarity of the AC power is on the positive side and the current polarity is on the negative side, the following A switch element (S3) for interlocking and controlling the voltage (VDC1) of the first DC capacitor dc1 can be selected. The voltage value (VDC1) can be controlled by increasing or decreasing the ON period (duty D3) of the switch element S3 of the first flying capacitor circuit 12 according to the voltage value (VDC1) of the first DC capacitor dc1.
 また、開示の技術の一形態においては、前記制御部は、前記交流電力の電圧極性が正側であり、前記電流極性が負側のときには、前記第2フライングキャパシタの電圧検出値と電圧指令値との偏差量が前記第1フライングキャパシタの電圧検出値と電圧指令値との偏差量より小さいことを条件として、前記第1直流キャパシタの電圧検出値が第2電圧値を超える場合には、前記第2キャパシタ回路の前記第5スイッチ素子(S11)の閉期間を減少させ、前記第1直流キャパシタの電圧検出値が第2電圧値未満の場合には、前記第2キャパシタ回路の前記第5スイッチ素子(S11)の閉期間を増加させる、ようにしてもよい。これにより、交流電力の電圧極性が正側であり、電流極性が負側のときにも、フライングキャパシタfc1の電圧(VFC1)に関する偏差量とフライングキャパシタfc2の電圧(VFC2)に関する偏差量とに応じて、第1直流キャパシタdc1の電圧(VDC1)を連動させて制御するためのスイッチ素子(S11)が選定できる。そして、第1直流キャパシタdc1の電圧値(VDC1)に応じて、第2フライングキャパシタ回路13のスイッチ素子S11のオン期間(デューティD11)を増加または減少させて電圧値(VDC1)が制御できる。 Further, in one aspect of the disclosed technique, the control unit controls the voltage detection value of the second flying capacitor and the voltage command value when the voltage polarity of the AC power is positive and the current polarity is negative. is smaller than the deviation between the voltage detection value of the first flying capacitor and the voltage command value, and when the voltage detection value of the first DC capacitor exceeds the second voltage value, the reducing the closed period of the fifth switch element (S11) of the second capacitor circuit, and when the voltage detection value of the first DC capacitor is less than the second voltage value, the fifth switch of the second capacitor circuit The closed period of the element (S11) may be increased. As a result, even when the voltage polarity of the AC power is positive and the current polarity is negative, the deviation amount of the voltage (VFC1) of the flying capacitor fc1 and the deviation amount of the voltage (VFC2) of the flying capacitor fc2 Thus, a switch element (S11) for interlocking and controlling the voltage (VDC1) of the first DC capacitor dc1 can be selected. The voltage value (VDC1) can be controlled by increasing or decreasing the ON period (duty D11) of the switch element S11 of the second flying capacitor circuit 13 according to the voltage value (VDC1) of the first DC capacitor dc1.
 また、開示の技術の他の一形態は、
 制御部と、前記制御部からの制御指令に基づいて複数のスイッチ素子のドレイン端子とソース端子との間を導通または開放し、第1入力端および第2入力端に入力された直流電力を交流電力に変換して第1出力端子および第2出力端子から出力する電力変換部と、を有する電力変換装置の制御方法であって、
 前記電力変換部は、
  前記第1入力端と前記第2入力端との間に直列に接続された第1直流キャパシタおよび第2直流キャパシタとを有し、前記第1直流キャパシタの一端が前記第1入力端と接続し、前記第2直流キャパシタの他端が前記第2入力端と接続される直流キャパシタ回路と、
  直列に接続された第1スイッチ素子、第2スイッチ素子、第3スイッチ素子および第4スイッチ素子と、前記第1スイッチ素子のソース端子と前記第2スイッチ素子のドレイン端子との接続点に一端が接続し、他端が前記3スイッチ素子のソース端子と前記第4スイッチ素子のドレイン端子との接続点とに接続された第1フライングキャパシタを有する第1キャパシタ回路と、
  直列に接続された第5スイッチ素子、第6スイッチ素子、第7スイッチ素子および第8スイッチ素子と、前記第5スイッチ素子のソース端子と前記第6スイッチ素子のドレイン端子との接続点に一端が接続し、他端が前記7スイッチ素子のソース端子と前記第8スイッチ素子のドレイン端子との接続点とに接続された第2フライングキャパシタを有する第2キャパシタ回路と、
  前記第1入力端と前記第2入力端との間に直列に接続された第9スイッチ素子、第10スイッチ素子、第11スイッチ素子および第12スイッチ素子を有し、前記第9スイッチ素子のドレイン端子が前記第1入力端に接続され、前記第12スイッチ素子のソース端子が前記第2入力端に接続される第1出力回路と、
  前記第1入力端と前記第2入力端との間に直列に接続された第13スイッチ素子、第14スイッチ素子、第15スイッチ素子および第16スイッチ素子を有し、前記第13スイッチ素子のドレイン端子が前記第1入力端に接続され、前記第16スイッチ素子のソース端子が前記第2入力端に接続される第2出力回路と、を備え、
 前記第1出力回路の前記第9スイッチ素子のソース端子と前記第10スイッチ素子のドレイン端子との接続点は、前記第1キャパシタ回路の前記第1スイッチ素子のドレイン端子と接続し、前記第11スイッチ素子のソース端子と前記第12スイッチ素子のドレイン端子との接続点は、前記第1キャパシタ回路の前記第4スイッチ素子のソース端子に接続され、前記第10スイッチ素子のソース端子と前記第11スイッチ素子のドレイン端子との接続点は、前記直流キャパシタ回路の第1直流キャパシタと第2直流キャパシタとの接続点に接続され、
 前記第2出力回路の前記第13スイッチ素子のソース端子と前記第14スイッチ素子のドレイン端子との接続点は、前記第2キャパシタ回路の前記第5スイッチ素子のドレイン端子と接続し、前記第15スイッチ素子のソース端子と前記第16スイッチ素子のドレイン端子との接続点は、前記第2キャパシタ回路の前記第8スイッチ素子のソース端子と接続し、前記第14スイッチ素子のソース端子と前記第15スイッチ素子のドレイン端子との接続点は、前記直流キャパシタ回路の第1直流キャパシタと第2直流キャパシタとの接続点に接続され、
 前記制御部は、
 前記第1フライングキャパシタの電圧検出値と電圧指令値との偏差、および、前記第2フライングキャパシタの電圧検出値と電圧指令値との偏差に基づいて、前記第1直流キャパシタおよび前記第2直流キャパシタの充放電に関する期間を増加または減少させ、
 第1キャパシタ回路の前記第2スイッチ素子のソース端子と前記第3スイッチのドレイン端子との接続点に接続された前記第2出力端子、および、第2キャパシタ回路の前記第6スイッチ素子のソース端子と前記第7スイッチのドレイン端子との接続点に接続された前記第1出力端子から交流電力を出力する、
 ことを実行する。
In addition, another aspect of the disclosed technique is
a control unit, and based on a control command from the control unit, conductive or open between the drain terminal and the source terminal of the plurality of switch elements, and converts the DC power input to the first input terminal and the second input terminal to the AC power; A control method for a power conversion device having a power conversion unit that converts into power and outputs from a first output terminal and a second output terminal,
The power conversion unit is
a first DC capacitor and a second DC capacitor connected in series between the first input terminal and the second input terminal, wherein one end of the first DC capacitor is connected to the first input terminal; , a DC capacitor circuit in which the other end of the second DC capacitor is connected to the second input terminal;
one end at a connection point between a first switch element, a second switch element, a third switch element and a fourth switch element connected in series and a source terminal of the first switch element and a drain terminal of the second switch element; a first capacitor circuit having a first flying capacitor connected at the other end to a connection point between the source terminal of the three switch elements and the drain terminal of the fourth switch element;
one end at a connection point between a fifth switching element, a sixth switching element, a seventh switching element and an eighth switching element connected in series and a source terminal of the fifth switching element and a drain terminal of the sixth switching element; a second capacitor circuit having a second flying capacitor connected at the other end to a connection point between the source terminal of the seven switch elements and the drain terminal of the eighth switch element;
a ninth switch element, a tenth switch element, an eleventh switch element, and a twelfth switch element connected in series between the first input terminal and the second input terminal, the drain of the ninth switch element a first output circuit having a terminal connected to the first input terminal and a source terminal of the twelfth switch element connected to the second input terminal;
a thirteenth switch element, a fourteenth switch element, a fifteenth switch element, and a sixteenth switch element connected in series between the first input terminal and the second input terminal, the drain of the thirteenth switch element a second output circuit having a terminal connected to the first input terminal and a source terminal of the sixteenth switch element connected to the second input terminal;
A connection point between the source terminal of the ninth switch element of the first output circuit and the drain terminal of the tenth switch element is connected to the drain terminal of the first switch element of the first capacitor circuit, and the eleventh A connection point between the source terminal of the switch element and the drain terminal of the twelfth switch element is connected to the source terminal of the fourth switch element of the first capacitor circuit, and the source terminal of the tenth switch element and the eleventh switch element are connected to the source terminal of the fourth switch element. a connection point between the switch element and the drain terminal is connected to a connection point between the first DC capacitor and the second DC capacitor of the DC capacitor circuit;
A connection point between the source terminal of the thirteenth switching element and the drain terminal of the fourteenth switching element of the second output circuit is connected to the drain terminal of the fifth switching element of the second capacitor circuit, and the fifteenth A connection point between the source terminal of the switch element and the drain terminal of the sixteenth switch element is connected to the source terminal of the eighth switch element of the second capacitor circuit, and the source terminal of the fourteenth switch element and the fifteenth switch element are connected to the source terminal of the eighth switch element. a connection point between the switch element and the drain terminal is connected to a connection point between the first DC capacitor and the second DC capacitor of the DC capacitor circuit;
The control unit
Based on the deviation between the voltage detection value and the voltage command value of the first flying capacitor and the deviation between the voltage detection value and the voltage command value of the second flying capacitor, the first DC capacitor and the second DC capacitor increase or decrease the period of charge and discharge of
the second output terminal connected to a connection point between the source terminal of the second switch element of the first capacitor circuit and the drain terminal of the third switch; and the source terminal of the sixth switch element of the second capacitor circuit. and outputting AC power from the first output terminal connected to the connection point of the drain terminal of the seventh switch,
carry out
 このような形態であっても、電力変換装置は、フライングキャパシタfc1の電圧(VFC1)に関する偏差量とフライングキャパシタfc2の電圧(VFC2)に関する偏差量とに応じて、第1直流キャパシタdc1および第2直流キャパシタdc2の充放電に関する期間を増加または減少させることができる。この結果、第1直流キャパシタdc1および第2直流キャパシタdc2の電圧が一定に制御できるため安定性が向上し、生成される交流電力の精度を高めることが可能になる。 Even in such a form, the power conversion device is configured such that the first DC capacitor dc1 and the second DC capacitor dc1 and the second DC capacitor dc1 and the second DC capacitor dc1 The period for charging and discharging DC capacitor dc2 can be increased or decreased. As a result, since the voltages of the first DC capacitor dc1 and the second DC capacitor dc2 can be controlled to be constant, the stability is improved, and the accuracy of the generated AC power can be improved.
 本発明によれば、フランイングキャパシタを用いたマルチレベルの電力変換装置において、部品パラメータのばらつきによる電圧変動を抑制し、安定性を向上させる技術が提供できる。 According to the present invention, it is possible to provide a technique for suppressing voltage fluctuations due to variations in component parameters and improving stability in a multi-level power converter using flying capacitors.
本発明の実施例1に係る電力変換装置の概略構成を示すブロック図である。BRIEF DESCRIPTION OF THE DRAWINGS It is a block diagram which shows schematic structure of the power converter device which concerns on Example 1 of this invention. 本発明の実施例1に係る5レベルの電位により生成される交流電力を説明する図である。FIG. 4 is a diagram illustrating AC power generated by five levels of potentials according to Example 1 of the present invention; 本発明の実施例1に係るフライングキャパシタにおける充放電モードを説明する図である。It is a figure explaining the charging/discharging mode in the flying capacitor based on Example 1 of this invention. 本発明の実施例1に係る電力変換部の各キャパシタにおける充放電状態を説明する図である。FIG. 4 is a diagram illustrating charge/discharge states in each capacitor of the power conversion unit according to Example 1 of the present invention; 本発明の実施例1におけるスイッチング時間のずれの影響を説明する図である。FIG. 4 is a diagram illustrating the influence of switching time lag in Example 1 of the present invention; 本発明の実施例1に係るフライングキャパシタfc1の電圧制御を説明する図である。It is a figure explaining the voltage control of flying capacitor fc1 which concerns on Example 1 of this invention. 本発明の実施例1に係るフライングキャパシタfc2の電圧制御を説明する図である。It is a figure explaining the voltage control of flying capacitor fc2 which concerns on Example 1 of this invention. 本発明の実施例1に係る第1直流キャパシタdc1および第2直流キャパシタdc2の電圧制御を説明する図である。It is a figure explaining the voltage control of 1st DC capacitor dc1 and 2nd DC capacitor dc2 which concern on Example 1 of this invention. 本発明の実施例1に係る第1直流キャパシタdc1および第2直流キャパシタdc2の電圧制御を説明する図である。It is a figure explaining the voltage control of 1st DC capacitor dc1 and 2nd DC capacitor dc2 which concern on Example 1 of this invention. 本発明の実施例1に係る制御部のハードウェア構成の一例を示す図である。It is a figure which shows an example of the hardware constitutions of the control part which concerns on Example 1 of this invention. 本発明の実施例1における電圧制御処理の一例を示すフローチャートである。4 is a flow chart showing an example of voltage control processing in Embodiment 1 of the present invention; 本発明の実施例1における電圧制御処理の一例を示すフローチャートである。4 is a flow chart showing an example of voltage control processing in Embodiment 1 of the present invention; 本発明の実施例1における電圧制御処理の一例を示すフローチャートである。4 is a flow chart showing an example of voltage control processing in Embodiment 1 of the present invention; 本発明の実施例1における電圧制御処理の一例を示すフローチャートである。5 is a flow chart showing an example of voltage control processing in Embodiment 1 of the present invention; 本発明の実施例1に係る制御処理のシミュレーション結果の一例を示す図である。It is a figure which shows an example of the simulation result of the control process which concerns on Example 1 of this invention.
〔適用例〕
 以下、本発明の適用例について、図面を参照しつつ説明する。
 図1は、本発明の適用例に係る電力変換装置1の概略構成を示すブロック図である。図1には、直流電源V1から供給された直流電力を複数レベル(本実施例では5レベル)の電圧を用いて正弦波の電圧指令値に追従する交流電力に変換する電力変換部10を備える電力変換装置が例示される。電力変換部10には、直流キャパシタ回路11と、第1フライングキャパシタ回路12と、第2フライングキャパシタ回路13と、第1出力回路14と、第2出力回路15とが含まれる。
[Example of application]
Hereinafter, application examples of the present invention will be described with reference to the drawings.
FIG. 1 is a block diagram showing a schematic configuration of a power converter 1 according to an application example of the present invention. FIG. 1 includes a power conversion unit 10 that converts DC power supplied from a DC power supply V1 into AC power that follows a sinusoidal voltage command value using voltages of multiple levels (five levels in this embodiment). A power converter is exemplified. The power converter 10 includes a DC capacitor circuit 11 , a first flying capacitor circuit 12 , a second flying capacitor circuit 13 , a first output circuit 14 and a second output circuit 15 .
 本適用例に係る電力変換部10は、第1フライングキャパシタ回路12と、第2フライングキャパシタ回路13と、第1出力回路14と、第2出力回路15とによる、アクティブ中性点クランプ形(Advanced Neutral-Point-Clamped、以下「ANPC方式」ともいう)のインバータ回路で構成される。ANPC方式のインバータ回路を採用する電力変換部10においては、第1直流キャパシタdc1および第2直流キャパシタdc2を「2E」の電圧、フライングキャパシタfc1およびフライングキャパシタfc2を「E」の電圧に制御することで、5レベルの電位(4E、2E、0、-2E、-4E)が生成される。生成された5レベルの電位は、第1フライングキャパシタ回路12、第2フライングキャパシタ回路13、第1出力回路14、第2出力回路15を構成する各スイッチ素子の開閉(オン/オフ)を選択制御することで出力端子Tp3、Tp4に出力される。 The power conversion unit 10 according to this application example includes a first flying capacitor circuit 12, a second flying capacitor circuit 13, a first output circuit 14, and a second output circuit 15. Neutral-Point-Clamped (hereinafter also referred to as "ANPC system") inverter circuit. In the power conversion unit 10 that employs the inverter circuit of the ANPC method, the first DC capacitor dc1 and the second DC capacitor dc2 are controlled to the voltage "2E", and the flying capacitor fc1 and the flying capacitor fc2 are controlled to the voltage "E". , five levels of potentials (4E, 2E, 0, -2E, -4E) are generated. The generated 5-level potential selectively controls opening/closing (on/off) of each switch element constituting the first flying capacitor circuit 12, the second flying capacitor circuit 13, the first output circuit 14, and the second output circuit 15. By doing so, they are output to the output terminals Tp3 and Tp4.
 直流キャパシタ回路11は、入力端子Tp1と入力端子Tp2との間に直列に接続された第1直流キャパシタdc1および第2直流キャパシタdc2とを備える。第1直流キャパシタdc1の一端は入力端子Tp1と接続し、第2直流キャパシタdc2の、第1直流キャパシタdc1との接続点の反対側の端子が入力端子Tp2に接続される。 The DC capacitor circuit 11 includes a first DC capacitor dc1 and a second DC capacitor dc2 connected in series between the input terminal Tp1 and the input terminal Tp2. One end of the first DC capacitor dc1 is connected to the input terminal Tp1, and the terminal of the second DC capacitor dc2 opposite to the connection point with the first DC capacitor dc1 is connected to the input terminal Tp2.
 第1フライングキャパシタ回路12は、スイッチ素子S3、スイッチ素子S1、スイッチ素子S2、スイッチ素子S4の順に直列に接続された4つのスイッチ素子を有する。また、スイッチ素子S3のソース端子とスイッチ素子S1のドレイン端子とが接続される接続点に一端が接続され、他端がスイッチ素子S2のソース端子とスイッチ素子S4のドレイン端子とが接続される接続点に接続されるフライングキャパシタfc1を備える。スイッチ素子S1のソース端子とスイッチ素子S2のドレイン端子とが接続される接続点は、電力変換部10の出力端子Tp4に接続される。 The first flying capacitor circuit 12 has four switch elements connected in series in the order of switch element S3, switch element S1, switch element S2, and switch element S4. One end is connected to the connection point where the source terminal of the switch element S3 and the drain terminal of the switch element S1 are connected, and the other end is connected to the source terminal of the switch element S2 and the drain terminal of the switch element S4. It has a flying capacitor fc1 connected to a point. A connection point where the source terminal of the switch element S1 and the drain terminal of the switch element S2 are connected is connected to the output terminal Tp4 of the power conversion section 10 .
 第2フライングキャパシタ回路13は、スイッチ素子S11、スイッチ素子S9、スイッチ素子S10、スイッチ素子S12の順に直列に接続された4つのスイッチ素子を有する。また、一端がスイッチ素子S11のソース端子とスイッチ素子S9のドレイン端子とが接続される接続点に接続され、他端がスイッチ素子S10のソース端子とスイッチ素子S12のドレイン端子とが接続される接続点に接続されるフライングキャパシタfc2を備える。スイッチ素子S9のソース端子とスイッチ素子S10のドレイン端子とが接続される接続点は、電力変換部10の出力端子Tp3に接続される。 The second flying capacitor circuit 13 has four switch elements connected in series in the order of switch element S11, switch element S9, switch element S10, and switch element S12. One end is connected to the connection point where the source terminal of the switch element S11 and the drain terminal of the switch element S9 are connected, and the other end is connected to the source terminal of the switch element S10 and the drain terminal of the switch element S12. It has a flying capacitor fc2 connected to the point. A connection point where the source terminal of the switch element S9 and the drain terminal of the switch element S10 are connected is connected to the output terminal Tp3 of the power conversion section 10 .
 第1出力回路14は、スイッチ素子S5、スイッチ素子S6、スイッチ素子S7、スイッチ素子S8が順に直列に接続された4つのスイッチ素子を有し、スイッチ素子S5のドレイン端子は入力端子Tp1と接続し、スイッチ素子S8のソース端子は入力端子Tp2と接続される。第2出力回路15は、スイッチ素子S13、スイッチ素子S14、スイッチ素子S15、スイッチ素子S16が順に直列に接続された4つのスイッチ素子を有し、スイッチ素子S13のドレイン端子は入力端子Tp1と接続し、スイッチ素子S16のソース端子は入力端子Tp2と接続される。 The first output circuit 14 has four switch elements in which a switch element S5, a switch element S6, a switch element S7, and a switch element S8 are connected in series in order, and the drain terminal of the switch element S5 is connected to the input terminal Tp1. , the source terminal of the switch element S8 is connected to the input terminal Tp2. The second output circuit 15 has four switch elements in which a switch element S13, a switch element S14, a switch element S15, and a switch element S16 are connected in series in order, and the drain terminal of the switch element S13 is connected to the input terminal Tp1. , the source terminal of the switch element S16 is connected to the input terminal Tp2.
 第1出力回路14の、スイッチ素子S6のソース端子とスイッチ素子S7のドレイン端子とが接続される接続点は、直流キャパシタ回路11の、第1直流キャパシタdc1と第2直流キャパシタdc2との接続点に接続される。第2出力回路15の、スイッチ素子S14のソース端子とスイッチ素子S15のドレイン端子とが接続される接続点は、直流キャパシタ回路11の、第1直流キャパシタdc1と第2直流キャパシタdc2との接続点に接続される。
 そして、第1フライングキャパシタ回路12のスイッチ素子S3のドレイン端子は、第1出力回路14の、スイッチ素子S5のソース端子とスイッチ素子S6のドレイン端子とが接続される接続点に接続される。第1フライングキャパシタ回路12のスイッチ素子S4のソース端子は、第1出力回路14の、スイッチ素子S7のソース端子とスイッチ素子S8のドレイン端子とが接続される接続点に接続される。また、第2フライングキャパシタ回路13のスイッチ素子S11のドレイン端子は、第2出力回路15の、スイッチ素子S13のソース端子とスイッチ素子S14のドレイン端子とが接続される接続点に接続される。第2フライングキャパシタ回路13のスイッチ素子S10のソース端子は、第2出力回路15の、スイッチ素子S15のソース端子とスイッチ素子S16のドレイン端子とが接続される接続点に接続される。
The connection point between the source terminal of the switch element S6 and the drain terminal of the switch element S7 in the first output circuit 14 is the connection point between the first DC capacitor dc1 and the second DC capacitor dc2 in the DC capacitor circuit 11. connected to The connection point of the second output circuit 15 where the source terminal of the switch element S14 and the drain terminal of the switch element S15 are connected is the connection point of the first DC capacitor dc1 and the second DC capacitor dc2 of the DC capacitor circuit 11. connected to
The drain terminal of the switch element S3 of the first flying capacitor circuit 12 is connected to the connection point of the first output circuit 14 where the source terminal of the switch element S5 and the drain terminal of the switch element S6 are connected. The source terminal of the switch element S4 of the first flying capacitor circuit 12 is connected to the connection point of the first output circuit 14 where the source terminal of the switch element S7 and the drain terminal of the switch element S8 are connected. The drain terminal of the switch element S11 of the second flying capacitor circuit 13 is connected to the connection point of the second output circuit 15 where the source terminal of the switch element S13 and the drain terminal of the switch element S14 are connected. The source terminal of the switching element S10 of the second flying capacitor circuit 13 is connected to the connection point of the second output circuit 15 where the source terminal of the switching element S15 and the drain terminal of the switching element S16 are connected.
 図2から図4に示すように、図3(a)から(d)のスイッチングパターンに係る時間が同じであれば、フライングキャパシタfc1およびfc2、第1直流キャパシタdc1および第2直流キャパシタdc2の電圧は一定になる。例えば、フライングキャパシタfc1およびfc2の電圧は「E」、第1直流キャパシタdc1および第2直流キャパシタdc2の電圧は「2E」となる。しかしながら、第1フライングキャパシタ回路12、第2フライングキャパシタ回路13、第1出力回路14、第2出力回路15のそれぞれを構成する部品パラメータのばらつきが存在する。例えば、各回路を構成するスイッチ素子の浮遊容量や抵抗がばらつくため、スイッチング時間にずれが生じることになる。スイッチング時間にずれが生じる場合には、電力変換部10から出力される電圧が変動する虞があった。 As shown in FIGS. 2 to 4, if the times associated with the switching patterns of FIGS. becomes constant. For example, the voltages of the flying capacitors fc1 and fc2 are "E", and the voltages of the first DC capacitor dc1 and the second DC capacitor dc2 are "2E". However, there are variations in the component parameters that configure the first flying capacitor circuit 12, the second flying capacitor circuit 13, the first output circuit 14, and the second output circuit 15, respectively. For example, the stray capacitances and resistances of the switch elements that make up each circuit vary, resulting in deviations in switching time. If there is a shift in switching time, the voltage output from the power converter 10 may fluctuate.
 図6から図14に示すように、本適用例に係る電力変換装置1は、フライングキャパシタfc1およびfc2、第1直流キャパシタdc1および第2直流キャパシタdc2の充放電に係る各スイッチ素子のスイッチングを制御することで、部品パラメータのばらつきによる電圧変動を抑制する。具体的には、電力変換装置1の制御部30は、第1フライングキャパシタ回路12のスイッチ素子S1およびS3のオン期間(デューティ)を増加または減少させることでフライングキャパシタfc1の電圧制御を行う。同様にして、制御部30は、第2フライングキャパシタ回路13のスイッチ素子S9およびS11のデューティを増加または減少させることでフライングキャパシタfc2の電圧制御を行う。そして、本適用例に係る電力変換装置1の制御部30は、フライングキャパシタfc1およびfc2の電圧に基づいて、スイッチ素子S3またはスイッチ素子S11のデューティを増加または減少させることで、第1直流キャパシタdc1および第2直流キャパシタdc2の電圧制御を行う。本適用例に係る電力変換装置1においては、上記スイッチ素子のスイッチング制御により、フライングキャパシタfc1およびfc2、第1直流キャパシタdc1および第2直流キャパシタdc2の電圧が一定に制御できるため安定性が向上し、生成される交流電力の精度を高めることが可能になる。 As shown in FIGS. 6 to 14, the power conversion device 1 according to this application example controls switching of switching elements associated with charging and discharging of the flying capacitors fc1 and fc2, the first DC capacitor dc1 and the second DC capacitor dc2. By doing so, voltage fluctuations due to variations in component parameters are suppressed. Specifically, the control unit 30 of the power conversion device 1 increases or decreases the ON period (duty) of the switch elements S1 and S3 of the first flying capacitor circuit 12 to control the voltage of the flying capacitor fc1. Similarly, the control unit 30 increases or decreases the duty of the switch elements S9 and S11 of the second flying capacitor circuit 13 to control the voltage of the flying capacitor fc2. Then, the control unit 30 of the power conversion device 1 according to this application example increases or decreases the duty of the switch element S3 or the switch element S11 based on the voltages of the flying capacitors fc1 and fc2, so that the first DC capacitor dc1 and voltage control of the second DC capacitor dc2. In the power converter 1 according to this application example, the voltages of the flying capacitors fc1 and fc2, the first DC capacitor dc1 and the second DC capacitor dc2 can be controlled to be constant by switching control of the switch elements, thereby improving stability. , it is possible to increase the accuracy of the generated AC power.
〔実施例1〕
 以下では、本発明の具体的な実施の形態について、図面を用いてより詳細に説明する。
[Example 1]
Specific embodiments of the present invention will be described in more detail below with reference to the drawings.
<装置構成>
 図1は、本発明の実施例に係る電力変換装置1の概略構成を示すブロック図である。電力変換装置1は、太陽光発電装置や蓄電池、燃料電池等を構成に含み、商用の電力系統に連系して運用される分散型電源システムのパワーコンディショナを構成する。分散型電源システムの太陽光発電装置や蓄電池、燃料電池等の分散型電源は、それぞれに各分散型電源の出力を制御可能なDC/DCコンバータに接続され、直流電源V1を構成する。電力変換装置1は、直流電源V1から供給される直流電力を交流電力に変換し、変換後の交流電力を負荷50や連系する電力系統に出力する。以下では、交流電力の出力対象を負荷50として説明する。電力変換装置1は、入力端子Tp1およびTp2を介して当該電力変換装置とDC/DCコンバータとの間を接続する直流バスに接続される。図1においては、入力端子Tp1は直流バスの正側バスに接続され、入力端子Tp2は直流バスの負側バスに接続されている。
<Device configuration>
FIG. 1 is a block diagram showing a schematic configuration of a power converter 1 according to an embodiment of the invention. The power conversion device 1 includes a photovoltaic power generation device, a storage battery, a fuel cell, etc. in its configuration, and constitutes a power conditioner of a distributed power supply system that is operated in conjunction with a commercial power system. Distributed power sources such as photovoltaic power generation devices, storage batteries, and fuel cells of the distributed power source system are connected to DC/DC converters capable of controlling the output of each distributed power source to form a DC power source V1. The power conversion device 1 converts the DC power supplied from the DC power supply V1 into AC power, and outputs the converted AC power to the load 50 and an interconnected power system. In the following description, it is assumed that the load 50 is the output target of AC power. The power conversion device 1 is connected to a DC bus connecting between the power conversion device and the DC/DC converter via input terminals Tp1 and Tp2. In FIG. 1, the input terminal Tp1 is connected to the positive bus of the DC bus, and the input terminal Tp2 is connected to the negative bus of the DC bus.
 電力変換装置1は、電力変換部10と、フィルタ部20と、制御部30とを構成に含む。電力変換部10は、直流電源V1から供給された直流電力を複数レベル(本実施例では5レベル)の電圧を用いて正弦波の電圧指令値に追従する交流電力に変換する。電力変換部10によって変換された交流電力は、出力端子Tp3およびTp4を通じてフィルタ部20に出力される。電力変換部10は、直流キャパシタ回路11と、第1フライングキャパシタ回路12と、第2フライングキャパシタ回路13と、第1出力回路14と、第2出力回路15と、を含む。本実施例においては、「直流キャパシタ回路11」は「直流キャパシタ回路」の一例に相当し、「第1フライングキャパシタ回路12」は「第1キャパシタ回路」、「第2フライングキャパシタ回路13」は「第2キャパシタ回路」の一例に相当する。 The power conversion device 1 includes a power conversion section 10, a filter section 20, and a control section 30 in its configuration. The power conversion unit 10 converts the DC power supplied from the DC power supply V1 into AC power following a sinusoidal voltage command value using voltages of multiple levels (five levels in this embodiment). The AC power converted by power conversion section 10 is output to filter section 20 through output terminals Tp3 and Tp4. The power converter 10 includes a DC capacitor circuit 11 , a first flying capacitor circuit 12 , a second flying capacitor circuit 13 , a first output circuit 14 and a second output circuit 15 . In this embodiment, the "DC capacitor circuit 11" corresponds to an example of the "DC capacitor circuit", the "first flying capacitor circuit 12" is the "first capacitor circuit", and the "second flying capacitor circuit 13" is the " It corresponds to an example of "second capacitor circuit".
 直流キャパシタ回路11は、入力端子Tp1と入力端子Tp2との間に直列に接続された第1直流キャパシタdc1および第2直流キャパシタdc2とを備える。第1直流キャパシタdc1の一端は入力端子Tp1と接続し、第2直流キャパシタdc2の、第1直流キャパシタdc1との接続点の反対側の端子が入力端子Tp2に接続される。第1直流キャパシタdc1および第2直流キャパシタdc2により、入力端子Tp1とTp2との間に入力される直流電力の電圧(4E)は等分に分圧され、図1に示すようにそれぞれのキャパシタ電圧が「2E」となる。また、第1直流キャパシタdc1および第2直流キャパシタdc2は、電力変換回路10内で生じるサージ電圧を抑制するスナバ機能を有する。本実施例においては、「第1直流キャパシタdc1」は「第1直流キャパシタ」の一例に相当し、「第2直流キャパシタdc2」は「第2直流キャパシタ」の一例に相当する。 The DC capacitor circuit 11 includes a first DC capacitor dc1 and a second DC capacitor dc2 connected in series between the input terminal Tp1 and the input terminal Tp2. One end of the first DC capacitor dc1 is connected to the input terminal Tp1, and the terminal of the second DC capacitor dc2 opposite to the connection point with the first DC capacitor dc1 is connected to the input terminal Tp2. The voltage (4E) of the DC power input between the input terminals Tp1 and Tp2 is equally divided by the first DC capacitor dc1 and the second DC capacitor dc2. becomes "2E". Also, the first DC capacitor dc1 and the second DC capacitor dc2 have a snubber function that suppresses a surge voltage generated within the power conversion circuit 10 . In this embodiment, the "first DC capacitor dc1" corresponds to an example of the "first DC capacitor", and the "second DC capacitor dc2" corresponds to an example of the "second DC capacitor".
 第1フライングキャパシタ回路12は、スイッチ素子S1と、スイッチ素子S2と、スイッチ素子S3と、スイッチ素子S4と、キャパシタfc1(以下、「フライングキャパシタfc1」ともいう)とを構成に含む。本実施例においては、「スイッチ素子S1」は「第2スイッチ素子」の一例に相当し、「スイッチ素子S2」は「第3スイッチ素子」の一例に相当し、「スイッチ素子S3」は「第1スイッチ素子」の一例に相当し、「スイッチ素子S4」は「第4スイッチ素子」の一例に相当する。また、実施例の、「キャパシタfc1」は「第1フライングキャパシタ」の一例に相当する。 The first flying capacitor circuit 12 includes a switch element S1, a switch element S2, a switch element S3, a switch element S4, and a capacitor fc1 (hereinafter also referred to as "flying capacitor fc1"). In this embodiment, the "switch element S1" corresponds to an example of a "second switch element", the "switch element S2" corresponds to an example of a "third switch element", and the "switch element S3" corresponds to a "third switch element". 1 switch element", and "switch element S4" corresponds to an example of "fourth switch element". Also, the "capacitor fc1" in the embodiment corresponds to an example of the "first flying capacitor".
 第1フライングキャパシタ回路12を構成するスイッチ素子S1からS4は、例えば、NチャンネルのMOSFET(Metal-Oxide-Semiconductor Field-Effect Transistor)であり、ドレイン端子-ソース端子間に接続されたダイオードを有する。ダイオードのアノードはNチャンネルのMOSFETのソース端子に接続され、カソードはドレイン端子に接続される。第1フライングキャパシタ回路12を構成するスイッチ素子S1からS4は、図1に示すように、スイッチ素子S3、スイッチ素子S1、スイッチ素子S2、スイッチ素子S4の順に直列に接続される。そして、フライングキャパシタfc1の一端は、スイッチ素子S3のソース端子とスイッチ素子S1のドレイン端子とが接続される接続点に接続され、他端は、スイッチ素子S2のソース端子とスイッチ素子S4のドレイン端子とが接続される接続点に接続される。スイッチ素子S1のソース端子とスイッチ素子S2のドレイン端子とが接続される接続点は、電力変換部10の出力端子Tp4に接続される。本実施例の、「出力端子Tp4」は「第2出力端子」の一例に相当する。 The switch elements S1 to S4 that constitute the first flying capacitor circuit 12 are, for example, N-channel MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) and have diodes connected between the drain terminal and the source terminal. The anode of the diode is connected to the source terminal of the N-channel MOSFET, and the cathode is connected to the drain terminal. The switch elements S1 to S4 constituting the first flying capacitor circuit 12 are connected in series in the order of switch element S3, switch element S1, switch element S2, and switch element S4, as shown in FIG. One end of the flying capacitor fc1 is connected to a connection point where the source terminal of the switching element S3 and the drain terminal of the switching element S1 are connected, and the other end is connected to the source terminal of the switching element S2 and the drain terminal of the switching element S4. is connected to the connection point where and are connected. A connection point where the source terminal of the switch element S1 and the drain terminal of the switch element S2 are connected is connected to the output terminal Tp4 of the power conversion section 10 . The "output terminal Tp4" in this embodiment corresponds to an example of the "second output terminal".
 第2フライングキャパシタ回路13は、スイッチ素子S9と、スイッチ素子S10と、スイッチ素子S11と、スイッチ素子S12と、キャパシタfc2(以下、「フライングキャパシタfc2」ともいう)とを構成に含む。本実施例においては、「スイッチ素子S9」は「第6スイッチ素子」の一例に相当し、「スイッチ素子S10」は「第7スイッチ素子」の一例に相当し、「スイッチ素子S11」は「第5スイッチ素子」の一例に相当し、「スイッチ素子S12」は「第8スイッチ素子」の一例に相当する。また、本実施例の、「キャパシタfc2」は「第2フライングキャパシタ」の一例に相当する。 The configuration of the second flying capacitor circuit 13 includes a switch element S9, a switch element S10, a switch element S11, a switch element S12, and a capacitor fc2 (hereinafter also referred to as "flying capacitor fc2"). In this embodiment, the "switch element S9" corresponds to an example of the "sixth switch element", the "switch element S10" corresponds to an example of the "seventh switch element", and the "switch element S11" corresponds to the "sixth switch element". 5 switch elements", and the "switch element S12" corresponds to an example of the "eighth switch element". Also, the "capacitor fc2" in this embodiment corresponds to an example of the "second flying capacitor".
 第2フライングキャパシタ回路13を構成するスイッチ素子S9からS12は、第1フライングキャパシタ回路12を構成するスイッチ素子と同様である。すなわち、ドレイン端子-ソース端子間にダイオードが接続されたNチャンネルのMOSFETで構成される。第2フライングキャパシタ回路13を構成するスイッチ素子S9からS12は、図1に示すように、スイッチ素子S11、スイッチ素子S9、スイッチ素子S10、スイッチ素子S12の順に直列に接続される。そして、フライングキャパシタfc2の一端は、スイッチ素子S11のソース端子とスイッチ素子S9のドレイン端子とが接続される接続点に接続され、他端は、スイッチ素子S10のソース端子とスイッチ素子S12のドレイン端子とが接続される接続点に接続される。スイッチ素子S9のソース端子とスイッチ素子S10のドレイン端子とが接続される接続点は、電力変換部10の出力端子Tp3に接続される。本実施例の、「出力端子Tp3」は「第1出力端子」の一例に相当する。 The switch elements S9 to S12 forming the second flying capacitor circuit 13 are the same as the switch elements forming the first flying capacitor circuit 12 . That is, it is composed of an N-channel MOSFET in which a diode is connected between the drain terminal and the source terminal. The switch elements S9 to S12 constituting the second flying capacitor circuit 13 are connected in series in the order of switch element S11, switch element S9, switch element S10, and switch element S12, as shown in FIG. One end of the flying capacitor fc2 is connected to a connection point where the source terminal of the switching element S11 and the drain terminal of the switching element S9 are connected, and the other end is connected to the source terminal of the switching element S10 and the drain terminal of the switching element S12. is connected to the connection point where and are connected. A connection point where the source terminal of the switch element S9 and the drain terminal of the switch element S10 are connected is connected to the output terminal Tp3 of the power conversion section 10 . The "output terminal Tp3" in this embodiment corresponds to an example of the "first output terminal".
 第1出力回路14は、スイッチ素子S5と、スイッチ素子S6と、スイッチ素子S7と、スイッチ素子S8とを構成に含む。各スイッチ素子S5からS8は、第1フライングキャパシタ回路12を構成するスイッチ素子と同様であり、NチャンネルのMOSFETのソース端子にアノードが接続し、ドレイン端子にカソードが接続されたダイオードを有する。スイッチ素子S5からスイッチ素子S8は、図1に示すように、スイッチ素子S5、スイッチ素子S6、スイッチ素子S7、スイッチ素子S8の順に直列に接続され、スイッチ素子S5のドレイン端子は入力端子Tp1と接続し、スイッチ素子S8のソース端子は入力端子Tp2と接続される。本実施例においては、「スイッチ素子S5」は「第9スイッチ素子」の一例に相当し、「スイッチ素子S6」は「第10スイッチ素子」の一例に相当し、「スイッチ素子S7」は「第11スイッチ素子」の一例に相当し、「スイッチ素子S8」は「第12スイッチ素子」の一例に相当する。 The configuration of the first output circuit 14 includes a switch element S5, a switch element S6, a switch element S7, and a switch element S8. Each of the switch elements S5 to S8 is similar to the switch elements forming the first flying capacitor circuit 12, and has a diode whose anode is connected to the source terminal of an N-channel MOSFET and whose cathode is connected to the drain terminal. As shown in FIG. 1, the switch elements S5 to S8 are connected in series in the order of switch element S5, switch element S6, switch element S7, and switch element S8, and the drain terminal of switch element S5 is connected to input terminal Tp1. The source terminal of the switch element S8 is connected to the input terminal Tp2. In this embodiment, the "switch element S5" corresponds to an example of the "ninth switch element", the "switch element S6" corresponds to an example of the "tenth switch element", and the "switch element S7" corresponds to the "first switch element". 11 switch element", and "switch element S8" corresponds to an example of "12th switch element".
 第2出力回路15は、スイッチ素子S13と、スイッチ素子S14と、スイッチ素子S15と、スイッチ素子S16とを構成に含む。各スイッチ素子S13からS16は、第1フライングキャパシタ回路12を構成するスイッチ素子と同様であり、NチャンネルのMOSFETのソース端子にアノードが接続し、ドレイン端子にカソードが接続されたダイオードを有する。スイッチ素子S13からスイッチ素子S16は、図1に示すように、スイッチ素子S13、スイッチ素子S14、スイッチ素子S15、スイッチ素子S16の順に直列に接続され、スイッチ素子S13のドレイン端子は入力端子Tp1と接続し、スイッチ素子S16のソース端子は入力端子Tp2と接続される。本実施例においては、「スイッチ素子S13」は「第13スイッチ素子」の一例に相当し、「スイッチ素子S14」は「第14スイッチ素子」の一例に相当し、「スイッチ素子S15」は「第15スイッチ素子」の一例に相当し、「スイッチ素子S16」は「第16スイッチ素子」の一例に相当する。 The configuration of the second output circuit 15 includes a switch element S13, a switch element S14, a switch element S15, and a switch element S16. Each of the switch elements S13 to S16 is similar to the switch elements forming the first flying capacitor circuit 12, and has a diode whose anode is connected to the source terminal of an N-channel MOSFET and whose cathode is connected to the drain terminal. As shown in FIG. 1, the switch elements S13 to S16 are connected in series in the order of the switch element S13, the switch element S14, the switch element S15, and the switch element S16, and the drain terminal of the switch element S13 is connected to the input terminal Tp1. The source terminal of the switch element S16 is connected to the input terminal Tp2. In this embodiment, the "switch element S13" corresponds to an example of the "thirteenth switch element", the "switch element S14" corresponds to one example of the "fourteenth switch element", and the "switch element S15" corresponds to the "thirteenth switch element". 15 switch elements", and the "switch element S16" corresponds to an example of the "sixteenth switch element".
 第1出力回路14の、スイッチ素子S6のソース端子とスイッチ素子S7のドレイン端子とが接続される接続点は、直流キャパシタ回路11の、第1直流キャパシタdc1と第2直流キャパシタdc2との接続点に接続される。同様にして、第2出力回路15の、スイッチ素子S14のソース端子とスイッチ素子S15のドレイン端子とが接続される接続点は、直流キャパシタ回路11の、第1直流キャパシタdc1と第2直流キャパシタdc2との接続点に接続される。
 第1フライングキャパシタ回路12のスイッチ素子S3のドレイン端子は、第1出力回路14の、スイッチ素子S5のソース端子とスイッチ素子S6のドレイン端子とが接続される接続点に接続される。第1フライングキャパシタ回路12のスイッチ素子S4のソース端子は、第1出力回路14の、スイッチ素子S7のソース端子とスイッチ素子S8のドレイン端子とが接続される接続点に接続される。
 同様にして、第2フライングキャパシタ回路13のスイッチ素子S11のドレイン端子は、第2出力回路15の、スイッチ素子S13のソース端子とスイッチ素子S14のドレイン端子とが接続される接続点に接続される。第2フライングキャパシタ回路13のスイッチ素子S12のソース端子は、第2出力回路15の、スイッチ素子S15のソース端子とスイッチ素子S16のドレイン端子とが接続される接続点に接続される。
The connection point between the source terminal of the switch element S6 and the drain terminal of the switch element S7 in the first output circuit 14 is the connection point between the first DC capacitor dc1 and the second DC capacitor dc2 in the DC capacitor circuit 11. connected to Similarly, the connection point where the source terminal of the switch element S14 and the drain terminal of the switch element S15 of the second output circuit 15 are connected is the first DC capacitor dc1 and the second DC capacitor dc2 of the DC capacitor circuit 11. connected to the connection point with
The drain terminal of the switch element S3 of the first flying capacitor circuit 12 is connected to the connection point of the first output circuit 14 where the source terminal of the switch element S5 and the drain terminal of the switch element S6 are connected. The source terminal of the switch element S4 of the first flying capacitor circuit 12 is connected to the connection point of the first output circuit 14 where the source terminal of the switch element S7 and the drain terminal of the switch element S8 are connected.
Similarly, the drain terminal of the switch element S11 of the second flying capacitor circuit 13 is connected to the connection point of the second output circuit 15 where the source terminal of the switch element S13 and the drain terminal of the switch element S14 are connected. . The source terminal of the switching element S12 of the second flying capacitor circuit 13 is connected to the connection point of the second output circuit 15 where the source terminal of the switching element S15 and the drain terminal of the switching element S16 are connected.
 このように、本実施例に係る電力変換部10は、第1フライングキャパシタ回路12と、第2フライングキャパシタ回路13と、第1出力回路14と、第2出力回路15とによる、アクティブ中性点クランプ形(Advanced Neutral-Point-Clamped、以下「ANPC方式」ともいう)のインバータ回路で構成される。ANPC方式のインバータ回路を採用する本実施例の電力変換部10においては、第1直流キャパシタdc1および第2直流キャパシタdc2を「2E」の電圧、フライングキャパシタfc1およびフライングキャパシタfc2を「E」の電圧に制御することで、5レベルの電位(4E、2E、0、-2E、-4E)が生成される。生成された5レベルの電位は、第1フライングキャパシタ回路12、第2フライングキャパシタ回路13、第1出力回路14、第2出力回路15を構成する各スイッチ素子の開閉を選択制御することで出力端子Tp3、Tp4に出力される。なお、本実施例においては、各スイッチ素子の“開”状態は、ドレイン端子とソース端子との間が開放される“オフ”状態を表し、“閉”状態は、ドレイン端子とソース端子との間が導通される“オン”状態を表す。 As described above, the power conversion unit 10 according to the present embodiment has the active neutral point by the first flying capacitor circuit 12, the second flying capacitor circuit 13, the first output circuit 14, and the second output circuit 15. It is composed of a clamp type (Advanced Neutral-Point-Clamped, hereinafter also referred to as "ANPC system") inverter circuit. In the power conversion unit 10 of this embodiment that employs the ANPC inverter circuit, the first DC capacitor dc1 and the second DC capacitor dc2 are set at a voltage of "2E", and the flying capacitor fc1 and the flying capacitor fc2 are set at a voltage of "E". 5 levels of potentials (4E, 2E, 0, -2E, -4E) are generated by controlling the potentials to . The generated 5-level potential is output to the output terminal by selectively controlling the opening/closing of each switch element constituting the first flying capacitor circuit 12, the second flying capacitor circuit 13, the first output circuit 14, and the second output circuit 15. Output to Tp3 and Tp4. In this embodiment, the "open" state of each switch element represents the "off" state in which the drain terminal and the source terminal are opened, and the "closed" state represents the connection between the drain terminal and the source terminal. represents an "on" state in which the current between the
 また、本実施例に係る電力変換部10は、第1フライングキャパシタ回路12のスイッチ素子S1のソース端子とスイッチ素子S2のドレイン端子とが接続される接続点と、第2フライングキャパシタ回路13のスイッチ素子S9のソース端子とスイッチ素子S10のドレイン端子とが接続される接続点とを通じて、生成された5レベルの電位による交流電力を負荷50や連系する電力系統に出力できる。したがって、本実施例に係る電力変換装置1の出力側に接続される負荷50等の機器や、直流バスを通じて接続された直流電源V1を構成する機器との間の、基準電位(GND)を通じて流れ込むコモンモードの抑制が可能になる。つまり、フライングキャパシタfc1の電圧値、フライングキャパシタfc2の電圧値、第1直流キャパシタdc1の電圧値、第2直流キャパシタdc2の電圧値が所望の値から外れるほど、コモンモードノイズは悪化し、所望の値に近付くほど、コモンモードノイズは低減されることになる。 Further, the power conversion unit 10 according to the present embodiment includes a connection point where the source terminal of the switch element S1 of the first flying capacitor circuit 12 and the drain terminal of the switch element S2 are connected, and the switch of the second flying capacitor circuit 13. Through the connection point where the source terminal of the element S9 and the drain terminal of the switch element S10 are connected, the AC power with the generated 5-level potential can be output to the load 50 and the connected power system. Therefore, it flows through the reference potential (GND) between devices such as the load 50 connected to the output side of the power conversion device 1 according to the present embodiment and devices constituting the DC power supply V1 connected through the DC bus. Suppression of common mode becomes possible. That is, the more the voltage value of the flying capacitor fc1, the voltage value of the flying capacitor fc2, the voltage value of the first DC capacitor dc1, and the voltage value of the second DC capacitor dc2 deviate from the desired values, the worse the common mode noise becomes. The closer to the value, the more common mode noise will be reduced.
 フィルタ部20は、インダクタ20aと、インダクタ20bと、キャパシタ20cとを構成に含む。インダクタ20aの一端は出力端子Tp4と接続し、他端はキャパシタ20cの一端と接続される。また、インダクタ20bの一端は出力端子Tp3と接続し、他端はキャパシタ20cの他端と接続される。フィルタ部20は、第1フライングキャパシタ回路12および第2フライングキャパシタ回路13から出力される交流電力の高調波成分を低減させて、当該交流電力を電力変換装置1と接続される負荷50や連系される電力系統に出力する。フィルタ部20においては、電力変換部10で生成されて負荷50側に出力される交流電力の出力電流値io、出力電圧値vo(キャパシタ20cの印加電圧)がそれぞれ電流センサおよび電圧センサを通じて計測される。 The filter section 20 includes an inductor 20a, an inductor 20b, and a capacitor 20c. One end of the inductor 20a is connected to the output terminal Tp4, and the other end is connected to one end of the capacitor 20c. One end of the inductor 20b is connected to the output terminal Tp3, and the other end is connected to the other end of the capacitor 20c. The filter unit 20 reduces harmonic components of the AC power output from the first flying capacitor circuit 12 and the second flying capacitor circuit 13, and transmits the AC power to the load 50 connected to the power conversion device 1 and the interconnection. output to the power system where In the filter unit 20, the output current value io and the output voltage value vo (applied voltage of the capacitor 20c) of the AC power generated by the power conversion unit 10 and output to the load 50 side are measured through a current sensor and a voltage sensor, respectively. be.
 制御部30は、プロセッサ(CPU等)、メモリ、ゲートドライバ、通信インタフェース回路等を含んで構成されるユニットである。制御部30には、電力変換部10に設けられた各種のセンサ(電圧センサ、電流センサ)、フィルタ部20等に設けられた電流センサ、電圧センサの出力が入力される。また、制御部30から、電力変換部10を構成する各スイッチ素子の開閉(オン/オフ)を制御する制御信号が出力される。制御部では、上記各種のセンサを通じて検出された情報に基づいて、スイッチ素子S1からS16の開閉を制御することで、第1直流キャパシタdc1および第2直流キャパシタdc2の電圧値が「2E」、フライングキャパシタfc1およびフライングキャパシタfc2の電圧値が「E」となるように制御される。同様にして、第1直流キャパシタdc1および第2直流キャパシタdc2、フライングキャパシタfc1およびフライングキャパシタfc2にクランプされた電圧値を、スイッチ素子S1からS16の開閉を選択して充放電させることで、5レベルの電位(4E、2E、0、-2E、-4E)を生成する。生成された5レベルの電位は、例えば、キャリア比較方式によるPWM(Pulse Width Modulation)変調が行われ、各スイッチ素子の開閉を選択する制御パターンに基づいて正弦波の電圧指令値に追従した加減算が行われ、出力端子Tp3およびTp4に出力される。 The control unit 30 is a unit including a processor (CPU, etc.), memory, gate driver, communication interface circuit, and the like. The control unit 30 receives outputs from various sensors (voltage sensor, current sensor) provided in the power conversion unit 10, and current sensors and voltage sensors provided in the filter unit 20 and the like. Further, the control unit 30 outputs a control signal for controlling the opening/closing (on/off) of each switch element forming the power conversion unit 10 . Based on the information detected by the various sensors described above, the control unit controls the opening and closing of the switch elements S1 to S16 so that the voltage values of the first DC capacitor dc1 and the second DC capacitor dc2 are set to "2E" and flying. The voltage values of capacitor fc1 and flying capacitor fc2 are controlled to be "E". Similarly, the voltage values clamped in the first DC capacitor dc1, the second DC capacitor dc2, the flying capacitor fc1, and the flying capacitor fc2 are charged and discharged by selectively opening and closing the switch elements S1 to S16, thereby obtaining 5 levels. potentials (4E, 2E, 0, -2E, -4E). The generated 5-level potential is, for example, PWM (Pulse Width Modulation) modulated by a carrier comparison method, and addition and subtraction following the sine wave voltage command value is performed based on the control pattern for selecting the opening and closing of each switch element. and output to output terminals Tp3 and Tp4.
 図2は、5レベルの電位により生成される交流電力を説明する図である。図2(1)には、5レベルの電位により生成される交流電力波形を示すグラフが例示され、図2(2)には、生成された電位2Eを出力する場合のスイッチングパターンが例示される。図2(1)において、縦軸は電力変換部10の出力電圧を表し、横軸は時間経過を表す。出力電圧“Vo”はフィルタ部20に入力される交流電圧を表し、出力電圧“Vg”は負荷50に入力される交流電圧を表す。なお、図2(1)における“Vg(=Vgm・sinθ)”のグラフは、正弦波の電圧指令値の推移を表し、“m”は変調率を表す。図2においては、“Vgm=4E・m”となる。 FIG. 2 is a diagram for explaining AC power generated by five levels of potential. FIG. 2(1) exemplifies a graph showing an AC power waveform generated by five levels of potential, and FIG. 2(2) exemplifies a switching pattern when outputting the generated potential 2E. . In FIG. 2(1), the vertical axis represents the output voltage of the power converter 10, and the horizontal axis represents the passage of time. An output voltage “Vo” represents an AC voltage input to the filter unit 20 , and an output voltage “Vg” represents an AC voltage input to the load 50 . The graph of "Vg (=Vgm·sin θ)" in FIG. 2(1) represents the transition of the voltage command value of the sine wave, and "m" represents the modulation factor. In FIG. 2, "Vgm=4E·m".
 図2(1)に示すように、丸囲み2の区間では、電圧値が正弦波の電圧指令値に追従するように電位“0”と“2E”との間でPWM変調が行われる。同様にして、丸囲み1の区間では電位“2E”と“4E”、丸囲み4の区間では電位“0”と“-2E”、丸囲み3の区間では電位“-2E”と“-4E”との間で、電圧値が正弦波の電圧指令値に追従するようにPWM変調が行われる。制御部30は、電圧値が正弦波の電圧指令値に追従するように各区間で生成された交流電力を出力するためのスイッチングパターンに基づいて、出力端子Tp3およびTp4に出力する。ここで、スイッチングパターンとは、それぞれの区間において変調された電圧値を正弦波の電圧指令値に追従して出力するための、導通または開放するスイッチ素子の組合せである。制御部30は、それぞれの区間に応じて開閉するスイッチ素子を選択して当該スイッチ素子の導通または開放を制御することで、フライングキャパシタfc1およびfc2の充放電を制御する。なお、フライングキャパシタfc1およびfc2のエネルギーは、第1直流キャパシタdc1および第2直流キャパシタdc2に充電されたエネルギーを通じて充電される。 As shown in FIG. 2 (1), in the section circled 2, PWM modulation is performed between potentials "0" and "2E" so that the voltage value follows the sine wave voltage command value. Similarly, potentials "2E" and "4E" in the section surrounded by circle 1, potentials "0" and "-2E" in the section surrounded by circle 4, and potentials "-2E" and "-4E" in the section surrounded by circle 3. ”, PWM modulation is performed so that the voltage value follows the sinusoidal voltage command value. The control unit 30 outputs to the output terminals Tp3 and Tp4 based on the switching pattern for outputting the AC power generated in each section so that the voltage value follows the sine wave voltage command value. Here, the switching pattern is a combination of switch elements that are conductive or open for outputting the voltage value modulated in each section following the voltage command value of the sine wave. The control unit 30 selects a switching element that opens and closes according to each section and controls conduction or opening of the switching element, thereby controlling charging/discharging of the flying capacitors fc1 and fc2. The energy of the flying capacitors fc1 and fc2 is charged through the energy charged in the first DC capacitor dc1 and the second DC capacitor dc2.
 図2(2)において、太実線で表された矢印は、2E出力時の電流が流れる経路を表す。図2(2)に示すように電位2Eを出力する場合では、太実線の矢印で表された経路上の各スイッチ素子が導通される。すなわち、第1出力回路14を構成するスイッチ素子S7のドレイン端子とソース端子が導通する。そして、第1フライングキャパシタ回路12を構成するスイッチ素子S4およびスイッチ素子S1のドレイン端子とソース端子が導通する。また、第2出力回路15を構成するスイッチ素子S16のドレイン端子とソース端子が導通し、第2フライングキャパシタ回路13を構成するスイッチ素子S12およびスイッチ素子S9のドレイン端子とソース端子が導通する。制御部30は、上記各スイッチ素子のゲート端子の動作電圧をオン状態に移行させ、スイッチ素子S7と、スイッチ素子S4と、スイッチ素子S1と、スイッチ素子S16と、スイッチ素子S12、スイッチ素子S9のドレイン端子とソース端子間を導通させる。この結果、第1フライングキャパシタ回路12のフライングキャパシタfc1に充電されたエネルギーが放電され、第2フライングキャパシタ回路13のフライングキャパシタfc2にエネルギーが充電される。そして、第2直流キャパシタdc2の端子間に係る電位「2E」が、第1フライングキャパシタ回路12のスイッチ素子S1のソース端子に接続された出力端子Tp4と、第2フライングキャパシタ回路13のスイッチ素子S9のソース端子に接続された出力端子Tp3とを通じてフィルタ回路20に出力される。つまり、第2直流キャパシタdc2の電圧値を「VDC2」、フライングキャパシタfc1に充電されたエネルギーを「VFC1」、フライングキャパシタfc2に充電されたエネルギーを「VFC2」、とすると、フィルタ回路20で検出される出力電圧値「vo」は、{VDC2+VFC1-VFC2}として表すことができる。 In FIG. 2(2), the thick solid arrow indicates the path through which the current flows during 2E output. When the potential 2E is output as shown in FIG. 2(2), each switch element on the path indicated by the thick solid line arrow is turned on. That is, the drain terminal and the source terminal of the switch element S7 forming the first output circuit 14 are electrically connected. Then, the drain terminals and the source terminals of the switch elements S4 and S1 that constitute the first flying capacitor circuit 12 are electrically connected. Also, the drain terminal and the source terminal of the switch element S16 constituting the second output circuit 15 are electrically connected, and the drain terminal and the source terminal of the switch element S12 and the switch element S9 constituting the second flying capacitor circuit 13 are electrically connected. The control unit 30 shifts the operating voltage of the gate terminal of each switch element to the ON state, and switches the switch element S7, the switch element S4, the switch element S1, the switch element S16, the switch element S12, and the switch element S9. Conduct between the drain terminal and the source terminal. As a result, the energy charged in the flying capacitor fc1 of the first flying capacitor circuit 12 is discharged, and the flying capacitor fc2 of the second flying capacitor circuit 13 is charged with energy. Then, the potential “2E” between the terminals of the second DC capacitor dc2 is applied to the output terminal Tp4 connected to the source terminal of the switch element S1 of the first flying capacitor circuit 12 and the switch element S9 of the second flying capacitor circuit 13. is output to the filter circuit 20 through the output terminal Tp3 connected to the source terminal of . That is, the voltage value of the second DC capacitor dc2 is "VDC2", the energy charged in the flying capacitor fc1 is "VFC1", and the energy charged in the flying capacitor fc2 is "VFC2". The output voltage value 'vo' for the current can be expressed as {VDC2+VFC1−VFC2}.
 図3は、フライングキャパシタfc1、fc2における充放電モードを説明する図である。図3においても、太実線で表された矢印は電流の流れる経路を表す。第1フライングキャパシタ回路12においては、フライングキャパシタfc1を充放電させるための2種類の電流経路が存在する。第2フライングキャパシタ回路13においても、フライングキャパシタfc2を充放電させるための2種類の電流経路が存在する。このため、第1フライングキャパシタ回路12および第2フライングキャパシタ回路13を構成に含む電力変換部10においては、図3(a)から(d)に示される4種類のスイッチングパターンが存在する。本実施例の電力変換部10においては、第1フライングキャパシタ回路12および第2フライングキャパシタ回路13と、第1出力回路14および第2出力回路15の各回路を構成するスイッチング素子S1からS16のオン/オフ状態を制御することで、正弦波の電圧指令値に追従する電圧が出力される。なお、図3(a)から(d)において、丸囲みされたスイッチ素子は、ドレイン端子-ソース端子間が導通されたオン状態を表す。また、図3(a)、(b)では、電流の流れが電力変換部10側から負荷50に向かう流れとなり、図3(c)、(d)では、電流の流れが負荷50側から電力変換部10へ向かう流れとなる。 FIG. 3 is a diagram for explaining charging and discharging modes in flying capacitors fc1 and fc2. In FIG. 3 as well, arrows represented by thick solid lines represent paths through which current flows. In the first flying capacitor circuit 12, there are two types of current paths for charging and discharging the flying capacitor fc1. Also in the second flying capacitor circuit 13, there are two types of current paths for charging and discharging the flying capacitor fc2. Therefore, in the power converter 10 including the first flying capacitor circuit 12 and the second flying capacitor circuit 13, there are four types of switching patterns shown in FIGS. 3(a) to 3(d). In the power conversion unit 10 of the present embodiment, the switching elements S1 to S16 constituting each circuit of the first flying capacitor circuit 12 and the second flying capacitor circuit 13 and the first output circuit 14 and the second output circuit 15 are turned on. By controlling the /OFF state, a voltage that follows the sinusoidal voltage command value is output. In FIGS. 3(a) to 3(d), the encircled switching elements represent an ON state in which the drain terminal and the source terminal are electrically connected. In addition, in FIGS. 3A and 3B, the current flows from the power converter 10 side to the load 50, and in FIGS. It becomes a flow toward the conversion unit 10 .
 図3(a)に示すスイッチングパターンでは、第1フライングキャパシタ回路12のスイッチ素子S3およびスイッチ素子S2のドレイン端子-ソース端子間が導通し、オン状態になる。また、第1出力回路14のスイッチ素子S5およびスイッチ素子S7のドレイン端子-ソース端子間が導通し、オン状態になる。第2フライングキャパシタ回路13においては、スイッチ素子S11およびスイッチ素子S10のドレイン端子-ソース端子間が導通し、オン状態になる。また、第2出力回路15では、スイッチ素子S14およびスイッチ素子S16のドレイン端子-ソース端子間が導通し、オン状態になる。この結果、第1直流キャパシタdc1の高電位側に接続されたスイッチ素子S5のドレイン端子、および、第1直流キャパシタdc1の低電位側に接続されたスイッチ素子S14のソース端子を通じて、負荷50側に向かう電流経路が形成される。すなわち、スイッチ素子S5→スイッチ素子S3→フライングキャパシタfc1→スイッチ素子S2→負荷50→スイッチ素子S10→フライングキャパシタfc2→スイッチ素子S11→スイッチ素子S14の経路で、第1直流キャパシタdc1の高電位側から低電位側に向かう電流経路が形成される。当該スイッチングパターンにより、フライングキャパシタfc1が充電され、フライングキャパシタfc2が放電される。 In the switching pattern shown in FIG. 3(a), the switch element S3 and the switch element S2 of the first flying capacitor circuit 12 are electrically connected between the drain terminal and the source terminal and turned on. Further, the switch element S5 and the switch element S7 of the first output circuit 14 are electrically connected between the drain terminal and the source terminal and turned on. In the second flying capacitor circuit 13, the switch element S11 and the switch element S10 are electrically connected between the drain terminal and the source terminal, and turned on. Also, in the second output circuit 15, the switch element S14 and the switch element S16 are electrically connected between the drain terminal and the source terminal, and are turned on. As a result, through the drain terminal of the switching element S5 connected to the high potential side of the first DC capacitor dc1 and the source terminal of the switching element S14 connected to the low potential side of the first DC capacitor dc1, A directed current path is formed. That is, the switch element S5→switch element S3→flying capacitor fc1→switch element S2→load 50→switch element S10→flying capacitor fc2→switch element S11→switch element S14. A current path toward the low potential side is formed. The switching pattern charges the flying capacitor fc1 and discharges the flying capacitor fc2.
 図3(b)に示すスイッチングパターンでは、第1フライングキャパシタ回路12のスイッチ素子S1およびスイッチ素子S4のドレイン端子-ソース端子間が導通し、オン状態になる。また、第1出力回路14のスイッチ素子S5およびスイッチ素子S7のドレイン端子-ソース端子間が導通し、オン状態になる。第2フライングキャパシタ回路13においては、スイッチ素子S9およびスイッチ素子S12のドレイン端子-ソース端子間が導通し、オン状態になる。また、第2出力回路15では、スイッチ素子S14およびスイッチ素子S16のドレイン端子-ソース端子間が導通し、オン状態になる。この結果、第2直流キャパシタdc2の高電位側に接続されたスイッチ素子S7のドレイン端子、および、第2直流キャパシタdc2の低電位側に接続されたスイッチ素子S16のソース端子を通じて、負荷50側に向かう電流経路が形成される。すなわち、スイッチ素子S7→スイッチ素子S4→フライングキャパシタfc1→スイッチ素子S1→負荷50→スイッチ素子S9→フライングキャパシタfc2→スイッチ素子S12→スイッチ素子S16の経路で、第2直流キャパシタdc2の高電位側から低電位側に向かう電流経路が形成される。当該スイッチングパターンにより、フライングキャパシタfc1が放電され、フライングキャパシタfc2が充電される。 In the switching pattern shown in FIG. 3(b), the switch element S1 and the switch element S4 of the first flying capacitor circuit 12 are electrically connected between the drain terminal and the source terminal and turned on. Further, the switch element S5 and the switch element S7 of the first output circuit 14 are electrically connected between the drain terminal and the source terminal and turned on. In the second flying capacitor circuit 13, the switch element S9 and the switch element S12 are electrically connected between the drain terminal and the source terminal, and turned on. Also, in the second output circuit 15, the switch element S14 and the switch element S16 are electrically connected between the drain terminal and the source terminal, and are turned on. As a result, through the drain terminal of the switching element S7 connected to the high potential side of the second DC capacitor dc2 and the source terminal of the switching element S16 connected to the low potential side of the second DC capacitor dc2, A directed current path is formed. That is, from the high potential side of the second DC capacitor dc2 in the route of switch element S7→switch element S4→flying capacitor fc1→switch element S1→load 50→switch element S9→flying capacitor fc2→switch element S12→switch element S16. A current path toward the low potential side is formed. The switching pattern discharges the flying capacitor fc1 and charges the flying capacitor fc2.
 図3(c)に示すスイッチングパターンでは、第1フライングキャパシタ回路12のスイッチ素子S3およびスイッチ素子S2のドレイン端子-ソース端子間が導通し、オン状態になる。また、第1出力回路14のスイッチ素子S6およびスイッチ素子S8のドレイン端子-ソース端子間が導通し、オン状態になる。第2フライングキャパシタ回路13においては、スイッチ素子S11およびスイッチ素子S10のドレイン端子-ソース端子間が導通し、オン状態になる。また、第2出力回路15では、スイッチ素子S13およびスイッチ素子S15のドレイン端子-ソース端子間が導通し、オン状態になる。この結果、第1直流キャパシタdc1の高電位側に接続されたスイッチ素子S13のドレイン端子、および、第1直流キャパシタdc1の低電位側に接続されたスイッチ素子S6のソース端子を通じて、負荷50側から電力変換部10に向かう電流経路が形成される。すなわち、スイッチ素子S13→スイッチ素子S11→フライングキャパシタfc2→スイッチ素子S10→負荷50→スイッチ素子S2→フライングキャパシタfc1→スイッチ素子S3→スイッチ素子S6の経路で、第1直流キャパシタdc1の高電位側から低電位側に向かう電流経路が形成される。当該スイッチングパターンにより、フライングキャパシタfc2が充電され、フライングキャパシタfc1が放電される。 In the switching pattern shown in FIG. 3(c), the switch element S3 and the switch element S2 of the first flying capacitor circuit 12 are electrically connected between the drain terminal and the source terminal and turned on. Also, the switch element S6 and the switch element S8 of the first output circuit 14 are electrically connected between the drain terminal and the source terminal, and turned on. In the second flying capacitor circuit 13, the switch element S11 and the switch element S10 are electrically connected between the drain terminal and the source terminal, and turned on. Also, in the second output circuit 15, the switch element S13 and the switch element S15 are electrically connected between the drain terminal and the source terminal, and are turned on. As a result, from the load 50 side through the drain terminal of the switching element S13 connected to the high potential side of the first DC capacitor dc1 and the source terminal of the switching element S6 connected to the low potential side of the first DC capacitor dc1. A current path toward the power converter 10 is formed. That is, from the high potential side of the first DC capacitor dc1 in the route of switch element S13→switch element S11→flying capacitor fc2→switch element S10→load 50→switch element S2→flying capacitor fc1→switch element S3→switch element S6. A current path toward the low potential side is formed. The switching pattern charges the flying capacitor fc2 and discharges the flying capacitor fc1.
 図3(d)に示すスイッチングパターンでは、第1フライングキャパシタ回路12のスイッチ素子S1およびスイッチ素子S4のドレイン端子-ソース端子間が導通し、オン状態になる。また、第1出力回路14のスイッチ素子S6およびスイッチ素子S8のドレイン端子-ソース端子間が導通し、オン状態になる。第2フライングキャパシタ回路13においては、スイッチ素子S9およびスイッチ素子S12のドレイン端子-ソース端子間が導通し、オン状態になる。また、第2出力回路15では、スイッチ素子S13およびスイッチ素子S15のドレイン端子-ソース端子間が導通し、オン状態になる。この結果、第2直流キャパシタdc2の高電位側に接続されたスイッチ素子S15のドレイン端子、および、第2直流キャパシタdc2の低電位側に接続されたスイッチ素子S8のソース端子を通じて、負荷50側から電力変換部10に向かう電流経路が形成される。すなわち、スイッチ素子S15→スイッチ素子S12→フライングキャパシタfc2→スイッチ素子S9→負荷50→スイッチ素子S1→フライングキャパシタfc1→スイッチ素子S4→スイッチ素子S8の経路で、第2直流キャパシタdc2の高電位側から低電位側に向かう電流経路が形成される。当該スイッチングパターンにより、フライングキャパシタfc2放電され、フライングキャパシタfc1が充電される。 In the switching pattern shown in FIG. 3(d), the switch element S1 and the switch element S4 of the first flying capacitor circuit 12 are electrically connected between the drain terminal and the source terminal and turned on. Also, the switch element S6 and the switch element S8 of the first output circuit 14 are electrically connected between the drain terminal and the source terminal, and turned on. In the second flying capacitor circuit 13, the switch element S9 and the switch element S12 are electrically connected between the drain terminal and the source terminal, and turned on. In addition, in the second output circuit 15, the switch element S13 and the switch element S15 are electrically connected between the drain terminal and the source terminal to be turned on. As a result, from the load 50 side through the drain terminal of the switching element S15 connected to the high potential side of the second DC capacitor dc2 and the source terminal of the switching element S8 connected to the low potential side of the second DC capacitor dc2. A current path directed to the power conversion unit 10 is formed. That is, from the high potential side of the second DC capacitor dc2 in the route of switch element S15→switch element S12→flying capacitor fc2→switch element S9→load 50→switch element S1→flying capacitor fc1→switch element S4→switch element S8. A current path toward the low potential side is formed. This switching pattern discharges the flying capacitor fc2 and charges the flying capacitor fc1.
 図4は、図3に示す各スイッチングパターンと電力変換部10に含まれる各キャパシタとの充放電状態を説明する図である。図4のTb1には、図3で説明した(a)から(d)のスイッチングパターンと、フライングキャパシタfc1およびfc2、第1直流キャパシタdc1および第2直流キャパシタdc2の充放電状態を表すテーブルが例示される。図4のTb1に示すように、図3(a)のスイッチングパターンでは、フライングキャパシタfc1が充電され、フライングキャパシタfc2が放電される。また、第1直流キャパシタdc1が放電され、第2直流キャパシタdc2が充電される。図3(b)のスイッチングパターンでは、フライングキャパシタfc1が放電され、フライングキャパシタfc2が充電され、第1直流キャパシタdc1が充電され、第2直流キャパシタdc2が放電される。同様にして、図3(c)のスイッチングパターンでは、フライングキャパシタfc1が放電され、フライングキャパシタfc2が充電され、第1直流キャパシタdc1が放電され、第2直流キャパシタdc2が充電される。図3(d)のスイッチングパターンでは、フライングキャパシタfc1が充電され、フライングキャパシタfc2が放電され、第1直流キャパシタdc1が充電され、第2直流キャパシタdc2が放電される。 FIG. 4 is a diagram for explaining the charging/discharging state of each switching pattern shown in FIG. 3 and each capacitor included in the power converter 10. FIG. Tb1 in FIG. 4 illustrates a table showing the switching patterns (a) to (d) described in FIG. 3 and the charging/discharging states of the flying capacitors fc1 and fc2, the first DC capacitor dc1 and the second DC capacitor dc2. be done. As indicated by Tb1 in FIG. 4, in the switching pattern of FIG. 3A, the flying capacitor fc1 is charged and the flying capacitor fc2 is discharged. Also, the first DC capacitor dc1 is discharged and the second DC capacitor dc2 is charged. In the switching pattern of FIG. 3(b), the flying capacitor fc1 is discharged, the flying capacitor fc2 is charged, the first DC capacitor dc1 is charged, and the second DC capacitor dc2 is discharged. Similarly, in the switching pattern of FIG. 3(c), the flying capacitor fc1 is discharged, the flying capacitor fc2 is charged, the first DC capacitor dc1 is discharged, and the second DC capacitor dc2 is charged. In the switching pattern of FIG. 3(d), the flying capacitor fc1 is charged, the flying capacitor fc2 is discharged, the first DC capacitor dc1 is charged, and the second DC capacitor dc2 is discharged.
 図4に示すように、図3(a)から(d)のスイッチングパターンに係る時間が同じであれば、フライングキャパシタfc1およびfc2、第1直流キャパシタdc1および第2直流キャパシタdc2の電圧は一定になる。例えば、フライングキャパシタfc1およびfc2の電圧は「E」、第1直流キャパシタdc1および第2直流キャパシタdc2の電圧は「2E」となる。しかしながら、第1フライングキャパシタ回路12、第2フライングキャパシタ回路13、第1出力回路14、第2出力回路15のそれぞれを構成する部品パラメータのばらつきが存在する。例えば、各回路を構成するスイッチ素子の浮遊容量や抵抗がばらつくため、スイッチング時間にずれが生じることになる。また、フライングキャパシタfc1の電圧値(VFC1)、フライングキャパシタfc2の電圧値(VFC2)、第1直流キャパシタdc1の電圧値(VDC1)、第2直流キャパシタdc2の電圧値(VDC2)が所望の値から外れるほど、コモンモードノイズは悪化し、所望の値に近付くほど、コモンモードノイズは低減されることになる。 As shown in FIG. 4, if the times associated with the switching patterns of FIGS. Become. For example, the voltages of the flying capacitors fc1 and fc2 are "E", and the voltages of the first DC capacitor dc1 and the second DC capacitor dc2 are "2E". However, there are variations in the component parameters that configure the first flying capacitor circuit 12, the second flying capacitor circuit 13, the first output circuit 14, and the second output circuit 15, respectively. For example, the stray capacitances and resistances of the switch elements that make up each circuit vary, resulting in deviations in switching time. Also, the voltage value of the flying capacitor fc1 (VFC1), the voltage value of the flying capacitor fc2 (VFC2), the voltage value of the first DC capacitor dc1 (VDC1), and the voltage value of the second DC capacitor dc2 (VDC2) are changed from desired values. The further away, the worse the common mode noise, and the closer to the desired value, the more the common mode noise will be reduced.
 図5は、スイッチング時間のずれによる影響を説明する図である。図5(1)は、図2(2)で説明した2Eを出力する直前のスイッチング状態を表し、図5(2)は、第1フライングキャパシタ回路12のスイッチ素子S1のスイッチング時間が相対的に遅い場合の状態を表す。なお、図5(3)には、比較としての、スイッチ素子S1のスイッチング時間が理想的な場合の状態が例示されている。なお、図5(1)から(3)においても、なお、丸囲みされたスイッチ素子はドレイン端子-ソース端子間が導通されたオン状態を表し、太実線で示された矢印は電流の流れる経路を表す。 FIG. 5 is a diagram explaining the influence of switching time lag. FIG. 5(1) shows the switching state immediately before outputting 2E explained in FIG. 2(2), and FIG. Represents the state when it is slow. For comparison, FIG. 5(3) exemplifies a state in which the switching time of the switch element S1 is ideal. In FIGS. 5(1) to 5(3) as well, the circled switch elements represent the ON state in which the drain terminal and the source terminal are electrically connected, and the thick solid arrow indicates the path through which the current flows. represents
 図5(1)に示す直近のスイッチング状態から2Eを出力する場合、図5(3)に示す理想的なスイッチング状態に遷移することが望ましい。すなわち、オン状態(ドレイン端子-ソース端子間が導通状態)に制御された、第2直流キャパシタdc2の高電位側にドレイン端子が接続されたスイッチ素子S7から、スイッチ素子S4およびスイッチ素子S1を通じて負荷側に向かう電流経路が形成される。また、オン状態に制御された、スイッチ素子S9およびスイッチ素子S12、スイッチ素子S16を通じて、負荷側から第2直流キャパシタdc2の低電位側に向かう電流経路が形成される。電流経路上のフライングキャパシタfc1が放電し、フライングキャパシタfc2が充電され、負荷の端子間には第2直流キャパシタdc2にクランプされた2Eにフライングキャパシタfc1の放電エネルギーとフライングキャパシタfc2の充電エネルギーを加えた{vo=VDC2+VFC1-VFC2}の電圧が印加される。 When outputting 2E from the latest switching state shown in FIG. 5(1), it is desirable to transition to the ideal switching state shown in FIG. 5(3). That is, from the switch element S7 whose drain terminal is connected to the high potential side of the second DC capacitor dc2, which is controlled to be in an ON state (a conductive state between the drain terminal and the source terminal), the load is switched through the switch element S4 and the switch element S1. A current path toward the side is formed. A current path from the load side to the low potential side of the second DC capacitor dc2 is formed through the switch element S9, the switch element S12, and the switch element S16 that are controlled to be on. The flying capacitor fc1 on the current path is discharged, the flying capacitor fc2 is charged, and the discharge energy of the flying capacitor fc1 and the charging energy of the flying capacitor fc2 are added to 2E clamped by the second DC capacitor dc2 between the terminals of the load. A voltage of {vo=VDC2+VFC1-VFC2} is also applied.
 しかしながら、図5(2)に示すように、例えば、部品パラメータのばらつきによりスイッチ素子S1の応答が遅い場合にはオン状態に遷移せず、スイッチ素子S4からフライングキャパシタfc1を通じてスイッチ素子S1に流れ込む電流経路が形成されない。電力変換部10では、直近のスイッチング状態で形成された電流経路に従って負荷側へ電流が流れ、オン状態に制御された、スイッチ素子S9およびスイッチ素子S12、スイッチ素子S16を通じて、負荷側から第2直流キャパシタdc2の低電位側に向かう電流経路が形成される。この結果、フライングキャパシタfc2は充電されることになるが、フライングキャパシタfc1は放電されずスイッチ素子S1がオン状態に遷移するまでの間、電圧が上昇することになり、電力変換部10から出力される電圧が変動する虞があった。 However, as shown in FIG. 5(2), for example, when the response of the switching element S1 is slow due to variations in component parameters, the current flowing from the switching element S4 to the switching element S1 through the flying capacitor fc1 does not transition to the ON state. No route is formed. In the power conversion unit 10, current flows to the load side according to the current path formed in the most recent switching state, and the second DC current flows from the load side through the switch elements S9, S12, and S16 that are controlled to be on. A current path directed to the low potential side of capacitor dc2 is formed. As a result, the flying capacitor fc2 is charged, but the flying capacitor fc1 is not discharged and the voltage rises until the switch element S1 transitions to the ON state. There was a risk that the voltage applied to the
 本実施例に係る電力変換装置1は、フライングキャパシタfc1およびfc2、第1直流キャパシタdc1および第2直流キャパシタdc2の充放電に係る各スイッチ素子のスイッチングを制御することで、部品パラメータのばらつきによる電圧変動を抑制する。具体的には、電力変換装置1の制御部30は、第1フライングキャパシタ回路12のスイッチ素子S1およびS3のオン期間(デューティ)を増加または減少させることでフライングキャパシタfc1の電圧制御を行う。同様にして、制御部30は、第2フライングキャパシタ回路13のスイッチ素子S9およびS11のデューティを増加または減少させることでフライングキャパシタfc2の電圧制御を行う。そして、本実施例に係る電力変換装置1の制御部30は、フライングキャパシタfc1およびfc2の電圧に基づいて、スイッチ素子S3またはスイッチ素子S11のデューティを増加または減少させることで、第1直流キャパシタdc1および第2直流キャパシタdc2の電圧制御を行う。本実施例に係る電力変換装置1においては、上記スイッチ素子のスイッチング制御により、フライングキャパシタfc1およびfc2、第1直流キャパシタdc1および第2直流キャパシタdc2の電圧が一定に制御できるため安定性が向上し、生成される交流電力の精度を高めることが可能になる。以下、図6から図9を用いて、フライングキャパシタfc1およびfc2、第1直流キャパシタdc1および第2直流キャパシタdc2の電圧制御を説明する。 The power conversion device 1 according to the present embodiment controls the switching of each switch element related to the charging and discharging of the flying capacitors fc1 and fc2, the first DC capacitor dc1 and the second DC capacitor dc2, thereby reducing the voltage caused by the variation in the component parameters. Control fluctuations. Specifically, the control unit 30 of the power conversion device 1 increases or decreases the ON period (duty) of the switch elements S1 and S3 of the first flying capacitor circuit 12 to control the voltage of the flying capacitor fc1. Similarly, the control unit 30 increases or decreases the duty of the switch elements S9 and S11 of the second flying capacitor circuit 13 to control the voltage of the flying capacitor fc2. Then, the control unit 30 of the power conversion device 1 according to the present embodiment increases or decreases the duty of the switch element S3 or the switch element S11 based on the voltages of the flying capacitors fc1 and fc2, so that the first DC capacitor dc1 and voltage control of the second DC capacitor dc2. In the power converter 1 according to the present embodiment, the voltages of the flying capacitors fc1 and fc2, the first DC capacitor dc1 and the second DC capacitor dc2 can be controlled to be constant by switching control of the switch elements, thereby improving stability. , it is possible to increase the accuracy of the generated AC power. Voltage control of the flying capacitors fc1 and fc2, the first DC capacitor dc1 and the second DC capacitor dc2 will be described below with reference to FIGS.
 図6は、フライングキャパシタfc1の電圧制御を説明する図である。図6(1)には、フライングキャパシタfc1における電流経路が太実線の矢印により例示されている。丸囲みされたスイッチ素子はドレイン端子-ソース端子間が導通されたオン状態を表す。図6(1)の(a)に示す電流経路は、フライングキャパシタfc1が充電される場合の電流経路であり、図6(1)の(b)に示す電流経路は、フライングキャパシタfc1が放電される場合の電流経路を表す。本実施例の電力変換装置1においては、スイッチ素子S1からS4のオン/オフ状態が選択され、フライングキャパシタfc1に流れる電流経路が選択されることで電圧制御が行われる。 FIG. 6 is a diagram explaining voltage control of the flying capacitor fc1. In FIG. 6(1), the current path in the flying capacitor fc1 is illustrated by a thick solid arrow. A switch element surrounded by a circle represents an ON state in which the drain terminal and the source terminal are electrically connected. The current path shown in (a) of FIG. 6(1) is the current path when the flying capacitor fc1 is charged, and the current path shown in (b) of FIG. 6(1) is the current path when the flying capacitor fc1 is discharged. represents the current path when In the power conversion device 1 of the present embodiment, voltage control is performed by selecting the ON/OFF states of the switch elements S1 to S4 and selecting the current path flowing through the flying capacitor fc1.
 図6(1)の(a)に示すように、第1フライングキャパシタ回路12のスイッチ素子S3のドレイン端子には、オン状態のスイッチ素子S5のドレイン端子-ソース端子を通じて第1直流キャパシタdc1の高電位側が接続される。スイッチ素子S3およびスイッチ素子S2がオン状態の場合には、スイッチ素子S3のドレイン端子-ソース端子→フライングキャパシタfc1→スイッチ素子S2のドレイン端子-ソース端子が導通し、負荷側に向かう電流経路が形成される。フライングキャパシタfc1には、オン状態のスイッチ素子S5のドレイン端子-ソース端子を通じて第1直流キャパシタdc1の高電位側から負荷側に電流が流れ、フライングキャパシタfc1が充電される。 As shown in (a) of FIG. 6(1), the drain terminal of the switching element S3 of the first flying capacitor circuit 12 receives the high voltage of the first DC capacitor dc1 through the drain terminal-source terminal of the ON state switching element S5. The potential side is connected. When the switch element S3 and the switch element S2 are in the ON state, the drain terminal-source terminal of the switch element S3→flying capacitor fc1→the drain terminal-source terminal of the switch element S2 are conducted, forming a current path toward the load side. be done. A current flows from the high potential side of the first DC capacitor dc1 to the load side through the drain terminal-source terminal of the ON-state switch element S5, and the flying capacitor fc1 is charged.
 図6(1)の(b)においては、第1フライングキャパシタ回路12のスイッチ素子S4のソース端子には、オン状態のスイッチ素子S7のドレイン端子-ソース端子を通じて第1直流キャパシタdc1の低電位側が接続される。スイッチ素子S4およびスイッチ素子S1がオン状態の場合には、スイッチ素子S4のドレイン端子-ソース端子→フライングキャパシタfc1→スイッチ素子S1のドレイン端子-ソース端子が導通し、負荷側に向かう電流経路が形成される。フライングキャパシタfc1には、オン状態のスイッチ素子S7のドレイン端子-ソース端子を通じて第1直流キャパシタdc1の低電位側から負荷側に電流が流れ、フライングキャパシタfc1が放電される。 6(1)(b), the low potential side of the first DC capacitor dc1 is connected to the source terminal of the switching element S4 of the first flying capacitor circuit 12 through the drain terminal-source terminal of the ON state switching element S7. Connected. When the switch element S4 and the switch element S1 are in the ON state, the drain terminal-source terminal of the switch element S4→flying capacitor fc1→the drain terminal-source terminal of the switch element S1 are conducted, forming a current path toward the load side. be done. In the flying capacitor fc1, current flows from the low potential side of the first DC capacitor dc1 to the load side through the drain terminal-source terminal of the ON state switch element S7, and the flying capacitor fc1 is discharged.
 図6(1)の(a)、(b)に示すように、スイッチ素子S3およびスイッチ素子S2、スイッチ素子S4およびスイッチ素子S1のオン期間(デューティ)の長さを制御することで、フライングキャパシタfc1の充放電に係る期間が制御でき、フライングキャパシタfc1の電圧制御が可能になる。 As shown in (a) and (b) of FIG. 6 (1), by controlling the length of the ON period (duty) of the switch element S3 and the switch element S2, the switch element S4 and the switch element S1, the flying capacitor The period for charging and discharging fc1 can be controlled, and the voltage of the flying capacitor fc1 can be controlled.
 図6(2)には、フライングキャパシタfc1の電圧制御に係る各スイッチ素子の相対的なタイミングチャートが例示される。図6(2)の縦軸は各スイッチ素子の2値(オン/オフ)のステータスを表し、横軸は時間の経過を表す。なお、第1フライングキャパシタ回路12のスイッチ素子S1およびS2のオン状態およびオフ状態は、一対で相補的に制御される。つまり、一方がオン状態のときには、他方はオフ状態に制御される。第1フライングキャパシタ回路12のスイッチ素子S3およびS4、第1出力回路14のスイッチ素子S5およびS6、スイッチ素子S7およびS8も同様である。 FIG. 6(2) illustrates a relative timing chart of each switch element related to voltage control of the flying capacitor fc1. The vertical axis of FIG. 6(2) represents the binary (on/off) status of each switch element, and the horizontal axis represents the passage of time. The ON state and OFF state of the switch elements S1 and S2 of the first flying capacitor circuit 12 are complementarily controlled as a pair. That is, when one is on, the other is controlled to be off. The same applies to switch elements S3 and S4 of the first flying capacitor circuit 12, switch elements S5 and S6 of the first output circuit 14, and switch elements S7 and S8.
 図6(2)の上段にはスイッチ素子S1(上線付きS2)のオン/オフ状態の遷移、中段にはスイッチ素子S3(上線付きS4)のオン/オフ状態の遷移、下段にはスイッチ素子S5(上線付きS6)およびスイッチ素子S7(上線付きS8)のオン/オフ状態の遷移が例示される。以下、スイッチ素子S1(上線付きS2)のオン期間を“デューティD1”、スイッチ素子S3(上線付きS4)のオン期間を“デューティD3”とも言う。 In FIG. 6B, the upper part shows the on/off state transition of the switch element S1 (upper line S2), the middle part shows the on/off state transition of the switch element S3 (upper line S4), and the lower part shows the switch element S5. (Overlined S6) and switch element S7 (overlined S8) ON/OFF state transitions are exemplified. Hereinafter, the ON period of the switch element S1 (S2 with the upper line) is also referred to as "duty D1", and the ON period of the switch element S3 (S4 with the upper line) is also referred to as the "duty D3".
 図6(2)の上段および中段の、細破線および一点鎖線のステータス遷移に示されるように、スイッチ素子S1(上線付きS2)のデューティD1が増加(細破線からから一点鎖線)し、スイッチ素子S3(上線付きS4)のデューティD3が減少(細破線から一点鎖線)すると、図6(1)の(a)に示す充電期間が相対的に短くなり、かつ、図6(1)の(b)に示す放電期間が相対的に長くなる。したがって、フライングキャパシタfc1の電圧(VFC1)は減少することになる。 As indicated by the thin dashed line and the one-dot chain line status transition in the upper and middle stages of FIG. When the duty D3 of S3 (S4 with an overlined line) decreases (from the thin dashed line to the dashed line), the charging period shown in (a) of FIG. ) is relatively long. Therefore, the voltage (VFC1) of the flying capacitor fc1 will decrease.
 同様にして、スイッチ素子S1(上線付きS2)のデューティD1が減少(一点鎖線から細破線)し、スイッチ素子S3(上線付きS4)のデューティD3が増加(一点鎖線から細破線)すると、図6(1)の(a)に示す充電期間が相対的に長くなり、かつ、図6(1)の(b)に示す放電期間が相対的に短くなる。したがって、フライングキャパシタfc1の電圧(VFC1)は増加することになる。なお、第1出力回路14のスイッチ素子S5(上線付きS6)、スイッチ素子S7(上線付きS8)のオン/オフ状態は一定のステータスに維持されている。 Similarly, when the duty D1 of the switch element S1 (S2 with the overlined line) decreases (from the dashed line to the thin dashed line) and the duty D3 of the switch element S3 (S4 with the overlined line) increases (from the dashed line to the thin dashed line), FIG. The charging period shown in (1)(a) becomes relatively longer, and the discharging period shown in FIG. 6(1)(b) becomes relatively shorter. Therefore, the voltage (VFC1) of the flying capacitor fc1 increases. The ON/OFF states of the switch element S5 (overlined S6) and the switch element S7 (overlined S8) of the first output circuit 14 are maintained at a constant status.
 本実施例の電力変換部10においては、スイッチ素子S1(上線付きS2)のオン期間であるデューティD1、および、スイッチ素子S3(上線付きS4)のオン期間であるデューティD3の長さを相対的に増加および減少させることでフライングキャパシタfc1の電圧(VFC1)が制御される。 In the power converter 10 of the present embodiment, the duty D1, which is the ON period of the switch element S1 (S2 with the upper line), and the duty D3, which is the ON period of the switch element S3 (S4 with the upper line), are relatively to control the voltage (VFC1) of the flying capacitor fc1.
 図7は、フライングキャパシタfc2の電圧制御を説明する図である。図6(1)と同様にして、図7(1)には、フライングキャパシタfc2における電流経路が太実線の矢印により例示されている。丸囲みされたスイッチ素子はドレイン端子-ソース端子間が導通されたオン状態を表し、図7(1)の(a)に示す電流経路は、フライングキャパシタfc2が充電される場合の電流経路であり、(b)に示す電流経路は、フライングキャパシタfc2が放電される場合の電流経路を表す。電力変換装置1においては、スイッチ素子S9からS12のオン/オフ状態が選択され、フライングキャパシタfc2に流れる電流経路が選択されることで電圧制御が行われる。 FIG. 7 is a diagram for explaining voltage control of the flying capacitor fc2. As in FIG. 6(1), in FIG. 7(1), the current path in the flying capacitor fc2 is illustrated by a thick solid arrow. The circled switch element represents an ON state in which the drain terminal and the source terminal are electrically connected, and the current path shown in (a) of FIG. 7(1) is the current path when the flying capacitor fc2 is charged. , (b) represents the current path when the flying capacitor fc2 is discharged. In the power conversion device 1, voltage control is performed by selecting the ON/OFF states of the switch elements S9 to S12 and selecting the current path flowing through the flying capacitor fc2.
 第2フライングキャパシタ回路13においては、図7(1)の(a)に示すように、スイッチ素子S11のドレイン端子には、オン状態のスイッチ素子S13のドレイン端子-ソース端子を通じて第1直流キャパシタdc1の高電位側が接続される。スイッチ素子S11およびスイッチ素子S10がオン状態の場合には、スイッチ素子S11のドレイン端子-ソース端子→フライングキャパシタfc2→スイッチ素子S10のドレイン端子-ソース端子が導通し、負荷側に向かう電流経路が形成される。フライングキャパシタfc2には、オン状態のスイッチ素子S13のドレイン端子-ソース端子を通じて第1直流キャパシタdc1の高電位側から負荷側に電流が流れ、フライングキャパシタfc2が充電されることになる。 In the second flying capacitor circuit 13, as shown in (a) of FIG. 7(1), the drain terminal of the switch element S11 is connected to the first DC capacitor dc1 through the drain terminal and the source terminal of the switch element S13 in the ON state. is connected to the high potential side of When the switch element S11 and the switch element S10 are in the ON state, the drain terminal-source terminal of the switch element S11→flying capacitor fc2→the drain terminal-source terminal of the switch element S10 are conducted, forming a current path toward the load side. be done. A current flows from the high potential side of the first DC capacitor dc1 to the load side through the drain terminal-source terminal of the ON-state switch element S13, and the flying capacitor fc2 is charged.
 また、第2フライングキャパシタ回路13においては、図7(1)の(b)に示すように、スイッチ素子S12のソース端子には、オン状態のスイッチ素子S15のドレイン端子-ソース端子を通じて第1直流キャパシタdc1の低電位側が接続される。スイッチ素子S12およびスイッチ素子S9がオン状態の場合には、スイッチ素子S12のドレイン端子-ソース端子→フライングキャパシタfc2→スイッチ素子S9のドレイン端子-ソース端子が導通し、負荷側に向かう電流経路が形成される。フライングキャパシタfc2には、オン状態のスイッチ素子S15のドレイン端子-ソース端子を通じて第1直流キャパシタdc1の低電位側から負荷側に電流が流れ、フライングキャパシタfc2が放電されることになる。したがって、図7(1)の(a)、(b)に示すように、スイッチ素子S11およびスイッチ素子S10、スイッチ素子S12およびスイッチ素子S9のオン期間(デューティ)の長さを制御することで、フライングキャパシタfc2の充放電に係る期間が制御でき、フライングキャパシタfc2の電圧制御が可能になる。 In the second flying capacitor circuit 13, as shown in FIG. 7(1)(b), the source terminal of the switch element S12 receives the first direct current through the drain terminal-source terminal of the switch element S15 in the ON state. The low potential side of capacitor dc1 is connected. When the switch element S12 and the switch element S9 are in the ON state, the drain terminal-source terminal of the switch element S12→flying capacitor fc2→drain terminal-source terminal of the switch element S9 are conducted, forming a current path toward the load side. be done. A current flows from the low potential side of the first DC capacitor dc1 to the load side of the flying capacitor fc2 through the drain terminal-source terminal of the ON state switch element S15, and the flying capacitor fc2 is discharged. Therefore, as shown in (a) and (b) of FIG. 7(1), by controlling the length of the ON period (duty) of the switch element S11 and the switch element S10, the switch element S12 and the switch element S9, The period for charging and discharging the flying capacitor fc2 can be controlled, and the voltage of the flying capacitor fc2 can be controlled.
 図7(2)には、フライングキャパシタfc2の電圧制御に係る各スイッチ素子の相対的なタイミングチャートが例示される。図7(2)の縦軸は各スイッチ素子の2値(オン/オフ)のステータスを表し、横軸は時間の経過を表す。なお、第2フライングキャパシタ回路13においても、スイッチ素子S9およびS10のオン状態およびオフ状態が、一対で相補的に制御される。スイッチ素子S9がオン状態のときには、スイッチ素子S10はオフ状態に制御される。第2フライングキャパシタ回路13のスイッチ素子S11およびS12、第2出力回路15のスイッチ素子S13およびS14、スイッチ素子S15およびS16も同様である。 FIG. 7(2) illustrates a relative timing chart of each switch element related to voltage control of the flying capacitor fc2. The vertical axis of FIG. 7(2) represents the binary (on/off) status of each switch element, and the horizontal axis represents the passage of time. Also in the second flying capacitor circuit 13, the on-state and off-state of the switch elements S9 and S10 are complementarily controlled as a pair. When the switch element S9 is on, the switch element S10 is controlled to be off. The same applies to switch elements S11 and S12 of the second flying capacitor circuit 13, switch elements S13 and S14 of the second output circuit 15, and switch elements S15 and S16.
 図7(2)の上段にはスイッチ素子S9(上線付きS10)のオン/オフ状態の遷移、中段にはスイッチ素子S11(上線付きS12)のオン/オフ状態の遷移、下段にはスイッチ素子S13(上線付きS14)およびスイッチ素子S15(上線付きS16)のオン/オフ状態の遷移が例示される。以下、スイッチ素子S9(上線付きS10)のオン期間を“デューティD9”、スイッチ素子S11(上線付きS12)のオン期間を“デューティD11”とも言う。 The upper part of FIG. 7B shows the on/off state transition of the switch element S9 (upper line S10), the middle part shows the on/off state transition of the switch element S11 (upper line S12), and the lower part shows the switch element S13. (Overlined S14) and switch element S15 (overlined S16) ON/OFF state transitions are exemplified. Hereinafter, the ON period of the switch element S9 (S10 with the upper line) is also referred to as "duty D9", and the ON period of the switch element S11 (S12 with the upper line) is also referred to as the "duty D11".
 図7(2)の上段および中段の、細破線および一点鎖線のステータス遷移に示されるように、スイッチ素子S9(上線付きS10)のデューティD9が増加(細破線から一点鎖線)し、スイッチ素子S11(上線付きS12)のデューティD11が減少(細破線から一点鎖線)すると、図7(1)の(a)に示す充電期間が短くなり、かつ、図7(1)の(b)に示す放電期間が長くなる。したがって、フライングキャパシタfc2の電圧(VFC2)は減少することになる。 As indicated by the thin dashed line and the alternate long and short dash line status transitions in the upper and middle stages of FIG. When the duty D11 of (S12 with an overlined line) decreases (from the thin dashed line to the dashed line), the charging period shown in (a) of FIG. 7(1) shortens, and the discharging period shown in (b) of FIG. 7(1) period is longer. Therefore, the voltage (VFC2) of the flying capacitor fc2 will decrease.
 同様にして、スイッチ素子S9(上線付きS10)のデューティD9が減少(一点鎖線から細破線)しスイッチ素子S11(上線付きS12)のデューティD11が増加(一点鎖線から細破線)すると、図7(1)の(a)に示す充電期間が長くなり、かつ、図7(1)の(b)に示す放電期間が相対的に短くなる。したがって、フライングキャパシタfc1の電圧(VFC1)は増加することになる。なお、第2出力回路15のスイッチ素子S13(上線付きS14)、スイッチ素子S15(上線付きS16)のオン/オフ状態は一定のステータスに維持されている。 Similarly, when the duty D9 of the switch element S9 (S10 with the overlined line) decreases (from the dashed line to the thin dashed line) and the duty D11 of the switch element S11 (S12 with the overlined line) increases (from the dashed line to the thin dashed line), FIG. 1) The charging period shown in (a) of FIG. 7 becomes longer, and the discharging period shown in (b) of FIG. 7(1) becomes relatively shorter. Therefore, the voltage (VFC1) of the flying capacitor fc1 increases. The ON/OFF states of the switch element S13 (overlined S14) and the switch element S15 (overlined S16) of the second output circuit 15 are maintained at a constant status.
 本実施例の電力変換部10においては、スイッチ素子S9(上線付きS10)のオン期間であるデューティD9、および、スイッチ素子S11(上線付きS12)のオン期間であるデューティD11の長さを相対的に増加および減少させることでフライングキャパシタfc2の電圧(VFC2)が制御される。 In the power converter 10 of the present embodiment, the duty D9, which is the ON period of the switch element S9 (S10 with the upper line), and the duty D11, which is the ON period of the switch element S11 (S12 with the upper line), are relatively to control the voltage (VFC2) of the flying capacitor fc2.
 図8、図9は、第1直流キャパシタdc1および第2直流キャパシタdc2の電圧制御を説明する図である。図8においても、(1)には、フライングキャパシタfc1における電流経路が太実線の矢印により例示されている。丸囲みされたスイッチ素子はドレイン端子-ソース端子間が導通されたオン状態を表す。図8(1)の(a)には、第1フライングキャパシタ回路12のオン状態のスイッチ素子S3を通じて負荷側に向かう電流経路が例示される。すなわち、第1直流キャパシタdc1の高電位側に接続されたオン状態のスイッチ素子S5、スイッチ素子S3、スイッチ素子S1の各ドレイン端子-ソース端子を通じて負荷側に向かう電流経路が形成される。スイッチ素子S1のソース端子から負荷側に向かう電流経路は、当該負荷を経由して、第2直流キャパシタdc2の低電位側に流れるように形成される。 8 and 9 are diagrams for explaining voltage control of the first DC capacitor dc1 and the second DC capacitor dc2. In FIG. 8, (1) also illustrates the current path in the flying capacitor fc1 by a thick solid arrow. A switch element surrounded by a circle represents an ON state in which the drain terminal and the source terminal are electrically connected. FIG. 8(1)(a) illustrates a current path toward the load through the ON-state switch element S3 of the first flying capacitor circuit 12. FIG. That is, a current path toward the load side is formed through each of the drain and source terminals of the switch element S5, switch element S3, and switch element S1 that are in the ON state and connected to the high potential side of the first DC capacitor dc1. A current path from the source terminal of the switch element S1 to the load side is formed to flow to the low potential side of the second DC capacitor dc2 via the load.
 図8(1)の(b)には、第1フライングキャパシタ回路12のスイッチ素子S3がオフ状態における負荷側に向かう電流経路が例示される。すなわち、第2直流キャパシタdc2の高電位側に接続されたオン状態のスイッチ素子S7のドレイン端子-ソース端子→スイッチ素子S4のドレイン端子-ソース端子→フライングキャパシタfc1→スイッチ素子S1の各ドレイン端子-ソース端子が導通し、負荷側に向かう電流経路が形成される。スイッチ素子S1のソース端子から負荷側に向かう電流経路は、当該負荷を経由して、第2直流キャパシタdc2の低電位側に流れるように形成される。したがって、電流経路上の第2直流キャパシタdc2、フライングキャパシタfc1が放電される。なお、図6で説明したように、第1フライングキャパシタ回路12のスイッチ素子S3のオフ状態におけるフライングキャパシタfc1の放電は、フライングキャパシタfc1の電圧制御に影響することになる。 (b) of FIG. 8(1) illustrates a current path toward the load side when the switch element S3 of the first flying capacitor circuit 12 is in the OFF state. That is, the drain terminal-source terminal of the ON state switch element S7 connected to the high potential side of the second DC capacitor dc2→drain terminal-source terminal of the switch element S4→flying capacitor fc1→each drain terminal of the switch element S1− The source terminal conducts, forming a current path toward the load side. A current path from the source terminal of the switch element S1 to the load side is formed to flow to the low potential side of the second DC capacitor dc2 via the load. Therefore, the second DC capacitor dc2 and the flying capacitor fc1 on the current path are discharged. As described with reference to FIG. 6, the discharge of the flying capacitor fc1 in the OFF state of the switching element S3 of the first flying capacitor circuit 12 affects the voltage control of the flying capacitor fc1.
 図8(2)には、フライングキャパシタfc1の電圧制御に係る各スイッチ素子の相対的なタイミングチャートが例示される。なお、図8(2)の縦軸は各スイッチ素子の2値(オン/オフ)のステータスを表し、横軸は時間の経過を表し、図6と同様に、フライングキャパシタ回路12のスイッチ素子S1およびS2、スイッチ素子S3およびS4のオン状態およびオフ状態は、一対で相補的に制御される。第1出力回路14のスイッチ素子S5およびS6、スイッチ素子S7およびS8も同様である。 FIG. 8(2) illustrates a relative timing chart of each switch element related to voltage control of the flying capacitor fc1. The vertical axis in FIG. 8(2) represents the binary (on/off) status of each switch element, and the horizontal axis represents the passage of time. and S2, and the ON and OFF states of switch elements S3 and S4 are complementarily controlled as a pair. The same applies to switch elements S5 and S6 and switch elements S7 and S8 of the first output circuit 14. FIG.
 図8(2)においても、上段にはスイッチ素子S1(上線付きS2)のオン/オフ状態の遷移、中段にはスイッチ素子S3(上線付きS4)のオン/オフ状態の遷移、下段にはスイッチ素子S5(上線付きS6)およびスイッチ素子S7(上線付きS8)のオン/オフ状態の遷移が例示される。図8(2)において、デューティD3はスイッチ素子S3(上線付きS4)のオン期間をあらわす。 In FIG. 8(2) as well, the upper stage shows the on/off state transition of the switch element S1 (overlined S2), the middle stage shows the on/off state transition of the switch element S3 (overlined S4), and the lower stage shows the switch The ON/OFF state transitions of element S5 (overlined S6) and switch element S7 (overlined S8) are exemplified. In FIG. 8(2), the duty D3 represents the ON period of the switch element S3 (S4 with an overlined line).
 図8(2)の中段の細破線および一点鎖線のステータス遷移に示されるように、スイッチ素子S3(上線付きS4)のデューティD3が減少(細破線から一点鎖線)すると、図8(1)の(b)に示す放電期間が相対的に長くなる。すなわち、第2直流キャパシタdc2の放電期間が長くなるため、第2直流キャパシタdc2の電圧(Vdc2)は減少し、第1直流キャパシタdc1の電圧(Vdc1)は増加することになる。 As indicated by the thin dashed line and dashed line status transition in the middle of FIG. The discharge period shown in (b) becomes relatively long. That is, since the discharge period of the second DC capacitor dc2 becomes longer, the voltage (Vdc2) of the second DC capacitor dc2 decreases and the voltage (Vdc1) of the first DC capacitor dc1 increases.
 同様にして、スイッチ素子S3(上線付きS4)のデューティD3が増加(一点鎖線から細破線)すると、図8(1)の(b)に示す放電期間が相対的に短くなる。すなわち、第2直流キャパシタdc2の放電期間が短くなるため、第2直流キャパシタdc2の電圧(Vdc2)は増加し、第1直流キャパシタdc1の電圧(Vdc1)は減少することになる。つまり、スイッチ素子S3(上線付きS4)のオン期間であるデューティD3の長さを相対的に増加および減少させることで第2直流キャパシタdc2の電圧(Vdc2)および第1直流キャパシタdc1の電圧(Vdc1)が制御可能になる。 Similarly, when the duty D3 of the switch element S3 (S4 with an overlined line) increases (from the dashed-dotted line to the thin dashed line), the discharge period shown in (b) of FIG. 8(1) becomes relatively shorter. That is, since the discharge period of the second DC capacitor dc2 is shortened, the voltage (Vdc2) of the second DC capacitor dc2 increases and the voltage (Vdc1) of the first DC capacitor dc1 decreases. That is, the voltage (Vdc2) of the second DC capacitor dc2 and the voltage (Vdc1 ) becomes controllable.
 次に、図9を説明する。図9の(1)には、フライングキャパシタfc2における電流経路が太実線の矢印により例示されている。丸囲みされたスイッチ素子はドレイン端子-ソース端子間が導通されたオン状態を表す。図9(1)の(a)には、第2フライングキャパシタ回路13のオン状態のスイッチ素子S11を通じて負荷側に向かう電流経路が例示される。すなわち、第1直流キャパシタdc1の高電位側に接続されたオン状態のスイッチ素子S13、スイッチ素子S11、スイッチ素子S9の各ドレイン端子-ソース端子を通じて負荷側に向かう電流経路が形成される。スイッチ素子S9のソース端子から負荷側に向かう電流経路は、当該負荷を経由して、第2直流キャパシタdc2の低電位側に流れるように形成される。 Next, FIG. 9 will be explained. In (1) of FIG. 9, the current path in the flying capacitor fc2 is illustrated by a thick solid arrow. A switch element surrounded by a circle represents an ON state in which the drain terminal and the source terminal are electrically connected. (a) of FIG. 9(1) illustrates a current path toward the load through the switch element S11 in the ON state of the second flying capacitor circuit 13 . That is, a current path toward the load side is formed through each of the drain terminals and the source terminals of the ON-state switch elements S13, S11, and S9 connected to the high potential side of the first DC capacitor dc1. A current path from the source terminal of the switch element S9 to the load side is formed to flow to the low potential side of the second DC capacitor dc2 via the load.
 図9(1)の(b)には、第2フライングキャパシタ回路13のスイッチ素子S11がオフ状態における負荷側に向かう電流経路が例示される。すなわち、第2直流キャパシタdc2の高電位側に接続されたオン状態のスイッチ素子S15のドレイン端子-ソース端子→スイッチ素子S12のドレイン端子-ソース端子→フライングキャパシタfc2→スイッチ素子S9の各ドレイン端子-ソース端子が導通し、負荷側に向かう電流経路が形成される。スイッチ素子S9のソース端子から負荷側に向かう電流経路は、当該負荷を経由して、第2直流キャパシタdc2の低電位側に流れるように形成される。したがって、電流経路上の第2直流キャパシタdc2、フライングキャパシタfc2が放電される。ここで、図7で説明したように、第2フライングキャパシタ回路13のスイッチ素子S11のオフ状態におけるフライングキャパシタfc2の放電は、フライングキャパシタfc2の電圧制御に影響することになる。 (b) of FIG. 9(1) illustrates a current path toward the load side when the switch element S11 of the second flying capacitor circuit 13 is in the OFF state. That is, the drain terminal-source terminal of the ON state switch element S15 connected to the high potential side of the second DC capacitor dc2→drain terminal-source terminal of the switch element S12→flying capacitor fc2→each drain terminal of the switch element S9− The source terminal conducts, forming a current path toward the load side. A current path from the source terminal of the switch element S9 to the load side is formed to flow to the low potential side of the second DC capacitor dc2 via the load. Therefore, the second DC capacitor dc2 and the flying capacitor fc2 on the current path are discharged. Here, as described with reference to FIG. 7, the discharge of the flying capacitor fc2 in the OFF state of the switch element S11 of the second flying capacitor circuit 13 affects the voltage control of the flying capacitor fc2.
 図9(2)には、フライングキャパシタfc2の電圧制御に係る各スイッチ素子の相対的なタイミングチャートが例示される。なお、図9(2)の縦軸は各スイッチ素子の2値(オン/オフ)のステータスを表し、横軸は時間の経過を表し、図7と同様に、フライングキャパシタ回路13のスイッチ素子S9およびS10、スイッチ素子S11およびS12のオン状態およびオフ状態は、一対で相補的に制御される。第2出力回路15のスイッチ素子S13およびS14、スイッチ素子S15およびS16も同様である。 FIG. 9(2) illustrates a relative timing chart of each switch element related to voltage control of the flying capacitor fc2. The vertical axis in FIG. 9(2) represents the binary (on/off) status of each switch element, and the horizontal axis represents the passage of time. and S10, and the ON and OFF states of switch elements S11 and S12 are complementarily controlled as a pair. The switch elements S13 and S14 and the switch elements S15 and S16 of the second output circuit 15 are the same.
 図9(2)においても、上段にはスイッチ素子S9(上線付きS10)のオン/オフ状態の遷移、中段にはスイッチ素子S11(上線付きS12)のオン/オフ状態の遷移、下段にはスイッチ素子S13(上線付きS14)およびスイッチ素子S15(上線付きS16)のオン/オフ状態の遷移が例示される。図9(2)において、デューティD11はスイッチ素子S11(上線付きS12)のオン期間をあらわす。 In FIG. 9(2) as well, the upper stage shows the on/off state transition of the switch element S9 (overlined S10), the middle stage shows the on/off state transition of the switch element S11 (overlined S12), and the lower stage shows the switch The on/off state transitions of element S13 (overlined S14) and switch element S15 (overlined S16) are exemplified. In FIG. 9(2), the duty D11 represents the ON period of the switch element S11 (S12 with an overlined line).
 図9(2)の中段の細破線および一点鎖線のステータス遷移に示されるように、スイッチ素子S11(上線付きS12)のデューティD11が減少(細破線から一点鎖線)すると、図9(1)の(b)に示す放電期間が長くなる。すなわち、第2直流キャパシタdc2の放電期間が長くなるため、第2直流キャパシタdc2の電圧(Vdc2)は減少し、第1直流キャパシタdc1の電圧(Vdc1)は増加することになる。 As indicated by the thin dashed line and the dashed-dotted line status transition in the middle of FIG. The discharge period shown in (b) is lengthened. That is, since the discharge period of the second DC capacitor dc2 becomes longer, the voltage (Vdc2) of the second DC capacitor dc2 decreases and the voltage (Vdc1) of the first DC capacitor dc1 increases.
 また、スイッチ素子S11(上線付きS12)のデューティD11が増加(一点鎖線から細破線)すると、図9(1)の(b)に示す放電期間が短くなる。すなわち、第2直流キャパシタdc2の放電期間が短くなるため、第2直流キャパシタdc2の電圧(Vdc2)は増加し、第1直流キャパシタdc1の電圧(Vdc1)は減少することになる。図9においても、スイッチ素子S11(上線付きS12)のオン期間であるデューティD11の長さを相対的に増加および減少させることで第2直流キャパシタdc2の電圧(Vdc2)および第1直流キャパシタdc1の電圧(Vdc1)が制御可能になる。 Also, when the duty D11 of the switch element S11 (S12 with an overlined line) increases (from the dashed-dotted line to the thin dashed line), the discharge period shown in (b) of FIG. 9(1) is shortened. That is, since the discharge period of the second DC capacitor dc2 is shortened, the voltage (Vdc2) of the second DC capacitor dc2 increases and the voltage (Vdc1) of the first DC capacitor dc1 decreases. In FIG. 9 as well, the voltage (Vdc2) of the second DC capacitor dc2 and the voltage of the first DC capacitor dc1 are increased and decreased by relatively increasing and decreasing the length of the duty D11, which is the ON period of the switch element S11 (S12 with an upper line). The voltage (Vdc1) becomes controllable.
 図8および図9で説明したように、スイッチ素子S3のデューティD3またはスイッチ素子S11のデューティD11の何れか一方を制御することで、第1直流キャパシタdc1の電圧(Vdc1)および第2直流キャパシタdc2の電圧(Vdc2)が相対的に制御できる。また、図6および図7で説明したように、スイッチ素子S3のデューティD3はフライングキャパシタfc1の電圧制御に影響し、スイッチ素子S11のデューティD11はフライングキャパシタfc2の電圧制御に影響する。したがって、本実施例に係る電力変換装置1においては、フライングキャパシタfc1の制御電圧(VFC1)とフライングキャパシタfc2の制御電圧(VFC2)に基づいて、第1直流キャパシタdc1の電圧(Vdc1)および第2直流キャパシタdc2の電圧(Vdc2)の制御対象になるスイッチ素子を決定する。本実施例においては、決定されたスイッチ素子のデューティの期間の長さを増加または減少させ、第1直流キャパシタdc1の電圧(Vdc1)および第2直流キャパシタdc2の電圧(Vdc2)の増加または減少が制御される。 8 and 9, by controlling either the duty D3 of the switch element S3 or the duty D11 of the switch element S11, the voltage (Vdc1) of the first DC capacitor dc1 and the second DC capacitor dc2 voltage (Vdc2) can be relatively controlled. 6 and 7, the duty D3 of the switching element S3 influences the voltage control of the flying capacitor fc1, and the duty D11 of the switching element S11 influences the voltage control of the flying capacitor fc2. Therefore, in the power converter 1 according to the present embodiment, based on the control voltage (VFC1) of the flying capacitor fc1 and the control voltage (VFC2) of the flying capacitor fc2, the voltage (Vdc1) of the first DC capacitor dc1 and the second A switch element to be controlled for the voltage (Vdc2) of the DC capacitor dc2 is determined. In this embodiment, the length of the determined duty period of the switch element is increased or decreased, and the voltage (Vdc1) of the first DC capacitor dc1 and the voltage (Vdc2) of the second DC capacitor dc2 are increased or decreased. controlled.
 <制御部構成>
 図10は、本実施例に係る電力変換装置1の制御部30のハードウェア構成の一例を示す図である。図10に示すように、制御部30は、接続バス106によって相互に接続されたプロセッサ101、主記憶装置102、補助記憶装置103、通信IF104、入出力IF105を構成要素に含むコンピュータである。主記憶装置102および補助記憶装置103は、制御部30が読み取り可能な記録媒体である。上記の構成要素はそれぞれ複数に設けられてもよいし、一部の構成要素を設けないようにしてもよい。
<Control unit configuration>
FIG. 10 is a diagram showing an example of the hardware configuration of the control unit 30 of the power converter 1 according to this embodiment. As shown in FIG. 10, the control unit 30 is a computer including, as constituent elements, a processor 101, a main storage device 102, an auxiliary storage device 103, a communication IF 104, and an input/output IF 105, which are interconnected by a connection bus . The main storage device 102 and the auxiliary storage device 103 are recording media readable by the control unit 30 . A plurality of the above components may be provided, or some of the components may be omitted.
 プロセッサ101は、制御部30全体の制御を行う中央処理演算装置である。プロセッサ101は、例えば、CPU(Central Processing Unit)やMPU(Micro-Processing Unit)、DSP(Digital Signal Processor)等である。プロセッサ101は、例えば、補助記憶装置103に記憶されたプログラムを主記憶装置102の作業領域に実行可能に展開し、当該プログラムの実行を通じて周辺機器の制御を行うことで所定の目的に合致した機能を提供する。但し、プロセッサ101が提供する一部または全部の機能が、ASIC(Application Specific Integrated Circuit)、GPU(Graphics Processing Unit)等によって提供されてもよい。同様にして、一部または全部の機能が、FPGA(Field-Programmable Gate Array)、数値演算プロセッサ等の専用LSI(large scale integration)、その他のハードウェア回路で実現されてもよい。 The processor 101 is a central processing unit that controls the control unit 30 as a whole. The processor 101 is, for example, a CPU (Central Processing Unit), an MPU (Micro-Processing Unit), a DSP (Digital Signal Processor), or the like. The processor 101, for example, develops a program stored in the auxiliary storage device 103 in a work area of the main storage device 102 so that it can be executed, and controls peripheral devices through execution of the program to perform a function that meets a predetermined purpose. I will provide a. However, some or all of the functions provided by the processor 101 may be provided by an ASIC (Application Specific Integrated Circuit), a GPU (Graphics Processing Unit), or the like. Similarly, some or all of the functions may be implemented by FPGAs (Field-Programmable Gate Arrays), dedicated LSIs (large scale integration) such as numerical processors, and other hardware circuits.
 主記憶装置102および補助記憶装置103は、制御部30のメモリを構成する。主記憶装置102は、プロセッサ101が実行するプログラム、当該プロセッサが処理するデータ等を記憶する。主記憶装置102は、フラッシュメモリ、RAM(Random Access Memory)やROM(Read Only Memory)を含む。補助記憶装置103は、プロセッサ101等により実行されるプログラムや、動作の設定情報などを記憶する記憶媒体である。補助記憶装置103は、例えば、HDD(Hard-disk Drive)やSSD(Solid State Drive)、EPROM(Erasable Programmable ROM)、フラッシュメモリ、USBメモリ、SD(Secure Digital)メモリカード等を含む。通信IF104は通信インタフェースである。通信IF104は、接続される機器との接続方式に応じて適宜の構成を採用できる。本実施例においては、通信IF104を介して接続された電力変換部10との間における各種の制御指令が通知される。さらに、本実施例においては、通信IF104を通じて接続された電力変換装置1の各部に設けられた各種のセンサの出力信号が取得される。入出力IF105は、電力変換装置1の備える入力デバイス、出力デバイスとの間でデータの入出力を行うインタフェースである。入出力IF105を通じて、LCD等の表示デバイスに出力される。また、入出力IF105を通じて、操作指示が受け付けられ、当該操作指示に基づいて操作者の意図する処理が行われる。 The main storage device 102 and the auxiliary storage device 103 constitute the memory of the control unit 30 . The main storage device 102 stores programs executed by the processor 101, data processed by the processor, and the like. The main storage device 102 includes flash memory, RAM (Random Access Memory), and ROM (Read Only Memory). The auxiliary storage device 103 is a storage medium that stores programs to be executed by the processor 101 or the like, operation setting information, and the like. The auxiliary storage device 103 includes, for example, a HDD (Hard-disk Drive), SSD (Solid State Drive), EPROM (Erasable Programmable ROM), flash memory, USB memory, SD (Secure Digital) memory card, and the like. Communication IF 104 is a communication interface. The communication IF 104 can adopt an appropriate configuration according to the connection method with the device to be connected. In this embodiment, various control commands to and from the power converter 10 connected via the communication IF 104 are notified. Furthermore, in the present embodiment, output signals of various sensors provided in each part of the power converter 1 connected through the communication IF 104 are acquired. The input/output IF 105 is an interface for inputting/outputting data between an input device and an output device provided in the power converter 1 . It is output to a display device such as an LCD through the input/output IF 105 . Further, an operation instruction is received through the input/output IF 105, and processing intended by the operator is performed based on the operation instruction.
<処理の流れ>
 図11から図14は、本実施例に係る電力変換装置1で提供される電圧制御処理の一例を示すフローチャートである。図11から図14の処理により、連動するフライングキャパシタfc1およびfc2、第1直流キャパシタdc1および第2直流キャパシタdc2の電圧安定化が図られる。本実施例に係る電圧制御処理は、図11から図14に示すように、負荷50側に出力される交流電力の出力電圧(vo;キャパシタ20cの印加電圧)の極性と出力電流(io)との極性との相対関係に応じて処理が行われる。負荷50側に出力される交流電力の出力電圧(vo)と出力電流(io)との相対的な位相領域(時間軸上の領域)は、それぞれの位相上における極性の組合せに応じて第1領域から第4領域に区分けされる。第1領域は、例えば、出力電圧の極性が正側であり出力電流の極性が正側である位相の領域として区分けされる。同様にして、第2領域は、例えば、出力電圧の極性が負側であり出力電流の極性が負側である位相の領域として区分けされる。また、出力電圧の極性が正側であり出力電流の極性が負側となる位相の領域は第3領域として区分けされ、出力電圧の極性が負側であり出力電流の極性が正側となる位相の領域は第4領域として区分けされる。本実施例に係る電力変換装置1においては、第1領域から第4領域に区分けされた負荷50側に出力される交流電力の出力電圧(vo)と出力電流(io)との相対位相の領域に応じて電圧制御処理を行うことで、電圧変換処理の安定性を向上させ、交流電力の精度を高めることができる。
<Process flow>
11 to 14 are flowcharts showing an example of voltage control processing provided by the power converter 1 according to this embodiment. 11 to 14, the voltages of the interlocked flying capacitors fc1 and fc2, the first DC capacitor dc1 and the second DC capacitor dc2 are stabilized. As shown in FIGS. 11 to 14, the voltage control process according to the present embodiment is based on the polarity of the output voltage (vo; voltage applied to the capacitor 20c) of the AC power output to the load 50, the output current (io), and the output current (io). The processing is performed according to the relative relationship with the polarity of . The relative phase region (region on the time axis) between the output voltage (vo) and the output current (io) of the AC power output to the load 50 side is the first The area is divided into a fourth area. The first region is, for example, classified as a phase region in which the polarity of the output voltage is on the positive side and the polarity of the output current is on the positive side. Similarly, the second region is classified as a phase region in which, for example, the polarity of the output voltage is negative and the polarity of the output current is negative. Further, the phase region in which the polarity of the output voltage is positive and the polarity of the output current is negative is classified as a third region, and the phase in which the polarity of the output voltage is negative and the polarity of the output current is positive is classified as the fourth area. In the power conversion device 1 according to the present embodiment, the relative phase region between the output voltage (vo) and the output current (io) of the AC power output to the load 50 side divided into the first region to the fourth region By performing the voltage control process according to , it is possible to improve the stability of the voltage conversion process and improve the accuracy of the AC power.
(第1領域)
 図11は、第1領域における電圧制御処理の一例を示すフローチャートである。図11の破線吹き出し領域Z1には、本フローの制御対象になる出力電圧(vo)と出力電流(io)との相対位相領域がハッチングされた矩形領域に例示される。図11のフローにおいて、電圧制御処理の開始後、電力変換部10のフライングキャパシタfc1の電圧値が一定値(E)であるかが判定される(ステップS101)。電力変換装置1の制御部30は、第1フライングキャパシタ回路12に設けられた電圧センサを通じてフライングキャパシタfc1の電圧値(VFC1)を取得する。ステップS101において、フライングキャパシタfc1の電圧値(VFC1)が一定値(E)を超える場合には(ステップS101、“>E”)、処理はステップS102に進み、一定値(E)未満の場合には(ステップS101、“<E”)、処理はステップS103に進む。ステップS101において、フライングキャパシタfc1の電圧値(VFC1)が一定値(E)の場合には(ステップS101、“=E”)、処理はステップS104に進む。
(First area)
FIG. 11 is a flowchart showing an example of voltage control processing in the first region. In the broken-line balloon area Z1 in FIG. 11, the relative phase area between the output voltage (vo) and the output current (io) to be controlled in this flow is illustrated as a hatched rectangular area. In the flow of FIG. 11, after starting the voltage control process, it is determined whether the voltage value of the flying capacitor fc1 of the power conversion unit 10 is a constant value (E) (step S101). The control unit 30 of the power converter 1 acquires the voltage value (VFC1) of the flying capacitor fc1 through the voltage sensor provided in the first flying capacitor circuit 12 . In step S101, if the voltage value (VFC1) of the flying capacitor fc1 exceeds the constant value (E) (step S101, ">E"), the process proceeds to step S102, and if it is less than the constant value (E) (step S101, "<E"), the process proceeds to step S103. In step S101, when the voltage value (VFC1) of the flying capacitor fc1 is a constant value (E) (step S101, "=E"), the process proceeds to step S104.
 ステップS102においては、フライングキャパシタfc1の電圧値(VFC1)が一定値(E)になるように、第1フライングキャパシタ回路12のスイッチング制御が行われる。具体的には、図6で説明したように、スイッチ素子S1(上線付きS2)のオン/オフ期間で特定される“デューティD1”の長さを増加させ、スイッチ素子S3(上線付きS4)のオン/オフ期間で特定される“デューティD3”の長さを減少させる。このようなスイッチング制御により、フライングキャパシタfc1の放電期間が相対的に長くなり、フライングキャパシタfc1の電圧値(VFC1)が一定値(E)になるように減少する。ステップS102の処理後、処理はステップS104に進む。 In step S102, switching control of the first flying capacitor circuit 12 is performed so that the voltage value (VFC1) of the flying capacitor fc1 becomes a constant value (E). Specifically, as described with reference to FIG. 6, the length of the "duty D1" specified by the on/off period of the switch element S1 (overlined S2) is increased, and the length of the switch element S3 (overlined S4) is increased. Decrease the length of "duty D3" specified by the ON/OFF period. With such switching control, the discharge period of the flying capacitor fc1 becomes relatively long, and the voltage value (VFC1) of the flying capacitor fc1 decreases to a constant value (E). After the process of step S102, the process proceeds to step S104.
 ステップS103においても、フライングキャパシタfc1の電圧値(VFC1)が一定値(E)になるように、第1フライングキャパシタ回路12のスイッチング制御が行われる。具体的には、図6で説明したように、スイッチ素子S1(上線付きS2)のオン/オフ期間で特定される“デューティD1”の長さを減少させ、スイッチ素子S3(上線付きS4)のオン/オフ期間で特定される“デューティD3”の長さを増加させる。このようなスイッチング制御により、フライングキャパシタfc1の放電期間が相対的に短くなり、フライングキャパシタfc1の電圧値(VFC1)が一定値(E)になるように増加する。ステップS103の処理後、処理はステップS104に進む。 Also in step S103, switching control of the first flying capacitor circuit 12 is performed so that the voltage value (VFC1) of the flying capacitor fc1 becomes a constant value (E). Specifically, as described with reference to FIG. 6, the length of the "duty D1" specified by the ON/OFF period of the switch element S1 (S2 with the overlined line) is reduced, and the length of the "duty D1" of the switch element S3 (S4 with the overlined line) is Increase the length of "duty D3" specified by the ON/OFF period. Through such switching control, the discharge period of the flying capacitor fc1 becomes relatively short, and the voltage value (VFC1) of the flying capacitor fc1 increases to a constant value (E). After the process of step S103, the process proceeds to step S104.
 ステップS104では、フライングキャパシタfc2を対象として電圧値が一定値(E)であるかが判定される。ステップS101と同様にして、第2フライングキャパシタ回路13に設けられた電圧センサを通じてフライングキャパシタfc2の電圧値(VFC2)が取得される。そして、フライングキャパシタfc2の電圧値(VFC2)が一定値(E)を超える場合には(ステップS104、“>E”)、処理はステップS105に進み、一定値(E)未満の場合には(ステップS104、“<E”)、処理はステップS106に進む。ステップS104において、フライングキャパシタfc2の電圧値(VFC2)が一定値(E)の場合には(ステップS104、“=E”)、処理はステップS107に進む。 In step S104, it is determined whether the voltage value of the flying capacitor fc2 is a constant value (E). Similarly to step S101, the voltage value (VFC2) of the flying capacitor fc2 is acquired through the voltage sensor provided in the second flying capacitor circuit 13. FIG. Then, when the voltage value (VFC2) of the flying capacitor fc2 exceeds the constant value (E) (step S104, ">E"), the process proceeds to step S105, and when it is less than the constant value (E) ( Step S104, "<E"), and the process proceeds to step S106. In step S104, when the voltage value (VFC2) of the flying capacitor fc2 is a constant value (E) (step S104, "=E"), the process proceeds to step S107.
 ステップS105においては、フライングキャパシタfc2の電圧値(VFC2)が一定値(E)になるように、第2フライングキャパシタ回路13のスイッチング制御が行われる。具体的には、スイッチ素子S9(上線付きS10)のオン期間で特定される“デューティD9”の長さを減少させ、スイッチ素子S11(上線付きS12)のオン期間で特定される“デューティD11”の長さを増加させる。つまり、第1領域では電流の極性が正側であるため、図7で説明した充放電の関係は反対になる。このようなスイッチング制御により、フライングキャパシタfc2の放電期間が相対的に長くなり、フライングキャパシタfc2の電圧値(VFC2)が一定値(E)になるように減少する。ステップS105の処理後、処理はステップS107に進む。 In step S105, switching control of the second flying capacitor circuit 13 is performed so that the voltage value (VFC2) of the flying capacitor fc2 becomes a constant value (E). Specifically, the length of the "duty D9" specified by the ON period of the switch element S9 (overlined S10) is reduced, and the "duty D11" specified by the ON period of the switch element S11 (overlined S12) is reduced. increase the length of That is, since the polarity of the current is positive in the first region, the charge/discharge relationship described with reference to FIG. 7 is reversed. By such switching control, the discharge period of the flying capacitor fc2 becomes relatively long, and the voltage value (VFC2) of the flying capacitor fc2 decreases to a constant value (E). After the process of step S105, the process proceeds to step S107.
 ステップS106においても、フライングキャパシタfc2の電圧値(VFC2)が一定値(E)になるように、第2フライングキャパシタ回路13のスイッチング制御が行われる。具体的には、スイッチ素子S9(上線付きS10)のオン期間で特定される“デューティD9”の長さを増加させ、スイッチ素子S11(上線付きS12)のオン期間で特定される“デューティD11”の長さを減少させる。このようなスイッチング制御により、フライングキャパシタfc2の放電期間が相対的に短くなり、フライングキャパシタfc2の電圧値(VFC2)が一定値(E)になるように増加する。ステップS106の処理後、処理はステップS107に進む。 Also in step S106, switching control of the second flying capacitor circuit 13 is performed so that the voltage value (VFC2) of the flying capacitor fc2 becomes a constant value (E). Specifically, the length of the "duty D9" specified by the ON period of the switch element S9 (S10 with the overlined line) is increased, and the "duty D11" specified by the ON period of the switch element S11 (S12 with the overlined line) is increased. decrease the length of By such switching control, the discharge period of the flying capacitor fc2 becomes relatively short, and the voltage value (VFC2) of the flying capacitor fc2 increases to a constant value (E). After the process of step S106, the process proceeds to step S107.
 ステップS107では、フライングキャパシタfc1の電圧(VFC1)とフライングキャパシタfc2の電圧(VFC2)に基づいて、第1直流キャパシタdc1の電圧(VDC1)および第2直流キャパシタdc2の電圧(VDC2)を連動して制御するために操作されるスイッチ素子が判定される。具体的には、5レベルの電位(4E、2E、0、-2E、-4E)を用いて交流電力を生成する正弦波の電圧指令値、および、当該電圧指令値に対する各フライングキャパシタ電圧値の偏差に応じて制御対象のスイッチ素子が判定される。 In step S107, based on the voltage (VFC1) of the flying capacitor fc1 and the voltage (VFC2) of the flying capacitor fc2, the voltage (VDC1) of the first DC capacitor dc1 and the voltage (VDC2) of the second DC capacitor dc2 are interlocked. A switch element to be manipulated to control is determined. Specifically, a sine wave voltage command value that generates AC power using five levels of potential (4E, 2E, 0, −2E, −4E), and each flying capacitor voltage value for the voltage command value A switch element to be controlled is determined according to the deviation.
 ステップS107において、制御部30は、フライングキャパシタfc1に対する電圧指令値と電圧センサを通じて取得された電圧値(VFC1)との偏差(差分の絶対値、“|ΔVFC1|”)を求める。同様にして、制御部30は、フライングキャパシタfc2に対する電圧指令値と電圧センサを通じて取得された電圧値(VFC2)との偏差(差分の絶対値、“|ΔVFC2|”)を求める。そして、フライングキャパシタfc1の偏差量(|ΔVFC1|)と、フライングキャパシタfc2の偏差量(|ΔVFC2|)との大小を判定する。フライングキャパシタfc1の偏差量(|ΔVFC1|)がフライングキャパシタfc2の偏差量(|ΔVFC2|)より小さい場合には(ステップS107、 “YES”)、処理はステップS108に進み、そうない場合には(ステップS107、 “NO”)、処理はステップS111に進む。 In step S107, the control unit 30 obtains the deviation (absolute value of difference, "|ΔVFC1|") between the voltage command value for the flying capacitor fc1 and the voltage value (VFC1) obtained through the voltage sensor. Similarly, the control unit 30 obtains a deviation (absolute value of difference, “|ΔVFC2|”) between the voltage command value for the flying capacitor fc2 and the voltage value (VFC2) obtained through the voltage sensor. Then, the magnitude of the deviation amount (|ΔVFC1|) of the flying capacitor fc1 and the deviation amount (|ΔVFC2|) of the flying capacitor fc2 is determined. If the deviation amount (|ΔVFC1|) of the flying capacitor fc1 is smaller than the deviation amount (|ΔVFC2|) of the flying capacitor fc2 (step S107, “YES”), the process proceeds to step S108; Step S107, "NO"), and the process proceeds to step S111.
 ステップS108では、第1直流キャパシタdc1を対象として電圧値が一定値(2E)であるかが判定される。電力変換装置1の制御部30は、第1出力回路14に設けられた電圧センサを通じて第1直流キャパシタdc1の電圧値(VDC1)を取得する。そして、第1直流キャパシタdc1の電圧値(VDC1)が一定値(2E)を超える場合には(ステップS108、“>2E”)、処理はステップS109に進み、一定値(2E)未満の場合には(ステップS108、“<2E”)、処理はステップS110に進む。ステップS108において、第1直流キャパシタdc1の電圧値(VDC1)が一定値(2E)に等しい場合には(ステップS108、“=2E”)、本ルーチンを一旦終了する。 In step S108, it is determined whether the voltage value of the first DC capacitor dc1 is a constant value (2E). The control unit 30 of the power converter 1 acquires the voltage value (VDC1) of the first DC capacitor dc1 through the voltage sensor provided in the first output circuit 14 . Then, when the voltage value (VDC1) of the first DC capacitor dc1 exceeds the constant value (2E) (step S108, ">2E"), the process proceeds to step S109, and when it is less than the constant value (2E) (step S108, "<2E"), the process proceeds to step S110. In step S108, when the voltage value (VDC1) of the first DC capacitor dc1 is equal to the constant value (2E) (step S108, "=2E"), this routine is temporarily terminated.
 ステップS109においては、第1直流キャパシタdc1の電圧値(VDC1)が一定値(2E)になるように、第1フライングキャパシタ回路12のスイッチング制御が行われる。具体的には、スイッチ素子S3(上線付きS4)のオン期間で特定される“デューティD3”の長さを増加させる。このようなスイッチング制御により、第2直流キャパシタdc2の放電期間が相対的に短くなり、第1直流キャパシタdc1の電圧値(VDC1)が一定値(2E)になるように減少する。ステップS109の処理後、本ルーチンの処理が一旦終了される。 In step S109, switching control of the first flying capacitor circuit 12 is performed so that the voltage value (VDC1) of the first DC capacitor dc1 becomes a constant value (2E). Specifically, the length of the "duty D3" specified by the ON period of the switch element S3 (overlined S4) is increased. Through such switching control, the discharge period of the second DC capacitor dc2 becomes relatively short, and the voltage value (VDC1) of the first DC capacitor dc1 decreases to a constant value (2E). After the processing of step S109, the processing of this routine is once terminated.
 ステップS110においても、第1直流キャパシタdc1の電圧値(VDC1)が一定値(2E)になるように、第1フライングキャパシタ回路12のスイッチング制御が行われる。具体的には、スイッチ素子S3(上線付きS4)のオン期間で特定される“デューティD3”の長さを減少させる。このようなスイッチング制御により、第2直流キャパシタdc2の放電期間が相対的に長くなり、第1直流キャパシタdc1の電圧値(VDC1)が一定値(2E)になるように増加する。ステップS110の処理後、本ルーチンの処理が一旦終了される。 Also in step S110, switching control of the first flying capacitor circuit 12 is performed so that the voltage value (VDC1) of the first DC capacitor dc1 becomes a constant value (2E). Specifically, the length of the "duty D3" specified by the ON period of the switch element S3 (overlined S4) is reduced. By such switching control, the discharge period of the second DC capacitor dc2 becomes relatively long, and the voltage value (VDC1) of the first DC capacitor dc1 increases to a constant value (2E). After the processing of step S110, the processing of this routine is once terminated.
 ステップS111においても、第1直流キャパシタdc1を対象として電圧値が一定値(2E)であるかが判定される。電力変換装置1の制御部30は、ステップS108と同様にして、第1出力回路14に設けられた電圧センサを通じて第1直流キャパシタdc1の電圧値(VDC1)を取得する。そして、第1直流キャパシタdc1の電圧値(VDC1)が一定値(2E)を超える場合には(ステップS111、“>2E”)、処理はステップS112に進み、一定値(2E)未満の場合には(ステップS111、“<2E”)、処理はステップS113に進む。ステップS111において、第1直流キャパシタdc1の電圧値(VDC1)が一定値(2E)に等しい場合には(ステップS111、“=2E”)、本ルーチンを一旦終了する。 Also in step S111, it is determined whether the voltage value of the first DC capacitor dc1 is a constant value (2E). The control unit 30 of the power converter 1 acquires the voltage value (VDC1) of the first DC capacitor dc1 through the voltage sensor provided in the first output circuit 14 in the same manner as in step S108. Then, when the voltage value (VDC1) of the first DC capacitor dc1 exceeds the constant value (2E) (step S111, ">2E"), the process proceeds to step S112, and when it is less than the constant value (2E) (step S111, "<2E"), the process proceeds to step S113. In step S111, when the voltage value (VDC1) of the first DC capacitor dc1 is equal to the constant value (2E) (step S111, "=2E"), this routine is once terminated.
 ステップS112においては、第1直流キャパシタdc1の電圧値(VDC1)が一定値(2E)になるように、第2フライングキャパシタ回路13のスイッチング制御が行われる。具体的には、スイッチ素子S11(上線付きS12)のオン期間で特定される“デューティD11”の長さを増加させる。このようなスイッチング制御により、第2直流キャパシタdc2の放電期間が相対的に短くなり、第1直流キャパシタdc1の電圧値(VDC1)が一定値(2E)になるように減少する。ステップS112の処理後、本ルーチンの処理が一旦終了される。 In step S112, switching control of the second flying capacitor circuit 13 is performed so that the voltage value (VDC1) of the first DC capacitor dc1 becomes a constant value (2E). Specifically, the length of the "duty D11" specified by the ON period of the switch element S11 (overlined S12) is increased. Through such switching control, the discharge period of the second DC capacitor dc2 becomes relatively short, and the voltage value (VDC1) of the first DC capacitor dc1 decreases to a constant value (2E). After the processing of step S112, the processing of this routine is temporarily terminated.
 ステップS113においても、第1直流キャパシタdc1の電圧値(VDC1)が一定値(2E)になるように、第2フライングキャパシタ回路13のスイッチング制御が行われる。スイッチ素子S11(上線付きS12)のオン期間で特定される“デューティD11”の長さを減少させる。このようなスイッチング制御により、第2直流キャパシタdc2の放電期間が相対的に長くなり、第1直流キャパシタdc1の電圧値(VDC1)が一定値(2E)になるように増加する。ステップS113の処理後、本ルーチンの処理が一旦終了される。 Also in step S113, switching control of the second flying capacitor circuit 13 is performed so that the voltage value (VDC1) of the first DC capacitor dc1 becomes a constant value (2E). The length of the "duty D11" specified by the ON period of the switch element S11 (S12 with an overlined line) is decreased. By such switching control, the discharge period of the second DC capacitor dc2 becomes relatively long, and the voltage value (VDC1) of the first DC capacitor dc1 increases to a constant value (2E). After the process of step S113, the process of this routine is once terminated.
 以上、説明したように、本実施例に係る電力変換装置1においては、フライングキャパシタfc1の電圧値(VFC1)が一定値(E)を超える場合には、スイッチ素子S1(上線付きS2)のデューティD1の長さを増加させ、スイッチ素子S3(上線付きS4)のデューティD3の長さを減少できる。上記スイッチ素子のスイッチング制御により、フライングキャパシタfc1の放電期間の長さを長くなるように制御し、電圧値(VFC1)が一定値(E)になるように減少できる。 As described above, in the power conversion device 1 according to the present embodiment, when the voltage value (VFC1) of the flying capacitor fc1 exceeds the constant value (E), the duty of the switch element S1 (S2 with the upper line) By increasing the length of D1, it is possible to decrease the length of the duty D3 of the switch element S3 (overlined S4). By controlling the switching of the switching element, the length of the discharge period of the flying capacitor fc1 can be controlled to be longer, and the voltage value (VFC1) can be reduced to a constant value (E).
 また、本実施例に係る電力変換装置1においては、フライングキャパシタfc1の電圧値(VFC1)が一定値(E)未満の場合には、スイッチ素子S1(上線付きS2)のデューティD1の長さを減少させ、スイッチ素子S3(上線付きS4)のデューティD3の長さを増加できる。上記スイッチ素子のスイッチング制御により、フライングキャパシタfc1の放電期間の長さを短くなるように制御し、電圧値(VFC1)が一定値(E)になるように増加できる。 Further, in the power converter 1 according to the present embodiment, when the voltage value (VFC1) of the flying capacitor fc1 is less than the constant value (E), the length of the duty D1 of the switch element S1 (overlined S2) is can be reduced, and the length of the duty D3 of the switch element S3 (overlined S4) can be increased. By controlling the switching of the switch element, the length of the discharge period of the flying capacitor fc1 can be controlled to be shortened, and the voltage value (VFC1) can be increased to a constant value (E).
 また、本実施例に係る電力変換装置1においては、フライングキャパシタfc2の電圧値(VFC2)が一定値(E)を超える場合には、スイッチ素子S9(上線付きS10)のデューティD9の長さを減少させ、スイッチ素子S11(上線付きS12)のデューティD11の長さを増加できる。上記スイッチ素子のスイッチング制御により、フライングキャパシタfc2の放電期間の長さを長くなるように制御し、電圧値(VFC2)が一定値(E)になるように減少できる。 Further, in the power conversion device 1 according to the present embodiment, when the voltage value (VFC2) of the flying capacitor fc2 exceeds a certain value (E), the length of the duty D9 of the switch element S9 (S10 with an upper line) is set to can be reduced, and the length of the duty D11 of the switch element S11 (S12 with an overlined line) can be increased. By controlling the switching of the switch element, the length of the discharge period of the flying capacitor fc2 can be controlled to be longer, and the voltage value (VFC2) can be reduced to a constant value (E).
 また、本実施例に係る電力変換装置1においては、フライングキャパシタfc2の電圧値(VFC2)が一定値(E)未満の場合には、スイッチ素子S9(上線付きS10)のデューティD9の長さを増加させ、スイッチ素子S11(上線付きS12)のデューティD11の長さを減少できる。上記スイッチ素子のスイッチング制御により、フライングキャパシタfc2の放電期間の長さを短くなるように制御し、電圧値(VFC2)が一定値(E)になるように増加できる。 Further, in the power conversion device 1 according to the present embodiment, when the voltage value (VFC2) of the flying capacitor fc2 is less than the constant value (E), the length of the duty D9 of the switch element S9 (S10 with an upper line) is set to can be increased, and the length of the duty D11 of the switch element S11 (overlined S12) can be reduced. By controlling the switching of the switch element, the length of the discharge period of the flying capacitor fc2 can be controlled to be shortened, and the voltage value (VFC2) can be increased to a constant value (E).
 また、本実施例に係る電力変換装置1においては、フライングキャパシタfc1の電圧(VFC1)に関する偏差量とフライングキャパシタfc2の電圧(VFC2)に関する偏差量とに応じて、第1直流キャパシタdc1の電圧(VDC1)を連動させて制御するためのスイッチ素子が選定できる。フライングキャパシタfc1の偏差量(|ΔVFC1|)がフライングキャパシタfc2の偏差量(|ΔVFC2|)より小さい場合には、第1直流キャパシタdc1の電圧値(VDC1)を一定値(2E)に制御するためのスイッチ素子S3(上線付きS4)が選定できる。同様にして、フライングキャパシタfc1の偏差量(|ΔVFC1|)がフライングキャパシタfc2の偏差量(|ΔVFC2|)以上の場合には、第1直流キャパシタdc1の電圧値(VDC1)を一定値(2E)に制御するためのスイッチ素子S11(上線付きS12)が選定できる。 Further, in the power conversion device 1 according to the present embodiment, the voltage of the first DC capacitor dc1 ( A switch element for interlocking and controlling VDC1) can be selected. When the deviation amount (|ΔVFC1|) of the flying capacitor fc1 is smaller than the deviation amount (|ΔVFC2|) of the flying capacitor fc2, the voltage value (VDC1) of the first DC capacitor dc1 is controlled to a constant value (2E). can be selected. Similarly, when the deviation amount (|ΔVFC1|) of the flying capacitor fc1 is equal to or larger than the deviation amount (|ΔVFC2|) of the flying capacitor fc2, the voltage value (VDC1) of the first DC capacitor dc1 is set to a constant value (2E). A switch element S11 (overlined S12) can be selected for controlling
 そして、本実施例に係る電力変換装置1においては、第1直流キャパシタdc1の電圧値(VDC1)が一定値(2E)を超える場合には、スイッチ素子S3(上線付きS4)のデューティD3の長さを増加し、一定値(2E)未満の場合には、デューティD3の長さを減少できる。本実施例においては、スイッチ素子S3(上線付きS4)のデューティD3の長さに基づいて、第1直流キャパシタdc1の電圧値(VDC1)が一定値(2E)になるように制御できる。 Then, in the power conversion device 1 according to the present embodiment, when the voltage value (VDC1) of the first DC capacitor dc1 exceeds a constant value (2E), the length of the duty D3 of the switch element S3 (S4 with an overlined line) If it is less than a certain value (2E), the length of duty D3 can be decreased. In this embodiment, the voltage value (VDC1) of the first DC capacitor dc1 can be controlled to a constant value (2E) based on the length of the duty D3 of the switch element S3 (overlined S4).
 また、本実施例に係る電力変換装置1においては、第1直流キャパシタdc1の電圧値(VDC1)が一定値(2E)を超える場合には、スイッチ素子S11(上線付きS12)のデューティD11の長さを増加させ、一定値(2E)未満の場合には、デューティD11の長さを減少できる。このようなスイッチング制御形態であっても、スイッチ素子S11(上線付きS12)のデューティD11の長さに基づいて、第1直流キャパシタdc1の電圧値(VDC1)が一定値(2E)になるように制御できる。 Further, in the power conversion device 1 according to the present embodiment, when the voltage value (VDC1) of the first DC capacitor dc1 exceeds a certain value (2E), the length of the duty D11 of the switch element S11 (S12 with an overlined line) The length of the duty D11 can be decreased when the duty D11 is less than a constant value (2E). Even in such a switching control mode, the voltage value (VDC1) of the first DC capacitor dc1 is set to a constant value (2E) based on the length of the duty D11 of the switch element S11 (S12 with an overlined line). You can control it.
(第2領域)
 図12は、第2領域における電圧制御処理の一例を示すフローチャートである。図12の破線吹き出し領域Z2には、本フローの制御対象になる出力電圧(vo)と出力電流(io)との相対位相領域がハッチングされた矩形領域に例示される。図12のフローにおいても、電圧制御処理の開始後、電力変換部10のフライングキャパシタfc1の電圧値が一定値(E)であるかが判定される(ステップS121)。フライングキャパシタfc1の電圧値(VFC1)は、第1フライングキャパシタ回路12に設けられた電圧センサを通じて取得される。ステップS121において、フライングキャパシタfc1の電圧値(VFC1)が一定値(E)を超える場合には(ステップS121、“>E”)、処理はステップS122に進み、一定値(E)未満の場合には(ステップS121、“<E”)、処理はステップS123に進む。ステップS121において、フライングキャパシタfc1の電圧値(VFC1)が一定値(E)の場合には(ステップS121、“=E”)、処理はステップS124に進む。
(Second area)
FIG. 12 is a flowchart showing an example of voltage control processing in the second area. In the broken-line balloon area Z2 in FIG. 12, the relative phase area between the output voltage (vo) and the output current (io) to be controlled in this flow is illustrated as a hatched rectangular area. Also in the flow of FIG. 12, after starting the voltage control process, it is determined whether the voltage value of the flying capacitor fc1 of the power conversion unit 10 is a constant value (E) (step S121). A voltage value (VFC1) of the flying capacitor fc1 is obtained through a voltage sensor provided in the first flying capacitor circuit 12 . In step S121, if the voltage value (VFC1) of the flying capacitor fc1 exceeds the constant value (E) (step S121, ">E"), the process proceeds to step S122. (step S121, "<E"), the process proceeds to step S123. In step S121, when the voltage value (VFC1) of the flying capacitor fc1 is a constant value (E) (step S121, "=E"), the process proceeds to step S124.
 ステップS122においては、フライングキャパシタfc1の電圧値(VFC1)が一定値(E)になるように、第1フライングキャパシタ回路12のスイッチング制御が行われる。具体的には、図6で説明したように、スイッチ素子S1(上線付きS2)のオン期間で特定される“デューティD1”の長さを減少させ、スイッチ素子S3(上線付きS4)のオン期間で特定される“デューティD3”の長さを増加させる。このようなスイッチング制御により、フライングキャパシタfc1の放電期間が相対的に長くなり、フライングキャパシタfc1の電圧値(VFC1)が一定値(E)になるように減少する。ステップS122の処理後、処理はステップS124に進む。 In step S122, switching control of the first flying capacitor circuit 12 is performed so that the voltage value (VFC1) of the flying capacitor fc1 becomes a constant value (E). Specifically, as described with reference to FIG. 6, the length of the "duty D1" specified by the ON period of the switch element S1 (S2 with the overlined line) is reduced, and the ON period of the switch element S3 (S4 with the overlined line) is reduced. Increase the length of "duty D3" specified by . With such switching control, the discharge period of the flying capacitor fc1 becomes relatively long, and the voltage value (VFC1) of the flying capacitor fc1 decreases to a constant value (E). After the process of step S122, the process proceeds to step S124.
 ステップS123においても、フライングキャパシタfc1の電圧値(VFC1)が一定値(E)になるように、第1フライングキャパシタ回路12のスイッチング制御が行われる。具体的には、図6で説明したように、スイッチ素子S1(上線付きS2)のオン期間で特定される“デューティD1”の長さを増加させ、スイッチ素子S3(上線付きS4)のオン期間で特定される“デューティD3”の長さを減少させる。このようなスイッチング制御により、フライングキャパシタfc1の放電期間が相対的に短くなり、フライングキャパシタfc1の電圧値(VFC1)が一定値(E)になるように増加する。ステップS123の処理後、処理はステップS124に進む。 Also in step S123, switching control of the first flying capacitor circuit 12 is performed so that the voltage value (VFC1) of the flying capacitor fc1 becomes a constant value (E). Specifically, as described with reference to FIG. 6, the length of the "duty D1" specified by the ON period of the switch element S1 (S2 with the overlined line) is increased, and the ON period of the switch element S3 (S4 with the overlined line) is increased. Decrease the length of "duty D3" specified by . Through such switching control, the discharge period of the flying capacitor fc1 becomes relatively short, and the voltage value (VFC1) of the flying capacitor fc1 increases to a constant value (E). After the process of step S123, the process proceeds to step S124.
 ステップS124では、フライングキャパシタfc2を対象として電圧値が一定値(E)であるかが判定される。フライングキャパシタfc2の電圧値(VFC2)は、第2フライングキャパシタ回路13に設けられた電圧センサを通じて取得される。そして、フライングキャパシタfc2の電圧値(VFC2)が一定値(E)を超える場合には(ステップS124、“>E”)、処理はステップS125に進み、一定値(E)未満の場合には(ステップS124、“<E”)、処理はステップS126に進む。ステップS124において、フライングキャパシタfc2の電圧値(VFC2)が一定値(E)の場合には(ステップS124、“=E”)、処理はステップS127に進む。 In step S124, it is determined whether the voltage value of the flying capacitor fc2 is a constant value (E). A voltage value (VFC2) of the flying capacitor fc2 is acquired through a voltage sensor provided in the second flying capacitor circuit 13 . Then, when the voltage value (VFC2) of the flying capacitor fc2 exceeds the constant value (E) (step S124, ">E"), the process proceeds to step S125, and when it is less than the constant value (E) ( Step S124, "<E"), and the process proceeds to step S126. In step S124, when the voltage value (VFC2) of the flying capacitor fc2 is a constant value (E) (step S124, "=E"), the process proceeds to step S127.
 ステップS125においては、フライングキャパシタfc2の電圧値(VFC2)が一定値(E)になるように、第2フライングキャパシタ回路13のスイッチング制御が行われる。具体的には、図7で説明したように、スイッチ素子S9(上線付きS10)のオン期間で特定される“デューティD9”の長さを増加させ、スイッチ素子S11(上線付きS12)のオン期間で特定される“デューティD11”の長さを減少させる。このようなスイッチング制御により、フライングキャパシタfc2の放電期間が相対的に長くなり、フライングキャパシタfc2の電圧値(VFC2)が一定値(E)になるように減少する。ステップS125の処理後、処理はステップS127に進む。 In step S125, switching control of the second flying capacitor circuit 13 is performed so that the voltage value (VFC2) of the flying capacitor fc2 becomes a constant value (E). Specifically, as described with reference to FIG. 7, the length of the "duty D9" specified by the ON period of the switch element S9 (S10 with the upper line) is increased, and the ON period of the switch element S11 (S12 with the upper line) is increased. Decrease the length of "duty D11" specified by . By such switching control, the discharge period of the flying capacitor fc2 becomes relatively long, and the voltage value (VFC2) of the flying capacitor fc2 decreases to a constant value (E). After the process of step S125, the process proceeds to step S127.
 ステップS126においても、フライングキャパシタfc2の電圧値(VFC2)が一定値(E)になるように、第2フライングキャパシタ回路13のスイッチング制御が行われる。具体的には、図7で説明したように、スイッチ素子S9(上線付きS10)のオン期間で特定される“デューティD9”の長さを減少させ、スイッチ素子S11(上線付きS12)のオン期間で特定される“デューティD11”の長さを増加させる。このようなスイッチング制御により、フライングキャパシタfc2の放電期間が相対的に短くなり、フライングキャパシタfc2の電圧値(VFC2)が一定値(E)になるように増加する。ステップS126の処理後、処理はステップS127に進む。 Also in step S126, switching control of the second flying capacitor circuit 13 is performed so that the voltage value (VFC2) of the flying capacitor fc2 becomes a constant value (E). Specifically, as described with reference to FIG. 7, the length of the "duty D9" specified by the on-period of the switch element S9 (overlined S10) is reduced, and the on-period of the switch element S11 (overlined S12) is reduced. Increase the length of "duty D11" specified by . By such switching control, the discharge period of the flying capacitor fc2 becomes relatively short, and the voltage value (VFC2) of the flying capacitor fc2 increases to a constant value (E). After the process of step S126, the process proceeds to step S127.
 ステップS127からステップS133の処理では、図11のフローに示すステップS107からステップS113の処理が実行される。すなわち、フライングキャパシタfc1に対する電圧指令値と電圧センサを通じて取得された電圧値(VFC1)との偏差量(|ΔVFC1|)、フライングキャパシタfc2に対する電圧指令値と電圧センサを通じて取得された電圧値(VFC2)との偏差量(|ΔVFC2|)が求められる。そして、フライングキャパシタfc1の偏差量(|ΔVFC1|)と、フライングキャパシタfc2の偏差量(|ΔVFC2|)との大小判定により、第1直流キャパシタdc1の電圧値を一定値(2E)に制御するためのスイッチ素子が判定される。 In the process from step S127 to step S133, the process from step S107 to step S113 shown in the flow of FIG. 11 is executed. That is, the amount of deviation (|ΔVFC1|) between the voltage command value for the flying capacitor fc1 and the voltage value (VFC1) acquired through the voltage sensor, the voltage command value for the flying capacitor fc2 and the voltage value (VFC2) acquired through the voltage sensor and the amount of deviation (|ΔVFC2|) is obtained. Then, the voltage value of the first DC capacitor dc1 is controlled to a constant value (2E) by judging the difference between the deviation amount (|ΔVFC1|) of the flying capacitor fc1 and the deviation amount (|ΔVFC2|) of the flying capacitor fc2. of switch elements are determined.
 そして、フライングキャパシタfc1の偏差量(|ΔVFC1|)がフライングキャパシタfc2の偏差量(|ΔVFC2|)より小さい場合には(ステップS127、“YES”)、スイッチ素子S3(上線付きS4)が制御対象に選定され、第1直流キャパシタdc1の電圧値を一定値(2E)に制御するための処理が行われる(ステップS128からステップS130)。フライングキャパシタfc1の偏差量(|ΔVFC1|)がフライングキャパシタfc2の偏差量(|ΔVFC2|)以上の場合には(ステップS127、“NO”)、スイッチ素子S11(上線付きS12)が制御対象に選定され、第1直流キャパシタdc1の電圧値を一定値(2E)に制御するための処理が行われる(ステップS131からステップS133)。ステップS133の処理後、本ルーチンの処理が一旦終了される。 Then, when the deviation amount (|ΔVFC1|) of the flying capacitor fc1 is smaller than the deviation amount (|ΔVFC2|) of the flying capacitor fc2 (step S127, “YES”), the switch element S3 (overlined S4) is the controlled object. , and a process for controlling the voltage value of the first DC capacitor dc1 to a constant value (2E) is performed (steps S128 to S130). If the deviation amount (|ΔVFC1|) of the flying capacitor fc1 is greater than or equal to the deviation amount (|ΔVFC2|) of the flying capacitor fc2 (step S127, "NO"), the switch element S11 (S12 with an overlined line) is selected as the control target. Then, a process for controlling the voltage value of the first DC capacitor dc1 to a constant value (2E) is performed (steps S131 to S133). After the processing of step S133, the processing of this routine is once terminated.
 以上、説明したように、本実施例に係る電力変換装置1においては、フライングキャパシタfc1の電圧値(VFC1)が一定値(E)を超える場合には、スイッチ素子S1(上線付きS2)のデューティD1の長さを減少させ、スイッチ素子S3(上線付きS4)のデューティD3の長さを増加できる。上記スイッチ素子のスイッチング制御により、フライングキャパシタfc1の放電期間の長さを相対的に長くなるように制御し、電圧値(VFC1)が一定値(E)になるように減少できる。 As described above, in the power conversion device 1 according to the present embodiment, when the voltage value (VFC1) of the flying capacitor fc1 exceeds the constant value (E), the duty of the switching element S1 (S2 with the upper line) The length of D1 can be decreased and the length of duty D3 of switch element S3 (S4 with an overlined line) can be increased. Through the switching control of the switch element, the length of the discharge period of the flying capacitor fc1 can be controlled to be relatively long, and the voltage value (VFC1) can be reduced to a constant value (E).
 また、本実施例に係る電力変換装置1においては、フライングキャパシタfc1の電圧値(VFC1)が一定値(E)未満の場合には、スイッチ素子S1(上線付きS2)のデューティD1の長さを増加させ、スイッチ素子S3(上線付きS4)のデューティD3の長さを減少できる。上記スイッチ素子のスイッチング制御により、フライングキャパシタfc1の放電期間の長さを短くなるように制御し、電圧値(VFC1)が一定値(E)になるように増加できる。 Further, in the power conversion device 1 according to the present embodiment, when the voltage value (VFC1) of the flying capacitor fc1 is less than the constant value (E), the length of the duty D1 of the switch element S1 (S2 with an upper line) is set to can be increased, and the length of the duty D3 of the switch element S3 (overlined S4) can be reduced. By controlling the switching of the switch element, the length of the discharge period of the flying capacitor fc1 can be controlled to be shortened, and the voltage value (VFC1) can be increased to a constant value (E).
 また、本実施例に係る電力変換装置1においては、フライングキャパシタfc2の電圧値(VFC2)が一定値(E)を超える場合には、スイッチ素子S9(上線付きS10)のデューティD9の長さを増加させ、スイッチ素子S11(上線付きS12)のデューティD11の長さを減少できる。上記スイッチ素子のスイッチング制御により、フライングキャパシタfc2の放電期間の長さを長くなるように制御し、電圧値(VFC2)が一定値(E)になるように減少できる。 Further, in the power conversion device 1 according to the present embodiment, when the voltage value (VFC2) of the flying capacitor fc2 exceeds a constant value (E), the length of the duty D9 of the switch element S9 (S10 with an upper line) is set to can be increased, and the length of the duty D11 of the switch element S11 (overlined S12) can be reduced. By controlling the switching of the switching element, the length of the discharge period of the flying capacitor fc2 can be controlled to be longer, and the voltage value (VFC2) can be reduced to a constant value (E).
 また、本実施例に係る電力変換装置1においては、フライングキャパシタfc2の電圧値(VFC2)が一定値(E)未満の場合には、スイッチ素子S9(上線付きS10)のデューティD9の長さを減少させ、スイッチ素子S11(上線付きS12)のデューティD11の長さを増加できる。上記スイッチ素子のスイッチング制御により、フライングキャパシタfc2の放電期間の長さを短くなるように制御し、電圧値(VFC2)が一定値(E)になるように増加できる。 Further, in the power conversion device 1 according to the present embodiment, when the voltage value (VFC2) of the flying capacitor fc2 is less than the constant value (E), the length of the duty D9 of the switch element S9 (S10 with an upper line) is set to can be reduced, and the length of the duty D11 of the switch element S11 (S12 with an overlined line) can be increased. By controlling the switching of the switch element, the length of the discharge period of the flying capacitor fc2 can be controlled to be shortened, and the voltage value (VFC2) can be increased to a constant value (E).
 さらに、第2領域の電圧制御においても、フライングキャパシタfc1の電圧(VFC1)に関する偏差量とフライングキャパシタfc2の電圧(VFC2)に関する偏差量とに応じて、第1直流キャパシタdc1の電圧(VDC1)を連動させて制御するためのスイッチ素子が選定できる。フライングキャパシタfc1の偏差量(|ΔVFC1|)がフライングキャパシタfc2の偏差量(|ΔVFC2|)より小さい場合には、第1直流キャパシタdc1の電圧値(VDC1)を一定値(2E)に制御するためのスイッチ素子S3(上線付きS4)が選定できる。同様にして、フライングキャパシタfc1の偏差量(|ΔVFC1|)がフライングキャパシタfc2の偏差量(|ΔVFC2|)以上の場合には、第1直流キャパシタdc1の電圧値(VDC1)を一定値(2E)に制御するためのスイッチ素子S11(上線付きS12)が選定できる。 Furthermore, in the voltage control in the second region, the voltage (VDC1) of the first DC capacitor dc1 is adjusted according to the deviation amount regarding the voltage (VFC1) of the flying capacitor fc1 and the deviation amount regarding the voltage (VFC2) of the flying capacitor fc2. A switch element for interlocking control can be selected. When the deviation amount (|ΔVFC1|) of the flying capacitor fc1 is smaller than the deviation amount (|ΔVFC2|) of the flying capacitor fc2, the voltage value (VDC1) of the first DC capacitor dc1 is controlled to a constant value (2E). can be selected. Similarly, when the deviation amount (|ΔVFC1|) of the flying capacitor fc1 is equal to or larger than the deviation amount (|ΔVFC2|) of the flying capacitor fc2, the voltage value (VDC1) of the first DC capacitor dc1 is set to a constant value (2E). A switch element S11 (overlined S12) can be selected for controlling
 そして、本実施例に係る電力変換装置1においては、第1直流キャパシタdc1の電圧値(VDC1)が一定値(2E)を超える場合には、スイッチ素子S3(上線付きS4)のデューティD3の長さを増加し、一定値(2E)未満の場合には、デューティD3の長さを減少できる。本実施例においては、スイッチ素子S3(上線付きS4)のデューティD3の長さに基づいて、第1直流キャパシタdc1の電圧値(VDC1)が一定値(2E)になるように制御できる。 Then, in the power conversion device 1 according to the present embodiment, when the voltage value (VDC1) of the first DC capacitor dc1 exceeds a constant value (2E), the length of the duty D3 of the switch element S3 (S4 with an overlined line) The length of the duty D3 can be decreased if it is less than a certain value (2E). In this embodiment, the voltage value (VDC1) of the first DC capacitor dc1 can be controlled to a constant value (2E) based on the length of the duty D3 of the switch element S3 (overlined S4).
 また、本実施例に係る電力変換装置1においては、第1直流キャパシタdc1の電圧値(VDC1)が一定値(2E)を超える場合には、スイッチ素子S11(上線付きS12)のデューティD11の長さを増加させ、一定値(2E)未満の場合には、デューティD11の長さを減少できる。このようなスイッチング制御形態であっても、スイッチ素子S11(上線付きS12)のデューティD11の長さに基づいて、第1直流キャパシタdc1の電圧値(VDC1)が一定値(2E)になるように制御できる。 Further, in the power conversion device 1 according to the present embodiment, when the voltage value (VDC1) of the first DC capacitor dc1 exceeds a constant value (2E), the length of the duty D11 of the switch element S11 (S12 with an overlined line) The length of the duty D11 can be decreased when the duty D11 is less than a constant value (2E). Even in such a switching control form, the voltage value (VDC1) of the first DC capacitor dc1 is set to a constant value (2E) based on the length of the duty D11 of the switch element S11 (S12 with an overlined line). You can control it.
(第3領域)
 図13は、第3領域における電圧制御処理の一例を示すフローチャートである。図13の破線吹き出し領域Z3には、本フローの制御対象になる出力電圧(vo)と出力電流(io)との相対位相領域がハッチングされた矩形領域に例示される。図13のフローにおいて、電圧制御処理の開始後に実行されるステップS141からステップS146の処理では、図12のフローに示すステップS121からステップS126の処理が実行される。
(Third area)
FIG. 13 is a flowchart showing an example of voltage control processing in the third area. In the broken-line balloon area Z3 in FIG. 13, the relative phase area between the output voltage (vo) and the output current (io) to be controlled in this flow is illustrated as a hatched rectangular area. In the flow of FIG. 13, the processing of steps S121 to S126 shown in the flow of FIG. 12 is executed in the processing of steps S141 to S146 executed after the start of the voltage control processing.
 すなわち、フライングキャパシタfc1の電圧値(VFC1)が一定値(E)を超える場合には(ステップS141、“>E”)、スイッチ素子S1(上線付きS2)のデューティD1の長さを減少させ、スイッチ素子S3(上線付きS4)のデューティD3の長さを増加させる(ステップS142)。また、フライングキャパシタfc1の電圧値(VFC1)が一定値(E)未満の場合には(ステップS141、“<E”)、スイッチ素子S1(上線付きS2)のデューティD1の長さを増加させ、スイッチ素子S3(上線付きS4)のデューティD3の長さを減少させる(ステップS143)。ステップS142の処理により、フライングキャパシタfc1の放電期間が相対的に長くなり、フライングキャパシタfc1の電圧値(VFC1)が一定値(E)になるように減少する。また、ステップS143の処理により、フライングキャパシタfc1の放電期間が相対的に短くなり、フライングキャパシタfc1の電圧値(VFC1)が一定値(E)になるように増加する。 That is, when the voltage value (VFC1) of the flying capacitor fc1 exceeds a certain value (E) (step S141, ">E"), the length of the duty D1 of the switch element S1 (overlined S2) is reduced, The length of the duty D3 of the switch element S3 (overlined S4) is increased (step S142). Further, when the voltage value (VFC1) of the flying capacitor fc1 is less than the constant value (E) (step S141, "<E"), the length of the duty D1 of the switch element S1 (overlined S2) is increased, The length of duty D3 of switch element S3 (overlined S4) is decreased (step S143). The process of step S142 relatively lengthens the discharge period of the flying capacitor fc1, and decreases the voltage value (VFC1) of the flying capacitor fc1 to a constant value (E). Moreover, the discharge period of the flying capacitor fc1 is relatively shortened by the process of step S143, and the voltage value (VFC1) of the flying capacitor fc1 increases to a constant value (E).
 さらに、フライングキャパシタfc2の電圧値(VFC2)が一定値(E)を超える場合には(ステップS144、“>E”)、スイッチ素子S9(上線付きS10)のデューティD9の長さを増加させ、スイッチ素子S11(上線付きS12)のデューティD11の長さを減少させる(ステップS145)。また、フライングキャパシタfc2の電圧値(VFC2)が一定値(E)未満の場合には(ステップS144、“<E”)、スイッチ素子S9(上線付きS10)のデューティD9の長さを減少させ、スイッチ素子S11(上線付きS12)のデューティD11の長さを増加させる(ステップS146)。ステップS145の処理により、フライングキャパシタfc2の放電期間が相対的に長くなり、フライングキャパシタfc2の電圧値(VFC2)が一定値(E)になるように減少する。また、ステップS146の処理により、フライングキャパシタfc2の放電期間が相対的に短くなり、フライングキャパシタfc2の電圧値(VFC2)が一定値(E)になるように増加する。ステップS146の処理後、処理はステップS147に進む。 Furthermore, when the voltage value (VFC2) of the flying capacitor fc2 exceeds a certain value (E) (step S144, ">E"), the length of the duty D9 of the switch element S9 (S10 with an overlined line) is increased, The length of the duty D11 of the switch element S11 (overlined S12) is decreased (step S145). Further, when the voltage value (VFC2) of the flying capacitor fc2 is less than the constant value (E) (step S144, "<E"), the length of the duty D9 of the switch element S9 (S10 with an overlined line) is reduced, The length of duty D11 of switch element S11 (overlined S12) is increased (step S146). By the process of step S145, the discharge period of the flying capacitor fc2 becomes relatively long, and the voltage value (VFC2) of the flying capacitor fc2 decreases to a constant value (E). Moreover, the discharge period of the flying capacitor fc2 is relatively shortened by the process of step S146, and the voltage value (VFC2) of the flying capacitor fc2 increases to a constant value (E). After the process of step S146, the process proceeds to step S147.
 ステップS147の処理では、図11のフローに示すステップS107の処理が実行される。すなわち、フライングキャパシタfc1に対する電圧指令値と電圧センサを通じて取得された電圧値(VFC1)との偏差量(|ΔVFC1|)、フライングキャパシタfc2に対する電圧指令値と電圧センサを通じて取得された電圧値(VFC2)との偏差量(|ΔVFC2|)が求められる。そして、フライングキャパシタfc1の偏差量(|ΔVFC1|)と、フライングキャパシタfc2の偏差量(|ΔVFC2|)との大小判定により、第1直流キャパシタdc1の電圧値を一定値(2E)に制御するためのスイッチ素子が判定される。 In the process of step S147, the process of step S107 shown in the flow of FIG. 11 is executed. That is, the amount of deviation (|ΔVFC1|) between the voltage command value for the flying capacitor fc1 and the voltage value (VFC1) acquired through the voltage sensor, the voltage command value for the flying capacitor fc2 and the voltage value (VFC2) acquired through the voltage sensor and the amount of deviation (|ΔVFC2|) is obtained. Then, the voltage value of the first DC capacitor dc1 is controlled to a constant value (2E) by judging the difference between the deviation amount (|ΔVFC1|) of the flying capacitor fc1 and the deviation amount (|ΔVFC2|) of the flying capacitor fc2. of switch elements are determined.
 ステップS147の処理において、フライングキャパシタfc1の偏差量(|ΔVFC1|)がフライングキャパシタfc2の偏差量(|ΔVFC2|)より小さい場合には(ステップS147、“YES”)、処理はステップS148に進み、そうない場合には(ステップS147、“NO”)、処理はステップS151に進む。 In the process of step S147, if the deviation amount (|ΔVFC1|) of the flying capacitor fc1 is smaller than the deviation amount (|ΔVFC2|) of the flying capacitor fc2 (step S147, "YES"), the process proceeds to step S148. Otherwise (step S147, "NO"), the process proceeds to step S151.
 ステップS148では、第1直流キャパシタdc1を対象として電圧値が一定値(2E)であるかが判定される。第1直流キャパシタdc1の電圧値(VDC1)は、第1出力回路14に設けられた電圧センサを通じて取得される。そして、第1直流キャパシタdc1の電圧値(VDC1)が一定値(2E)を超える場合には(ステップS148、“>2E”)、処理はステップS149に進み、一定値(2E)未満の場合には(ステップS148、“<2E”)、処理はステップS150に進む。ステップS148において、第1直流キャパシタdc1の電圧値(VDC1)が一定値(2E)に等しい場合には(ステップS148、“=2E”)、本ルーチンを一旦終了する。 In step S148, it is determined whether the voltage value of the first DC capacitor dc1 is a constant value (2E). A voltage value (VDC1) of the first DC capacitor dc1 is obtained through a voltage sensor provided in the first output circuit 14 . Then, if the voltage value (VDC1) of the first DC capacitor dc1 exceeds the constant value (2E) (step S148, ">2E"), the process proceeds to step S149, and if it is less than the constant value (2E) (step S148, "<2E"), the process proceeds to step S150. In step S148, when the voltage value (VDC1) of the first DC capacitor dc1 is equal to the constant value (2E) (step S148, "=2E"), this routine is temporarily terminated.
 ステップS149においては、第1直流キャパシタdc1の電圧値(VDC1)が一定値(2E)になるように、第1フライングキャパシタ回路12のスイッチング制御が行われる。具体的には、図8で説明したように、スイッチ素子S3(上線付きS4)のオン/オフ期間で特定される“デューティD3”の長さを減少させる。このようなスイッチング制御により、第2直流キャパシタdc2の放電期間が相対的に短くなり、第1直流キャパシタdc1の電圧値(VDC1)が一定値(2E)になるように減少する。ステップS149の処理後、本ルーチンの処理が一旦終了される。 In step S149, switching control of the first flying capacitor circuit 12 is performed so that the voltage value (VDC1) of the first DC capacitor dc1 becomes a constant value (2E). Specifically, as described with reference to FIG. 8, the length of the "duty D3" specified by the on/off period of the switch element S3 (overlined S4) is reduced. Through such switching control, the discharge period of the second DC capacitor dc2 becomes relatively short, and the voltage value (VDC1) of the first DC capacitor dc1 decreases to a constant value (2E). After the process of step S149, the process of this routine is once terminated.
 ステップS150においても、第1直流キャパシタdc1の電圧値(VDC1)が一定値(2E)になるように、第1フライングキャパシタ回路12のスイッチング制御が行われる。具体的には、スイッチ素子S3(上線付きS4)のオン期間で特定されるデューティD3の長さを増加させる。このようなスイッチング制御により、第2直流キャパシタdc2の放電期間が相対的に長くなり、第1直流キャパシタdc1の電圧値(VDC1)が一定値(2E)になるように増加する。ステップS150の処理後、本ルーチンの処理が一旦終了される。 Also in step S150, switching control of the first flying capacitor circuit 12 is performed so that the voltage value (VDC1) of the first DC capacitor dc1 becomes a constant value (2E). Specifically, the length of the duty D3 specified by the ON period of the switch element S3 (overlined S4) is increased. By such switching control, the discharge period of the second DC capacitor dc2 becomes relatively long, and the voltage value (VDC1) of the first DC capacitor dc1 increases to a constant value (2E). After the processing of step S150, the processing of this routine is once terminated.
 ステップS151においては、第1直流キャパシタdc1を対象として電圧値が一定値(2E)であるかが判定される。第1直流キャパシタdc1の電圧値(VDC1)は、第1出力回路14に設けられた電圧センサを通じて取得される。そして、第1直流キャパシタdc1の電圧値(VDC1)が一定値(2E)を超える場合には(ステップS151、 “>2E”)、処理はステップS152に進み、一定値(2E)未満の場合には(ステップS151、“<2E”)、処理はステップS153に進む。ステップS151において、第1直流キャパシタdc1の電圧値(VDC1)が一定値(2E)に等しい場合には(ステップS151、“=2E”)、本ルーチンを一旦終了する。 In step S151, it is determined whether the voltage value of the first DC capacitor dc1 is a constant value (2E). A voltage value (VDC1) of the first DC capacitor dc1 is obtained through a voltage sensor provided in the first output circuit 14 . Then, if the voltage value (VDC1) of the first DC capacitor dc1 exceeds the constant value (2E) (step S151, ">2E"), the process proceeds to step S152, and if it is less than the constant value (2E) (step S151, "<2E"), the process proceeds to step S153. In step S151, when the voltage value (VDC1) of the first DC capacitor dc1 is equal to the constant value (2E) (step S151, "=2E"), this routine is temporarily terminated.
 ステップS152においては、第1直流キャパシタdc1の電圧値(VDC1)が一定値(2E)になるように、第2フライングキャパシタ回路13のスイッチング制御が行われる。具体的には、スイッチ素子S11(上線付きS12)のオン期間で特定されるデューティD11の長さを減少させる。このようなスイッチング制御により、第2直流キャパシタdc2の放電期間が相対的に短くなり、第1直流キャパシタdc1の電圧値(VDC1)が一定値(2E)になるように減少する。ステップS152の処理後、本ルーチンの処理が一旦終了される。 In step S152, switching control of the second flying capacitor circuit 13 is performed so that the voltage value (VDC1) of the first DC capacitor dc1 becomes a constant value (2E). Specifically, the length of the duty D11 specified by the ON period of the switch element S11 (overlined S12) is reduced. Through such switching control, the discharge period of the second DC capacitor dc2 becomes relatively short, and the voltage value (VDC1) of the first DC capacitor dc1 decreases to a constant value (2E). After the process of step S152, the process of this routine is temporarily terminated.
 ステップS153においても、第1直流キャパシタdc1の電圧値(VDC1)が一定値(2E)になるように、第2フライングキャパシタ回路13のスイッチング制御が行われる。スイッチ素子S11(上線付きS12)のオン期間で特定されるデューティD11の長さを増加させる。このようなスイッチング制御により、第2直流キャパシタdc2の放電期間が相対的に長くなり、第1直流キャパシタdc1の電圧値(VDC1)が一定値(2E)になるように増加する。ステップS153の処理後、本ルーチンの処理が一旦終了される。 Also in step S153, switching control of the second flying capacitor circuit 13 is performed so that the voltage value (VDC1) of the first DC capacitor dc1 becomes a constant value (2E). The length of duty D11 specified by the ON period of switch element S11 (overlined S12) is increased. By such switching control, the discharge period of the second DC capacitor dc2 becomes relatively long, and the voltage value (VDC1) of the first DC capacitor dc1 increases to a constant value (2E). After the processing of step S153, the processing of this routine is once terminated.
 以上、説明したように、本実施例に係る電力変換装置1は第3領域においても、フライングキャパシタfc1の電圧値(VFC1)が一定値(E)を超える場合には、スイッチ素子S1(上線付きS2)のデューティD1の長さを減少させ、スイッチ素子S3(上線付きS4)のデューティD3の長さを増加できる。フライングキャパシタfc1の放電期間の長さを相対的に長くなるように制御し、電圧値(VFC1)が一定値(E)になるように減少できる。また、フライングキャパシタfc1の電圧値(VFC1)が一定値(E)未満の場合には、スイッチ素子S1(上線付きS2)のデューティD1の長さを増加させ、スイッチ素子S3(上線付きS4)のデューティD3の長さを減少できる。このような制御により、フライングキャパシタfc1の放電期間が相対的に短くなり、電圧値(VFC1)が一定値(E)になるように増加できる。 As described above, in the power conversion device 1 according to the present embodiment, even in the third region, when the voltage value (VFC1) of the flying capacitor fc1 exceeds the constant value (E), the switch element S1 ( The length of the duty D1 of S2) can be decreased, and the length of the duty D3 of the switch element S3 (S4 with an overlined line) can be increased. By controlling the length of the discharge period of the flying capacitor fc1 to be relatively long, the voltage value (VFC1) can be decreased to a constant value (E). Further, when the voltage value (VFC1) of the flying capacitor fc1 is less than the constant value (E), the length of the duty D1 of the switch element S1 (S2 with the upper line) is increased, and the duty D1 of the switch element S3 (S4 with the upper line) is increased. The length of duty D3 can be reduced. By such control, the discharge period of the flying capacitor fc1 becomes relatively short, and the voltage value (VFC1) can be increased to a constant value (E).
 さらに、第3領域においても、フライングキャパシタfc2の電圧値(VFC2)が一定値(E)を超える場合には、スイッチ素子S9(上線付きS10)のデューティD9の長さを増加させ、スイッチ素子S11(上線付きS12)のデューティD11の長さを減少できる。上記スイッチ素子のスイッチング制御により、フライングキャパシタfc2の放電期間の長さを相対的に長くなるように制御し、電圧値(VFC2)が一定値(E)になるように減少できる。また、フライングキャパシタfc2の電圧値(VFC2)が一定値(E)未満の場合には、スイッチ素子S9(上線付きS10)のデューティD9の長さを減少させ、スイッチ素子S11(上線付きS12)のデューティD11の長さを増加できる。このような制御により、フライングキャパシタfc2の放電期間を相対的に短くし、電圧値(VFC2)が一定値(E)になるように増加できる。 Further, even in the third region, when the voltage value (VFC2) of the flying capacitor fc2 exceeds the constant value (E), the length of the duty D9 of the switch element S9 (S10 with an overlined line) is increased, and the switch element S11 The length of the duty D11 of (S12 with an overline) can be reduced. Through the switching control of the switch element, the length of the discharge period of the flying capacitor fc2 can be controlled to be relatively long, and the voltage value (VFC2) can be reduced to a constant value (E). Further, when the voltage value (VFC2) of the flying capacitor fc2 is less than the constant value (E), the length of the duty D9 of the switch element S9 (S10 with the upper line) is reduced, and the duty D9 of the switch element S11 (S12 with the upper line) is reduced. The length of duty D11 can be increased. By such control, the discharge period of the flying capacitor fc2 can be relatively shortened, and the voltage value (VFC2) can be increased to a constant value (E).
 さらに、第3領域の電圧制御においても、フライングキャパシタfc1の電圧(VFC1)に関する偏差量とフライングキャパシタfc2の電圧(VFC2)に関する偏差量とに応じて、第1直流キャパシタdc1の電圧(VDC1)を連動させて制御するためのスイッチ素子が選定できる。フライングキャパシタfc1の偏差量(|ΔVFC1|)がフライングキャパシタfc2の偏差量(|ΔVFC2|)より小さい場合には、第1直流キャパシタdc1の電圧値(VDC1)を一定値(2E)に制御するためのスイッチ素子S3(上線付きS4)が選定できる。同様にして、フライングキャパシタfc1の偏差量(|ΔVFC1|)がフライングキャパシタfc2の偏差量(|ΔVFC2|)以上の場合には、第1直流キャパシタdc1の電圧値(VDC1)を一定値(2E)に制御するためのスイッチ素子S11(上線付きS12)が選定できる。 Furthermore, in the voltage control in the third region, the voltage (VDC1) of the first DC capacitor dc1 is adjusted according to the deviation amount regarding the voltage (VFC1) of the flying capacitor fc1 and the deviation amount regarding the voltage (VFC2) of the flying capacitor fc2. A switch element for interlocking control can be selected. When the deviation amount (|ΔVFC1|) of the flying capacitor fc1 is smaller than the deviation amount (|ΔVFC2|) of the flying capacitor fc2, the voltage value (VDC1) of the first DC capacitor dc1 is controlled to a constant value (2E). can be selected. Similarly, when the deviation amount (|ΔVFC1|) of the flying capacitor fc1 is equal to or larger than the deviation amount (|ΔVFC2|) of the flying capacitor fc2, the voltage value (VDC1) of the first DC capacitor dc1 is set to a constant value (2E). A switch element S11 (overlined S12) can be selected for controlling
 そして、本実施例に係る電力変換装置1においては、第1直流キャパシタdc1の電圧値(VDC1)が一定値(2E)を超える場合には、スイッチ素子S3(上線付きS4)のデューティD3の長さを減少させ、一定値(2E)未満の場合には、デューティD3の長さを増加できる。本実施例においては、スイッチ素子S3(上線付きS4)のデューティD3の長さに基づいて、第1直流キャパシタdc1の電圧値(VDC1)が一定値(2E)になるように制御できる。 Then, in the power conversion device 1 according to the present embodiment, when the voltage value (VDC1) of the first DC capacitor dc1 exceeds a constant value (2E), the length of the duty D3 of the switch element S3 (S4 with an overlined line) If it is less than a certain value (2E), the length of duty D3 can be increased. In this embodiment, the voltage value (VDC1) of the first DC capacitor dc1 can be controlled to a constant value (2E) based on the length of the duty D3 of the switch element S3 (overlined S4).
 また、本実施例に係る電力変換装置1においては、第1直流キャパシタdc1の電圧値(VDC1)が一定値(2E)を超える場合には、スイッチ素子S11(上線付きS12)のデューティD11の長さを減少させ、一定値(2E)未満の場合には、デューティD11の長さを増加できる。このようなスイッチング制御形態であっても、スイッチ素子S11(上線付きS12)のデューティD11の長さに基づいて、第1直流キャパシタdc1の電圧値(VDC1)が一定値(2E)になるように制御できる。 Further, in the power conversion device 1 according to the present embodiment, when the voltage value (VDC1) of the first DC capacitor dc1 exceeds a constant value (2E), the length of the duty D11 of the switch element S11 (S12 with an overlined line) If it is less than a certain value (2E), the length of duty D11 can be increased. Even in such a switching control form, the voltage value (VDC1) of the first DC capacitor dc1 is set to a constant value (2E) based on the length of the duty D11 of the switch element S11 (S12 with an overlined line). You can control it.
(第4領域)
 図14は、第4領域における電圧制御処理の一例を示すフローチャートである。図14の破線吹き出し領域Z4には、本フローの制御対象になる出力電圧(vo)と出力電流(io)との相対位相領域がハッチングされた矩形領域に例示される。図14のフローにおいて、電圧制御処理の開始後に実行されるステップS161からステップS166の処理では、図11のフローに示すステップS101からステップS106の処理が実行される。
(Fourth area)
FIG. 14 is a flowchart showing an example of voltage control processing in the fourth area. In the broken-line balloon area Z4 in FIG. 14, the relative phase area between the output voltage (vo) and the output current (io) to be controlled in this flow is illustrated as a hatched rectangular area. In the flow of FIG. 14, in the processing of steps S161 to S166 executed after the start of the voltage control processing, the processing of steps S101 to S106 shown in the flow of FIG. 11 is executed.
 すなわち、フライングキャパシタfc1の電圧値(VFC1)が一定値(E)を超える場合には(ステップS161、“>E”)、スイッチ素子S1(上線付きS2)のデューティD1の長さを増加させ、スイッチ素子S3(上線付きS4)のデューティD3の長さを減少させる(ステップS162)。また、フライングキャパシタfc1の電圧値(VFC1)が一定値(E)未満の場合には(ステップS161、“<E”)、スイッチ素子S1(上線付きS2)のデューティD1の長さを減少させ、スイッチ素子S3(上線付きS4)のデューティD3の長さを増加させる(ステップS163)。ステップS162の処理により、フライングキャパシタfc1の放電期間が相対的に長くなり、フライングキャパシタfc1の電圧値(VFC1)が一定値(E)になるように減少する。また、ステップS163の処理により、フライングキャパシタfc1の放電期間が相対的に短くなり、フライングキャパシタfc1の電圧値(VFC1)が一定値(E)になるように増加する。 That is, when the voltage value (VFC1) of the flying capacitor fc1 exceeds a certain value (E) (step S161, ">E"), the length of the duty D1 of the switch element S1 (overlined S2) is increased, The length of duty D3 of switch element S3 (overlined S4) is decreased (step S162). Further, when the voltage value (VFC1) of the flying capacitor fc1 is less than the constant value (E) (step S161, "<E"), the length of the duty D1 of the switch element S1 (overlined S2) is reduced, The length of duty D3 of switch element S3 (overlined S4) is increased (step S163). By the process of step S162, the discharge period of the flying capacitor fc1 becomes relatively long, and the voltage value (VFC1) of the flying capacitor fc1 decreases to a constant value (E). Moreover, the discharge period of the flying capacitor fc1 is relatively shortened by the process of step S163, and the voltage value (VFC1) of the flying capacitor fc1 increases to a constant value (E).
 さらに、フライングキャパシタfc2の電圧値(VFC2)が一定値(E)を超える場合には(ステップS164、“>E”)、スイッチ素子S9(上線付きS10)のデューティD9の長さを減少させ、スイッチ素子S11(上線付きS12)のデューティD11の長さを増加させる(ステップS165)。また、フライングキャパシタfc2の電圧値(VFC2)が一定値(E)未満の場合には(ステップS164、“<E”)、スイッチ素子S9(上線付きS10)のデューティD9の長さを増加させ、スイッチ素子S11(上線付きS12)のデューティD11の長さを減少させる(ステップS166)。ステップS165の処理により、フライングキャパシタfc2の放電期間が相対的に長くなり、フライングキャパシタfc2の電圧値(VFC2)が一定値(E)になるように減少する。また、ステップS166の処理により、フライングキャパシタfc2の放電期間が相対的に短くなり、フライングキャパシタfc2の電圧値(VFC2)が一定値(E)になるように増加する。ステップS166の処理後、処理はステップS167に進む。 Furthermore, when the voltage value (VFC2) of the flying capacitor fc2 exceeds a certain value (E) (step S164, ">E"), the length of the duty D9 of the switch element S9 (S10 with an overlined line) is reduced, The length of the duty D11 of the switch element S11 (overlined S12) is increased (step S165). Further, when the voltage value (VFC2) of the flying capacitor fc2 is less than the constant value (E) (step S164, "<E"), the length of the duty D9 of the switch element S9 (S10 with an overlined line) is increased, The length of duty D11 of switch element S11 (overlined S12) is decreased (step S166). By the process of step S165, the discharge period of the flying capacitor fc2 is relatively lengthened, and the voltage value (VFC2) of the flying capacitor fc2 decreases to a constant value (E). Moreover, the discharge period of the flying capacitor fc2 is relatively shortened by the process of step S166, and the voltage value (VFC2) of the flying capacitor fc2 increases to a constant value (E). After the process of step S166, the process proceeds to step S167.
 ステップS167からステップS173の処理では、図13のフローに示すステップS147からステップS153の処理が実行される。すなわち、フライングキャパシタfc1に対する電圧指令値と電圧センサを通じて取得された電圧値(VFC1)との偏差量(|ΔVFC1|)、フライングキャパシタfc2に対する電圧指令値と電圧センサを通じて取得された電圧値(VFC2)との偏差量(|ΔVFC2|)が求められる。そして、フライングキャパシタfc1の偏差量(|ΔVFC1|)と、フライングキャパシタfc2の偏差量(|ΔVFC2|)との大小判定により、第1直流キャパシタdc1の電圧値を一定値(2E)に制御するためのスイッチ素子が判定される。 In the process from step S167 to step S173, the process from step S147 to step S153 shown in the flow of FIG. 13 is executed. That is, the amount of deviation (|ΔVFC1|) between the voltage command value for the flying capacitor fc1 and the voltage value (VFC1) acquired through the voltage sensor, the voltage command value for the flying capacitor fc2 and the voltage value (VFC2) acquired through the voltage sensor and the amount of deviation (|ΔVFC2|) is obtained. Then, the voltage value of the first DC capacitor dc1 is controlled to a constant value (2E) by judging the difference between the deviation amount (|ΔVFC1|) of the flying capacitor fc1 and the deviation amount (|ΔVFC2|) of the flying capacitor fc2. of switch elements are determined.
 そして、フライングキャパシタfc1の偏差量(|ΔVFC1|)がフライングキャパシタfc2の偏差量(|ΔVFC2|)より小さい場合には(ステップS167、“YES”)、スイッチ素子S3(上線付きS4)が制御対象に選定され、第1直流キャパシタdc1の電圧値を一定値(2E)に制御するための処理が行われる(ステップS168からステップS170)。また、フライングキャパシタfc1の偏差量(|ΔVFC1|)がフライングキャパシタfc2の偏差量(|ΔVFC2|)以上の場合には(ステップS167、“NO”)、スイッチ素子S11(上線付きS12)が制御対象に選定され、第1直流キャパシタdc1の電圧値を一定値(2E)に制御するための処理が行われる(ステップS171からステップS173)。ステップS173の処理後、本ルーチンの処理が一旦終了される。 Then, when the deviation amount (|ΔVFC1|) of the flying capacitor fc1 is smaller than the deviation amount (|ΔVFC2|) of the flying capacitor fc2 (step S167, “YES”), the switch element S3 (overlined S4) is to be controlled. , and a process for controlling the voltage value of the first DC capacitor dc1 to a constant value (2E) is performed (steps S168 to S170). Further, when the deviation amount (|ΔVFC1|) of the flying capacitor fc1 is equal to or larger than the deviation amount (|ΔVFC2|) of the flying capacitor fc2 (step S167, “NO”), the switch element S11 (overlined S12) is to be controlled. , and a process for controlling the voltage value of the first DC capacitor dc1 to a constant value (2E) is performed (steps S171 to S173). After the processing of step S173, the processing of this routine is once terminated.
 以上、説明したように、本実施例に係る電力変換装置1は第4領域においても、フライングキャパシタfc1の電圧値(VFC1)が一定値(E)を超える場合には、スイッチ素子S1(上線付きS2)のデューティD1の長さを増加させ、スイッチ素子S3(上線付きS4)のデューティD3の長さを減少できる。フライングキャパシタfc1の放電期間の長さを相対的に長くなるように制御し、電圧値(VFC1)が一定値(E)になるように減少できる。また、フライングキャパシタfc1の電圧値(VFC1)が一定値(E)未満の場合には、スイッチ素子S1(上線付きS2)のデューティD1の長さを減少させ、スイッチ素子S3(上線付きS4)のデューティD3の長さを増加できる。このような制御により、フライングキャパシタfc1の放電期間が相対的に短くなり、電圧値(VFC1)が一定値(E)になるように増加できる。 As described above, in the power conversion device 1 according to the present embodiment, even in the fourth region, the switching element S1 (overlined The length of the duty D1 of S2) can be increased, and the length of the duty D3 of the switch element S3 (overlined S4) can be decreased. By controlling the length of the discharge period of the flying capacitor fc1 to be relatively long, the voltage value (VFC1) can be decreased to a constant value (E). Further, when the voltage value (VFC1) of the flying capacitor fc1 is less than the constant value (E), the length of the duty D1 of the switch element S1 (S2 with the upper line) is reduced, and the duty D1 of the switch element S3 (S4 with the upper line) is reduced. The length of duty D3 can be increased. By such control, the discharge period of the flying capacitor fc1 becomes relatively short, and the voltage value (VFC1) can be increased to a constant value (E).
 さらに、第4領域においても、フライングキャパシタfc2の電圧値(VFC2)が一定値(E)を超える場合には、スイッチ素子S9(上線付きS10)のデューティD9の長さを減少させ、スイッチ素子S11(上線付きS12)のデューティD11の長さを増加できる。上記スイッチ素子のスイッチング制御により、フライングキャパシタfc2の放電期間の長さを相対的に長くなるように制御し、電圧値(VFC2)が一定値(E)になるように減少できる。また、フライングキャパシタfc2の電圧値(VFC2)が一定値(E)未満の場合には、スイッチ素子S9(上線付きS10)のデューティD9の長さを増加させ、スイッチ素子S11(上線付きS12)のデューティD11の長さを減少できる。このような制御により、フライングキャパシタfc2の放電期間を相対的に短くし、電圧値(VFC2)が一定値(E)になるように増加できる。 Further, even in the fourth region, when the voltage value (VFC2) of the flying capacitor fc2 exceeds the constant value (E), the length of the duty D9 of the switch element S9 (S10 with an overlined line) is reduced, and the switch element S11 (Overlined S12) can increase the length of the duty D11. Through the switching control of the switch element, the length of the discharge period of the flying capacitor fc2 can be controlled to be relatively long, and the voltage value (VFC2) can be reduced to a constant value (E). Further, when the voltage value (VFC2) of the flying capacitor fc2 is less than the constant value (E), the length of the duty D9 of the switch element S9 (S10 with the upper line) is increased, and the duty D9 of the switch element S11 (S12 with the upper line) is The length of duty D11 can be reduced. By such control, the discharge period of the flying capacitor fc2 can be relatively shortened, and the voltage value (VFC2) can be increased to a constant value (E).
 さらに、第4領域の電圧制御においても、フライングキャパシタfc1の電圧(VFC1)に関する偏差量とフライングキャパシタfc2の電圧(VFC2)に関する偏差量とに応じて、第1直流キャパシタdc1の電圧(VDC1)を連動させて制御するためのスイッチ素子が選定できる。フライングキャパシタfc1の偏差量(|ΔVFC1|)がフライングキャパシタfc2の偏差量(|ΔVFC2|)より小さい場合には、第1直流キャパシタdc1の電圧値(VDC1)を一定値(2E)に制御するためのスイッチ素子S3(上線付きS4)が選定できる。同様にして、フライングキャパシタfc1の偏差量(|ΔVFC1|)がフライングキャパシタfc2の偏差量(|ΔVFC2|)以上の場合には、第1直流キャパシタdc1の電圧値(VDC1)を一定値(2E)に制御するためのスイッチ素子S11(上線付きS12)が選定できる。 Furthermore, in the voltage control in the fourth region, the voltage (VDC1) of the first DC capacitor dc1 is changed according to the deviation amount regarding the voltage (VFC1) of the flying capacitor fc1 and the deviation amount regarding the voltage (VFC2) of the flying capacitor fc2. A switch element for interlocking control can be selected. When the deviation amount (|ΔVFC1|) of the flying capacitor fc1 is smaller than the deviation amount (|ΔVFC2|) of the flying capacitor fc2, the voltage value (VDC1) of the first DC capacitor dc1 is controlled to a constant value (2E). can be selected. Similarly, when the deviation amount (|ΔVFC1|) of the flying capacitor fc1 is equal to or larger than the deviation amount (|ΔVFC2|) of the flying capacitor fc2, the voltage value (VDC1) of the first DC capacitor dc1 is set to a constant value (2E). A switch element S11 (overlined S12) can be selected for controlling
 第4領域においても、電力変換装置1は、第1直流キャパシタdc1の電圧値(VDC1)が一定値(2E)を超える場合には、スイッチ素子S3(上線付きS4)のデューティD3の長さを減少させ、一定値(2E)未満の場合には、デューティD3の長さを増加できる。本実施例においては、スイッチ素子S3(上線付きS4)のデューティD3の長さに基づいて、第1直流キャパシタdc1の電圧値(VDC1)が一定値(2E)になるように制御できる。 Also in the fourth region, when the voltage value (VDC1) of the first DC capacitor dc1 exceeds a constant value (2E), the power conversion device 1 sets the length of the duty D3 of the switch element S3 (S4 with an overlined line) to If it is decreased and is less than a constant value (2E), the length of duty D3 can be increased. In this embodiment, the voltage value (VDC1) of the first DC capacitor dc1 can be controlled to a constant value (2E) based on the length of the duty D3 of the switch element S3 (overlined S4).
 また、第1直流キャパシタdc1の電圧値(VDC1)が一定値(2E)を超える場合には、スイッチ素子S11(上線付きS12)のデューティD11の長さを減少させ、一定値(2E)未満の場合には、デューティD11の長さを増加できる。このようなスイッチング制御形態であっても、スイッチ素子S11(上線付きS12)のデューティD11の長さに基づいて、第1直流キャパシタdc1の電圧値(VDC1)が一定値(2E)になるように制御できる。 Further, when the voltage value (VDC1) of the first DC capacitor dc1 exceeds the constant value (2E), the length of the duty D11 of the switch element S11 (overlined S12) is reduced, In this case, the length of duty D11 can be increased. Even in such a switching control form, the voltage value (VDC1) of the first DC capacitor dc1 is set to a constant value (2E) based on the length of the duty D11 of the switch element S11 (S12 with an overlined line). You can control it.
 図15は、本実施例に係る電圧制御方式によるシミュレーション結果を示す図である。シミュレーション条件は、入力電圧が「330V」、出力電圧が「202V」、出力電力が「5500W」、出力周波数が「50Hz」、力率が「1」である。図15の1段目には、時間経過に伴う直流電源V1の入力電圧の推移を表すグラフが例示され、2段目には直流電源V1の入力電流の推移を表すグラフが例示される。同様にして、3段目にはインバータ出力電圧(出力端子Tp3-Tp4間電圧)の推移、4段目にはキャパシタ20に印加される電圧の推移、5段目には出力電流(io)の推移、6段目にはキャパシタ電圧(VFC1、VFC2)の推移、7段目にはDDV(VDC1、VDC2)の推移、8段目には出力電力の推移を表すグラフが例示される。 FIG. 15 is a diagram showing simulation results by the voltage control method according to this embodiment. The simulation conditions are an input voltage of "330 V", an output voltage of "202 V", an output power of "5500 W", an output frequency of "50 Hz", and a power factor of "1". The first stage of FIG. 15 illustrates a graph representing the transition of the input voltage of the DC power supply V1 over time, and the second stage illustrates a graph representing the transition of the input current of the DC power supply V1. Similarly, the transition of the inverter output voltage (the voltage between the output terminals Tp3 and Tp4) is shown in the third stage, the transition of the voltage applied to the capacitor 20 is shown in the fourth stage, and the output current (io) is shown in the fifth stage. Graphs showing transitions, transitions of capacitor voltages (VFC1, VFC2) on the sixth stage, transitions of DDV (VDC1, VDC2) on the seventh stage, and transitions of output power on the eighth stage are exemplified.
 図15の6段目のグラフに示すように、本実施例の電圧制御方式を採用しない場合には、時間経過とともにフライングキャパシタfc1およびfc2の電圧が変動する。例えば、2点鎖線で示されるように、フライングキャパシタfc2の電圧値(VFC2_制御なし)は、時間経過とともに上昇し80V近傍から150V近傍まで変化する。また、1点鎖線で示されるように、フライングキャパシタfc1の電圧値(VFC1_制御なし)は、時間経過とともに下降し80V近傍から30V近傍まで変化する。しかしながら、本実施例の電圧制御方式を採用する場合には、破線に示すようにフライングキャパシタfc1およびfc2の電圧値(VFC1_制御あり、VFC2_制御あり)は粗一定値で推移することがわかる。 As shown in the sixth graph in FIG. 15, the voltages of the flying capacitors fc1 and fc2 fluctuate over time if the voltage control method of this embodiment is not employed. For example, as indicated by the chain double-dashed line, the voltage value of the flying capacitor fc2 (VFC2_no control) rises over time and changes from around 80V to around 150V. Also, as indicated by the one-dot chain line, the voltage value of the flying capacitor fc1 (VFC1_no control) drops over time and changes from around 80V to around 30V. However, when the voltage control method of this embodiment is adopted, the voltage values of the flying capacitors fc1 and fc2 (with VFC1_control, with VFC2_control) change at roughly constant values as indicated by the dashed lines.
 また、図15の7段目のグラフに示すように、本実施例の電圧制御方式を採用しない場合には、時間経過とともに第1直流キャパシタdc1および第2直流キャパシタdc2の電圧も変動する。例えば、1点鎖線で示される第1直流キャパシタdc1の電圧値(Vdc1_制御なし)は、時間経過とともに上昇し165V近傍から166V近傍まで変化する。また、2点鎖線で示される第2直流キャパシタdc2の電圧値(Vdc2_制御なし)は、時間経過とともに下降し165V近傍から164V近傍まで変化する。しかしながら、本実施例の電圧制御方式を採用する場合には、破線で示される第2直流キャパシタdc2の電圧値(Vdc2_制御あり)は、一定値で推移することがわかる。同様にして、実線で示される第1直流キャパシタdc1の電圧値(Vdc1_制御あり)も、一定値で推移することがわかる。 In addition, as shown in the graph on the seventh stage in FIG. 15, the voltages of the first DC capacitor dc1 and the second DC capacitor dc2 also fluctuate over time if the voltage control method of this embodiment is not employed. For example, the voltage value (Vdc1_no control) of the first DC capacitor dc1 indicated by the dashed-dotted line rises over time and changes from around 165V to around 166V. Also, the voltage value of the second DC capacitor dc2 indicated by the two-dot chain line (Vdc2_no control) decreases over time and changes from around 165V to around 164V. However, when the voltage control method of this embodiment is adopted, the voltage value (with Vdc2_control) of the second DC capacitor dc2 indicated by the dashed line changes at a constant value. Similarly, it can be seen that the voltage value of the first DC capacitor dc1 (with Vdc1_control) indicated by the solid line also changes at a constant value.
(その他)
 上記の実施形態はあくまでも一例であって、本実施の形態の開示はその要旨を逸脱しない範囲内で適宜変更して実施し得る。本開示において説明した処理や手段は、技術的な矛盾が生じない限りにおいて、自由に組合せて実施することができる。
(others)
The above-described embodiment is merely an example, and the disclosure of the present embodiment can be modified as appropriate without departing from the gist thereof. The processes and means described in the present disclosure can be freely combined and implemented as long as there is no technical contradiction.
 また、1つの装置が行うものとして説明した処理が、複数の装置によって分担して実行されてもよい。あるいは、異なる装置が行うものとして説明した処理が、1つの装置によって実行されても構わない。コンピュータシステムにおいて、各機能をどのようなハードウェア構成によって実現するかは柔軟に変更可能である。 Further, the processing explained as being performed by one device may be shared and performed by a plurality of devices. Alternatively, processes described as being performed by different devices may be performed by one device. In a computer system, it is possible to flexibly change what kind of hardware configuration realizes each function.
 《コンピュータが読み取り可能な記録媒体》
 情報処理装置その他の機械、装置(以下、コンピュータ等)に上記何れかの機能を実現させるプログラムをコンピュータ等が読み取り可能な記録媒体に記録することができる。そして、コンピュータ等に、この記録媒体のプログラムを読み込ませて実行させることにより、その機能を提供させることができる。
《Computer-readable recording medium》
A computer-readable recording medium can record a program that causes an information processing device or other machine or device (hereinafter referred to as a computer or the like) to implement any of the functions described above. By causing a computer or the like to read and execute the program of this recording medium, the function can be provided.
 ここで、コンピュータ等が読み取り可能な記録媒体とは、データやプログラム等の情報を電気的、磁気的、光学的、機械的、または化学的作用によって蓄積し、コンピュータ等から読み取ることができる記録媒体をいう。このような記録媒体のうちコンピュータ等から取り外し可能なものとしては、例えばフレキシブルディスク、光磁気ディスク、CD-ROM、CD-R/W、DVD、ブルーレイディスク、DAT、8mmテープ、フラッシュメモリなどのメモリカード等がある。また、コンピュータ等に固定された記録媒体としてハードディスクやROM等がある。 Here, a computer-readable recording medium is a recording medium that stores information such as data and programs by electrical, magnetic, optical, mechanical, or chemical action and can be read by a computer, etc. Say. Examples of such recording media that can be removed from a computer or the like include memories such as flexible disks, magneto-optical disks, CD-ROMs, CD-R/Ws, DVDs, Blu-ray disks, DATs, 8 mm tapes, and flash memories. There are cards, etc. In addition, there are a hard disk, a ROM, and the like as recording media fixed to a computer or the like.
 なお、以下には本発明の構成要件と実施例の構成とを対比可能とするために、本発明の構成要件を図面の符号付きで記載しておく。
<発明1>
 制御部(30)と、前記制御部(30)からの制御指令に基づいて複数のスイッチ素子のドレイン端子とソース端子との間を導通または開放し、第1入力端(Tp1)および第2入力端(Tp2)に入力された直流電力を交流電力に変換して第1出力端子(Tp3)および第2出力端子(Tp4)から出力する電力変換部(10)と、を有する電力変換装置(1)であって、
 前記電力変換部(10)は、
  前記第1入力端(Tp1)と前記第2入力端(Tp2)との間に直列に接続された第1直流キャパシタ(dc1)および第2直流キャパシタ(dc2)とを有し、前記第1直流キャパシタ(dc1)の一端が前記第1入力端(Tp1)と接続し、前記第2直流キャパシタ(dc2)の他端が前記第2入力端(Tp2)と接続される直流キャパシタ回路(11)と、
  直列に接続された第1スイッチ素子(S3)、第2スイッチ素子(S1)、第3スイッチ素子(S2)および第4スイッチ素子(S4)と、前記第1スイッチ素子(S3)のソース端子と前記第2スイッチ素子(S1)のドレイン端子との接続点に一端が接続し、他端が前記3スイッチ素子(S2)のソース端子と前記第4スイッチ素子(S4)のドレイン端子との接続点とに接続された第1フライングキャパシタ(fc1)を有する第1キャパシタ回路(12)と、
  直列に接続された第5スイッチ素子(S11)、第6スイッチ素子(S9)、第7スイッチ素子(S10)および第8スイッチ素子(S12)と、前記第5スイッチ素子(S11)のソース端子と前記第6スイッチ素子(S9)のドレイン端子との接続点に一端が接続し、他端が前記7スイッチ素子(S10)のソース端子と前記第8スイッチ素子(S12)のドレイン端子との接続点とに接続された第2フライングキャパシタ(fc2)を有する第2キャパシタ回路(13)と、
  前記第1入力端(Tp1)と前記第2入力端(Tp2)との間に直列に接続された第9スイッチ素子(S5)、第10スイッチ素子(S6)、第11スイッチ素子(S7)および第12スイッチ素子(S8)を有し、前記第9スイッチ素子(S5)のドレイン端子が前記第1入力端(Tp1)に接続され、前記第12スイッチ素子(S8)のソース端子が前記第2入力端(Tp2)に接続される第1出力回路(14)と、
  前記第1入力端(Tp1)と前記第2入力端(Tp2)との間に直列に接続された第13スイッチ素子(S13)、第14スイッチ素子(S14)、第15スイッチ素子(S15)および第16スイッチ素子(S16)を有し、前記第13スイッチ素子(S13)のドレイン端子が前記第1入力端(Tp1)に接続され、前記第16スイッチ素子(S16)のソース端子が前記第2入力端(Tp2)に接続される第2出力回路(15)と、を備え、
 前記第1出力回路(14)の前記第9スイッチ素子(S5)のソース端子と前記第10スイッチ素子(S6)のドレイン端子との接続点は、前記第1キャパシタ回路(12)の前記第1スイッチ素子(S1)のドレイン端子と接続し、前記第11スイッチ素子(S7)のソース端子と前記第12スイッチ素子(S8)のドレイン端子との接続点は、前記第1キャパシタ回路(12)の前記第4スイッチ素子(S4)のソース端子に接続され、前記第10スイッチ素子(S6)のソース端子と前記第11スイッチ素子(S7)のドレイン端子との接続点は、前記直流キャパシタ回路(11)の第1直流キャパシタ(dc1)と第2直流キャパシタ(dc2)との接続点に接続され、
 前記第2出力回路(15)の前記第13スイッチ素子(S13)のソース端子と前記第14スイッチ素子(S14)のドレイン端子との接続点は、前記第2キャパシタ回路(13)の前記第5スイッチ素子(S11)のドレイン端子と接続し、前記第15スイッチ素子(S15)のソース端子と前記第16スイッチ素子(S16)のドレイン端子との接続点は、前記第2キャパシタ回路(13)の前記第8スイッチ素子(S12)のソース端子と接続し、前記第14スイッチ素子(S14)のソース端子と前記第15スイッチ素子(S15)のドレイン端子との接続点は、前記直流キャパシタ回路(11)の第1直流キャパシタ(dc1)と第2直流キャパシタ(dc2)との接続点に接続され、
 前記制御部(30)は、
 前記第1フライングキャパシタ(fc1)の電圧検出値と電圧指令値との偏差量、および、前記第2フライングキャパシタ(fc2)の電圧検出値と電圧指令値との偏差量に基づいて、前記第1直流キャパシタ(dc1)および前記第2直流キャパシタ(dc2)の充放電に関する期間を増加または減少させ、
 第1キャパシタ回路(12)の前記第2スイッチ素子(S1)のソース端子と前記第3スイッチ(S2)のドレイン端子との接続点に接続された前記第2出力端子(Tp4)、および、第2キャパシタ回路(13)の前記第6スイッチ素子(S9)のソース端子と前記第7スイッチ(S10)のドレイン端子との接続点に接続された前記第1出力端子(Tp3)から交流電力を出力する、
 ことを特徴とする電力変換装置(1)。
In order to allow comparison between the constituent elements of the present invention and the configurations of the embodiments, the constituent elements of the present invention will be described below with reference numerals in the drawings.
<Invention 1>
a control unit (30) for conducting or disconnecting between the drain terminal and the source terminal of a plurality of switch elements based on a control command from the control unit (30), a first input terminal (Tp1) and a second input; a power conversion unit (10) that converts DC power input to a terminal (Tp2) into AC power and outputs the power from a first output terminal (Tp3) and a second output terminal (Tp4); ) and
The power conversion unit (10)
a first DC capacitor (dc1) and a second DC capacitor (dc2) connected in series between the first input terminal (Tp1) and the second input terminal (Tp2); a DC capacitor circuit (11) in which one end of the capacitor (dc1) is connected to the first input terminal (Tp1) and the other end of the second DC capacitor (dc2) is connected to the second input terminal (Tp2); ,
A first switch element (S3), a second switch element (S1), a third switch element (S2) and a fourth switch element (S4) connected in series, and a source terminal of the first switch element (S3) One end is connected to the connection point with the drain terminal of the second switch element (S1), and the other end is the connection point between the source terminal of the third switch element (S2) and the drain terminal of the fourth switch element (S4). a first capacitor circuit (12) having a first flying capacitor (fc1) connected to
A fifth switch element (S11), a sixth switch element (S9), a seventh switch element (S10) and an eighth switch element (S12) connected in series, and a source terminal of the fifth switch element (S11) One end is connected to the connection point with the drain terminal of the sixth switch element (S9), and the other end is the connection point between the source terminal of the seventh switch element (S10) and the drain terminal of the eighth switch element (S12). a second capacitor circuit (13) having a second flying capacitor (fc2) connected to
A ninth switch element (S5), a tenth switch element (S6), an eleventh switch element (S7) connected in series between the first input terminal (Tp1) and the second input terminal (Tp2), and A twelfth switch element (S8) is provided, the drain terminal of the ninth switch element (S5) is connected to the first input terminal (Tp1), and the source terminal of the twelfth switch element (S8) is connected to the second switch element (S8). a first output circuit (14) connected to the input terminal (Tp2);
A thirteenth switch element (S13), a fourteenth switch element (S14), a fifteenth switch element (S15) connected in series between the first input terminal (Tp1) and the second input terminal (Tp2), and A 16th switch element (S16) is provided, the drain terminal of the 13th switch element (S13) is connected to the first input terminal (Tp1), and the source terminal of the 16th switch element (S16) is connected to the second input terminal (Tp1). a second output circuit (15) connected to the input terminal (Tp2);
A connection point between the source terminal of the ninth switch element (S5) of the first output circuit (14) and the drain terminal of the tenth switch element (S6) is the first switch element of the first capacitor circuit (12). The connection point between the drain terminal of the switch element (S1) and the source terminal of the eleventh switch element (S7) and the drain terminal of the twelfth switch element (S8) is the connection point of the first capacitor circuit (12). The connection point between the source terminal of the fourth switch element (S4) and the source terminal of the tenth switch element (S6) and the drain terminal of the eleventh switch element (S7) is the DC capacitor circuit (11 ) is connected to the connection point between the first DC capacitor (dc1) and the second DC capacitor (dc2),
The connection point between the source terminal of the thirteenth switch element (S13) of the second output circuit (15) and the drain terminal of the fourteenth switch element (S14) is the fifth switch element of the second capacitor circuit (13). The connection point between the source terminal of the fifteenth switch element (S15) and the drain terminal of the sixteenth switch element (S16) is connected to the drain terminal of the switch element (S11), and the connection point of the second capacitor circuit (13) is connected to the drain terminal of the switch element (S11). The connection point between the source terminal of the eighth switch element (S12) and the source terminal of the fourteenth switch element (S14) and the drain terminal of the fifteenth switch element (S15) is the DC capacitor circuit (11 ) is connected to the connection point between the first DC capacitor (dc1) and the second DC capacitor (dc2),
The control unit (30)
The first increasing or decreasing the period for charging and discharging the DC capacitor (dc1) and the second DC capacitor (dc2);
the second output terminal (Tp4) connected to the connection point between the source terminal of the second switch element (S1) of the first capacitor circuit (12) and the drain terminal of the third switch (S2); AC power is output from the first output terminal (Tp3) connected to the connection point between the source terminal of the sixth switch element (S9) and the drain terminal of the seventh switch (S10) of the two-capacitor circuit (13). do,
A power converter (1) characterized by:
1   電力変換装置
10  電力変換部
11  直流キャパシタ回路
12  第1フライングキャパシタ回路
13  第2フライングキャパシタ回路
14  第1出力回路
15  第2出力回路
20  フィルタ部
30  制御部
50  負荷
101 プロセッサ
102 主記憶装置
103 補助記憶装置
104 通信IF
105 入出力IF
106 接続バス
dc1 第1直流キャパシタ
dc2 第2直流キャパシタ
fc1 フライングキャパシタ(第1フライングキャパシタ)
fc2 フライングキャパシタ(第2フライングキャパシタ)
S1、S2、S3、S4、S5、S6、S7、S8、S9、S10、S11、S12、S13、S14、S15、S16 スイッチ素子
Tp1、Tp2 入力端子
Tp3、Tp4 出力端子
V1 直流電源
1 power conversion device 10 power conversion section 11 DC capacitor circuit 12 first flying capacitor circuit 13 second flying capacitor circuit 14 first output circuit 15 second output circuit 20 filter section 30 control section 50 load 101 processor 102 main storage device 103 auxiliary Storage device 104 Communication IF
105 input/output IF
106 connection bus dc1 first DC capacitor dc2 second DC capacitor fc1 flying capacitor (first flying capacitor)
fc2 flying capacitor (second flying capacitor)
S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16 Switch elements Tp1, Tp2 Input terminals Tp3, Tp4 Output terminal V1 DC power supply

Claims (14)

  1.  制御部と、前記制御部からの制御指令に基づいて複数のスイッチ素子のドレイン端子とソース端子との間を導通または開放し、第1入力端および第2入力端に入力された直流電力を交流電力に変換して第1出力端子および第2出力端子から出力する電力変換部と、を有する電力変換装置であって、
     前記電力変換部は、
      前記第1入力端と前記第2入力端との間に直列に接続された第1直流キャパシタおよび第2直流キャパシタとを有し、前記第1直流キャパシタの一端が前記第1入力端と接続し、前記第2直流キャパシタの他端が前記第2入力端と接続される直流キャパシタ回路と、
      直列に接続された第1スイッチ素子、第2スイッチ素子、第3スイッチ素子および第4スイッチ素子と、前記第1スイッチ素子のソース端子と前記第2スイッチ素子のドレイン端子との接続点に一端が接続し、他端が前記3スイッチ素子のソース端子と前記第4スイッチ素子のドレイン端子との接続点とに接続された第1フライングキャパシタを有する第1キャパシタ回路と、
      直列に接続された第5スイッチ素子、第6スイッチ素子、第7スイッチ素子および第8スイッチ素子と、前記第5スイッチ素子のソース端子と前記第6スイッチ素子のドレイン端子との接続点に一端が接続し、他端が前記7スイッチ素子のソース端子と前記第8スイッチ素子のドレイン端子との接続点とに接続された第2フライングキャパシタを有する第2キャパシタ回路と、
      前記第1入力端と前記第2入力端との間に直列に接続された第9スイッチ素子、第10スイッチ素子、第11スイッチ素子および第12スイッチ素子を有し、前記第9スイッチ素子のドレイン端子が前記第1入力端に接続され、前記第12スイッチ素子のソース端子が前記第2入力端に接続される第1出力回路と、
      前記第1入力端と前記第2入力端との間に直列に接続された第13スイッチ素子、第14スイッチ素子、第15スイッチ素子および第16スイッチ素子を有し、前記第13スイッチ素子のドレイン端子が前記第1入力端に接続され、前記第16スイッチ素子のソース端子が前記第2入力端に接続される第2出力回路と、を備え、
     前記第1出力回路の前記第9スイッチ素子のソース端子と前記第10スイッチ素子のドレイン端子との接続点は、前記第1キャパシタ回路の前記第1スイッチ素子のドレイン端子と接続し、前記第11スイッチ素子のソース端子と前記第12スイッチ素子のドレイン端子との接続点は、前記第1キャパシタ回路の前記第4スイッチ素子のソース端子に接続され、前記第10スイッチ素子のソース端子と前記第11スイッチ素子のドレイン端子との接続点は、前記直流キャパシタ回路の第1直流キャパシタと第2直流キャパシタとの接続点に接続され、
     前記第2出力回路の前記第13スイッチ素子のソース端子と前記第14スイッチ素子のドレイン端子との接続点は、前記第2キャパシタ回路の前記第5スイッチ素子のドレイン端子と接続し、前記第15スイッチ素子のソース端子と前記第16スイッチ素子のドレイン端子との接続点は、前記第2キャパシタ回路の前記第8スイッチ素子のソース端子と接続し、前記第14スイッチ素子のソース端子と前記第15スイッチ素子のドレイン端子との接続点は、前記直流キャパシタ回路の第1直流キャパシタと第2直流キャパシタとの接続点に接続され、
     前記制御部は、
     前記第1フライングキャパシタの電圧検出値と電圧指令値との偏差量、および、前記第2フライングキャパシタの電圧検出値と電圧指令値との偏差量に基づいて、前記第1直流キャパシタおよび前記第2直流キャパシタの充放電に関する期間を増加または減少させ、 第1キャパシタ回路の前記第2スイッチ素子のソース端子と前記第3スイッチのドレイン端子との接続点に接続された前記第2出力端子、および、第2キャパシタ回路の前記第6スイッチ素子のソース端子と前記第7スイッチのドレイン端子との接続点に接続された前記第1出力端子から交流電力を出力する、
     ことを特徴とする電力変換装置。
    a control unit, and based on a control command from the control unit, conductive or open between the drain terminal and the source terminal of the plurality of switch elements, and converts the DC power input to the first input terminal and the second input terminal to the AC power; A power conversion device having a power conversion unit that converts into power and outputs from a first output terminal and a second output terminal,
    The power conversion unit is
    a first DC capacitor and a second DC capacitor connected in series between the first input terminal and the second input terminal, wherein one end of the first DC capacitor is connected to the first input terminal; , a DC capacitor circuit in which the other end of the second DC capacitor is connected to the second input terminal;
    one end at a connection point between a first switch element, a second switch element, a third switch element and a fourth switch element connected in series and a source terminal of the first switch element and a drain terminal of the second switch element; a first capacitor circuit having a first flying capacitor connected at the other end to a connection point between the source terminal of the three switch elements and the drain terminal of the fourth switch element;
    one end at a connection point between a fifth switching element, a sixth switching element, a seventh switching element and an eighth switching element connected in series and a source terminal of the fifth switching element and a drain terminal of the sixth switching element; a second capacitor circuit having a second flying capacitor connected at the other end to a connection point between the source terminal of the seven switch elements and the drain terminal of the eighth switch element;
    a ninth switch element, a tenth switch element, an eleventh switch element, and a twelfth switch element connected in series between the first input terminal and the second input terminal, the drain of the ninth switch element a first output circuit having a terminal connected to the first input terminal and a source terminal of the twelfth switch element connected to the second input terminal;
    a thirteenth switch element, a fourteenth switch element, a fifteenth switch element, and a sixteenth switch element connected in series between the first input terminal and the second input terminal, the drain of the thirteenth switch element a second output circuit having a terminal connected to the first input terminal and a source terminal of the sixteenth switch element connected to the second input terminal;
    A connection point between the source terminal of the ninth switch element of the first output circuit and the drain terminal of the tenth switch element is connected to the drain terminal of the first switch element of the first capacitor circuit, and the eleventh A connection point between the source terminal of the switch element and the drain terminal of the twelfth switch element is connected to the source terminal of the fourth switch element of the first capacitor circuit, and the source terminal of the tenth switch element and the eleventh switch element are connected to the source terminal of the fourth switch element. a connection point between the switch element and the drain terminal is connected to a connection point between the first DC capacitor and the second DC capacitor of the DC capacitor circuit;
    A connection point between the source terminal of the thirteenth switching element and the drain terminal of the fourteenth switching element of the second output circuit is connected to the drain terminal of the fifth switching element of the second capacitor circuit, and the fifteenth A connection point between the source terminal of the switch element and the drain terminal of the sixteenth switch element is connected to the source terminal of the eighth switch element of the second capacitor circuit, and the source terminal of the fourteenth switch element and the fifteenth switch element are connected to the source terminal of the eighth switch element. a connection point between the switch element and the drain terminal is connected to a connection point between the first DC capacitor and the second DC capacitor of the DC capacitor circuit;
    The control unit
    Based on the amount of deviation between the detected voltage value of the first flying capacitor and the voltage command value and the amount of deviation between the detected voltage value of the second flying capacitor and the voltage command value, a second output terminal that increases or decreases the period for charging and discharging a DC capacitor and is connected to a connection point between the source terminal of the second switch element of the first capacitor circuit and the drain terminal of the third switch; AC power is output from the first output terminal connected to a connection point between the source terminal of the sixth switch element and the drain terminal of the seventh switch of the second capacitor circuit;
    A power conversion device characterized by:
  2.  前記制御部は、
     前記交流電力の電流極性が正側であり、前記第1フライングキャパシタの電圧検出値が第1電圧値を超える場合には、前記第1キャパシタ回路の前記第2スイッチ素子の閉期間を増加させ、前記第1スイッチ素子の閉期間を減少させるとともに、前記第1フライングキャパシタの電圧検出値が第1電圧値未満の場合には、前記第1キャパシタ回路の前記第2スイッチ素子の閉期間を減少させ、前記第1スイッチ素子の閉期間を増加させる、ことを特徴とする請求項1に記載の電力変換装置。
    The control unit
    when the current polarity of the AC power is on the positive side and the voltage detection value of the first flying capacitor exceeds the first voltage value, increasing the closing period of the second switch element of the first capacitor circuit; reducing the closed period of the first switch element and reducing the closed period of the second switch element of the first capacitor circuit when the voltage detection value of the first flying capacitor is less than the first voltage value; , increasing the closed period of the first switch element.
  3.  前記制御部は、
     前記交流電力の電流極性が正側であり、前記第2フライングキャパシタの電圧検出値が第1電圧値を超える場合には、前記第2キャパシタ回路の前記第6スイッチ素子の閉期間を減少させ、前記第5スイッチ素子の閉期間を増加させるとともに、前記第2フライングキャパシタの電圧検出値が第1電圧値未満の場合には、前記第2キャパシタ回路の前記第6スイッチ素子の閉期間を増加させ、前記第5スイッチ素子の閉期間を減少させる、ことを特徴とする請求項1または2に記載の電力変換装置。
    The control unit
    when the current polarity of the AC power is on the positive side and the voltage detection value of the second flying capacitor exceeds the first voltage value, reducing the closed period of the sixth switch element of the second capacitor circuit; increasing the closed period of the fifth switch element and increasing the closed period of the sixth switch element of the second capacitor circuit when the detected voltage value of the second flying capacitor is less than the first voltage value; 3. The power converter according to claim 1, wherein the closed period of the fifth switch element is reduced.
  4.  前記制御部は、
     前記交流電力の電流極性が負側であり、前記第1フライングキャパシタの電圧検出値が第1電圧値を超える場合には、前記第1キャパシタ回路の前記第2スイッチ素子の閉期間を減少させ、前記第1スイッチ素子の閉期間を増加させるとともに、前記第1フライングキャパシタの電圧検出値が第1電圧値未満の場合には、前記第1キャパシタ回路の前記第2スイッチ素子の閉期間を増加させ、前記第1スイッチ素子の閉期間を減少させる、ことを特徴とする請求項1から3の何れか一項に記載の電力変換装置。
    The control unit
    when the current polarity of the AC power is negative and the voltage detection value of the first flying capacitor exceeds the first voltage value, reducing the closed period of the second switch element of the first capacitor circuit, increasing the closed period of the first switch element, and increasing the closed period of the second switch element of the first capacitor circuit when the voltage detection value of the first flying capacitor is less than the first voltage value; 4. The power converter according to any one of claims 1 to 3, wherein the closing period of the first switch element is reduced.
  5.  前記制御部は、
     前記交流電力の電流極性が負側であり、前記第2フライングキャパシタの電圧検出値が第1電圧値を超える場合には、前記第2キャパシタ回路の前記第6スイッチ素子の閉期間を増加させ、前記第5スイッチ素子の閉期間を減少させるとともに、前記第2フライングキャパシタの電圧検出値が第1電圧値未満の場合には、前記第2キャパシタ回路の前記第6スイッチ素子の閉期間を減少させ、前記第5スイッチ素子の閉期間を増加させる、ことを特徴とする請求項1から4の何れか一項に記載の電力変換装置。
    The control unit
    when the current polarity of the AC power is negative and the voltage detection value of the second flying capacitor exceeds the first voltage value, increasing the closed period of the sixth switch element of the second capacitor circuit, reducing the closed period of the fifth switch element and reducing the closed period of the sixth switch element of the second capacitor circuit when the voltage detection value of the second flying capacitor is less than the first voltage value; , increasing the closed period of the fifth switch element.
  6.  前記制御部は、
     前記交流電力の電圧極性が正側であり、前記電流極性が正側のときには、
     前記第2フライングキャパシタの電圧検出値と電圧指令値との偏差量が前記第1フライングキャパシタの電圧検出値と電圧指令値との偏差量より大きいことを条件として、前記第1直流キャパシタの電圧検出値が第2電圧値を超える場合には、前記第1キャパシタ回路の前記第1スイッチ素子の閉期間を増加させ、前記第1直流キャパシタの電圧検出値が第2電圧値未満の場合には、前記第1キャパシタ回路の前記第1スイッチ素子の閉期間を減少させる、ことを特徴とする請求項2または3に記載の電力変換装置。
    The control unit
    When the voltage polarity of the AC power is positive and the current polarity is positive,
    Voltage detection of the first DC capacitor on the condition that the amount of deviation between the voltage detection value of the second flying capacitor and the voltage command value is greater than the deviation amount of the voltage detection value of the first flying capacitor and the voltage command value. If the value exceeds a second voltage value, the closed period of the first switch element of the first capacitor circuit is increased, and if the detected voltage value of the first DC capacitor is less than the second voltage value, 4. The power converter according to claim 2, wherein the closed period of said first switch element of said first capacitor circuit is reduced.
  7.  前記制御部は、
     前記交流電力の電圧極性が正側であり、前記電流極性が正側のときには、
     前記第2フライングキャパシタの電圧検出値と電圧指令値との偏差量が前記第1フライングキャパシタの電圧検出値と電圧指令値との偏差量より小さいことを条件として、前記第1直流キャパシタの電圧検出値が第2電圧値を超える場合には、前記第2キャパシタ回路の前記第5スイッチ素子の閉期間を増加させ、前記第1直流キャパシタの電圧検出値が第2電圧値未満の場合には、前記第2キャパシタ回路の前記第5スイッチ素子の閉期間を減少させる、ことを特徴とする請求項2または3に記載の電力変換装置。
    The control unit
    When the voltage polarity of the AC power is positive and the current polarity is positive,
    Voltage detection of the first DC capacitor on the condition that the amount of deviation between the voltage detection value of the second flying capacitor and the voltage command value is smaller than the deviation amount of the voltage detection value of the first flying capacitor and the voltage command value. If the value exceeds the second voltage value, the closed period of the fifth switch element of the second capacitor circuit is increased, and if the detected voltage value of the first DC capacitor is less than the second voltage value, 4. The power conversion apparatus according to claim 2, wherein the closed period of said fifth switch element of said second capacitor circuit is reduced.
  8.  前記制御部は、
     前記交流電力の電圧極性が負側であり、前記電流極性が負側のときには、
     前記第2フライングキャパシタの電圧検出値と電圧指令値との偏差量が前記第1フライングキャパシタの電圧検出値と電圧指令値との偏差量より大きいことを条件として、前記第1直流キャパシタの電圧検出値が第2電圧値を超える場合には、前記第1キャパシタ回路の前記第1スイッチ素子の閉期間を増加させ、前記第1直流キャパシタの電圧検出値が第2電圧値未満の場合には、前記第1キャパシタ回路の前記第1スイッチ素子の閉期間を減少させる、ことを特徴とする請求項4または5に記載の電力変換装置。
    The control unit
    When the voltage polarity of the AC power is negative and the current polarity is negative,
    Voltage detection of the first DC capacitor on the condition that the amount of deviation between the voltage detection value of the second flying capacitor and the voltage command value is greater than the deviation amount of the voltage detection value of the first flying capacitor and the voltage command value. If the value exceeds a second voltage value, the closed period of the first switch element of the first capacitor circuit is increased, and if the detected voltage value of the first DC capacitor is less than the second voltage value, 6. The power converter according to claim 4, wherein the closed period of said first switch element of said first capacitor circuit is reduced.
  9.  前記制御部は、
     前記交流電力の電圧極性が負側であり、前記電流極性が負側のときには、
     前記第2フライングキャパシタの電圧検出値と電圧指令値との偏差量が前記第1フライングキャパシタの電圧検出値と電圧指令値との偏差量より小さいことを条件として、前記第1直流キャパシタの電圧検出値が第2電圧値を超える場合には、前記第2キャパシタ回路の前記第5スイッチ素子の閉期間を増加させ、前記第1直流キャパシタの電圧検出値が第2電圧値未満の場合には、前記第2キャパシタ回路の前記第5スイッチ素子の閉期間を減少させる、ことを特徴とする請求項4または5に記載の電力変換装置。
    The control unit
    When the voltage polarity of the AC power is negative and the current polarity is negative,
    Voltage detection of the first DC capacitor on the condition that the amount of deviation between the voltage detection value of the second flying capacitor and the voltage command value is smaller than the deviation amount of the voltage detection value of the first flying capacitor and the voltage command value. If the value exceeds the second voltage value, the closed period of the fifth switch element of the second capacitor circuit is increased, and if the detected voltage value of the first DC capacitor is less than the second voltage value, 6. The power converter according to claim 4, wherein the closed period of said fifth switch element of said second capacitor circuit is reduced.
  10.  前記制御部は、
     前記交流電力の電圧極性が負側であり、前記電流極性が正側のときには、
     前記第2フライングキャパシタの電圧検出値と電圧指令値との偏差量が前記第1フライングキャパシタの電圧検出値と電圧指令値との偏差量より大きいことを条件として、前記第1直流キャパシタの電圧検出値が第2電圧値を超える場合には、前記第1キャパシタ回路の前記第1スイッチ素子の閉期間を減少させ、前記第1直流キャパシタの電圧検出値が第2電圧値未満の場合には、前記第1キャパシタ回路の前記第1スイッチ素子の閉期間を増加させる、ことを特徴とする請求項2または3に記載の電力変換装置。
    The control unit
    When the voltage polarity of the AC power is negative and the current polarity is positive,
    Voltage detection of the first DC capacitor on the condition that the amount of deviation between the voltage detection value of the second flying capacitor and the voltage command value is greater than the deviation amount of the voltage detection value of the first flying capacitor and the voltage command value. If the value exceeds a second voltage value, the closed period of the first switch element of the first capacitor circuit is decreased, and if the detected voltage value of the first DC capacitor is less than the second voltage value, 4. The power converter according to claim 2, wherein the closed period of said first switch element of said first capacitor circuit is increased.
  11.  前記制御部は、
     前記交流電力の電圧極性が負側であり、前記電流極性が正側のときには、
     前記第2フライングキャパシタの電圧検出値と電圧指令値との偏差量が前記第1フライングキャパシタの電圧検出値と電圧指令値との偏差量より小さいことを条件として、前記第1直流キャパシタの電圧検出値が第2電圧値を超える場合には、前記第2キャパシタ回路の前記第5スイッチ素子の閉期間を減少させ、前記第1直流キャパシタの電圧検出値が第2電圧値未満の場合には、前記第2キャパシタ回路の前記第5スイッチ素子の閉期間を増加させる、ことを特徴とする請求項2または3に記載の電力変換装置。
    The control unit
    When the voltage polarity of the AC power is negative and the current polarity is positive,
    Voltage detection of the first DC capacitor on the condition that the amount of deviation between the voltage detection value of the second flying capacitor and the voltage command value is smaller than the deviation amount of the voltage detection value of the first flying capacitor and the voltage command value. If the value exceeds a second voltage value, the closed period of the fifth switch element of the second capacitor circuit is decreased, and if the detected voltage value of the first DC capacitor is less than the second voltage value, 4. The power converter according to claim 2, wherein the closed period of said fifth switch element of said second capacitor circuit is increased.
  12.  前記制御部は、
     前記交流電力の電圧極性が正側であり、前記電流極性が負側のときには、
     前記第2フライングキャパシタの電圧検出値と電圧指令値との偏差量が前記第1フライングキャパシタの電圧検出値と電圧指令値との偏差量より大きいことを条件として、前記第1直流キャパシタの電圧検出値が第2電圧値を超える場合には、前記第1キャパシタ回路の前記第1スイッチ素子の閉期間を減少させ、前記第1直流キャパシタの電圧検出値が第2電圧値未満の場合には、前記第1キャパシタ回路の前記第1スイッチ素子の閉期間を増加させる、ことを特徴とする請求項4または5に記載の電力変換装置。
    The control unit
    When the voltage polarity of the AC power is positive and the current polarity is negative,
    Voltage detection of the first DC capacitor on the condition that the amount of deviation between the voltage detection value of the second flying capacitor and the voltage command value is greater than the deviation amount of the voltage detection value of the first flying capacitor and the voltage command value. If the value exceeds a second voltage value, the closed period of the first switch element of the first capacitor circuit is decreased, and if the detected voltage value of the first DC capacitor is less than the second voltage value, 6. The power converter according to claim 4, wherein the closed period of said first switch element of said first capacitor circuit is increased.
  13.  前記制御部は、
     前記交流電力の電圧極性が正側であり、前記電流極性が負側のときには、
     前記第2フライングキャパシタの電圧検出値と電圧指令値との偏差量が前記第1フライングキャパシタの電圧検出値と電圧指令値との偏差量より小さいことを条件として、前記第1直流キャパシタの電圧検出値が第2電圧値を超える場合には、前記第2キャパシタ回路の前記第5スイッチ素子の閉期間を減少させ、前記第1直流キャパシタの電圧検出値が第2電圧値未満の場合には、前記第2キャパシタ回路の前記第5スイッチ素子の閉期間を増加させる、ことを特徴とする請求項4または5に記載の電力変換装置。
    The control unit
    When the voltage polarity of the AC power is positive and the current polarity is negative,
    Voltage detection of the first DC capacitor on the condition that the amount of deviation between the voltage detection value of the second flying capacitor and the voltage command value is smaller than the deviation amount of the voltage detection value of the first flying capacitor and the voltage command value. If the value exceeds a second voltage value, the closed period of the fifth switch element of the second capacitor circuit is decreased, and if the detected voltage value of the first DC capacitor is less than the second voltage value, 6. The power converter according to claim 4, wherein the closed period of said fifth switch element of said second capacitor circuit is increased.
  14.  制御部と、前記制御部からの制御指令に基づいて複数のスイッチ素子のドレイン端子とソース端子との間を導通または開放し、第1入力端および第2入力端に入力された直流電力を交流電力に変換して第1出力端子および第2出力端子から出力する電力変換部と、を有する電力変換装置の制御方法であって、
     前記電力変換部は、
      前記第1入力端と前記第2入力端との間に直列に接続された第1直流キャパシタおよび第2直流キャパシタとを有し、前記第1直流キャパシタの一端が前記第1入力端と接続し、前記第2直流キャパシタの他端が前記第2入力端と接続される直流キャパシタ回路と、
      直列に接続された第1スイッチ素子、第2スイッチ素子、第3スイッチ素子および第4スイッチ素子と、前記第1スイッチ素子のソース端子と前記第2スイッチ素子のドレイン端子との接続点に一端が接続し、他端が前記3スイッチ素子のソース端子と前記第4スイッチ素子のドレイン端子との接続点とに接続された第1フライングキャパシタを有する第1キャパシタ回路と、
      直列に接続された第5スイッチ素子、第6スイッチ素子、第7スイッチ素子および第8スイッチ素子と、前記第5スイッチ素子のソース端子と前記第6スイッチ素子のドレイン端子との接続点に一端が接続し、他端が前記7スイッチ素子のソース端子と前記第8スイッチ素子のドレイン端子との接続点とに接続された第2フライングキャパシタを有する第2キャパシタ回路と、
      前記第1入力端と前記第2入力端との間に直列に接続された第9スイッチ素子、第10スイッチ素子、第11スイッチ素子および第12スイッチ素子を有し、前記第9スイッチ素子のドレイン端子が前記第1入力端に接続され、前記第12スイッチ素子のソース端子が前記第2入力端に接続される第1出力回路と、
      前記第1入力端と前記第2入力端との間に直列に接続された第13スイッチ素子、第14スイッチ素子、第15スイッチ素子および第16スイッチ素子を有し、前記第13スイッチ素子のドレイン端子が前記第1入力端に接続され、前記第16スイッチ素子のソース端子が前記第2入力端に接続される第2出力回路と、を備え、
     前記第1出力回路の前記第9スイッチ素子のソース端子と前記第10スイッチ素子のドレイン端子との接続点は、前記第1キャパシタ回路の前記第1スイッチ素子のドレイン端子と接続し、前記第11スイッチ素子のソース端子と前記第12スイッチ素子のドレイン端子との接続点は、前記第1キャパシタ回路の前記第4スイッチ素子のソース端子に接続され、前記第10スイッチ素子のソース端子と前記第11スイッチ素子のドレイン端子との接続点は、前記直流キャパシタ回路の第1直流キャパシタと第2直流キャパシタとの接続点に接続され、
     前記第2出力回路の前記第13スイッチ素子のソース端子と前記第14スイッチ素子のドレイン端子との接続点は、前記第2キャパシタ回路の前記第5スイッチ素子のドレイン端子と接続し、前記第15スイッチ素子のソース端子と前記第16スイッチ素子のドレイン端子との接続点は、前記第2キャパシタ回路の前記第8スイッチ素子のソース端子と接続し、前記第14スイッチ素子のソース端子と前記第15スイッチ素子のドレイン端子との接続点は、前記直流キャパシタ回路の第1直流キャパシタと第2直流キャパシタとの接続点に接続され、
     前記制御部は、
     前記第1フライングキャパシタの電圧検出値と電圧指令値との偏差、および、前記第2フライングキャパシタの電圧検出値と電圧指令値との偏差に基づいて、前記第1直流キャパシタおよび前記第2直流キャパシタの充放電に関する期間を増加または減少させ、
     第1キャパシタ回路の前記第2スイッチ素子のソース端子と前記第3スイッチのドレイン端子との接続点に接続された前記第2出力端子、および、第2キャパシタ回路の前記第6スイッチ素子のソース端子と前記第7スイッチのドレイン端子との接続点に接続された前記第1出力端子から交流電力を出力する、
     ことを実行する制御方法。
    a control unit, and based on a control command from the control unit, conductive or open between the drain terminal and the source terminal of the plurality of switch elements, and converts the DC power input to the first input terminal and the second input terminal to the AC power; A control method for a power conversion device having a power conversion unit that converts into power and outputs from a first output terminal and a second output terminal,
    The power conversion unit is
    a first DC capacitor and a second DC capacitor connected in series between the first input terminal and the second input terminal, wherein one end of the first DC capacitor is connected to the first input terminal; , a DC capacitor circuit in which the other end of the second DC capacitor is connected to the second input terminal;
    one end at a connection point between a first switch element, a second switch element, a third switch element and a fourth switch element connected in series and a source terminal of the first switch element and a drain terminal of the second switch element; a first capacitor circuit having a first flying capacitor connected at the other end to a connection point between the source terminal of the three switch elements and the drain terminal of the fourth switch element;
    one end at a connection point between a fifth switching element, a sixth switching element, a seventh switching element and an eighth switching element connected in series and a source terminal of the fifth switching element and a drain terminal of the sixth switching element; a second capacitor circuit having a second flying capacitor connected at the other end to a connection point between the source terminal of the seven switch elements and the drain terminal of the eighth switch element;
    a ninth switch element, a tenth switch element, an eleventh switch element, and a twelfth switch element connected in series between the first input terminal and the second input terminal, the drain of the ninth switch element a first output circuit having a terminal connected to the first input terminal and a source terminal of the twelfth switch element connected to the second input terminal;
    a thirteenth switch element, a fourteenth switch element, a fifteenth switch element, and a sixteenth switch element connected in series between the first input terminal and the second input terminal, the drain of the thirteenth switch element a second output circuit having a terminal connected to the first input terminal and a source terminal of the sixteenth switch element connected to the second input terminal;
    A connection point between the source terminal of the ninth switch element of the first output circuit and the drain terminal of the tenth switch element is connected to the drain terminal of the first switch element of the first capacitor circuit, and the eleventh A connection point between the source terminal of the switch element and the drain terminal of the twelfth switch element is connected to the source terminal of the fourth switch element of the first capacitor circuit, and the source terminal of the tenth switch element and the eleventh switch element are connected to the source terminal of the fourth switch element. a connection point between the switch element and the drain terminal is connected to a connection point between the first DC capacitor and the second DC capacitor of the DC capacitor circuit;
    A connection point between the source terminal of the thirteenth switching element and the drain terminal of the fourteenth switching element of the second output circuit is connected to the drain terminal of the fifth switching element of the second capacitor circuit, and the fifteenth A connection point between the source terminal of the switch element and the drain terminal of the sixteenth switch element is connected to the source terminal of the eighth switch element of the second capacitor circuit, and the source terminal of the fourteenth switch element and the fifteenth switch element are connected to the source terminal of the eighth switch element. a connection point between the switch element and the drain terminal is connected to a connection point between the first DC capacitor and the second DC capacitor of the DC capacitor circuit;
    The control unit
    Based on the deviation between the voltage detection value and the voltage command value of the first flying capacitor and the deviation between the voltage detection value and the voltage command value of the second flying capacitor, the first DC capacitor and the second DC capacitor increase or decrease the period of charge and discharge of
    the second output terminal connected to a connection point between the source terminal of the second switch element of the first capacitor circuit and the drain terminal of the third switch; and the source terminal of the sixth switch element of the second capacitor circuit. and outputting AC power from the first output terminal connected to the connection point of the drain terminal of the seventh switch,
    How to control how things are done.
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TOBIAS GEYER ; SILVIA MASTELLONE: "Model Predictive Direct Torque Control of a Five-Level ANPC Converter Drive System", IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS., IEEE SERVICE CENTER, PISCATAWAY, NJ., US, vol. 48, no. 5, 1 September 2012 (2012-09-01), US , pages 1565 - 1575, XP011461568, ISSN: 0093-9994, DOI: 10.1109/TIA.2012.2210174 *

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