WO2022161101A1

WO2022161101A1 - Uboot startup method and apparatus for multi-core system on chip, and device and storage medium

Info

Publication number: WO2022161101A1
Application number: PCT/CN2021/143252
Authority: WO
Inventors: 刘刚
Original assignee: 苏州浪潮智能科技有限公司
Priority date: 2021-01-29
Filing date: 2021-12-30
Publication date: 2022-08-04
Also published as: CN112799729A

Abstract

Disclosed are a uboot startup method and apparatus for a multi-core system on chip, and a device and a storage medium. The method comprises: acquiring ID numbers of a plurality of CPUs in response to a system being powered on; according to the plurality of ID numbers, dividing a uboot program stored in a nor flash into a plurality of branch programs; using each CPU to respectively match a corresponding branch program from the nor flash according to the ID numbers and execute the branch program; and in response to the plurality of CPUs all completing the execution of the corresponding branch programs, confirming that a multi-core system on chip completes uboot startup. By means of the solution of the present application, each CPU is used to match a corresponding branch program from a nor flash according to an ID number and executes the branch program, thereby implementing the parallel execution of a uboot by a plurality of CPUs, improving the CPU resource utilization rate of a multi-core system on chip, and effectively shortening the execution time of a uboot program.

Description

Uboot startup method, device, device and storage medium of multi-core system-on-chip

This application claims the priority of the Chinese patent application filed on January 29, 2021 with the application number 202110123712.2 and the invention titled "Uboot startup method, device, device and storage medium for multi-core system-on-a-chip", the entire contents of which are Incorporated herein by reference.

technical field

The present application belongs to the field of computer technology, and in particular, relates to a uboot startup method, apparatus, device and storage medium of a multi-core system-on-chip.

Background technique

A System on Chip (SoC) is an integrated circuit with a special purpose, which contains a complete system and has all the contents of embedded software. In recent years, with the wide application of multi-core SoC system-on-chip in data centers, handheld devices and other fields. uboot (Universal boot Loader) is a boot loader for embedded systems in SoC chips. It is used to boot the kernel, so it is an essential step for the normal operation of the SoC system, and the uboot startup time of the SoC system is getting more and more more attention.

Currently, in the SoC system technology, uboot startup is performed by only one CPU. For a multi-core SoC system, other CPUs are in an idle state when uboot is executed. For example, assuming that a SoC system includes CPU0 and CPU1, the existing uboot execution process is as follows: After the system is powered on, CPU0 reads instructions and data from the non-volatile flash memory (nor flash), while CPU1 is idle at this time. In addition, since many interface drivers are integrated in the existing uboot, the uboot program is very large, and it takes a long time for the SoC system to execute the uboot startup.

SUMMARY OF THE INVENTION

In view of this, it is necessary to provide a uboot startup method, device, device and storage medium of a multi-core system-on-chip which can shorten the uboot startup time of the system-on-chip to solve the above technical problems.

According to a first aspect of the present application, a uboot startup method of a multi-core system-on-a-chip is provided, the method comprising:

In response to the system being powered on, the ID numbers of multiple CPUs are obtained;

Divide the uboot program stored in the non-volatile flash memory into multiple branch programs according to multiple ID numbers;

Utilize each CPU to match and execute the corresponding branch program from the non-volatile flash memory according to the ID number;

In response to the multiple CPUs executing the corresponding branch programs, it is confirmed that the multi-core system-on-a-chip completes the uboot startup.

In one of the embodiments, the step of dividing the uboot program stored in the non-volatile flash memory into multiple branch programs according to multiple ID numbers includes:

The uboot program is divided into a first branch program and a second branch program, wherein the first branch program is used for driver matching, and the second branch program is used to initialize the memory and store the existence in the non-volatile flash memory The uboot program is migrated to the initialized memory;

The first branch program and the second branch program are respectively stored in the first storage area and the second storage area of the nonvolatile flash memory.

In one of the embodiments, the step of using each CPU to match a corresponding branch program from the non-volatile flash memory according to the ID number and execute it includes:

The ID number of each CPU is matched with the first preset ID number and the second preset ID number respectively;

The CPU corresponding to the first preset ID number is denoted as the main CPU, and the CPU corresponding to the second preset ID number is denoted as the slave CPU;

Utilize the main CPU to read and execute the first branch program of the first storage area of the non-volatile flash memory;

The second branch program of the second storage area of the nonvolatile flash memory is read and executed by the slave CPU.

In one embodiment, the method further includes:

Obtain the offset address of the instruction to be read by the main CPU;

In response to the slave CPU completing the execution of the second branch program, the slave CPU sends a notification to the master CPU;

In response to the master CPU receiving the notification sent by the slave CPU, the master CPU jumps to the memory, and reads and executes the subsequent steps of the first branch program from the memory according to the offset address. instruction.

In one embodiment, the step of confirming that the multi-core system-on-a-chip completes the uboot startup in response to the multiple CPUs executing and completing the corresponding branch program includes:

Detecting whether the first branch program and the second branch program are executed respectively;

In response to the completion of execution of both the first branch program and the second branch program, confirming that the multi-core system-on-a-chip completes uboot startup;

In response to the fact that the first branch program and/or the second branch program has not been executed within a preset time, it is determined that the multi-core system-on-a-chip uboot fails to start.

In one embodiment, the method further includes:

In response to the failure to start the uboot of the multi-core system-on-chip, the multiple CPUs and timers are reset and the process returns to the step of acquiring the ID numbers of the multiple CPUs.

In one embodiment, the method further includes:

Count the number of times the uboot failed to start the multi-core SoC;

In response to the number of startup failures exceeding the preset value, the failure of the uboot program in the non-volatile flash memory is confirmed and an alarm is issued.

According to a second aspect of the present application, a uboot boot device of a multi-core system-on-chip is provided, the device comprising:

The ID number acquisition module is used to acquire the ID numbers of multiple CPUs when the system is powered on;

The program division module is used to divide the uboot program stored in the non-volatile flash memory into multiple branch programs according to multiple ID numbers;

a matching module, for using each CPU to match the corresponding branch program from the non-volatile flash memory according to the ID number and execute it;

The startup completion confirmation unit is used to confirm that the multi-core on-chip system completes the uboot startup when the corresponding branch programs are executed by multiple CPUs.

According to a third aspect of the present application, a computer device is also provided, the computer device comprising:

at least one processor; and

The memory stores a computer program that can run on the processor, and when the processor executes the program, the processor executes the aforementioned uboot startup method of the multi-core system-on-a-chip.

According to a fourth aspect of the present application, a computer-readable storage medium is also provided, where the computer-readable storage medium stores a computer program, and when the computer program is executed by the processor, executes the aforementioned uboot startup method of the multi-core system-on-a-chip.

The above-mentioned uboot startup method of a multi-core system-on-a-chip obtains the ID numbers of multiple CPUs after the system is powered on, and divides the uboot program stored in the non-volatile flash memory into multiple branch programs according to the multiple ID numbers, and then Use each CPU to match the corresponding branch program from the non-volatile flash memory according to the ID number and execute it. Finally, when multiple CPUs execute the corresponding branch program, it is confirmed that the multi-core on-chip system has completed the uboot startup, realizing the parallel execution of multiple CPUs. uboot improves the CPU resource utilization of the multi-core SoC and effectively shortens the execution time of the uboot program.

In addition, the present application also provides a uboot boot device of a multi-core system-on-chip, a computer device, and a computer-readable storage medium, which can also achieve the above technical effects, which are not repeated here.

Description of drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the accompanying drawings that need to be used in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only These are some embodiments of the present application. For those of ordinary skill in the art, other embodiments can also be obtained according to these drawings without creative efforts.

1 is a schematic flowchart of a uboot startup method of a multi-core system-on-a-chip provided by an embodiment of the present application;

FIG. 2 provides a schematic structural diagram of a uboot boot device of a multi-core system-on-chip according to another embodiment of the present application;

FIG. 3 is an internal structural diagram of a computer device in another embodiment of the present application.

Detailed ways

In order to make the objectives, technical solutions and advantages of the present application clearer, the following describes the embodiments of the present application in detail with reference to the accompanying drawings and specific embodiments.

It should be noted that all expressions using "first" and "second" in the embodiments of the present application are for the purpose of distinguishing two entities with the same name but not the same or non-identical parameters. It can be seen that "first" and "second" It is only for the convenience of expression and should not be construed as a limitation on the embodiments of the present application, and subsequent embodiments will not describe them one by one.

In one embodiment, please refer to FIG. 1 , the present application provides a uboot startup method of a multi-core system-on-a-chip, and the method includes the following steps:

S100, in response to the system being powered on, acquiring ID numbers of multiple CPUs;

Among them, the multi-core system-on-a-chip refers to the SoC system including two or more CPUs. The ID of the CPU refers to the serial number of the CPU. Each CPU also has a unique ID number, that is, the CPUID. The CPUID is used when the CPU is manufactured. Put into the CPU by the manufacturer, the CPUID is unchanged for life.

S200, dividing the uboot program stored in the nonvolatile flash memory into a plurality of branch programs according to the plurality of ID numbers;

The number of divided branch programs is multiple, for example, the ID numbers of two CPUs are obtained, the uboot program is divided into two parts to form two branch programs, and one branch program corresponds to the ID number of one CPU.

S300, utilize each CPU to match the corresponding branch program from the non-volatile flash memory according to the ID number and execute it;

S400 , confirming that the multi-core system-on-a-chip completes the uboot startup in response to the multiple CPUs executing the corresponding branch programs.

In yet another embodiment, the foregoing step S200 specifically includes:

S210: Divide the uboot program into a first branch program and a second branch program, wherein the first branch program is used for driver matching, and the second branch program is used to initialize the memory and store the memory in a non-volatile The uboot program in the flash memory is migrated to the initialized memory;

S220: Store the first branch program and the second branch program in a first storage area and a second storage area of the non-volatile flash memory, respectively.

In yet another embodiment, the foregoing step S300 specifically includes:

S310, the ID number of each CPU is matched with the first preset ID number and the second preset ID number respectively;

S320, the CPU corresponding to the first preset ID number is denoted as the main CPU, and the CPU corresponding to the second preset ID number is denoted as the slave CPU;

S330, using the main CPU to read and execute the first branch program of the first storage area of the nonvolatile flash memory;

S340, using the slave CPU to read and execute the second branch program of the second storage area of the non-volatile flash memory.

In order to facilitate the understanding of the technical solution of the present application, the following takes a SoC system including four CPUs as an example for description. It is assumed that the four CPUs are denoted as CPU0, CPU1, CPU2, and CPU3, respectively, and the ID numbers of CPU0 and CPU1 are used in advance to store the data stored in The uboot program in the non-volatile flash memory is divided into a first branch program and a second branch program, wherein CPU0 corresponds to the first branch program, that is, CPU0 performs the task of driving matching, and CPU1 corresponds to the second branch program, that is, CPU1 executes the program. For the code migration task, when the system is powered on, the ID numbers of CPU0, CPU1, CPU2, and CPU3 are read. If the ID number of CPU0 is read, then CPU0 reads the first ID number stored in the non-volatile flash memory at this time. The instructions and data of the branch program are processed for driver matching. If the ID number of the CPU1 is read, then the CPU1 reads the instructions and data of the second branch program from the non-volatile flash memory and executes the code from the flash memory. Migration processing to memory. It should be noted that since the IDs of CPU2 and CPU3 are not assigned branch programs, CPU2 and CPU3 enter the waiting state; finally, after CPU1 completes the code migration, it notifies CPU0 to make CPU0 execute from non-volatile flash memory (nor flash) Jump to memory (Double Data Rate synchronous dynamic random access memory, referred to as DDR), complete uboot execution, and wait for kernal to start.

In yet another embodiment, on the basis of the foregoing embodiment, step S400 specifically includes the following sub-steps:

S410, respectively detecting whether the execution of the first branch program and the second branch program is completed;

S420, in response to the completion of execution of both the first branch program and the second branch program, confirm that the multi-core system-on-a-chip completes uboot startup;

S430, in response to the fact that the first branch program and/or the second branch program has not been executed within a preset time, confirm that the multi-core system-on-a-chip uboot fails to start.

In yet another embodiment, in order to ensure the normal execution of the uboot program, the method further includes:

S510, obtain the offset address of the instruction to be read by the main CPU;

S520, in response to the slave CPU completing executing the second branch program, the slave CPU sends a notification to the master CPU;

S530, in response to the master CPU receiving the notification sent by the slave CPU, the master CPU jumps to the memory, reads and executes the first branch program from the memory according to the offset address subsequent instructions.

Specifically, the following continues to take a SoC system including four CPUs as an example. After CPU1 completes the migration of the uboot program from the non-volatile flash memory to the memory, it notifies CPU0. Since CPU0 is performing driver matching at this time, there is no Before receiving the notification to complete the migration, CPU0 will sequentially fetch the instructions, data, etc. of the first branch program from the flash memory. After receiving the notification of completing the migration, the CPU will record the offset address of the next instruction to be fetched through the register. , after which the CPU0 no longer fetches instructions from the non-volatile flash memory but fetches instructions from the memory until the first branch program is completely completed.

In yet another embodiment, the method of the present application further includes:

In step S610, in response to the failure to start the uboot of the multi-core system-on-chip, reset the multiple CPUs and timers and return to the step of acquiring the ID numbers of the multiple CPUs.

Optionally, the method of the present application also includes:

S620, count the number of times that the uboot fails to start the multi-core SoC;

S630, in response to the number of startup failures exceeding a preset value, confirm the failure of the uboot program in the non-volatile flash memory and issue an alarm.

The above-mentioned uboot startup method of a multi-core system-on-chip, if and only when the first branch program and the second branch program are executed, uboot is successfully started, and in any case, the system is allowed to try to start uboot again, and in order to prevent multi-core The waste of CPU resources of the on-chip system, repeated execution of invalid uboot startup, can also automatically alarm the abnormal situation, which is convenient for operation and maintenance personnel to find and maintain in time, and allows automatic restart in the event of an error within a certain limit, which realizes automatic Start uboot several times to ensure that the uboot of the multi-core SoC can be started normally.

In yet another embodiment, please refer to FIG. 2 , the present application further provides a uboot boot device 70 for a core system on a chip, the device includes:

The ID number acquisition module 71 is used to acquire the ID numbers of multiple CPUs when the system is powered on;

The program dividing module 72 is used for dividing the uboot program stored in the non-volatile flash memory into a plurality of branch programs according to a plurality of ID numbers;

Matching module 73, for utilizing each CPU to match corresponding branch program and execute respectively from described non-volatile flash memory according to ID number;

The startup completion confirmation unit 74 is used to confirm that the multi-core system-on-a-chip completes the uboot startup when the corresponding branch programs are all executed by the multiple CPUs.

It should be noted that, for the specific limitation of the uboot startup device of the multi-core system-on-a-chip, reference may be made to the limitation of the uboot startup method of the multi-core system-on-a-chip above, which will not be repeated here. Each module in the uboot boot device of the multi-core system-on-chip can be implemented in whole or in part by software, hardware and combinations thereof. The above modules can be embedded in or independent of the processor in the computer device in the form of hardware, or stored in the memory in the computer device in the form of software, so that the processor can call and execute the operations corresponding to the above modules.

According to another aspect of the present application, a computer device is provided, and the computer device may be a server. Please refer to FIG. 3 for an internal structure diagram of the computer device. The computer device includes a processor, memory, a network interface, and a database connected by a system bus. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium, an internal memory. The nonvolatile storage medium stores an operating system, a computer program, and a database. The internal memory provides an environment for the execution of the operating system and computer programs in the non-volatile storage medium. The database of the computer device is used to store data. The network interface of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, the above-mentioned uboot startup method of the multi-core system-on-a-chip is realized.

Those of ordinary skill in the art can understand that all or part of the processes in the methods of the above embodiments can be implemented by instructing relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage In the medium, when the computer program is executed, it may include the processes of the above-mentioned method embodiments. Wherein, any reference to memory, storage, database or other medium used in the various embodiments provided in this application may include non-volatile and/or volatile memory. Nonvolatile memory may include read only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory may include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in various forms such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous chain Road (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.

The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity, all possible combinations of the technical features in the above embodiments are not described. However, as long as there is no contradiction in the combination of these technical features, all It is considered to be the range described in this specification.

The above-mentioned embodiments only represent several embodiments of the present application, and the descriptions thereof are specific and detailed, but should not be construed as a limitation on the scope of the invention patent. It should be pointed out that for those skilled in the art, without departing from the concept of the present application, several modifications and improvements can be made, which all belong to the protection scope of the present application. Therefore, the scope of protection of the patent of the present application shall be subject to the appended claims.

Claims

A uboot startup method of a multi-core system-on-a-chip, characterized in that the method comprises:

In response to the system being powered on, the ID numbers of multiple CPUs are obtained;

Divide the uboot program stored in the non-volatile flash memory into multiple branch programs according to multiple ID numbers;

Utilize each CPU to match and execute the corresponding branch program from the non-volatile flash memory according to the ID number;

In response to the multiple CPUs executing the corresponding branch programs, it is confirmed that the multi-core system-on-a-chip completes the uboot startup.
The method according to claim 1, wherein the step of dividing the uboot program stored in the non-volatile flash memory into a plurality of branch programs according to a plurality of ID numbers comprises:

The uboot program is divided into a first branch program and a second branch program, wherein the first branch program is used for driver matching, and the second branch program is used to initialize the memory and store the data stored in the non-volatile flash memory. The uboot program is migrated to the initialized memory;

The first branch program and the second branch program are respectively stored in the first storage area and the second storage area of the nonvolatile flash memory.
The method according to claim 2, wherein the step of using each CPU to match and execute a corresponding branch program from the non-volatile flash memory according to the ID number comprises:

The ID number of each CPU is matched with the first preset ID number and the second preset ID number respectively;

The CPU corresponding to the first preset ID number is denoted as the main CPU, and the CPU corresponding to the second preset ID number is denoted as the slave CPU;

Utilize the main CPU to read and execute the first branch program of the first storage area of the non-volatile flash memory;

The second branch program of the second storage area of the non-volatile flash memory is read and executed by the slave CPU.
The method according to claim 3, wherein the method further comprises:

Obtain the offset address of the instruction to be read by the main CPU;

In response to the slave CPU completing the execution of the second branch program, the slave CPU sends a notification to the master CPU;

In response to the master CPU receiving the notification sent by the slave CPU, the master CPU jumps to the memory, and reads and executes the subsequent steps of the first branch program from the memory according to the offset address. instruction.
The method according to claim 2, wherein the step of confirming that the multi-core system-on-a-chip completes the uboot startup in response to the execution of the corresponding branch programs by the multiple CPUs comprises:

Detecting whether the first branch program and the second branch program are executed respectively;

In response to the completion of execution of both the first branch program and the second branch program, confirming that the multi-core system-on-a-chip completes uboot startup;

In response to the fact that the first branch program and/or the second branch program has not been executed within a preset time, it is determined that the multi-core system-on-a-chip uboot fails to start.
The method according to claim 5, wherein the method further comprises:

In response to the failure to start the uboot of the multi-core system-on-chip, the multiple CPUs and timers are reset and the process returns to the step of acquiring the ID numbers of the multiple CPUs.
The method according to claim 6, wherein the method further comprises:

Count the number of times the uboot failed to start the multi-core SoC;

In response to the number of startup failures exceeding the preset value, the failure of the uboot program in the non-volatile flash memory is confirmed and an alarm is issued.
A uboot boot device for a multi-core system-on-a-chip, characterized in that the device comprises:

The ID number acquisition module is used to acquire the ID numbers of multiple CPUs when the system is powered on;

The program division module is used to divide the uboot program stored in the non-volatile flash memory into multiple branch programs according to multiple ID numbers;

a matching module, for using each CPU to match the corresponding branch program from the non-volatile flash memory according to the ID number and execute it;

The startup completion confirmation unit is used to confirm that the multi-core on-chip system completes the uboot startup when the corresponding branch programs are executed by multiple CPUs.
A computer equipment, characterized in that, comprising:

at least one processor; and

a memory, where the memory stores a computer program executable in the processor, and the processor executes the method according to any one of claims 1 to 7 when the processor executes the program.
A computer-readable storage medium storing a computer program, characterized in that, when the computer program is executed by a processor, the method of any one of claims 1 to 7 is executed.