WO2022156370A1 - 一种基于fpga的dma设备及dma数据搬移方法 - Google Patents

一种基于fpga的dma设备及dma数据搬移方法 Download PDF

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WO2022156370A1
WO2022156370A1 PCT/CN2021/134142 CN2021134142W WO2022156370A1 WO 2022156370 A1 WO2022156370 A1 WO 2022156370A1 CN 2021134142 W CN2021134142 W CN 2021134142W WO 2022156370 A1 WO2022156370 A1 WO 2022156370A1
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data
module
channel
target
target request
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PCT/CN2021/134142
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French (fr)
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王峰
张闯
任智新
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苏州浪潮智能科技有限公司
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    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/20Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24Handling requests for interconnection or transfer for access to input/output bus using interrupt
    • G06F13/26Handling requests for interconnection or transfer for access to input/output bus using interrupt with priority control
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/28DMA
    • G06F2213/2806Space or buffer allocation for DMA transfers

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  • the present application relates to the technical field of data transmission, and in particular, to an FPGA-based DMA device and a DMA data transfer method.
  • accelerator cards based on FPGA are also developing rapidly.
  • the acceleration card FPGA is connected to the server host through the PCIE interface, and the server host sends the data to be accelerated to the acceleration card FPGA through the PCIE (that is, peripheral component interconnect express, a high-speed serial computer expansion bus standard) interface.
  • PCIE peripheral component interconnect express, a high-speed serial computer expansion bus standard
  • DMA direct memory access, direct memory access
  • DMA is a commonly used data moving device, which is used to receive the moving instructions from the host, apply for bus control rights, and perform data moving.
  • the present application discloses an FPGA-based DMA device, including a configuration module, a multi-channel module, and an arbitration module, wherein,
  • the configuration module is used to obtain the configuration information sent by the host, and based on the configuration information, respectively deliver the corresponding data moving tasks to the corresponding multiple data moving channels in the multi-channel module; wherein, the configuration information includes each data moving channel to be moved.
  • the multi-channel module is used to send a transfer request to the arbitration module based on the corresponding data transfer task through each data transfer channel;
  • the arbitration module is configured to determine the first target request from the multiple transfer requests based on the preset channel priority, and process the first target request to transfer the target data in the first storage device through the data transfer channel corresponding to the first target request It is moved to the second storage device, and when the amount of data in the first storage device corresponding to the first target request is insufficient, the second target request is determined for processing based on the preset channel priority.
  • the arbitration module is configured to determine the second target request for processing based on the preset channel priority and the destination address corresponding to the move request.
  • the arbitration module is further configured to suspend processing of the second target request and continue to process the first target request when the amount of data in the first storage device satisfies the condition for continuing to read.
  • the target data is read from the first storage device based on the first target request, and the target data is placed in the cache of the data moving channel corresponding to the first target request, and the target is read from the cache. Data is written to the second storage device.
  • it also includes:
  • the status module is used to record the transfer status corresponding to all data transfer channels.
  • the arbitration module is further used to:
  • the multi-channel module is also used to:
  • it also includes:
  • the interrupt module is used to send the corresponding interrupt to the host when any data moving task is completed.
  • the present application discloses a FPGA-based DMA data transfer method, comprising:
  • the arbitration module determines the first target request from the multiple move requests based on the preset channel priority, and processes the first target request to move the target data in the first storage device to the data moving channel corresponding to the first target request.
  • the second storage device when the amount of data in the first storage device corresponding to the first target request is insufficient, determines the second target request for processing based on the preset channel priority.
  • determining the second target request for processing based on a preset channel priority includes:
  • the second target request is determined for processing based on the preset channel priority and the destination address corresponding to the move request.
  • Embodiments of the present application further provide a computer device, including a memory and one or more processors, where computer-readable instructions are stored in the memory, and when the computer-readable instructions are executed by the one or more processors, cause The one or more processors execute the steps of any one of the above-mentioned FPGA-based DMA data transfer methods.
  • the embodiments of the present application further provide one or more non-volatile computer-readable storage media storing computer-readable instructions.
  • the computer-readable instructions are executed by one or more processors, the one or more A plurality of processors execute the steps of any one of the above-mentioned FPGA-based DMA data transfer methods.
  • FIG. 1 is a schematic structural diagram of a FPGA-based DMA device provided by the application according to one or more embodiments;
  • FIG. 2 is a schematic structural diagram of a specific FPGA-based DMA device provided by the application according to one or more embodiments;
  • FIG. 3 is a schematic structural diagram of a specific FPGA-based DMA device provided by the application according to one or more embodiments;
  • FIG. 4 is a schematic diagram of a specific data migration provided by this application according to one or more embodiments.
  • Fig. 5 is a kind of FPGA-based DMA data moving method flow chart provided by this application according to one or more embodiments;
  • FIG. 6 is a schematic diagram of an internal structure of a computer device provided according to one or more embodiments.
  • FIG. 7 is a schematic diagram of an internal structure of a computer device provided according to one or more embodiments.
  • the existing DMA can only receive one move instruction at a time, then multiple DMAs need to work at the same time to meet the requirements, which obviously increases the complexity of the system. And because they are all hung on the same bus, multiple DMAs cannot move data at the same time, and only one DMA can acquire the bus at the same time to move data. In this way, the bus needs to be switched between multiple DMAs, which is less efficient.
  • the present application provides an FPGA-based DMA solution, which can meet data transfer requirements between multiple external storage devices, avoid bus switching between multiple DMAs, and improve data transfer efficiency.
  • an embodiment of the present application discloses an FPGA-based DMA device, including a configuration module 11, a multi-channel module 12, and an arbitration module 13, wherein,
  • the configuration module 11 is used to obtain the configuration information sent by the host, and based on the configuration information, the corresponding multiple data movement channels in the multi-channel module 12 are respectively issued corresponding data movement tasks; wherein, the configuration information includes each data movement channel to be The amount of data moved, the source address, and the destination address.
  • the multi-channel module 12 is configured to send a transfer request to the arbitration module 13 based on the corresponding data transfer task through each data transfer channel.
  • the number of channels in the multi-channel module can be set according to actual requirements, such as 4, 16, etc., which is not specifically limited here.
  • the arbitration module 13 is configured to determine a first target request from a plurality of transfer requests based on a preset channel priority, and process the first target request to transfer the target in the first storage device through the data transfer channel corresponding to the first target request.
  • the data is moved to the second storage device, and when the amount of data in the first storage device corresponding to the first target request is insufficient, the second target request is determined for processing based on the preset channel priority.
  • the priority of the channel can be set, and the request corresponding to the channel with the highest priority is processed first.
  • the priorities of channel 1 to channel 4 are decreased in sequence.
  • the moving task of channel 1 is preferentially executed.
  • the task of channel 1 is in a waiting state due to insufficient data for the device to be read, then the task of channel 2 is started to avoid waiting, because the waiting time is too long, DMA will lose the bus control, if necessary Apply for bus control again.
  • the storage device itself judges the amount of data, and when the data is less than the amount of one read, the storage device pulls up the waiting signal to inform the DMA to enter the wait. That is, the signal is pulled high to inform the arbitration module that the amount of data is insufficient. For example, DMA is reading from storage, and another device is writing to storage. If the DMA reads fast, the stored data will be read empty, and it needs to wait.
  • the arbitration module 13 is specifically configured to read the target data from the first storage device based on the first target request, and place the target data in the cache of the data moving channel corresponding to the first target request, and store the target data from the cache. The read target data is written into the second storage device.
  • the arbitration module generates request data conforming to the Avalon bus protocol format based on the first target request and sends it to the FPGA Avalon bus, the Avalon bus sends the request data to the first storage device, reads the target data and returns it to the arbitration module, and the arbitration module will The target data is stored in the corresponding cache.
  • the arbitration module 13 is specifically configured to determine the second target request for processing based on the preset channel priority and the destination address corresponding to the move request.
  • a request with a different destination address corresponding to the first target request and with the highest channel priority is determined from the unprocessed move requests as the second target request, the second target request is determined, and the second target request is to be processed.
  • the arbitration module is further configured to suspend processing of the second target request and continue to process the first target request when the amount of data in the first storage device satisfies the condition for continuing to read.
  • the waiting signal is pulled low to notify the arbitration module to continue processing the first target request.
  • the FPGA-based DMA device disclosed in the embodiment of the present application includes a configuration module, a multi-channel module, and an arbitration module, wherein the configuration module is used to obtain configuration information sent by the host, and based on the configuration information, send the configuration information to the corresponding multi-channel module.
  • a plurality of data moving channels respectively issue corresponding data moving tasks; wherein, the configuration information includes the amount of data to be moved, source address and destination address of each data moving channel; the multi-channel module is used for each data moving channel based on the corresponding The data moving task sends a moving request to the arbitration module; the arbitration module is used to determine the first target request from a plurality of moving requests based on the preset channel priority, and process the first target request to request the corresponding data through the first target.
  • the moving channel moves the target data in the first storage device to the second storage device. When the amount of data in the first storage device corresponding to the first target request is insufficient, the second target request is determined based on the preset channel priority for processing.
  • the source address, destination address, and the amount of data to be moved are configured to perform multiple data movement tasks through multiple data movement channels, and the arbitration module determines the target request for data movement. If the current target request corresponds to When the data of the storage device is insufficient, a new target request is determined for data movement to avoid the waiting time process. In this way, the data movement requirements between multiple external storage devices can be met, and the bus switching between multiple DMAs can be avoided. Data movement efficiency.
  • the embodiment of the present application discloses a specific FPGA-based DMA device, including a configuration module 21, a multi-channel module 22, an arbitration module 23, a status module 24, and an interrupt module 25, wherein,
  • the configuration module 21 is used to obtain the configuration information sent by the host, and based on the configuration information, the corresponding multiple data movement channels in the multi-channel module 22 are respectively issued corresponding data movement tasks; wherein, the configuration information includes each data movement channel to be The amount of data moved, the source address and the destination address;
  • the multi-channel module 22 is used to send a transfer request to the arbitration module 23 based on the corresponding data transfer task through each data transfer channel;
  • the arbitration module 23 is configured to determine the first target request from the multiple transfer requests based on the preset channel priority, and process the first target request to transfer the target in the first storage device through the data transfer channel corresponding to the first target request.
  • the data is moved to the second storage device, and when the amount of data in the first storage device corresponding to the first target request is insufficient, the second target request is determined for processing based on the preset channel priority.
  • the status module 24 is used to record the transfer status corresponding to all data transfer channels.
  • the moving state includes: the internal fifo (First Input First Output, first in, first out) of each data moving channel is empty and full, and the current data moving channel task state includes moving, waiting, ending, and remaining data.
  • the internal fifo First Input First Output, first in, first out
  • the current data moving channel task state includes moving, waiting, ending, and remaining data.
  • the arbitration module 23 is further configured to: write the moving state into the state module.
  • the multi-channel module 22 is further configured to: write the moving state into the state module.
  • the transfer status can be written into the status module through the arbitration module 23 or the multi-channel module 22 .
  • the interrupt module 25 is configured to send a corresponding interrupt to the host after any data moving task is completed.
  • an interrupt or other information may be sent to inform the host that the task is complete.
  • the host can also shield these interrupts and obtain the corresponding information by reading the status module.
  • FIG. 3 an embodiment of the present application discloses a specific FPGA-based DMA device.
  • the entire DMA workflow is illustrated by the data transfer between the three devices: SRAM, DDR, and flash.
  • FIG. 4 is a schematic diagram of a specific data transfer disclosed by an embodiment of the present application.
  • the configuration information delivered by the Host to the configuration module is that channel1 moves 256M data from SRAM address A to DDR address C, channel2 moves 256M data from flash address E to DDR address D, and channel3 moves 256M data from SRAM address B To the flash address E, channel4 moves 100M data from the flash address F to the DDR address G.
  • the configuration module After the configuration module receives the configuration information sent by the host, it starts the DMA and starts to work. Since only one device can occupy the bus at the same time, channel1 has the highest priority, DMA first starts to perform data transfer from A->C, and the status module records the status. At this time, the arbitration module starts to process the request of channel2 according to the situation, and executes the data transfer of E->D. When channel2 is moved to 64M, the SRAM data is sufficient, and channel1 re-enters the transfer state. At this time, channel2 will be suspended and continue to execute A-> C move. When channel1 executes to the 192M transfer amount, SRAM waits again, at this time channel enters waiting again, and channel2 starts to continue to execute.
  • channel2 executes to 128M, if the flash also has insufficient data or other conditions need to wait, channel2 also enters the waiting state. At this time, channel3 should be started under normal circumstances, and the data movement of B->E should be performed, but because there is also a movement related to address E in channel2, and the priority of channel2 is high, if there is no software sequence restriction in the host application layer, If the data movement of B->E is performed at this time, the data of E will be destroyed, resulting in an error of the data movement of E->D. In the case of address conflict, the arbitration module will prevent the channel with low priority from starting, so channel3 will not be executed at this time, and channel4 will be started at this time.
  • the interrupt module When a channel completes the relocation task, the interrupt module will issue a corresponding interrupt to inform the host. In this way, from a macro point of view, the tasks of channel1, channel2 and channel4 are almost executed in parallel. When channel1 enters waiting, channel2 continues to execute, and when channel2 waits, channel4 continues to execute. If the number of channels is large enough, it is difficult for all channels to wait at the same time at the same time, DMA will always have the control of the bus, and the data transmission efficiency is very high, so that multiple DMAs are not needed to complete multiple moving tasks together. Moreover, the host does not need to avoid the conflict between channel2 and channel3 at the software layer, and the DMA's own logic can ensure that there will be no conflict.
  • time-division multi-channel DMA is implemented based on FPGA, and the implementation logic of DMA can be encapsulated into IP for independent use, which can be applied to data transfer between multiple peripherals.
  • DMA time-division multi-channel DMA
  • an embodiment of the present application discloses an FPGA-based DMA data transfer method, including:
  • Step S11 Obtain configuration information sent by the host through the configuration module, and deliver corresponding data moving tasks to the corresponding multiple data moving channels in the multi-channel module based on the configuration information.
  • Step S12 Send a transfer request to the arbitration module through each data transfer channel in the multi-channel module based on the corresponding data transfer task.
  • Step S13 Determine the first target request from the plurality of transfer requests based on the preset channel priority through the arbitration module, and process the first target request to transfer the target in the first storage device through the data transfer channel corresponding to the first target request.
  • the data is moved to the second storage device, and when the amount of data in the first storage device corresponding to the first target request is insufficient, the second target request is determined for processing based on the preset channel priority.
  • the target data is read from the first storage device based on the first target request by the arbitration module, and the target data is placed in the cache of the data moving channel corresponding to the first target request, and read from the cache The target data is written to the second storage device.
  • the arbitration module may determine the second target request for processing based on the preset channel priority and the destination address corresponding to the move request.
  • the arbitration module suspends the processing of the second target request and continues to process the first target request.
  • the above method also includes:
  • the above method further includes: writing the moving state into the state module through the arbitration module, or writing the moving state into the state module through the multi-channel module.
  • the above method also includes:
  • the interrupt module when any data transfer task is completed, the corresponding interrupt is sent to the host.
  • the configuration information sent by the host is obtained through the configuration module, and based on the configuration information, the corresponding data movement tasks are respectively issued to the corresponding multiple data movement channels in the multi-channel module;
  • the channel sends a transfer request to the arbitration module based on the corresponding data transfer task;
  • the arbitration module determines the first target request from the plurality of transfer requests based on the preset channel priority, and processes the first target request to pass the corresponding first target request.
  • the data moving channel moves the target data in the first storage device to the second storage device. When the amount of data in the first storage device corresponding to the first target request is insufficient, the second target request is determined based on the preset channel priority for processing. .
  • the source address, destination address, and the amount of data to be moved are configured to perform multiple data movement tasks through multiple data movement channels, and the arbitration module determines the target request for data movement. If the current target request corresponds to When the data of the storage device is insufficient, a new target request is determined for data movement to avoid the waiting time process. In this way, the data movement requirements between multiple external storage devices can be met, and the bus switching between multiple DMAs can be avoided. Data movement efficiency.
  • a computer device is provided, and the computer device may be a terminal, and its internal structure diagram may be as shown in FIG. 6 .
  • the computer equipment includes a processor, memory, a network interface, a display screen, and an input device connected by a system bus.
  • the processor of the computer device is used to provide computing and control capabilities.
  • the memory of the computer device includes a non-volatile storage medium, an internal memory.
  • the non-volatile storage medium stores an operating system and computer-readable instructions.
  • the internal memory provides an environment for the execution of the operating system and computer-readable instructions in the non-volatile storage medium.
  • the network interface of the computer device is used to communicate with an external terminal through a network connection.
  • the computer-readable instructions when executed by the processor, implement an FPGA-based DMA data transfer method.
  • the display screen of the computer equipment may be a liquid crystal display screen or an electronic ink display screen
  • the input device of the computer equipment may be a touch layer covered on the display screen, or a button, a trackball or a touchpad set on the shell of the computer equipment , or an external keyboard, trackpad, or mouse.
  • a computer device in one embodiment, is provided, and the computer device can be a server, and its internal structure diagram can be as shown in FIG. 7 .
  • the computer device includes a processor, memory, a network interface, and a database connected by a system bus. Among them, the processor of the computer device is used to provide computing and control capabilities.
  • the memory of the computer device includes a non-volatile storage medium, an internal memory.
  • the non-volatile storage medium stores an operating system, computer readable instructions and a database.
  • the internal memory provides an environment for the execution of the operating system and computer-readable instructions in the non-volatile storage medium.
  • the computer device's database is used to store preset channel priorities.
  • the network interface of the computer device is used to communicate with an external terminal through a network connection.
  • the computer-readable instructions when executed by the processor, implement an FPGA-based DMA data transfer method.
  • a computer device includes a memory and one or more processors, wherein computer readable instructions are stored in the memory, and when executed by the processors, the computer readable instructions cause the one or more processors to perform the above method.
  • One or more non-volatile storage media storing computer-readable instructions that, when executed by one or more processors, cause the one or more processors to perform the above-described method.
  • Nonvolatile memory may include read only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory.
  • Volatile memory may include random access memory (RAM) or external cache memory.
  • RAM is available in various forms such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous chain Road (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.

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Abstract

一种基于FPGA的DMA设备及DMA数据搬移方法,DMA设备包括:配置模块(11)用于获取主机发送的配置信息,并基于配置信息向多通道模块(12)中多个数据搬移通道分别下发数据搬移任务;配置信息包括每个通道待搬移的数据量、源地址、目的地址;多通道模块(12)用于通过每个数据搬移通道基于对应的搬移任务向仲裁模块(13)发送搬移请求;仲裁模块(13)用于基于预设通道优先级从多个搬移请求中确定出第一目标请求,并处理第一目标请求以通过对应的数据搬移通道将第一存储设备中的目标数据搬移至第二存储设备,当第一存储设备中数据量不足,则基于预设通道优先级确定出第二目标请求进行处理。

Description

一种基于FPGA的DMA设备及DMA数据搬移方法
相关申请的交叉引用
[根据细则91更正 27.12.2021] 
本申请要求于2021年01月20日提交中国专利局,申请号为202110076297.X,申请名称为“一种基于FPGA的DMA设备及DMA数据搬移方法”的中国专利申请的优先权,其全部内容通过引用结合在本申请中。
技术领域
本申请涉及数据传输技术领域,特别涉及一种基于FPGA的DMA设备及DMA数据搬移方法。
背景技术
随着异构加速日益广泛的应用,基于FPGA(即Field Programmable Gate Array现场可编程与门阵列)的加速卡也发展迅速。加速卡FPGA通过PCIE接口与服务器主机连接,服务器主机通过PCIE(即peripheral component interconnect express,一种高速串行计算机扩展总线标准)接口将需要加速的数据发送给加速卡FPGA,加速卡FPGA处理完成后通过PCIE接口返回相关的数据。在数据传输过程中,DMA(即direct memory access,直接存储器访问)是常用的数据搬移设备,用于接收主机的搬移指令,申请总线控制权,进行数据搬移。
发明人意识到,目前,如果系统中的外设较多,现有的DMA一次只能接收一次搬移指令,那就需要多个DMA同时工作才能满足要求,而这样显然会增加系统复杂性。而且因为都挂在同一总线上,多个DMA并不能同时搬移数据,同一时刻只有一个DMA能获取总线,进行数据搬移。这样总线就需要在多个DMA之间进行切换,效率较低。
发明内容
第一方面,本申请公开了一种基于FPGA的DMA设备,包括配置模块、多通道模块、仲裁模块,其中,
配置模块,用于获取主机发送的配置信息,并基于配置信息向多通道模块中相应的多个数据搬移通道分别下发对应的数据搬移任务;其中,配置信息包括每个数据搬移通 道待搬移的数据量、源地址以及目的地址;
多通道模块,用于通过每个数据搬移通道基于对应的数据搬移任务向仲裁模块发送搬移请求;
仲裁模块,用于基于预设通道优先级从多个搬移请求中确定出第一目标请求,并处理第一目标请求以通过第一目标请求对应的数据搬移通道将第一存储设备中的目标数据搬移至第二存储设备,当第一目标请求对应的第一存储设备中数据量不足,则基于预设通道优先级确定出第二目标请求进行处理。
在其中一个实施例中,仲裁模块,用于基于预设通道优先级以及搬移请求对应的目的地址确定出第二目标请求进行处理。
在其中一个实施例中,仲裁模块,还用于当第一存储设备中数据量满足继续读取条件,则暂停处理第二目标请求,继续处理第一目标请求。
在其中一个实施例中,用于基于第一目标请求从第一存储设备中读取目标数据,并将目标数据放置于第一目标请求对应的数据搬移通道的缓存中,从缓存中读取目标数据写入第二存储设备中。
在其中一个实施例中,还包括:
状态模块,用于记录全部数据搬移通道对应的搬移状态。
在其中一个实施例中,仲裁模块还用于:
将搬移状态写入状态模块。
在其中一个实施例中,多通道模块还用于:
将搬移状态写入状态模块。
在其中一个实施例中,还包括:
中断模块,用于当任一数据搬移任务完成后,发送对应的中断至主机。
第二方面,本申请公开了一种基于FPGA的DMA数据搬移方法,包括:
通过配置模块获取主机发送的配置信息,并基于配置信息向多通道模块中相应的多个数据搬移通道分别下发对应的数据搬移任务;
通过多通道模块中每个数据搬移通道基于对应的数据搬移任务向仲裁模块发送搬移请求;和
通过仲裁模块基于预设通道优先级从多个搬移请求中确定出第一目标请求,并处理第一目标请求以通过第一目标请求对应的数据搬移通道将第一存储设备中的目标数据搬移至第二存储设备,当第一目标请求对应的第一存储设备中数据量不足,则基于预设通道优先级确定出第二目标请求进行处理。
在其中一个实施例中,基于预设通道优先级确定出第二目标请求进行处理,包括:
基于预设通道优先级以及搬移请求对应的目的地址确定出第二目标请求进行处理。
本申请实施例还提供了一种计算机设备,包括存储器及一个或多个处理器,存储器中储存有计算机可读指令,所述计算机可读指令被所述一个或多个处理器执行时,使得所述一个或多个处理器执行上述任一项基于FPGA的DMA数据搬移方法的步骤。
本申请实施例最后还提供了一个或多个存储有计算机可读指令的非易失性计算机可读存储介质,所述计算机可读指令被一个或多个处理器执行时,使得所述一个或多个处理器执行上述任一项基于FPGA的DMA数据搬移方法的步骤。
本申请的一个或多个实施例的细节在下面的附图和描述中提出。本申请的其它特征和优点将从说明书、附图以及权利要求书变得明显。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案,下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图仅仅是本申请的实施例,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据提供的附图获得其他的附图。
图1为本申请根据一个或多个实施例提供的一种基于FPGA的DMA设备结构示意图;
图2为本申请根据一个或多个实施例提供的一种具体的基于FPGA的DMA设备结构示意图;
图3为本申请根据一个或多个实施例提供的一种具体的基于FPGA的DMA设备结构示意图;
图4为本申请根据一个或多个实施例提供的一种具体的数据搬移示意图;
图5为本申请根据一个或多个实施例提供的一种基于FPGA的DMA数据搬移方法流程图;
图6为根据一个或多个实施例提供的计算机设备的内部结构示意图;
图7为根据一个或多个实施例提供的计算机设备的内部结构示意图。
具体实施方式
下面将结合本申请实施例中的附图,对本申请实施例中的技术方案进行清楚、完整 地描述,显然,所描述的实施例仅仅是本申请一部分实施例,而不是全部的实施例。基于本申请中的实施例,本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例,都属于本申请保护的范围。
目前,如果系统中的外设较多,现有的DMA一次只能接收一次搬移指令,那就需要多个DMA同时工作才能满足要求,而这样显然会增加系统复杂性。而且因为都挂在同一总线上,多个DMA并不能同时搬移数据,同一时刻只有一个DMA能获取总线,进行数据搬移。这样总线就需要在多个DMA之间进行切换,效率较低。为此本申请提供了一种基于FPGA的DMA方案,能够满足多个外部存储设备之间的数据搬移需求,避免总线在多个DMA之间进行切换,提升数据搬移效率。
参见图1所示,本申请实施例公开一种基于FPGA的DMA设备,包括配置模块11、多通道模块12、仲裁模块13,其中,
配置模块11,用于获取主机发送的配置信息,并基于配置信息向多通道模块12中相应的多个数据搬移通道分别下发对应的数据搬移任务;其中,配置信息包括每个数据搬移通道待搬移的数据量、源地址以及目的地址。
多通道模块12,用于通过每个数据搬移通道基于对应的数据搬移任务向仲裁模块13发送搬移请求。
其中,多通道模块中的通道数量可以根据实际需求进行设定,比如4、16等,在此不做具体限定。
仲裁模块13,用于基于预设通道优先级从多个搬移请求中确定出第一目标请求,并处理第一目标请求以通过第一目标请求对应的数据搬移通道将第一存储设备中的目标数据搬移至第二存储设备,当第一目标请求对应的第一存储设备中数据量不足,则基于预设通道优先级确定出第二目标请求进行处理。
也即,本实施实施可以设置通道的优先级,先处理优先级最高的通道对应的请求。例如,通道1至通道4优先级依次降低,当通道1和通道2都有搬移任务时,优先执行通道1的搬移任务。但是当通道1的任务因对应待读取设备的数据不足而处于等待状态,那么就开始执行通道2的任务,这样避免等待,因为等待时间太久,DMA会失去总线控制权,如果需要就要再次申请总线控制权。
并且,当第一目标请求对应的第一存储设备中数据量不足,则将对应搬移任务的状态记为等待。具体的,存储设备自身进行数据量判断,当数据不足一次读取量时,存储设备则拉高等待信号告知DMA进入等待。也即,拉高信号通知仲裁模块数据量不足。例如,DMA在从存储里读取,而另一个设备在往存储里面写,如果DMA读的快了,存储的 数据就会被读空,那就需要等待。
在具体的实施方式中,仲裁模块13具体用于基于第一目标请求从第一存储设备中读取目标数据,并将目标数据放置于第一目标请求对应的数据搬移通道的缓存中,从缓存中读取目标数据写入第二存储设备中。
具体的,仲裁模块基于第一目标请求生成符合Avalon总线协议格式的请求数据发送至FPGA Avalon总线,Avalon总线将请求数据发送至第一存储设备,读取出目标数据返回给仲裁模块,仲裁模块将目标数据存储至对应缓存中。
并且,仲裁模块13具体用于基于预设通道优先级以及搬移请求对应的目的地址确定出第二目标请求进行处理。
具体的,从未开始处理的搬移请求中确定出与第一目标请求对应的目的地址不同的且通道优先级最高的请求作为第二目标请求,确定出第二目标请求并对该第二目标请求进行处理。
需要指出的是,如果出现地址冲突,在后处理的请求会破坏相同目的地址的已搬移数据。
进一步的,仲裁模块,还用于当第一存储设备中数据量满足继续读取条件,则暂停处理第二目标请求,继续处理第一目标请求。
具体的,当第一存储设备中的数据量充足,则拉低等待信号,通知仲裁模块继续处理第一目标请求。
也即,当第一存储设备中的数据量充足时,则暂停处理第二目标请求,继续处理第一目标请求。
可见,本申请实施例公开的基于FPGA的DMA设备,包括配置模块、多通道模块、仲裁模块,其中,配置模块,用于获取主机发送的配置信息,并基于配置信息向多通道模块中相应的多个数据搬移通道分别下发对应的数据搬移任务;其中,配置信息包括每个数据搬移通道待搬移的数据量、源地址以及目的地址;多通道模块,用于通过每个数据搬移通道基于对应的数据搬移任务向仲裁模块发送搬移请求;仲裁模块,用于基于预设通道优先级从多个搬移请求中确定出第一目标请求,并处理第一目标请求以通过第一目标请求对应的数据搬移通道将第一存储设备中的目标数据搬移至第二存储设备,当第一目标请求对应的第一存储设备中数据量不足,则基于预设通道优先级确定出第二目标请求进行处理。也即,本申请实施例通过配置数据搬移的源地址、目的地址和搬移数据量通过多个数据搬移通道执行多个数据搬移任务,通过仲裁模块确定出目标请求进行数据搬移,若当前目标请求对应的存储设备数据不足时,确定出新的目标请求进行数据搬 移,避免等待时间过程,这样,能够满足多个外部存储设备之间的数据搬移需求,避免总线在多个DMA之间进行切换,提升数据搬移效率。
参见图2所示,本申请实施例公开了一种具体的基于FPGA的DMA设备,包括配置模块21、多通道模块22、仲裁模块23,状态模块24,中断模块25,其中,
配置模块21,用于获取主机发送的配置信息,并基于配置信息向多通道模块22中相应的多个数据搬移通道分别下发对应的数据搬移任务;其中,配置信息包括每个数据搬移通道待搬移的数据量、源地址以及目的地址;
多通道模块22,用于通过每个数据搬移通道基于对应的数据搬移任务向仲裁模块23发送搬移请求;
仲裁模块23,用于基于预设通道优先级从多个搬移请求中确定出第一目标请求,并处理第一目标请求以通过第一目标请求对应的数据搬移通道将第一存储设备中的目标数据搬移至第二存储设备,当第一目标请求对应的第一存储设备中数据量不足,则基于预设通道优先级确定出第二目标请求进行处理。
状态模块24,用于记录全部数据搬移通道对应的搬移状态。
其中,搬移状态包括:各个数据搬移通道内部fifo(First Input First Output,先进先出)空满状态,当前数据搬移通道任务状态包括正在搬移、等待、结束,以及剩余数据量等。
在一种具体的实施方式中,仲裁模块23还用于:将搬移状态写入状态模块。
在另一种具体的实施方式中,多通道模块22还用于:将搬移状态写入状态模块。
也即,可以通过仲裁模块23或多通道模块22将搬移状态写入状态模块。
中断模块25,用于当任一数据搬移任务完成后,发送对应的中断至主机。
在具体的实施方式中,可以发送中断或其他信息告知主机任务完成。当然,主机也可以屏蔽这些中断,通过读取状态模块获取对应信息。
例如,参见图3所示,本申请实施例公开了一种具体的基于FPGA的DMA设备。以SRAM,DDR,flash三个设备之间的数据搬移来说明整个DMA的工作流程。如图4所示,图4为本申请实施例公开的一种具体的数据搬移示意图。Host向配置模块下发的配置信息为channel1从SRAM的地址A搬移256M的数据到DDR的地址C,channel2从flash的地址E搬移256M数据到DDR的地址D,channel3从SRAM的地址B搬移256M数据到flash的地址E,channel4从flash地址F搬移100M数据到DDR的地址G。配置模块收到host下发的配置信息后,启动DMA开始工作。由于同一时刻只能有一个设备占 据总线,channel1优先级最高,DMA首先开始执行A->C的数据搬移,状态模块记录状态。此时仲裁模块根据情况开始处理channel2的请求,执行E->D的数据搬移,channel2搬到64M时,SRAM的数据充足了,channel1重新进入搬移状态,此时会暂停channel2,继续执行A->C搬移。当channel1执行到192M搬移量时,SRAM再次等待,此时channel又进入等待,channel2开始继续执行。当channel2执行到128M时,如果flash也出现数据不足或者其他情况需要等待,channel2也进入等待状态。此时正常情况下应该启动channel3,执行B->E的数据搬移,但是因为channel2中也有地址E相关的搬移,而且channel2的优先级高,如果在host应用层没有软件进行顺序限制的情况下,如果此时执行B->E的数据搬移,会破坏E的数据,导致E->D搬移数据错误。仲裁模块在有地址冲突的情况下,会阻止优先级低的channel启动,所以此时不会执行channel3,此时会启动channel4。当某个channel完成搬移任务后,中断模块会发出对应中断告知host。这样,从宏观上看,channel1和channel2以及channel4的任务几乎是并行执行的,在channel1进入等待的情况下,channel2继续执行,channel2等待时,channel4继续执行。如果channel的数量足够多,同一时刻很难出现所有channel同时等待的情况,DMA会一直有总线的控制权,数据传输效率很高,这样就不需要多个DMA来共同完成多个搬移任务。而且host不需要在软件层避免channel2与channel3的冲突,DMA自己逻辑能够确保不会发生冲突。
这样,基于FPGA实现时分多通道DMA,可以将DMA的实现逻辑封装成IP独立使用,能够适用多个外设之间的数据搬移。提升灵活性和可移植性以及可扩展性,在可以直接调用,为相应产品的开发提供便利,缩短开发周期。
参见图5所示,本申请实施例公开了一种基于FPGA的DMA数据搬移方法,包括:
步骤S11:通过配置模块获取主机发送的配置信息,并基于配置信息向多通道模块中相应的多个数据搬移通道分别下发对应的数据搬移任务。
步骤S12:通过多通道模块中每个数据搬移通道基于对应的数据搬移任务向仲裁模块发送搬移请求。
步骤S13:通过仲裁模块基于预设通道优先级从多个搬移请求中确定出第一目标请求,并处理第一目标请求以通过第一目标请求对应的数据搬移通道将第一存储设备中的目标数据搬移至第二存储设备,当第一目标请求对应的第一存储设备中数据量不足,则基于预设通道优先级确定出第二目标请求进行处理。
在具体的实施方式中,通过仲裁模块基于第一目标请求从第一存储设备中读取目标 数据,并将目标数据放置于第一目标请求对应的数据搬移通道的缓存中,从缓存中读取目标数据写入第二存储设备中。
在具体的实施方式中,可以通过仲裁模块基于预设通道优先级以及搬移请求对应的目的地址确定出第二目标请求进行处理。
并且,当第一存储设备中数据量满足继续读取条件,通过仲裁模块暂停处理第二目标请求,继续处理第一目标请求。
进一步的,上述方法还包括:
通过状态模块记录全部数据搬移通道对应的搬移状态。
相应的,上述方法还包括:通过仲裁模块将搬移状态写入状态模块,或通过多通道模块将搬移状态写入状态模块。
另外,上述方法还包括:
通过中断模块当任一数据搬移任务完成后,发送对应的中断至主机。
可见,本申请实施例通过配置模块获取主机发送的配置信息,并基于配置信息向多通道模块中相应的多个数据搬移通道分别下发对应的数据搬移任务;通过多通道模块中每个数据搬移通道基于对应的数据搬移任务向仲裁模块发送搬移请求;通过仲裁模块基于预设通道优先级从多个搬移请求中确定出第一目标请求,并处理第一目标请求以通过第一目标请求对应的数据搬移通道将第一存储设备中的目标数据搬移至第二存储设备,当第一目标请求对应的第一存储设备中数据量不足,则基于预设通道优先级确定出第二目标请求进行处理。也即,本申请实施例通过配置数据搬移的源地址、目的地址和搬移数据量通过多个数据搬移通道执行多个数据搬移任务,通过仲裁模块确定出目标请求进行数据搬移,若当前目标请求对应的存储设备数据不足时,确定出新的目标请求进行数据搬移,避免等待时间过程,这样,能够满足多个外部存储设备之间的数据搬移需求,避免总线在多个DMA之间进行切换,提升数据搬移效率。
在一个实施例中,提供了一种计算机设备,该计算机设备可以是终端,其内部结构图可以如图6所示。该计算机设备包括通过系统总线连接的处理器、存储器、网络接口、显示屏和输入装置。其中,该计算机设备的处理器用于提供计算和控制能力。该计算机设备的存储器包括非易失性存储介质、内存储器。该非易失性存储介质存储有操作系统和计算机可读指令。该内存储器为非易失性存储介质中的操作系统和计算机可读指令的运行提供环境。该计算机设备的网络接口用于与外部的终端通过网络连接通信。该计算机可读指令被处理器执行时以实现一种基于FPGA的DMA数据搬移方法。该计算机设备的显示屏可以是液晶显示屏或者电子墨水显示屏,该计算机设备的输入装置可以是 显示屏上覆盖的触摸层,也可以是计算机设备外壳上设置的按键、轨迹球或触控板,还可以是外接的键盘、触控板或鼠标等。
在一个实施例中,提供了一种计算机设备,该计算机设备可以是服务器,其内部结构图可以如图7所示。该计算机设备包括通过系统总线连接的处理器、存储器、网络接口和数据库。其中,该计算机设备的处理器用于提供计算和控制能力。该计算机设备的存储器包括非易失性存储介质、内存储器。该非易失性存储介质存储有操作系统、计算机可读指令和数据库。该内存储器为非易失性存储介质中的操作系统和计算机可读指令的运行提供环境。该计算机设备的数据库用于存储预设通道优先级。该计算机设备的网络接口用于与外部的终端通过网络连接通信。该计算机可读指令被处理器执行时以实现一种基于FPGA的DMA数据搬移方法。
一种计算机设备,包括存储器和一个或多个处理器,存储器中储存有计算机可读指令,计算机可读指令被处理器执行时,使得一个或多个处理器执行上述方法。
一个或多个存储有计算机可读指令的非易失性存储介质,计算机可读指令被一个或多个处理器执行时,使得一个或多个处理器执行上述方法。
本领域普通技术人员可以理解实现上述实施例方法中的全部或部分流程,是可以通过计算机可读指令来指令相关的硬件来完成,所述的计算机可读指令可存储于一非易失性计算机可读取存储介质中,该计算机可读指令在执行时,可包括如上述各方法的实施例的流程。其中,本申请所提供的各实施例中所使用的对存储器、存储、数据库或其它介质的任何引用,均可包括非易失性和/或易失性存储器。非易失性存储器可包括只读存储器(ROM)、可编程ROM(PROM)、电可编程ROM(EPROM)、电可擦除可编程ROM(EEPROM)或闪存。易失性存储器可包括随机存取存储器(RAM)或者外部高速缓冲存储器。作为说明而非局限,RAM以多种形式可得,诸如静态RAM(SRAM)、动态RAM(DRAM)、同步DRAM(SDRAM)、双数据率SDRAM(DDRSDRAM)、增强型SDRAM(ESDRAM)、同步链路(Synchlink)DRAM(SLDRAM)、存储器总线(Rambus)直接RAM(RDRAM)、直接存储器总线动态RAM(DRDRAM)、以及存储器总线动态RAM(RDRAM)等。
以上实施例的各技术特征可以进行任意的组合,为使描述简洁,未对上述实施例中的各个技术特征所有可能的组合都进行描述,然而,只要这些技术特征的组合不存在矛盾,都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本申请的几种实施方式,其描述较为具体和详细,但并不能因此而理解为对发明专利范围的限制。应当指出的是,对于本领域的普通技术人员来 说,在不脱离本申请构思的前提下,还可以做出若干变形和改进,这些都属于本申请的保护范围。因此,本申请专利的保护范围应以所附权利要求为准。

Claims (12)

  1. 一种基于FPGA的DMA设备,其特征在于,包括配置模块、多通道模块、仲裁模块,其中,
    所述配置模块,用于获取主机发送的配置信息,并基于所述配置信息向所述多通道模块中相应的多个数据搬移通道分别下发对应的数据搬移任务;其中,所述配置信息包括每个所述数据搬移通道待搬移的数据量、源地址以及目的地址;
    所述多通道模块,用于通过每个所述数据搬移通道基于对应的所述数据搬移任务向所述仲裁模块发送搬移请求;和
    所述仲裁模块,用于基于预设通道优先级从多个所述搬移请求中确定出第一目标请求,并处理所述第一目标请求以通过所述第一目标请求对应的所述数据搬移通道将第一存储设备中的目标数据搬移至第二存储设备,当所述第一目标请求对应的所述第一存储设备中数据量不足,则基于所述预设通道优先级确定出第二目标请求进行处理。
  2. 根据权利要求1所述的基于FPGA的DMA设备,其特征在于,所述仲裁模块,用于基于所述预设通道优先级以及搬移请求对应的所述目的地址确定出所述第二目标请求进行处理。
  3. 根据权利要求1所述的基于FPGA的DMA设备,其特征在于,所述仲裁模块,还用于当所述第一存储设备中数据量满足继续读取条件,则暂停处理所述第二目标请求,继续处理所述第一目标请求。
  4. 根据权利要求1所述的基于FPGA的DMA设备,其特征在于,所述仲裁模块,用于基于所述第一目标请求从所述第一存储设备中读取所述目标数据,并将所述目标数据放置于所述第一目标请求对应的所述数据搬移通道的缓存中,从所述缓存中读取所述目标数据写入所述第二存储设备中。
  5. 根据权利要求1所述的基于FPGA的DMA设备,其特征在于,还包括:
    状态模块,用于记录全部所述数据搬移通道对应的搬移状态。
  6. 根据权利要求5所述的基于FPGA的DMA设备,其特征在于,所述仲裁模块还用于:
    将所述搬移状态写入所述状态模块。
  7. 根据权利要求5所述的基于FPGA的DMA设备,其特征在于,所述多通道模块还用于:
    将所述搬移状态写入所述状态模块。
  8. 根据权利要求1所述的基于FPGA的DMA设备,其特征在于,还包括:
    中断模块,用于当任一所述数据搬移任务完成后,发送对应的中断至所述主机。
  9. 一种基于FPGA的DMA数据搬移方法,其特征在于,包括:
    通过配置模块获取主机发送的配置信息,并基于所述配置信息向多通道模块中相应的多个数据搬移通道分别下发对应的数据搬移任务;
    通过所述多通道模块中每个所述数据搬移通道基于对应的所述数据搬移任务向仲裁模块发送搬移请求;和
    通过所述仲裁模块基于预设通道优先级从多个所述搬移请求中确定出第一目标请求,并处理所述第一目标请求以通过所述第一目标请求对应的所述数据搬移通道将第一存储设备中的目标数据搬移至第二存储设备,当所述第一目标请求对应的所述第一存储设备中数据量不足,则基于所述预设通道优先级确定出第二目标请求进行处理。
  10. 根据权利要求9所述的基于FPGA的DMA数据搬移方法,其特征在于,所述基于所述预设通道优先级确定出第二目标请求进行处理,包括:
    基于所述预设通道优先级以及搬移请求对应的所述目的地址确定出所述第二目标请求进行处理。
  11. 一种计算机设备,包括存储器及一个或多个处理器,所述存储器中储存有计算机可读指令,所述计算机可读指令被所述一个或多个处理器执行时,使得所述一个或多个处理器执行如权利要求9-10任意一项所述的方法的步骤。
  12. 一个或多个存储有计算机可读指令的非易失性计算机可读存储介质,所述计算机可读指令被一个或多个处理器执行时,使得所述一个或多个处理器执行如权利要求9-10任意一项所述的方法的步骤。
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