WO2022156064A1 - 闪存芯片可靠性等级预测方法、装置及存储介质 - Google Patents

闪存芯片可靠性等级预测方法、装置及存储介质 Download PDF

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WO2022156064A1
WO2022156064A1 PCT/CN2021/083538 CN2021083538W WO2022156064A1 WO 2022156064 A1 WO2022156064 A1 WO 2022156064A1 CN 2021083538 W CN2021083538 W CN 2021083538W WO 2022156064 A1 WO2022156064 A1 WO 2022156064A1
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flash memory
predicted
memory chip
reliability level
prediction model
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PCT/CN2021/083538
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English (en)
French (fr)
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陈卓
张浩明
潘玉茜
刘政林
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置富科技（深圳）股份有限公司
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0614—Improving the reliability of storage systems
    • G06F3/0616—Improving the reliability of storage systems in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0646—Horizontal data movement in storage systems, i.e. moving data in between storage devices or systems
    • G06F3/0652—Erasing, e.g. deleting, data cleaning, moving of data to a wastebasket
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor

Definitions

  • the present invention relates to the technical field of memory, and in particular, to a method, device, storage medium and computer equipment for predicting reliability level of flash memory chips.
  • Flash memory is a kind of non-volatile memory, which has its unique advantages in many aspects, such as: can save data for a long time, fast data transmission speed, large storage capacity and so on. Therefore, the frequency of flash memory in communication, consumption, industrial control, military and other fields is getting higher and higher, and it is getting more and more attention.
  • flash memory also has its shortcomings that cannot be ignored. Among them, the reliability problem is one of the most important problems of flash memory. Because of its unique physical structure, flash memory causes the oxide layer structure of the memory cells to be worn out during use. This wear is irreversible. Once the wear level exceeds a certain limit, data will appear during the data storage process. Bit errors, the uncorrectable data errors generated during flash memory operation, will affect the normal use of the entire storage system. Therefore, in storage systems, error correction algorithms are often added to correct data bit errors caused by reliability problems. However, the error correction algorithm has an error upper limit. Once the number of worn memory cells in the flash memory block exceeds a certain limit, the error correction algorithm cannot completely correct errors, that is, the data after error correction will still have bit errors. The occurrence of this situation will seriously endanger the information security of communication, consumption, industrial control, military and other fields, and even cause inestimable losses.
  • the present application provides a method, device, storage medium and computer equipment for predicting reliability level of flash memory chips, the main purpose of which is to solve the technical problem of poor prediction accuracy of existing methods for predicting reliability level of flash memory chips.
  • a method for predicting the reliability level of a flash memory chip comprising:
  • the second subset in the data set of the flash memory chips to be predicted is input into the second flash memory reliability level prediction model to obtain a first prediction result of the reliability level of the flash memory chips to be predicted.
  • the first prediction result of the reliability level of the flash memory chip to be predicted includes the predicted reliability level of the flash memory chip to be predicted after Tm programming-erase operations, where Tm is defined as the number of program-erase operation cycles.
  • the method further includes: performing T m programming-erase operations on the flash memory chip to be predicted, and collecting the actual reliability level of the flash memory chip to be predicted after the T m programming-erasing operations ;
  • the actual reliability level of the flash memory chip to be predicted after the operation is compared with the predicted reliability level of the flash memory chip to be predicted after T m programming-erase operations; if the actual reliability of the flash memory chip to be predicted after T m programming-erase operations If the reliability level is inconsistent with the predicted reliability level of the flash memory chip to be predicted after T m programming-erase operations, the parameters of the second flash memory reliability level prediction model are adjusted to obtain the third flash memory reliability level prediction model;
  • the third subset in the flash memory chip data set is input into the third flash memory reliability level prediction model to obtain a second prediction
  • performing parameter adjustment on the second flash memory reliability level prediction model to obtain a third flash memory reliability level prediction model including: collecting the to-be-predicted flash memory during T m times of programming-erase operations of the to-be-predicted flash memory chip. at least one feature quantity of the chip; perform operation on at least one feature quantity of the flash memory chip to be predicted, obtain the feature operation value of the flash memory chip to be predicted, and store the feature value of the flash memory chip to be predicted and the feature operation value of the flash memory chip to be predicted In the data set of the flash memory chips to be predicted; the fourth subset in the data set of the flash memory chips to be predicted is input into the optimization program of the second flash memory reliability level prediction model, and the second flash memory reliability level prediction model is carried out. The parameters are adjusted to obtain the third flash memory reliability level prediction model.
  • the number of program-erase operation cycles T m is a single preset value or a combination of multiple preset values, wherein, when T m is a combination of multiple preset values, the flash memory chip to be predicted
  • the first prediction result of the reliability level includes a plurality of predicted reliability levels of the flash memory chip to be predicted after T m programming-erase operations corresponding to the preset values one-to-one.
  • the flash memory product set includes multiple flash memory chips of the same type and different batches under the same manufacturing process; then multiple flash memory chips are extracted from the flash memory product set as sample flash memory chips, including: randomly selected from the flash memory product set. A predetermined number of flash memory chips are extracted as sample flash memory chips.
  • the machine learning classifier includes one or more of a support vector machine classifier, a naive Bayes classifier, a k-nearest neighbor classifier, a decision tree classifier, an ensemble learning classifier, and a linear discriminant classifier.
  • the optimization program of the first flash memory reliability level prediction model and the optimization program of the second flash memory reliability level prediction model correspond to the machine learning classifier used for training the first flash memory reliability level prediction model; wherein the first The optimizer of the flash memory reliability level prediction model and the optimizer of the second flash memory reliability level prediction model include a support vector machine classifier model optimizer, a naive Bayes classifier model optimizer, a k-nearest neighbor classifier model optimizer, a decision-making One or more of a tree classifier model optimizer, an ensemble learning classifier model optimizer, and a linear discriminant classifier model optimizer.
  • the characteristic quantities of the flash memory chips to be predicted and the characteristic quantities of the sample flash memory chips include one or more of the following characteristic quantities: the time of each flash memory operation of the flash memory chip, the current during each flash memory operation, the power consumption of the chip, and the threshold value. Voltage distribution and voltage variation, flash block number, flash page number, current number of program-erase cycles, number of conditionally faulty pages in a flash block, number of conditionally faulty blocks, raw error bits, and raw error bit rate.
  • the operation method of the characteristic quantity of the flash memory chip to be predicted and the operation method of the characteristic quantity of the sample flash memory chip include one or more of the following operation methods: linear operation of the characteristic quantity, nonlinear operation of the characteristic quantity operation, linear operation between different feature quantities, nonlinear operation between different feature quantities, calculating the maximum value of different storage page characteristic quantities, calculating the minimum value of different storage page characteristic quantities, linear operation between different storage page characteristic quantities, Nonlinear operation between different memory page feature quantities, linear operation between different memory block feature quantities, nonlinear operation between different memory block characteristic quantities, calculating the maximum value of different memory block characteristic quantities and calculating different memory block characteristics the minimum value of the quantity.
  • the first prediction result of the reliability level of the flash memory chip to be predicted and the second prediction result of the reliability level of the flash memory chip to be predicted include one or more of the following results: the current error bit of the flash memory chip to be predicted Quantity level, the current error bit rate level of the flash memory chip to be predicted, the number of error bits of the flash memory chip to be predicted after T m program-erase operations, and the error bit rate of the flash memory chip to be predicted after T m program-erase operations level and number of remaining program-erase cycles for the flash chip to be predicted.
  • a device for predicting reliability levels of flash memory chips comprising:
  • a feature quantity collection module used for performing flash memory operation on the flash memory chip to be predicted, and collecting at least one feature quantity of the flash memory chip to be predicted during the flash memory operation process;
  • the data set building module is used to perform an operation on at least one characteristic quantity of the flash memory chip to be predicted, and obtain the characteristic operation value of the flash memory chip to be predicted. According to the characteristic quantity of the flash memory chip to be predicted and the characteristic operation value of the flash memory chip to be predicted, construct The data set of the flash memory chip to be predicted;
  • a model parameter adjustment module configured to input the first subset in the data set of the flash memory chips to be predicted into the optimization program of the first flash memory reliability level prediction model, and adjust the parameters of the first flash memory reliability level prediction model, obtaining a second flash memory reliability level prediction model;
  • the prediction result output module is configured to input the second subset in the data set of the flash memory chips to be predicted into the second flash memory reliability level prediction model to obtain a first prediction result of the reliability level of the flash memory chips to be predicted.
  • a storage medium is provided on which a computer program is stored, and when the program is executed by a processor, the above-mentioned method for predicting the reliability level of a flash memory chip is implemented.
  • a computer device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, the processor implementing the above-mentioned flash memory chip when executing the program Reliability rating prediction method.
  • the invention provides a method, device, storage medium and computer equipment for predicting the reliability level of a flash memory chip.
  • the characteristic operation value is obtained by collecting at least one characteristic quantity of the flash memory chip, and then performing an operation on the collected at least one characteristic quantity. , and then optimize the parameters of the flash memory reliability level prediction model, and finally use the characteristic quantities and characteristic operation values of the flash memory chip as the input of the optimized flash memory reliability level prediction model to obtain the first prediction result of the reliability level of the flash memory chip.
  • the prediction accuracy of the flash memory reliability level prediction model can be effectively improved.
  • the above method obtains the parameter-optimized prediction model by inputting the feature quantity of the chip to be predicted and the operation processing result of the feature quantity into the optimization program of the initial prediction model, which can be differentiated and specialized for each flash memory chip.
  • the model parameters are optimized, which solves the problem that the reliability level prediction accuracy decreases due to the difference between flash memory chips. Therefore, the above method can effectively improve the prediction accuracy of the reliability level of the flash memory chip, and effectively reduce the hidden danger of data security caused by the data failure of the flash memory chip.
  • FIG. 1 shows a schematic flowchart of a method for predicting a reliability level of a flash memory chip provided by an embodiment of the present invention
  • FIG. 2 shows a schematic flowchart of another method for predicting reliability levels of flash memory chips provided by an embodiment of the present invention
  • FIG. 3 shows a schematic flowchart of another method for predicting reliability levels of flash memory chips provided by an embodiment of the present invention
  • FIG. 4 shows a schematic flowchart of a flash memory chip testing method based on flash memory chip reliability level prediction provided by an embodiment of the present invention
  • FIG. 5 shows a schematic flowchart of a method for constructing a flash memory reliability level prediction model based on a decision tree classifier according to an embodiment of the present invention
  • FIG. 6 shows a schematic structural diagram of a method for optimizing a flash memory reliability level prediction model based on a decision tree classifier according to an embodiment of the present invention
  • FIG. 7 shows a schematic structural diagram of an apparatus for predicting a reliability level of a flash memory chip provided by an embodiment of the present invention
  • FIG. 8 shows a schematic structural diagram of another device for predicting reliability levels of flash memory chips according to an embodiment of the present invention.
  • a method for predicting the reliability level of a flash memory chip is provided, and the method is applied to a computer device as an example for description, including the following steps:
  • the flash memory operation refers to the programming operation, reading operation and erasing operation of the flash memory chip.
  • the programming operation and the erasing operation are counted as one operation cycle.
  • This operation cycle is usually It is called a P-E (Program-Erase) operation.
  • the feature quantity refers to the physical information and the life information of the flash memory chip that can be collected by the computer equipment through the flash memory test device during the flash memory operation of the flash memory chip, such as the time, current, and voltage distribution of the flash memory operation, the number of the flash memory block, and the length of the flash memory block.
  • the more important characteristic quantity is the lifetime information of the flash memory chip, such as the number of original error bits in the page of the flash memory block and the number of program-erase cycles that the flash memory block has experienced currently. Through these lifetime information, the computer device can know to the current state of the flash memory chip to be predicted, so that a more accurate prediction can be made.
  • the computer device can perform an operation on one or more characteristic quantities of the flash memory chip to be predicted, and obtain one or more characteristic operation values of the flash memory chip to be predicted. Perform an average operation on the original page error bits of the page, and obtain the arithmetic average of the page original error bits of all pages in the flash memory block of the flash memory chip to be predicted. And obtain the square mean of the original page error bits of all pages in the flash block, the median of the page original error bits of all pages in the flash block and other characteristic operation values.
  • the computer device can store the collected characteristic quantities of the flash memory chips to be predicted and the characteristic operation values of the flash memory chips to be predicted obtained by operation in the same data set, thereby constructing the data set of the flash memory chips to be predicted.
  • the computer equipment can also continuously perform flash operations on the predicted chip in the subsequent prediction process to obtain more feature quantities and feature operation values, and use these features.
  • Quantities and characteristic operation values are stored in the data set of the flash memory chip to be predicted, thereby continuously enriching the data in the data set.
  • the computer device can perform a single operation on one feature of the flash memory chip to be predicted, or can perform a combined operation on multiple features of the flash chip to be predicted.
  • the feature quantities are operated in various forms to obtain various feature operation values. It can be understood that the more types of feature quantities of the flash memory chips to be predicted, and the richer the operation modes of the feature quantities of the flash memory chips to be predicted, the more helpful it is to obtain accurate reliability level prediction results of the flash memory chips to be predicted.
  • the first flash memory reliability level prediction model refers to the initial prediction model pre-trained based on the machine learning classifier
  • the second flash memory reliability level prediction model refers to the prediction after targeted parameter optimization for the flash memory chip to be predicted model
  • the optimization program of the first flash memory reliability level prediction model refers to an optimization program corresponding to the machine learning classifier used for training the first flash memory reliability level prediction model
  • the first flash memory reliability level prediction model used for training The machine learning classifier can include one or more classifiers such as support vector machine classifier, naive Bayes classifier, k-nearest neighbor classifier, decision tree classifier, ensemble learning classifier and linear discriminant classifier. The example is not specifically limited here.
  • the computer device may input the first subset of the data set of the flash memory chips to be predicted into the optimization program of the first flash memory reliability level prediction model, and according to the first flash memory reliability level prediction model corresponding to the optimization program In each optimization step, the parameters of the first flash memory reliability level prediction model are adjusted, so as to obtain a second flash memory reliability level prediction model after parameter optimization.
  • the first subset is a data subset randomly selected from the data set for predicting flash memory chips, and the data amount in the first subset is less than or equal to the data amount in the data set for predicting flash memory chips.
  • the computer device may input the second subset in the data set of the flash memory chips to be predicted into the second flash memory reliability level prediction model after parameter optimization, so as to obtain the first prediction result of the reliability level of the flash memory chips to be predicted .
  • the second subset is another data subset randomly selected from the data set of the predicted flash memory chip, the amount of data in the second subset is less than or equal to the amount of data in the data set of the predicted flash memory chip, and,
  • the second subset may be the same or a different subset than the first subset, and the second subset and the first subset may or may not have an intersection. It can be understood that when the overlap rate of the data in the second subset and the data in the first subset is smaller, the predicted result is more objective and true.
  • the reliability level of the flash memory chip to be predicted may include the current reliability level of the flash memory chip to be predicted, the reliability level of the flash memory chip to be predicted after programming-erasing a preset number of times, and the reliability level of the flash memory chip to be predicted. Remaining life rating and other results.
  • the reliability level may be represented by an error bit number level and/or an error bit rate level
  • the remaining life level may be represented by a remaining program-erase cycle number level.
  • the number of error bits refers to the number of error bits generated by the uncorrected data read after the flash chip read operation compared with the data written during the programming operation;
  • the error bit rate level refers to the flash chip read The proportion of error bits generated by the uncorrected data read after the operation compared with the data written during the programming operation;
  • the number of remaining program-erase cycles refers to the number of flash memory chips from the current to the time of exceeding a certain error rate. The number of program-erase cycles experienced between.
  • the numerical intervals of the number of error bits, the error bit rate, and the number of remaining program-erase cycles can be divided into two or more sub-intervals, and each sub-interval corresponds to a reliability level.
  • the method for predicting the reliability level of a flash memory chip collects at least one feature quantity of the flash memory chip, and then performs an operation operation on the collected at least one feature quantity to obtain a feature operation value, and then predicts the reliability level of the flash memory model. Carry out parameter optimization, and finally use the characteristic quantity and characteristic operation value of the flash memory chip as the input of the optimized flash memory reliability level prediction model to obtain the first prediction result of the reliability level of the flash memory chip. Compared with the prediction model whose quantity is the input, the prediction accuracy of the flash memory reliability level prediction model can be effectively improved.
  • the above method obtains the parameter-optimized prediction model by inputting the feature quantity of the chip to be predicted and the operation processing result of the feature quantity into the optimization program of the initial prediction model, which can be differentiated and specialized for each flash memory chip.
  • the model parameters are optimized, which solves the problem that the reliability level prediction accuracy decreases due to the difference between flash memory chips. Therefore, the above method can effectively improve the prediction accuracy of the reliability level of the flash memory chip, and effectively reduce the hidden danger of data security caused by the data failure of the flash memory chip.
  • a method for predicting the reliability level of a flash memory chip includes the following steps:
  • an initial prediction model of the reliability level of the flash memory must be established first, that is, the first flash memory reliability level prediction model is established.
  • the first step in establishing the model is to extract a plurality of flash memory chips from the flash memory product collection as sample flash memory chips, and collect at least one characteristic quantity of each sample flash memory chip through a flash memory test device.
  • the flash memory product set includes multiple flash memory chips of the same type and different batches under the same manufacturing process.
  • the specific method for extracting sample flash memory chips may be: randomly select from the flash memory product set A predetermined number of flash memory chips are taken as sample flash memory chips.
  • the sample flash memory chips include multiple sample flash memory chips with the same process, type and model but different batches. In this way, the diversity of training samples can be guaranteed, thereby better enhancing the generalization ability of the initial prediction model and reducing the burden of subsequent model parameter optimization.
  • the numbers of the sample flash memory chips can preferably cover the front, middle and rear areas in the flash memory number list.
  • the collected characteristic quantities of the sample flash memory chip may include one or more of the following characteristic quantities: the time of each flash memory operation of the flash memory chip (including programming time, reading time, erasing time, etc. ), the current during each flash memory operation (including the current during programming, the current during reading, and the current during erasing, etc.), chip power consumption, threshold voltage distribution and voltage variation, flash block number, flash page number, current Number of Program-Erase Cycles, Number of Conditionally Errored Pages in Flash Block, Number of Conditionally Errored Blocks, Number of Raw Error Bits, and Raw Error Bit Rate. It can be understood that, the more types and quantities of the characteristic quantities of the sample flash memory chips collected, the more helpful the training of the output accurate flash memory reliability level prediction model.
  • the method for collecting the characteristic quantity of a sample flash memory chip may include the following steps: firstly recording the current number of program-erase cycles of the sample flash memory chip by a flash memory test device, and then sending test data to the sample flash memory chip, The erase operation and editing operation are performed on the sample flash memory chip, and the current and power consumption when the sample flash memory chip performs the editing operation, as well as the programming time of each page of the sample flash memory chip and the memory block number corresponding to the programming time are collected through the flash memory test device. Store the page number. After the editing operation is performed, the data is not stored or the data is stored for a certain period of time, and the read operation is performed on the sample flash memory chip.
  • the threshold voltage distribution of the sample flash memory chip when the read operation is performed is collected by the flash memory test device. , current, power consumption, and reading time of each page of the sample flash memory chip, and finally compare the data read during the read operation with the data written during the edit operation to obtain the number of conditional error pages and conditional error blocks of the sample flash memory chip number, raw error bits, and raw error bit rate.
  • the method of collecting the threshold voltage distribution of the sample flash memory chip is as follows: the flash memory test device executes the command set required for the read operation, so that the reference voltage of the read operation of the sample flash memory chip is shifted, and then the read operation reference voltage is shifted.
  • the data obtained by the operation is mathematically analyzed and operated to obtain the threshold voltage distribution of the sample flash memory chip. It should be noted that in the process of predicting the reliability level of the sample flash memory chips, it is necessary to perform multiple rounds of programming-erase operations on all the sample flash memory chips in the above-mentioned manner, and continuously collect each sample flash memory chip during the operation. At least one characteristic quantity for each round of program-erase operations of the sample flash chip.
  • the second step of establishing the model is to perform an operation on one or more characteristic quantities of the sample flash memory chip, so as to obtain one or more characteristic operation values of the sample flash memory chip, and then use the collected sample flash memory chip's characteristic operation value.
  • the feature quantity and the feature operation value of the sample flash memory chip obtained by operation are stored in the same data set, so that the data set of the sample flash memory chip is constructed.
  • the computer device can perform a single operation on one feature of the sample flash memory chip, or can perform a combined operation on multiple features of the sample flash chip.
  • the feature quantities are operated in various forms to obtain various feature operation values.
  • the operation method of the feature quantity of the sample flash memory chip may include one or more of the following operation methods: linear operation of the feature quantity, nonlinear operation of the feature quantity, between different feature quantities linear operation, nonlinear operation between different feature quantities, calculation of the maximum value of different storage page characteristic quantities, calculation of the minimum value of different storage page characteristic quantities, linear operation between different storage page characteristic quantities, and difference between different storage page characteristic quantities.
  • the third step of building the model is to use a subset of the data set of the sample flash memory chip as the input of the selected machine learning classifier, and train the model according to the training steps of the selected machine learning classifier, and obtain A trained predictive model.
  • the subset selected from the data set of the sample flash memory chip is a data subset randomly selected, and the amount of data in the subset is less than or equal to the amount of data in the data set of the sample flash memory chip, and the sample flash memory Another mutually exclusive subset that is not selected in the data set of the chip can be used as test data to adjust the parameters of the trained prediction model, thereby obtaining the first flash memory reliability level prediction model.
  • the machine learning classifier used for training the first flash memory reliability level prediction model may be a support vector machine classifier, a naive Bayes classifier, a k-nearest neighbor classifier, a decision tree classifier, an ensemble One or more of a learning classifier and a linear discriminant classifier, which is not specifically limited in this embodiment.
  • the reliability level of the flash memory chip to be predicted can be predicted by using the first flash memory reliability level prediction model.
  • the first step of prediction is to perform several flash operations on the flash memory chip to be predicted, and collect one or more characteristic quantities of the flash memory chip to be predicted through the flash memory test system during the flash memory operation.
  • the collected characteristic quantities of the flash memory chips to be predicted correspond to the characteristic quantities of the sample flash memory chips used for training the model, and may also include one or more of the following characteristic quantities: Operation time, current during each flash operation, chip power consumption, threshold voltage distribution and voltage variation, flash block number, flash page number, current program-erase cycles, number of conditional error pages in the flash block, conditional error blocks number, raw error bits, and raw error bit rate. It can be understood that the more types and quantities of the collected feature quantities of the flash memory chip to be predicted, the more helpful it is to obtain an accurate prediction result of the reliability level.
  • the second step of prediction is to perform an operation on one or more characteristic quantities of the flash memory chip to be predicted, so as to obtain one or more characteristic operation values of the flash memory chip to be predicted, and then collect the collected flash memory chip to be predicted.
  • the feature quantity of the to-be-predicted flash memory chip and the characteristic operation value of the to-be-predicted flash memory chip obtained by the operation are stored in the same data set, thereby constructing the data set of the to-be-predicted flash memory chip. It should be noted that, after the data set of the flash memory chip to be predicted is constructed, the computer equipment can also continuously perform flash memory operations on the predicted chip in the subsequent prediction process to obtain more feature quantities and feature operation values.
  • feature quantities and feature operation values are stored in the data set of the flash memory chip to be predicted, so as to continuously enrich the data in the data set.
  • the computer device can perform a single operation on one feature of the flash memory chip to be predicted, or can perform a combined operation on multiple features of the flash chip to be predicted.
  • the feature quantities are operated in various forms to obtain various feature operation values.
  • the operation method of the feature quantity of the flash memory chip to be predicted corresponds to the operation method of the feature quantity of the sample flash memory chip, and may also include one or more of the following operation methods: Linear operation of quantity, nonlinear operation of characteristic quantity, linear operation between different characteristic quantities, nonlinear operation between different characteristic quantities, calculating the maximum value of different storage page characteristic quantities, calculating the minimum value of different storage page characteristic quantities, different Linear operation between storage page feature quantities, nonlinear operation between different storage page characteristic quantities, linear operation between different storage block characteristic quantities, nonlinear operation between different storage block characteristic quantities, calculation of different storage block characteristics The maximum value of the quantity and the minimum value of the characteristic quantity of different memory blocks are calculated. It can be understood that the more types and quantities of characteristic operation values of the flash memory chip to be predicted, the more helpful it is to obtain an accurate prediction result of the reliability level.
  • the third step of prediction is to input the first subset in the data set of the flash memory chips to be predicted into the optimization program of the first flash memory reliability level prediction model, and according to the first flash memory reliability level prediction model corresponding
  • Each optimization step in the optimization program adjusts parameters of the first flash memory reliability level prediction model, so as to obtain a second flash memory reliability level prediction model after parameter optimization.
  • the first subset is a data subset randomly selected from the data set for predicting flash memory chips, and the data amount in the first subset is less than or equal to the data amount in the data set for predicting flash memory chips.
  • the optimization procedure of the first flash reliability level prediction model corresponds to the machine learning classifier used for training the first flash memory reliability level prediction model, for example, when the first flash memory reliability level prediction model When it is a support vector machine classifier model, the optimization program of the first flash memory reliability level prediction model is an optimization program of the support vector machine classifier model.
  • the optimization program of the first flash memory reliability level prediction model may include a support vector machine classifier model optimization program, a naive Bayes classifier model optimization program, a k-nearest neighbor One or more of a classifier model optimizer, a decision tree classifier model optimizer, an ensemble learning classifier model optimizer, and a linear discriminant classifier model optimizer.
  • the fourth step of prediction is to input the second subset in the data set of the flash memory chip to be predicted into the second flash memory reliability level prediction model after parameter optimization, so as to obtain the first reliability level of the flash memory chip to be predicted.
  • a prediction result is another data subset randomly selected from the data set of the predicted flash memory chip, the amount of data in the second subset is less than or equal to the amount of data in the data set of the predicted flash memory chip, and,
  • the second subset may be the same or a different subset than the first subset, and the second subset and the first subset may or may not have an intersection. It can be understood that when the overlap rate of the data in the second subset and the data in the first subset is smaller, the predicted result is more objective and true.
  • the first prediction result of the reliability level of the flash memory chip to be predicted includes the predicted reliability level of the flash memory chip to be predicted after T m programming-erase operations, where T m is defined as programming - The number of cycles for the erase operation.
  • the number of program-erase operation cycles T m may be a single preset value, or may be a combination of multiple preset values, wherein, when T m is a combination of multiple preset values , the first prediction result of the reliability level of the flash memory chip to be predicted also includes a plurality of predicted reliability levels of the flash memory chip to be predicted after T m programming-erase operations corresponding to the preset values one-to-one. In this way, the method can accurately predict the reliability level of the flash memory chip after a certain number of PE operations, thereby effectively reducing data security risks caused by data failure of the flash memory chip.
  • the second flash memory reliability level is determined.
  • the parameters of the prediction model are adjusted to obtain a third flash memory reliability level prediction model.
  • the predicted reliability level of the flash memory chip to be predicted after T m programming-erase operations in the first prediction result can be further optimized.
  • the second flash memory reliability level prediction model is used to obtain a third flash memory reliability level prediction model that is more targeted and more accurate, and a more accurate second prediction result is obtained through the third flash memory reliability level prediction model.
  • the first step in optimizing the prediction model is to perform T m times of programming-erase operations on the flash memory chip to be predicted, and collect and calculate the actual reliability level of the flash memory chip to be predicted after T m times of programming-erase operations .
  • the second step of optimizing the prediction model is to program the actual reliability level of the flash memory chip to be predicted after the acquisition and calculation T m times of programming-erase operations and the T m times of programming output by the second flash memory reliability level prediction model. - Compare the predicted reliability levels of the flash memory chips to be predicted after the erase operation.
  • the third step of optimizing the prediction model that is, adjust the parameters of the second flash memory reliability level prediction model to obtain a third flash memory Reliability level prediction model, if the two are consistent, record the number of programming-erase cycles currently experienced by the flash memory chip to be predicted, and predict the reliability level of the flash memory chip to be predicted again to obtain Tr ( T r > T m )
  • the predicted reliability level of the flash memory chip is to be predicted, and then the above steps related to optimizing the prediction model are repeated. In this way, multiple rounds of parameter optimization can be continuously performed on the first flash memory reliability level prediction model, and a third flash memory reliability level prediction model with higher prediction accuracy and wider prediction range can be obtained.
  • the parameter adjustment is performed on the second flash memory reliability level prediction model
  • the method for obtaining the third flash memory reliability level prediction model specifically includes the following steps: first, During the T m times of programming-erase operations of the flash memory chip to be predicted, at least one feature of the flash memory chip to be predicted is collected, and then an operation is performed on at least one feature of the flash memory chip to be predicted to obtain the flash memory chip to be predicted.
  • Feature operation value then store the feature quantity of the flash memory chip to be predicted and the feature operation value of the flash memory chip to be predicted in the data set of the flash memory chip to be predicted, and finally input the fourth subset in the data set of the flash memory chip to be predicted into
  • the parameters of the second flash memory reliability level prediction model are adjusted to obtain a third flash memory reliability level prediction model.
  • the optimization program of the second flash memory reliability level prediction model corresponds to the machine learning classifier used for training the first flash memory reliability level prediction model
  • the fourth subset is selected from the data set for predicting flash memory chips
  • a subset of data the amount of data in the fourth subset is less than or equal to the amount of data in the data set for predicting flash memory chips
  • the fourth subset contains the flash memory chips to be predicted collected during the T m programming-erase operations.
  • the third subset in the data set of the flash memory chips to be predicted can also be input into the third flash memory reliability level prediction model in order to obtain a more accurate second prediction result of the reliability level of the flash memory chip to be predicted, and after obtaining a new second prediction result through the third flash memory reliability level prediction model, the above steps 208 to 210 may be repeated. , to get a more accurate flash memory reliability level prediction model and prediction results. In this way, parameter optimization and reliability level prediction of the prediction model can be continuously performed during the normal operation of the flash memory, which further improves the prediction accuracy.
  • the first prediction result of the reliability level of the flash memory chip to be predicted and the second prediction result of the reliability level of the flash memory chip to be predicted include one or more of the following results: to be predicted The current level of the number of error bits of the flash memory chip, the current level of the error bit rate of the flash memory chip to be predicted, the level of the number of error bits of the flash memory chip to be predicted after T m times of program-erase operations, and the level of the number of error bits of the flash memory chip to be predicted after T m times of program-erase operations The error bit rate rating of the flash chip and the remaining program-erase cycle number rating of the flash chip to be predicted.
  • the number of error bits refers to the number of error bits generated by the uncorrected data read after the flash chip read operation compared with the data written during the programming operation;
  • the error bit rate level refers to the flash chip read The proportion of error bits generated by the uncorrected data read after the operation compared with the data written during the programming operation;
  • the number of remaining program-erase cycles refers to the number of flash memory chips from the current to the time of exceeding a certain error rate. The number of program-erase cycles experienced between.
  • the numerical intervals of the number of error bits, the error bit rate, and the number of remaining program-erase cycles can be divided into two or more sub-intervals, and each sub-interval corresponds to a reliability level.
  • an initial prediction model of the reliability level of a flash memory chip is obtained by using the characteristic quantity of the sample flash memory chip and the characteristic operation value of the sample flash memory chip. Compared with the prediction model whose feature quantity is input, the prediction accuracy of the flash memory reliability level prediction model can be effectively improved.
  • the method optimizes the parameters of the trained initial prediction model by using the characteristic quantity of the flash memory chip to be predicted and the characteristic operation value of the sample flash memory chip during the actual use of the flash memory chip to be predicted, and further improves the flash memory reliability level prediction model. prediction accuracy.
  • the method can continuously optimize the flash memory reliability prediction model, which greatly improves the reliability of the prediction model for each flash memory chip. Prediction accuracy of grades.
  • FIG. 3 is a schematic flowchart of establishing and optimizing a flash memory reliability level prediction model according to this embodiment.
  • the flash memory chip test flow shown in Figure 4 based on the flash reliability level applies to all types of flash memory chips from all manufacturers.
  • the model building and optimization process based on the decision tree classifier shown in Figure 5 and Figure 6 is applicable to other machine learning classifiers.
  • the following takes a manufacturer's TLC NAND Flash flash memory product (hereinafter referred to as "Model M flash memory”) as an example to introduce the steps of flash chip testing, model establishment, and model optimization, and explain each step in Figure 3 in detail.
  • Model M flash memory manufacturer's TLC NAND Flash flash memory product
  • step 1 the characteristic quantity of the sample flash memory chip is collected and an arithmetic operation is performed to construct a data set of the sample flash memory chip.
  • This step is the data collection and processing for building an initial prediction model for flash reliability levels.
  • the sample flash memory chips are selected according to the following rules: the sample flash memory needs to be selected from different batches of model M flash memory with the same process, type, and model, so as to ensure the diversity of training samples and better enhance the initial prediction
  • the generalization ability of the model reduces the burden of subsequent model parameter optimization.
  • 96 flash memory blocks of different batches of type M flash memory are selected for data collection, and the numbers of the sample flash memory blocks cover the front, middle and rear areas in the flash memory number list.
  • Tpe Determine the value of Tpe . If the value of Tpe is a multiple of 50, a page read operation is performed on the sample flash block. Compare the read page data with the test pattern written in the programming operation of the corresponding page, obtain and record the flash memory error information, and then go to step (5). If the value of T pe is not a multiple of 50, go directly to step (2).
  • step (2) Determine whether the original page error bit rate RBER in the flash memory error information exceeds the upper limit value T of the ECC error correction algorithm. If it exceeds, the test will be stopped and the test termination flag of the sample flash block will be returned. If it does not exceed, go to step (2).
  • the collected characteristic quantities of the sample flash memory chip include: the number of original page error bits of the flash memory block, and the number of program-erase cycles that the flash memory block has experienced currently.
  • the operation on the characteristic quantity of the sample flash memory chip includes: taking an arithmetic average of the original page error bit numbers of all pages in the flash memory block where x i is the original number of error bits in the i-th page, and n is the maximum flash page number), take the square average of the original number of error bits in all pages in the flash block Where x i is the page original error bit number of the i-th page, n is the maximum flash page number), and the median is the page original error bit number of all pages in the flash block.
  • Step 2 Adjust the parameters of the initial prediction model of the decision tree, use a subset of the sample flash memory chip data set as the model input, train the initial prediction model, and extract the initial prediction model function.
  • the input of the initial prediction model based on the decision tree classifier includes: the arithmetic mean of the original number of error bits in the page, the square mean of the number of original error bits in the page, the median of the number of original error bits in the page, the current The number of program-erase cycles elapsed.
  • the prediction target of the initial prediction model is the reliability level of the flash memory after T m times of PE operations, where T m is set to 100, and the reliability level is divided into five categories, which respectively represent the total original error bits of the flash memory block. five ranges of numbers.
  • Step 3 Collect characteristic quantities of the flash memory chip to be predicted and perform arithmetic operations to construct a data set of the flash memory chip to be predicted, and record the number of programming-erase cycles experienced by the flash memory block at the moment as T renew . This step is for subsequent data collection for the optimization of the parameters of the initial prediction model.
  • the feature quantity and operation operation of the flash memory chip to be predicted are the same as in step 1.
  • Step 4 Take a subset of the data set of the flash memory chip to be predicted, input it into the decision tree classifier model optimization program, optimize and adjust the parameters in the initial prediction model that has been trained, and replace the original prediction model with the parameter-optimized prediction model. prediction model.
  • step (3) If the node queue is not empty, the first node P in the node queue is taken out, and P is found in the old decision tree model, followed by step (3). If the node queue is empty, proceed to step (7).
  • step (3) Determine whether there is a node P in the old decision tree model. If the node P exists in the old decision tree model, the node P is stored on the node of the old decision tree model, followed by step (4). If there is no node P in the old decision tree model, go to step (5).
  • step (6) Determine whether the reliability level corresponding to the node P is the same as the reliability level corresponding to the old decision tree model. If they are the same, proceed directly to step (6). If different, update the attribute list and the CC table, re-divide the node P according to the new attribute list and the CC table, then reconstruct the subtree of the node P, and then proceed to step (6).
  • Step 5 During the subsequent normal operation of the flash memory chip to be predicted, the operation of step 3 is repeated, and a subset of the new data set of the flash memory chip to be predicted is input into the updated reliability level prediction model to obtain the predicted flash memory.
  • the chip reliability level G predict and the number of programming-erase cycles T now experienced by the flash memory block is recorded at the same time, and the two are combined into a combination (T now , G predict ) and saved.
  • Step 6 when the number of programming-erase cycles that the flash memory block has experienced is T now + T m , determine whether G predict is the same as the actual reliability level G real of the flash memory block to be predicted currently. If the same, go to step seven. If not, skip to step 4, and re-optimize the parameters of the old decision tree reliability level prediction model.
  • Step 7 when the number of program-erase cycles experienced by the flash memory block is T renew + Tr (T r is the number of PE cycles required for re-optimization of the prediction model parameters when the prediction is correct, in this embodiment, T r is 500), jump to step 4, and re-optimize the parameters of the old decision tree reliability level prediction model, so as to continuously optimize the parameters of the prediction model and predict the reliability level during the normal operation of the flash memory.
  • T r is the number of PE cycles required for re-optimization of the prediction model parameters when the prediction is correct, in this embodiment, T r is 500
  • this embodiment provides an apparatus for predicting reliability levels of flash memory chips.
  • the apparatus includes: a feature quantity collection module 31 , a data set construction Module 32 , model parameter adjustment module 33 and prediction result output module 34 .
  • the feature quantity collection module 31 can be used to perform flash memory operation on the flash memory chip to be predicted, and collect at least one feature quantity of the flash memory chip to be predicted during the flash memory operation process;
  • the data set building module 32 can be used to perform an operation on at least one feature quantity of the flash memory chip to be predicted to obtain the feature operation value of the flash memory chip to be predicted, and according to the feature quantity of the flash memory chip to be predicted and the feature operation value of the flash memory chip to be predicted, Construct the data set of the flash memory chip to be predicted;
  • the model parameter adjustment module 33 is configured to input the first subset in the data set of the flash memory chips to be predicted into the optimization program of the first flash memory reliability level prediction model, and adjust the parameters of the first flash memory reliability level prediction model , obtain the second flash memory reliability level prediction model;
  • the prediction result output module 34 may be configured to input the second subset in the data set of the flash memory chips to be predicted into the second flash memory reliability level prediction model to obtain a first prediction result of the reliability level of the flash memory chips to be predicted.
  • the feature collection module 31 can also be used to perform T m times of programming-erase operations on the flash memory chip to be predicted, and collect the actual reliability of the flash memory chip to be predicted after T m times of programming-erase operations reliability level; compare the actual reliability level of the flash memory chip to be predicted after T m programming-erase operations with the predicted reliability level of the flash memory chip to be predicted after T m programming-erasing operations; if T m programming-erasures - If the actual reliability level of the flash memory chip to be predicted after the erase operation is inconsistent with the predicted reliability level of the flash memory chip to be predicted after the T m times of programming-erase operation, the model parameter adjustment module 33 can also be used to adjust the second flash memory
  • the reliability level prediction model performs parameter adjustment to obtain a third flash memory reliability level prediction model; the first prediction result output module 34 can also be used to input the third subset of the data set of the flash memory chips to be predicted into the third flash memory In the reliability level prediction model, a second prediction result of the reliability level of
  • the model parameter adjustment module 33 can also be specifically used to collect at least one feature quantity of the flash memory chip to be predicted during the T m times of programming-erase operations of the flash memory chip to be predicted; Perform an operation on at least one feature of the flash memory chip to obtain a feature operation value of the flash memory chip to be predicted, and store the feature value of the flash memory chip to be predicted and the feature operation value of the flash memory chip to be predicted in the data set of the flash memory chip to be predicted; Input the fourth subset in the data set of the flash memory chips to be predicted into the optimization program of the second flash memory reliability level prediction model, and adjust the parameters of the second flash memory reliability level prediction model to obtain the third flash memory reliability level prediction model.
  • the number of program-erase operation cycles T m is a single preset value or a combination of multiple preset values, wherein, when T m is a combination of multiple preset values, the number to be predicted
  • the first prediction result of the reliability level of the flash memory chip includes a plurality of predicted reliability levels of the flash memory chip to be predicted after T m programming-erase operations corresponding to the preset values one-to-one.
  • the device further includes a prediction model training module 35, which can specifically be used to extract a plurality of flash memory chips from the flash memory product set as sample flash memory chips, and Collect at least one feature quantity of the sample flash memory chip through the flash memory test system; perform operation on at least one feature quantity of the sample flash memory chip to obtain the feature operation value of the sample flash memory chip, according to the feature quantity of the sample flash memory chip and the sample flash memory chip.
  • the feature operation value is used to construct the data set of the sample flash memory chip; the subset of the data set of the flash memory chip to be predicted is used as the input of the machine learning classifier, and the machine learning classifier is trained to obtain the first flash memory reliability level prediction model.
  • the flash memory product collection contains multiple flash memory chips of the same type and different batches under the same manufacturing process; then multiple flash memory chips are extracted from the flash memory product collection as sample flash memory chips, including: A predetermined number of flash memory chips are randomly selected from the set as sample flash memory chips.
  • machine learning classifiers include one or more of support vector machine classifiers, naive Bayes classifiers, k-nearest neighbor classifiers, decision tree classifiers, ensemble learning classifiers and linear discriminant classifiers kind.
  • the optimization program of the first flash memory reliability level prediction model and the optimization program of the second flash memory reliability level prediction model correspond to the machine learning classifier used for training the first flash memory reliability level prediction model; wherein , the optimization program of the first flash reliability level prediction model and the optimization program of the second flash memory reliability level prediction model include support vector machine classifier model optimization program, naive Bayes classifier model optimization program, k-nearest neighbor classifier model optimization program One or more of a program, a decision tree classifier model optimizer, an ensemble learning classifier model optimizer, and a linear discriminant classifier model optimizer.
  • the characteristic quantities of the flash memory chips to be predicted and the characteristic quantities of the sample flash memory chips include one or more of the following characteristic quantities: the time of each flash memory operation of the flash memory chip, the current of each flash memory operation, the chip function power consumption, threshold voltage distribution and voltage variation, flash block number, flash page number, number of current program-erase cycles, number of conditionally faulty pages in flash block, number of conditionally faulty blocks, number of raw error bits, and raw error bit rate.
  • the operation method of the feature quantity of the flash memory chip to be predicted and the operation method of the feature quantity of the sample flash memory chip include one or more of the following operation methods: linear operation of the feature quantity, feature quantity non-linear operations, linear operations between different feature quantities, nonlinear operations between different feature quantities, calculating the maximum value of different storage page characteristic quantities, calculating the minimum value of different storage page characteristic quantities, and the difference between different storage page characteristic quantities.
  • Linear operation, nonlinear operation between different storage page feature quantities, linear operation between different storage block characteristic quantities, nonlinear operation between different storage block characteristic quantities, calculating the maximum value of different storage block characteristic quantities and calculating different The minimum value of the block feature quantity is stored.
  • the first prediction result of the reliability level of the flash memory chip to be predicted and the second prediction result of the reliability level of the flash memory chip to be predicted include one or more of the following results: Current error bit count level, current error bit rate level of the flash memory chip to be predicted, error bit count level of the flash memory chip to be predicted after T m program-erase operations, error bit count level of the flash memory chip to be predicted after T m program-erase operations Error bit rate level and number of remaining program-erase cycles for the flash chip to be predicted.
  • this embodiment further provides a storage medium on which a computer program is stored.
  • the program is executed by a processor, the above-mentioned methods shown in FIGS. 1 to 6 are implemented.
  • the technical solution of the present application can be embodied in the form of a software product, and the software product to be identified can be stored in a non-volatile storage medium (which can be a CD-ROM, U disk, mobile hard disk, etc.), Several instructions are included to cause a computer device (which may be a personal computer, a server, or a network device, etc.) to execute the methods described in various implementation scenarios of this application.
  • a computer device which may be a personal computer, a server, or a network device, etc.
  • this embodiment further provides a reliability level of flash memory chips
  • the predicted physical device can specifically be a personal computer, a server, a smart phone, a tablet computer, a smart watch, or other network devices, etc.
  • the physical device includes a storage medium and a processor; a storage medium for storing computer programs; a processor, It is used to execute a computer program to realize the above-mentioned methods as shown in FIGS. 1 to 6 .
  • the physical device may further include a user interface, a network interface, a camera, a radio frequency (Radio Frequency, RF) circuit, a sensor, an audio circuit, a WI-FI module, and the like.
  • the user interface may include a display screen (Display), an input unit such as a keyboard (Keyboard), etc., and the optional user interface may also include a USB interface, a card reader interface, and the like.
  • Optional network interfaces may include standard wired interfaces, wireless interfaces (such as WI-FI interfaces), and the like.
  • the physical device structure for predicting the reliability level of a flash memory chip provided in this embodiment does not constitute a limitation on the physical device, and may include more or less components, or combine some components, Or a different component arrangement.
  • the storage medium may also include an operating system and a network communication module.
  • the operating system is a program that manages the above-mentioned physical device hardware and software resources to be identified, and supports the operation of information processing programs and other software and/or programs to be identified.
  • the network communication module is used to realize the communication between various components in the storage medium, as well as the communication with other hardware and software in the information processing entity device.
  • the present application can be implemented by means of software plus a necessary general hardware platform, and can also be implemented by hardware.
  • the subset is input into the optimization program of the first flash memory reliability level prediction model, and the parameters of the first flash memory reliability level prediction model are adjusted to obtain the second flash memory reliability level prediction model, and finally the to-be-predicted flash memory chip data set is included.
  • the second subset of the flash memory chips is input into the second flash memory reliability level prediction model to obtain a first prediction result of the reliability level of the flash memory chip to be predicted.
  • the above method obtains the characteristic operation value by collecting at least one characteristic quantity of the flash memory chip, and performing an operation on the collected at least one characteristic quantity, and uses the characteristic quantity and characteristic operation value of the flash memory chip as the characteristic operation value.
  • the common input of the flash memory reliability level prediction model compared with the prediction model obtained by training only based on the feature quantity, the prediction accuracy of the flash memory reliability level prediction model proposed by this method is higher.
  • the characteristic quantities and the operation processing results of the characteristic quantities are input into the optimization program of the initial prediction model, and the prediction model after parameter optimization is obtained.
  • the above method can effectively improve the prediction accuracy of the reliability level of the flash memory chip, thereby effectively reducing the hidden danger of data security caused by the data failure of the flash memory chip.
  • the accompanying drawing is only a schematic diagram of a preferred implementation scenario, and the modules or processes in the accompanying drawing are not necessarily necessary to implement the present application.
  • the modules in the device in the implementation scenario may be distributed in the device in the implementation scenario according to the description of the implementation scenario, or may be located in one or more devices different from the implementation scenario with corresponding changes.
  • the modules of the above implementation scenarios may be combined into one module, or may be further split into multiple sub-modules.

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Abstract

本发明公开了一种闪存芯片可靠性等级预测方法、装置及存储介质。其中方法包括：对待预测闪存芯片进行闪存操作，并在闪存操作过程中采集待预测闪存芯片的至少一种特征量；对待预测闪存芯片的至少一种特征量进行运算操作，得到待预测闪存芯片的特征运算值，依据待预测闪存芯片的特征量和待预测闪存芯片的特征运算值，建构待预测闪存芯片的数据集合；将待预测闪存芯片的数据集合中的第一子集输入到第一闪存可靠性等级预测模型的优化程序中，并对第一闪存可靠性等级预测模型进行参数调整，得到第二闪存可靠性等级预测模型；将待预测闪存芯片数据集合中的第二子集输入到第二闪存可靠性等级预测模型中，得到待预测闪存芯片的可靠性等级的第一预测结果。上述方法可以提高闪存芯片可靠性等级的预测准确度。

Description

闪存芯片可靠性等级预测方法、装置及存储介质
本申请要求与2021年01月19日提交中国专利局、申请号为202110066138.1、申请名称为“闪存芯片可靠性等级预测方法、装置及存储介质”的中国专利申请的优先权，其全部内容通过引用结合在申请中。
技术领域
本发明涉及存储器技术领域，尤其是涉及一种闪存芯片可靠性等级预测方法、装置、存储介质及计算机设备。
背景技术
存储器作为数据存储的载体，早已出现在现代电子产品的各个角落，并成为电子系统中不可或缺的一部分。在存储器领域，闪存扮演着十分重要的角色。闪存是一种非易失性存储器，在许多方面有其独特的优点，如：能长时间保存数据、数据传输速度快、存储容量较大等等。因此，闪存在通信、消费、工业控制、军事等领域出现的频率越来越高，也越来越受到重视。
但闪存也有其不可忽视的缺点。其中，可靠性问题便是闪存最主要的问题之一。闪存因为其独特的物理结构，导致其在使用过程中，存储单元的氧化层结构会遭受到磨损，这种磨损是不可逆的，一旦磨损程度超过一定限度，就会在数据存储过程中，出现数据比特错误，闪存运行时产生的这种无法纠正的数据错误将会影响到整个存储系统的正常使用。因此，在存储系统中，往往会加入纠错算法，来纠正因可靠性问题导致的数据比特错误。但是，纠错算法存在错误上限，一旦闪存存储块内发生磨损的存储单元数量超过一定限度，纠错算法就会无法完全纠错，即纠错后的数据仍将出现比特错误。这种情况的发生将会严重地危害通信、消费、工业控制、军事等领域的信息安全，甚至造成不可估计的损失。
基于以上的原因，目前就出现了一些预测闪存可靠性等级的方法，通过这些方法，可以使用户了解闪存内部的损耗情况，并及时做出存储策略调整，从而延长闪存的使用寿命，以及避免因存储器中突发性的闪存数据错误增加而导致的损失。但是，由于闪存芯片之间存在一定差异，这就导致了闪存芯片可靠性等级预测难以达到较高的准确度。因此，如何提高闪存芯片可靠性等级预测的准确度，成为目前亟需解决的问题。
发明内容
有鉴于此，本申请提供了一种闪存芯片可靠性等级预测方法、装置、存储介质及计算机设备，主要目的在于解决现有闪存芯片可靠性等级预测方法的预测准确度较差的技术问题。
根据本发明的第一个方面，提供了一种闪存芯片可靠性等级预测方法，该方法包括：
对待预测闪存芯片进行闪存操作，并在闪存操作过程中采集待预测闪存芯片的至少一种特征量；
对待预测闪存芯片的至少一种特征量进行运算操作，得到待预测闪存芯片的特征运算值，依据待预测闪存芯片的特征量和待预测闪存芯片的特征运算值，建构待预测闪存芯片的数据集合；
将待预测闪存芯片的数据集合中的第一子集输入到第一闪存可靠性等级预测模型的优化程序中，并对第一闪存可靠性等级预测模型进行参数调整，得到第二闪存可靠性等级预测模型；
将待预测闪存芯片数据集合中的第二子集输入到第二闪存可靠性等级预测模型中，得到待预测闪存 芯片的可靠性等级的第一预测结果。
可选的，待预测闪存芯片的可靠性等级的第一预测结果包括T m次编程-擦除操作后待预测闪存芯片的预测可靠性等级，其中，T m定义为编程-擦除操作周期数，则该方法还包括：对待预测闪存芯片进行T m次编程-擦除操作，并采集T m次编程-擦除操作后待预测闪存芯片的实际可靠性等级；将T m次编程-擦除操作后待预测闪存芯片的实际可靠性等级与T m次编程-擦除操作后待预测闪存芯片的预测可靠性等级进行比较；若T m次编程-擦除操作后待预测闪存芯片的实际可靠性等级与T m次编程-擦除操作后待预测闪存芯片的预测可靠性等级不一致，则对第二闪存可靠性等级预测模型进行参数调整，得到第三闪存可靠性等级预测模型；将待预测闪存芯片数据集合中的第三子集输入到第三闪存可靠性等级预测模型中，得到待预测闪存芯片的可靠性等级的第二预测结果。
可选的，对第二闪存可靠性等级预测模型进行参数调整，得到第三闪存可靠性等级预测模型，包括：在待预测闪存芯片的T m次编程-擦除操作过程中，采集待预测闪存芯片的至少一种特征量；对待预测闪存芯片的至少一种特征量进行运算操作，得到待预测闪存芯片的特征运算值，将待预测闪存芯片的特征量和待预测闪存芯片的特征运算值存储在待预测闪存芯片的数据集合中；将待预测闪存芯片的数据集合中的第四子集输入到第二闪存可靠性等级预测模型的优化程序中，并对第二闪存可靠性等级预测模型进行参数调整，得到第三闪存可靠性等级预测模型。
可选的，编程-擦除操作周期数T m为单一预设定值或多个预设定值的组合，其中，当T m为多个预设定值的组合时，待预测闪存芯片的可靠性等级的第一预测结果包括多个与预设定值一一对应的T m次编程-擦除操作后待预测闪存芯片的预测可靠性等级。
可选的，第一闪存可靠性等级预测模型的训练方法，包括：从闪存产品集合中抽取出多个闪存芯片作为样本闪存芯片，并通过闪存测试系统采集样本闪存芯片的至少一种特征量；对样本闪存芯片的至少一种特征量进行运算操作，得到样本闪存芯片的特征运算值，依据样本闪存芯片的特征量和样本闪存芯片的特征运算值，建构样本闪存芯片的数据集合；将样本闪存芯片的数据集合中的子集作为机器学习分类器的输入，对机器学习分类器进行训练，得到第一闪存可靠性等级预测模型。
可选的，闪存产品集合中包含同一制造工艺下相同类型且不同批次的多种闪存芯片；则从闪存产品集合中抽取出多个闪存芯片作为样本闪存芯片，包括：从闪存产品集合中随机抽取出预定数量的闪存芯片作为样本闪存芯片。
可选的，机器学习分类器包括支持向量机分类器、朴素贝叶斯分类器、k近邻分类器、决策树分类器、集成学习分类器和线性判别分类器中的一种或多种。
可选的，第一闪存可靠性等级预测模型的优化程序和第二闪存可靠性等级预测模型的优化程序与第一闪存可靠性等级预测模型训练所用的机器学习分类器相对应；其中，第一闪存可靠性等级预测模型的优化程序和第二闪存可靠性等级预测模型的优化程序包括支持向量机分类器模型优化程序、朴素贝叶斯分类器模型优化程序、k近邻分类器模型优化程序、决策树分类器模型优化程序、集成学习分类器模型优化程序、线性判别分类器模型优化程序中的一种或多种。
可选的，待预测闪存芯片的特征量和样本闪存芯片的特征量包括以下特征量中的一种或多种：闪存芯片各闪存操作的时间、各闪存操作时的电流、芯片功耗、阈值电压分布及电压变化量、闪存块编号、闪存页编号、当前编程-擦除周期数、闪存块中条件错误页数、条件错误块数、原始错误比特数和原始错误比特率。
可选的，待预测闪存芯片的特征量的运算操作方法和样本闪存芯片的特征量的运算操作方法包括以下运算操作方法中的一种或多种：特征量的线性运算、特征量的非线性运算、不同特征量间的线性运算、不同特征量间的非线性运算、计算不同存储页面特征量的最大值、计算不同存储页面特征量的最小 值、不同存储页面特征量之间的线性运算、不同存储页面特征量之间的非线性运算、不同存储块特征量之间的线性运算、不同存储块特征量之间的非线性运算、计算不同存储块特征量的最大值和计算不同存储块特征量的最小值。
可选的，待预测闪存芯片的可靠性等级的第一预测结果和待预测闪存芯片的可靠性等级的第二预测结果包括以下结果中的一种或多种：待预测闪存芯片的当前错误比特数量等级、待预测闪存芯片的当前错误比特率等级、T m次编程-擦除操作后待预测闪存芯片的错误比特数量等级、T m次编程-擦除操作后待预测闪存芯片的错误比特率等级和待预测闪存芯片的剩余编程-擦除周期数量等级。
根据本发明的第二个方面，提供了一种闪存芯片可靠性等级预测装置，该装置包括：
特征量采集模块，用于对待预测闪存芯片进行闪存操作，并在闪存操作过程中采集待预测闪存芯片的至少一种特征量；
数据集合构建模块，用于对待预测闪存芯片的至少一种特征量进行运算操作，得到待预测闪存芯片的特征运算值，依据待预测闪存芯片的特征量和待预测闪存芯片的特征运算值，建构待预测闪存芯片的数据集合；
模型参数调整模块，用于将待预测闪存芯片的数据集合中的第一子集输入到第一闪存可靠性等级预测模型的优化程序中，并对第一闪存可靠性等级预测模型进行参数调整，得到第二闪存可靠性等级预测模型；
预测结果输出模块，用于将待预测闪存芯片数据集合中的第二子集输入到第二闪存可靠性等级预测模型中，得到待预测闪存芯片的可靠性等级的第一预测结果。
根据本发明的第三个方面，提供了一种存储介质，其上存储有计算机程序，所述程序被处理器执行时实现上述闪存芯片可靠性等级预测方法。
根据本发明的第四个方面，提供了一种计算机设备，包括存储器、处理器及存储在存储器上并可在处理器上运行的计算机程序，所述处理器执行所述程序时实现上述闪存芯片可靠性等级预测方法。
本发明提供的一种闪存芯片可靠性等级预测方法、装置、存储介质及计算机设备，通过采集闪存芯片的至少一种特征量，然后对采集到的至少一种特征量进行运算操作得到特征运算值，继而对闪存可靠性等级预测模型进行参数优化，最后将闪存芯片的特征量和特征运算值作为优化后的闪存可靠性等级预测模型的输入得到闪存芯片的可靠性等级的第一预测结果，相比单一的只以闪存芯片的特征量为输入的预测模型相比，可以有效的提高闪存可靠性等级预测模型的预测准确度。此外，上述方法通过将待预测芯片的特征量和特征量的运算处理结果输入到初始预测模型的优化程序中，得到参数优化后的预测模型，能够差异化地针对每一个闪存芯片进行专一化的模型参数优化，从而解决了因为闪存芯片之间的差异导致的可靠性等级预测准确率下降的问题。因此，上述方法可以有效提高闪存芯片可靠性等级的预测准确度，并有效降低因为闪存芯片数据失效导致的数据安全隐患。
上述说明仅是本申请技术方案的概述，为了能够更清楚了解本申请的技术手段，而可依照说明书的内容予以实施，并且为了让本申请的上述和其它目的、特征和优点能够更明显易懂，以下特举本申请的具体实施方式。
附图说明
此处所说明的附图用来提供对本发明的进一步理解，构成本申请的一部分，本发明的示意性实施例及其说明用于解释本发明，并不构成对本发明的不当限定。在附图中：
图1示出了本发明实施例提供的一种闪存芯片可靠性等级预测方法的流程示意图；
图2示出了本发明实施例提供的另一种闪存芯片可靠性等级预测方法的流程示意图；
图3示出了本发明实施例提供的又一种闪存芯片可靠性等级预测方法的流程示意图；
图4示出了本发明实施例提供的一种基于闪存芯片可靠性等级预测的闪存芯片测试方法的流程示意图；
图5示出了本发明实施例提供的一种基于决策树分类器的闪存可靠性等级预测模型的构建方法的流程示意图；
图6示出了本发明实施例提供的一种基于决策树分类器的闪存可靠性等级预测模型的优化方法的结构示意图；
图7示出了本发明实施例提供的一种闪存芯片可靠性等级预测装置的结构示意图；
图8示出了本发明实施例提供的另一种闪存芯片可靠性等级预测装置的结构示意图。
具体实施方式
下文中将参考附图并结合实施例来详细说明本发明。需要说明的是，在不冲突的情况下，本申请中的实施例及实施例中的特征可以相互组合。
在一个实施例中，如图1所示，提供了一种闪存芯片可靠性等级预测方法，以该方法应用于计算机设备为例进行说明，包括以下步骤：
101、对待预测闪存芯片进行闪存操作，并在闪存操作过程中采集待预测闪存芯片的至少一种特征量。
其中，闪存操作是指对闪存芯片进行编程操作、读取操作和擦除操作，一般来说，在对闪存芯片进行测试时会将编程操作和擦除操作算作一次操作周期，这个操作周期通常称为P-E(编程-擦除)操作。特征量指的是闪存芯片在进行闪存操作过程中计算机设备可以通过闪存测试装置采集到的物理信息和闪存芯片寿命信息，如闪存操作的时间、电流、电压分布、闪存块的编号、闪存块的页原始错误比特数，闪存块当前已经历的编程-擦除周期数等等。
具体的，在对待预测闪存芯片进行可靠性等级预测时，首先要对待预测闪存芯片进行若干次的闪存操作，并在闪存操作的过程中采集待预测闪存芯片的一种或多种特征量。在本实施例中，较为重要的特征量是闪存芯片的寿命信息，如闪存块的页原始错误比特数和闪存块当前已经历的编程-擦除周期数，通过这些寿命信息，计算机设备可以了解到待预测闪存芯片的当前状态，从而做出更加准确的预测。
102、对待预测闪存芯片的至少一种特征量进行运算操作，得到待预测闪存芯片的特征运算值，依据待预测闪存芯片的特征量和待预测闪存芯片的特征运算值，建构待预测闪存芯片的数据集合。
具体的，计算机设备可以对待预测闪存芯片的一种或多种特征量进行运算操作，并得到待预测闪存芯片的一种或多种特征运算值，如计算机设备可以对待预测闪存芯片闪存块内所有页的页原始错误比特数进行平均数运算操作，并得到待预测闪存芯片闪存块内所有页的页原始错误比特数的算数平均数，此外，计算机设备还可以对特征量进行其他形式的运算，并得到闪存块内所有页的页原始错误比特数的平方平均数，闪存块内所有页的页原始错误比特数的中位数等多种特征运算值。
进一步的，计算机设备可以将采集到的待预测闪存芯片的特征量以及运算得到的待预测闪存芯片的特征运算值存在同一个数据集合中，从而建构出待预测闪存芯片的数据集合，需要说明的是，待预测闪 存芯片的数据集合在构建完成后，计算机设备还可以在后续的预测过程中不断地对待预测芯片进行闪存操作，以获取到更多的特征量以及特征运算值，并将这些特征量和特征运算值存储在待预测闪存芯片的数据集合中，从而不断丰富数据集合中的数据。在本实施例中，计算机设备可以对待预测闪存芯片的一种特征量进行单独运算操作，也可以对待预测闪存芯片的多种特征量进行组合运算操作，计算机设备还可以根据采集到的不同种类的特征量进行多种形式的运算，从而得到多种特征运算值。可以理解的是，待预测闪存芯片的特征量的种类越多、待预测闪存芯片的特征量的运算操作方式越丰富，越有助于得到准确的待预测闪存芯片的可靠性等级预测结果。
103、将待预测闪存芯片的数据集合中的第一子集输入到第一闪存可靠性等级预测模型的优化程序中，并对第一闪存可靠性等级预测模型进行参数调整，得到第二闪存可靠性等级预测模型。
其中，第一闪存可靠性等级预测模型指的是基于机器学习分类器预先训练好的初始预测模型，第二闪存可靠性等级预测模型指的是针对待预测闪存芯片进行针对性参数优化后的预测模型，第一闪存可靠性等级预测模型的优化程序指的是与第一闪存可靠性等级预测模型训练所用的机器学习分类器相对应的优化程序，其中，第一闪存可靠性等级预测模型训练所用的机器学习分类器可以包括支持向量机分类器、朴素贝叶斯分类器、k近邻分类器、决策树分类器、集成学习分类器和线性判别分类器等一种或多种分类器，本实施例在此不做具体限定。
具体的，计算机设备可以将待预测闪存芯片的数据集合中的第一子集输入到第一闪存可靠性等级预测模型的优化程序中，并依据第一闪存可靠性等级预测模型对应的优化程序中的各个优化步骤对第一闪存可靠性等级预测模型进行参数调整，从而得到参数优化后的第二闪存可靠性等级预测模型。在本实施例中，第一子集为从预测闪存芯片的数据集合随机选取出的一个数据子集，第一子集中的数据量小于等于预测闪存芯片的数据集合中的数据量。
104、将待预测闪存芯片数据集合中的第二子集输入到第二闪存可靠性等级预测模型中，得到待预测闪存芯片的可靠性等级的第一预测结果。
具体的，计算机设备可以将待预测闪存芯片数据集合中的第二子集输入到参数优化后的第二闪存可靠性等级预测模型中，从而得到待预测闪存芯片的可靠性等级的第一预测结果。在本实施例中，第二子集为从预测闪存芯片的数据集合随机选取出的另一个数据子集，第二子集中的数据量小于等于预测闪存芯片的数据集合中的数据量，并且，第二子集可以是与第一子集相同或不同的子集，第二子集和第一子集可以有交集或没有交集。可以理解的是，当第二子集中的数据与第一子集中的数据重叠率较小时，预测的结果更加客观真实。
在本实施例中，待预测闪存芯片的可靠性等级可以包括待预测闪存芯片当前的可靠性等级，待预测闪存芯片经过预设次数编程-擦除后的可靠性等级等级以及待预测闪存芯片的剩余寿命等级等多种结果。具体的，可靠性等级可以用错误比特数量等级和/或错误比特率等级来表示，剩余寿命等级可以用剩余编程-擦除周期数量等级来表示。其中，错误比特数量指的是闪存芯片读取操作后读取的未经纠错的数据与编程操作时写入的数据相比产生的错误比特数量；错误比特率等级指的是闪存芯片读取操作后读取的未经纠错的数据与编程操作时写入的数据相比产生的错误比特所占比例；剩余编程-擦除周期数量指的是闪存芯片由当前直至超过一定的错误率之间经历的编程-擦除周期数量。在本实施例中，错误比特数量、错误比特率以及剩余编程-擦除周期数量的数值区间均可以划分为两个或两个以上的子区间，每个子区间对应一个可靠性等级。
本实施例提供的闪存芯片可靠性等级预测方法，通过采集闪存芯片的至少一种特征量，然后对采集到的至少一种特征量进行运算操作得到特征运算值，继而对闪存可靠性等级预测模型进行参数优化，最后将闪存芯片的特征量和特征运算值作为优化后的闪存可靠性等级预测模型的输入得到闪存芯片的可靠性等级的第一预测结果，相比单一的只以闪存芯片的特征量为输入的预测模型相比，可以有效的提高 闪存可靠性等级预测模型的预测准确度。此外，上述方法通过将待预测芯片的特征量和特征量的运算处理结果输入到初始预测模型的优化程序中，得到参数优化后的预测模型，能够差异化地针对每一个闪存芯片进行专一化的模型参数优化，从而解决了因为闪存芯片之间的差异导致的可靠性等级预测准确率下降的问题。因此，上述方法可以有效提高闪存芯片可靠性等级的预测准确度，并有效降低因为闪存芯片数据失效导致的数据安全隐患。
进一步的，作为上述实施例具体实施方式的细化和扩展，为了完整说明本实施例的实施过程，提供了闪存芯片可靠性等级预测方法，如图2所示，该方法包括以下步骤：
201、从闪存产品集合中抽取出多个闪存芯片作为样本闪存芯片，并通过闪存测试系统采集样本闪存芯片的至少一种特征量。
具体的，在对待预测闪存芯片进行可靠性等级预测之前，首先要建立闪存可靠性等级的初始预测模型，即建立第一闪存可靠性等级预测模型。建立模型的第一步是从闪存产品集合中抽取出多个闪存芯片作为样本闪存芯片，并通过闪存测试装置采集每一个样本闪存芯片的至少一种特征量。
在一个可选的实施方式中，闪存产品集合中包含有同一制造工艺下相同类型且不同批次的多种闪存芯片，那么，抽取样本闪存芯片的具体方法可以为：从闪存产品集合中随机抽取出预定数量的闪存芯片作为样本闪存芯片。其中，样本闪存芯片中涵盖有相同工艺、类型和型号但批次不同的多个样本闪存芯片。通过这种方式，可以保证训练样本的多样性，从而更好地增强初始预测模型的泛化能力，减轻后续模型参数优化的负担。在本实施例中，样本闪存芯片的编号最好能够覆盖到闪存编号列表中的前中后区域。
在一个可选的实施方式中，采集的样本闪存芯片的特征量可以包括以下特征量中的一种或多种：闪存芯片各闪存操作的时间(包括编程时间、读取时间和擦除时间等)、各闪存操作时的电流(包括编程时的电流、读取时的电流和擦除时的电流等)、芯片功耗、阈值电压分布及电压变化量、闪存块编号、闪存页编号、当前编程-擦除周期数、闪存块中条件错误页数、条件错误块数、原始错误比特数和原始错误比特率。可以理解的是，采集到的样本闪存芯片的特征量的种类和数量越多，越有助于训练出输出准确的闪存可靠性等级预测模型。
在一个可选的实施方式中，采集样本闪存芯片的特征量的方法可以包括以下步骤：首先通过闪存测试装置记录样本闪存芯片的当前编程-擦除周期数，然后向样本闪存芯片发送测试数据，并对样本闪存芯片执行擦除操作和编辑操作，同时通过闪存测试装置采集样本闪存芯片执行编辑操作时的电流和功耗，以及样本闪存芯片各个页面的编程时间和编程时间对应的存储块号和存储页号，在执行完编辑操作之后，不保持数据存储或保持数据储存一定时长后，对样本闪存芯片执行读取操作，同时通过闪存测试装置采集样本闪存芯片执行读取操作时的阈值电压分布、电流、功耗以及样本闪存芯片各个页面的读取时间，最后将读取操作时读取的数据与编辑操作时写入的数据进行比较，得到样本闪存芯片的条件错误页数、条件错误块数、原始错误比特数和原始错误比特率。在本实施方式中，采集样本闪存芯片的阈值电压分布的方式为：通过闪存测试装置执行读取操作所需的命令集，使得样本闪存芯片的读取操作参考电压产生偏移，然后对读取操作所得的数据进行数学分析和运算，得到样本闪存芯片的阈值电压分布。需要说明的是，在对样本闪存芯片的可靠性等级进行预测的过程中，需要通过上述方式对所有的样本闪存芯片进行多轮的编程-擦除操作，并在操作的过程中不断采集每一个样本闪存芯片的每一轮编程-擦除操作的至少一种特征量。
202、对样本闪存芯片的至少一种特征量进行运算操作，得到样本闪存芯片的特征运算值，依据样本闪存芯片的特征量和样本闪存芯片的特征运算值，建构样本闪存芯片的数据集合。
具体的，建立模型的第二步是对样本闪存芯片的一种或多种特征量进行运算操作，从而得到样本闪存芯片的一种或多种特征运算值，然后将采集到的样本闪存芯片的特征量以及运算得到的样本闪存芯片的特征运算值存在同一个数据集合中，从而建构出样本闪存芯片的数据集合。在本实施例中，计算机设备可以对样本闪存芯片的一种特征量进行单独运算操作，也可以对样本闪存芯片的多种特征量进行组合运算操作，计算机设备还可以根据采集到的不同种类的特征量进行多种形式的运算，从而得到多种特征运算值。
在一个可选的实施方式中，样本闪存芯片的特征量的运算操作方法可以包括以下运算操作方法中的一种或多种：特征量的线性运算、特征量的非线性运算、不同特征量间的线性运算、不同特征量间的非线性运算、计算不同存储页面特征量的最大值、计算不同存储页面特征量的最小值、不同存储页面特征量之间的线性运算、不同存储页面特征量之间的非线性运算、不同存储块特征量之间的线性运算、不同存储块特征量之间的非线性运算、计算不同存储块特征量的最大值和计算不同存储块特征量的最小值。可以理解的是，样本闪存芯片的特征运算值的种类和数量越多，越有助于训练出输出准确的闪存可靠性等级预测模型。
203、将样本闪存芯片的数据集合中的子集作为机器学习分类器的输入，对机器学习分类器进行训练，得到第一闪存可靠性等级预测模型。
具体的，建立模型的第三步是将样本闪存芯片的数据集合中的一个子集作为选定的机器学习分类器的输入，按照选定的机器学习分类器的训练步骤对模型进行训练，得到训练好的预测模型。在本实施例中，从样本闪存芯片的数据集合中选取出的子集为随机选取出的一个数据子集，该子集中的数据量小于等于样本闪存芯片的数据集合中的数据量，样本闪存芯片的数据集合中未选取出的另一个互斥子集可以作为测试数据，对训练好的预测模型进行参数调整，从而得到第一闪存可靠性等级预测模型。
在一个可选的实施方式中，训练第一闪存可靠性等级预测模型所用的机器学习分类器可以为支持向量机分类器、朴素贝叶斯分类器、k近邻分类器、决策树分类器、集成学习分类器和线性判别分类器中的一种或多种，本实施例在此不做具体限定。
204、对待预测闪存芯片进行闪存操作，并在闪存操作过程中采集待预测闪存芯片的至少一种特征量。
具体的，在第一闪存可靠性等级预测模型训练完成之后，即可通过第一闪存可靠性等级预测模型对待预测闪存芯片的可靠性等级进行预测。预测的第一步是对待预测闪存芯片进行若干次的闪存操作，并在闪存操作的过程中通过闪存测试系统采集待预测闪存芯片的一种或多种特征量。
在一个可选的实施方式中，采集的待预测闪存芯片的特征量与训练模型所用的样本闪存芯片的特征量相对应，同样可以包括以下特征量中的一种或多种：闪存芯片各闪存操作的时间、各闪存操作时的电流、芯片功耗、阈值电压分布及电压变化量、闪存块编号、闪存页编号、当前编程-擦除周期数、闪存块中条件错误页数、条件错误块数、原始错误比特数和原始错误比特率。可以理解的是，采集到的待预测闪存芯片的特征量的种类和数量越多，越有助于得到准确的可靠性等级的预测结果。
205、对待预测闪存芯片的至少一种特征量进行运算操作，得到待预测闪存芯片的特征运算值，依据待预测闪存芯片的特征量和待预测闪存芯片的特征运算值，建构待预测闪存芯片的数据集合。
具体的，预测的第二步是对待预测闪存芯片的一种或多种特征量进行运算操作，从而得到待预测闪存芯片的一种或多种特征运算值，然后将采集到的待预测闪存芯片的特征量以及运算得到的待预测闪存芯片的特征运算值存在同一个数据集合中，从而建构出待预测闪存芯片的数据集合。需要说明的是，待预测闪存芯片的数据集合在构建完成后，计算机设备还可以在后续的预测过程中不断地对待预测芯片进行闪存操作，以获取到更多的特征量以及特征运算值，并将这些特征量和特征运算值存储在待预测闪存 芯片的数据集合中，从而不断丰富数据集合中的数据。在本实施例中，计算机设备可以对待预测闪存芯片的一种特征量进行单独运算操作，也可以对待预测闪存芯片的多种特征量进行组合运算操作，计算机设备还可以根据采集到的不同种类的特征量进行多种形式的运算，从而得到多种特征运算值。
在一个可选的实施方式中，待预测闪存芯片的特征量的运算操作方法与样本闪存芯片的特征量的运算操作方法相对应，同样可以包括以下运算操作方法中的一种或多种：特征量的线性运算、特征量的非线性运算、不同特征量间的线性运算、不同特征量间的非线性运算、计算不同存储页面特征量的最大值、计算不同存储页面特征量的最小值、不同存储页面特征量之间的线性运算、不同存储页面特征量之间的非线性运算、不同存储块特征量之间的线性运算、不同存储块特征量之间的非线性运算、计算不同存储块特征量的最大值和计算不同存储块特征量的最小值。可以理解的是，待预测闪存芯片的特征运算值的种类和数量越多，越有助于得到准确的可靠性等级的预测结果。
206、将待预测闪存芯片的数据集合中的第一子集输入到第一闪存可靠性等级预测模型的优化程序中，并对第一闪存可靠性等级预测模型进行参数调整，得到第二闪存可靠性等级预测模型。
具体的，预测的第三步是将待预测闪存芯片的数据集合中的第一子集输入到第一闪存可靠性等级预测模型的优化程序中，并依据第一闪存可靠性等级预测模型对应的优化程序中的各个优化步骤对第一闪存可靠性等级预测模型进行参数调整，从而得到参数优化后的第二闪存可靠性等级预测模型。在本实施例中，第一子集为从预测闪存芯片的数据集合随机选取出的一个数据子集，第一子集中的数据量小于等于预测闪存芯片的数据集合中的数据量。
在一个可选的实施方式中，第一闪存可靠性等级预测模型的优化程序与第一闪存可靠性等级预测模型训练所用的机器学习分类器相对应，例如，当第一闪存可靠性等级预测模型为支持向量机分类器模型时，第一闪存可靠性等级预测模型的优化程序就为支持向量机分类器模型的优化程序。具体的，与第一闪存可靠性等级预测模型相对应的，第一闪存可靠性等级预测模型的优化程序可以包括支持向量机分类器模型优化程序、朴素贝叶斯分类器模型优化程序、k近邻分类器模型优化程序、决策树分类器模型优化程序、集成学习分类器模型优化程序、线性判别分类器模型优化程序中的一种或多种。
207、将待预测闪存芯片数据集合中的第二子集输入到第二闪存可靠性等级预测模型中，得到待预测闪存芯片的可靠性等级的第一预测结果。
具体的，预测的第四步是将待预测闪存芯片数据集合中的第二子集输入到参数优化后的第二闪存可靠性等级预测模型中，从而得到待预测闪存芯片的可靠性等级的第一预测结果。在本实施例中，第二子集为从预测闪存芯片的数据集合随机选取出的另一个数据子集，第二子集中的数据量小于等于预测闪存芯片的数据集合中的数据量，并且，第二子集可以是与第一子集相同或不同的子集，第二子集和第一子集可以有交集或没有交集。可以理解的是，当第二子集中的数据与第一子集中的数据重叠率较小时，预测的结果更加客观真实。
在一个可选的实施方式中，待预测闪存芯片的可靠性等级的第一预测结果中包括T m次编程-擦除操作后待预测闪存芯片的预测可靠性等级，其中，T m定义为编程-擦除操作周期数。在本实施方式中，编程-擦除操作周期数T m可以为单一预设定值，也可以为多个预设定值的组合，其中，当T m为多个预设定值的组合时，待预测闪存芯片的可靠性等级的第一预测结果也包括多个与预设定值一一对应的T m次编程-擦除操作后待预测闪存芯片的预测可靠性等级。通过这种方式，本方法可以对一定次数P-E操作后闪存芯片可靠性等级进行准确预测，从而有效地降低因为闪存芯片数据失效导致数据安全隐患。
208、对待预测闪存芯片进行T m次编程-擦除操作，并采集T m次编程-擦除操作后待预测闪存芯片的实际可靠性等级。
209、将T m次编程-擦除操作后待预测闪存芯片的实际可靠性等级与T m次编程-擦除操作后待预测闪存芯片的预测可靠性等级进行比较。
210、若T m次编程-擦除操作后待预测闪存芯片的实际可靠性等级与T m次编程-擦除操作后待预测闪存芯片的预测可靠性等级不一致，则对第二闪存可靠性等级预测模型进行参数调整，得到第三闪存可靠性等级预测模型。
具体的，在得到待预测闪存芯片的可靠性等级的第一预测结果之后，还可以通过第一预测结果中的T m次编程-擦除操作后待预测闪存芯片的预测可靠性等级进一步优化第二闪存可靠性等级预测模型，从而得到针对性更强和准确性更高的第三闪存可靠性等级预测模型，并通过第三闪存可靠性等级预测模型得到更准确的第二预测结果。
在本实施例中，优化预测模型的第一步是对待预测闪存芯片进行T m次编程-擦除操作，并采集和计算T m次编程-擦除操作后待预测闪存芯片的实际可靠性等级。进一步的，优化预测模型的第二步是将采集和计算得到的T m次编程-擦除操作后待预测闪存芯片的实际可靠性等级与第二闪存可靠性等级预测模型输出的T m次编程-擦除操作后待预测闪存芯片的预测可靠性等级进行比较，若二者不一致，则进行优化预测模型的第三步，即对第二闪存可靠性等级预测模型进行参数调整，得到第三闪存可靠性等级预测模型，若二者一致，则记录待预测闪存芯片当前经历的编程-擦除周期次数，并对待预测闪存芯片的可靠性等级进行再次预测，得到T r(T r>T m)次编程-擦除操作后待预测闪存芯片的预测可靠性等级，然后重复上述优化预测模型相关步骤。通过这种方式，可以持续对第一闪存可靠性等级预测模型进行多轮参数优化，并得到预测准确度较高且预测范围较广的第三闪存可靠性等级预测模型。
在一个可选的实施方式中，在优化预测模型的第三步中，对第二闪存可靠性等级预测模型进行参数调整，得到第三闪存可靠性等级预测模型的方法具体包括以下步骤：首先，在待预测闪存芯片的T m次编程-擦除操作过程中，采集待预测闪存芯片的至少一种特征量，然后对待预测闪存芯片的至少一种特征量进行运算操作，得到待预测闪存芯片的特征运算值，继而将待预测闪存芯片的特征量和待预测闪存芯片的特征运算值存储在待预测闪存芯片的数据集合中，最后将待预测闪存芯片的数据集合中的第四子集输入到第二闪存可靠性等级预测模型的优化程序中，并对第二闪存可靠性等级预测模型进行参数调整，得到第三闪存可靠性等级预测模型。在本实施例中，第二闪存可靠性等级预测模型的优化程序与第一闪存可靠性等级预测模型训练所用的机器学习分类器相对应，第四子集为从预测闪存芯片的数据集合选取出的一个数据子集，第四子集中的数据量小于等于预测闪存芯片的数据集合中的数据量，并且，第四子集中包含待预测闪存芯片在T m次编程-擦除操作过程中采集到的特征量以及这些特征量运算得到的特征运算值。
211、将待预测闪存芯片数据集合中的第三子集输入到第三闪存可靠性等级预测模型中，得到待预测闪存芯片的可靠性等级的第二预测结果。
具体的，在得到针对性更强和准确性更高的第三闪存可靠性等级预测模型之后，还可以将待预测闪存芯片数据集合中的第三子集输入到第三闪存可靠性等级预测模型中，从而得到更准确的待预测闪存芯片的可靠性等级的第二预测结果，并且，在通过第三闪存可靠性等级预测模型得到新的第二预测结果之后，还可以重复上述步骤208至210，以得到更准确的闪存可靠性等级预测模型和预测结果。通过这种方式，可以在闪存正常操作过程中，持续地进行预测模型的参数优化和可靠性等级预测，进一步提高了预测的准确度。
在一个可选的实施方式中，待预测闪存芯片的可靠性等级的第一预测结果和待预测闪存芯片的可靠性等级的第二预测结果中包括以下结果中的一种或多种：待预测闪存芯片的当前错误比特数量等级、待预测闪存芯片的当前错误比特率等级、T m次编程-擦除操作后待预测闪存芯片的错误比特数量等级、T m次编程-擦除操作后待预测闪存芯片的错误比特率等级和待预测闪存芯片的剩余编程-擦除周期数量等 级。其中，错误比特数量指的是闪存芯片读取操作后读取的未经纠错的数据与编程操作时写入的数据相比产生的错误比特数量；错误比特率等级指的是闪存芯片读取操作后读取的未经纠错的数据与编程操作时写入的数据相比产生的错误比特所占比例；剩余编程-擦除周期数量指的是闪存芯片由当前直至超过一定的错误率之间经历的编程-擦除周期数量。在本实施例中，错误比特数量、错误比特率以及剩余编程-擦除周期数量的数值区间均可以划分为两个或两个以上的子区间，每个子区间对应一个可靠性等级。
本实施例提供的闪存芯片可靠性等级预测方法，首先通过样本闪存芯片的特征量和样本闪存芯片的特征运算值，得到闪存可靠性等级的初始预测模型，该模型与单一的只以闪存芯片的特征量为输入的预测模型相比，可以有效的提高闪存可靠性等级预测模型的预测准确度。其次，本方法通过在待预测闪存芯片实际使用过程中利用待预测闪存芯片的特征量和样本闪存芯片的特征运算值对训练好的初始预测模型进行参数优化，进一步提升了闪存可靠性等级预测模型的预测准确度。最后，本方法通过将闪存芯片的实际可靠性等级与预测可靠性等级进行比较，能够持续性的对闪存可靠性预测模型进行优化，极大的提升了预测模型针对每一种闪存芯片的可靠性等级的预测准确度。
进一步的，下面结合一个具体的实例对上述实施例提出的方法进行具体描述，可以理解的是，下述所举实例只用于解释本发明，并非用于限定本发明的范围。
图3为本实施例建立和优化闪存可靠性等级预测模型的流程示意图。图4中所示基于闪存可靠性等级的闪存芯片测试流程适用于所有厂商所有类型的闪存芯片。图5和图6中所示基于决策树分类器的模型构建、优化流程适用于其他机器学习分类器上。下面以某厂商的TLC NAND Flash闪存产品(以下简称为“型号M闪存”)为例，介绍闪存芯片测试、模型建立、模型优化的步骤，并对图3中的各步骤进行详细的解释说明。
步骤一，采集样本闪存芯片的特征量并进行运算操作，构建样本闪存芯片的数据集合。这一步是为了构建闪存可靠性等级初始预测模型而进行的数据采集和处理。
本实施例中，选取样本闪存芯片按照以下规则进行抽取：样本闪存需要挑取相同工艺、类型、型号的不同批次的型号M闪存，以保证训练样本具有多样性，能更好地增强初始预测模型的泛化能力，减轻后续模型参数优化的负担。在本实施例中，挑取型号M闪存的不同批次的96个闪存块进行数据采集，样本闪存块的编号覆盖了闪存编号列表中的前中后区域。
本实施例中，对样本闪存芯片进行特征量采集的步骤如图4所示：
(1)将样本闪存芯片与闪存测试系统进行连接，设置型号M闪存的规格、测试信息以及测试图样。
(2)对样本闪存的样本闪存块进行块擦除操作，再对样本闪存块进行页编程操作，将测试图样写入样本闪存块中。
(3)更新编程/擦除周期数的值，该周期数以参数T pe表示，数值更新表达式为：T pe＝T pe+1。
(4)判断T pe的值。若T pe的值为50的倍数，则对样本闪存块进行页读取操作。将读取到的页数据与对应页的编程操作写入的测试图样进行数据对比，获取闪存错误信息并记录，然后转至步骤(5)。若T pe的值不是50的倍数，则直接转至步骤(2)。
(5)判断闪存错误信息中页原始错误比特率RBER是否超过ECC纠错算法上限值T。若超过，则停止测试，返回样本闪存块测试终止标志。若没有超过，则跳转至步骤(2)。
本实施例中，采集的样本闪存芯片特征量包括：闪存块的页原始错误比特数，闪存块当前已经历的编程-擦除周期数。
本实施例中，对样本闪存芯片特征量的运算操作包括：对闪存块内所有页的页原始错误比特数取算数平均数
Figure PCTCN2021083538-appb-000001
其中x i为第i页的页原始错误比特数，n为最大闪存页编号)、对闪存块内所有页的页原始错误比特数取平方平均数
Figure PCTCN2021083538-appb-000002
其中x i为第i页的页原始错误比特数，n为最大闪存页编号)，对闪存块内所有页的页原始错误比特数取中位数。
步骤二，调整决策树初始预测模型参数，将样本闪存芯片数据集合的子集作为模型输入，训练初始预测模型，并提取初始预测模型函数。
本实施例中，以决策树分类器为基础的初始预测模型的输入包括：页原始错误比特数算数平均数、页原始错误比特数平方平均数、页原始错误比特数中位数、闪存块当前已经历的编程-擦除周期数。
本实施例中，初始预测模型的预测目标为T m次P-E操作后的闪存可靠性等级，其中T m设置为100，可靠性等级分为五类，这五类分别代表闪存块总原始错误比特数的五个区间。
本实施例中，对决策树分类器初始预测模型进行训练的步骤如图5所示：
(1)从节点集合中选取适当的分裂节点，并对分裂节点的取值范围进行区域划分。
(2)根据划分的区域类别，计算该种划分方式下的回归方差
Figure PCTCN2021083538-appb-000003
集合I为某个区域类别代表的区间，x i为某一样本点对应的100次P-E操作后的可靠性等级，μ是区间内所有样本点的可靠性等级平均值)。
(3)若回归方差较大，未小于阈值，则重复步骤(1)和步骤(2)，调整区域划分层数以及分裂节点，直至回归方差小于阈值。
(4)回归方差小于阈值后，停止训练，保存并提取决策树分类器模型。
步骤三，采集待预测闪存芯片的特征量并进行运算操作，构建待预测闪存芯片的数据集合，记录闪存块此刻已经历的编程-擦除周期数为T renew。这一步是为了后续对初始预测模型参数优化进行数据采集工作。
本实施例中，待预测闪存芯片的特征量和运算操作，与步骤一相同。
步骤四，取待预测闪存芯片数据集合的子集，输入决策树分类器模型优化程序中，对已训练得到的初始预测模型中进行参数优化调整，并将参数优化后的预测模型取代原先已有的预测模型。
本实施例中，决策树分类器模型优化程序步骤如图6所示：
(1)初始化待预测闪存芯片数据集，生成属性列表和每个属性对应的类别数表(以下简称为CC表)。同时创建节点队列。
(2)若节点队列不为空，则取出节点队列中第一个节点P，在旧决策树模型中寻找P，后接步骤(3)。若节点队列为空，则后接步骤(7)。
(3)判断旧决策树模型中是否存在节点P。若旧决策树模型中存在节点P，则将节点P存放在旧决策树模型节点上，后接步骤(4)。若旧决策树模型中不存在节点P，后接步骤(5)。
(4)判断节点P对应的可靠性等级与旧决策树模型对应的可靠性等级是否相同。若相同，则直接后接步骤(6)。若不同，则更新属性列表和CC表，按新的属性列表和CC表重新划分节点P，然后重构节点P的子树，再后接步骤(6)。
(5)整合待预测闪存芯片训练集和样本闪存芯片训练集，重新生成CC表。后接步骤(6)
(6)将节点P从节点列表中删除，再跳转至步骤(2)。
(7)终止决策树分类器模型优化程序，保存优化后的决策树模型。
步骤五，后续在待预测闪存芯片正常地运行过程中，重复步骤三的操作，并将新的待预测闪存芯片数据集合的子集输入到更新后的可靠性等级预测模型中，获得预测的闪存芯片可靠性等级G predict，同时记录闪存块当前已经历的编程-擦除周期数T now，将二者构成组合(T now，G predict)并保存。
步骤六，当闪存块已经历的编程-擦除周期数为T now+T m时，判断G predict与当前待预测闪存块实际可靠性等级G real是否相同。若相同，则继续执行步骤七。若不相同，则跳转至步骤四，重新对旧决策树可靠性等级预测模型进行参数优化。
步骤七，当闪存块已经历的编程-擦除周期数为T renew+T r时(T r为预测无误情况下预测模型参数重新优化所需的P-E周期数，在本实施例中，T r为500)，跳转至步骤四，重新对旧决策树可靠性等级预测模型进行参数优化，以实现在闪存正常操作过程中，持续地进行预测模型参数优化和可靠性等级预测。
进一步的，作为图1至图6所示方法的具体实现，本实施例提供了一种闪存芯片可靠性等级预测装置，如图7所示，该装置包括：特征量采集模块31、数据集合构建模块32、模型参数调整模块33和预测结果输出模块模块34。
特征量采集模块31，可用于对待预测闪存芯片进行闪存操作，并在闪存操作过程中采集待预测闪存芯片的至少一种特征量；
数据集合构建模块32，可用于对待预测闪存芯片的至少一种特征量进行运算操作，得到待预测闪存芯片的特征运算值，依据待预测闪存芯片的特征量和待预测闪存芯片的特征运算值，建构待预测闪存芯片的数据集合；
模型参数调整模块33，可用于将待预测闪存芯片的数据集合中的第一子集输入到第一闪存可靠性等级预测模型的优化程序中，并对第一闪存可靠性等级预测模型进行参数调整，得到第二闪存可靠性等级预测模型；
预测结果输出模块34，可用于将待预测闪存芯片数据集合中的第二子集输入到第二闪存可靠性等级预测模型中，得到待预测闪存芯片的可靠性等级的第一预测结果。
在具体的应用场景中，所述特征量采集模块31，还可用于对待预测闪存芯片进行T m次编程-擦除操作，并采集T m次编程-擦除操作后待预测闪存芯片的实际可靠性等级；将T m次编程-擦除操作后待预测闪存芯片的实际可靠性等级与T m次编程-擦除操作后待预测闪存芯片的预测可靠性等级进行比较；若T m次编程-擦除操作后待预测闪存芯片的实际可靠性等级与T m次编程-擦除操作后待预测闪存芯片的预测可靠性等级不一致，则所述模型参数调整模块33，还可用于对第二闪存可靠性等级预测模型进行参数调整，得到第三闪存可靠性等级预测模型；所述第一预测结果输出模块34，还可用于将待预测闪存芯片数据集合中的第三子集输入到第三闪存可靠性等级预测模型中，得到待预测闪存芯片的可靠性等级的第二预测结果。
在具体的应用场景中，所述模型参数调整模块33，具体还可用于在待预测闪存芯片的T m次编程-擦除操作过程中，采集待预测闪存芯片的至少一种特征量；对待预测闪存芯片的至少一种特征量进行运算操作，得到待预测闪存芯片的特征运算值，将待预测闪存芯片的特征量和待预测闪存芯片的特征运算值存储在待预测闪存芯片的数据集合中；将待预测闪存芯片的数据集合中的第四子集输入到第二闪存可靠性等级预测模型的优化程序中，并对第二闪存可靠性等级预测模型进行参数调整，得到第三闪存可靠性等级预测模型。
在具体的应用场景中，编程-擦除操作周期数T m为单一预设定值或多个预设定值的组合，其中，当T m为多个预设定值的组合时，待预测闪存芯片的可靠性等级的第一预测结果包括多个与预设定值一一对应的T m次编程-擦除操作后待预测闪存芯片的预测可靠性等级。
在具体的应用场景中，如图8所示，本装置还包括预测模型训练模块35，所述预测模型训练模块35具体可用于从闪存产品集合中抽取出多个闪存芯片作为样本闪存芯片，并通过闪存测试系统采集样本闪存芯片的至少一种特征量；对样本闪存芯片的至少一种特征量进行运算操作，得到样本闪存芯片的特征运算值，依据样本闪存芯片的特征量和样本闪存芯片的特征运算值，建构样本闪存芯片的数据集合；将待预测闪存芯片的数据集合中的子集作为机器学习分类器的输入，对机器学习分类器进行训练，得到第一闪存可靠性等级预测模型。
在具体的应用场景中，闪存产品集合中包含同一制造工艺下相同类型且不同批次的多种闪存芯片；则从闪存产品集合中抽取出多个闪存芯片作为样本闪存芯片，包括：从闪存产品集合中随机抽取出预定数量的闪存芯片作为样本闪存芯片。
在具体的应用场景中，机器学习分类器包括支持向量机分类器、朴素贝叶斯分类器、k近邻分类器、决策树分类器、集成学习分类器和线性判别分类器中的一种或多种。
在具体的应用场景中，第一闪存可靠性等级预测模型的优化程序和第二闪存可靠性等级预测模型的优化程序与第一闪存可靠性等级预测模型训练所用的机器学习分类器相对应；其中，第一闪存可靠性等级预测模型的优化程序和第二闪存可靠性等级预测模型的优化程序包括支持向量机分类器模型优化程序、朴素贝叶斯分类器模型优化程序、k近邻分类器模型优化程序、决策树分类器模型优化程序、集成学习分类器模型优化程序、线性判别分类器模型优化程序中的一种或多种。
在具体的应用场景中，待预测闪存芯片的特征量和样本闪存芯片的特征量包括以下特征量中的一种或多种：闪存芯片各闪存操作的时间、各闪存操作时的电流、芯片功耗、阈值电压分布及电压变化量、闪存块编号、闪存页编号、当前编程-擦除周期数、闪存块中条件错误页数、条件错误块数、原始错误比特数和原始错误比特率。
在具体的应用场景中，待预测闪存芯片的特征量的运算操作方法和样本闪存芯片的特征量的运算操作方法包括以下运算操作方法中的一种或多种：特征量的线性运算、特征量的非线性运算、不同特征量间的线性运算、不同特征量间的非线性运算、计算不同存储页面特征量的最大值、计算不同存储页面特征量的最小值、不同存储页面特征量之间的线性运算、不同存储页面特征量之间的非线性运算、不同存储块特征量之间的线性运算、不同存储块特征量之间的非线性运算、计算不同存储块特征量的最大值和计算不同存储块特征量的最小值。
在具体的应用场景中，待预测闪存芯片的可靠性等级的第一预测结果和待预测闪存芯片的可靠性等级的第二预测结果包括以下结果中的一种或多种：待预测闪存芯片的当前错误比特数量等级、待预测闪存芯片的当前错误比特率等级、T m次编程-擦除操作后待预测闪存芯片的错误比特数量等级、T m次编程-擦除操作后待预测闪存芯片的错误比特率等级和待预测闪存芯片的剩余编程-擦除周期数量等级。
需要说明的是，本实施例提供的一种闪存芯片可靠性等级预测装置所涉及各功能单元的其它相应描述，可以参考图1至图6中的对应描述，在此不再赘述。
基于上述如图1至图6所示方法，相应的，本实施例还提供了一种存储介质，其上存储有计算机程序，该程序被处理器执行时实现上述如图1至图6所示的闪存芯片可靠性等级预测方法。
基于这样的理解，本申请的技术方案可以以软件产品的形式体现出来，该待识别软件产品可以存储在一个非易失性存储介质(可以是CD-ROM，U盘，移动硬盘等)中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本申请各个实施场景所述的方法。
基于上述如图1至图6所示的方法，以及图7和图8所示的闪存芯片可靠性等级预测装置实施例，为了实现上述目的，本实施例还提供了一种闪存芯片可靠性等级预测的实体设备，具体可以为个人计算机、服务器、智能手机、平板电脑、智能手表、或者其它网络设备等，该实体设备包括存储介质和处理器；存储介质，用于存储计算机程序；处理器，用于执行计算机程序以实现上述如图1至图6所示的方法。
可选的，该实体设备还可以包括用户接口、网络接口、摄像头、射频(Radio Frequency，RF)电路，传感器、音频电路、WI-FI模块等等。用户接口可以包括显示屏(Display)、输入单元比如键盘(Keyboard)等，可选用户接口还可以包括USB接口、读卡器接口等。网络接口可选的可以包括标准的有线接口、无线接口(如WI-FI接口)等。
本领域技术人员可以理解，本实施例提供的一种闪存芯片可靠性等级预测的实体设备结构并不构成对该实体设备的限定，可以包括更多或更少的部件，或者组合某些部件，或者不同的部件布置。
存储介质中还可以包括操作系统、网络通信模块。操作系统是管理上述实体设备硬件和待识别软件资源的程序，支持信息处理程序以及其它待识别软件和/或程序的运行。网络通信模块用于实现存储介质内部各组件之间的通信，以及与信息处理实体设备中其它硬件和软件之间通信。
通过以上的实施方式的描述，本领域的技术人员可以清楚地了解到本申请可以借助软件加必要的通用硬件平台的方式来实现，也可以通过硬件实现。通过应用本申请的技术方案，首先对待预测闪存芯片进行闪存操作，并在闪存操作过程中采集待预测闪存芯片的至少一种特征量，然后对待预测闪存芯片的至少一种特征量进行运算操作，得到待预测闪存芯片的特征运算值，依据待预测闪存芯片的特征量和待预测闪存芯片的特征运算值，建构待预测闪存芯片的数据集合，继而将待预测闪存芯片的数据集合中的第一子集输入到第一闪存可靠性等级预测模型的优化程序中，并对第一闪存可靠性等级预测模型进行参数调整，得到第二闪存可靠性等级预测模型，最后将待预测闪存芯片数据集合中的第二子集输入到第二闪存可靠性等级预测模型中，得到待预测闪存芯片的可靠性等级的第一预测结果。与现有技术相比，上述方法通过采集闪存芯片的至少一种特征量，并对采集到的至少一种特征量进行运算操作得到特征运算值，以及将闪存芯片的特征量和特征运算值作为闪存可靠性等级预测模型的共同输入，与仅以特征量为依据训练得到预测模型相比，本方法提出的闪存可靠性等级预测模型的预测准确度更高，此外，上述方法通过将待预测芯片的特征量和特征量的运算处理结果输入到初始预测模型的优化程序中，得到参数优化后的预测模型，能够差异化地针对每一个闪存芯片进行专一性模型参数优化，从而解决了因为闪存芯片之间差异导致的可靠性等级预测准确率下降的问题。因此，上述方法可以有效提高闪存芯片可靠性等级的预测准确度，从而有效地降低因为闪存芯片数据失效导致的数据安全隐患。
本领域技术人员可以理解附图只是一个优选实施场景的示意图，附图中的模块或流程并不一定是实施本申请所必须的。本领域技术人员可以理解实施场景中的装置中的模块可以按照实施场景描述进行分布于实施场景的装置中，也可以进行相应变化位于不同于本实施场景的一个或多个装置中。上述实施场景的模块可以合并为一个模块，也可以进一步拆分成多个子模块。
上述本申请序号仅仅为了描述，不代表实施场景的优劣。以上公开的仅为本申请的几个具体实施场景，但是，本申请并非局限于此，任何本领域的技术人员能思之的变化都应落入本申请的保护范围。

Claims (10)

  1. 一种闪存芯片可靠性等级预测方法，其特征在于，所述方法包括：
    对待预测闪存芯片进行闪存操作，并在闪存操作过程中采集所述待预测闪存芯片的至少一种特征量；
    对所述待预测闪存芯片的至少一种特征量进行运算操作，得到所述待预测闪存芯片的特征运算值，依据所述待预测闪存芯片的特征量和所述待预测闪存芯片的特征运算值，建构待预测闪存芯片的数据集合；
    将所述待预测闪存芯片的数据集合中的第一子集输入到第一闪存可靠性等级预测模型的优化程序中，并对所述第一闪存可靠性等级预测模型进行参数调整，得到第二闪存可靠性等级预测模型；
    将所述待预测闪存芯片数据集合中的第二子集输入到所述第二闪存可靠性等级预测模型中，得到所述待预测闪存芯片的可靠性等级的第一预测结果。
  2. 根据权利要求1所述的方法，其特征在于，所述待预测闪存芯片的可靠性等级的第一预测结果包括T m次编程-擦除操作后待预测闪存芯片的预测可靠性等级，其中，所述T m定义为编程-擦除操作周期数，则所述方法还包括：
    对所述待预测闪存芯片进行T m次编程-擦除操作，并采集T m次编程-擦除操作后待预测闪存芯片的实际可靠性等级；
    将所述T m次编程-擦除操作后待预测闪存芯片的实际可靠性等级与所述T m次编程-擦除操作后待预测闪存芯片的预测可靠性等级进行比较；
    若所述T m次编程-擦除操作后待预测闪存芯片的实际可靠性等级与所述T m次编程-擦除操作后待预测闪存芯片的预测可靠性等级不一致，则对所述第二闪存可靠性等级预测模型进行参数调整，得到第三闪存可靠性等级预测模型；
    将所述待预测闪存芯片数据集合中的第三子集输入到所述第三闪存可靠性等级预测模型中，得到所述待预测闪存芯片的可靠性等级的第二预测结果。
  3. 根据权利要求2所述的方法，其特征在于，所述对第二闪存可靠性等级预测模型进行参数调整，得到第三闪存可靠性等级预测模型，包括：
    在所述待预测闪存芯片的T m次编程-擦除操作过程中，采集所述待预测闪存芯片的至少一种特征量；
    对所述待预测闪存芯片的至少一种特征量进行运算操作，得到所述待预测闪存芯片的特征运算值，将所述待预测闪存芯片的特征量和所述待预测闪存芯片的特征运算值存储在所述待预测闪存芯片 的数据集合中；
    将所述待预测闪存芯片的数据集合中的第四子集输入到所述第二闪存可靠性等级预测模型的优化程序中，并对所述第二闪存可靠性等级预测模型进行参数调整，得到第三闪存可靠性等级预测模型。
  4. 根据权利要求2所述的方法，其特征在于，所述编程-擦除操作周期数T m为单一预设定值或多个预设定值的组合，其中，当所述T m为多个预设定值的组合时，所述待预测闪存芯片的可靠性等级的第一预测结果包括多个与所述预设定值一一对应的T m次编程-擦除操作后待预测闪存芯片的预测可靠性等级。
  5. 根据权利要求1所述的方法，其特征在于，所述第一闪存可靠性等级预测模型的训练方法，包括：
    从闪存产品集合中抽取出多个闪存芯片作为样本闪存芯片，并通过闪存测试系统采集所述样本闪存芯片的至少一种特征量；
    对所述样本闪存芯片的至少一种特征量进行运算操作，得到所述样本闪存芯片的特征运算值，依据所述样本闪存芯片的特征量和所述样本闪存芯片的特征运算值，建构样本闪存芯片的数据集合；
    将所述样本闪存芯片的数据集合中的子集作为机器学习分类器的输入，对所述机器学习分类器进行训练，得到第一闪存可靠性等级预测模型。
  6. 根据权利要求5所述的方法，其特征在于，所述闪存产品集合中包含同一制造工艺下相同类型且不同批次的多种闪存芯片；则所述从闪存产品集合中抽取出多个闪存芯片作为样本闪存芯片，包括：从所述闪存产品集合中随机抽取出预定数量的闪存芯片作为样本闪存芯片。
  7. 根据权利要求5所述的方法，其特征在于，所述机器学习分类器包括支持向量机分类器、朴素贝叶斯分类器、k近邻分类器、决策树分类器、集成学习分类器和线性判别分类器中的一种或多种。
  8. 一种闪存芯片可靠性等级预测装置，其特征在于，所述装置包括：
    特征量采集模块，用于对待预测闪存芯片进行闪存操作，并在闪存操作过程中采集所述待预测闪存芯片的至少一种特征量；
    数据集合构建模块，用于对所述待预测闪存芯片的至少一种特征量进行运算操作，得到所述待预测闪存芯片的特征运算值，依据所述待预测闪存芯片的特征量和所述待预测闪存芯片的特征运算值，建构待预测闪存芯片的数据集合；
    模型参数调整模块，用于将所述待预测闪存芯片的数据集合中的第一子集输入到第一闪存可靠性等级预测模型的优化程序中，并对所述第一闪存可靠性等级预测模型进行参数调整，得到第二闪存可靠性等级预测模型；
    预测结果输出模块，用于将所述待预测闪存芯片数据集合中的第二子集输入到所述第二闪存可 靠性等级预测模型中，得到所述待预测闪存芯片的可靠性等级的第一预测结果。
  9. 一种存储介质，其上存储有计算机程序，其特征在于，所述计算机程序被处理器执行时实现权利要求1至7中任一项所述的方法的步骤。
  10. 一种计算机设备，包括存储器、处理器及存储在存储器上并可在处理器上运行的计算机程序，其特征在于，所述计算机程序被处理器执行时实现权利要求1至7中任一项所述的方法的步骤。
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