WO2022153808A1 - Imaging device and electronic apparatus - Google Patents

Imaging device and electronic apparatus Download PDF

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Publication number
WO2022153808A1
WO2022153808A1 PCT/JP2021/047594 JP2021047594W WO2022153808A1 WO 2022153808 A1 WO2022153808 A1 WO 2022153808A1 JP 2021047594 W JP2021047594 W JP 2021047594W WO 2022153808 A1 WO2022153808 A1 WO 2022153808A1
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WIPO (PCT)
Prior art keywords
color filter
pixel region
color
pixel
pixels
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PCT/JP2021/047594
Other languages
French (fr)
Japanese (ja)
Inventor
健一郎 安城
Original Assignee
ソニーセミコンダクタソリューションズ株式会社
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Publication of WO2022153808A1 publication Critical patent/WO2022153808A1/en

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    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N23/00Cameras or camera modules comprising electronic image sensors; Control thereof
    • H04N23/10Cameras or camera modules comprising electronic image sensors; Control thereof for generating image signals from different wavelengths
    • H04N23/12Cameras or camera modules comprising electronic image sensors; Control thereof for generating image signals from different wavelengths with one sensor only
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70SSIS architectures; Circuits associated therewith
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70SSIS architectures; Circuits associated therewith
    • H04N25/76Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/77Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components

Definitions

  • the embodiments according to the present disclosure relate to an imaging device and an electronic device.
  • Time delay integration (TDI) sensors are used in fields such as FA (Factory Automation) and aerial photography.
  • This TDI sensor is a sensor that performs TDI processing that integrates the amount of electric charge while shifting the time according to the moving speed of the subject (see Patent Document 1).
  • the present disclosure provides an imaging device and an electronic device capable of suppressing deterioration of image quality due to vibration.
  • a photoelectric conversion unit provided for each of a plurality of pixels and outputting an electrical signal photoelectrically converted within a period corresponding to the moving speed of a relatively moving subject.
  • a calculation unit that integrates the electric signal for each color of the plurality of pixels is provided.
  • An imaging device is provided in which two pixels that photoelectrically convert light of different colors are arranged without gaps along the relative moving direction of the subject.
  • the third pixel region including one or more of the pixels that photoelectrically convert the light of the first color and the light of the third color different from the second color is without a gap along the relative moving direction of the subject. It may be arranged.
  • Each of the first pixel region, the second pixel region, and the third pixel region includes one or more of the pixels in the first direction, which is the relative movement direction of the subject, and in the first direction.
  • One or more of the pixels may be included in the intersecting second direction.
  • the first pixel region, the second pixel region, and the third pixel region are arranged without being mixed in the second direction.
  • the first pixel region and the second pixel region are arranged without gaps in the first direction.
  • the second pixel region and the third pixel region may be arranged without a gap in the first direction.
  • the first pixel region, the second pixel region, and the third pixel region are arranged in a mixed manner in the first direction and the second direction.
  • the first pixel region and the second pixel region are arranged without gaps in the first direction.
  • the second pixel region and the third pixel region may be arranged without a gap in the first direction.
  • the first pixel area, the second pixel area, and the third pixel area may be arranged in a bayer array.
  • the pixel has a color filter corresponding to the wavelength band of light to be photoelectrically converted.
  • the two color filters corresponding to different colors may be arranged without gaps along the relative moving direction of the subject.
  • the first pixel region comprises one or more of the pixels having a first color filter that transmits light of the first color.
  • the second pixel region comprises one or more of the pixels having a second color filter that transmits light of the second color.
  • the third pixel region comprises one or more of the pixels having a third color filter that transmits light of the third color.
  • the first color filter, the second color filter, and the third color filter may be arranged without gaps along the first direction, which is the relative movement direction of the subject.
  • the first color filter, the second color filter, and the third color filter are arranged without being mixed in the second direction intersecting the first direction.
  • the first color filter and the second color filter are arranged without gaps in the first direction.
  • the second color filter and the third color filter may be arranged without a gap in the first direction.
  • the first color filter, the second color filter, and the third color filter are arranged in a mixed manner in the first direction and the second direction intersecting the first direction.
  • the first color filter and the second color filter are arranged without gaps in the first direction.
  • the second color filter and the third color filter may be arranged without a gap in the first direction.
  • the first color filter, the second color filter, and the third color filter may be arranged in a bayer array.
  • An ADC Analog to Digital Converter
  • the calculation unit may integrate the digital signals for each color.
  • the first chip on which the photoelectric conversion unit is arranged and A second chip that is laminated with the first chip and on which the ADC is arranged may be further provided.
  • the ADC may be arranged at a position where it overlaps with the photoelectric conversion unit in the stacking direction.
  • the imaging device and A moving unit that moves the subject of the imaging device at a predetermined speed is provided.
  • the image pickup device A photoelectric conversion unit provided for each of a plurality of pixels and outputting an electrical signal photoelectrically converted within a period corresponding to the moving speed of a relatively moving subject.
  • a calculation unit that integrates the electric signal for each color of the plurality of pixels is provided.
  • An electronic device is provided in which two pixels that photoelectrically convert light of different colors are arranged without gaps along the relative moving direction of the subject.
  • pixel AD Analog to Digital
  • ADC Analog to Digital Converter
  • the imaging device and the electronic device will be described with reference to the drawings.
  • the main components of the image pickup device and the electronic device will be mainly described, but the image pickup device and the electronic device may have components and functions not shown or described.
  • the following description does not exclude components or functions not shown or described.
  • FIG. 1 is a block diagram showing a configuration example of an image pickup apparatus 100 according to a first embodiment of the present technology.
  • the image pickup device 100 is a device for capturing image data, and includes an optical unit 110, a solid-state image sensor 200, a storage unit 120, a control unit 130, and a communication unit 140.
  • the optical unit 110 collects the incident light and guides it to the solid-state image sensor 200.
  • the solid-state image sensor 200 captures image data.
  • the solid-state image sensor 200 supplies image data to the storage unit 120 via a signal line 209.
  • the storage unit 120 stores image data.
  • the control unit 130 controls the solid-state image sensor 200 to capture image data.
  • the control unit 130 supplies the solid-state image sensor 200 with a vertical synchronization signal VSYNC indicating the image pickup timing, for example, via the signal line 208.
  • the communication unit 140 reads the image data from the storage unit 120 and transmits it to the outside.
  • FIG. 2 is a diagram for explaining a usage example of the image pickup apparatus 100 in the first embodiment of the present technology. As illustrated in the figure, the image pickup apparatus 100 is used in a factory or the like where a belt conveyor 510 is provided.
  • FIG. 2 is also a diagram showing the electronic device 1 of the present technology.
  • the electronic device 1 includes an image pickup device 100 and a belt conveyor (moving unit) 510.
  • the electronic device 1 may include a housing (not shown) or the like for fixing the image pickup apparatus 100.
  • the belt conveyor 510 moves the subject 511 in a predetermined direction at a constant speed.
  • the image pickup apparatus 100 is fixed in the vicinity of the belt conveyor 510, and images the subject 511 to generate image data.
  • the image data is used, for example, for inspection of the presence or absence of defects. As a result, FA is realized.
  • the image pickup apparatus 100 captures a subject 511 moving at a constant speed, but the present invention is not limited to this configuration.
  • the image pickup device 100 may move at a constant speed to take an image of the subject, such as in aerial photography.
  • FIG. 3 is a diagram showing an example of a laminated structure of the solid-state image sensor 200 according to the first embodiment of the present technology.
  • the solid-state image sensor 200 includes a circuit chip (second chip) 202 and a light receiving chip (first chip) 201 laminated on the circuit chip 202. These chips are electrically connected via a connection such as a via. In addition to vias, it can also be connected by Cu-Cu bonding or bumps.
  • FIG. 4 is a block diagram showing a configuration example of the light receiving chip 201 according to the first embodiment of the present technology.
  • the light receiving chip 201 is provided with a pixel array unit 210 and a peripheral circuit 212.
  • a plurality of pixel circuits 220 are arranged in a two-dimensional grid pattern in the pixel array unit 210. Further, the pixel array unit 210 is divided into a plurality of pixel blocks 211. In each of these pixel blocks 211, for example, a pixel circuit 220 having 4 rows ⁇ 2 columns is arranged. Further, for each pixel circuit 220, a plurality of transistors are further arranged outside the pixel circuit 220, but these transistors are omitted in the figure for convenience of description.
  • a circuit that supplies a DC (Direct Current) voltage is arranged in the peripheral circuit 212.
  • FIG. 5 is a block diagram showing a configuration example of the circuit chip 202 according to the first embodiment of the present technology.
  • a DAC Digital to Analog Converter
  • a pixel drive circuit 252 a time code generation unit 253, a pixel AD conversion unit 254, and a vertical scanning circuit 255 are arranged on the circuit chip 202.
  • a control circuit 256, a signal processing circuit 400, an image processing circuit 260, and an output circuit 257 are arranged on the circuit chip 202.
  • the DAC 251 generates a reference signal by DA (Digital to Analog) conversion within a predetermined AD conversion period. For example, a saw blade-shaped lamp signal is used as a reference signal.
  • the DAC 251 supplies the reference signal to the pixel AD conversion unit 254.
  • the time code generation unit 253 generates a time code indicating the time within the AD conversion period.
  • the time code generation unit 253 is realized by, for example, a counter. As the counter, for example, a Gray code counter is used.
  • the time code generation unit 253 supplies the time code to the pixel AD conversion unit 254.
  • the pixel drive circuit 252 drives each of the pixel circuits 220 to generate an analog pixel signal.
  • the pixel AD conversion unit 254 performs AD conversion that converts each analog signal (that is, a pixel signal) of the pixel circuit 220 into a digital signal.
  • the pixel AD conversion unit 254 is divided by a plurality of clusters 300.
  • the cluster 300 is provided for each pixel block 211 and converts the analog signal in the corresponding pixel block 211 into a digital signal.
  • the pixel AD conversion unit 254 generates image data in which digital signals are arranged by AD conversion as a frame and supplies the image data to the signal processing circuit 400.
  • the vertical scanning circuit 255 drives the pixel AD conversion unit 254 to execute AD conversion.
  • the signal processing circuit 400 performs predetermined signal processing on the frame. As signal processing, various processes including CDS (Correlated Double Sampling) processing and TDI processing are executed. The signal processing circuit 400 supplies the processed frame to the image processing circuit 260.
  • CDS Correlated Double Sampling
  • TDI Time Division Multiplexing
  • the image processing circuit 260 executes predetermined image processing on the frame from the signal processing circuit 400. As image processing, image recognition processing, black level correction processing, image correction processing, demosaic processing, and the like are executed. The image processing circuit 260 supplies the processed frame to the output circuit 257.
  • the output circuit 257 outputs the frame after image processing to the outside.
  • the control circuit 256 controls the operation timings of the DAC 251, the pixel drive circuit 252, the vertical scanning circuit 255, the signal processing circuit 400, the image processing circuit 260, and the output circuit 257 in synchronization with the vertical synchronization signal VSYNC.
  • FIG. 6 is a diagram showing a configuration example of the pixel AD conversion unit 254 according to the first embodiment of the present technology.
  • a plurality of ADCs 310 are arranged in a two-dimensional grid pattern in the pixel AD conversion unit 254.
  • the ADC 310 is arranged for each pixel circuit 220.
  • N is an integer
  • M is an integer
  • each of the clusters 300 the same number of ADC 310s as the number of pixel circuits 220 in the pixel block 211 are arranged.
  • the ADC 310 having 4 rows ⁇ 2 columns is also arranged in the cluster 300.
  • the ADC 310 performs AD conversion on an analog pixel signal generated by the corresponding pixel circuit 220.
  • the ADC 310 compares the pixel signal and the reference signal in the AD conversion, and holds the time code when the comparison result is inverted. Then, the ADC 310 outputs the held time code as a digital signal after AD conversion.
  • a repeater unit 360 is arranged for each row of the cluster 300.
  • M / 2 repeater units 360 are arranged.
  • the repeater unit 360 transfers the time code.
  • the repeater unit 360 transfers the time code from the time code generation unit 253 to the ADC 310.
  • the repeater unit 360 transfers a digital signal from the ADC 310 to the signal processing circuit 400. This transfer of digital signals is also referred to as "reading" the digital signals.
  • the numbers in parentheses indicate an example of the reading order of the digital signals of the ADC 310.
  • the odd-numbered column digital signal in the first row is read first, and the even-numbered column digital signal in the first row is read second.
  • the odd-numbered column digital signal in the second row is read out third, and the even-numbered column digital signal in the second row is read out third.
  • the odd-numbered columns and even-numbered columns of the digital signals in each row are read out in order.
  • ADC 310 is arranged for each pixel circuit 220, the configuration is not limited to this.
  • a plurality of pixel circuits 220 may be configured to share one ADC 310.
  • FIG. 7 is a block diagram showing a configuration example of the ADC 310 according to the first embodiment of the present technology.
  • the ADC 310 includes a differential input circuit 320, a positive feedback circuit 330, a latch control circuit 340, and a plurality of latch circuits 350.
  • an amplifier circuit 230 is arranged between the pixel circuit 220 and the ADC 310.
  • the amplifier circuit 230 amplifies the pixel signal from the pixel circuit 220 and supplies it to the ADC 310.
  • the circuit including the pixel circuit 220 and the amplifier circuit 230 functions as one pixel.
  • the pixel circuit 220, the amplifier circuit 230, and a part of the differential input circuit 320 are arranged on the light receiving chip 201, and the rest of the differential input circuit 320 and the circuit in the subsequent stage are arranged on the circuit chip 202. To.
  • the differential input circuit (comparator) 320 compares the pixel signal from the amplifier circuit 230 with the reference signal from the DAC 251.
  • the differential input circuit 320 supplies a comparison result signal indicating the comparison result to the positive feedback circuit 330.
  • the positive feedback circuit 330 adds a part of the output to the input (comparison result signal) and supplies it to the latch control circuit 340 as an output signal VCO.
  • the latch control circuit 340 causes a plurality of latch circuits 350 to hold the time code when the output signal VCO is inverted according to the control signal xWORD from the vertical scanning circuit 255.
  • the latch circuit 350 holds the time code from the repeater unit 360 according to the control of the latch control circuit 340.
  • the latch circuit 350 is provided for the number of bits of the time code. For example, when the time code is 15 bits, 15 latch circuits 350 are arranged in the ADC 310. Further, the held time code is read out by the repeater unit 360 as a digital signal after AD conversion.
  • the ADC 310 converts the pixel signal from the amplifier circuit 230 into a digital signal.
  • FIG. 8 is a circuit diagram showing a configuration example of a pixel circuit 220, a differential input circuit 320, and a positive feedback circuit 330 according to the first embodiment of the present technology.
  • the differential input circuit 320 includes pMOS (p-channel Metal Oxide Semiconductor) transistors 321, 324 and 326. Further, the differential input circuit 320 includes nMOS (n-channel MOS) transistors 322, 323, 325, 327 and 328. Of these, the nMOS transistors 322, 323, 325 and 328 are arranged on the light receiving chip 201, and the rest are arranged on the circuit chip 202.
  • pMOS p-channel Metal Oxide Semiconductor
  • nMOS n-channel MOS
  • the nMOS transistors 322 and 325 form a differential pair, and the source of these transistors is commonly connected to the drain of the nMOS transistor 323. Further, the drain of the nMOS transistor 322 is connected to the drain of the pMOS transistor 321 and the gate of the pMOS transistors 321 and 324. The drain of the nMOS transistor 325 is connected to the drain of the pMOS transistor 324 and the gate of the pMOS transistor 326. Further, a reference signal REF from the DAC 251 is input to the gate of the nMOS transistor 322.
  • a predetermined bias voltage Vb is applied to the gate of the nMOS transistor 323, and a predetermined ground voltage is applied to the source of the nMOS transistor 323.
  • the pixel signal SIG from the amplifier circuit 230 is input to the gate of the nMOS transistor 325.
  • the pMOS transistors 321, 324 and 326 form a current mirror circuit.
  • a power supply voltage VDDH is applied to the sources of the pMOS transistors 321, 324 and 326. This power supply voltage VDDH is higher than the power supply voltage VDDL described later.
  • a power supply voltage VDDL is applied to the gate of the nMOS transistor 327. Further, the drain of the nMOS transistor 327 is connected to the drain of the pMOS transistor 326, and the source is connected to the positive feedback circuit 330.
  • the nMOS transistor 328 short-circuits the gate and drain of the nMOS transistor 325 according to the auto zero signal AZ from the pixel drive circuit 252.
  • the positive feedback circuit 330 includes pMOS transistors 331, 332, 334 and 335, and nMOS transistors 333, 336 and 337.
  • the pMOS transistors 331 and 332 and the nMOS transistor 333 are connected in series with the power supply voltage VDDL. Further, a drive signal INI2 from the vertical scanning circuit 255 is input to the gate of the pMOS transistor 331.
  • the connection points of the pMOS transistor 332 and the nMOS transistor 333 are connected to the source of the nMOS transistor 327.
  • a ground voltage is applied to the source of the nMOS transistor 333, and a drive signal INI1 from the vertical scanning circuit 255 is input to the gate.
  • the pMOS transistors 334 and 335 are connected in series with the power supply voltage VDDL. Further, the drain of the pMOS transistor 335 is connected to the gate of the pMOS transistor 332 and the drain of the nMOS transistors 336 and 337.
  • the control signal TESTVCO from the vertical scanning circuit 255 is input to the gates of the pMOS transistor 335 and the nMOS transistor 337. Further, the gates of the pMOS transistor 334 and the nMOS transistor 336 are connected to the connection points of the pMOS transistor 332 and the nMOS transistor 333.
  • the output signal VCO is output from the connection point of the pMOS transistor 335 and the nMOS transistor 337. Further, a ground voltage is applied to the sources of the nMOS transistors 336 and 337.
  • each of the differential input circuit 320 and the positive feedback circuit 330 is not limited to the circuit illustrated in FIG. 8 as long as it has the functions described in FIG. 7.
  • FIG. 9 is a circuit diagram showing a configuration example of the pixel circuit 220 and the amplifier circuit 230 according to the first embodiment of the present technology.
  • the pixel circuit 220 includes an emission transistor 221, a photoelectric conversion element 222, a transfer transistor 223, a reset transistor 224, a capacitance 225, a gain control transistor 226, and a floating diffusion layer 227.
  • an nMOS transistor is used as the emission transistor 221, the transfer transistor 223, the reset transistor 224, and the gain control transistor 226.
  • the discharge transistor 221 discharges the electric charge accumulated in the photoelectric conversion element 222 according to the drive signal OFG from the pixel drive circuit 252.
  • the photoelectric conversion element 222 generates an electric charge by photoelectric conversion.
  • the transfer transistor 223 transfers an electric charge from the photoelectric conversion element 222 to the floating diffusion layer 227 according to the transfer signal TG from the pixel drive circuit 252.
  • the reset transistor 224 initializes the floating diffusion layer 227 according to the reset signal RST from the pixel drive circuit 252.
  • the capacitance 225 is inserted between the connection node of the reset transistor 224 and the gain control transistor 226 and the ground terminal.
  • the gain control transistor 226 controls the analog gain with respect to the voltage of the floating diffusion layer 227 according to the control signal FDG from the pixel drive circuit 252. By reducing the voltage of the floating diffusion layer 227 by analog gain and outputting it, the amount of signals handled by the pixel circuit 220, that is, the amount of saturation signals can be increased.
  • the floating diffusion layer 227 accumulates the transferred electric charge and generates a voltage according to the amount of electric charge.
  • the amplifier circuit 230 includes nMOS transistors 231 and 232 and a capacitance 233.
  • the nMOS transistors 231 and 232 are connected in series between the power supply and the ground terminal.
  • the gate of the nMOS transistor 231 on the power supply side is connected to the floating diffusion layer 227.
  • a predetermined bias voltage VB2 is applied to the gate of the nMOS transistor 232 on the ground side.
  • connection nodes of the nMOS transistors 231 and 232 are connected to the differential input circuit 320 via the capacitance 233.
  • the capacitance value of the capacitance 233 is considerably larger than the gate-source capacitance Cgs. Set. If the floating diffusion layer 227 and the gate of the nMOS transistor 325 are directly connected, the fluctuation of the floating diffusion layer 227 becomes large due to the coupling between the gate-source capacitance Cgs and the floating diffusion layer 227, and the AD conversion period becomes longer. It may take a long time. However, the effect of this coupling can be mitigated by adding capacity 233.
  • each of the pixel circuit 220 and the amplifier circuit 230 is not limited to the circuit illustrated in FIG. 9 as long as it has the functions described in FIG. 7.
  • FIG. 10 is a plan view showing an example of the layout of the elements in the pixels according to the first embodiment of the present technology.
  • the optical axis of the incident light is the Z axis
  • the predetermined axis perpendicular to the Z axis is the X axis
  • the Z axis and the axis perpendicular to the X axis are the Y axes.
  • a plurality of photoelectric conversion elements 222 in rows N and columns M are arranged in a two-dimensional lattice pattern.
  • the size of these photoelectric conversion elements 222 in the Y-axis direction is defined as Y1.
  • the M photoelectric conversion elements 222 are arranged adjacent to each other along the X-axis direction without any gap.
  • the set of M photoelectric conversion elements 222 arranged in the X-axis direction and the set of digital signals corresponding to them are hereinafter referred to as "lines”.
  • the N photoelectric conversion elements 222 are arranged with an interval of Y2.
  • the N lines are arranged at intervals of Y2.
  • the interval Y2 is the same value as the size Y1. As illustrated in Equation 1, the interval Y2 can be made larger than the size Y1. When the interval Y2 is larger than the size Y1, the interval Y2 is set to an integral multiple of Y1. As the interval Y2 is increased, the size of the lower ADC 310 in the Y-axis direction can be increased. Therefore, the size of the ADC 310 in the X-axis direction can be reduced accordingly to miniaturize the pixels in the X-axis direction. can.
  • a transistor arrangement region 241 is provided in the gap region 240 between each of the N photoelectric conversion elements 222.
  • a predetermined number of transistors, a floating diffusion layer 227, and capacitances 233 and 225 are arranged in the transistor arrangement region 241.
  • a predetermined number of transistors include discharge transistors 221 and reset transistors 224 and gain control transistors 226, and nMOS transistors 231, 232, 322, 323 and 325.
  • the transistor in the differential input circuit 320 illustrated in FIG. 8 and the transistor in the pixel circuit 220 and the amplifier circuit 230 illustrated in FIG. 9 are arranged. As described with reference to FIG.
  • these transistors generate a signal (pixel signal or a signal obtained by amplifying the pixel signal) according to the amount of electric charge generated by any one of the plurality of photoelectric conversion elements 222. do. Further, a transfer transistor 223 is arranged between the transistor arrangement region 241 and the photoelectric conversion element 222.
  • the N-row and M-column photoelectric conversion elements 222 are arranged without gaps along the X-axis direction and the Y-axis direction, and various transistors such as the discharge transistor 221 and the stray diffusion layer 227 are arranged in the photoelectric conversion element 222.
  • various transistors such as the discharge transistor 221 and the stray diffusion layer 227 are arranged in the photoelectric conversion element 222.
  • transistors and the like can be arranged in the gap area 240.
  • the light receiving area can be made wider than that of the comparative example. By expanding the light receiving area, the sensitivity of the pixel can be improved. Further, since more transistors can be arranged than in the comparative example, additional circuits such as an amplifier circuit 230 can be further arranged in addition to the pixel circuit 220.
  • one pixel P includes a photoelectric conversion element 222 and a gap region 240.
  • FIG. 11 is a block diagram showing a configuration example of the signal processing circuit 400 according to the first embodiment of the present technology.
  • the signal processing circuit 400 includes a plurality of selectors 405, a plurality of arithmetic circuits 410, a CDS frame memory 440, and a TDI frame memory 450.
  • the selector 405 is arranged for each column of the cluster 300, in other words, for each repeater unit 360. When two rows of ADC 310s are arranged in the cluster 300, a selector 405 is arranged in every two rows. Further, the arithmetic circuit 410 is arranged for each row of the ADC 310. When the ADC 310 has M columns, M / 2 selectors 405 and M arithmetic circuits 410 are arranged.
  • the repeater unit 360 outputs an odd-numbered row of digital signals and an even-numbered row of digital signals in order.
  • the selector 405 selects the output destination of the digital signal according to the control of the control circuit 256.
  • the selector 405 When an odd-numbered sequence is output by the repeater unit 360, the selector 405 outputs a digital signal to the arithmetic circuit 410 corresponding to the odd-numbered sequence.
  • the selector 405 When an even-numbered sequence is output, the selector 405 outputs a digital signal to the arithmetic circuit 410 corresponding to the even-numbered sequence.
  • the arithmetic circuit 410 performs CDS processing and TDI processing on the digital signal from the selector 405.
  • the digital signal includes a P-phase level and a D-phase level.
  • the P-phase level indicates the level when the pixel circuit 220 is initialized by the reset signal RST.
  • the D-phase level indicates a level according to the exposure amount when the electric charge is transferred by the transfer signal TG.
  • the P-phase level is also called the reset level, and the D-phase level is also called the signal level.
  • the M arithmetic circuits 410 hold the P-phase frames in which the P-phase levels are arranged in the CDS frame memory 440. Then, the M arithmetic circuits 410 obtain the difference between the P-phase level and the D-phase level for each pixel, and generate a CDS frame in which the difference data is arranged.
  • the M arithmetic circuits 410 hold the frames after the CDS processing in the TDI frame memory 450, and update the TDI frame memory 450 with the integrated data.
  • the M arithmetic circuits 410 supply the CDS frame and the TDI frame after the TDI processing to the image processing circuit 260.
  • FIG. 12 is a circuit diagram showing a configuration example of the arithmetic circuit 410 according to the first embodiment of the present technology.
  • the arithmetic circuit 410 includes a TDI circuit 420 and a CDS circuit 430.
  • the TDI circuit 420 includes a buffer 421, a selector 422, an adder 423, and a switch 424.
  • the CDS circuit 430 includes a selector 431, a buffer 432, a selector 433, a subtractor 434 and a switch 435.
  • the operation of the selectors 422, 431 and 433 and the switches 424 and 425, respectively, is controlled by, for example, the control circuit 256.
  • the selector 431 selects either a digital signal from the selector 405 or a digital signal from the TDI frame memory 450 and outputs it to the buffer 421.
  • the buffer 421 delays and outputs the signal from the selector 431.
  • the selector 422 selects either a digital signal from the buffer 421 or a digital signal having a decimal value of "0" and outputs it to the adder 423.
  • the adder 423 adds the digital signal from the selector 422 and the digital signal from the buffer 432.
  • the adder 423 supplies a digital signal indicating the added value to the switch 424 as integrated data.
  • the switch 424 opens and closes the path between the adder 423 and the TDI frame memory 450.
  • the buffer 432 delays and outputs the signal from the CDS frame memory 440.
  • the selector 433 selects either a digital signal from the buffer 432 or a digital signal having a decimal value of "0" and outputs it to the subtractor 434.
  • the subtractor 434 calculates the difference between the digital signal from the buffer 421 and the digital signal from the selector 433.
  • the subtractor 434 supplies a digital signal indicating the difference to the switch 435 as the difference data.
  • the switch 435 opens and closes the path between the subtractor 434 and the CDS frame memory 440.
  • the CDS circuit 430 can perform CDS processing. Further, the TDI circuit 420 can perform TDI processing.
  • FIG. 13 is a diagram showing an example of TDI processing in the first embodiment of the present technology.
  • the CDS frame memory 440 and the TDI frame memory 450 are initialized, the frame F1 is first imaged, and then the frames F2, F3, F4, F5, F6, F7 and F8 are imaged in order.
  • frames F5 and later are omitted.
  • the arrows in the figure indicate the moving direction of the subject.
  • the subject moves one line at a time in the direction in which the row address increases along the Y-axis direction.
  • the gray part between the lines in the figure shows the gap area between the lines.
  • the gap area is for one line.
  • the signal processing circuit 400 integrates the line L1 of the frame F1 after the CDS processing, the line L2 of the frame F3, the line L3 of the frame F5, and the line L4 of the frame F7. As described above, since the subject moves one line at a time and the gap area is one line, the pattern of each line to be integrated is the same.
  • the signal processing circuit 400 outputs the integrated line as the last line of the TDI frame.
  • the signal processing circuit 400 integrates the line L1 of the frame F2 after the CDS processing, the line L2 of the frame F4, the line L3 of the frame F6, and the line L4 of the frame F8.
  • the signal processing circuit 400 outputs the integrated line as the penultimate line of the TDI frame.
  • the other lines are generated by integrating the four lines after the frame F3.
  • the moving speed of the subject is fast, it is necessary to shorten the exposure time in order to prevent blurring. If the exposure time is shortened, the image may become dark, but by performing the TDI process, it is possible to integrate a plurality of lines of the same pattern to improve the brightness. Further, as the number of integrated lines increases, noise is reduced due to the smoothing effect. By improving the brightness and reducing the noise, the image quality of the frame (that is, the image data) can be improved as compared with the case where the TDI processing is not performed.
  • the signal processing circuit 400 integrates four lines, but the number of integrated lines is not limited to four as long as it is two or more. Further, the signal processing circuit 400 integrates four lines from the first line for the first eight frames, but the present invention is not limited to this configuration. For example, when the moving direction of the subject is opposite, the signal processing circuit 400 may integrate 4 lines from the last line for the first 8 frames.
  • lines of the same pattern are integrated by setting every other frame to be integrated, such as frames F1, F3, F5 and F7. be able to.
  • the gap area between the lines is set to 2 lines or 3 lines
  • the frames to be integrated may be set to every 2 or 3 frames.
  • FIG. 14 is an example of a flowchart showing an example of the operation of the solid-state image sensor 200 according to the first embodiment of the present technology. This operation is started, for example, when a predetermined application for imaging a frame is executed.
  • the pixel drive circuit 252 in the solid-state image sensor 200 drives all the pixels and starts exposure at the same time (step S901). Such control of exposing all pixels at the same time is called a global shutter method.
  • the ADC 310 AD-converts the P-phase level (step S902). Then, at the end of the exposure, the ADC 310 AD-converts the D-phase level, and the arithmetic circuit 410 performs the CDS process (step S903).
  • the image processing circuit 260 performs predetermined image processing on the frame after the CDS processing (step S904), and the arithmetic circuit 410 performs TDI processing (step S905).
  • the image processing circuit 260 performs predetermined image processing on the frame after the TDI processing (step S906), and the output circuit 257 outputs the processing result (step S907).
  • the solid-state image sensor 200 ends the process of imaging one frame. When two or more frames are continuously imaged, steps S901 to S907 are repeatedly executed in synchronization with the vertical synchronization signal VSYNC.
  • a plurality of photoelectric conversion elements 222 are arranged at regular intervals along the Y-axis direction, and transistors are arranged between them.
  • the light receiving area of the photoelectric conversion element 222 can be made wider than that in the case where the light receiving area is not opened. Thereby, the sensitivity of the pixel can be improved.
  • FIG. 15 is a diagram showing an example of the configuration of the image pickup apparatus 100 according to the first embodiment of the present technology.
  • the image pickup apparatus 100 shown in FIG. 15 is a TDI color sensor having a color filter. Further, the image pickup apparatus 100 is, for example, a TDI linear image sensor. The color filter passes light in a wavelength band corresponding to a predetermined color. The data of TDI processing is added for each color.
  • the pixel P shown in FIG. 15 corresponds to the pixel P shown in FIG.
  • the pixel P includes a pixel PR arranged in the red filter (R), a pixel PG arranged in the green filter (G), and a pixel PB arranged in the blue filter (B).
  • the color pattern is a color group array.
  • the color filter includes, for example, a red filter group, a green filter group, and a blue filter group in which a plurality of red filters, green filters, and blue filters are arranged adjacent to each other.
  • pixels P of the same color are arranged in the X direction and the Y direction, respectively.
  • the number of pixels P arranged is not limited to this.
  • the image pickup apparatus 100 is a linear sensor, for example, pixels P such as 1000 or 2000 are arranged side by side in the X direction. Further, for example, 16 pixels P per color are arranged side by side in the Y direction.
  • One pixel P includes a photoelectric conversion element 222.
  • the photoelectric conversion element 222 is provided in each of the plurality of pixels P, and outputs an electrical signal photoelectrically converted within a period corresponding to the moving speed of the relatively moving subject 511.
  • the "relative movement direction" is not limited to the case described with reference to FIG. 2, and includes the case where the subject 511 is fixed and the image pickup apparatus 100 is moved.
  • the ADC 310 is arranged for each of the plurality of pixels P and converts an electric signal into a digital signal.
  • the arithmetic circuit (calculation unit) 410 arranged outside the pixel area integrates electric signals for each color of a plurality of pixels P. More specifically, the arithmetic circuit 410 integrates the digital signals converted by the ADC 310 for each color. Therefore, as shown in FIG. 5, the arithmetic circuit 410 in the signal processing circuit 400 integrates the digital signals output from the ADC 310 in the pixel AD conversion unit 254 for each color.
  • the image pickup apparatus 100 has a laminated structure as described with reference to FIG.
  • the ADC 310 is arranged at a position where it overlaps with the photoelectric conversion element 222 in the stacking direction. More specifically, the differential input circuit 320 and the latch circuit 350 are arranged directly below the photoelectric conversion element 222.
  • the differential input circuit 320 receives a slope signal from the DAC 251 arranged outside the pixel area. As a result, the ADC 310 performs the single slope AD conversion.
  • the digital value is held in the latch circuit 350 and transferred every H to a logic circuit such as the signal processing circuit 400.
  • the two pixels P that photoelectrically convert light of different colors are arranged without a gap along the relative moving direction (Y direction) of the subject 511.
  • the pixel PR and the pixel PG that are adjacent to each other along the Y direction are arranged so as to be in contact with each other without a gap.
  • the pixel PG and the pixel PB that are adjacent to each other along the Y direction are arranged so as to be in contact with each other without a gap.
  • deterioration of image quality due to vibration can be suppressed. That is, the vibration resistance of the image pickup apparatus 100 and the electronic device 1 can be improved. The details of the vibration resistance will be described later with reference to FIGS. 16A to 19.
  • a first pixel region including one or more pixels P that photoelectrically convert light of the first color and one or more pixels P that photoelectrically convert light of a second color different from the first color are formed.
  • the relative movement direction (Y) of the subject 511 is the second pixel region including the second pixel region and the third pixel region including one or more pixels P that photoelectrically convert the light of the first color and the third color different from the second color. It is arranged without a gap along the direction).
  • the first color, the second color, and the third color are, for example, red, green, and blue, respectively, but the type and order of the colors are not limited to this.
  • the first pixel area, the second pixel area, and the third pixel area are, for example, areas in which one or more red pixel PRs, one or more green pixel PGs, and one or more blue pixel PBs are arranged, respectively. , The type and order of colors are not limited to this.
  • Each of the first pixel region, the second pixel region, and the third pixel region includes one or more pixels P in the first direction (Y direction), which is the relative movement direction of the subject 511, and is in the first direction.
  • One or more pixels P are included in the intersecting second direction (X direction).
  • Pixels P of each color are arranged according to a color group array. That is, the first pixel region, the second pixel region, and the third pixel region are arranged without being mixed in the X direction. The first pixel area and the second pixel area are arranged without a gap in the Y direction. The second pixel area and the third pixel area are arranged without a gap in the Y direction.
  • Pixel P has a color filter corresponding to the wavelength band of light to be photoelectrically converted.
  • the two color filters corresponding to different colors are arranged without gaps along the relative moving direction of the subject 511.
  • the first pixel region has one or more pixels P having a first color filter that transmits light of the first color.
  • the second pixel region has one or more pixels P having a second color filter that transmits light of the second color.
  • the third pixel region has one or more pixels P having a third color filter that transmits light of the third color.
  • the first color filter, the second color filter, and the third color filter are arranged without gaps along the Y direction, which is the relative movement direction of the subject 511.
  • first color filter, the second color filter, and the third color filter are arranged without being mixed in the X direction intersecting the Y direction.
  • the first color filter and the second color filter are arranged without a gap in the Y direction.
  • the second color filter and the third color filter are arranged without a gap in the Y direction.
  • FIG. 16A is a diagram illustrating the effect of vibration when the color gap is large.
  • FIG. 16B is a diagram illustrating the effect of vibration when the color gap is small.
  • FIG. 16A shows an example assuming that a subject is scanned and synthesized at different times using a linear sensor for single colors of red, green, and blue.
  • the vibration V at the left and right reading positions (positions in the X direction) of the image has almost no correlation between the red, green, and blue colors. Therefore, in the composite image, color shift occurs according to the difference in vibration V for each color.
  • FIG. 16B shows an example in which it is assumed that the positions in the scanning direction (positions in the Y direction) are almost the same between the colors using the linear sensors for red, green, and blue monochromatic colors.
  • the vibration V at the left and right reading positions of the image is almost the same for each color. That is, the correlation of vibration V for each color is strong. Therefore, there is almost no color shift in the composite image.
  • the intercolor gap of the pixel P in TDI can be considered in the same manner as in FIGS. 16A and 16B. That is, the smaller the intercolor gap of the pixel P, the stronger the correlation between the vibration Vs at the left and right reading positions. As a result, the color shift of the composite image is reduced. As a result, deterioration of image quality due to vibration can be suppressed.
  • FIG. 17 is a diagram illustrating the intercolor gap GC.
  • FIG. 17 shows a pixel PR for red and a pixel PG for green as an example.
  • the intercolor gap GC is a value obtained by subtracting the same color pixel distance DP from the CF end distance DCF, which is the distance between the color filter (CF) end of the red filter and the CF end of the green filter.
  • the same-color pixel distance DP is the product of the pixel pitch and the number of same-color TDI stages.
  • the pixel pitch indicates the distance of one pixel P in the Y direction.
  • the number of TDI stages of the same color is the number of stages of the pixels P of the same color arranged side by side in the Y direction, and is 4 in the example shown in FIG.
  • FIG. 18 is a diagram for explaining the relationship between the intercolor gap GC and vibration.
  • the read interval of the TDI pixel is 1 ⁇ s
  • the read interval between the colors of the first red pixel and the first green pixel is 10 ⁇ s.
  • the high-frequency vibration noise NH and the low-frequency vibration noise NL shown in FIG. 18 are models that follow 1 / f. That is, as shown in FIG. 18, the vibration noise NL having a large amplitude has a low frequency, and the vibration noise NH having a small amplitude has a high frequency. Vibration noise is defined as a simple difference of lateral (X direction) vibration received between colors. Moreover, since the TDI pixel can be regarded as the act of averaging the TDI pixel, the transfer function can be calculated by the Laplace transform and the reaction to the noise spectrum can be quantified.
  • FIG. 19 is a graph showing the transfer function.
  • the vibration noise spectrum NS generally shows a vibration spectrum in which the amplitude is large when the frequency is low and the amplitude is small when the frequency is high.
  • the read interval between the colors of the first red pixel and the first green pixel is 10 ⁇ s
  • the read interval of one pixel is 1 ⁇ s
  • the non-TDI transmission when four pixels are added is a function.
  • the transmission function TF2 is a TDI transmission function when the read interval between the colors of the first red pixel and the first green pixel is 10 ⁇ s
  • the read interval of one pixel is 1 ⁇ s
  • four pixels are added.
  • the transmission function TF2 is a TDI transmission function when the read interval between the colors of the first red pixel and the first green pixel is 5 ⁇ s
  • the read interval of one pixel is 1 ⁇ s
  • four pixels are added. Is.
  • the transfer function shows wavy behavior depending on the frequency.
  • a value of zero in the transfer function indicates that the difference in vibration is zero between the first pixel in red and the first pixel in green, for example, when the frequencies have maximum vibration values. That is, the residual noise of vibration becomes zero due to the correspondence between the read time difference between the first red pixel and the first green pixel and the frequency of vibration. For example, if the frequency shifts and the vibration difference does not become zero, the transfer function becomes a finite value. The transfer function periodically becomes zero, depending on the multiple of the frequency.
  • the final residual noise is the integral (area) of the product of the vibration noise spectrum NS and the transfer functions TF1 to TF3.
  • the unit of the area is arbitrary, and the area of the product of the vibration noise spectrum NS and the transfer functions TF1 to TF3 is 29161.9, 7945.6, and 4000, respectively.
  • Comparing the transfer function TF1 and the transfer function TF2 it can be seen that the noise can be compressed by averaging with 4 pixels by the TDI process. Further, when the transfer function TF2 and the transfer function TF3 are compared, it can be seen that the smaller the read interval between the colors of the first red pixel and the first green pixel, the smaller the noise. Therefore, it can be seen that the vibration resistance is improved by reducing the intercolor gap.
  • the image pickup apparatus 100 which is a TDI color sensor
  • two pixels P for different colors are arranged so as to be in contact with each other without a gap.
  • the intercolor gap GC can be suppressed, and deterioration of image quality due to vibration can be suppressed.
  • the arrangement of the color filters is not necessarily limited to the example shown in FIG.
  • a color filter in which one of red, blue, and green is further added may be used.
  • FIG. 20 is a diagram showing an example of the configuration of the image pickup apparatus 100 in the first comparative example.
  • the first modification is different from the first embodiment in that a CCD (Charge Coupled Device) structure is used instead of the CMOS (Complementary Metal Oxide Semiconductor) structure.
  • CCD Charge Coupled Device
  • CMOS Complementary Metal Oxide Semiconductor
  • the CCD structure since the CCD structure is used, for example, a circuit for extracting the electric charge generated by the red pixel PR is arranged between the red pixel PR and the green pixel PG. To. As a result, the intercolor gap GC of the pixel P becomes large. As a result, the accuracy of the composite image deteriorates due to vibration in the direction (X direction) perpendicular to the traveling direction (Y direction) of the subject. That is, the image quality deteriorates due to vibration. In the CCD structure, it is difficult to reduce the intercolor gap GC because it is necessary to provide a space for the output circuit between the color pixel groups. In the example shown in FIG. 20, the blue pixel PB is omitted, but the intercolor gap GC between the green pixel PG and the blue pixel PB is also the same.
  • the image pickup apparatus 100 in the first embodiment has a CMOS structure, and an ADC 310 is arranged for each pixel P.
  • the TDI processing in the arithmetic circuit 410 (signal processing circuit 400) can be the addition of digital signals.
  • the space of the output circuit in the CCD structure becomes unnecessary. Therefore, the intercolor gap GC (gap between color pixel groups) of the pixel P can be suppressed, and the deterioration of the image quality due to vibration can be suppressed.
  • FIG. 21 is a diagram showing an example of the configuration of the image pickup apparatus 100 in the second modification.
  • the second modification is different from the first embodiment in that the ADC 310 is provided not for each pixel P but for each column (pixel string) including a plurality of pixels P.
  • a column ADC type in which ADC 310 is arranged for each column is also conceivable.
  • the signal line emits a signal line for outputting the signal line voltage toward the lower side of the paper surface of FIG. 21.
  • the intercolor gap can be suppressed as in the first embodiment.
  • the aperture ratio is lowered.
  • the signal line is arranged above the pixels P of other colors (Z direction).
  • the first embodiment it is possible to suppress a decrease in the aperture ratio due to the arrangement of the signal line, and it is possible to suppress a decrease in the area of the photoelectric conversion element 222.
  • the column ADC type can also suppress the intercolor gap and suppress the deterioration of image quality due to vibration.
  • the ADC 310 is arranged for each pixel P.
  • FIG. 22 is a diagram showing an example of the configuration of the image pickup apparatus 100 according to the second embodiment of the present technology.
  • the second embodiment is different from the first embodiment in that the color pattern of the color filter is a bayer array.
  • the color of the pixel P changes for each pixel P along the Y direction. That is, the two pixels P adjacent to each other along the moving direction of the subject 511 receive light of different colors.
  • the first pixel area, the second pixel area, and the third pixel area are arranged in a mixed manner in the Y direction and the X direction.
  • the first pixel area and the second pixel area are arranged without a gap in the Y direction.
  • the second pixel area and the third pixel area are arranged without a gap in the Y direction. More specifically, as shown in FIG. 22, the first pixel region, the second pixel region, and the third pixel region are arranged in a bayer array.
  • first color filter, the second color filter, and the third color filter are arranged in a mixed manner in the Y direction and the X direction.
  • the first color filter and the second color filter are arranged without a gap in the Y direction.
  • the second color filter and the third color filter are arranged without a gap in the Y direction. More specifically, as shown in FIG. 22, the first color filter, the second color filter, and the third color filter are arranged in a bayer array.
  • the bayer array pixels P for different colors are arranged in the line next to a certain pixel P.
  • the time difference of the imaging timing for each color can be shortened.
  • the correlation of vibrations received for each color can be further strengthened, and deterioration of image quality due to vibrations such as color shift can be further suppressed. Therefore, the bayer arrangement can be selected as an option when emphasizing color shift.
  • the ADC 310 is arranged for each pixel P, and the latch circuit 350 holds the time code as described with reference to FIG. 7, so that the integration process is performed later. Can be done. As a result, the color filter of the bayer array can be selected.
  • the present technology can have the following configurations.
  • a photoelectric conversion unit provided for each of a plurality of pixels and outputting an electrical signal photoelectrically converted within a period corresponding to the moving speed of a relatively moving subject.
  • a calculation unit that integrates the electric signal for each color of the plurality of pixels is provided.
  • An imaging device in which two pixels that photoelectrically convert light of different colors are arranged without gaps along the relative moving direction of the subject.
  • a second pixel region including one or more of the pixels that photoelectrically convert light of the first color and one or more of the pixels that photoelectrically convert light of a second color different from the first color.
  • a pixel region and a third pixel region containing one or more of the pixels that photoelectrically convert light of the first color and a third color different from the second color are along the relative moving direction of the subject.
  • the imaging device according to (1) which is arranged without gaps.
  • Each of the first pixel region, the second pixel region, and the third pixel region includes one or more of the pixels in the first direction, which is the relative movement direction of the subject, and the first pixel region.
  • the imaging apparatus according to (2) which includes one or more of the pixels in a second direction intersecting in one direction.
  • the first pixel region, the second pixel region, and the third pixel region are arranged without being mixed in the second direction.
  • the first pixel region and the second pixel region are arranged without gaps in the first direction.
  • the imaging apparatus wherein the second pixel region and the third pixel region are arranged without gaps in the first direction.
  • the first pixel region, the second pixel region, and the third pixel region are arranged in a mixed manner in the first direction and the second direction.
  • the first pixel region and the second pixel region are arranged without gaps in the first direction.
  • the imaging apparatus according to (3), wherein the second pixel region and the third pixel region are arranged without gaps in the first direction.
  • the image pickup apparatus according to (5), wherein the first pixel region is arranged in the second pixel region and the third pixel region is arranged in a bayer array.
  • the pixel has a color filter corresponding to the wavelength band of light to be photoelectrically converted.
  • the imaging device according to any one of (1) to (6), wherein the two color filters corresponding to different colors are arranged without a gap along the relative moving direction of the subject.
  • the first pixel region has one or more of the pixels having a first color filter that transmits light of the first color.
  • the second pixel region comprises one or more of the pixels having a second color filter that transmits light of the second color.
  • the third pixel region comprises one or more of the pixels having a third color filter that transmits light of the third color.
  • the first color filter, the second color filter, and the third color filter are arranged without gaps along the first direction, which is the relative movement direction of the subject, (2) to (6).
  • the imaging apparatus according to any one of the above.
  • the first color filter, the second color filter, and the third color filter are arranged without being mixed in the second direction intersecting the first direction.
  • the first color filter and the second color filter are arranged without gaps in the first direction.
  • the image pickup apparatus according to (8), wherein the second color filter and the third color filter are arranged without gaps in the first direction.
  • the first color filter, the second color filter, and the third color filter are arranged in a mixed manner in the first direction and the second direction intersecting the first direction.
  • the first color filter and the second color filter are arranged without gaps in the first direction.
  • the image pickup apparatus according to (8), wherein the second color filter and the third color filter are arranged without gaps in the first direction.
  • the image pickup apparatus (11) The image pickup apparatus according to (10), wherein the first color filter, the second color filter, and the third color filter are arranged in a bayer array. (12) An ADC (Analog to Digital Converter), which is arranged for each of the plurality of pixels and converts the electric signal into a digital signal, is further provided.
  • the imaging device according to any one of (1) to (11), wherein the calculation unit integrates the digital signals for each color.
  • the image pickup apparatus (14) The image pickup apparatus according to (13), wherein the ADC is arranged at a position overlapping the photoelectric conversion unit in the stacking direction.
  • Imaging device and A moving unit that moves the subject of the imaging device at a predetermined speed is provided.
  • the image pickup device A photoelectric conversion unit provided for each of a plurality of pixels and outputting an electrical signal photoelectrically converted within a period corresponding to the moving speed of a relatively moving subject.
  • a calculation unit that integrates the electric signal for each color of the plurality of pixels is provided.
  • An electronic device in which two pixels that photoelectrically convert light of different colors are arranged without gaps along the relative moving direction of the subject.

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Abstract

[Problem] To curb degradation of image quality due to vibration. [Solution] This imaging device is provided with: a photoelectric conversion unit that is provided to each of a plurality of pixels and outputs an electrical signal obtained through photoelectric conversion within a period corresponding to a speed of movement of a subject moving in a relative manner; and a computation unit for integrating the electrical signal for each of the colors of the plurality of pixels. Two aforementioned pixels that perform photoelectric conversion of different colors of light are arranged without any gap along the direction of relative movement of the subject.

Description

撮像装置及び電子機器Imaging devices and electronic devices
 本開示による実施形態は、撮像装置及び電子機器に関する。 The embodiments according to the present disclosure relate to an imaging device and an electronic device.
 FA(Factory Automation)及び空撮等の分野において、時間遅延積分(TDI:Time Delay Integration)センサが用いられている。このTDIセンサは、被写体の移動速度に合わせて時間をずらしながら、電荷量を積分するTDI処理を行うセンサである(特許文献1を参照)。 Time delay integration (TDI) sensors are used in fields such as FA (Factory Automation) and aerial photography. This TDI sensor is a sensor that performs TDI processing that integrates the amount of electric charge while shifting the time according to the moving speed of the subject (see Patent Document 1).
特表2014-510447号公報Japanese Patent Application Laid-Open No. 2014-510447
 しかしながら、例えば、CCD(Charge Coupled Device)構造においてTDIカラーセンサを実現する場合、赤群、緑群及び青群等の各色群間に出力回路を配置する必要がある。すなわち、色群間に色間ギャップが生じてしまう。CCD構造では、色間ギャップを抑制することが困難である。色間ギャップができると、TDIカラーセンサの原稿(被写体)読み取り時の原稿の進行方向に垂直方向の振動により、色ずれにより復元画像の正確さが低下するという問題があった。すなわち、読み取り時の振動によってTDIカラーセンサの画質が劣化してしまう可能性がある。 However, for example, when realizing a TDI color sensor in a CCD (Charge Coupled Device) structure, it is necessary to arrange an output circuit between each color group such as a red group, a green group, and a blue group. That is, a color gap is generated between the color groups. In the CCD structure, it is difficult to suppress the intercolor gap. When a color gap is formed, there is a problem that the accuracy of the restored image is lowered due to color shift due to vibration in the direction perpendicular to the traveling direction of the document when the document (subject) is read by the TDI color sensor. That is, the image quality of the TDI color sensor may deteriorate due to vibration during reading.
 そこで、本開示では、振動による画質の劣化を抑制することができる撮像装置及び電子機器を提供するものである。 Therefore, the present disclosure provides an imaging device and an electronic device capable of suppressing deterioration of image quality due to vibration.
 上記の課題を解決するために、本開示によれば、
 複数の画素のそれぞれに設けられ、相対的に移動する被写体の移動速度に応じた期間内に光電変換された電気信号を出力する光電変換部と、
 前記電気信号を前記複数の画素の色ごとに積算する演算部と、を備え、
 互いに異なる色の光を光電変換する2つの前記画素は、前記被写体の相対的な移動方向に沿って、隙間無く配置される、撮像装置が提供される。
To solve the above problems, according to this disclosure,
A photoelectric conversion unit provided for each of a plurality of pixels and outputting an electrical signal photoelectrically converted within a period corresponding to the moving speed of a relatively moving subject.
A calculation unit that integrates the electric signal for each color of the plurality of pixels is provided.
An imaging device is provided in which two pixels that photoelectrically convert light of different colors are arranged without gaps along the relative moving direction of the subject.
 第1色の光を光電変換する1以上の前記画素を含む第1画素領域と、前記第1色とは異なる第2色の光を光電変換する1以上の前記画素を含む第2画素領域と、前記第1色及び前記第2色とは異なる第3色の光を光電変換する1以上の前記画素を含む第3画素領域と、が前記被写体の相対的な移動方向に沿って、隙間無く配置されてもよい。 A first pixel region containing one or more of the pixels that photoelectrically convert light of the first color, and a second pixel region including one or more of the pixels that photoelectrically convert light of a second color different from the first color. The third pixel region including one or more of the pixels that photoelectrically convert the light of the first color and the light of the third color different from the second color is without a gap along the relative moving direction of the subject. It may be arranged.
 前記第1画素領域、前記第2画素領域、及び前記第3画素領域のそれぞれは、前記被写体の相対的な移動方向である第1方向に1以上の前記画素を含み、かつ前記第1方向に交差する第2方向に1以上の前記画素を含んでもよい。 Each of the first pixel region, the second pixel region, and the third pixel region includes one or more of the pixels in the first direction, which is the relative movement direction of the subject, and in the first direction. One or more of the pixels may be included in the intersecting second direction.
 前記第1画素領域、前記第2画素領域、及び前記第3画素領域は、前記第2方向に混在されずに配置され、
 前記第1画素領域及び前記第2画素領域は、前記第1方向に隙間無く配置され、
 前記第2画素領域及び前記第3画素領域は、前記第1方向に隙間無く配置されてもよい。
The first pixel region, the second pixel region, and the third pixel region are arranged without being mixed in the second direction.
The first pixel region and the second pixel region are arranged without gaps in the first direction.
The second pixel region and the third pixel region may be arranged without a gap in the first direction.
 前記第1画素領域、前記第2画素領域、及び前記第3画素領域は、前記第1方向及び前記第2方向に混在されて配置され、
 前記第1画素領域及び前記第2画素領域は、前記第1方向に隙間無く配置され、
 前記第2画素領域及び前記第3画素領域は、前記第1方向に隙間無く配置されてもよい。
The first pixel region, the second pixel region, and the third pixel region are arranged in a mixed manner in the first direction and the second direction.
The first pixel region and the second pixel region are arranged without gaps in the first direction.
The second pixel region and the third pixel region may be arranged without a gap in the first direction.
 前記第1画素領域は、前記第2画素領域、及び前記第3画素領域は、ベイヤ配列で配置されてもよい。 The first pixel area, the second pixel area, and the third pixel area may be arranged in a bayer array.
 前記画素は、光電変換する光の波長帯に対応するカラーフィルタを有し、
 互いに異なる色に対応する2つの前記カラーフィルタは、前記被写体の相対的な移動方向に沿って、隙間無く配置されてもよい。
The pixel has a color filter corresponding to the wavelength band of light to be photoelectrically converted.
The two color filters corresponding to different colors may be arranged without gaps along the relative moving direction of the subject.
 前記第1画素領域は、前記第1色の光を透過する第1カラーフィルタを有する1以上の前記画素を有し、
 前記第2画素領域は、前記第2色の光を透過する第2カラーフィルタを有する1以上の前記画素を有し、
 前記第3画素領域は、前記第3色の光を透過する第3カラーフィルタを有する1以上の前記画素を有し、
 前記第1カラーフィルタ、前記第2カラーフィルタ、及び前記第3カラーフィルタは、前記被写体の相対的な移動方向である第1方向に沿って、隙間無く配置されてもよい。
The first pixel region comprises one or more of the pixels having a first color filter that transmits light of the first color.
The second pixel region comprises one or more of the pixels having a second color filter that transmits light of the second color.
The third pixel region comprises one or more of the pixels having a third color filter that transmits light of the third color.
The first color filter, the second color filter, and the third color filter may be arranged without gaps along the first direction, which is the relative movement direction of the subject.
 前記第1カラーフィルタ、前記第2カラーフィルタ、及び前記第3カラーフィルタは、前記第1方向に交差する第2方向に混在されずに配置され、
 前記第1カラーフィルタ及び前記第2カラーフィルタは、前記第1方向に隙間無く配置され、
 前記第2カラーフィルタ及び前記第3カラーフィルタは、前記第1方向に隙間無く配置されてもよい。
The first color filter, the second color filter, and the third color filter are arranged without being mixed in the second direction intersecting the first direction.
The first color filter and the second color filter are arranged without gaps in the first direction.
The second color filter and the third color filter may be arranged without a gap in the first direction.
 前記第1カラーフィルタ、前記第2カラーフィルタ、及び前記第3カラーフィルタは、前記第1方向及び前記第1方向に交差する第2方向に混在されて配置され、
 前記第1カラーフィルタ及び前記第2カラーフィルタは、前記第1方向に隙間無く配置され、
 前記第2カラーフィルタ及び前記第3カラーフィルタは、前記第1方向に隙間無く配置されてもよい。
The first color filter, the second color filter, and the third color filter are arranged in a mixed manner in the first direction and the second direction intersecting the first direction.
The first color filter and the second color filter are arranged without gaps in the first direction.
The second color filter and the third color filter may be arranged without a gap in the first direction.
 前記第1カラーフィルタ、前記第2カラーフィルタ、及び前記第3カラーフィルタは、ベイヤ配列で配置されてもよい。 The first color filter, the second color filter, and the third color filter may be arranged in a bayer array.
 前記複数の画素のそれぞれごとに配置され、前記電気信号をデジタル信号に変換するADC(Analog to Digital Converter)をさらに備え、
 前記演算部は、前記デジタル信号を色ごとに積算してもよい。
An ADC (Analog to Digital Converter), which is arranged for each of the plurality of pixels and converts the electric signal into a digital signal, is further provided.
The calculation unit may integrate the digital signals for each color.
 前記光電変換部が配置される第1チップと、
 前記第1チップと積層され、前記ADCが配置される第2チップと、をさらに備えてもよい。
The first chip on which the photoelectric conversion unit is arranged and
A second chip that is laminated with the first chip and on which the ADC is arranged may be further provided.
 前記ADCは、前記光電変換部と積層方向に重なる位置に配置されてもよい。 The ADC may be arranged at a position where it overlaps with the photoelectric conversion unit in the stacking direction.
 本開示によれば、撮像装置と、
 前記撮像装置の被写体を所定の速度で移動させる移動部と、を備え、
 前記撮像装置は、
 複数の画素のそれぞれに設けられ、相対的に移動する被写体の移動速度に応じた期間内に光電変換された電気信号を出力する光電変換部と、
 前記電気信号を前記複数の画素の色ごとに積算する演算部と、を備え、
 互いに異なる色の光を光電変換する2つの前記画素は、前記被写体の相対的な移動方向に沿って、隙間無く配置される、電子機器が提供される。
According to the present disclosure, the imaging device and
A moving unit that moves the subject of the imaging device at a predetermined speed is provided.
The image pickup device
A photoelectric conversion unit provided for each of a plurality of pixels and outputting an electrical signal photoelectrically converted within a period corresponding to the moving speed of a relatively moving subject.
A calculation unit that integrates the electric signal for each color of the plurality of pixels is provided.
An electronic device is provided in which two pixels that photoelectrically convert light of different colors are arranged without gaps along the relative moving direction of the subject.
本技術の第1の実施の形態における撮像装置の一構成例を示すブロック図である。It is a block diagram which shows one configuration example of the image pickup apparatus in the 1st Embodiment of this technique. 本技術の第1の実施の形態における撮像システムの利用例を説明するための図である。It is a figure for demonstrating the use example of the image pickup system in 1st Embodiment of this technique. 本技術の第1の実施の形態における固体撮像素子の積層構造の一例を示す図である。It is a figure which shows an example of the laminated structure of the solid-state image pickup device in the 1st Embodiment of this technique. 本技術の第1の実施の形態における受光チップの一構成例を示すブロック図である。It is a block diagram which shows one structural example of the light receiving chip in the 1st Embodiment of this technique. 本技術の第1の実施の形態における回路チップの一構成例を示すブロック図である。It is a block diagram which shows one structural example of the circuit chip in 1st Embodiment of this technique. 本技術の第1の実施の形態における画素AD(Analog to Digital)変換部の一構成例を示す図である。It is a figure which shows one configuration example of the pixel AD (Analog to Digital) conversion part in the 1st Embodiment of this technique. 本技術の第1の実施の形態におけるADC(Analog to Digital Converter)の一構成例を示すブロック図である。It is a block diagram which shows one configuration example of ADC (Analog to Digital Converter) in the 1st Embodiment of this technique. 本技術の第1の実施の形態における差動入力回路および正帰還回路の一構成例を示す回路図である。It is a circuit diagram which shows one configuration example of the differential input circuit and the positive feedback circuit in the 1st Embodiment of this technique. 本技術の第1の実施の形態における画素回路および増幅回路の一構成例を示す回路図である。It is a circuit diagram which shows one configuration example of the pixel circuit and the amplifier circuit in the 1st Embodiment of this technique. 本技術の第1の実施の形態における画素内の素子のレイアウトの一例を示す平面図である。It is a top view which shows an example of the layout of the element in a pixel in 1st Embodiment of this technique. 本技術の第1の実施の形態における信号処理回路の一構成例を示すブロック図である。It is a block diagram which shows one structural example of the signal processing circuit in 1st Embodiment of this technique. 本技術の第1の実施の形態における演算回路の一構成例を示す回路図である。It is a circuit diagram which shows one structural example of the arithmetic circuit in 1st Embodiment of this technique. 本技術の第1の実施の形態におけるTDI処理の一例を示す図である。It is a figure which shows an example of TDI processing in 1st Embodiment of this technique. 本技術の第1の実施の形態における撮像システムの動作の一例を示すフローチャートの一例である。This is an example of a flowchart showing an example of the operation of the imaging system according to the first embodiment of the present technology. 本技術の第1の実施の形態における撮像装置の構成の一例を示す図である。It is a figure which shows an example of the structure of the image pickup apparatus in the 1st Embodiment of this technique. 色間ギャップが大きい場合における振動の影響を説明する図である。It is a figure explaining the influence of vibration when the intercolor gap is large. 色間ギャップが小さい場合における振動の影響を説明する図である。It is a figure explaining the influence of vibration when the intercolor gap is small. 色間ギャップを説明する図である。It is a figure explaining the intercolor gap. 色間ギャップと振動の関係を説明する図である。It is a figure explaining the relationship between a color gap and vibration. 伝達関数を示すグラフである。It is a graph which shows a transfer function. 第1変形例における撮像素子の構成の一例を示す図である。It is a figure which shows an example of the structure of the image pickup device in the 1st modification. 第2変形例における撮像装置の構成の一例を示す図である。It is a figure which shows an example of the structure of the image pickup apparatus in the 2nd modification. 本技術の第2の実施の形態における撮像装置の構成の一例を示す図である。It is a figure which shows an example of the structure of the image pickup apparatus in the 2nd Embodiment of this technique.
 以下、図面を参照して、撮像装置及び電子機器の実施形態について説明する。以下では、撮像装置及び電子機器の主要な構成部分を中心に説明するが、撮像装置及び電子機器には、図示又は説明されていない構成部分や機能が存在しうる。以下の説明は、図示又は説明されていない構成部分や機能を除外するものではない。 Hereinafter, embodiments of the imaging device and the electronic device will be described with reference to the drawings. In the following, the main components of the image pickup device and the electronic device will be mainly described, but the image pickup device and the electronic device may have components and functions not shown or described. The following description does not exclude components or functions not shown or described.
 <第1の実施の形態>
 [撮像装置の構成例]
 図1は、本技術の第1の実施の形態における撮像装置100の一構成例を示すブロック図である。この撮像装置100は、画像データを撮像する装置であり、光学部110、固体撮像素子200、記憶部120、制御部130および通信部140を備える。
<First Embodiment>
[Configuration example of imaging device]
FIG. 1 is a block diagram showing a configuration example of an image pickup apparatus 100 according to a first embodiment of the present technology. The image pickup device 100 is a device for capturing image data, and includes an optical unit 110, a solid-state image sensor 200, a storage unit 120, a control unit 130, and a communication unit 140.
 光学部110は、入射光を集光して固体撮像素子200に導くものである。固体撮像素子200は、画像データを撮像するものである。この固体撮像素子200は、画像データを記憶部120に信号線209を介して供給する。 The optical unit 110 collects the incident light and guides it to the solid-state image sensor 200. The solid-state image sensor 200 captures image data. The solid-state image sensor 200 supplies image data to the storage unit 120 via a signal line 209.
 記憶部120は、画像データを記憶するものである。制御部130は、固体撮像素子200を制御して画像データを撮像させるものである。この制御部130は、例えば、信号線208を介して、撮像タイミングを示す垂直同期信号VSYNCを固体撮像素子200に供給する。 The storage unit 120 stores image data. The control unit 130 controls the solid-state image sensor 200 to capture image data. The control unit 130 supplies the solid-state image sensor 200 with a vertical synchronization signal VSYNC indicating the image pickup timing, for example, via the signal line 208.
 通信部140は、画像データを記憶部120から読み出して外部に送信するものである。 The communication unit 140 reads the image data from the storage unit 120 and transmits it to the outside.
 図2は、本技術の第1の実施の形態における撮像装置100の利用例を説明するための図である。同図に例示するように、撮像装置100は、ベルトコンベア510が設けられた工場などで用いられる。 FIG. 2 is a diagram for explaining a usage example of the image pickup apparatus 100 in the first embodiment of the present technology. As illustrated in the figure, the image pickup apparatus 100 is used in a factory or the like where a belt conveyor 510 is provided.
 図2は、本技術の電子機器1を示す図でもある。電子機器1は、撮像装置100と、ベルトコンベア(移動部)510と、を含む。電子機器1は、撮像装置100を固定するための筐体(図示せず)等を含んでいてもよい。 FIG. 2 is also a diagram showing the electronic device 1 of the present technology. The electronic device 1 includes an image pickup device 100 and a belt conveyor (moving unit) 510. The electronic device 1 may include a housing (not shown) or the like for fixing the image pickup apparatus 100.
 ベルトコンベア510は、一定の速度で、被写体511を所定の方向に移動させるものである。撮像装置100は、ベルトコンベア510の近傍に固定され、この被写体511を撮像して画像データを生成する。画像データは、例えば、欠陥の有無などの検査に用いられる。これにより、FAが実現される。 The belt conveyor 510 moves the subject 511 in a predetermined direction at a constant speed. The image pickup apparatus 100 is fixed in the vicinity of the belt conveyor 510, and images the subject 511 to generate image data. The image data is used, for example, for inspection of the presence or absence of defects. As a result, FA is realized.
 なお、撮像装置100は、一定速度で移動する被写体511を撮像しているが、この構成に限定されない。空撮など、被写体に対して撮像装置100が一定速度で移動して撮像する構成であってもよい。 The image pickup apparatus 100 captures a subject 511 moving at a constant speed, but the present invention is not limited to this configuration. The image pickup device 100 may move at a constant speed to take an image of the subject, such as in aerial photography.
 [固体撮像素子の構成例]
 図3は、本技術の第1の実施の形態における固体撮像素子200の積層構造の一例を示す図である。この固体撮像素子200は、回路チップ(第2チップ)202と、その回路チップ202に積層された受光チップ(第1チップ)201とを備える。これらのチップは、ビアなどの接続部を介して電気的に接続される。なお、ビアの他、Cu-Cu接合やバンプにより接続することもできる。
[Structure example of solid-state image sensor]
FIG. 3 is a diagram showing an example of a laminated structure of the solid-state image sensor 200 according to the first embodiment of the present technology. The solid-state image sensor 200 includes a circuit chip (second chip) 202 and a light receiving chip (first chip) 201 laminated on the circuit chip 202. These chips are electrically connected via a connection such as a via. In addition to vias, it can also be connected by Cu-Cu bonding or bumps.
 図4は、本技術の第1の実施の形態における受光チップ201の一構成例を示すブロック図である。受光チップ201には、画素アレイ部210および周辺回路212が設けられる。 FIG. 4 is a block diagram showing a configuration example of the light receiving chip 201 according to the first embodiment of the present technology. The light receiving chip 201 is provided with a pixel array unit 210 and a peripheral circuit 212.
 画素アレイ部210には、複数の画素回路220が二次元格子状に配列される。また、画素アレイ部210は、複数の画素ブロック211に分割される。これらの画素ブロック211のそれぞれには、例えば、4行×2列の画素回路220が配列される。また、画素回路220ごとに、その画素回路220の外部に複数のトランジスタがさらに配置されているが、それらのトランジスタは、記載の便宜上、同図において省略されている。 A plurality of pixel circuits 220 are arranged in a two-dimensional grid pattern in the pixel array unit 210. Further, the pixel array unit 210 is divided into a plurality of pixel blocks 211. In each of these pixel blocks 211, for example, a pixel circuit 220 having 4 rows × 2 columns is arranged. Further, for each pixel circuit 220, a plurality of transistors are further arranged outside the pixel circuit 220, but these transistors are omitted in the figure for convenience of description.
 周辺回路212には、例えば、DC(Direct Current)電圧を供給する回路などが配置される。 For example, a circuit that supplies a DC (Direct Current) voltage is arranged in the peripheral circuit 212.
 図5は、本技術の第1の実施の形態における回路チップ202の一構成例を示すブロック図である。この回路チップ202には、DAC(Digital to Analog Converter)251、画素駆動回路252、時刻コード生成部253、画素AD変換部254および垂直走査回路255が配置される。さらに回路チップ202には、制御回路256、信号処理回路400、画像処理回路260、出力回路257が配置される。 FIG. 5 is a block diagram showing a configuration example of the circuit chip 202 according to the first embodiment of the present technology. A DAC (Digital to Analog Converter) 251, a pixel drive circuit 252, a time code generation unit 253, a pixel AD conversion unit 254, and a vertical scanning circuit 255 are arranged on the circuit chip 202. Further, a control circuit 256, a signal processing circuit 400, an image processing circuit 260, and an output circuit 257 are arranged on the circuit chip 202.
 DAC251は、所定のAD変換期間内に亘って参照信号をDA(Digital to Analog)変換により生成するものである。例えば、のこぎり刃状のランプ信号が参照信号として用いられる。DAC251は、参照信号を画素AD変換部254に供給する。 The DAC 251 generates a reference signal by DA (Digital to Analog) conversion within a predetermined AD conversion period. For example, a saw blade-shaped lamp signal is used as a reference signal. The DAC 251 supplies the reference signal to the pixel AD conversion unit 254.
 時刻コード生成部253は、AD変換期間内の時刻を示す時刻コードを生成するものである。時刻コード生成部253は、例えば、カウンタにより実現される。カウンタとして、例えば、グレイコードカウンタが用いられる。時刻コード生成部253は、時刻コードを画素AD変換部254へ供給する。 The time code generation unit 253 generates a time code indicating the time within the AD conversion period. The time code generation unit 253 is realized by, for example, a counter. As the counter, for example, a Gray code counter is used. The time code generation unit 253 supplies the time code to the pixel AD conversion unit 254.
 画素駆動回路252は、画素回路220のそれぞれを駆動してアナログの画素信号を生成させるものである。 The pixel drive circuit 252 drives each of the pixel circuits 220 to generate an analog pixel signal.
 画素AD変換部254は、画素回路220のそれぞれのアナログ信号(すなわち、画素信号)をデジタル信号に変換するAD変換を行うものである。この画素AD変換部254は、複数のクラスタ300により分割される。クラスタ300は、画素ブロック211ごとに設けられ、対応する画素ブロック211内のアナログ信号をデジタル信号に変換する。 The pixel AD conversion unit 254 performs AD conversion that converts each analog signal (that is, a pixel signal) of the pixel circuit 220 into a digital signal. The pixel AD conversion unit 254 is divided by a plurality of clusters 300. The cluster 300 is provided for each pixel block 211 and converts the analog signal in the corresponding pixel block 211 into a digital signal.
 画素AD変換部254は、AD変換によりデジタル信号を配列した画像データをフレームとして生成し、信号処理回路400に供給する。 The pixel AD conversion unit 254 generates image data in which digital signals are arranged by AD conversion as a frame and supplies the image data to the signal processing circuit 400.
 垂直走査回路255は、画素AD変換部254を駆動してAD変換を実行させるものである。 The vertical scanning circuit 255 drives the pixel AD conversion unit 254 to execute AD conversion.
 信号処理回路400は、フレームに対して所定の信号処理を行うものである。信号処理として、CDS(Correlated Double Sampling)処理およびTDI処理を含む各種の処理が実行される。この信号処理回路400は、処理後のフレームを画像処理回路260に供給する。 The signal processing circuit 400 performs predetermined signal processing on the frame. As signal processing, various processes including CDS (Correlated Double Sampling) processing and TDI processing are executed. The signal processing circuit 400 supplies the processed frame to the image processing circuit 260.
 画像処理回路260は、信号処理回路400からのフレームに対して、所定の画像処理を実行するものである。画像処理として、画像認識処理、黒レベル補正処理、画像補正処理やデモザイク処理などが実行される。この画像処理回路260は、処理後のフレームを出力回路257に供給する。 The image processing circuit 260 executes predetermined image processing on the frame from the signal processing circuit 400. As image processing, image recognition processing, black level correction processing, image correction processing, demosaic processing, and the like are executed. The image processing circuit 260 supplies the processed frame to the output circuit 257.
 出力回路257は、画像処理後のフレームを外部に出力するものである。 The output circuit 257 outputs the frame after image processing to the outside.
 制御回路256は、DAC251、画素駆動回路252、垂直走査回路255、信号処理回路400、画像処理回路260および出力回路257のそれぞれの動作タイミングを垂直同期信号VSYNCに同期して制御するものである。 The control circuit 256 controls the operation timings of the DAC 251, the pixel drive circuit 252, the vertical scanning circuit 255, the signal processing circuit 400, the image processing circuit 260, and the output circuit 257 in synchronization with the vertical synchronization signal VSYNC.
 [画素AD変換部の構成例]
 図6は、本技術の第1の実施の形態における画素AD変換部254の一構成例を示す図である。この画素AD変換部254には、複数のADC310が二次元格子状に配列される。ADC310は、画素回路220ごとに配置される。画素回路220の行数および列数がN行(Nは、整数)およびM列(Mは、整数)である場合、N×M個のADC310が配置される。
[Configuration example of pixel AD conversion unit]
FIG. 6 is a diagram showing a configuration example of the pixel AD conversion unit 254 according to the first embodiment of the present technology. A plurality of ADCs 310 are arranged in a two-dimensional grid pattern in the pixel AD conversion unit 254. The ADC 310 is arranged for each pixel circuit 220. When the number of rows and columns of the pixel circuit 220 is N rows (N is an integer) and M columns (M is an integer), N × M ADC 310s are arranged.
 クラスタ300のそれぞれには、画素ブロック211内の画素回路220の個数と同じ個数のADC310が配置される。画素ブロック211内に4行×2列の画素回路220が配列される場合、クラスタ300内にも4行×2列のADC310が配列される。 In each of the clusters 300, the same number of ADC 310s as the number of pixel circuits 220 in the pixel block 211 are arranged. When the pixel circuit 220 having 4 rows × 2 columns is arranged in the pixel block 211, the ADC 310 having 4 rows × 2 columns is also arranged in the cluster 300.
 ADC310は、対応する画素回路220により生成されたアナログの画素信号に対してAD変換を行うものである。このADC310は、AD変換において、画素信号と参照信号とを比較し、その比較結果が反転したときの時刻コードを保持する。そして、ADC310は、保持した時刻コードをAD変換後のデジタル信号として出力する。 The ADC 310 performs AD conversion on an analog pixel signal generated by the corresponding pixel circuit 220. The ADC 310 compares the pixel signal and the reference signal in the AD conversion, and holds the time code when the comparison result is inverted. Then, the ADC 310 outputs the held time code as a digital signal after AD conversion.
 また、クラスタ300の列ごとにリピータ部360が配置される。クラスタ300の列数がM/2である場合、M/2個のリピータ部360が配置される。リピータ部360は、時刻コードを転送するものである。リピータ部360は、時刻コード生成部253からADC310へ時刻コードを転送する。また、リピータ部360は、ADC310から信号処理回路400へデジタル信号を転送する。このデジタル信号の転送は、デジタル信号の「読出し」とも呼ばれる。 In addition, a repeater unit 360 is arranged for each row of the cluster 300. When the number of columns of the cluster 300 is M / 2, M / 2 repeater units 360 are arranged. The repeater unit 360 transfers the time code. The repeater unit 360 transfers the time code from the time code generation unit 253 to the ADC 310. Further, the repeater unit 360 transfers a digital signal from the ADC 310 to the signal processing circuit 400. This transfer of digital signals is also referred to as "reading" the digital signals.
 また、同図において、かっこ内の数字は、ADC310のデジタル信号の読出し順序の一例を示す。例えば、1行目の奇数列のデジタル信号が1番目に読み出され、1行目の偶数列のデジタル信号が2番目に読み出される。2行目の奇数列のデジタル信号が3番目に読み出され、2行目の偶数列のデジタル信号が3番目に読み出される。以下、同様に、各行の奇数列、偶数列のデジタル信号が順に読み出される。 Further, in the figure, the numbers in parentheses indicate an example of the reading order of the digital signals of the ADC 310. For example, the odd-numbered column digital signal in the first row is read first, and the even-numbered column digital signal in the first row is read second. The odd-numbered column digital signal in the second row is read out third, and the even-numbered column digital signal in the second row is read out third. Hereinafter, similarly, the odd-numbered columns and even-numbered columns of the digital signals in each row are read out in order.
 なお、画素回路220ごとに、ADC310を配置しているが、この構成に限定されない。複数の画素回路220が1つのADC310を共有する構成であってもよい。 Although the ADC 310 is arranged for each pixel circuit 220, the configuration is not limited to this. A plurality of pixel circuits 220 may be configured to share one ADC 310.
 [ADCの構成例]
 図7は、本技術の第1の実施の形態におけるADC310の一構成例を示すブロック図である。このADC310は、差動入力回路320と、正帰還回路330と、ラッチ制御回路340と、複数のラッチ回路350とを備える。
[ADC configuration example]
FIG. 7 is a block diagram showing a configuration example of the ADC 310 according to the first embodiment of the present technology. The ADC 310 includes a differential input circuit 320, a positive feedback circuit 330, a latch control circuit 340, and a plurality of latch circuits 350.
 また、画素回路220とADC310との間には、増幅回路230が配置される。この増幅回路230は、画素回路220からの画素信号を増幅してADC310に供給するものである。これらの画素回路220および増幅回路230からなる回路は、1つの画素として機能する。 Further, an amplifier circuit 230 is arranged between the pixel circuit 220 and the ADC 310. The amplifier circuit 230 amplifies the pixel signal from the pixel circuit 220 and supplies it to the ADC 310. The circuit including the pixel circuit 220 and the amplifier circuit 230 functions as one pixel.
 また、画素回路220および増幅回路230と差動入力回路320の一部とは、受光チップ201に配置され、差動入力回路320の残りと、その後段の回路とは、回路チップ202に配置される。 Further, the pixel circuit 220, the amplifier circuit 230, and a part of the differential input circuit 320 are arranged on the light receiving chip 201, and the rest of the differential input circuit 320 and the circuit in the subsequent stage are arranged on the circuit chip 202. To.
 差動入力回路(コンパレータ)320は、増幅回路230からの画素信号と、DAC251からの参照信号とを比較するものである。この差動入力回路320は、比較結果を示す比較結果信号を正帰還回路330に供給する。 The differential input circuit (comparator) 320 compares the pixel signal from the amplifier circuit 230 with the reference signal from the DAC 251. The differential input circuit 320 supplies a comparison result signal indicating the comparison result to the positive feedback circuit 330.
 正帰還回路330は、出力の一部を入力(比較結果信号)に加算し、出力信号VCOとしてラッチ制御回路340に供給するものである。 The positive feedback circuit 330 adds a part of the output to the input (comparison result signal) and supplies it to the latch control circuit 340 as an output signal VCO.
 ラッチ制御回路340は、垂直走査回路255からの制御信号xWORDに従って、出力信号VCOが反転したときの時刻コードを複数のラッチ回路350に保持させるものである。 The latch control circuit 340 causes a plurality of latch circuits 350 to hold the time code when the output signal VCO is inverted according to the control signal xWORD from the vertical scanning circuit 255.
 ラッチ回路350は、ラッチ制御回路340の制御に従って、リピータ部360からの時刻コードを保持するものである。ラッチ回路350は、時刻コードのビット数の分、設けられる。例えば、時刻コードが15ビットの場合、ADC310内に、15個のラッチ回路350が配置される。また、保持された時刻コードは、AD変換後のデジタル信号としてリピータ部360により読み出される。 The latch circuit 350 holds the time code from the repeater unit 360 according to the control of the latch control circuit 340. The latch circuit 350 is provided for the number of bits of the time code. For example, when the time code is 15 bits, 15 latch circuits 350 are arranged in the ADC 310. Further, the held time code is read out by the repeater unit 360 as a digital signal after AD conversion.
 同図に例示した構成により、ADC310は、増幅回路230からの画素信号をデジタル信号に変換する。 According to the configuration illustrated in the figure, the ADC 310 converts the pixel signal from the amplifier circuit 230 into a digital signal.
 [差動入力回路および正帰還回路の構成例]
 図8は、本技術の第1の実施の形態における画素回路220、差動入力回路320および正帰還回路330の一構成例を示す回路図である。
[Configuration example of differential input circuit and positive feedback circuit]
FIG. 8 is a circuit diagram showing a configuration example of a pixel circuit 220, a differential input circuit 320, and a positive feedback circuit 330 according to the first embodiment of the present technology.
 差動入力回路320は、pMOS(p-channel Metal Oxide Semiconductor)トランジスタ321、324および326を備える。また、差動入力回路320はnMOS(n-channel MOS)トランジスタ322、323、325、327および328を備える。これらのうちnMOSトランジスタ322、323、325および328は、受光チップ201に配置され、残りは回路チップ202に配置される。 The differential input circuit 320 includes pMOS (p-channel Metal Oxide Semiconductor) transistors 321, 324 and 326. Further, the differential input circuit 320 includes nMOS (n-channel MOS) transistors 322, 323, 325, 327 and 328. Of these, the nMOS transistors 322, 323, 325 and 328 are arranged on the light receiving chip 201, and the rest are arranged on the circuit chip 202.
 nMOSトランジスタ322および325は、差動対を構成し、これらのトランジスタのソースは、nMOSトランジスタ323のドレインに共通に接続される。また、nMOSトランジスタ322のドレインは、pMOSトランジスタ321のドレインとpMOSトランジスタ321および324のゲートとに接続される。nMOSトランジスタ325のドレインは、pMOSトランジスタ324のドレインとpMOSトランジスタ326のゲートとに接続される。また、nMOSトランジスタ322のゲートには、DAC251からの参照信号REFが入力される。 The nMOS transistors 322 and 325 form a differential pair, and the source of these transistors is commonly connected to the drain of the nMOS transistor 323. Further, the drain of the nMOS transistor 322 is connected to the drain of the pMOS transistor 321 and the gate of the pMOS transistors 321 and 324. The drain of the nMOS transistor 325 is connected to the drain of the pMOS transistor 324 and the gate of the pMOS transistor 326. Further, a reference signal REF from the DAC 251 is input to the gate of the nMOS transistor 322.
 nMOSトランジスタ323のゲートには、所定のバイアス電圧Vbが印加され、nMOSトランジスタ323のソースには、所定の接地電圧が印加される。 A predetermined bias voltage Vb is applied to the gate of the nMOS transistor 323, and a predetermined ground voltage is applied to the source of the nMOS transistor 323.
 nMOSトランジスタ325のゲートには、増幅回路230からの画素信号SIGが入力される。 The pixel signal SIG from the amplifier circuit 230 is input to the gate of the nMOS transistor 325.
 pMOSトランジスタ321、324および326は、カレントミラー回路を構成する。pMOSトランジスタ321、324および326のソースには、電源電圧VDDHが印加される。この電源電圧VDDHは、後述する電源電圧VDDLよりも高い。 The pMOS transistors 321, 324 and 326 form a current mirror circuit. A power supply voltage VDDH is applied to the sources of the pMOS transistors 321, 324 and 326. This power supply voltage VDDH is higher than the power supply voltage VDDL described later.
 nMOSトランジスタ327のゲートには電源電圧VDDLが印加される。また、nMOSトランジスタ327のドレインは、pMOSトランジスタ326のドレインに接続され、ソースは、正帰還回路330に接続される。 A power supply voltage VDDL is applied to the gate of the nMOS transistor 327. Further, the drain of the nMOS transistor 327 is connected to the drain of the pMOS transistor 326, and the source is connected to the positive feedback circuit 330.
 nMOSトランジスタ328は、画素駆動回路252からのオートゼロ信号AZに従って、nMOSトランジスタ325のゲートおよびドレインを短絡するものである。 The nMOS transistor 328 short-circuits the gate and drain of the nMOS transistor 325 according to the auto zero signal AZ from the pixel drive circuit 252.
 正帰還回路330はpMOSトランジスタ331、332、334および335と、nMOSトランジスタ333、336および337とを備える。pMOSトランジスタ331および332とnMOSトランジスタ333とは、電源電圧VDDLに直列に接続される。また、pMOSトランジスタ331のゲートには、垂直走査回路255からの駆動信号INI2が入力される。pMOSトランジスタ332およびnMOSトランジスタ333の接続点は、nMOSトランジスタ327のソースに接続される。 The positive feedback circuit 330 includes pMOS transistors 331, 332, 334 and 335, and nMOS transistors 333, 336 and 337. The pMOS transistors 331 and 332 and the nMOS transistor 333 are connected in series with the power supply voltage VDDL. Further, a drive signal INI2 from the vertical scanning circuit 255 is input to the gate of the pMOS transistor 331. The connection points of the pMOS transistor 332 and the nMOS transistor 333 are connected to the source of the nMOS transistor 327.
 nMOSトランジスタ333のソースには接地電圧が印加され、ゲートには、垂直走査回路255からの駆動信号INI1が入力される。 A ground voltage is applied to the source of the nMOS transistor 333, and a drive signal INI1 from the vertical scanning circuit 255 is input to the gate.
 pMOSトランジスタ334および335は、電源電圧VDDLに直列に接続される。また、pMOSトランジスタ335のドレインは、pMOSトランジスタ332のゲートと、nMOSトランジスタ336および337のドレインとに接続される。pMOSトランジスタ335およびnMOSトランジスタ337のゲートには、垂直走査回路255からの制御信号TESTVCOが入力される。また、pMOSトランジスタ334およびnMOSトランジスタ336のゲートは、pMOSトランジスタ332およびnMOSトランジスタ333の接続点に接続される。 The pMOS transistors 334 and 335 are connected in series with the power supply voltage VDDL. Further, the drain of the pMOS transistor 335 is connected to the gate of the pMOS transistor 332 and the drain of the nMOS transistors 336 and 337. The control signal TESTVCO from the vertical scanning circuit 255 is input to the gates of the pMOS transistor 335 and the nMOS transistor 337. Further, the gates of the pMOS transistor 334 and the nMOS transistor 336 are connected to the connection points of the pMOS transistor 332 and the nMOS transistor 333.
 pMOSトランジスタ335およびnMOSトランジスタ337の接続点からは、出力信号VCOが出力される。また、nMOSトランジスタ336および337のソースには、接地電圧が印加される。 The output signal VCO is output from the connection point of the pMOS transistor 335 and the nMOS transistor 337. Further, a ground voltage is applied to the sources of the nMOS transistors 336 and 337.
 なお、差動入力回路320および正帰還回路330のそれぞれは、図7で説明した機能を持つのであれば、図8に例示した回路に限定されない。 Note that each of the differential input circuit 320 and the positive feedback circuit 330 is not limited to the circuit illustrated in FIG. 8 as long as it has the functions described in FIG. 7.
 [増幅回路および画素回路の構成例]
 図9は、本技術の第1の実施の形態における画素回路220および増幅回路230の一構成例を示す回路図である。
[Configuration example of amplifier circuit and pixel circuit]
FIG. 9 is a circuit diagram showing a configuration example of the pixel circuit 220 and the amplifier circuit 230 according to the first embodiment of the present technology.
 画素回路220は、排出トランジスタ221、光電変換素子222、転送トランジスタ223、リセットトランジスタ224、容量225、ゲイン制御トランジスタ226および浮遊拡散層227を備える。排出トランジスタ221、転送トランジスタ223、リセットトランジスタ224およびゲイン制御トランジスタ226として、例えば、nMOSトランジスタが用いられる。 The pixel circuit 220 includes an emission transistor 221, a photoelectric conversion element 222, a transfer transistor 223, a reset transistor 224, a capacitance 225, a gain control transistor 226, and a floating diffusion layer 227. For example, an nMOS transistor is used as the emission transistor 221, the transfer transistor 223, the reset transistor 224, and the gain control transistor 226.
 排出トランジスタ221は、画素駆動回路252からの駆動信号OFGに従って光電変換素子222に蓄積された電荷を排出させるものである。光電変換素子222は、光電変換により電荷を生成するものである。 The discharge transistor 221 discharges the electric charge accumulated in the photoelectric conversion element 222 according to the drive signal OFG from the pixel drive circuit 252. The photoelectric conversion element 222 generates an electric charge by photoelectric conversion.
 転送トランジスタ223は、画素駆動回路252からの転送信号TGに従って、光電変換素子222から浮遊拡散層227へ電荷を転送するものである。 The transfer transistor 223 transfers an electric charge from the photoelectric conversion element 222 to the floating diffusion layer 227 according to the transfer signal TG from the pixel drive circuit 252.
 リセットトランジスタ224は、画素駆動回路252からのリセット信号RSTに従って、浮遊拡散層227を初期化するものである。 The reset transistor 224 initializes the floating diffusion layer 227 according to the reset signal RST from the pixel drive circuit 252.
 容量225は、リセットトランジスタ224およびゲイン制御トランジスタ226の接続ノードと接地端子との間に挿入される。 The capacitance 225 is inserted between the connection node of the reset transistor 224 and the gain control transistor 226 and the ground terminal.
 ゲイン制御トランジスタ226は、画素駆動回路252からの制御信号FDGに従って、浮遊拡散層227の電圧に対するアナログゲインを制御するものである。浮遊拡散層227の電圧をアナログゲインにより低減して出力することにより、画素回路220の取扱い信号量、すなわち飽和信号量を拡大することができる。 The gain control transistor 226 controls the analog gain with respect to the voltage of the floating diffusion layer 227 according to the control signal FDG from the pixel drive circuit 252. By reducing the voltage of the floating diffusion layer 227 by analog gain and outputting it, the amount of signals handled by the pixel circuit 220, that is, the amount of saturation signals can be increased.
 浮遊拡散層227は、転送された電荷を蓄積して、電荷量に応じた電圧を生成するものである。 The floating diffusion layer 227 accumulates the transferred electric charge and generates a voltage according to the amount of electric charge.
 また、増幅回路230は、nMOSトランジスタ231および232と、容量233とを備える。nMOSトランジスタ231および232は、電源と接地端子との間において直列に接続される。電源側のnMOSトランジスタ231のゲートは、浮遊拡散層227に接続される。接地側のnMOSトランジスタ232のゲートには、所定のバイアス電圧VB2が印加される。 Further, the amplifier circuit 230 includes nMOS transistors 231 and 232 and a capacitance 233. The nMOS transistors 231 and 232 are connected in series between the power supply and the ground terminal. The gate of the nMOS transistor 231 on the power supply side is connected to the floating diffusion layer 227. A predetermined bias voltage VB2 is applied to the gate of the nMOS transistor 232 on the ground side.
 また、nMOSトランジスタ231および232の接続ノードは、容量233を介して差動入力回路320に接続される。差動入力回路320内の差動対のうち画素信号側のnMOSトランジスタ325のゲート-ソース間容量をCgsとすると、容量233の容量値は、ゲート-ソース間容量Cgsよりも、かなり大きな値に設定される。仮に浮遊拡散層227とnMOSトランジスタ325のゲートとを直接接続すると、ゲート-ソース間容量Cgsと浮遊拡散層227との間のカップリングにより、浮遊拡散層227の揺らぎが大きくなり、AD変換期間が長期化するおそれがある。しかし、容量233を追加することにより、このカップリングによる影響を緩和することができる。 Further, the connection nodes of the nMOS transistors 231 and 232 are connected to the differential input circuit 320 via the capacitance 233. Assuming that the gate-source capacitance of the nMOS transistor 325 on the pixel signal side of the differential pairs in the differential input circuit 320 is Cgs, the capacitance value of the capacitance 233 is considerably larger than the gate-source capacitance Cgs. Set. If the floating diffusion layer 227 and the gate of the nMOS transistor 325 are directly connected, the fluctuation of the floating diffusion layer 227 becomes large due to the coupling between the gate-source capacitance Cgs and the floating diffusion layer 227, and the AD conversion period becomes longer. It may take a long time. However, the effect of this coupling can be mitigated by adding capacity 233.
 なお、画素回路220および増幅回路230のそれぞれは、図7で説明した機能を持つのであれば、図9に例示した回路に限定されない。 Note that each of the pixel circuit 220 and the amplifier circuit 230 is not limited to the circuit illustrated in FIG. 9 as long as it has the functions described in FIG. 7.
 図10は、本技術の第1の実施の形態における画素内の素子のレイアウトの一例を示す平面図である。入射光の光軸をZ軸とし、Z軸に垂直な所定の軸をX軸とし、Z軸およびX軸に垂直な軸をY軸とする。 FIG. 10 is a plan view showing an example of the layout of the elements in the pixels according to the first embodiment of the present technology. The optical axis of the incident light is the Z axis, the predetermined axis perpendicular to the Z axis is the X axis, and the Z axis and the axis perpendicular to the X axis are the Y axes.
 受光面、すなわちXY平面において、N行およびM列の複数の光電変換素子222が二次元格子状に配列される。これらの光電変換素子222のY軸方向のサイズをY1とする。このXY平面においてM個の光電変換素子222は、X軸方向に沿って、隙間なく隣接して配列される。X軸方向に配列されたM個の光電変換素子222の集合と、それらに対応するデジタル信号の集合とを以下、「ライン」と称する。一方、Y軸方向に沿って、N個の光電変換素子222は、Y2の間隔を空けて配列される。言い換えれば、N個のラインは、Y2の間隔を空けて配列される。ここで、サイズY1と間隔Y2との間には、次の関係が成立するものとする。
  Y1≦Y2                    ・・・式1
On the light receiving surface, that is, the XY plane, a plurality of photoelectric conversion elements 222 in rows N and columns M are arranged in a two-dimensional lattice pattern. The size of these photoelectric conversion elements 222 in the Y-axis direction is defined as Y1. In this XY plane, the M photoelectric conversion elements 222 are arranged adjacent to each other along the X-axis direction without any gap. The set of M photoelectric conversion elements 222 arranged in the X-axis direction and the set of digital signals corresponding to them are hereinafter referred to as "lines". On the other hand, along the Y-axis direction, the N photoelectric conversion elements 222 are arranged with an interval of Y2. In other words, the N lines are arranged at intervals of Y2. Here, it is assumed that the following relationship is established between the size Y1 and the interval Y2.
Y1 ≤ Y2 ・ ・ ・ Equation 1
 同図においては、間隔Y2は、サイズY1と同じ値である。なお、式1に例示するように、間隔Y2をサイズY1より大きくすることもできる。間隔Y2をサイズY1より大きくする場合、間隔Y2は、Y1の整数倍に設定される。間隔Y2を大きくするほど、下側のADC310のY軸方向のサイズを大きくすることができるため、その分、ADC310のX軸方向のサイズを小さくしてX軸方向の画素を微細化することができる。 In the figure, the interval Y2 is the same value as the size Y1. As illustrated in Equation 1, the interval Y2 can be made larger than the size Y1. When the interval Y2 is larger than the size Y1, the interval Y2 is set to an integral multiple of Y1. As the interval Y2 is increased, the size of the lower ADC 310 in the Y-axis direction can be increased. Therefore, the size of the ADC 310 in the X-axis direction can be reduced accordingly to miniaturize the pixels in the X-axis direction. can.
 また、Y軸方向において、N個の光電変換素子222のそれぞれの間の隙間領域240には、トランジスタ配置領域241が設けられる。このトランジスタ配置領域241内には、所定数のトランジスタと、浮遊拡散層227と、容量233および225とが配置される。所定数のトランジスタは、排出トランジスタ221、リセットトランジスタ224およびゲイン制御トランジスタ226と、nMOSトランジスタ231、232、322、323および325とを含む。言い換えれば、トランジスタ配置領域241には、図8に例示した差動入力回路320内のトランジスタと、図9に例示した画素回路220および増幅回路230内のトランジスタとが配置される。これらのトランジスタは、図9を参照して説明したように、複数の光電変換素子222のいずれかにより生成された電荷量に応じた信号(画素信号や、その画素信号を増幅した信号)を生成する。また、トランジスタ配置領域241と光電変換素子222との間には、転送トランジスタ223が配置される。 Further, in the Y-axis direction, a transistor arrangement region 241 is provided in the gap region 240 between each of the N photoelectric conversion elements 222. A predetermined number of transistors, a floating diffusion layer 227, and capacitances 233 and 225 are arranged in the transistor arrangement region 241. A predetermined number of transistors include discharge transistors 221 and reset transistors 224 and gain control transistors 226, and nMOS transistors 231, 232, 322, 323 and 325. In other words, in the transistor arrangement region 241, the transistor in the differential input circuit 320 illustrated in FIG. 8 and the transistor in the pixel circuit 220 and the amplifier circuit 230 illustrated in FIG. 9 are arranged. As described with reference to FIG. 9, these transistors generate a signal (pixel signal or a signal obtained by amplifying the pixel signal) according to the amount of electric charge generated by any one of the plurality of photoelectric conversion elements 222. do. Further, a transfer transistor 223 is arranged between the transistor arrangement region 241 and the photoelectric conversion element 222.
 ここで、X軸方向およびY軸方向に沿って、N行、M列の光電変換素子222を隙間なく配列して、排出トランジスタ221などの各種のトランジスタや浮遊拡散層227を光電変換素子222の周囲に配置する比較例を想定する。この比較例では、光電変換素子222の受光面積は、トランジスタ数が多くなるほど狭くなってしまう。 Here, the N-row and M-column photoelectric conversion elements 222 are arranged without gaps along the X-axis direction and the Y-axis direction, and various transistors such as the discharge transistor 221 and the stray diffusion layer 227 are arranged in the photoelectric conversion element 222. Let's assume a comparative example of arranging around. In this comparative example, the light receiving area of the photoelectric conversion element 222 becomes narrower as the number of transistors increases.
 これに対して、同図に例示したように、Y軸方向において、N個の光電変換素子222を所定の間隔を空けて配列する構成では、トランジスタ等を隙間領域240に配置することができるため、比較例よりも受光面積を広くすることができる。受光面積の拡大により、画素の感度を向上させることができる。また、比較例よりもトランジスタを多く配置することができるため、画素回路220に加えて、増幅回路230などの追加の回路をさらに配置することができる。 On the other hand, as illustrated in the figure, in the configuration in which N photoelectric conversion elements 222 are arranged at predetermined intervals in the Y-axis direction, transistors and the like can be arranged in the gap area 240. , The light receiving area can be made wider than that of the comparative example. By expanding the light receiving area, the sensitivity of the pixel can be improved. Further, since more transistors can be arranged than in the comparative example, additional circuits such as an amplifier circuit 230 can be further arranged in addition to the pixel circuit 220.
 また、図10に示す例では、1つの画素Pは、光電変換素子222及び隙間領域240を含む。 Further, in the example shown in FIG. 10, one pixel P includes a photoelectric conversion element 222 and a gap region 240.
 [信号処理回路の構成例]
 図11は、本技術の第1の実施の形態における信号処理回路400の一構成例を示すブロック図である。この信号処理回路400は、複数のセレクタ405と、複数の演算回路410と、CDSフレームメモリ440と、TDIフレームメモリ450とを備える。
[Example of signal processing circuit configuration]
FIG. 11 is a block diagram showing a configuration example of the signal processing circuit 400 according to the first embodiment of the present technology. The signal processing circuit 400 includes a plurality of selectors 405, a plurality of arithmetic circuits 410, a CDS frame memory 440, and a TDI frame memory 450.
 セレクタ405は、クラスタ300の列ごと、言い換えれば、リピータ部360ごとに配置される。クラスタ300に2列のADC310が配列される場合、2列ごとにセレクタ405が配置される。また、演算回路410は、ADC310の列ごとに配置される。ADC310がM列である場合、M/2個のセレクタ405と、M個の演算回路410とが配置される。 The selector 405 is arranged for each column of the cluster 300, in other words, for each repeater unit 360. When two rows of ADC 310s are arranged in the cluster 300, a selector 405 is arranged in every two rows. Further, the arithmetic circuit 410 is arranged for each row of the ADC 310. When the ADC 310 has M columns, M / 2 selectors 405 and M arithmetic circuits 410 are arranged.
 前述したようにリピータ部360は、奇数列のデジタル信号と偶数列のデジタル信号とを順に出力する。 As described above, the repeater unit 360 outputs an odd-numbered row of digital signals and an even-numbered row of digital signals in order.
 セレクタ405は、制御回路256の制御に従って、デジタル信号の出力先を選択するものである。リピータ部360により奇数列が出力された場合にセレクタ405は、その奇数列に対応する演算回路410にデジタル信号を出力する。一方、偶数列が出力された場合にセレクタ405は、その偶数列に対応する演算回路410にデジタル信号を出力する。 The selector 405 selects the output destination of the digital signal according to the control of the control circuit 256. When an odd-numbered sequence is output by the repeater unit 360, the selector 405 outputs a digital signal to the arithmetic circuit 410 corresponding to the odd-numbered sequence. On the other hand, when an even-numbered sequence is output, the selector 405 outputs a digital signal to the arithmetic circuit 410 corresponding to the even-numbered sequence.
 演算回路410は、セレクタ405からのデジタル信号に対してCDS処理とTDI処理とを行うものである。 The arithmetic circuit 410 performs CDS processing and TDI processing on the digital signal from the selector 405.
 ここで、デジタル信号は、P相レベルとD相レベルとを含む。P相レベルは、画素回路220がリセット信号RSTにより初期化されたときのレベルを示す。一方、D相レベルは、転送信号TGにより電荷が転送されたときの露光量に応じたレベルを示す。P相レベルは、リセットレベルとも呼ばれ、D相レベルは、信号レベルとも呼ばれる。 Here, the digital signal includes a P-phase level and a D-phase level. The P-phase level indicates the level when the pixel circuit 220 is initialized by the reset signal RST. On the other hand, the D-phase level indicates a level according to the exposure amount when the electric charge is transferred by the transfer signal TG. The P-phase level is also called the reset level, and the D-phase level is also called the signal level.
 CDS処理において、M個の演算回路410は、P相レベルを配列したP相フレームをCDSフレームメモリ440に保持させる。そして、M個の演算回路410は、画素毎にP相レベルと、D相レベルとの差分を求め、差分データを配列したCDSフレームを生成する。一方、TDI処理において、M個の演算回路410は、CDS処理後のフレームをTDIフレームメモリ450に保持させ、積算したデータによりTDIフレームメモリ450を更新する。 In the CDS processing, the M arithmetic circuits 410 hold the P-phase frames in which the P-phase levels are arranged in the CDS frame memory 440. Then, the M arithmetic circuits 410 obtain the difference between the P-phase level and the D-phase level for each pixel, and generate a CDS frame in which the difference data is arranged. On the other hand, in the TDI processing, the M arithmetic circuits 410 hold the frames after the CDS processing in the TDI frame memory 450, and update the TDI frame memory 450 with the integrated data.
 また、M個の演算回路410は、CDSフレームと、TDI処理後のTDIフレームとを画像処理回路260に供給する。 Further, the M arithmetic circuits 410 supply the CDS frame and the TDI frame after the TDI processing to the image processing circuit 260.
 [演算回路の構成例]
 図12は、本技術の第1の実施の形態における演算回路410の一構成例を示す回路図である。この演算回路410は、TDI回路420およびCDS回路430を備える。TDI回路420は、バッファ421、セレクタ422、加算器423およびスイッチ424を備える。CDS回路430は、セレクタ431、バッファ432、セレクタ433、減算器434およびスイッチ435を備える。セレクタ422、431および433と、スイッチ424および425とのそれぞれの動作は、例えば、制御回路256により制御される。
[Configuration example of arithmetic circuit]
FIG. 12 is a circuit diagram showing a configuration example of the arithmetic circuit 410 according to the first embodiment of the present technology. The arithmetic circuit 410 includes a TDI circuit 420 and a CDS circuit 430. The TDI circuit 420 includes a buffer 421, a selector 422, an adder 423, and a switch 424. The CDS circuit 430 includes a selector 431, a buffer 432, a selector 433, a subtractor 434 and a switch 435. The operation of the selectors 422, 431 and 433 and the switches 424 and 425, respectively, is controlled by, for example, the control circuit 256.
 セレクタ431は、セレクタ405からのデジタル信号とTDIフレームメモリ450からのデジタル信号とのいずれかを選択してバッファ421に出力するものである。 The selector 431 selects either a digital signal from the selector 405 or a digital signal from the TDI frame memory 450 and outputs it to the buffer 421.
 バッファ421は、セレクタ431からの信号を遅延させて出力するものである。 The buffer 421 delays and outputs the signal from the selector 431.
 セレクタ422は、バッファ421からのデジタル信号と、10進数で「0」の値のデジタル信号とのいずれかを選択して加算器423に出力するものである。 The selector 422 selects either a digital signal from the buffer 421 or a digital signal having a decimal value of "0" and outputs it to the adder 423.
 加算器423は、セレクタ422からのデジタル信号とバッファ432からのデジタル信号とを加算するものである。この加算器423は、加算値を示すデジタル信号を積算データとしてスイッチ424に供給する。 The adder 423 adds the digital signal from the selector 422 and the digital signal from the buffer 432. The adder 423 supplies a digital signal indicating the added value to the switch 424 as integrated data.
 スイッチ424は、加算器423とTDIフレームメモリ450との間の経路を開閉するものである。 The switch 424 opens and closes the path between the adder 423 and the TDI frame memory 450.
 バッファ432は、CDSフレームメモリ440からの信号を遅延させて出力するものである。 The buffer 432 delays and outputs the signal from the CDS frame memory 440.
 セレクタ433は、バッファ432からのデジタル信号と、10進数で「0」の値のデジタル信号とのいずれかを選択して減算器434に出力するものである。 The selector 433 selects either a digital signal from the buffer 432 or a digital signal having a decimal value of "0" and outputs it to the subtractor 434.
 減算器434は、バッファ421からのデジタル信号とセレクタ433からのデジタル信号との差分を演算するものである。この減算器434は、差分を示すデジタル信号を差分データとしてスイッチ435に供給する。 The subtractor 434 calculates the difference between the digital signal from the buffer 421 and the digital signal from the selector 433. The subtractor 434 supplies a digital signal indicating the difference to the switch 435 as the difference data.
 スイッチ435は、減算器434とCDSフレームメモリ440との間の経路を開閉するものである。 The switch 435 opens and closes the path between the subtractor 434 and the CDS frame memory 440.
 同図に例示した構成により、CDS回路430は、CDS処理を行うことができる。また、TDI回路420は、TDI処理を行うことができる。 According to the configuration illustrated in the figure, the CDS circuit 430 can perform CDS processing. Further, the TDI circuit 420 can perform TDI processing.
 図13は、本技術の第1の実施の形態におけるTDI処理の一例を示す図である。例えば、CDSフレームメモリ440およびTDIフレームメモリ450が初期化され、最初にフレームF1が撮像され、続いてフレームF2、F3、F4、F5、F6、F7およびF8が順に撮像されたものとする。同図において、フレームF5以降は、省略されている。また、同図における矢印は、被写体の移動方向を示す。同図に例示するように、この被写体は、Y軸方向に沿って、行アドレスが大きくなる方向に1ラインずつ移動するものとする。同図におけるライン間の灰色の部分は、ライン間の隙間領域を示す。隙間領域は、1ライン分とする。 FIG. 13 is a diagram showing an example of TDI processing in the first embodiment of the present technology. For example, it is assumed that the CDS frame memory 440 and the TDI frame memory 450 are initialized, the frame F1 is first imaged, and then the frames F2, F3, F4, F5, F6, F7 and F8 are imaged in order. In the figure, frames F5 and later are omitted. The arrows in the figure indicate the moving direction of the subject. As illustrated in the figure, it is assumed that the subject moves one line at a time in the direction in which the row address increases along the Y-axis direction. The gray part between the lines in the figure shows the gap area between the lines. The gap area is for one line.
 信号処理回路400は、TDI処理において、CDS処理後のフレームF1のラインL1と、フレームF3のラインL2と、フレームF5のラインL3と、フレームF7のラインL4とを積算する。前述したように、被写体は1ラインずつ移動し、隙間領域が1ライン分であるため、積算対象の各ラインのパターンは、同一となる。信号処理回路400は、積算したラインをTDIフレームの最後のラインとして出力する。 In the TDI processing, the signal processing circuit 400 integrates the line L1 of the frame F1 after the CDS processing, the line L2 of the frame F3, the line L3 of the frame F5, and the line L4 of the frame F7. As described above, since the subject moves one line at a time and the gap area is one line, the pattern of each line to be integrated is the same. The signal processing circuit 400 outputs the integrated line as the last line of the TDI frame.
 また、信号処理回路400は、TDI処理において、CDS処理後のフレームF2のラインL1と、フレームF4のラインL2と、フレームF6のラインL3と、フレームF8のラインL4とを積算する。信号処理回路400は、積算したラインをTDIフレームの最後から2番目のラインとして出力する。他のラインについても同様に、フレームF3以降の4ラインの積算により生成される。 Further, in the TDI processing, the signal processing circuit 400 integrates the line L1 of the frame F2 after the CDS processing, the line L2 of the frame F4, the line L3 of the frame F6, and the line L4 of the frame F8. The signal processing circuit 400 outputs the integrated line as the penultimate line of the TDI frame. Similarly, the other lines are generated by integrating the four lines after the frame F3.
 被写体の移動速度が速い場合には、ブレを防止するために、露光時間を短くする必要がある。露光時間を短くすると、画像が暗くなるおそれがあるが、TDI処理を行うことにより、同じパターンの複数のラインを積算して明るさを向上させることができる。また、積算するライン数が多いほど、平滑化効果によりノイズが低減する。これらの明るさの向上とノイズ低減とにより、TDI処理を行わない場合と比較して、フレーム(すなわち、画像データ)の画質を向上させることができる。 When the moving speed of the subject is fast, it is necessary to shorten the exposure time in order to prevent blurring. If the exposure time is shortened, the image may become dark, but by performing the TDI process, it is possible to integrate a plurality of lines of the same pattern to improve the brightness. Further, as the number of integrated lines increases, noise is reduced due to the smoothing effect. By improving the brightness and reducing the noise, the image quality of the frame (that is, the image data) can be improved as compared with the case where the TDI processing is not performed.
 なお、信号処理回路400は、4つのラインを積算しているが、積算するライン数は、2以上であれば、4つに限定されない。また、信号処理回路400は、最初の8フレームについて先頭のラインから4ラインを積分しているが、この構成に限定されない。例えば、被写体の移動方向が逆の場合、信号処理回路400は、最初の8フレームについて最後のラインから4ラインを積分すればよい。 The signal processing circuit 400 integrates four lines, but the number of integrated lines is not limited to four as long as it is two or more. Further, the signal processing circuit 400 integrates four lines from the first line for the first eight frames, but the present invention is not limited to this configuration. For example, when the moving direction of the subject is opposite, the signal processing circuit 400 may integrate 4 lines from the last line for the first 8 frames.
 また、ライン間には1ライン分の隙間領域が存在するが、フレームF1、F3、F5およびF7のように、積算対象のフレームを1つ置きにすることにより、同一のパターンのラインを積算することができる。なお、ライン間の隙間領域を2ライン分や3ライン分にする場合、積算対象のフレームを2つ置きや、3つ置きにすればよい。 Further, although there is a gap area for one line between the lines, lines of the same pattern are integrated by setting every other frame to be integrated, such as frames F1, F3, F5 and F7. be able to. When the gap area between the lines is set to 2 lines or 3 lines, the frames to be integrated may be set to every 2 or 3 frames.
 [固体撮像素子の動作例]
 図14は、本技術の第1の実施の形態における固体撮像素子200の動作の一例を示すフローチャートの一例である。この動作は、例えば、フレームの撮像を行うための所定のアプリケーションが実行されたときに開始される。
[Operation example of solid-state image sensor]
FIG. 14 is an example of a flowchart showing an example of the operation of the solid-state image sensor 200 according to the first embodiment of the present technology. This operation is started, for example, when a predetermined application for imaging a frame is executed.
 固体撮像素子200内の画素駆動回路252は、全画素を駆動し、同時に露光を開始させる(ステップS901)。このように、全画素を同時に露光させる制御は、グローバルシャッター方式と呼ばれる。 The pixel drive circuit 252 in the solid-state image sensor 200 drives all the pixels and starts exposure at the same time (step S901). Such control of exposing all pixels at the same time is called a global shutter method.
 露光終了の直前にADC310は、P相レベルをAD変換する(ステップS902)。そして、露光終了時にADC310は、D相レベルをAD変換し、演算回路410は、CDS処理を行う(ステップS903)。 Immediately before the end of exposure, the ADC 310 AD-converts the P-phase level (step S902). Then, at the end of the exposure, the ADC 310 AD-converts the D-phase level, and the arithmetic circuit 410 performs the CDS process (step S903).
 画像処理回路260は、CDS処理後のフレームに対して所定の画像処理を行い(ステップS904)、演算回路410は、TDI処理を行う(ステップS905)。画像処理回路260は、TDI処理後のフレームに対して所定の画像処理を行い(ステップS906)、出力回路257は、処理結果を出力する(ステップS907)。ステップS907の後に固体撮像素子200は、1フレームを撮像する処理を終了する。2フレーム以上を連続して撮像する際には、ステップS901乃至S907が垂直同期信号VSYNCに同期して繰り返し実行される。 The image processing circuit 260 performs predetermined image processing on the frame after the CDS processing (step S904), and the arithmetic circuit 410 performs TDI processing (step S905). The image processing circuit 260 performs predetermined image processing on the frame after the TDI processing (step S906), and the output circuit 257 outputs the processing result (step S907). After step S907, the solid-state image sensor 200 ends the process of imaging one frame. When two or more frames are continuously imaged, steps S901 to S907 are repeatedly executed in synchronization with the vertical synchronization signal VSYNC.
 このように、本技術の第1の実施の形態によれば、Y軸方向に沿って、一定の間隔を空けて複数の光電変換素子222を配列し、それらの間にトランジスタを配置したため、間隔を空けない場合よりも光電変換素子222の受光面積を広くすることができる。これにより、画素の感度を向上させることができる。 As described above, according to the first embodiment of the present technique, a plurality of photoelectric conversion elements 222 are arranged at regular intervals along the Y-axis direction, and transistors are arranged between them. The light receiving area of the photoelectric conversion element 222 can be made wider than that in the case where the light receiving area is not opened. Thereby, the sensitivity of the pixel can be improved.
 [カラーセンサ]
 図15は、本技術の第1の実施の形態における撮像装置100の構成の一例を示す図である。
[Color sensor]
FIG. 15 is a diagram showing an example of the configuration of the image pickup apparatus 100 according to the first embodiment of the present technology.
 図15に示す撮像装置100は、カラーフィルタを有するTDIカラーセンサである。また、撮像装置100は、例えば、TDIリニアイメージセンサである。カラーフィルタは、所定の色に応じた波長帯の光を通過させる。TDI処理のデータの加算は、色ごとに行われる。 The image pickup apparatus 100 shown in FIG. 15 is a TDI color sensor having a color filter. Further, the image pickup apparatus 100 is, for example, a TDI linear image sensor. The color filter passes light in a wavelength band corresponding to a predetermined color. The data of TDI processing is added for each color.
 図15に示す画素Pは、図10に示す画素Pに対応する。画素Pは、赤色フィルタ(R)に配置される画素PR、緑色フィルタ(G)に配置される画素PG及び青色フィルタ(B)に配置される画素PBを含む。 The pixel P shown in FIG. 15 corresponds to the pixel P shown in FIG. The pixel P includes a pixel PR arranged in the red filter (R), a pixel PG arranged in the green filter (G), and a pixel PB arranged in the blue filter (B).
 図15に示すカラーフィルタは、色パターンが色群配列である。カラーフィルタは、例えば、赤色フィルタ、緑色フィルタ及び青色フィルタのそれぞれが複数隣接して配置される赤色フィルタ群、緑色フィルタ群及び青色フィルタ群を含む。 In the color filter shown in FIG. 15, the color pattern is a color group array. The color filter includes, for example, a red filter group, a green filter group, and a blue filter group in which a plurality of red filters, green filters, and blue filters are arranged adjacent to each other.
 なお、図15に示す例では、同じ色の画素PがX方向及びY方向にそれぞれ3つ配置されている。しかし、画素Pの配置数はこれに限られない。撮像装置100がリニアセンサである場合、例えば、1000又は2000等の画素PがX方向に並べて配置される。また、例えば、1色あたり16の画素PがY方向に並べて配置される。 In the example shown in FIG. 15, three pixels P of the same color are arranged in the X direction and the Y direction, respectively. However, the number of pixels P arranged is not limited to this. When the image pickup apparatus 100 is a linear sensor, for example, pixels P such as 1000 or 2000 are arranged side by side in the X direction. Further, for example, 16 pixels P per color are arranged side by side in the Y direction.
 1つの画素Pには、光電変換素子222が含まれる。光電変換素子222は、複数の画素Pのそれぞれに設けられ、相対的に移動する被写体511の移動速度に応じた期間内に光電変換された電気信号を出力する。なお、「相対的な移動方向」は、図2を参照して説明した場合に限られず、被写体511を固定して撮像装置100を移動する場合を含む。 One pixel P includes a photoelectric conversion element 222. The photoelectric conversion element 222 is provided in each of the plurality of pixels P, and outputs an electrical signal photoelectrically converted within a period corresponding to the moving speed of the relatively moving subject 511. The "relative movement direction" is not limited to the case described with reference to FIG. 2, and includes the case where the subject 511 is fixed and the image pickup apparatus 100 is moved.
 ADC310は、複数の画素Pのそれぞれごとに配置され、電気信号をデジタル信号に変換する。 The ADC 310 is arranged for each of the plurality of pixels P and converts an electric signal into a digital signal.
 画素エリア外に配置された演算回路(演算部)410は、電気信号を複数の画素Pの色ごとに積算する。より詳細には、演算回路410は、ADC310により変換されたデジタル信号を色ごとに積算する。従って、図5に示すように、信号処理回路400内の演算回路410は、画素AD変換部254内のADC310から出力されたデジタル信号を色ごとに積算する。 The arithmetic circuit (calculation unit) 410 arranged outside the pixel area integrates electric signals for each color of a plurality of pixels P. More specifically, the arithmetic circuit 410 integrates the digital signals converted by the ADC 310 for each color. Therefore, as shown in FIG. 5, the arithmetic circuit 410 in the signal processing circuit 400 integrates the digital signals output from the ADC 310 in the pixel AD conversion unit 254 for each color.
 撮像装置100は、図3を参照して説明したように、積層構造を有する。ADC310は、光電変換素子222と積層方向に重なる位置に配置される。より詳細には、光電変換素子222の直下に差動入力回路320及びラッチ回路350が配置される。差動入力回路320は、画素エリア外に配置されたDAC251からスロープ信号を受け取る。これにより、ADC310は、シングルスロープAD変換を実行する。デジタル値は、ラッチ回路350に保持され、信号処理回路400等のロジック回路へ毎H転送される。 The image pickup apparatus 100 has a laminated structure as described with reference to FIG. The ADC 310 is arranged at a position where it overlaps with the photoelectric conversion element 222 in the stacking direction. More specifically, the differential input circuit 320 and the latch circuit 350 are arranged directly below the photoelectric conversion element 222. The differential input circuit 320 receives a slope signal from the DAC 251 arranged outside the pixel area. As a result, the ADC 310 performs the single slope AD conversion. The digital value is held in the latch circuit 350 and transferred every H to a logic circuit such as the signal processing circuit 400.
 次に、画素Pおよびカラーフィルタの色ごとの配置の詳細について説明する。 Next, the details of the arrangement of the pixel P and the color filter for each color will be described.
 互いに異なる色の光を光電変換する2つの画素Pは、被写体511の相対的な移動方向(Y方向)に沿って、隙間無く配置される。図15に示す例では、Y方向に沿って隣接する画素PRと画素PGとは、隙間なく接するように配置される。Y方向に沿って隣接する画素PGと画素PBとは、隙間なく接するように配置される。これにより、画素PRと画素PGとの間、及び、画素PGと画素PBとの間における色間ギャップがほとんどない。この結果、振動による画質の劣化を抑制することができる。すなわち、撮像装置100および電子機器1の振動耐性を向上させることができる。なお、振動耐性の詳細については、図16A~図19を参照して、後で説明する。 The two pixels P that photoelectrically convert light of different colors are arranged without a gap along the relative moving direction (Y direction) of the subject 511. In the example shown in FIG. 15, the pixel PR and the pixel PG that are adjacent to each other along the Y direction are arranged so as to be in contact with each other without a gap. The pixel PG and the pixel PB that are adjacent to each other along the Y direction are arranged so as to be in contact with each other without a gap. As a result, there is almost no intercolor gap between the pixel PR and the pixel PG and between the pixel PG and the pixel PB. As a result, deterioration of image quality due to vibration can be suppressed. That is, the vibration resistance of the image pickup apparatus 100 and the electronic device 1 can be improved. The details of the vibration resistance will be described later with reference to FIGS. 16A to 19.
 図15に示す例では、第1色の光を光電変換する1以上の画素Pを含む第1画素領域と、第1色とは異なる第2色の光を光電変換する1以上の画素Pを含む第2画素領域と、第1色及び第2色とは異なる第3色の光を光電変換する1以上の画素Pを含む第3画素領域と、が被写体511の相対的な移動方向(Y方向)に沿って、隙間無く配置される。 In the example shown in FIG. 15, a first pixel region including one or more pixels P that photoelectrically convert light of the first color and one or more pixels P that photoelectrically convert light of a second color different from the first color are formed. The relative movement direction (Y) of the subject 511 is the second pixel region including the second pixel region and the third pixel region including one or more pixels P that photoelectrically convert the light of the first color and the third color different from the second color. It is arranged without a gap along the direction).
 なお、第1色、第2色及び第3色は、例えば、それぞれ赤色、緑色及び青色であるが、色の種類及び順番はこれに限られない。第1画素領域、第2画素領域及び第3画素領域は、例えば、それぞれ1以上の赤色の画素PR、1以上の緑色の画素PG及び1以上の青色の画素PBが配置される領域であるが、色の種類及び順番はこれに限られない。 The first color, the second color, and the third color are, for example, red, green, and blue, respectively, but the type and order of the colors are not limited to this. The first pixel area, the second pixel area, and the third pixel area are, for example, areas in which one or more red pixel PRs, one or more green pixel PGs, and one or more blue pixel PBs are arranged, respectively. , The type and order of colors are not limited to this.
 第1画素領域、第2画素領域、及び第3画素領域のそれぞれは、被写体511の相対的な移動方向である第1方向(Y方向)に1以上の画素Pを含み、かつ第1方向に交差する第2方向(X方向)に1以上の画素Pを含む。 Each of the first pixel region, the second pixel region, and the third pixel region includes one or more pixels P in the first direction (Y direction), which is the relative movement direction of the subject 511, and is in the first direction. One or more pixels P are included in the intersecting second direction (X direction).
 各色の画素Pは、色群配列により配置される。すなわち、第1画素領域、第2画素領域、及び第3画素領域は、X方向に混在されずに配置される。第1画素領域及び第2画素領域は、Y方向に隙間無く配置される。第2画素領域及び第3画素領域は、Y方向に隙間無く配置される。 Pixels P of each color are arranged according to a color group array. That is, the first pixel region, the second pixel region, and the third pixel region are arranged without being mixed in the X direction. The first pixel area and the second pixel area are arranged without a gap in the Y direction. The second pixel area and the third pixel area are arranged without a gap in the Y direction.
 画素Pは、光電変換する光の波長帯に対応するカラーフィルタを有する。互いに異なる色に対応する2つのカラーフィルタは、被写体511の相対的な移動方向に沿って、隙間無く配置される。 Pixel P has a color filter corresponding to the wavelength band of light to be photoelectrically converted. The two color filters corresponding to different colors are arranged without gaps along the relative moving direction of the subject 511.
 第1画素領域は、第1色の光を透過する第1カラーフィルタを有する1以上の画素Pを有する。第2画素領域は、第2色の光を透過する第2カラーフィルタを有する1以上の画素Pを有する。第3画素領域は、第3色の光を透過する第3カラーフィルタを有する1以上の画素Pを有する。第1カラーフィルタ、第2カラーフィルタ、及び第3カラーフィルタは、被写体511の相対的な移動方向であるY方向に沿って、隙間無く配置される。 The first pixel region has one or more pixels P having a first color filter that transmits light of the first color. The second pixel region has one or more pixels P having a second color filter that transmits light of the second color. The third pixel region has one or more pixels P having a third color filter that transmits light of the third color. The first color filter, the second color filter, and the third color filter are arranged without gaps along the Y direction, which is the relative movement direction of the subject 511.
 また、第1カラーフィルタ、第2カラーフィルタ、及び第3カラーフィルタは、Y方向に交差するX方向に混在されずに配置される。第1カラーフィルタ及び第2カラーフィルタは、Y方向に隙間無く配置される。第2カラーフィルタ及び第3カラーフィルタは、Y方向に隙間無く配置される。 Further, the first color filter, the second color filter, and the third color filter are arranged without being mixed in the X direction intersecting the Y direction. The first color filter and the second color filter are arranged without a gap in the Y direction. The second color filter and the third color filter are arranged without a gap in the Y direction.
 [振動耐性]
 次に、画素Pの色間ギャップと振動耐性との関係について説明する。
[Vibration resistance]
Next, the relationship between the intercolor gap of the pixel P and the vibration resistance will be described.
 図16Aは、色間ギャップが大きい場合における振動の影響を説明する図である。図16Bは、色間ギャップが小さい場合における振動の影響を説明する図である。 FIG. 16A is a diagram illustrating the effect of vibration when the color gap is large. FIG. 16B is a diagram illustrating the effect of vibration when the color gap is small.
 図16Aは、赤、緑及び青の単色用のリニアセンサを用いて、被写体を別時間にスキャンして合成することを仮定した例を示す。この場合、画像の左右の読み位置(X方向の位置)の振動Vは、赤、緑及び青の色間で相関がほとんどない。従って、合成画像には、色ごとの振動Vの差に応じた色ずれが生じてしまう。 FIG. 16A shows an example assuming that a subject is scanned and synthesized at different times using a linear sensor for single colors of red, green, and blue. In this case, the vibration V at the left and right reading positions (positions in the X direction) of the image has almost no correlation between the red, green, and blue colors. Therefore, in the composite image, color shift occurs according to the difference in vibration V for each color.
 図16Bは、赤、緑及び青の単色用のリニアセンサを用いて、色間でスキャン方向の位置(Y方向の位置)がほぼ同じであることを仮定した例を示す。この場合、各色で画像の左右の読み位置の振動Vはほぼ同じである。すなわち、色ごとの振動Vの相関が強い。従って、合成画像には、色ずれがほぼない。 FIG. 16B shows an example in which it is assumed that the positions in the scanning direction (positions in the Y direction) are almost the same between the colors using the linear sensors for red, green, and blue monochromatic colors. In this case, the vibration V at the left and right reading positions of the image is almost the same for each color. That is, the correlation of vibration V for each color is strong. Therefore, there is almost no color shift in the composite image.
 TDIにおける画素Pの色間ギャップは、図16A及び図16Bと同様に考えることができる。すなわち、画素Pの色間ギャップが小さいほど、左右の読み位置の振動Vの相関が強くなる。これにより、合成画像の色ずれが小さくなる。この結果、振動による画質の劣化を抑制することができる。 The intercolor gap of the pixel P in TDI can be considered in the same manner as in FIGS. 16A and 16B. That is, the smaller the intercolor gap of the pixel P, the stronger the correlation between the vibration Vs at the left and right reading positions. As a result, the color shift of the composite image is reduced. As a result, deterioration of image quality due to vibration can be suppressed.
 図17は、色間ギャップGCを説明する図である。図17は、一例として、赤色用の画素PR及び緑色用の画素PGを示す。 FIG. 17 is a diagram illustrating the intercolor gap GC. FIG. 17 shows a pixel PR for red and a pixel PG for green as an example.
 色間ギャップGCは、赤色フィルタのカラーフィルタ(CF)端と緑色フィルタのCF端との間の距離であるCF端間距離DCFから、同色画素距離DPを引いた値である。同色画素距離DPは、画素ピッチと同色TDI段数との積である。画素ピッチは、1つの画素PのY方向の距離を示す。同色TDI段数は、並べて配置された同色の画素PのY方向の段数であり、図17に示す例では4段である。 The intercolor gap GC is a value obtained by subtracting the same color pixel distance DP from the CF end distance DCF, which is the distance between the color filter (CF) end of the red filter and the CF end of the green filter. The same-color pixel distance DP is the product of the pixel pitch and the number of same-color TDI stages. The pixel pitch indicates the distance of one pixel P in the Y direction. The number of TDI stages of the same color is the number of stages of the pixels P of the same color arranged side by side in the Y direction, and is 4 in the example shown in FIG.
 図18は、色間ギャップGCと振動の関係を説明する図である。図18では、例えば、TDI画素の読み出し間隔を1μsとし、赤の1画素目と緑の1画素目の色間の読み出し間隔を10μsとする。 FIG. 18 is a diagram for explaining the relationship between the intercolor gap GC and vibration. In FIG. 18, for example, the read interval of the TDI pixel is 1 μs, and the read interval between the colors of the first red pixel and the first green pixel is 10 μs.
 図18に示す高周波の振動ノイズNH及び低周波の振動ノイズNLは、1/fに従うモデルとする。すなわち、図18に示すように、振幅の大きい振動ノイズNLは周波数が低く、振幅の小さい振動ノイズNHは周波数が高い。振動ノイズは、色間で受けた横方向(X方向)の振動の単純差分と定義する。また、TDI画素はその平均をとる行為とみなせるので、ラプラス変換で伝達関数を計算し、ノイズスペクトラムへの反応を定量化することができる。 The high-frequency vibration noise NH and the low-frequency vibration noise NL shown in FIG. 18 are models that follow 1 / f. That is, as shown in FIG. 18, the vibration noise NL having a large amplitude has a low frequency, and the vibration noise NH having a small amplitude has a high frequency. Vibration noise is defined as a simple difference of lateral (X direction) vibration received between colors. Moreover, since the TDI pixel can be regarded as the act of averaging the TDI pixel, the transfer function can be calculated by the Laplace transform and the reaction to the noise spectrum can be quantified.
 図19は、伝達関数を示すグラフである。 FIG. 19 is a graph showing the transfer function.
 振動ノイズスペクトラムNSは、図18を参照して説明したように、周波数が低い場合は振幅が大きく、周波数が高い場合は振幅が小さい、一般的に振動のスペクトルを示す。 As explained with reference to FIG. 18, the vibration noise spectrum NS generally shows a vibration spectrum in which the amplitude is large when the frequency is low and the amplitude is small when the frequency is high.
 伝達関数TF1は、赤の1画素目と緑の1画素目との色間の読み出し間隔が10μsであり、1つの画素の読み出し間隔が1μsであり、4画素を加算する場合の非TDIの伝達関数である。伝達関数TF2は、赤の1画素目と緑の1画素目との色間の読み出し間隔が10μsであり、1つの画素の読み出し間隔が1μsであり、4画素を加算する場合のTDIの伝達関数である。伝達関数TF2は、赤の1画素目と緑の1画素目との色間の読み出し間隔が5μsであり、1つの画素の読み出し間隔が1μsであり、4画素を加算する場合のTDIの伝達関数である。 In the transmission function TF1, the read interval between the colors of the first red pixel and the first green pixel is 10 μs, the read interval of one pixel is 1 μs, and the non-TDI transmission when four pixels are added. It is a function. The transmission function TF2 is a TDI transmission function when the read interval between the colors of the first red pixel and the first green pixel is 10 μs, the read interval of one pixel is 1 μs, and four pixels are added. Is. The transmission function TF2 is a TDI transmission function when the read interval between the colors of the first red pixel and the first green pixel is 5 μs, the read interval of one pixel is 1 μs, and four pixels are added. Is.
 伝達関数は、周波数によって波打つ振る舞いを示す。伝達関数のゼロの値は、赤の1画素目と緑の1画素目とで、例えば、それぞれ振動の極大値をとる周波数である場合、振動の差分がゼロになることを示す。すなわち、赤の1画素目と緑の1画素目との間の読み出しの時間差と、振動の周波数と、の対応関係により振動の残存ノイズがゼロになる。例えば、周波数がずれて振動の差分がゼロにならない場合、伝達関数は有限の値になる。伝達関数は、周波数の倍数によって、周期的にゼロになる。 The transfer function shows wavy behavior depending on the frequency. A value of zero in the transfer function indicates that the difference in vibration is zero between the first pixel in red and the first pixel in green, for example, when the frequencies have maximum vibration values. That is, the residual noise of vibration becomes zero due to the correspondence between the read time difference between the first red pixel and the first green pixel and the frequency of vibration. For example, if the frequency shifts and the vibration difference does not become zero, the transfer function becomes a finite value. The transfer function periodically becomes zero, depending on the multiple of the frequency.
 最終的な残存ノイズは、振動ノイズスペクトラムNSと伝達関数TF1~TF3との掛け算の積分(面積)となる。例えば、面積の単位を任意として、振動ノイズスペクトラムNSと伝達関数TF1~TF3との掛け算の面積は、それぞれ29161.9、7495.6及び4000である。伝達関数TF1と伝達関数TF2とを比較すると、TDI処理により4画素で平均化されることにより、ノイズを圧縮することができることがわかる。また、伝達関数TF2と伝達関数TF3とを比較すると、赤の1画素目と緑の1画素目との色間の読み出し間隔が小さくなるほど、さらにノイズが小さくなることがわかる。従って、色間ギャップを小さくすることにより、振動耐性が向上することがわかる。 The final residual noise is the integral (area) of the product of the vibration noise spectrum NS and the transfer functions TF1 to TF3. For example, the unit of the area is arbitrary, and the area of the product of the vibration noise spectrum NS and the transfer functions TF1 to TF3 is 29161.9, 7945.6, and 4000, respectively. Comparing the transfer function TF1 and the transfer function TF2, it can be seen that the noise can be compressed by averaging with 4 pixels by the TDI process. Further, when the transfer function TF2 and the transfer function TF3 are compared, it can be seen that the smaller the read interval between the colors of the first red pixel and the first green pixel, the smaller the noise. Therefore, it can be seen that the vibration resistance is improved by reducing the intercolor gap.
 以上のように、第1の実施の形態によれば、TDIカラーセンサである撮像装置100では、異なる色用の2つの画素Pが隙間なく接するように配置されている。これにより、色間ギャップGCを抑制し、振動による画質の劣化を抑制することができる。 As described above, according to the first embodiment, in the image pickup apparatus 100 which is a TDI color sensor, two pixels P for different colors are arranged so as to be in contact with each other without a gap. As a result, the intercolor gap GC can be suppressed, and deterioration of image quality due to vibration can be suppressed.
 なお、カラーフィルタの配置は、必ずしも図15に示す例に限られない。例えば、赤、青、緑のうち一色をさらに追加したカラーフィルタが用いられてもよい。 The arrangement of the color filters is not necessarily limited to the example shown in FIG. For example, a color filter in which one of red, blue, and green is further added may be used.
 [第1比較例]
 図20は、第1比較例における撮像装置100の構成の一例を示す図である。第1変形例は、CMOS(Complementary Metal Oxide Semiconductor)構造に代えてCCD(Charge Coupled Device)構造が用いられる点で、第1の実施の形態とは異なっている。
[First Comparative Example]
FIG. 20 is a diagram showing an example of the configuration of the image pickup apparatus 100 in the first comparative example. The first modification is different from the first embodiment in that a CCD (Charge Coupled Device) structure is used instead of the CMOS (Complementary Metal Oxide Semiconductor) structure.
 図20に示す例では、CCD構造が用いられるため、例えば、赤色用の画素PRで生成された電荷を取り出すための回路が、赤色用の画素PRと緑色用の画素PGとの間に配置される。これにより、画素Pの色間ギャップGCが大きくなってしまう。この結果、被写体の進行方向(Y方向)に垂直方向(X方向)の振動により、合成画像の正確性が劣化する。すなわち、振動により画質が劣化してしまう。CCD構造では、カラー画素群間に出力回路のスペースを設ける必要があるために、色間ギャップGCを小さくすることが困難である。なお、図20に示す例では、青色用の画素PBは省略されているが、緑色用の画素PGと青色用の画素PBとの間の色間ギャップGCも同様である。 In the example shown in FIG. 20, since the CCD structure is used, for example, a circuit for extracting the electric charge generated by the red pixel PR is arranged between the red pixel PR and the green pixel PG. To. As a result, the intercolor gap GC of the pixel P becomes large. As a result, the accuracy of the composite image deteriorates due to vibration in the direction (X direction) perpendicular to the traveling direction (Y direction) of the subject. That is, the image quality deteriorates due to vibration. In the CCD structure, it is difficult to reduce the intercolor gap GC because it is necessary to provide a space for the output circuit between the color pixel groups. In the example shown in FIG. 20, the blue pixel PB is omitted, but the intercolor gap GC between the green pixel PG and the blue pixel PB is also the same.
 これに対して、第1の実施の形態における撮像装置100は、CMOS構造を有し、画素PごとにADC310が配置される。これにより、演算回路410(信号処理回路400)におけるTDI処理をデジタル信号の加算とすることができる。この結果、CCD構造における出力回路のスペースが不要になる。従って、画素Pの色間ギャップGC(カラー画素群間ギャップ)を抑制することができ、振動による画質の劣化を抑制することができる。 On the other hand, the image pickup apparatus 100 in the first embodiment has a CMOS structure, and an ADC 310 is arranged for each pixel P. As a result, the TDI processing in the arithmetic circuit 410 (signal processing circuit 400) can be the addition of digital signals. As a result, the space of the output circuit in the CCD structure becomes unnecessary. Therefore, the intercolor gap GC (gap between color pixel groups) of the pixel P can be suppressed, and the deterioration of the image quality due to vibration can be suppressed.
 [第2比較例]
 図21は、第2変形例における撮像装置100の構成の一例を示す図である。第2変形例は、ADC310が画素Pごとではなく、複数の画素Pを含むカラム(画素列)ごとに設けられる点で、第1の実施の形態とは異なっている。
[Second comparative example]
FIG. 21 is a diagram showing an example of the configuration of the image pickup apparatus 100 in the second modification. The second modification is different from the first embodiment in that the ADC 310 is provided not for each pixel P but for each column (pixel string) including a plurality of pixels P.
 CMOS構造でTDI処理を実現する場合、列ごとにADC310が配置されるカラムADC型も考えられる。この場合、信号線は、例えば、図21の紙面下方に向かって信号線電圧を出力するための信号線を出すことが考えられる。これにより、第1の実施の形態と同様に、色間ギャップを抑制することができる。しかし、信号線の配線を配置する必要があるため、開口率が低下してしまう。図21に示す例では、信号線は、他の色の画素Pの上空(Z方向)に配置される。 When realizing TDI processing with a CMOS structure, a column ADC type in which ADC 310 is arranged for each column is also conceivable. In this case, for example, it is conceivable that the signal line emits a signal line for outputting the signal line voltage toward the lower side of the paper surface of FIG. 21. Thereby, the intercolor gap can be suppressed as in the first embodiment. However, since it is necessary to arrange the wiring of the signal line, the aperture ratio is lowered. In the example shown in FIG. 21, the signal line is arranged above the pixels P of other colors (Z direction).
 これに対して、第1の実施の形態では、信号線を配置することによる開口率の低下を抑制することができ、光電変換素子222の面積の低下を抑制することができる。カラムADC型も、色間ギャップを抑制することができ、振動による画質の劣化を抑制することができる。しかし、開口率等の画素特性の観点からは、画素PごとにADC310が配置される方がより好ましい。 On the other hand, in the first embodiment, it is possible to suppress a decrease in the aperture ratio due to the arrangement of the signal line, and it is possible to suppress a decrease in the area of the photoelectric conversion element 222. The column ADC type can also suppress the intercolor gap and suppress the deterioration of image quality due to vibration. However, from the viewpoint of pixel characteristics such as aperture ratio, it is more preferable that the ADC 310 is arranged for each pixel P.
 <第2の実施の形態>
 図22は、本技術の第2の実施の形態における撮像装置100の構成の一例を示す図である。第2の実施の形態は、カラーフィルタの色パターンがベイヤ配列である点で、第1の実施の形態とは異なっている。
<Second Embodiment>
FIG. 22 is a diagram showing an example of the configuration of the image pickup apparatus 100 according to the second embodiment of the present technology. The second embodiment is different from the first embodiment in that the color pattern of the color filter is a bayer array.
 図22に示すカラーフィルタは、Y方向に沿って、1つの画素Pごとに画素Pの色が変化する。すなわち、被写体511の移動方向に沿って隣接する2つの画素Pは、互いに異なる色の光を受光する。 In the color filter shown in FIG. 22, the color of the pixel P changes for each pixel P along the Y direction. That is, the two pixels P adjacent to each other along the moving direction of the subject 511 receive light of different colors.
 第1画素領域、第2画素領域、及び第3画素領域は、Y方向及びX方向に混在されて配置される。第1画素領域及び第2画素領域は、Y方向に隙間無く配置される。第2画素領域及び第3画素領域は、Y方向に隙間無く配置される。より詳細には、図22に示すように、第1画素領域、第2画素領域、及び第3画素領域は、ベイヤ配列で配置される。 The first pixel area, the second pixel area, and the third pixel area are arranged in a mixed manner in the Y direction and the X direction. The first pixel area and the second pixel area are arranged without a gap in the Y direction. The second pixel area and the third pixel area are arranged without a gap in the Y direction. More specifically, as shown in FIG. 22, the first pixel region, the second pixel region, and the third pixel region are arranged in a bayer array.
 また、第1カラーフィルタ、第2カラーフィルタ、及び第3カラーフィルタは、Y方向及びX方向に混在されて配置される。
 第1カラーフィルタ及び第2カラーフィルタは、Y方向に隙間無く配置される。第2カラーフィルタ及び第3カラーフィルタは、Y方向に隙間無く配置される。より詳細には、図22に示すように、第1カラーフィルタ、第2カラーフィルタ、及び第3カラーフィルタは、ベイヤ配列で配置される。
Further, the first color filter, the second color filter, and the third color filter are arranged in a mixed manner in the Y direction and the X direction.
The first color filter and the second color filter are arranged without a gap in the Y direction. The second color filter and the third color filter are arranged without a gap in the Y direction. More specifically, as shown in FIG. 22, the first color filter, the second color filter, and the third color filter are arranged in a bayer array.
 色間ギャップがほぼゼロであっても、色ごとにY方向の位置が異なる場合、各色で受ける振動の影響は必ずしも同じではない。図15に示す色群配列において、例えば、赤色用の画素PRのラインの撮像タイミングで振動を受け、その後に、緑色用の画素PG及び青色用の画素PBのラインの撮像タイミングとなる場合が考えられる。この場合、色ごとに受ける振動の相関が弱くなってしまう。 Even if the intercolor gap is almost zero, if the position in the Y direction is different for each color, the effect of vibration on each color is not necessarily the same. In the color group arrangement shown in FIG. 15, for example, there is a case where vibration is received at the imaging timing of the red pixel PR line, and then the imaging timing of the green pixel PG and the blue pixel PB line. Be done. In this case, the correlation of vibrations received for each color is weakened.
 これに対して、ベイヤ配列では、或る画素Pの次のラインには、異なる色用の画素Pが配置されている。これにより、色ごとの撮像タイミングの時間差を短くすることができる。この結果、色ごとに受ける振動の相関をさらに強くすることができ、色ずれ等の振動による画質の劣化をさらに抑制することができる。従って、色ずれ重視の際のオプションとして、ベイヤ配列が選択可能である。 On the other hand, in the bayer array, pixels P for different colors are arranged in the line next to a certain pixel P. Thereby, the time difference of the imaging timing for each color can be shortened. As a result, the correlation of vibrations received for each color can be further strengthened, and deterioration of image quality due to vibrations such as color shift can be further suppressed. Therefore, the bayer arrangement can be selected as an option when emphasizing color shift.
 また、通常、CCD構造のTDIセンサでは、図20を参照して説明したように、物理転送により、電荷が発生した直後に積算する必要があり、回路配置の制約からベイヤ配列で画素を配置することが困難である。 Further, usually, in a TDI sensor having a CCD structure, as described with reference to FIG. 20, it is necessary to integrate the charges immediately after the electric charges are generated by physical transfer, and the pixels are arranged in a Bayer arrangement due to the limitation of the circuit arrangement. Is difficult.
 これに対して、第2の実施の形態では、画素PごとにADC310が配置され、図7を参照して説明したようにラッチ回路350が時刻コードを保持するため、積算処理は後で行うことができる。この結果、ベイヤ配列のカラーフィルタを選択することができる。 On the other hand, in the second embodiment, the ADC 310 is arranged for each pixel P, and the latch circuit 350 holds the time code as described with reference to FIG. 7, so that the integration process is performed later. Can be done. As a result, the color filter of the bayer array can be selected.
 なお、本技術は以下のような構成を取ることができる。
 (1)複数の画素のそれぞれに設けられ、相対的に移動する被写体の移動速度に応じた期間内に光電変換された電気信号を出力する光電変換部と、
 前記電気信号を前記複数の画素の色ごとに積算する演算部と、を備え、
 互いに異なる色の光を光電変換する2つの前記画素は、前記被写体の相対的な移動方向に沿って、隙間無く配置される、撮像装置。
 (2)第1色の光を光電変換する1以上の前記画素を含む第1画素領域と、前記第1色とは異なる第2色の光を光電変換する1以上の前記画素を含む第2画素領域と、前記第1色及び前記第2色とは異なる第3色の光を光電変換する1以上の前記画素を含む第3画素領域と、が前記被写体の相対的な移動方向に沿って、隙間無く配置される、(1)に記載の撮像装置。
 (3)前記第1画素領域、前記第2画素領域、及び前記第3画素領域のそれぞれは、前記被写体の相対的な移動方向である第1方向に1以上の前記画素を含み、かつ前記第1方向に交差する第2方向に1以上の前記画素を含む、(2)に記載の撮像装置。
 (4)前記第1画素領域、前記第2画素領域、及び前記第3画素領域は、前記第2方向に混在されずに配置され、
 前記第1画素領域及び前記第2画素領域は、前記第1方向に隙間無く配置され、
 前記第2画素領域及び前記第3画素領域は、前記第1方向に隙間無く配置される、(3)に記載の撮像装置。
 (5)前記第1画素領域、前記第2画素領域、及び前記第3画素領域は、前記第1方向及び前記第2方向に混在されて配置され、
 前記第1画素領域及び前記第2画素領域は、前記第1方向に隙間無く配置され、
 前記第2画素領域及び前記第3画素領域は、前記第1方向に隙間無く配置される、(3)に記載の撮像装置。
 (6)前記第1画素領域は、前記第2画素領域、及び前記第3画素領域は、ベイヤ配列で配置される、(5)に記載の撮像装置。
 (7)前記画素は、光電変換する光の波長帯に対応するカラーフィルタを有し、
 互いに異なる色に対応する2つの前記カラーフィルタは、前記被写体の相対的な移動方向に沿って、隙間無く配置される、(1)乃至(6)のいずれか一項に記載の撮像装置。
 (8)前記第1画素領域は、前記第1色の光を透過する第1カラーフィルタを有する1以上の前記画素を有し、
 前記第2画素領域は、前記第2色の光を透過する第2カラーフィルタを有する1以上の前記画素を有し、
 前記第3画素領域は、前記第3色の光を透過する第3カラーフィルタを有する1以上の前記画素を有し、
 前記第1カラーフィルタ、前記第2カラーフィルタ、及び前記第3カラーフィルタは、前記被写体の相対的な移動方向である第1方向に沿って、隙間無く配置される、(2)乃至(6)のいずれか一項に記載の撮像装置。
 (9)前記第1カラーフィルタ、前記第2カラーフィルタ、及び前記第3カラーフィルタは、前記第1方向に交差する第2方向に混在されずに配置され、
 前記第1カラーフィルタ及び前記第2カラーフィルタは、前記第1方向に隙間無く配置され、
 前記第2カラーフィルタ及び前記第3カラーフィルタは、前記第1方向に隙間無く配置される、(8)に記載の撮像装置。
 (10)前記第1カラーフィルタ、前記第2カラーフィルタ、及び前記第3カラーフィルタは、前記第1方向及び前記第1方向に交差する第2方向に混在されて配置され、
 前記第1カラーフィルタ及び前記第2カラーフィルタは、前記第1方向に隙間無く配置され、
 前記第2カラーフィルタ及び前記第3カラーフィルタは、前記第1方向に隙間無く配置される、(8)に記載の撮像装置。
 (11)前記第1カラーフィルタ、前記第2カラーフィルタ、及び前記第3カラーフィルタは、ベイヤ配列で配置される、(10)に記載の撮像装置。
 (12)前記複数の画素のそれぞれごとに配置され、前記電気信号をデジタル信号に変換するADC(Analog to Digital Converter)をさらに備え、
 前記演算部は、前記デジタル信号を色ごとに積算する、(1)乃至(11)のいずれか一項に記載の撮像装置。
 (13)前記光電変換部が配置される第1チップと、
 前記第1チップと積層され、前記ADCが配置される第2チップと、をさらに備える、(12)に記載の撮像装置。
 (14)前記ADCは、前記光電変換部と積層方向に重なる位置に配置される、(13)に記載の撮像装置。
 (15)撮像装置と、
 前記撮像装置の被写体を所定の速度で移動させる移動部と、を備え、
 前記撮像装置は、
 複数の画素のそれぞれに設けられ、相対的に移動する被写体の移動速度に応じた期間内に光電変換された電気信号を出力する光電変換部と、
 前記電気信号を前記複数の画素の色ごとに積算する演算部と、を備え、
 互いに異なる色の光を光電変換する2つの前記画素は、前記被写体の相対的な移動方向に沿って、隙間無く配置される、電子機器。
The present technology can have the following configurations.
(1) A photoelectric conversion unit provided for each of a plurality of pixels and outputting an electrical signal photoelectrically converted within a period corresponding to the moving speed of a relatively moving subject.
A calculation unit that integrates the electric signal for each color of the plurality of pixels is provided.
An imaging device in which two pixels that photoelectrically convert light of different colors are arranged without gaps along the relative moving direction of the subject.
(2) A second pixel region including one or more of the pixels that photoelectrically convert light of the first color and one or more of the pixels that photoelectrically convert light of a second color different from the first color. A pixel region and a third pixel region containing one or more of the pixels that photoelectrically convert light of the first color and a third color different from the second color are along the relative moving direction of the subject. The imaging device according to (1), which is arranged without gaps.
(3) Each of the first pixel region, the second pixel region, and the third pixel region includes one or more of the pixels in the first direction, which is the relative movement direction of the subject, and the first pixel region. The imaging apparatus according to (2), which includes one or more of the pixels in a second direction intersecting in one direction.
(4) The first pixel region, the second pixel region, and the third pixel region are arranged without being mixed in the second direction.
The first pixel region and the second pixel region are arranged without gaps in the first direction.
The imaging apparatus according to (3), wherein the second pixel region and the third pixel region are arranged without gaps in the first direction.
(5) The first pixel region, the second pixel region, and the third pixel region are arranged in a mixed manner in the first direction and the second direction.
The first pixel region and the second pixel region are arranged without gaps in the first direction.
The imaging apparatus according to (3), wherein the second pixel region and the third pixel region are arranged without gaps in the first direction.
(6) The image pickup apparatus according to (5), wherein the first pixel region is arranged in the second pixel region and the third pixel region is arranged in a bayer array.
(7) The pixel has a color filter corresponding to the wavelength band of light to be photoelectrically converted.
The imaging device according to any one of (1) to (6), wherein the two color filters corresponding to different colors are arranged without a gap along the relative moving direction of the subject.
(8) The first pixel region has one or more of the pixels having a first color filter that transmits light of the first color.
The second pixel region comprises one or more of the pixels having a second color filter that transmits light of the second color.
The third pixel region comprises one or more of the pixels having a third color filter that transmits light of the third color.
The first color filter, the second color filter, and the third color filter are arranged without gaps along the first direction, which is the relative movement direction of the subject, (2) to (6). The imaging apparatus according to any one of the above.
(9) The first color filter, the second color filter, and the third color filter are arranged without being mixed in the second direction intersecting the first direction.
The first color filter and the second color filter are arranged without gaps in the first direction.
The image pickup apparatus according to (8), wherein the second color filter and the third color filter are arranged without gaps in the first direction.
(10) The first color filter, the second color filter, and the third color filter are arranged in a mixed manner in the first direction and the second direction intersecting the first direction.
The first color filter and the second color filter are arranged without gaps in the first direction.
The image pickup apparatus according to (8), wherein the second color filter and the third color filter are arranged without gaps in the first direction.
(11) The image pickup apparatus according to (10), wherein the first color filter, the second color filter, and the third color filter are arranged in a bayer array.
(12) An ADC (Analog to Digital Converter), which is arranged for each of the plurality of pixels and converts the electric signal into a digital signal, is further provided.
The imaging device according to any one of (1) to (11), wherein the calculation unit integrates the digital signals for each color.
(13) The first chip on which the photoelectric conversion unit is arranged and
The imaging apparatus according to (12), further comprising a second chip that is laminated with the first chip and on which the ADC is arranged.
(14) The image pickup apparatus according to (13), wherein the ADC is arranged at a position overlapping the photoelectric conversion unit in the stacking direction.
(15) Imaging device and
A moving unit that moves the subject of the imaging device at a predetermined speed is provided.
The image pickup device
A photoelectric conversion unit provided for each of a plurality of pixels and outputting an electrical signal photoelectrically converted within a period corresponding to the moving speed of a relatively moving subject.
A calculation unit that integrates the electric signal for each color of the plurality of pixels is provided.
An electronic device in which two pixels that photoelectrically convert light of different colors are arranged without gaps along the relative moving direction of the subject.
 本開示の態様は、上述した個々の実施形態に限定されるものではなく、当業者が想到しうる種々の変形も含むものであり、本開示の効果も上述した内容に限定されない。すなわち、特許請求の範囲に規定された内容およびその均等物から導き出される本開示の概念的な思想と趣旨を逸脱しない範囲で種々の追加、変更および部分的削除が可能である。 The aspect of the present disclosure is not limited to the individual embodiments described above, but also includes various modifications that can be conceived by those skilled in the art, and the effects of the present disclosure are not limited to the above-mentioned contents. That is, various additions, changes and partial deletions are possible without departing from the conceptual idea and purpose of the present disclosure derived from the contents defined in the claims and their equivalents.
1 電子機器、100 撮像装置、201 受光チップ、202 回路チップ、222 光電変換素子、310 ADC、400 信号処理回路、410 演算回路、510 ベルトコンベア、511 被写体、P 画素、PR 画素、PG 画素、PB 画素 1 Electronic device, 100 image pickup device, 201 light receiving chip, 202 circuit chip, 222 photoelectric conversion element, 310 ADC, 400 signal processing circuit, 410 arithmetic circuit, 510 belt conveyor, 511 subject, P pixel, PR pixel, PG pixel, PB Pixel

Claims (15)

  1.  複数の画素のそれぞれに設けられ、相対的に移動する被写体の移動速度に応じた期間内に光電変換された電気信号を出力する光電変換部と、
     前記電気信号を前記複数の画素の色ごとに積算する演算部と、を備え、
     互いに異なる色の光を光電変換する2つの前記画素は、前記被写体の相対的な移動方向に沿って、隙間無く配置される、撮像装置。
    A photoelectric conversion unit provided for each of a plurality of pixels and outputting an electrical signal photoelectrically converted within a period corresponding to the moving speed of a relatively moving subject.
    A calculation unit that integrates the electric signal for each color of the plurality of pixels is provided.
    An imaging device in which two pixels that photoelectrically convert light of different colors are arranged without gaps along the relative moving direction of the subject.
  2.  第1色の光を光電変換する1以上の前記画素を含む第1画素領域と、前記第1色とは異なる第2色の光を光電変換する1以上の前記画素を含む第2画素領域と、前記第1色及び前記第2色とは異なる第3色の光を光電変換する1以上の前記画素を含む第3画素領域と、が前記被写体の相対的な移動方向に沿って、隙間無く配置される、請求項1に記載の撮像装置。 A first pixel region containing one or more of the pixels that photoelectrically convert light of the first color, and a second pixel region including one or more of the pixels that photoelectrically convert light of a second color different from the first color. The third pixel region including one or more of the pixels that photoelectrically convert the light of the first color and the light of the third color different from the second color is without a gap along the relative moving direction of the subject. The imaging device according to claim 1, which is arranged.
  3.  前記第1画素領域、前記第2画素領域、及び前記第3画素領域のそれぞれは、前記被写体の相対的な移動方向である第1方向に1以上の前記画素を含み、かつ前記第1方向に交差する第2方向に1以上の前記画素を含む、請求項2に記載の撮像装置。 Each of the first pixel region, the second pixel region, and the third pixel region includes one or more of the pixels in the first direction, which is the relative movement direction of the subject, and in the first direction. The imaging apparatus according to claim 2, further comprising one or more of the pixels in a second intersecting direction.
  4.  前記第1画素領域、前記第2画素領域、及び前記第3画素領域は、前記第2方向に混在されずに配置され、
     前記第1画素領域及び前記第2画素領域は、前記第1方向に隙間無く配置され、
     前記第2画素領域及び前記第3画素領域は、前記第1方向に隙間無く配置される、請求項3に記載の撮像装置。
    The first pixel region, the second pixel region, and the third pixel region are arranged without being mixed in the second direction.
    The first pixel region and the second pixel region are arranged without gaps in the first direction.
    The imaging device according to claim 3, wherein the second pixel region and the third pixel region are arranged without gaps in the first direction.
  5.  前記第1画素領域、前記第2画素領域、及び前記第3画素領域は、前記第1方向及び前記第2方向に混在されて配置され、
     前記第1画素領域及び前記第2画素領域は、前記第1方向に隙間無く配置され、
     前記第2画素領域及び前記第3画素領域は、前記第1方向に隙間無く配置される、請求項3に記載の撮像装置。
    The first pixel region, the second pixel region, and the third pixel region are arranged in a mixed manner in the first direction and the second direction.
    The first pixel region and the second pixel region are arranged without gaps in the first direction.
    The imaging device according to claim 3, wherein the second pixel region and the third pixel region are arranged without gaps in the first direction.
  6.  前記第1画素領域、前記第2画素領域、及び前記第3画素領域は、ベイヤ配列で配置される、請求項5に記載の撮像装置。 The imaging device according to claim 5, wherein the first pixel region, the second pixel region, and the third pixel region are arranged in a bayer array.
  7.  前記画素は、光電変換する光の波長帯に対応するカラーフィルタを有し、
     互いに異なる色に対応する2つの前記カラーフィルタは、前記被写体の相対的な移動方向に沿って、隙間無く配置される、請求項1に記載の撮像装置。
    The pixel has a color filter corresponding to the wavelength band of light to be photoelectrically converted.
    The imaging device according to claim 1, wherein the two color filters corresponding to different colors are arranged without gaps along the relative moving direction of the subject.
  8.  前記第1画素領域は、前記第1色の光を透過する第1カラーフィルタを有する1以上の前記画素を有し、
     前記第2画素領域は、前記第2色の光を透過する第2カラーフィルタを有する1以上の前記画素を有し、
     前記第3画素領域は、前記第3色の光を透過する第3カラーフィルタを有する1以上の前記画素を有し、
     前記第1カラーフィルタ、前記第2カラーフィルタ、及び前記第3カラーフィルタは、前記被写体の相対的な移動方向である第1方向に沿って、隙間無く配置される、請求項2に記載の撮像装置。
    The first pixel region comprises one or more of the pixels having a first color filter that transmits light of the first color.
    The second pixel region comprises one or more of the pixels having a second color filter that transmits light of the second color.
    The third pixel region comprises one or more of the pixels having a third color filter that transmits light of the third color.
    The imaging according to claim 2, wherein the first color filter, the second color filter, and the third color filter are arranged without gaps along the first direction, which is the relative movement direction of the subject. Device.
  9.  前記第1カラーフィルタ、前記第2カラーフィルタ、及び前記第3カラーフィルタは、前記第1方向に交差する第2方向に混在されずに配置され、
     前記第1カラーフィルタ及び前記第2カラーフィルタは、前記第1方向に隙間無く配置され、
     前記第2カラーフィルタ及び前記第3カラーフィルタは、前記第1方向に隙間無く配置される、請求項8に記載の撮像装置。
    The first color filter, the second color filter, and the third color filter are arranged without being mixed in the second direction intersecting the first direction.
    The first color filter and the second color filter are arranged without gaps in the first direction.
    The imaging device according to claim 8, wherein the second color filter and the third color filter are arranged without gaps in the first direction.
  10.  前記第1カラーフィルタ、前記第2カラーフィルタ、及び前記第3カラーフィルタは、前記第1方向及び前記第1方向に交差する第2方向に混在されて配置され、
     前記第1カラーフィルタ及び前記第2カラーフィルタは、前記第1方向に隙間無く配置され、
     前記第2カラーフィルタ及び前記第3カラーフィルタは、前記第1方向に隙間無く配置される、請求項8に記載の撮像装置。
    The first color filter, the second color filter, and the third color filter are arranged in a mixed manner in the first direction and the second direction intersecting the first direction.
    The first color filter and the second color filter are arranged without gaps in the first direction.
    The imaging device according to claim 8, wherein the second color filter and the third color filter are arranged without gaps in the first direction.
  11.  前記第1カラーフィルタ、前記第2カラーフィルタ、及び前記第3カラーフィルタは、ベイヤ配列で配置される、請求項10に記載の撮像装置。 The imaging device according to claim 10, wherein the first color filter, the second color filter, and the third color filter are arranged in a bayer array.
  12.  前記複数の画素のそれぞれごとに配置され、前記電気信号をデジタル信号に変換するADC(Analog to Digital Converter)をさらに備え、
     前記演算部は、前記デジタル信号を色ごとに積算する、請求項1に記載の撮像装置。
    An ADC (Analog to Digital Converter), which is arranged for each of the plurality of pixels and converts the electric signal into a digital signal, is further provided.
    The imaging device according to claim 1, wherein the calculation unit integrates the digital signals for each color.
  13.  前記光電変換部が配置される第1チップと、
     前記第1チップと積層され、前記ADCが配置される第2チップと、をさらに備える、請求項12に記載の撮像装置。
    The first chip on which the photoelectric conversion unit is arranged and
    The imaging apparatus according to claim 12, further comprising a second chip that is laminated with the first chip and on which the ADC is arranged.
  14.  前記ADCは、前記光電変換部と積層方向に重なる位置に配置される、請求項13に記載の撮像装置。 The imaging device according to claim 13, wherein the ADC is arranged at a position overlapping the photoelectric conversion unit in the stacking direction.
  15.  撮像装置と、
     前記撮像装置の被写体を所定の速度で移動させる移動部と、を備え、
     前記撮像装置は、
     複数の画素のそれぞれに設けられ、相対的に移動する被写体の移動速度に応じた期間内に光電変換された電気信号を出力する光電変換部と、
     前記電気信号を前記複数の画素の色ごとに積算する演算部と、を備え、
     互いに異なる色の光を光電変換する2つの前記画素は、前記被写体の相対的な移動方向に沿って、隙間無く配置される、電子機器。
    Imaging device and
    A moving unit that moves the subject of the imaging device at a predetermined speed is provided.
    The image pickup device
    A photoelectric conversion unit provided for each of a plurality of pixels and outputting an electrical signal photoelectrically converted within a period corresponding to the moving speed of a relatively moving subject.
    A calculation unit that integrates the electric signal for each color of the plurality of pixels is provided.
    An electronic device in which two pixels that photoelectrically convert light of different colors are arranged without gaps along the relative moving direction of the subject.
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