WO2022153521A1 - Semiconductor power conversion device - Google Patents

Semiconductor power conversion device Download PDF

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Publication number
WO2022153521A1
WO2022153521A1 PCT/JP2021/001419 JP2021001419W WO2022153521A1 WO 2022153521 A1 WO2022153521 A1 WO 2022153521A1 JP 2021001419 W JP2021001419 W JP 2021001419W WO 2022153521 A1 WO2022153521 A1 WO 2022153521A1
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Prior art keywords
terminal
voltage
switching element
semiconductor switching
clamp
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PCT/JP2021/001419
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French (fr)
Japanese (ja)
Inventor
晃郎 島田
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三菱電機株式会社
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Priority to PCT/JP2021/001419 priority Critical patent/WO2022153521A1/en
Priority to JP2021544371A priority patent/JPWO2022153521A1/ja
Publication of WO2022153521A1 publication Critical patent/WO2022153521A1/en

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode

Definitions

  • the present disclosure discloses a power conversion device that performs DC-AC power conversion using a semiconductor power conversion device such as an IGBT (Insulated Gate Bipolar Transistor), particularly a semiconductor capable of suppressing a surge voltage generated when a semiconductor switching element is turned off.
  • a semiconductor power conversion device such as an IGBT (Insulated Gate Bipolar Transistor), particularly a semiconductor capable of suppressing a surge voltage generated when a semiconductor switching element is turned off.
  • a general semiconductor power conversion device has a power conversion circuit that uses a semiconductor switching element. For example, by connecting semiconductor switching elements such as IGBTs in series and turning the semiconductor switching elements on and off alternately. , Converts power from DC power to AC power. In such a semiconductor power conversion device, it is necessary to reduce the influence of the surge voltage generated when the semiconductor switching element is turned off, and a surge voltage suppression circuit or the like is added to take countermeasures (for example, Patent Document 1). ..
  • the voltage between the terminals of the clamp capacitor connected between the collector and gate of the IGBT is the auxiliary DC power supply or the positive voltage for the drive signal source.
  • the power supply holds the surge voltage at the voltage that starts the operation to suppress the surge voltage (hereinafter referred to as “clamping operation”) (hereinafter referred to as “clamping operation start voltage”), and the IGBT starts the turn-off operation between the collector and the emitter.
  • Patent Document 1 although the surge voltage can be suppressed, an auxiliary DC power supply is required in addition to the DC power supply when the clamp operation is performed using the auxiliary DC power supply. Further, when the clamp operation is performed using the positive voltage for the drive signal source, the voltage of the positive voltage for the drive signal source is too low as the power source for setting the clamp operation start voltage, so even a low clamp operation start voltage is predetermined. It is necessary to divide the voltage between the collector and the emitter using a voltage dividing resistor so that the clamping operation can be started when a surge voltage is generated. Therefore, in the method of Patent Document 1, an auxiliary DC power supply or a voltage dividing resistor is extra required, and the circuit becomes large.
  • the clamp capacitor is charged to the clamp operation start voltage, but when a surge voltage is generated and the clamp operation is performed, the clamp capacitor is additionally charged by the surge voltage.
  • the clamp operation start voltage when the next clamp operation is performed becomes higher than the clamp operation start voltage when the clamp operation is first performed. Therefore, when the semiconductor switching element is repeatedly switched and a large surge voltage is continuously generated between the collector and emitter of the IGBT, even if a surge voltage to be suppressed occurs, it is clamped at the desired clamping operation start voltage. The operation may not be started, the effect of suppressing the surge voltage may not be sufficient, and the IGBT may be damaged.
  • the present disclosure has been made in view of the above, and is applied to the semiconductor switching element when the semiconductor switching element is turned off even if the semiconductor switching element is repeatedly switched while reducing the size of the surge voltage suppression circuit.
  • the purpose is to obtain a semiconductor power converter that can stably suppress the surge voltage.
  • the first terminal is connected to the positive side of the DC power supply
  • the second terminal is an output terminal that outputs AC power. It has a first semiconductor switching element connected and a second semiconductor switching element in which the second terminal is connected to the negative side of the DC power supply and the first terminal is connected to the output terminal.
  • a semiconductor power conversion device that converts DC power to AC power by alternately turning on and off the semiconductor switching element and the second semiconductor switching element, and the cathode is the third semiconductor switching element of the first semiconductor switching element.
  • a first backflow prevention diode connected to the terminal of the first, one end connected to the first terminal of the first semiconductor switching element, and the other end connected to the anode of the first backflow prevention diode.
  • the clamp capacitor, the first gate resistor whose one end is connected to the third terminal of the first semiconductor switching element, and the drive signal output terminal are connected to the other end of the first gate resistor, and the first A first drive circuit for driving a semiconductor switching element, a first charge / discharge resistor having one end connected to the negative side of a DC power supply and the other end connected to the anode of a first backflow prevention diode, and an anode.
  • a second clamping capacitor connected to the cathode of the semiconductor switching element, a second gate resistor having one end connected to the third terminal of the second semiconductor switching element, and a second gate resistor whose drive signal output terminal is a second gate resistor.
  • a second drive circuit connected to the other end of the semiconductor switching element to drive the second semiconductor switching element, one end connected to the positive side of the DC power supply, and the other end connected to the cathode of the second backflow prevention diode. It is characterized by having a second charge / discharge resistor.
  • the semiconductor power conversion device stabilizes the surge voltage applied to the semiconductor switching element when the semiconductor switching element is turned off even if the semiconductor switching element is repeatedly switched while miniaturizing the surge voltage suppression circuit. It has the effect of being able to suppress it.
  • FIG. 1 is a diagram showing a circuit configuration of the semiconductor power conversion device according to the first embodiment of the present disclosure.
  • the power conversion circuit of a general semiconductor power converter is a three-phase bridge circuit, and is composed of a three-phase series circuit electrically connected in parallel between the positive side and the negative side of the DC power supply. There is.
  • the series circuit is also called an arm, and is configured by electrically connecting a semiconductor switching element on the upper side of the arm and a semiconductor switching element on the lower side of the arm in series.
  • FIG. 1 shows a circuit configuration using an IGBT as a semiconductor switching element as an example, and is connected to the IGBT 1a on the upper side of the arm connected to the positive electrode side of the DC power supply 7 and to the negative electrode side of the DC power supply 7.
  • An example of one phase of a power conversion circuit in which the IGBT 1b on the lower side of the arm is connected in series is shown.
  • the semiconductor power conversion device shown in FIG. 1 includes an IGBT 1a, 1b having a gate G, a collector C, and an emitter E, a freewheeling diode 2a, 2b, a gate resistor 3a, 3b, a clamping capacitor 4a, 4b, and a backflow prevention diode 5a, It includes 5b, charging / discharging resistors 6a and 6b, a DC power supply 7, an output terminal 8 for outputting AC power, and drive circuits 10a and 10b for driving the IGBTs 1a and 1b.
  • the drive circuits 10a and 10b include positive power supplies 13a and 13b for the drive circuit, negative power supplies 14a and 14b for the drive circuit, NPN transistors 11a and 11b, PNP transistors 12a and 12b, control signal input terminals 15a and 15b, and drive signals, respectively.
  • the output terminals 16a and 16b are provided.
  • the semiconductor power conversion device operates so that the circuit portion including the clamping capacitors 4a and 4b, the backflow prevention diodes 5a and 5b, and the charge and discharge resistors 6a and 6b suppress the surge voltage due to the turn-off of the IGBTs 1a and 1b.
  • IGBTs 1a and 1b are examples of a first semiconductor switching element and a second semiconductor switching element
  • gate resistors 3a and 3b are examples of a first gate resistor and a second gate resistor
  • clamping capacitors 4a and 4b Is an example of a first clamp capacitor and a second clamp capacitor
  • backflow prevention diodes 5a and 5b are examples of a first backflow prevention diode and a second backflow prevention diode for charging and discharging.
  • the resistors 6a and 6b are examples of the first charge / discharge resistor and the second charge / discharge resistor
  • the drive circuits 10a and 10b are examples of the first drive circuit and the second drive circuit.
  • the collector C, the emitter E, and the gate G included in the IGBTs 1a and 1b are examples of the first terminal, the second terminal, and the third terminal of the semiconductor switching element.
  • the circuit configuration on the upper side of the arm is as follows. First, in the IGBT 1a, the collector C is connected to the positive electrode side of the DC power supply 7, the emitter E is connected to the output terminal 8, and the gate G is connected to one end of the gate resistor 3a. In the freewheeling diode 2a, the anode is connected to the emitter E of the IGBT 1a and the cathode is connected to the collector C of the IGBT 1a. One end of the clamping capacitor 4a is connected to the anode of the backflow prevention diode 5a, and the other end is connected to the collector C of the IGBT 1a. The cathode of the backflow prevention diode 5a is connected to the gate G of the IGBT 1a.
  • the drive signal output terminal 16a is connected to the other end of the gate resistor 3a.
  • the drive signal output terminal 16a is connected to the NPN transistor 11a and the emitter E of the PNP transistor 12a.
  • the control signal input terminal 15a is connected to the NPN transistor 11a and the base B of the PNP transistor 12a.
  • the positive electrode terminal is connected to the collector C of the NPN transistor 11a, and the negative electrode terminal is connected to the emitter E of the IGBT 1a.
  • the negative power supply 14a the negative electrode terminal is connected to the collector C of the PNP transistor 12a, and the positive electrode terminal is connected to the emitter E of the IGBT 1a.
  • One end of the charge / discharge resistor 6a is connected to the negative electrode side of the DC power supply 7, and the other end is connected to the anode of the backflow prevention diode 5a.
  • the circuit configuration on the lower side of the arm is almost the same as the circuit configuration on the upper side of the arm.
  • the collector C is connected to the output terminal 8
  • the emitter E is connected to the negative electrode side of the DC power supply 7
  • the gate G is connected to one end of the gate resistor 3b.
  • the freewheeling diode 2b the anode is connected to the emitter E of the IGBT 1b and the cathode is connected to the collector C of the IGBT 1b.
  • One end of the clamping capacitor 4b is connected to the cathode of the backflow prevention diode 5b, and the other end is connected to the gate G of the IGBT 1b.
  • the anode of the backflow prevention diode 5b is connected to the collector C of the IGBT 1b.
  • the drive signal output terminal 16b is connected to the other end of the gate resistor 3b.
  • the drive signal output terminal 16b is connected to the NPN transistor 11b and the emitter E of the PNP transistor 12b.
  • the control signal input terminal 15b is connected to the base B of the NPN transistor 11b and the PNP transistor 12b.
  • the positive power supply 13b for the drive circuit is connected to the collector C of the NPN transistor 11b, and the negative electrode terminal is connected to the emitter E of the IGBT 1b.
  • the negative electrode terminal is connected to the collector C of the PNP transistor 12b, and the positive electrode terminal is connected to the emitter E of the IGBT 1b.
  • One end of the charge / discharge resistor 6b is connected to the positive electrode side of the DC power supply 7, and the other end is connected to the cathode of the backflow prevention diode 5b.
  • FIG. 2 also shows, as a comparative example, the characteristics of a semiconductor switching element in a semiconductor power conversion device not provided with the surge voltage suppression circuit as shown in FIG.
  • FIGS. 2 (a) to 2 (d) 31, 32, 33, and 34 shown by solid lines are characteristic curves of the gate-emitter voltage Vge with respect to the IGBTs 1a and 1b of the semiconductor power conversion device according to the first embodiment.
  • 21, 22, 23, and 24 shown by broken lines are the characteristic curve of the gate-emitter voltage Vge and the characteristic curve of the collector-emitter voltage Vce with respect to the IGBTs 1a and 1b of the semiconductor power converter shown in FIG. It is a characteristic curve of a collector current Ic and a turn-off loss, and is shown as a comparative example.
  • the drive signal of the positive pulse is output from the drive signal output terminal 16a of the drive circuit 10a by the control signal input from the control signal input terminal 15a
  • the drive signal is supplied to the gate G of the IGBT 1a via the gate resistor 3a.
  • IGBT1a turns on.
  • the voltage V4a between the terminals of the clamping capacitor 4a is held at the same voltage as the DC power supply 7 via the charging / discharging resistor 6a.
  • control signal input from the control signal input terminal 15a changes the drive signal output from the drive signal output terminal 16a of the drive circuit 10a from a positive pulse to a negative pulse, and the negative pulse changes to a gate resistance.
  • the control signal input from the control signal input terminal 15a changes the drive signal output from the drive signal output terminal 16a of the drive circuit 10a from a positive pulse to a negative pulse, and the negative pulse changes to a gate resistance.
  • the gate-emitter voltage Vge1a changes so as to temporarily increase with respect to the characteristic curve 21 near time t1 as shown in the characteristic curve 31 of FIG. 2 (a), and becomes a threshold voltage.
  • the IGBT 1a is turned on, and the collector-emitter voltage Vce1a is clamped to the clamp voltage Vcecr near time t2.
  • the current change (di / dt) of the collector current Ic1a flowing between the collector and the emitter of the IGBT 1a becomes gentler than that of the characteristic curve 23 as shown in the characteristic curve 33 of FIG. 2 (c).
  • the arm upper clamp operation start voltage is an example of the first clamp operation start voltage.
  • the clamp voltage Vsecr in the first embodiment can be expressed by the following equation (1).
  • Vcecr V4a + Vge (th) + V5a ... (1)
  • Vge (th) indicates the threshold voltage of IGBT 1a.
  • the terminal voltage V4a of the clamping capacitor 4a is charged to the same voltage as the DC power supply 7, and the threshold voltage Vge (th) and the forward voltage V5a of the backflow prevention diode 5a are sufficient for the DC power supply voltage. Since it is small, the clamp voltage Vcecr is almost equal to the DC power supply voltage.
  • the operation of the circuit on the lower side of the arm is the same as that of the circuit on the upper side of the arm. Specifically, when the drive signal of the positive pulse is output from the drive circuit 10b by the control signal input from the control signal input terminal 15b, the drive signal is supplied to the gate G of the IGBT 1b via the gate resistor 3b. , IGBT1b turns on. At this time, the voltage V4b between the terminals of the clamping capacitor 4b is changed from the voltage of the DC power supply 7 to the positive power supply 13b for the drive circuit according to the control signal input from the control signal input terminal 15b via the charging / discharging resistor 6b.
  • control signal input from the control signal input terminal 15b changes the drive signal output from the drive signal output terminal 16b of the drive circuit 10b from a positive pulse to a negative pulse, and the negative pulse changes to a gate resistance.
  • the control signal input from the control signal input terminal 15b changes the drive signal output from the drive signal output terminal 16b of the drive circuit 10b from a positive pulse to a negative pulse, and the negative pulse changes to a gate resistance.
  • the gate-emitter voltage Vge1b changes so as to temporarily increase with respect to the characteristic curve 21 near time t1 as shown in the characteristic curve 31 of FIG. 2 (a), and becomes a threshold voltage.
  • the IGBT 1b is turned on, and the collector-emitter voltage Vce1b is clamped to the same clamping voltage as in the equation (1) near the time t2.
  • the current change (di / dt) of the collector current Ic1b flowing between the collector and the emitter due to the turn-off of the IGBT 1b becomes gentler than that of the characteristic curve 23 as shown in the characteristic curve 33 of FIG. 2 (c).
  • the lower clamp operation start voltage of the arm is an example of the second clamp operation start voltage.
  • the voltage between the terminals of the clamping capacitors 4a and 4b is charged and the voltage rises temporarily, but DC is supplied via the charging / discharging resistors 6a and 6b. It is discharged to the power source 7.
  • the clamp capacitor 4a is discharged until it reaches the same potential as the DC power supply 7.
  • the discharge of the clamping capacitor 4b is the voltage obtained by subtracting the drive circuit positive power supply 13b from the voltage of the DC power supply 7 or the voltage of the DC power supply 7 according to the drive signal input from the control signal input terminal 15b. It is discharged until it reaches the same potential as the voltage to which the negative power supply 14b is applied.
  • the clamping capacitor 4b is discharged until the potential becomes substantially the same as that of the DC power supply 7. In this way, the clamping capacitors 4a and 4b charged by the surge voltage are discharged via the charging / discharging resistors 6a and 6b, so that the clamping operation start voltage at the time of the second and subsequent switching of the semiconductor switching element becomes. It is maintained at the same voltage as the clamp operation start voltage at the time of the first switching of the semiconductor switching element. Therefore, the semiconductor power conversion device according to the embodiment of the present disclosure stably suppresses the surge voltage applied between the collector and the emitter at the time of turn-off even if the semiconductor switching element is repeatedly switched. Can be done.
  • the energy discharged from the clamping capacitors 4a and 4b is limited to the energy charged more than the DC power supply 7 by the surge voltage, not the total energy charged in the clamping capacitors 4a and 4b.
  • the discharge loss can be minimized, and the charging / discharging resistors 6a and 6b can be miniaturized.
  • the charging / discharging resistors 6a and 6b are not only used as a charging / discharging path for the capacitors 4a and 4b, but also suppress the current flowing from the DC power supply 7 to the gates of the IGBTs 1a and 1b.
  • the semiconductor power conversion device has a configuration in which a clamping capacitor is connected between the collector and gate of the IGBT, and the clamping capacitor is charged and discharged from the DC power supply via the charging / discharging resistor.
  • This makes it possible to set the clamp operation start voltage without using an auxiliary DC power supply or a voltage dividing resistor, and it is possible to suppress the surge voltage while reducing the size of the surge voltage suppression circuit.
  • the clamp capacitor by configuring the clamp capacitor to discharge the excess charge to the DC power supply via the charging / discharging resistor, the clamping operation start voltage is set to a predetermined voltage even if the semiconductor switching element is repeatedly switched. It is possible to stably suppress the surge voltage applied between the collector and the emitter when the semiconductor switching element is turned off.
  • Embodiment 2 There is a trade-off relationship between surge voltage suppression and turn-off loss, and if the surge voltage suppression effect is high, turn-off loss increases.
  • the clamp voltage that determines the surge voltage suppression effect is determined by the voltage between the terminals of the clamp capacitor (that is, the DC power supply voltage), the threshold voltage of the semiconductor switching element, and the forward voltage of the backflow prevention diode. Since the clamp voltage cannot be adjusted flexibly, the trade-off between surge voltage suppression and increase in turn-off loss cannot be flexibly adjusted.
  • a semiconductor power conversion device capable of flexibly adjusting the clamp voltage and flexibly adjusting the trade-off between surge voltage suppression and increase in turn-off loss will be described. The same parts as those of the first embodiment will be omitted, and the parts different from the first embodiment will be described.
  • FIG. 3 is a diagram showing a circuit configuration of the semiconductor power conversion device according to the second embodiment.
  • the semiconductor power conversion device shown in FIG. 3 includes clamp current suppression resistors 9a and 9b that suppress the clamp operation start current, and other configurations are the same as those in FIG.
  • the same components as those shown in FIG. 1 are designated by the same reference numerals.
  • the clamp current suppression resistors 9a and 9b are examples of the first clamp current suppression resistor and the second clamp current suppression resistor.
  • One end of the clamp current suppression resistor 9a is connected to the collector C of the IGBT 1a, and the other end of the clamp current suppression resistor 9a is connected to the terminal opposite to the terminal of the clamp capacitor 4a connected to the backflow prevention diode 5a. Has been done.
  • clamp current suppression resistor 9b One end of the clamp current suppression resistor 9b is connected to the collector C of the IGBT 1b, and the other end of the clamp current suppression resistor 9b is connected to the anode of the backflow prevention diode 5b.
  • the connection configuration of the clamp current suppression resistors 9a and 9b shown in FIG. 3 is an example, and the clamp current suppression resistors 9a and 9b may be provided so as to suppress the clamp operation start current. That is, the clamp current suppression resistor 9a is connected in series with the clamp capacitor 4a between the collector C and the gate G of the IGBT 1a, and the clamp current suppression resistor 9b is connected between the collector C and the gate G of the IGBT 1b. It suffices if it is connected in series with the clamping capacitor 4b.
  • FIGS. 2 and 3 The operation of the semiconductor power conversion device according to the second embodiment will be described with reference to FIGS. 2 and 3. Similar to the description in the first embodiment, when either of the IGBTs 1a and 1b is turned off, a surge voltage is generated between the collector and the emitter of the IGBT that has turned off. Since the operation is the same regardless of whether the IGBT 1a is turned off or the IGBT 1b is turned off, the case where the IGBT 1a on the upper side of the arm is turned off will be described below as an example.
  • the voltage obtained by subtracting the clamp operation start voltage on the upper side of the arm from the collector-emitter voltage Vce1a of the IGBT 1a is the clamp current suppression resistor 9a. Is applied to. Therefore, the current obtained by dividing the applied voltage to the clamp current suppression resistance 9a by the resistance value R9a of the clamp current suppression resistance 9a flows from the collector C of the IGBT 1a to the gate resistance 3a as the arm upper clamp operation start current, and becomes the gate resistance 3a. A voltage is generated in the direction opposite to that of the drive circuit negative power supply 14a.
  • the gate-emitter voltage Vge1a changes so as to temporarily increase.
  • the gate-emitter voltage Vge1a of the IGBT 1a at this time shows a characteristic curve as shown in 41 of FIG. 2 (a). That is, the characteristic curve 41 of the gate-emitter voltage Vge1a of the IGBT 1a of the second embodiment temporarily rises near time t1, but the clamp operation start current on the upper side of the arm is limited by the clamp current suppression resistor 9a. As a result, the increase in the gate-emitter voltage Vge1a after the turn-off of the IGBT 1a is reduced as compared with the characteristic curve 31 of the gate-emitter voltage Vge1a of the first embodiment.
  • the characteristic curve of the collector-emitter voltage Vce1a at this time is a characteristic curve as shown in 42 of FIG. 2 (b). That is, the characteristic curve 42 of the collector-emitter voltage Vce1a of the IGBT 1a of the second embodiment is the voltage immediately after the turn-off near the time t2 as compared with the characteristic curve 32 of the collector-emitter voltage Vce1a of the IGBT 1a of the first embodiment. The rise of is slightly higher, but after that, it quickly converges to the steady state voltage.
  • the clamp voltage Vcecr at this time can be expressed by the following equation (2).
  • Vcecr V4a + (Vge (th) + V14a) x R9a / R3a + V5a + Vge (th) ⁇ ⁇ ⁇ (2)
  • V4a is the voltage between the terminals of the clamping capacitor 4a
  • Vge (th) is the threshold voltage of the IGBT 1a
  • V14a is the voltage of the negative power supply 14a for the drive circuit
  • R9a is the resistance value of the clamping current suppression resistor 9a.
  • R3a indicates the resistance value of the gate resistance 3a
  • V5a indicates the forward voltage of the backflow prevention diode 5a.
  • the second term (Vge (th) + V14a) ⁇ R9a The clamp voltage can be predominantly adjusted with / R3a.
  • the inter-terminal voltage V4a of the clamp capacitor 4a is charged by the clamp operation start current Icr flowing from the collector of the IGBT 1a when a surge voltage is generated.
  • the clamp operation start current Icr can be expressed by the following equation (3).
  • the capacitance of the clamp capacitor 4a is not sufficient with respect to the clamp operation start current Icr flowing from the collector C of the IGBT 1a into the clamp capacitor 4a, the voltage V4a between the terminals of the clamp capacitor 4a rises, and the clamp voltage Vcecr Will be higher than the originally planned voltage, so there is a risk that an excessive surge voltage will be applied to the IGBT 1a. Therefore, regarding the capacitance of the clamping capacitor 4a, it is necessary to select a capacitor having an appropriate capacitance with respect to the clamping operation start current Icr flowing from the collector C of the IGBT 1a into the clamping capacitor 4a.
  • the collector-emitter voltage Vce1a of the IGBT 1a is clamped, and the IGBT 1a has the characteristic curve 41 of the gate-emitter voltage Vge1a and the characteristic curve 42 of the collector-emitter voltage Vce1a.
  • the characteristic curve of the collector current Ic1a of the IGBT 1a shows the characteristic curve shown in 43 of FIG. 2 (c).
  • the slope of the current change (di / dt) of the collector current Ic of 43 in FIG. 2 (c) is compared with the slope of the current change (di / dt) of the collector current Ic of 33 in FIG. 2 (c).
  • the clamp current suppression resistor 9a has a function of adjusting the inclination of the current change (di / dt) of the collector current Ic.
  • the slope of the current change (di / dt) of the collector current Ic of 43 in FIG. 2 (c) became larger than the slope of the current change (di / dt) of the collector current Ic of 33 in FIG. 2 (c).
  • the turn-off loss 44 of the IGBT 1a is reduced as compared with the turn-off loss 34.
  • the semiconductor power converter flexibly adjusts the clamping voltage between the collector and the emitter of the IGBT by the clamping current suppression resistor provided in series with the clamping capacitor between the collector and the gate of the IGBT. Since it can be adjusted to flexibly adjust the trade-off between surge voltage suppression and increase in turn-off loss, the desired surge voltage suppression within the allowable range of turn-off loss can be achieved by selecting an appropriate resistance value for the clamp current suppression resistance. The effect can be obtained.
  • the semiconductor switching element has been described as an IGBT, but the same action / effect can be obtained by replacing the semiconductor switching element with a MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor).
  • MOSFET Metal-Oxide-Semiconductor Field Effect Transistor
  • the semiconductor switching element is configured so that the collector C is replaced with the drain D and the emitter E is replaced with the source S.
  • the drain D, the source S, and the gate G included in the MOSFET are examples of the first terminal, the second terminal, and the third terminal of the semiconductor switching element.
  • the configuration shown in the above-described embodiment shows an example of the contents of the present disclosure, can be combined with another known technique, and has a configuration within a range that does not deviate from the gist of the present disclosure. It is also possible to omit or change a part.

Abstract

The present invention comprises: a diode 5a that has a cathode that is connected to a gate of an IGBT 1a; a capacitor 4a that is connected at one end to a collector of IGBT 1a and is connected at the other end to an anode of diode 5a; a resistor 3a that is connected at one end to the gate of IGBT 1a; a drive circuit 10a that has a drive signal output terminal that is connected to the other end of resistor 3a and drives IGBT 1a; a resistor 6a that is connected at one end to a negative electrode side of a direct-current power supply and is connected at the other end to the anode of diode 5a; a diode 5b that has an anode that is connected to a collector of an IGBT 1b; a capacitor 4b that is connected at one end to a gate of IGBT 1b and is connected at the other end to a cathode of diode 5b; a resistor 3b that is connected at one end to the gate of IGBT 1b; a drive circuit 10b that has a drive signal output terminal that is connected to the other end of resistor 3b and drives IGBT 1b; and a resistor 6b that is connected at one end to a positive electrode side of the direct-current power supply and is connected at the other end to the cathode of diode 5b.

Description

半導体電力変換装置Semiconductor power converter
　本開示は、ＩＧＢＴ（Ｉｎｓｕｌａｔｅｄ　Ｇａｔｅ　Ｂｉｐｏｌａｒ　Ｔｒａｎｓｉｓｔｏｒ）等の半導体電力変換装置を用いた直流－交流電力変換を行う電力変換装置、特に半導体スイッチング素子がターンオフしたときに発生するサージ電圧の抑制が可能な半導体電力変換装置に関する。 The present disclosure discloses a power conversion device that performs DC-AC power conversion using a semiconductor power conversion device such as an IGBT (Insulated Gate Bipolar Transistor), particularly a semiconductor capable of suppressing a surge voltage generated when a semiconductor switching element is turned off. Regarding power converters.
　一般的な半導体電力変換装置は、半導体スイッチング素子を利用する電力変換回路を有しており、例えば、ＩＧＢＴ等の半導体スイッチング素子を直列に接続し、半導体スイッチング素子を交互にオン・オフさせることで、直流電力から交流電力へ電力変換を行う。このような半導体電力変換装置では、半導体スイッチング素子がターンオフする時に発生するサージ電圧の影響を低減することが必要とされ、サージ電圧抑制回路等を付加して対策を行う（例えば、特許文献１）。 A general semiconductor power conversion device has a power conversion circuit that uses a semiconductor switching element. For example, by connecting semiconductor switching elements such as IGBTs in series and turning the semiconductor switching elements on and off alternately. , Converts power from DC power to AC power. In such a semiconductor power conversion device, it is necessary to reduce the influence of the surge voltage generated when the semiconductor switching element is turned off, and a surge voltage suppression circuit or the like is added to take countermeasures (for example, Patent Document 1). ..
　特許文献１のサージ電圧抑制回路は、ＩＧＢＴがターンオフ動作をしていないときは、ＩＧＢＴのコレクタ・ゲート間に接続されたクランプ用コンデンサの端子間電圧が、補助直流電源、又は駆動信号源用正極電源によって、サージ電圧を抑制する動作（以降、「クランプ動作」という）を開始する電圧（以降、「クランプ動作開始電圧」という）に保持され、ＩＧＢＴがターンオフ動作を開始して、コレクタ・エミッタ間にサージ電圧が発生し、そのサージ電圧がクランプ動作開始電圧を超えると、クランプ動作開始電圧を超えた電圧に対応する電流がクランプ用コンデンサからゲートに流れ込み、ゲートに正電荷が補充されることによって、コレクタ電圧上昇を緩やかにしてサージ電圧を抑制する。 In the surge voltage suppression circuit of Patent Document 1, when the IGBT is not in the turn-off operation, the voltage between the terminals of the clamp capacitor connected between the collector and gate of the IGBT is the auxiliary DC power supply or the positive voltage for the drive signal source. The power supply holds the surge voltage at the voltage that starts the operation to suppress the surge voltage (hereinafter referred to as "clamping operation") (hereinafter referred to as "clamping operation start voltage"), and the IGBT starts the turn-off operation between the collector and the emitter. When a surge voltage is generated in the gate and the surge voltage exceeds the clamp operation start voltage, the current corresponding to the voltage exceeding the clamp operation start voltage flows from the clamp capacitor to the gate, and the gate is replenished with positive charge. , The collector voltage rise is moderated to suppress the surge voltage.
特開２００１－２３８４３１号公報Japanese Unexamined Patent Publication No. 2001-238431
　しかし、特許文献１では、サージ電圧の抑制は可能であるが、補助直流電源を用いてクランプ動作する場合は、直流電源とは別に補助直流電源が必要になる。また、駆動信号源用正極電源を用いてクランプ動作する場合は、クランプ動作開始電圧を設定するための電源としては駆動信号源用正極電源の電圧が低すぎるため、低いクランプ動作開始電圧でも所定のサージ電圧が発生したときにクランプ動作を開始できるように、コレクタ・エミッタ間の電圧を分圧抵抗を用いて分圧させる必要がある。このため、特許文献１の方法では、補助直流電源、又は分圧抵抗が余分に必要になり、回路が大型化してしまう。 However, in Patent Document 1, although the surge voltage can be suppressed, an auxiliary DC power supply is required in addition to the DC power supply when the clamp operation is performed using the auxiliary DC power supply. Further, when the clamp operation is performed using the positive voltage for the drive signal source, the voltage of the positive voltage for the drive signal source is too low as the power source for setting the clamp operation start voltage, so even a low clamp operation start voltage is predetermined. It is necessary to divide the voltage between the collector and the emitter using a voltage dividing resistor so that the clamping operation can be started when a surge voltage is generated. Therefore, in the method of Patent Document 1, an auxiliary DC power supply or a voltage dividing resistor is extra required, and the circuit becomes large.
　また、クランプ動作を行うまでは、クランプ用コンデンサはクランプ動作開始電圧まで充電されているが、サージ電圧が発生しクランプ動作を行うと、クランプ用コンデンサがサージ電圧によって余分に充電されてしまう。その結果、半導体スイッチング素子のスイッチングが繰り返し行われると、次回クランプ動作を行うときのクランプ動作開始電圧が、最初にクランプ動作を行ったときのクランプ動作開始電圧よりも高くなってしまう。そのため、半導体スイッチング素子のスイッチングが繰り返し行われ、連続してＩＧＢＴのコレクタ・エミッタ間に大きなサージ電圧が発生する場合には、抑制すべきサージ電圧が生じても、所望するクランプ動作開始電圧でクランプ動作が開始されなくなり、十分なサージ電圧の抑制効果が得られずＩＧＢＴが破損する恐れがある。 Also, until the clamp operation is performed, the clamp capacitor is charged to the clamp operation start voltage, but when a surge voltage is generated and the clamp operation is performed, the clamp capacitor is additionally charged by the surge voltage. As a result, when the semiconductor switching element is repeatedly switched, the clamp operation start voltage when the next clamp operation is performed becomes higher than the clamp operation start voltage when the clamp operation is first performed. Therefore, when the semiconductor switching element is repeatedly switched and a large surge voltage is continuously generated between the collector and emitter of the IGBT, even if a surge voltage to be suppressed occurs, it is clamped at the desired clamping operation start voltage. The operation may not be started, the effect of suppressing the surge voltage may not be sufficient, and the IGBT may be damaged.
　本開示は、上記に鑑みてなされたものであって、サージ電圧抑制回路を小型化しつつ、半導体スイッチング素子のスイッチングが繰り返し行われても、半導体スイッチング素子がターンオフしたときに半導体スイッチング素子に印可されるサージ電圧を安定して抑制できる半導体電力変換装置を得ることを目的とする。 The present disclosure has been made in view of the above, and is applied to the semiconductor switching element when the semiconductor switching element is turned off even if the semiconductor switching element is repeatedly switched while reducing the size of the surge voltage suppression circuit. The purpose is to obtain a semiconductor power converter that can stably suppress the surge voltage.
　上述した課題を解決し、目的を達成するために、本開示の半導体電力変換装置は、第１の端子が直流電源の正極側に接続され、第２の端子が交流電力を出力する出力端子に接続された第１の半導体スイッチング素子と、第２の端子が直流電源の負極側に接続され、第１の端子が出力端子に接続された第２の半導体スイッチング素子とを有し、第１の半導体スイッチング素子と第２の半導体スイッチング素子とを交互にオン・オフさせることで、直流電力から交流電力へ電力変換を行う半導体電力変換装置であって、カソードが第１の半導体スイッチング素子の第３の端子に接続された第１の逆流防止用ダイオードと、一端が第１の半導体スイッチング素子の第１の端子に接続され、他端が第１の逆流防止用ダイオードのアノードに接続された第１のクランプ用コンデンサと、一端が第１の半導体スイッチング素子の第３の端子に接続された第１のゲート抵抗と、駆動信号出力端子が第１のゲート抵抗の他端に接続され、第１の半導体スイッチング素子を駆動する第１のドライブ回路と、一端が直流電源の負極側に接続され、他端が第１の逆流防止用ダイオードのアノードに接続された第１の充放電用抵抗と、アノードが第２の半導体スイッチング素子の第１の端子に接続された第２の逆流防止用ダイオードと、一端が第２の半導体スイッチング素子の第３の端子に接続され、他端が第２の逆流防止用ダイオードのカソードに接続された第２のクランプ用コンデンサと、一端が第２の半導体スイッチング素子の第３の端子に接続された第２のゲート抵抗と、駆動信号出力端子が第２のゲート抵抗の他端に接続され、第２の半導体スイッチング素子を駆動する第２のドライブ回路と、一端が直流電源の正極側に接続され、他端が第２の逆流防止用ダイオードのカソードに接続された第２の充放電用抵抗と、を備えたことを特徴とする。 In order to solve the above-mentioned problems and achieve the object, in the semiconductor power conversion device of the present disclosure, the first terminal is connected to the positive side of the DC power supply, and the second terminal is an output terminal that outputs AC power. It has a first semiconductor switching element connected and a second semiconductor switching element in which the second terminal is connected to the negative side of the DC power supply and the first terminal is connected to the output terminal. A semiconductor power conversion device that converts DC power to AC power by alternately turning on and off the semiconductor switching element and the second semiconductor switching element, and the cathode is the third semiconductor switching element of the first semiconductor switching element. A first backflow prevention diode connected to the terminal of the first, one end connected to the first terminal of the first semiconductor switching element, and the other end connected to the anode of the first backflow prevention diode. The clamp capacitor, the first gate resistor whose one end is connected to the third terminal of the first semiconductor switching element, and the drive signal output terminal are connected to the other end of the first gate resistor, and the first A first drive circuit for driving a semiconductor switching element, a first charge / discharge resistor having one end connected to the negative side of a DC power supply and the other end connected to the anode of a first backflow prevention diode, and an anode. Is connected to the first terminal of the second semiconductor switching element, and one end is connected to the third terminal of the second semiconductor switching element, and the other end is the second backflow prevention. A second clamping capacitor connected to the cathode of the semiconductor switching element, a second gate resistor having one end connected to the third terminal of the second semiconductor switching element, and a second gate resistor whose drive signal output terminal is a second gate resistor. A second drive circuit connected to the other end of the semiconductor switching element to drive the second semiconductor switching element, one end connected to the positive side of the DC power supply, and the other end connected to the cathode of the second backflow prevention diode. It is characterized by having a second charge / discharge resistor.
　本開示にかかる半導体電力変換装置は、サージ電圧抑制回路を小型化しつつ、半導体スイッチング素子のスイッチングが繰り返し行われても、半導体スイッチング素子がターンオフしたときに半導体スイッチング素子に印可されるサージ電圧を安定して抑制できるという効果を奏する。 The semiconductor power conversion device according to the present disclosure stabilizes the surge voltage applied to the semiconductor switching element when the semiconductor switching element is turned off even if the semiconductor switching element is repeatedly switched while miniaturizing the surge voltage suppression circuit. It has the effect of being able to suppress it.
実施の形態１にかかる半導体電力変換装置の回路構成を示す図The figure which shows the circuit structure of the semiconductor power conversion apparatus which concerns on Embodiment 1. 本開示の実施の形態にかかる半導体電力変換装置における半導体スイッチング素子の各部の電圧および電流、またはターンオフ損失の時間的変動を示す特性図A characteristic diagram showing temporal fluctuations in voltage and current of each part of a semiconductor switching element in the semiconductor power converter according to the embodiment of the present disclosure, or turn-off loss. 実施の形態２にかかる半導体電力変換装置の回路構成を示す図The figure which shows the circuit structure of the semiconductor power conversion apparatus which concerns on Embodiment 2. サージ電圧抑制回路を設けていない半導体電力変換装置の回路構成を示す図The figure which shows the circuit structure of the semiconductor power conversion apparatus which does not provide a surge voltage suppression circuit.
　以下に、本開示の実施の形態にかかる半導体電力変換装置を図面に基づいて詳細に説明する。なお、この実施の形態により本開示が限定されるものではない。 Hereinafter, the semiconductor power conversion device according to the embodiment of the present disclosure will be described in detail with reference to the drawings. The present disclosure is not limited to this embodiment.
実施の形態１．
　図１は、本開示の実施形態１にかかる半導体電力変換装置の回路構成を示す図である。一般的な半導体電力変換装置の電力変換回路は、３相ブリッジ回路であり、３相分の直列回路が直流電源の正極側と負極側との間に電気的に並列に接続されて構成されている。直列回路はアームとも呼ばれ、アーム上側の半導体スイッチング素子とアーム下側の半導体スイッチング素子とが電気的に直列に接続されて構成されている。図１には、一例として半導体スイッチング素子にＩＧＢＴを使用した回路構成を示したものであり、直流電源７の正極側に接続されるアーム上側のＩＧＢＴ１aと、直流電源７の負極側に接続されるアーム下側のＩＧＢＴ１ｂとが直列に接続する電力変換回路１相分の例を示すものである。 Embodiment 1.
FIG. 1 is a diagram showing a circuit configuration of the semiconductor power conversion device according to the first embodiment of the present disclosure. The power conversion circuit of a general semiconductor power converter is a three-phase bridge circuit, and is composed of a three-phase series circuit electrically connected in parallel between the positive side and the negative side of the DC power supply. There is. The series circuit is also called an arm, and is configured by electrically connecting a semiconductor switching element on the upper side of the arm and a semiconductor switching element on the lower side of the arm in series. FIG. 1 shows a circuit configuration using an IGBT as a semiconductor switching element as an example, and is connected to the IGBT 1a on the upper side of the arm connected to the positive electrode side of the DC power supply 7 and to the negative electrode side of the DC power supply 7. An example of one phase of a power conversion circuit in which the IGBT 1b on the lower side of the arm is connected in series is shown.
　図１に示す半導体電力変換装置は、ゲートＧとコレクタＣとエミッタＥを備えたＩＧＢＴ１ａ，１ｂ、還流ダイオード２ａ，２ｂ、ゲート抵抗３ａ，３ｂ、クランプ用コンデンサ４a，４ｂ、逆流防止用ダイオード５a，５ｂ、充放電用抵抗６a，６ｂ、直流電源７、交流電力を出力する出力端子８、ＩＧＢＴ1ａ，１ｂを駆動するドライブ回路１０ａ，１０ｂを備えている。ドライブ回路１０ａ，１０ｂは、それぞれドライブ回路用正側電源１３a，１３ｂ、ドライブ回路用負側電源１４a，１４ｂ、ＮＰＮトランジスタ１１ａ，１１ｂ、ＰＮＰトランジスタ１２ａ，１２ｂ、制御信号入力端子１５a，１５ｂ、駆動信号出力端子１６ａ，１６ｂを備える。半導体電力変換装置は、クランプ用コンデンサ４a，４ｂ、逆流防止用ダイオード５a，５ｂ、充放電用抵抗６a，６ｂからなる回路部分がＩＧＢＴ１a，１ｂのターンオフによるサージ電圧を抑制するよう動作する。 The semiconductor power conversion device shown in FIG. 1 includes an IGBT 1a, 1b having a gate G, a collector C, and an emitter E, a freewheeling diode 2a, 2b, a gate resistor 3a, 3b, a clamping capacitor 4a, 4b, and a backflow prevention diode 5a, It includes 5b, charging / discharging resistors 6a and 6b, a DC power supply 7, an output terminal 8 for outputting AC power, and drive circuits 10a and 10b for driving the IGBTs 1a and 1b. The drive circuits 10a and 10b include positive power supplies 13a and 13b for the drive circuit, negative power supplies 14a and 14b for the drive circuit, NPN transistors 11a and 11b, PNP transistors 12a and 12b, control signal input terminals 15a and 15b, and drive signals, respectively. The output terminals 16a and 16b are provided. The semiconductor power conversion device operates so that the circuit portion including the clamping capacitors 4a and 4b, the backflow prevention diodes 5a and 5b, and the charge and discharge resistors 6a and 6b suppress the surge voltage due to the turn-off of the IGBTs 1a and 1b.
　ＩＧＢＴ１a，１ｂが第１の半導体スイッチング素子、第２の半導体スイッチング素子の一例であり、ゲート抵抗３ａ，３ｂが第１のゲート抵抗、第２のゲート抵抗の一例であり、クランプ用コンデンサ４a，４ｂが第１のクランプ用コンデンサ、第２のクランプ用コンデンサの一例であり、逆流防止用ダイオード５a，５ｂが第１の逆流防止用ダイオード、第２の逆流防止用ダイオードの一例であり、充放電用抵抗６a，６ｂが第１の充放電用抵抗、第２の充放電用抵抗の一例であり、ドライブ回路１０ａ，１０ｂが第１のドライブ回路、第２のドライブ回路の一例である。また、ＩＧＢＴ１ａ，１ｂが備えるコレクタＣ、エミッタＥ、ゲートＧが、半導体スイッチング素子の第１の端子、第２の端子、第３の端子の一例である。 IGBTs 1a and 1b are examples of a first semiconductor switching element and a second semiconductor switching element, gate resistors 3a and 3b are examples of a first gate resistor and a second gate resistor, and clamping capacitors 4a and 4b. Is an example of a first clamp capacitor and a second clamp capacitor, and backflow prevention diodes 5a and 5b are examples of a first backflow prevention diode and a second backflow prevention diode for charging and discharging. The resistors 6a and 6b are examples of the first charge / discharge resistor and the second charge / discharge resistor, and the drive circuits 10a and 10b are examples of the first drive circuit and the second drive circuit. Further, the collector C, the emitter E, and the gate G included in the IGBTs 1a and 1b are examples of the first terminal, the second terminal, and the third terminal of the semiconductor switching element.
　アーム上側の回路構成は、次のような構成になっている。まず、ＩＧＢＴ１ａは、コレクタＣが直流電源７の正極側に接続され、エミッタＥが出力端子８に接続され、ゲートＧがゲート抵抗３ａの一端に接続される。還流ダイオード２ａは、アノードがＩＧＢＴ１aのエミッタＥに接続され、カソードがＩＧＢＴ１aのコレクタＣに接続される。クランプ用コンデンサ４aは、一端が逆流防止用ダイオード５aのアノードに接続され、他端がＩＧＢＴ１ａのコレクタＣに接続される。逆流防止用ダイオード５aは、カソードがＩＧＢＴ１ａのゲートＧに接続される。ドライブ回路１０ａは、駆動信号出力端子１６ａがゲート抵抗３ａの他端に接続される。駆動信号出力端子１６ａは、ＮＰＮトランジスタ１１ａ、及びＰＮＰトランジスタ１２ａのエミッタＥに接続される。制御信号入力端子１５ａは、ＮＰＮトランジスタ１１ａ、及びＰＮＰトランジスタ１２ａのベースＢに接続される。ドライブ回路用正側電源１３aは、正極端子がＮＰＮトランジスタ１１ａのコレクタＣに接続され、負極端子がＩＧＢＴ１ａのエミッタＥに接続される。ドライブ回路用負側電源１４aは、負極端子がＰＮＰトランジスタ１２ａのコレクタＣに接続され、正極端子がＩＧＢＴ１ａのエミッタＥに接続される。充放電用抵抗６aは、一端が直流電源７の負極側に接続され、他端が逆流防止用ダイオード５aのアノードに接続される。 The circuit configuration on the upper side of the arm is as follows. First, in the IGBT 1a, the collector C is connected to the positive electrode side of the DC power supply 7, the emitter E is connected to the output terminal 8, and the gate G is connected to one end of the gate resistor 3a. In the freewheeling diode 2a, the anode is connected to the emitter E of the IGBT 1a and the cathode is connected to the collector C of the IGBT 1a. One end of the clamping capacitor 4a is connected to the anode of the backflow prevention diode 5a, and the other end is connected to the collector C of the IGBT 1a. The cathode of the backflow prevention diode 5a is connected to the gate G of the IGBT 1a. In the drive circuit 10a, the drive signal output terminal 16a is connected to the other end of the gate resistor 3a. The drive signal output terminal 16a is connected to the NPN transistor 11a and the emitter E of the PNP transistor 12a. The control signal input terminal 15a is connected to the NPN transistor 11a and the base B of the PNP transistor 12a. In the drive circuit positive power supply 13a, the positive electrode terminal is connected to the collector C of the NPN transistor 11a, and the negative electrode terminal is connected to the emitter E of the IGBT 1a. In the drive circuit negative power supply 14a, the negative electrode terminal is connected to the collector C of the PNP transistor 12a, and the positive electrode terminal is connected to the emitter E of the IGBT 1a. One end of the charge / discharge resistor 6a is connected to the negative electrode side of the DC power supply 7, and the other end is connected to the anode of the backflow prevention diode 5a.
　また、アーム下側の回路構成についても、アーム上側の回路構成とほぼ同様な構成になる。具体的には、ＩＧＢＴ１ｂは、コレクタＣが出力端子８に接続され、エミッタＥが直流電源７の負極側に接続され、ゲートＧがゲート抵抗３ｂの一端に接続される。還流ダイオード２ｂは、アノードがＩＧＢＴ１ｂのエミッタＥに接続され、カソードがＩＧＢＴ１ｂのコレクタＣに接続される。クランプ用コンデンサ４ｂは、一端が逆流防止用ダイオード５ｂのカソードに接続され、他端がＩＧＢＴ１ｂのゲートＧに接続される。逆流防止用ダイオード５ｂは、アノードがＩＧＢＴ１ｂのコレクタＣに接続される。ドライブ回路１０ｂは、駆動信号出力端子１６ｂがゲート抵抗３ｂの他端に接続される。駆動信号出力端子１６ｂは、ＮＰＮトランジスタ１１ｂ、及びＰＮＰトランジスタ１２ｂのエミッタＥに接続される。制御信号入力端子１５ｂは、ＮＰＮトランジスタ１１ｂ、及びＰＮＰトランジスタ１２ｂのベースＢに接続される。ドライブ回路用正側電源１３ｂは、ＮＰＮトランジスタ１１ｂのコレクタＣに接続され、負極端子がＩＧＢＴ１ｂのエミッタＥに接続される。ドライブ回路用負側電源１４ｂは、負極端子がＰＮＰトランジスタ１２ｂのコレクタＣに接続され、正極端子がＩＧＢＴ１ｂのエミッタＥに接続される。充放電用抵抗６ｂは、一端が直流電源７の正極側に接続され、他端が逆流防止用ダイオード５ｂのカソードに接続される。 Also, the circuit configuration on the lower side of the arm is almost the same as the circuit configuration on the upper side of the arm. Specifically, in the IGBT 1b, the collector C is connected to the output terminal 8, the emitter E is connected to the negative electrode side of the DC power supply 7, and the gate G is connected to one end of the gate resistor 3b. In the freewheeling diode 2b, the anode is connected to the emitter E of the IGBT 1b and the cathode is connected to the collector C of the IGBT 1b. One end of the clamping capacitor 4b is connected to the cathode of the backflow prevention diode 5b, and the other end is connected to the gate G of the IGBT 1b. The anode of the backflow prevention diode 5b is connected to the collector C of the IGBT 1b. In the drive circuit 10b, the drive signal output terminal 16b is connected to the other end of the gate resistor 3b. The drive signal output terminal 16b is connected to the NPN transistor 11b and the emitter E of the PNP transistor 12b. The control signal input terminal 15b is connected to the base B of the NPN transistor 11b and the PNP transistor 12b. The positive power supply 13b for the drive circuit is connected to the collector C of the NPN transistor 11b, and the negative electrode terminal is connected to the emitter E of the IGBT 1b. In the drive circuit negative power supply 14b, the negative electrode terminal is connected to the collector C of the PNP transistor 12b, and the positive electrode terminal is connected to the emitter E of the IGBT 1b. One end of the charge / discharge resistor 6b is connected to the positive electrode side of the DC power supply 7, and the other end is connected to the cathode of the backflow prevention diode 5b.
　また、図２（a）乃至（ｄ）は、本開示の実施の形態にかかる半導体電力変換装置における半導体スイッチング素子の各部の電圧および電流、またはターンオフ損失の時間的変動を示す特性図であって、（a）はＩＧＢＴ1ａ，１ｂのゲート・エミッタ間電圧Ｖｇｅ、（ｂ）はＩＧＢＴ1ａ，１ｂのコレクタ・エミッタ間電圧Ｖｃｅ、（ｃ）はＩＧＢＴ1ａ，１ｂのコレクタ電流Ｉｃ、（ｄ）はＩＧＢＴ1ａ，１ｂのターンオフ損失である。なお、図２には、比較例として、図４に示すようなサージ電圧抑制回路を設けていない半導体電力変換装置における半導体スイッチング素子の特性も示している。 2 (a) to 2 (d) are characteristic diagrams showing the time variation of the voltage and current of each part of the semiconductor switching element in the semiconductor power conversion device according to the embodiment of the present disclosure, or the turn-off loss. , (A) is the gate-emitter voltage Vge of the IGBTs 1a and 1b, (b) is the collector-emitter voltage Vce of the IGBTs 1a and 1b, (c) is the collector current Ic of the IGBTs 1a and 1b, and (d) is the IGBT 1a and 1b. Turn-off loss. Note that FIG. 2 also shows, as a comparative example, the characteristics of a semiconductor switching element in a semiconductor power conversion device not provided with the surge voltage suppression circuit as shown in FIG.
　図２（a）乃至（ｄ）において、実線で示した３1、３２、３３、３４は、実施の形態１にかかる半導体電力変換装置のＩＧＢＴ1ａ，１ｂに関する、ゲート・エミッタ間電圧Ｖｇｅの特性曲線、コレクタ・エミッタ間電圧Ｖｃｅの特性曲線、コレクタ電流Ｉｃの特性曲線、ターンオフ損失の特性曲線であり、一点鎖線で示した４1、４２、４３、４４は、後述する実施の形態２にかかる半導体電力変換装置のＩＧＢＴ1ａ，１ｂに関する、ゲート・エミッタ間電圧Ｖｇｅの特性曲線、コレクタ・エミッタ間電圧Ｖｃｅの特性曲線、コレクタ電流Ｉｃ、ターンオフ損失の特性曲線である。また、破線で示した２１、２２、２３、２４は、図４に示した半導体電力変換装置のＩＧＢＴ1ａ，１ｂに関する、ゲート・エミッタ間電圧Ｖｇｅの特性曲線、コレクタ・エミッタ間電圧Ｖｃｅの特性曲線、コレクタ電流Ｉｃ、ターンオフ損失の特性曲線であり、比較例として示すものである。 In FIGS. 2 (a) to 2 (d), 31, 32, 33, and 34 shown by solid lines are characteristic curves of the gate-emitter voltage Vge with respect to the IGBTs 1a and 1b of the semiconductor power conversion device according to the first embodiment. The characteristic curve of the collector-emitter voltage Vce, the characteristic curve of the collector current Ic, and the characteristic curve of the turn-off loss. It is a characteristic curve of the gate-emitter voltage Vge, the characteristic curve of the collector-emitter voltage Vce, the collector current Ic, and the characteristic curve of the turn-off loss with respect to the IGBTs 1a and 1b of the apparatus. 21, 22, 23, and 24 shown by broken lines are the characteristic curve of the gate-emitter voltage Vge and the characteristic curve of the collector-emitter voltage Vce with respect to the IGBTs 1a and 1b of the semiconductor power converter shown in FIG. It is a characteristic curve of a collector current Ic and a turn-off loss, and is shown as a comparative example.
　実施形態１における半導体電力変換装置の動作を、図１及び図２を用いて説明する。まず、アーム上側の回路の動作について説明する。 The operation of the semiconductor power conversion device according to the first embodiment will be described with reference to FIGS. 1 and 2. First, the operation of the circuit on the upper side of the arm will be described.
　制御信号入力端子1５ａより入力される制御信号によってドライブ回路１０ａの駆動信号出力端子１６ａから正極性パルスの駆動信号が出力されると、その駆動信号がゲート抵抗３ａを介してＩＧＢＴ１aのゲートＧに供給され、ＩＧＢＴ１aがターンオンする。このとき、クランプ用コンデンサ４ａの端子間電圧Ｖ４ａは充放電用抵抗６ａを介して直流電源７と同電圧に保持されている。 When the drive signal of the positive pulse is output from the drive signal output terminal 16a of the drive circuit 10a by the control signal input from the control signal input terminal 15a, the drive signal is supplied to the gate G of the IGBT 1a via the gate resistor 3a. Then, IGBT1a turns on. At this time, the voltage V4a between the terminals of the clamping capacitor 4a is held at the same voltage as the DC power supply 7 via the charging / discharging resistor 6a.
　次に、制御信号入力端子１５ａより入力される制御信号によって、ドライブ回路１０ａの駆動信号出力端子１６ａから出力される駆動信号が正極性パルスから負極性パルスに変化し、その負極性パルスがゲート抵抗３ａを介してＩＧＢＴ１aのゲートＧに供給されると、ＩＧＢＴ１aのゲートＧに蓄積されていた正電荷がゲート抵抗３ａを介して引き抜かれ、ＩＧＢＴ１aがターンオフする。 Next, the control signal input from the control signal input terminal 15a changes the drive signal output from the drive signal output terminal 16a of the drive circuit 10a from a positive pulse to a negative pulse, and the negative pulse changes to a gate resistance. When supplied to the gate G of the IGBT 1a via the 3a, the positive charge accumulated in the gate G of the IGBT 1a is extracted via the gate resistor 3a, and the IGBT 1a turns off.
　ＩＧＢＴ１aがターンオフした結果、ＩＧＢＴ１aのコレクタ・エミッタ間にサージ電圧が発生して、そのサージ電圧が、クランプ用コンデンサ４ａの端子間電圧Ｖ４ａと、ＩＧＢＴ１aのゲート・エミッタ間電圧Ｖｇｅ１aと、逆流防止用ダイオード５ａの順方向電圧Ｖ５aとを合計した電圧（以降、「アーム上側クランプ動作開始電圧」という）を超えると、アーム上側クランプ動作開始電圧を超えた電圧に対応する電流（以降、「アーム上側クランプ動作開始電流」という）がクランプ用コンデンサ４ａを介してゲートＧへ流れこむ。この結果、ゲート・エミッタ間電圧Ｖｇｅ１aは、図２（ａ）の特性曲線３１に示されるように、時刻ｔ１付近にて特性曲線２１に比べて一時的に上昇するように変化し、スレッショルド電圧に達すると、ＩＧＢＴ１ａがオンして、時刻ｔ２付近にてコレクタ・エミッタ間電圧Ｖｃｅ１ａがクランプ電圧Ｖｃｅｃｒにクランプされる。そして、ＩＧＢＴ１aのコレクタ・エミッタ間を流れるコレクタ電流Ｉｃ１aの電流変化（ｄｉ／ｄｔ）が図２（ｃ）の特性曲線３３に示されるように特性曲線２３に比べて緩やかになる。その結果、コレクタ・エミッタ間電圧Ｖｃｅ１aの特性曲線としては、図２（ｂ）の特性曲線３２に示されるように、特性曲線２２に比べてピーク値が低減され、サージ電圧がクランプされるような特性曲線になる。上記に置いて、アーム上側クランプ動作開始電圧が第1のクランプ動作開始電圧の一例である。 As a result of IGBT1a turning off, a surge voltage is generated between the collector and emitter of IGBT1a, and the surge voltage is the voltage between terminals V4a of the clamping capacitor 4a, the voltage Vge1a between the gate and emitter of IGBT1a, and the backflow prevention diode. When the sum of the forward voltage V5a of 5a and the voltage (hereinafter referred to as "arm upper clamp operation start voltage") is exceeded, the current corresponding to the voltage exceeding the arm upper clamp operation start voltage (hereinafter, "arm upper clamp operation start voltage") The "starting current") flows into the gate G via the clamping capacitor 4a. As a result, the gate-emitter voltage Vge1a changes so as to temporarily increase with respect to the characteristic curve 21 near time t1 as shown in the characteristic curve 31 of FIG. 2 (a), and becomes a threshold voltage. When it reaches, the IGBT 1a is turned on, and the collector-emitter voltage Vce1a is clamped to the clamp voltage Vcecr near time t2. Then, the current change (di / dt) of the collector current Ic1a flowing between the collector and the emitter of the IGBT 1a becomes gentler than that of the characteristic curve 23 as shown in the characteristic curve 33 of FIG. 2 (c). As a result, as the characteristic curve of the collector-emitter voltage Vce1a, as shown in the characteristic curve 32 of FIG. 2B, the peak value is reduced as compared with the characteristic curve 22, and the surge voltage is clamped. It becomes a characteristic curve. In the above, the arm upper clamp operation start voltage is an example of the first clamp operation start voltage.
　このとき、実施の形態１におけるクランプ電圧Ｖｃｅｃｒは下記式（１）で表すことができる。 At this time, the clamp voltage Vsecr in the first embodiment can be expressed by the following equation (1).
[数１]
　Ｖｃｅｃｒ＝Ｖ４ａ+Ｖｇｅ（ｔｈ）+Ｖ５ａ　　　　　・・・（１） [Number 1]
Vcecr = V4a + Vge (th) + V5a ... (1)
　式（１）において、Ｖｇｅ（ｔｈ）はＩＧＢＴ１ａのスレッショルド電圧を示している。クランプ用コンデンサ４ａの端子間電圧Ｖ４ａは直流電源７と同電圧まで充電されており、また、スレッショルド電圧Ｖｇｅ（ｔｈ）、逆流防止用ダイオード５aの順方向電圧Ｖ５ａは、直流電源電圧に対して十分小さいため、クランプ電圧Ｖｃｅｃｒは直流電源電圧とほぼ同等になる。 In equation (1), Vge (th) indicates the threshold voltage of IGBT 1a. The terminal voltage V4a of the clamping capacitor 4a is charged to the same voltage as the DC power supply 7, and the threshold voltage Vge (th) and the forward voltage V5a of the backflow prevention diode 5a are sufficient for the DC power supply voltage. Since it is small, the clamp voltage Vcecr is almost equal to the DC power supply voltage.
　次に、アーム下側の回路の動作について説明する。アーム下側の回路の動作は、アーム上側の回路と基本動作は同じである。具体的には、制御信号入力端子１５ｂより入力される制御信号によってドライブ回路１０ｂから正極性パルスの駆動信号が出力されると、その駆動信号がゲート抵抗３ｂを介してＩＧＢＴ１ｂのゲートＧに供給され、ＩＧＢＴ１ｂがターンオンする。このとき、クランプ用コンデンサ４ｂの端子間電圧Ｖ４ｂは充放電用抵抗６ｂを介して、制御信号入力端子１５ｂより入力される制御信号に応じて、直流電源７の電圧からドライブ回路用正側電源１３ｂを引いた電圧、又は直流電源７の電圧からドライブ回路用負側電源１４ｂを加えた電圧のいずれかに保持されている。但し、ドライブ回路用正側電源１３ｂ、ドライブ回路用負側電源１４ｂは直流電源７に比べて電圧が小さいため、クランプ用コンデンサ４ｂの端子間電圧Ｖ４ｂは、ほぼ直流電源７と同じ電圧に保持されている。 Next, the operation of the circuit on the lower side of the arm will be described. The operation of the circuit on the lower side of the arm is the same as that of the circuit on the upper side of the arm. Specifically, when the drive signal of the positive pulse is output from the drive circuit 10b by the control signal input from the control signal input terminal 15b, the drive signal is supplied to the gate G of the IGBT 1b via the gate resistor 3b. , IGBT1b turns on. At this time, the voltage V4b between the terminals of the clamping capacitor 4b is changed from the voltage of the DC power supply 7 to the positive power supply 13b for the drive circuit according to the control signal input from the control signal input terminal 15b via the charging / discharging resistor 6b. Is held at either the voltage obtained by subtracting the voltage of the DC power supply 7 or the voltage obtained by adding the negative power supply 14b for the drive circuit from the voltage of the DC power supply 7. However, since the positive power supply 13b for the drive circuit and the negative power supply 14b for the drive circuit have smaller voltages than the DC power supply 7, the terminal voltage V4b of the clamping capacitor 4b is maintained at substantially the same voltage as the DC power supply 7. ing.
　次に、制御信号入力端子１５ｂより入力される制御信号によって、ドライブ回路１０ｂの駆動信号出力端子１６ｂから出力される駆動信号が正極性パルスから負極性パルスに変化し、その負極性パルスがゲート抵抗３ｂを介してＩＧＢＴ１ｂのゲートＧに供給されると、ＩＧＢＴ１ｂのゲートＧに蓄積されていた正電荷がゲート抵抗３ｂを介して引き抜かれ、ＩＧＢＴ１ｂがターンオフする。 Next, the control signal input from the control signal input terminal 15b changes the drive signal output from the drive signal output terminal 16b of the drive circuit 10b from a positive pulse to a negative pulse, and the negative pulse changes to a gate resistance. When supplied to the gate G of the IGBT 1b via the 3b, the positive charge accumulated in the gate G of the IGBT 1b is withdrawn via the gate resistor 3b, and the IGBT 1b turns off.
　ＩＧＢＴ１ｂがターンオフした結果、ＩＧＢＴ１ｂのコレクタ・エミッタ間にサージ電圧が発生して、そのサージ電圧が、クランプ用コンデンサ４ｂの端子間電圧Ｖ４ｂと、ＩＧＢＴ１ｂのゲート・エミッタ間電圧Ｖｇｅ１ｂと、逆流防止用ダイオード５ｂの順方向電圧Ｖ５ｂとを合計した電圧（以降、「アーム下側クランプ動作開始電圧」という）を超えると、アーム下側クランプ動作開始電圧を超えた電圧に対応する電流（以降、「アーム下側クランプ動作開始電流」という）がクランプ用コンデンサ４ｂを介してゲートＧへ流れこむ。この結果、ゲート・エミッタ間電圧Ｖｇｅ１ｂは、図２（ａ）の特性曲線３１に示されるように、時刻ｔ１付近にて特性曲線２１に比べて一時的に上昇するように変化し、スレッショルド電圧に達すると、ＩＧＢＴ１ｂがオンして、時刻ｔ２付近にてコレクタ・エミッタ間電圧Ｖｃｅ１ｂが式（１）と同様なクランプ電圧にクランプされる。そして、ＩＧＢＴ１ｂのターンオフによるコレクタ・エミッタ間を流れるコレクタ電流Ｉｃ１ｂの電流変化（ｄｉ／ｄｔ）が図２（ｃ）の特性曲線３３に示されるように特性曲線２３に比べて緩やかになる。その結果、コレクタ・エミッタ間電圧Ｖｃｅ１ｂの特性曲線としては、図２（ｂ）の特性曲線３２に示されるように、特性曲線２２に比べてピーク値が低減され、サージ電圧がクランプされるような特性曲線になる。上記に置いて、アーム下側クランプ動作開始電圧が第２のクランプ動作開始電圧の一例である。 As a result of IGBT1b turning off, a surge voltage is generated between the collector and emitter of IGBT1b, and the surge voltage is the voltage between terminals V4b of the clamping capacitor 4b, the voltage Vge1b between the gate and emitter of IGBT1b, and the backflow prevention diode. When the sum of the forward voltage V5b of 5b and the voltage (hereinafter referred to as "arm lower clamp operation start voltage") is exceeded, the current corresponding to the voltage exceeding the arm lower clamp operation start voltage (hereinafter "arm lower"). The side clamping operation start current) flows into the gate G via the clamping capacitor 4b. As a result, the gate-emitter voltage Vge1b changes so as to temporarily increase with respect to the characteristic curve 21 near time t1 as shown in the characteristic curve 31 of FIG. 2 (a), and becomes a threshold voltage. When it reaches, the IGBT 1b is turned on, and the collector-emitter voltage Vce1b is clamped to the same clamping voltage as in the equation (1) near the time t2. Then, the current change (di / dt) of the collector current Ic1b flowing between the collector and the emitter due to the turn-off of the IGBT 1b becomes gentler than that of the characteristic curve 23 as shown in the characteristic curve 33 of FIG. 2 (c). As a result, as the characteristic curve of the collector-emitter voltage Vce1b, as shown in the characteristic curve 32 of FIG. 2B, the peak value is reduced as compared with the characteristic curve 22, and the surge voltage is clamped. It becomes a characteristic curve. In the above, the lower clamp operation start voltage of the arm is an example of the second clamp operation start voltage.
　サージ電圧によりクランプ用コンデンサ４ａ，４ｂに電流が流れることで、クランプ用コンデンサ４ａ，４ｂの端子間電圧は充電されて一時的に電圧が上昇するが、充放電用抵抗６ａ，６ｂを介して直流電源７に放電される。クランプ用コンデンサ４ａの放電は直流電源７と同電位になるまで放電される。クランプ用コンデンサ４ｂの放電は、制御信号入力端子１５ｂより入力される駆動信号に応じて、直流電源７の電圧からドライブ回路用正側電源１３ｂを引いた電圧、又は直流電源７の電圧にドライブ回路用負側電源１４ｂを加えた電圧と同電位になるまで放電される。但し、ドライブ回路用正側電源１３ｂ、ドライブ回路用負側電源１４ｂは直流電源７に比べて電圧が小さいため、クランプ用コンデンサ４ｂの放電は直流電源７とほぼ同電位になるまで放電される。このように、サージ電圧により充電されたクランプ用コンデンサ４ａ，４ｂが充放電用抵抗６ａ，６ｂを介して放電されることにより、半導体スイッチング素子の２回目以降のスイッチング時のクランプ動作開始電圧は、半導体スイッチング素子の1回目のスイッチング時のクランプ動作開始電圧と同じ電圧に維持される。このため、本開示の実施の形態にかかる半導体電力変換装置は、半導体スイッチング素子のスイッチングが繰り返し行われても、ターンオフしたときにコレクタ・エミッタ間に印可されるサージ電圧を安定して抑制することができる。 When a current flows through the clamping capacitors 4a and 4b due to the surge voltage, the voltage between the terminals of the clamping capacitors 4a and 4b is charged and the voltage rises temporarily, but DC is supplied via the charging / discharging resistors 6a and 6b. It is discharged to the power source 7. The clamp capacitor 4a is discharged until it reaches the same potential as the DC power supply 7. The discharge of the clamping capacitor 4b is the voltage obtained by subtracting the drive circuit positive power supply 13b from the voltage of the DC power supply 7 or the voltage of the DC power supply 7 according to the drive signal input from the control signal input terminal 15b. It is discharged until it reaches the same potential as the voltage to which the negative power supply 14b is applied. However, since the voltage of the drive circuit positive power supply 13b and the drive circuit negative power supply 14b is smaller than that of the DC power supply 7, the clamping capacitor 4b is discharged until the potential becomes substantially the same as that of the DC power supply 7. In this way, the clamping capacitors 4a and 4b charged by the surge voltage are discharged via the charging / discharging resistors 6a and 6b, so that the clamping operation start voltage at the time of the second and subsequent switching of the semiconductor switching element becomes. It is maintained at the same voltage as the clamp operation start voltage at the time of the first switching of the semiconductor switching element. Therefore, the semiconductor power conversion device according to the embodiment of the present disclosure stably suppresses the surge voltage applied between the collector and the emitter at the time of turn-off even if the semiconductor switching element is repeatedly switched. Can be done.
　また、クランプ用コンデンサ４ａ，４ｂから放電されるエネルギーは、クランプ用コンデンサ４ａ，４ｂに充電されている全エネルギーではなく、サージ電圧によって直流電源７よりも余分に充電されたエネルギーに限定されるため、放電損失を最小限に抑えることができ、充放電用抵抗６ａ，６ｂを小型化できる。また、充放電用抵抗６ａ，６ｂはコンデンサ４ａ，４ｂの充放電の通り道としてだけではなく、直流電源７からＩＧＢＴ１ａ，１ｂのゲートへ流れる電流を抑制するため、直流電源７の電圧が何らかの原因で急上昇した場合でも、クランプ用コンデンサ４ａ，４ｂを介してＩＧＢＴ１ａ，１ｂのゲートへ流れ込む電流を抑制し、ＩＧＢＴ１ａ，１ｂが誤ってスイッチングすることを防止することができる。 Further, the energy discharged from the clamping capacitors 4a and 4b is limited to the energy charged more than the DC power supply 7 by the surge voltage, not the total energy charged in the clamping capacitors 4a and 4b. The discharge loss can be minimized, and the charging / discharging resistors 6a and 6b can be miniaturized. Further, the charging / discharging resistors 6a and 6b are not only used as a charging / discharging path for the capacitors 4a and 4b, but also suppress the current flowing from the DC power supply 7 to the gates of the IGBTs 1a and 1b. Even when the voltage rises sharply, the current flowing into the gates of the IGBTs 1a and 1b via the clamping capacitors 4a and 4b can be suppressed, and the IGBTs 1a and 1b can be prevented from being erroneously switched.
　従って、本開示の実施の形態にかかる半導体電力変換装置は、ＩＧＢＴのコレクタ・ゲート間にクランプ用コンデンサを接続し、充放電用抵抗を介して直流電源からクランプ用コンデンサを充放電する構成にしたことにより、補助直流電源や、分圧抵抗を用いずに、クランプ動作開始電圧を設定することが可能となり、サージ電圧抑制回路を小型化しつつサージ電圧を抑制することができる。また、クランプ用コンデンサに余分に充電された電荷を充放電用抵抗を介して直流電源に放電する構成にしたことにより、半導体スイッチング素子のスイッチングが繰り返し行われてもクランプ動作開始電圧を所定の電圧に維持することができ、半導体スイッチング素子がターンオフしたときにコレクタ・エミッタ間に印可されるサージ電圧を安定して抑制できる。 Therefore, the semiconductor power conversion device according to the embodiment of the present disclosure has a configuration in which a clamping capacitor is connected between the collector and gate of the IGBT, and the clamping capacitor is charged and discharged from the DC power supply via the charging / discharging resistor. This makes it possible to set the clamp operation start voltage without using an auxiliary DC power supply or a voltage dividing resistor, and it is possible to suppress the surge voltage while reducing the size of the surge voltage suppression circuit. In addition, by configuring the clamp capacitor to discharge the excess charge to the DC power supply via the charging / discharging resistor, the clamping operation start voltage is set to a predetermined voltage even if the semiconductor switching element is repeatedly switched. It is possible to stably suppress the surge voltage applied between the collector and the emitter when the semiconductor switching element is turned off.
実施の形態２．
　サージ電圧抑制とターンオフ損失とは、トレードオフの関係にあり、サージ電圧抑制効果が高いとターンオフ損失は増加する。実施の形態１では、サージ電圧抑制効果を決めるクランプ電圧は、クランプ用コンデンサの端子間電圧（すなわち、直流電源電圧）と、半導体スイッチング素子のスレッショルド電圧と、逆流防止用ダイオードの順方向電圧で決定されてしまい、クランプ電圧を柔軟に調節することができないため、サージ電圧抑制とターンオフ損失増加のトレードオフを柔軟に調節することができなかった。実施の形態２では、クランプ電圧を柔軟に調節することができ、サージ電圧抑制とターンオフ損失増加のトレードオフを柔軟に調節することが可能な半導体電力変換装置について説明する。実施の形態１と同じ部分については説明を省略し、実施の形態１と異なる部分について説明する。 Embodiment 2.
There is a trade-off relationship between surge voltage suppression and turn-off loss, and if the surge voltage suppression effect is high, turn-off loss increases. In the first embodiment, the clamp voltage that determines the surge voltage suppression effect is determined by the voltage between the terminals of the clamp capacitor (that is, the DC power supply voltage), the threshold voltage of the semiconductor switching element, and the forward voltage of the backflow prevention diode. Since the clamp voltage cannot be adjusted flexibly, the trade-off between surge voltage suppression and increase in turn-off loss cannot be flexibly adjusted. In the second embodiment, a semiconductor power conversion device capable of flexibly adjusting the clamp voltage and flexibly adjusting the trade-off between surge voltage suppression and increase in turn-off loss will be described. The same parts as those of the first embodiment will be omitted, and the parts different from the first embodiment will be described.
　図３は、実施の形態２にかかる半導体電力変換装置の回路構成を示す図である。 FIG. 3 is a diagram showing a circuit configuration of the semiconductor power conversion device according to the second embodiment.
　図３に示す半導体電力変換装置は、クランプ動作開始電流を抑制するクランプ電流抑制抵抗９ａ，９ｂを備えており、その他の構成は図１と同じである。図１に図示された構成と同じ構成については同じ符号をつけている。クランプ電流抑制抵抗９ａ，９ｂが第１のクランプ電流抑制抵抗、第２のクランプ電流抑制抵抗の一例である。クランプ電流抑制抵抗９ａの一端は、ＩＧＢＴ１ａのコレクタＣに接続され、クランプ電流抑制抵抗９ａの他端は、逆流防止用ダイオード５aと接続しているクランプ用コンデンサ４ａの端子と反対側の端子に接続されている。クランプ電流抑制抵抗９ｂの一端は、ＩＧＢＴ１ｂのコレクタＣに接続され、クランプ電流抑制抵抗９ｂの他端は、逆流防止用ダイオード５ｂのアノードに接続されている。図３に示したクランプ電流抑制抵抗９ａ，９ｂの接続構成は一例であって、クランプ電流抑制抵抗９ａ，９ｂは、クランプ動作開始電流を抑制するように設けられていればよい。すなわち、クランプ電流抑制抵抗９ａは、ＩＧＢＴ１ａのコレクタＣとゲートＧとの間でクランプ用コンデンサ４ａに対して直列に接続され、クランプ電流抑制抵抗９ｂは、ＩＧＢＴ１ｂのコレクタＣとゲートＧとの間でクランプ用コンデンサ４ｂに対して直列に接続されていれば良い。 The semiconductor power conversion device shown in FIG. 3 includes clamp current suppression resistors 9a and 9b that suppress the clamp operation start current, and other configurations are the same as those in FIG. The same components as those shown in FIG. 1 are designated by the same reference numerals. The clamp current suppression resistors 9a and 9b are examples of the first clamp current suppression resistor and the second clamp current suppression resistor. One end of the clamp current suppression resistor 9a is connected to the collector C of the IGBT 1a, and the other end of the clamp current suppression resistor 9a is connected to the terminal opposite to the terminal of the clamp capacitor 4a connected to the backflow prevention diode 5a. Has been done. One end of the clamp current suppression resistor 9b is connected to the collector C of the IGBT 1b, and the other end of the clamp current suppression resistor 9b is connected to the anode of the backflow prevention diode 5b. The connection configuration of the clamp current suppression resistors 9a and 9b shown in FIG. 3 is an example, and the clamp current suppression resistors 9a and 9b may be provided so as to suppress the clamp operation start current. That is, the clamp current suppression resistor 9a is connected in series with the clamp capacitor 4a between the collector C and the gate G of the IGBT 1a, and the clamp current suppression resistor 9b is connected between the collector C and the gate G of the IGBT 1b. It suffices if it is connected in series with the clamping capacitor 4b.
　実施形態２における半導体電力変換装置の動作を、図２及び図３を用いて説明する。実施の形態１での説明と同様に、ＩＧＢＴ１ａ，１ｂのいずれかがターンオフしたことにより、ターンオフした方のＩＧＢＴのコレクタ・エミッタ間にサージ電圧が発生する。ＩＧＢＴ１ａがターンオフした場合でも、ＩＧＢＴ１ｂがターンオフした場合でも、動作は同じであるため、以降は一例として、アーム上側のＩＧＢＴ１ａがターンオフした場合について説明する。 The operation of the semiconductor power conversion device according to the second embodiment will be described with reference to FIGS. 2 and 3. Similar to the description in the first embodiment, when either of the IGBTs 1a and 1b is turned off, a surge voltage is generated between the collector and the emitter of the IGBT that has turned off. Since the operation is the same regardless of whether the IGBT 1a is turned off or the IGBT 1b is turned off, the case where the IGBT 1a on the upper side of the arm is turned off will be described below as an example.
　アーム上側のＩＧＢＴ１ａがターンオフしたことにより、ＩＧＢＴ１ａのコレクタ・エミッタ間にサージ電圧が発生すると、ＩＧＢＴ１ａのコレクタ・エミッタ間電圧Ｖｃｅ１ａから、アーム上側クランプ動作開始電圧を引いた電圧が、クランプ電流抑制抵抗９ａに印可される。このため、クランプ電流抑制抵抗９ａへの印可電圧をクランプ電流抑制抵抗９ａの抵抗値Ｒ９ａで割った電流がアーム上側クランプ動作開始電流として、ＩＧＢＴ１ａのコレクタＣよりゲート抵抗３ａに流れ、ゲート抵抗３ａにドライブ回路用負側電源１４ａと逆方向の電圧を発生させる。この結果、ゲート・エミッタ間電圧Ｖｇｅ１aは、一時的に上昇するように変化する。このときのＩＧＢＴ１ａのゲート・エミッタ間電圧Ｖｇｅ１ａは図２（ａ）の４１のような特性曲線を示す。すなわち、実施の形態２のＩＧＢＴ１ａのゲート・エミッタ間電圧Ｖｇｅ１ａの特性曲線４１は、時刻ｔ１付近にて一時的に上昇するが、クランプ電流抑制抵抗９ａによりアーム上側クランプ動作開始電流が制限されることにより、実施の形態１のゲート・エミッタ間電圧Ｖｇｅ１ａの特性曲線３１に比べ、ＩＧＢＴ１ａのターンオフ後のゲート・エミッタ間電圧Ｖｇｅ１ａの上昇が低減される。 When a surge voltage is generated between the collector and emitter of the IGBT 1a due to the turn-off of the IGBT 1a on the upper side of the arm, the voltage obtained by subtracting the clamp operation start voltage on the upper side of the arm from the collector-emitter voltage Vce1a of the IGBT 1a is the clamp current suppression resistor 9a. Is applied to. Therefore, the current obtained by dividing the applied voltage to the clamp current suppression resistance 9a by the resistance value R9a of the clamp current suppression resistance 9a flows from the collector C of the IGBT 1a to the gate resistance 3a as the arm upper clamp operation start current, and becomes the gate resistance 3a. A voltage is generated in the direction opposite to that of the drive circuit negative power supply 14a. As a result, the gate-emitter voltage Vge1a changes so as to temporarily increase. The gate-emitter voltage Vge1a of the IGBT 1a at this time shows a characteristic curve as shown in 41 of FIG. 2 (a). That is, the characteristic curve 41 of the gate-emitter voltage Vge1a of the IGBT 1a of the second embodiment temporarily rises near time t1, but the clamp operation start current on the upper side of the arm is limited by the clamp current suppression resistor 9a. As a result, the increase in the gate-emitter voltage Vge1a after the turn-off of the IGBT 1a is reduced as compared with the characteristic curve 31 of the gate-emitter voltage Vge1a of the first embodiment.
　このようなゲート・エミッタ間電圧Ｖｇｅ１ａの推移に従ってＩＧＢＴ１ａのゲート・エミッタ間電圧がスレッショルド電圧に達すると、ＩＧＢＴ１ａがオンして、コレクタ・エミッタ間電圧Ｖｃｅ１ａがクランプ電圧Ｖｃｅｃｒにクランプされる。このときのコレクタ・エミッタ間電圧Ｖｃｅ１ａの特性曲線は、図２（ｂ）の４２に示すような特性曲線になる。すなわち、実施の形態２のＩＧＢＴ１ａのコレクタ・エミッタ間電圧Ｖｃｅ１ａの特性曲線４２は、実施の形態１のＩＧＢＴ１ａのコレクタ・エミッタ間電圧Ｖｃｅ１ａの特性曲線３２に比べて、時刻ｔ２付近におけるターンオフ直後の電圧の上昇は若干高くなるが、それ以降は定常状態の電圧に早く収束する。 When the gate-emitter voltage of the IGBT 1a reaches the threshold voltage according to such a transition of the gate-emitter voltage Vge1a, the IGBT 1a is turned on and the collector-emitter voltage Vce1a is clamped to the clamp voltage Vcecr. The characteristic curve of the collector-emitter voltage Vce1a at this time is a characteristic curve as shown in 42 of FIG. 2 (b). That is, the characteristic curve 42 of the collector-emitter voltage Vce1a of the IGBT 1a of the second embodiment is the voltage immediately after the turn-off near the time t2 as compared with the characteristic curve 32 of the collector-emitter voltage Vce1a of the IGBT 1a of the first embodiment. The rise of is slightly higher, but after that, it quickly converges to the steady state voltage.
　このときのクランプ電圧Ｖｃｅｃｒは下記式（２）で表すことができる。 The clamp voltage Vcecr at this time can be expressed by the following equation (2).
［数２］
　Ｖｃｅｃｒ＝Ｖ４ａ+（Ｖｇｅ（ｔｈ）+Ｖ１４ａ）×Ｒ９ａ/Ｒ３ａ
　　　　　　　+Ｖ５ａ+Ｖｇｅ（ｔｈ）　　　　　　　　　・・・（２） [Number 2]
Vcecr = V4a + (Vge (th) + V14a) x R9a / R3a
+ V5a + Vge (th) ・ ・ ・ (2)
　式（２）において、Ｖ４ａはクランプ用コンデンサ４ａの端子間電圧、Ｖｇｅ（ｔｈ）はＩＧＢＴ１ａのスレッショルド電圧、Ｖ１４ａはドライブ回路用負側電源１４ａの電圧、Ｒ９ａはクランプ電流抑制抵抗９ａの抵抗値、Ｒ３ａはゲート抵抗３ａの抵抗値、Ｖ５ａは逆流防止用ダイオード５aの順方向電圧を示している。逆流防止用ダイオード５aの順方向電圧Ｖ５ａ、ＩＧＢＴ１ａのスレッショルド電圧Ｖｇｅ（ｔｈ）は、ＩＧＢＴ１ａのコレクタ・エミッタ間電圧Ｖｃｅ１ａに対して十分小さいため、第２項の（Ｖｇｅ（ｔｈ）+Ｖ１４ａ）×Ｒ９ａ/Ｒ３ａにてクランプ電圧を支配的に調節することができる。 In the formula (2), V4a is the voltage between the terminals of the clamping capacitor 4a, Vge (th) is the threshold voltage of the IGBT 1a, V14a is the voltage of the negative power supply 14a for the drive circuit, and R9a is the resistance value of the clamping current suppression resistor 9a. R3a indicates the resistance value of the gate resistance 3a, and V5a indicates the forward voltage of the backflow prevention diode 5a. Since the forward voltage V5a of the backflow prevention diode 5a and the threshold voltage Vge (th) of the IGBT 1a are sufficiently smaller than the collector-emitter voltage Vce1a of the IGBT 1a, the second term (Vge (th) + V14a) × R9a The clamp voltage can be predominantly adjusted with / R3a.
　クランプ用コンデンサ４ａの端子間電圧Ｖ４ａはサージ電圧が発生した際に、ＩＧＢＴ１ａのコレクタから流れ込むクランプ動作開始電流Iｃｒによって充電される。クランプ動作開始電流Iｃｒは下記式（３）で表すことができる。 The inter-terminal voltage V4a of the clamp capacitor 4a is charged by the clamp operation start current Icr flowing from the collector of the IGBT 1a when a surge voltage is generated. The clamp operation start current Icr can be expressed by the following equation (3).
［数３］
　Iｃｒ＝（Ｖｃｅ１ａ－Ｖｇｅ１ａ－Ｖ４ａ－Ｖ５ａ）/Ｒ９ａ・・（３） [Number 3]
Icr = (Vce1a-Vge1a-V4a-V5a) / R9a ... (3)
　ＩＧＢＴ１ａのコレクタＣからクランプ用コンデンサ４ａに流れ込むクランプ動作開始電流Iｃｒに対して、クランプ用コンデンサ４ａの容量が十分でないと、クランプ用コンデンサ４ａの端子間電圧Ｖ４ａが電圧上昇してしまい、クランプ電圧Ｖｃｅｃｒが当初予定していた電圧より高くなってしまうので、ＩＧＢＴ１ａに過大なサージ電圧が印可される恐れがある。このため、クランプ用コンデンサ４ａの容量については、ＩＧＢＴ１ａのコレクタＣからクランプ用コンデンサ４ａに流れ込むクランプ動作開始電流Iｃｒに対して、適切な容量のコンデンサを選定する必要がある。 If the capacitance of the clamp capacitor 4a is not sufficient with respect to the clamp operation start current Icr flowing from the collector C of the IGBT 1a into the clamp capacitor 4a, the voltage V4a between the terminals of the clamp capacitor 4a rises, and the clamp voltage Vcecr Will be higher than the originally planned voltage, so there is a risk that an excessive surge voltage will be applied to the IGBT 1a. Therefore, regarding the capacitance of the clamping capacitor 4a, it is necessary to select a capacitor having an appropriate capacitance with respect to the clamping operation start current Icr flowing from the collector C of the IGBT 1a into the clamping capacitor 4a.
　実施の形態２に示す前述のクランプ動作により、ＩＧＢＴ１ａのコレクタ・エミッタ間電圧Ｖｃｅ１ａがクランプされ、ＩＧＢＴ１ａが、ゲート・エミッタ間電圧Ｖｇｅ１ａの特性曲線４１、及びコレクタ・エミッタ間電圧Ｖｃｅ１ａの特性曲線４２のような特性曲線を示すとき、ＩＧＢＴ１ａのコレクタ電流Ｉｃ１ａの特性曲線は、図２（ｃ）の４３に示される特性曲線を示す。このとき、図２（ｃ）の４３のコレクタ電流Ｉｃの電流変化（ｄｉ/ｄｔ）の傾きは、図２（ｃ）の３３のコレクタ電流Ｉｃの電流変化（ｄｉ/ｄｔ）の傾きに比べて、大きくなる。このように、クランプ電流抑制抵抗９ａはコレクタ電流Ｉｃの電流変化（ｄｉ/ｄｔ）の傾きを調節する働きがある。図２（ｃ）の４３のコレクタ電流Ｉｃの電流変化（ｄｉ/ｄｔ）の傾きが、図２（ｃ）の３３のコレクタ電流Ｉｃの電流変化（ｄｉ/ｄｔ）の傾きよりも、大きくなった結果、図２（ｄ）に示されるように、ＩＧＢＴ１ａのターンオフ損失４４は、ターンオフ損失３４に比べて低減される。 By the above-mentioned clamping operation shown in the second embodiment, the collector-emitter voltage Vce1a of the IGBT 1a is clamped, and the IGBT 1a has the characteristic curve 41 of the gate-emitter voltage Vge1a and the characteristic curve 42 of the collector-emitter voltage Vce1a. When showing such a characteristic curve, the characteristic curve of the collector current Ic1a of the IGBT 1a shows the characteristic curve shown in 43 of FIG. 2 (c). At this time, the slope of the current change (di / dt) of the collector current Ic of 43 in FIG. 2 (c) is compared with the slope of the current change (di / dt) of the collector current Ic of 33 in FIG. 2 (c). ,growing. As described above, the clamp current suppression resistor 9a has a function of adjusting the inclination of the current change (di / dt) of the collector current Ic. The slope of the current change (di / dt) of the collector current Ic of 43 in FIG. 2 (c) became larger than the slope of the current change (di / dt) of the collector current Ic of 33 in FIG. 2 (c). As a result, as shown in FIG. 2D, the turn-off loss 44 of the IGBT 1a is reduced as compared with the turn-off loss 34.
　従って、本実施の形態２によれば、半導体電力変換装置は、ＩＧＢＴのコレクタ・ゲート間のクランプ用コンデンサに直列に設けたクランプ電流抑制抵抗により、柔軟にＩＧＢＴのコレクタ・エミッタ間のクランプ電圧を調節し、サージ電圧抑制とターンオフ損失増加のトレードオフを柔軟に調節することができるので、クランプ電流抑制抵抗に適切な抵抗値を選定することによって、ターンオフ損失の許容範囲内で所望のサージ電圧抑制効果を得ることができる。 Therefore, according to the second embodiment, the semiconductor power converter flexibly adjusts the clamping voltage between the collector and the emitter of the IGBT by the clamping current suppression resistor provided in series with the clamping capacitor between the collector and the gate of the IGBT. Since it can be adjusted to flexibly adjust the trade-off between surge voltage suppression and increase in turn-off loss, the desired surge voltage suppression within the allowable range of turn-off loss can be achieved by selecting an appropriate resistance value for the clamp current suppression resistance. The effect can be obtained.
　なお、上記具体例では、半導体スイッチング素子をＩＧＢＴとして説明したがＭＯＳＦＥＴ（Ｍｅｔａｌ－Ｏｘｉｄｅ－Ｓｅｍｉｃｏｎｄｕｃｔｏｒ　Ｆｉｅｌｄ　Ｅｆｆｅｃｔ　Ｔｒａｎｓｉｓｔｏｒ）に置き換えても同様の作用・効果を得ることができる。ＭＯＳＦＥＴに置き換えた場合、コレクタＣをドレインＤ、エミッタＥをソースＳに置き換えるように半導体スイッチング素子を構成する。この場合、ＭＯＳＦＥＴが備えるドレインＤ、ソースＳ、ゲートＧが、半導体スイッチング素子の第１の端子、第２の端子、第３の端子の一例である。 In the above specific example, the semiconductor switching element has been described as an IGBT, but the same action / effect can be obtained by replacing the semiconductor switching element with a MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor). When replaced with a MOSFET, the semiconductor switching element is configured so that the collector C is replaced with the drain D and the emitter E is replaced with the source S. In this case, the drain D, the source S, and the gate G included in the MOSFET are examples of the first terminal, the second terminal, and the third terminal of the semiconductor switching element.
　以上の実施の形態に示した構成は、本開示の内容の一例を示すものであり、別の公知の技術と組合せることも可能であるし、本開示の要旨を逸脱しない範囲で、構成の一部を省略、変更することも可能である。 The configuration shown in the above-described embodiment shows an example of the contents of the present disclosure, can be combined with another known technique, and has a configuration within a range that does not deviate from the gist of the present disclosure. It is also possible to omit or change a part.
　１ａ,１ｂ　ＩＧＢＴ、２ａ,２ｂ　還流ダイオード、３ａ,３ｂ　ゲート抵抗、４ａ,４ｂ　クランプ用コンデンサ、５ａ,５ｂ　逆流防止用ダイオード、６ａ,６ｂ　充放電用抵抗、７　直流電源、８　出力端子、９ａ,９ｂ　クランプ電流抑制抵抗、１０ａ,１０ｂ　ドライブ回路、１１ａ,１１ｂ　ＮＰＮトランジスタ、１２ａ,１２ｂ　ＰＮＰトランジスタ、１３ａ,１３ｂ　ドライブ回路用正側電源、１４ａ,１４ｂ　ドライブ回路用負側電源、１５ａ,１５ｂ　制御信号入力端子、１６ａ,１６ｂ　駆動信号出力端子。 1a, 1b IGBT, 2a, 2b freewheeling diode, 3a, 3b gate resistance, 4a, 4b clamp capacitor, 5a, 5b backflow prevention diode, 6a, 6b charge / discharge resistor, 7 DC power supply, 8 output terminal, 9a, 9b Clamp current suppression diode, 10a, 10b drive circuit, 11a, 11b NPN transistor, 12a, 12b PNP transistor, 13a, 13b positive power supply for drive circuit, 14a, 14b negative power supply for drive circuit, 15a, 15b control signal input Terminals, 16a, 16b drive signal output terminals.

Claims (3)

  1. 　第１の端子が直流電源の正極側に接続され、第２の端子が交流電力を出力する出力端子に接続された第１の半導体スイッチング素子と、第２の端子が前記直流電源の負極側に接続され、第１の端子が前記出力端子に接続された第２の半導体スイッチング素子とを有し、前記第１の半導体スイッチング素子と前記第２の半導体スイッチング素子とを交互にオン・オフさせることで、直流電力から前記交流電力へ電力変換を行う半導体電力変換装置であって、
    　カソードが前記第１の半導体スイッチング素子の第３の端子に接続された第１の逆流防止用ダイオードと、
    　一端が前記第１の半導体スイッチング素子の第１の端子に接続され、他端が前記第１の逆流防止用ダイオードのアノードに接続された第１のクランプ用コンデンサと、
    　一端が前記第１の半導体スイッチング素子の第３の端子に接続された第１のゲート抵抗と、
    　駆動信号出力端子が前記第１のゲート抵抗の他端に接続され、前記第１の半導体スイッチング素子を駆動する第１のドライブ回路と、
    　一端が前記直流電源の負極側に接続され、他端が前記第１の逆流防止用ダイオードのアノードに接続された第１の充放電用抵抗と、
    　アノードが前記第２の半導体スイッチング素子の第１の端子に接続された第２の逆流防止用ダイオードと、
    　一端が前記第２の半導体スイッチング素子の第３の端子に接続され、他端が前記第２の逆流防止用ダイオードのカソードに接続された第２のクランプ用コンデンサと、
    　一端が前記第２の半導体スイッチング素子の第３の端子に接続された第２のゲート抵抗と、
    　駆動信号出力端子が前記第２のゲート抵抗の他端に接続され、前記第２の半導体スイッチング素子を駆動する第２のドライブ回路と、
    　一端が前記直流電源の正極側に接続され、他端が前記第２の逆流防止用ダイオードのカソードに接続された第２の充放電用抵抗と、
    　を備えたことを特徴とする半導体電力変換装置。     The first semiconductor switching element in which the first terminal is connected to the positive side of the DC power supply and the second terminal is connected to the output terminal for outputting AC power, and the second terminal is on the negative side of the DC power supply. Having a second semiconductor switching element connected and having a first terminal connected to the output terminal, the first semiconductor switching element and the second semiconductor switching element are alternately turned on and off. It is a semiconductor power conversion device that converts DC power to the AC power.
    A first backflow prevention diode whose cathode is connected to the third terminal of the first semiconductor switching element, and
    A first clamp capacitor having one end connected to the first terminal of the first semiconductor switching element and the other end connected to the anode of the first backflow prevention diode.
    A first gate resistor whose one end is connected to the third terminal of the first semiconductor switching element,
    A first drive circuit in which a drive signal output terminal is connected to the other end of the first gate resistor to drive the first semiconductor switching element, and
    A first charge / discharge resistor having one end connected to the negative electrode side of the DC power supply and the other end connected to the anode of the first backflow prevention diode.
    A second backflow prevention diode whose anode is connected to the first terminal of the second semiconductor switching element, and
    A second clamping capacitor having one end connected to the third terminal of the second semiconductor switching element and the other end connected to the cathode of the second backflow prevention diode.
    A second gate resistor whose end is connected to the third terminal of the second semiconductor switching element,
    A second drive circuit in which a drive signal output terminal is connected to the other end of the second gate resistor to drive the second semiconductor switching element, and
    A second charge / discharge resistor having one end connected to the positive electrode side of the DC power supply and the other end connected to the cathode of the second backflow prevention diode.
    A semiconductor power converter characterized by being equipped with.
  2. 　前記第１の半導体スイッチング素子がターンオフしたことにより、前記第１の半導体スイッチング素子の第１の端子と第２の端子との間にサージ電圧が発生した場合、前記サージ電圧が、前記第１のクランプ用コンデンサの端子間電圧と、前記第１の半導体スイッチング素子の第２の端子と第３の端子との間の電圧と、前記第１の逆流防止用ダイオードの順方向電圧とを合計した電圧である第１のクランプ動作開始電圧を超えると、前記第１のクランプ動作開始電圧を超えた電圧に対応する電流が前記第１のクランプ用コンデンサを介して前記第１の半導体スイッチング素子の第３の端子へ流れこみ、前記サージ電圧をクランプするとともに、前記第１のクランプ用コンデンサに充電された電荷を前記第１の充放電用抵抗を介して前記直流電源に放電し、
    　前記第２の半導体スイッチング素子がターンオフしたことにより、前記第２の半導体スイッチング素子の第１の端子と第２の端子との間にサージ電圧が発生した場合、前記サージ電圧が、前記第２のクランプ用コンデンサの端子間電圧と、前記第２の半導体スイッチング素子の第２の端子と第３の端子との間の電圧と、前記第２の逆流防止用ダイオードの順方向電圧とを合計した電圧である第２のクランプ動作開始電圧を超えると、前記第２のクランプ動作開始電圧を超えた電圧に対応する電流が前記第２のクランプ用コンデンサを介して前記第２の半導体スイッチング素子の第３の端子へ流れこみ、前記サージ電圧をクランプするとともに、前記第２のクランプ用コンデンサに充電された電荷を前記第２の充放電用抵抗を介して前記直流電源に放電することを特徴とする請求項１に記載の半導体電力変換装置。     When a surge voltage is generated between the first terminal and the second terminal of the first semiconductor switching element due to the turn-off of the first semiconductor switching element, the surge voltage becomes the first The sum of the voltage between the terminals of the clamping capacitor, the voltage between the second terminal and the third terminal of the first semiconductor switching element, and the forward voltage of the first backflow prevention diode. When the first clamp operation start voltage is exceeded, a current corresponding to the voltage exceeding the first clamp operation start voltage reaches the third of the first semiconductor switching element via the first clamp capacitor. The surge voltage is clamped, and the charge charged in the first clamping capacitor is discharged to the DC power supply via the first charging / discharging resistor.
    When a surge voltage is generated between the first terminal and the second terminal of the second semiconductor switching element due to the turn-off of the second semiconductor switching element, the surge voltage becomes the second terminal. The sum of the voltage between the terminals of the clamping capacitor, the voltage between the second terminal and the third terminal of the second semiconductor switching element, and the forward voltage of the second backflow prevention diode. When the second clamp operation start voltage is exceeded, a current corresponding to the voltage exceeding the second clamp operation start voltage reaches the third of the second semiconductor switching element via the second clamp capacitor. The claim is characterized in that it flows into the terminal of the above, clamps the surge voltage, and discharges the charge charged in the second clamping capacitor to the DC power supply via the second charging / discharging resistor. Item 2. The semiconductor power conversion device according to Item 1.
  3. 　前記第１の半導体スイッチング素子の第１の端子と第３の端子との間で前記第１のクランプ用コンデンサに対して直列に接続された第１のクランプ電流抑制抵抗と、
    　前記第２の半導体スイッチング素子の第１の端子と第３の端子との間で前記第２のクランプ用コンデンサに対して直列に接続された第２のクランプ電流抑制抵抗と、
    　を備えたことを特徴とする請求項１、又は請求項２に記載の半導体電力変換装置。     A first clamp current suppression resistor connected in series with the first clamp capacitor between the first terminal and the third terminal of the first semiconductor switching element.
    A second clamp current suppression resistor connected in series with the second clamp capacitor between the first terminal and the third terminal of the second semiconductor switching element, and
    The semiconductor power conversion device according to claim 1 or 2, wherein the semiconductor power conversion device is provided.
PCT/JP2021/001419 2021-01-18 2021-01-18 Semiconductor power conversion device WO2022153521A1 (en)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009273244A (en) * 2008-04-11 2009-11-19 Nippon Soken Inc Switching circuit
JP2013201590A (en) * 2012-03-24 2013-10-03 Toshiba Corp Fet drive circuit and fet module
JP2019129565A (en) * 2018-01-23 2019-08-01 日産自動車株式会社 Driving device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009273244A (en) * 2008-04-11 2009-11-19 Nippon Soken Inc Switching circuit
JP2013201590A (en) * 2012-03-24 2013-10-03 Toshiba Corp Fet drive circuit and fet module
JP2019129565A (en) * 2018-01-23 2019-08-01 日産自動車株式会社 Driving device

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