WO2022146474A1

WO2022146474A1 - Apparatus and method of configurable reduction to signal resolution

Info

Publication number: WO2022146474A1
Application number: PCT/US2021/029225
Authority: WO
Inventors: Jian Gu
Original assignee: Zeku, Inc.
Priority date: 2021-01-04
Filing date: 2021-04-26
Publication date: 2022-07-07

Abstract

According to one embodiment, an apparatus for digital signal processing is disclosed. The apparatus may include a first signal processing circuit and a first resolution reduction circuit. The first signal processing circuit may process first signals with a first bit-width. The first resolution reduction circuit may receive a first resolution configuration signal configuring a first resolution reduction. The first resolution reduction circuit may further receive a first signal with the first bit-width and a first resolution. The first resolution reduction circuit may generate a second signal with the first bit-width and a second resolution by applying a first resolution reduction function to the first signal. The first resolution reduction function may be associated with the first resolution reduction. The second resolution may be lower than the first resolution. The first resolution reduction circuit may output the second signal to the first signal processing circuit.

Description

APPARATUS AND METHOD OF CONFIGURABLE REDUCTION TO SIGNAL RESOLUTION

CROSS-REFERENCE TO RELATED APPLICATION

[0001] This application claims the benefit of priority to U.S. Provisional Application No. 63/133,777, entitled “METHOD OF POWER SAVING IN DIGITAL SIGNAL PROCESSING” and filed on January 4, 2021, which is incorporated by reference herein in its entirety.

BACKGROUND

[0002] Embodiments of the present disclosure relate to apparatus and method for wireless communication.

[0003] A digital signal processor (DSP) is a specialized microprocessor chip with an architecture optimized for digital signal processing. Digital signal processors (DSPs) are often fabricated as part of an integrated silicon circuit chip used in electronic devices. DSPs are widely used in audio signal processing, wireless communication devices (such as user equipments (UEs), base stations, access nodes, etc.), digital image processing, radar, sonar, speech recognition systems, and in consumer electronic devices, e.g., such as mobile phones, tablets, laptops, and high-definition television (HDTV) devices, just to name a few.

SUMMARY

[0004] Embodiments of apparatus and method for reducing the power consumption of a fixed bit-width signal processing circuit and/or a fixed bit-width signal processor by reducing the resolution of an input signal are disclosed herein.

[0005] According to another aspect of the present disclosure, a second apparatus for digital signal processing is disclosed. The second apparatus may include a memory, a first signal processor coupled to the memory, and a first resolution converter coupled to the memory. The first signal processor may be configured to process first signals with a first bit-width. The first resolution converter may be configured to receive a first resolution configuration signal configuring a first resolution reduction. The first resolution converter may be further configured to receive a first signal with the first bit-width and a first resolution. The first resolution converter may be further configured to generate a second signal with the first bit-width and a second resolution by applying a first resolution reduction function to the first signal. The first resolution reduction function may be associated with the first resolution reduction. The second resolution may be lower than the first resolution. The first resolution converter may be further configured to output the second signal to the first signal processor.

[0006] According to another aspect of the present disclosure, a second apparatus for digital signal processing is disclosed. The second apparatus may include a memory, a first signal processor coupled to the memory, and a first resolution converter coupled to the memory. The first signal processor may be configured to process first signals with a first bit-width. The first resolution converter may be configured to receive a first resolution configuration signal configuring a first resolution reduction. The first resolution converter may be further configured to receive a first signal with the first bit-width and a first resolution from the first signal processor. The first resolution converter may be configured to generate a second signal with a second resolution by applying a first resolution reduction function to the first signal. The first resolution reduction function may be associated with the first resolution reduction. The second resolution may be lower than the first resolution. The first resolution converter may be further configured to output the second signal to the memory.

[0007] According to another aspect of the present disclosure, a method of digital signal processing is disclosed. The method may include processing, using a first signal processor, first signals with a first bit-width. The method may further include receiving, using a first resolution converter, a first resolution configuration signal configuring a first resolution reduction. The method may further include receiving, using the first resolution converter, a first signal with the first bit-width and a first resolution. The method may further include generating, using the first resolution converter, a second signal with the first bit-width and a second resolution by applying a first resolution reduction function to the first signal. The first resolution reduction function may be associated with the first resolution reduction. The second resolution may be lower than the first resolution. The method may further include outputting, using the first resolution converter, the second signal to the first signal processor.

BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate embodiments of the present disclosure and, together with the description, further serve to explain the principles of the present disclosure and to enable a person skilled in the pertinent art to make and use the present disclosure.

[0009] FIG. 1 A illustrates a block diagram of a first exemplary DSP apparatus, according to some embodiments of the present disclosure.

[0010] FIG. IB illustrates a block diagram of a second exemplary DSP apparatus, according to some embodiments of the present disclosure.

[0011] FIG. 2 illustrates an exemplary wireless network, according to some embodiments of the present disclosure.

[0012] FIG. 3 illustrates a block diagram of an apparatus including a baseband chip, a radio frequency (RF) chip, and a host chip, according to some embodiments of the present disclosure.

[0013] FIG. 4 illustrates a flow chart of an exemplary method of wireless communication, according to some embodiments of the present disclosure.

[0014] FIG. 5 illustrates a block diagram of an exemplary node, according to some embodiments of the present disclosure.

[0015] FIG. 6A illustrates a block diagram of conventional dual signal processing circuits.

[0016] FIG. 6B illustrates a block diagram of conventional signal processors.

[0017] Embodiments of the present disclosure will be described with reference to the accompanying drawings.

DETAILED DESCRIPTION

[0018] Although specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. A person skilled in the pertinent art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of the present disclosure. It will be apparent to a person skilled in the pertinent art that the present disclosure can also be employed in a variety of other applications.

[0019] It is noted that references in the specification to “one embodiment,” “an embodiment,” “an example embodiment,” “some embodiments,” “certain embodiments,” etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it would be within the knowledge of a person skilled in the pertinent art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.

[0020] In general, terminology may be understood at least in part from usage in context. For example, the term “one or more” as used herein, depending at least in part upon context, may be used to describe any feature, structure, or characteristic in a singular sense or may be used to describe combinations of features, structures or characteristics in a plural sense. Similarly, terms, such as “a,” “an,” or “the,” again, may be understood to convey a singular usage or to convey a plural usage, depending at least in part upon context. In addition, the term “based on” may be understood as not necessarily intended to convey an exclusive set of factors and may, instead, allow for existence of additional factors not necessarily expressly described, again, depending at least in part on context.

[0021] Various aspects of digital signal processing will now be described with reference to various apparatus and methods. These apparatus and methods will be described in the following detailed description and illustrated in the accompanying drawings by various blocks, modules, units, components, circuits, steps, operations, processes, algorithms, etc. (collectively referred to as “elements”). These elements may be implemented using electronic hardware, firmware, computer software, or any combination thereof. Whether such elements are implemented as hardware, firmware, or software depends upon the particular application and design constraints imposed on the overall system.

[0022] The DSP apparatuses and methods described herein may be implemented in various devices, e.g., such as a computer processing unit (CPU), a graphics processing unit (GPU), a core, a system-on-chip (SoC), a baseband chip, a modem, an integrated circuit device, speakers, speech recognition devices, digital cameras, mobile phones, tablets, laptops, personal computers (PCs), internet-of-things (loT) devices, base stations, access nodes, smart devices, user equipment, autonomous vehicles, drones, digital image processing devices, audio processing devices, radar equipment, sonar equipment, speech recognition systems, and other electronic apparatuses. The terms “DSP,” “DSP apparatus,” “signal processing circuit” and “signal processor” may be used interchangeably in the following description.

[0023] A DSP may be configured to measure, filter, and/or compress continuous real- world analog signals. Most general -purpose microprocessors can also execute digital signal processing algorithms successfully, but may not be able to keep up with such processing continuously in real-time. Also, DSPs often provide increased power efficiency as compared to general purpose microprocesses, and thus, DSPs are often more suitable for digital signal processing in portable devices such as mobile phones or other wireless devices that operate under power consumption constraints.

[0024] Although DSPs may consume less power than a general -purpose microprocessor performing the same and/or similar operations, power consumption is still an important consideration when designing a DSP. This may be particularly important when the DSP is used in a device that has a battery as its on-board power source. While improvements in battery technology have assisted in prolonging the operational period before a battery recharge is required, control aspects have also been introduced into the operation of such devices to enhance the efficiency and improve performance. It is commonly provided for battery-operated devices to switch between full power mode and reduced power mode once the battery power reaches a threshold. For example, while in full power mode, and while not being charged, the battery power may until the threshold is reached. At this point, the device may switch to reduced power mode to prolong the lifetime of the battery by limiting certain operations, e.g., such as automatically checking and updating information such as the weather and/or emails, by way of example. On the other hand, when the battery is charging, the device may switch back to full power mode once the battery power increases to the threshold.

[0025] The power consumed by a DSP may have a significant impact on battery life. A signal processing circuit and/or signal processor that processes a signal with a larger bit-width consumes more power than one that performs similar processing of a signal with a comparatively smaller bit-width. In a reduced power scenario, it may not be possible to halt the operations of the signal processing circuits and/or signal processors without negatively impacting the user’s experience. Moreover, certain signal processing circuits and/or signal processors may be dedicated to processing signals of fixed bit-width, and thus, it may not be possible to reduce power consumption at these DSPs by reducing the bit-width of the signals being processed. Certain known approaches, such as those discussed below in connection with FIGs. 6A and 6B, have been developed to reduce the power consumption associated with DSPs under certain scenarios, such as when a device enters low power mode.

[0026] FIG. 6A illustrates a block diagram 600 of one such known approach, which includes dual signal processing circuits each configured to process signals of different bit-widths by switching from one to the other under various power conditions. For example, as illustrated in FIG. 6A, a first signal processing circuit 602a processes signals of a first bit- width (e.g., Ni-bit) during full power mode, and a second signal processing circuit 602b processes signals of a second, lower bit-width (e.g., Nx-bit) while in low power mode. While using second signal processing circuit 602b may extend the life of the battery while in low power mode, the lack of granularity of such a dual circuit system may negatively impact the user experience by processing signals of a significantly lower resolution. Moreover, the circuit footprint within the device is increased when dual signal processing circuit are implemented therein, which also increases the manufacturing cost.

[0027] FIG. 6B illustrates a block diagram 610 of another of these known approaches, which includes a plurality of different processors each configured to process signals of a different bit-width. For example, during full power mode, Ni-bit processor 605a may be operational and process signals with Ni number of bits. During low power mode, Nx-bit processor 605b may be operational and process signals with NK number of bits, which is less than the Ni number of bits. While this known approach may also save power, it suffers from the same drawbacks as those discussed above in connection with FIG. 6A.

[0028] Thus, there is an unmet need for a technique to reduce power consumption at fixed bit-width signal processing circuits and/or processors with a higher degree of granularity, reduced cost, and a smaller baseband chip footprint, as compared with the known approaches.

[0029] To reduce power consumption, and hence, improve the overall performance of an apparatus that includes one or more DSPs, a DSP apparatus and technique is disclosed herein that reduces the resolution of a fixed bit-width signal prior to its input into the DSP rather than include additional lower bit-width DSPs alongside other higher bit-width DSPs. Moreover, the resolution reduction disclosed herein may be configurable such that there are N - 1 number of possible resolution reductions that may be implemented under various power conditions, where N is the fixed number of bits. In a hardware implementation, a resolution reduction circuit may be placed on the input side of a signal processing circuit. The resolution reduction circuit may receive a signal that configures a particular resolution reduction of the signal before it is input to the signal processing circuit. Similarly, in a software implementation, a resolution converter may be positioned on the input side of a processor. Here too, the resolution converter may receive a signal that configures the resolution reduction based on the instantaneous power or performance conditions of the apparatus. Using the techniques described below in connection with FIGs. 1 A- 5, an apparatus of the present disclosure may achieve a desired tradeoff between power and performance and with a higher degree of granularity and smaller footprint/cost, as compared with known approaches.

[0030] FIG. 1A illustrates a block diagram of a first exemplary DSP apparatus 100, according to some embodiments of the present disclosure. Referring to FIG. 1 A, DSP apparatus 100 may include, e.g., a first resolution reduction circuit 102a, a first signal processing circuit 104a, a second resolution reduction circuit 102b, and a second signal processing circuit 104b connected in series. First signal processing circuit 104a may be configured to process A-bit signals, and second signal processing circuit 104b may be configured to process AAbit signals, where M may be the same number or a different number than N. First resolution reduction circuit 102a and second resolution reduction circuit 102b may be in communication with a resolution configuration unit, e.g., such as resolution configuration unit 322 in FIG. 3.

[0031] Under certain power threshold condition(s), first resolution reduction circuit 102a may receive a first resolution configuration signal 111 from resolution configuration unit 322. First resolution configuration signal 111 may indicate a resolution reduction of N- N’. In other words, first resolution configuration signal 111 configures a resolution of N’. Here, first resolution reduction circuit 102a may obtain a first resolution reduction function. In one example implementation, the exemplary resolution reduction function may be implemented by applying the function shown below in Equation (1) to the first A-bit signal 101 :

where b_N indicates the value of the bit located in position N in the bit-sequence of the TV-bit signal, N’ is the resolution reduction, and N is the number of bits in the signal.

[0032] By way of example and not limitation, assume N = 16 and N’ = 13. Moreover, assume the bit-sequence of first TV-bit signal 101 with a resolution of TVis, e.g., 1111011011011111. Then, using the function illustrated above in Equation (1), first resolution reduction circuit 102a may apply the function which changes the last A - A’ number of least significant bits (LSBs) in first A-bit signal 101 signal to ‘0’ to generate a second A-bit signal 103 with a resolution of A’. Using the same bit-sequence example, the bit-sequence of the generated second A-bit signal is, e.g., 1111011011011000, where the A- A’ LSBs are changed to ‘0’ to reduce the signal’s resolution.

[0033] In another example implementation, the exemplary resolution reduction function may be implemented by applying the function shown below in Equation (2):

The function illustrated in Equation (2) may be implemented using any of the following conditions:

where b_N indicates the value of the bit located in position N in the bit-sequence of the TV-bit signal,

N’ is the resolution reduction, and N is the number of bits in the signal.

[0034] When first TV-bit signal 101a is received, first resolution reduction circuit 102a may generate a second TV-bit signal 103 that has a resolution of TV’ by applying the first resolution reduction function, e.g., Equation (1) or Equation (2). This reduces the resolution of first TV-bit signal 101 by TV- TV’. Second TV-bit signal 103 may then be input to first signal processing circuit 104a, which may process the second TV-bit signal 103 using less power than processing first TV-bit signal 101 with a higher resolution of TV. In the example illustrated in FIG. 1A, first resolution reduction circuit 102a, first signal processing circuit 104a, second resolution reduction circuit 102b, and second signal processing circuit 104b are shown as connected in series. In such an example implementation, first signal processing circuit 104a may process second TV-bit signal 103 to generate third A/-bit signal 105, where AV may be the same or different than TV.

[0035] Under certain power threshold condition(s), second resolution reduction circuit 102b may receive a second resolution configuration signal 113 from resolution configuration unit 322. Second resolution configuration signal 113 may indicate a resolution reduction of M-M’ (or a desired resolution of A/’). Here, second resolution reduction circuit 102b may obtain a second resolution reduction function. The second resolution reduction function may be implemented using the same or similar functions as those shown above in Equations (1) and (2), except TV and TV’ in Equations (1) and (2) are replaced with the values of Aland M’, respectively.

[0036] Second resolution reduction circuit 102b may generate a fourth A/-bit signal 107 by applying the second resolution reduction function to the third A -bit signal 105 received from first signal processing circuit 104a. Fourth A7-bit signal 107 may have a resolution of M’, which is less than the resolution M of third A -bit signal 105. Fourth A7-bit signal 107 may then be input to second signal processing circuit 104b, which may use less power processing fourth A7-bit signal 107 with a resolution of M’ than it would processing third A7-bit signal 103 with a resolution of M. In this way, the DSP apparatus 100 of the FIG. 1A may achieve a tradeoff between power and performance and with a higher degree of granularity and smaller footprint/cost, as compared with known approaches.

[0037] FIG. IB illustrates a second exemplary implementation of a DSP apparatus 150, according to some embodiments of the present disclosure. Referring to FIG. IB, DSP apparatus 150 may include, e.g., a memory 110, a first resolution converter 112a, a signal processor 114 (e.g., fixed bit-width processor), a second resolution converter 112b, a register 116, and an arbitrator 118.

[0038] Under certain power threshold condition(s), first resolution converter 112a may receive a first resolution configuration signal 129 from a resolution configuration unit which may configure a resolution reduction at DSP apparatus 150 based on the instantaneous or intermittent performance or power conditions of the device. The resolution configuration unit 322 described below in connection with FIG. 3 is one example of such a resolution configuration unit. First resolution configuration signal 129 may indicate a resolution reduction of N - N’ (or a desired resolution of A’). Here, first resolution converter 112a may apply a first resolution reduction function, e.g., such as Equation (1) or Equation (2) described above in connection with FIG. 1 A. Similar operations may be implemented at second resolution converter 112b when second configuration signal 131 is received.

[0039] Signal processor 114 may write data via arbitrator 118 to memory 110. There are two embodiments to save signal 121 in memory 110. In the first write embodiment, first resolution converter 112a may reduce the resolution of signal 123 such that signal 121 is written to memory 110 using less power than if signal 123 were written to memory 110. For example, signal processor 114 may perform signal processing to generate signal 123, e.g., with a bit width of N and a resolution of N. First resolution converter 112a may apply the resolution reduction of A - A’ to signal 123 to generate signal 121 that has a bit width of A and a resolution of A’, which is then written to memory 110 using less power than if signal 123 with a bit width of A and resolution of A were written to memory 110. Still referring to the first write embodiment, second resolution converter 112b may reduce the resolution of signal 125 such that signal 127 is written to register 116 using less power than if signal 125 were written to register 116. For example, signal processor 114 may perform signal processing to generate signal 125, e.g., with a bit width of N and a resolution of N. Second resolution converter 112b may apply the resolution reduction of N-N’ to signal 125 to generate signal 127 that has a bit width of N and a resolution of N’, which may then be written to register 116 using less power than if signal 125 with a bit width of N and resolution of N were written to register 116.

[0040] In the second write embodiment, first resolution converter 112a may reduce both the bit width and the resolution of signal 123 to generate signal 121. Thus, signal 121 may be written to memory 110 using less power and less space within the corresponding memory address than if signal 123 were written to memory 110. For example, signal processor 114 may perform signal processing to generate signal 123, e.g., with a bit width of N and a resolution of N. First resolution converter 112a may apply the resolution reduction of TV - TV’ to signal 123 to generate signal 121 that has a bit width of N and a resolution of N’. For example, the last TV- TV’ LSB of signal 123 may be changed to zero using, e.g., Equation (1) or Equation (2), which reduces the resolution of signal 123. Then, the N- N’ LSB may be removed such that signal 121 has a bit width and a resolution of N’. Here, K number of parallel TV ’-bit signals may be stored in a K’ number of TV-bit memory addresses of memory 110, where K' = ^j and function [x] means the smallest integer that is larger than or equal to x. In so doing, the memory access power consumption of DSP apparatus 150 may be reduced as compared with saving TV-bit signals with a resolution of TV’ at memory 110. Referring to the second write embodiment, second resolution converter 112b may perform the same or similar operations as those described in connection with first resolution converter 112a such that signal 127 may be stored at register 116 using reduced power and less space within the memory address than if signal 125 were stored in register 116.

[0041] Signal processor 114 may read data from memory 110 via arbitrator 118. There are two embodiments to read data from memory 110 via arbitrator. To begin, signal processor 114 may send a read request for data to memory 110 via arbitrator 118. In the first read embodiment, neither the bit width nor the resolution are changed between memory 110 and signal processor 114. For example, if the requested data stored in memory 110 has a bit width and resolution of TV, then the data received by signal processor 114 has the same bit width and resolution of TV. In other words, first resolution converter 112a makes no changes such that signal 123 input into signal processor 114 is the same as signal 121 output by memory. Similarly, second resolution converter 112b make no changes to a signal output by register 116 such that signal 125 input to signal processor 114 is the same as signal 127 output by register 116. In a second read embodiment, the resolution of a signal may be reduced between memory 110 and signal processor. For example, if signal 121 output by memory 110 has a bit width and resolution of N, first resolution converter 112a may reduce the resolution by N-N’ such that signal 123 input into signal processor 114 has a bit width of N and a resolution of N’. Here, signal processor 114 may use less power processing signal 123 than if it were to process signal 121 with a bit width and resolution of N. The same or similar operations may be performed by second resolution converter 112b such that the resolution of signal 125 input into signal processor 114 is less than signal 127 output by register 116.

[0042] In this way, the DSP apparatus 150 of the FIG. IB may achieve a tradeoff between power and performance and with a higher degree of granularity and smaller footprint/cost, as compared with known approaches.

[0043] In one example implementation, the DSP apparatuses 100, 150 and techniques described above in connection with FIGs. 1A and IB may be implemented in an apparatus for wireless communication, which is described below for illustrative purposes. However, as would be readily apparent to one of ordinary skill, the DSP apparatuses 100, 150 and the techniques described above in connection with FIGs. 1A and IB are not limited to implementation in an apparatus for wireless communication. Rather, DSP apparatus 100 and DPS apparatus 150 may be implemented in any digital signal processing apparatus without departing from the scope of the present disclosure. The example wireless communication use case will be described below in connection with FIGs. 2, 3, and 5.

[0044] FIG. 2 illustrates an exemplary wireless network 200, in which some aspects of the present disclosure may be implemented, according to some embodiments of the present disclosure. As shown in FIG. 2, wireless network 200 may include a network of nodes, such as a user equipment (UE) 202, an access node 204, and a core network element 206. UE 202 may be any terminal device, such as a mobile phone, a desktop computer, a laptop computer, a tablet, a vehicle computer, a gaming console, a printer, a positioning device, a wearable electronic device, a smart sensor, or any other device capable of receiving, processing, and transmitting information, such as any member of a vehicle to everything (V2X) network, a cluster network, a smart grid node, or an Internet-of-Things (loT) node. It is understood that user equipment 202 is illustrated as a mobile phone simply by way of illustration and not by way of limitation.

[0045] Access node 204 may be a device that communicates with user equipment 202, such as a wireless access point, a base station (BS), a Node B, an enhanced Node B (eNodeB or eNB), a next-generation NodeB (gNodeB or gNB), a cluster master node, or the like. Access node 204 may have a wired connection to user equipment 202, a wireless connection to user equipment 202, or any combination thereof. Access node 204 may be connected to user equipment 202 by multiple connections, and user equipment 202 may be connected to other access nodes in addition to access node 204. Access node 204 may also be connected to other user equipments. It is understood that access node 204 is illustrated by a radio tower by way of illustration and not by way of limitation. [0046] Core network element 206 may serve access node 204 and user equipment 202 to provide core network services. Examples of core network element 206 may include a home subscriber server (HSS), a mobility management entity (MME), a serving gateway (SGW), or a packet data network gateway (PGW). These are examples of core network elements of an evolved packet core (EPC) system, which is a core network for the LTE system. Other core network elements may be used in LTE and in other communication systems. In some embodiments, core network element 206 includes an access and mobility management function (AMF) device, a session management function (SMF) device, or a user plane function (UPF) device, of a core network for the NR. system. It is understood that core network element 206 is shown as a set of rack-mounted servers by way of illustration and not by way of limitation.

[0047] Core network element 206 may connect with a large network, such as the Internet 208, or another Internet Protocol (IP) network, to communicate packet data over any distance. In this way, data from user equipment 202 may be communicated to other user equipments connected to other access points, including, for example, a computer 210 connected to Internet 208, for example, using a wired connection or a wireless connection, or to a tablet 212 wirelessly connected to Internet 208 via a router 214. Thus, computer 210 and tablet 212 provide additional examples of possible user equipments, and router 214 provides an example of another possible access node. [0048] A generic example of a rack-mounted server is provided as an illustration of core network element 206. However, there may be multiple elements in the core network including database servers, such as a database 216, and security and authentication servers, such as an authentication server 218. Database 216 may, for example, manage data related to user subscription to network services. A home location register (HLR) is an example of a standardized database of subscriber information for a cellular network. Likewise, authentication server 218 may handle authentication of users, sessions, and so on. In the NR. system, an authentication server function (AUSF) device may be the specific entity to perform user equipment authentication. In some embodiments, a single server rack may handle multiple such functions, such that the connections between core network element 206, authentication server 218, and database 216, may be local connections within a single rack.

[0049] Each element in FIG. 2 may be considered a node of wireless network 200. More detail regarding the possible implementation of a node is provided by way of example in the description of a node 500 in FIG. 5. Node 500 may be configured as user equipment 202, access node 204, or core network element 206 in FIG. 2. Similarly, node 500 may also be configured as computer 210, router 214, tablet 212, database 216, or authentication server 218 in FIG. 2. As shown in FIG. 5, node 500 may include a processor 502, a memory 504, and a transceiver 506. These components are shown as connected to one another by a bus, but other connection types are also permitted. When node 500 is user equipment 202, additional components may also be included, such as a user interface (UI), sensors, and the like. Similarly, node 500 may be implemented as a blade in a server system when node 500 is configured as core network element 206. Other implementations are also possible.

[0050] Transceiver 506 may include any suitable device for sending and/or receiving data. Node 500 may include one or more transceivers, although only one transceiver 506 is shown for simplicity of illustration. An antenna 508 is shown as a possible communication mechanism for node 500. Multiple antennas and/or arrays of antennas may be utilized for receiving multiple spatially multiplex data streams. Additionally, examples of node 500 may communicate using wired techniques rather than (or in addition to) wireless techniques. For example, access node 204 may communicate wirelessly to user equipment 202 and may communicate by a wired connection (for example, by optical or coaxial cable) to core network element 206. Other communication hardware, such as a network interface card (NIC), may be included as well.

[0051] As shown in FIG. 5, node 500 may include processor 502. Although only one processor is shown, it is understood that multiple processors can be included. Processor 502 may include microprocessors, microcontroller units (MCUs), digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), programmable logic devices (PLDs), state machines, gated logic, discrete hardware circuits, and other suitable hardware configured to perform the various functions described throughout the present disclosure. Processor 502 may be a hardware device having one or more processing cores. Processor 502 may execute software. Software shall be construed broadly to mean instructions, instruction sets, code, code segments, program code, programs, subprograms, software modules, applications, software applications, software packages, routines, subroutines, objects, executables, threads of execution, procedures, functions, etc., whether referred to as software, firmware, middleware, microcode, hardware description language, or otherwise. Software can include computer instructions written in an interpreted language, a compiled language, or machine code. Other techniques for instructing hardware are also permitted under the broad category of software. [0052] As shown in FIG. 5, node 500 may also include memory 504. Although only one memory is shown, it is understood that multiple memories can be included. Memory 504 can broadly include both memory and storage. For example, memory 504 may include random-access memory (RAM), read-only memory (ROM), static RAM (SRAM), dynamic RAM (DRAM), ferroelectric RAM (FRAM), electrically erasable programmable ROM (EEPROM), compact disc readonly memory (CD-ROM) or other optical disk storage, hard disk drive (HDD), such as magnetic disk storage or other magnetic storage devices, Flash drive, solid-state drive (SSD), or any other medium that can be used to carry or store desired program code in the form of instructions that can be accessed and executed by processor 502. Broadly, memory 504 may be embodied by any computer-readable medium, such as a non-transitory computer-readable medium.

[0053] Processor 502, memory 504, and transceiver 506 may be implemented in various forms in node 500 for performing wireless communication functions. In some embodiments, processor 502, memory 504, and transceiver 506 of node 500 are implemented (e.g., integrated) on one or more system-on-chips (SoCs). In one example, processor 502 and memory 504 may be integrated on an application processor (AP) SoC (sometimes known as a “host,” referred to herein as a “host chip”) that handles application processing in an operating system (OS) environment, including generating raw data to be transmitted. In another example, processor 502 and memory 504 may be integrated on a baseband processor (BP) SoC (sometimes known as a “modem,” referred to herein as a “baseband chip”) that converts the raw data, e.g., from the host chip, to signals that can be used to modulate the carrier frequency for transmission, and vice versa, which can run a real-time operating system (RTOS). In still another example, processor 502 and transceiver 506 (and memory 504 in some cases) may be integrated on an RF SoC (sometimes known as a “transceiver,” referred to herein as an “RF chip”) that transmits and receives RF signals with antenna 508. It is understood that in some examples, some or all of the host chip, baseband chip, and RF chip may be integrated as a single SoC. For example, a baseband chip and an RF chip may be integrated into a single SoC that manages all the radio functions for cellular communication. [0054] Referring back to FIG. 2, in some embodiments, user equipment 202 may be configured to reduce the power consumed by fixed bit-width signal processing circuits and/or signal processors using a resolution reduction function that achieves the best tradeoff between performance and power consumption under the present power threshold conditions, as described above in connection with FIGs. 1A and IB. As a result, the power consumption of the UE 202 described herein may be reduced by at least 10%, while at the same time reducing the cost of manufacturing the baseband chip, as compared with known solutions.

[0055] FIG. 3 illustrates a block diagram of an apparatus 300 including a baseband chip 302, an RF chip 304, and a host chip 306, according to some embodiments of the present disclosure. Apparatus 300 may be an example of any suitable node of wireless network 200 in FIG. 2, such as user equipment 202 or access node 204. As shown in FIG. 3, apparatus 300 may include baseband chip 302, RF chip 304, host chip 306, and one or more antennas 310. In some embodiments, baseband chip 302 is implemented by processor 502 and memory 504, and RF chip 304 is implemented by processor 502, memory 504, and transceiver 506, as described above with respect to FIG. 5. Besides the on-chip memory 318 (also known as “internal memory,” e.g., registers, buffers, or caches) on each chip 302, 304, or 306, apparatus 300 may further include an external memory 308 (e.g., the system memory or main memory) that can be shared by each chip 302, 304, or 306 through the system/main bus. Although baseband chip 302 is illustrated as a standalone SoC in FIG. 3, it is understood that in one example, baseband chip 302 and RF chip 304 may be integrated as one SoC; in another example, baseband chip 302 and host chip 306 may be integrated as one SoC; in still another example, baseband chip 302, RF chip 304, and host chip 306 may be integrated as one SoC, as described above.

[0056] In the uplink, host chip 306 may generate raw data and send it to baseband chip 302 for encoding, modulation, and mapping. Interface 314 of baseband chip 302 may receive the data from host chip 306. Baseband chip 302 may also access the raw data generated by host chip 306 and stored in external memory 308, for example, using the direct memory access (DMA). Baseband chip 302 may perform signal processing of the data obtained from host chip 306. For example, baseband chip 302 may first encode (e.g., by source coding and/or channel coding) the raw data and modulate the coded data using any suitable modulation techniques, such as multiphase shift keying (MPSK) modulation or quadrature amplitude modulation (QAM). Baseband chip 302 may perform any other functions, such as symbol or layer mapping, to convert the raw data into a signal that can be used to modulate the carrier frequency for transmission. In the uplink, baseband chip 302 may send the modulated signal to RF chip 304 via interface 314. RF chip 304, through the transmitter, may convert the modulated signal in the digital form into analog signals, i.e., RF signals, and perform any suitable front-end RF functions, such as filtering, digital predistortion, up-conversion, or sample-rate conversion. Antenna 310 (e.g., an antenna array) may transmit the RF signals provided by the transmitter of RF chip 304.

[0057] In the downlink, antenna 310 may receive RF signals from one or more nodes 204. The RF signals may be passed to the receiver (Rx) of RF chip 304. RF chip 304 may perform any suitable front-end RF functions, such as filtering, IQ imbalance compensation, down-paging conversion, or sample-rate conversion, and convert the RF signals (e.g., transmission) into low- frequency digital signals (baseband signals) that can be processed by baseband chip 302. For example, interface 314 of baseband chip 302 may receive the RF signals, which are passed to signal processing unit 316. Signal processing unit 316 may perform other functions, such as demodulation, decoding, error checking, de-mapping, channel estimation, descrambling, etc. The raw data provided to baseband chip 302 may be sent to host chip 306 directly via interface 314 or stored in external memory 308.

[0058] In the uplink and the downlink, baseband chip 302 may perform signal processing using signal processing unit 316. One signal processing unit 316 is depicted in FIG. 3 for simplicity of illustration, though any number of signal processing units may be included in baseband chip 302 without departing from the scope of the present disclosure. In certain implementations, signal processing unit 316 may be implemented as hardware, e.g., such as a signal processing circuit as described above in connection with FIG. 1 A. In certain other implementations, signal processing unit 316 may be implemented as software/firmware, e.g., such as a signal processor as described above in connection with FIG. IB. In either implementation, signal processing unit 316 may be configured to process signals of a fixed bit-width or signals of different bit-widths. The fixed bitwidth may include N number of bits, where N is an integer value. Signal processing unit 316 may be configured to process signals of variable resolutions. For example, signal processing unit 316 may process a signal with A-bits and with a resolution of N, a signal with A-bits and with a resolution of A - 1, a signal with A-bits and with a resolution of A - 2, and so on.

[0059] In addition to signal processing unit 316, baseband chip 302 may include a resolution reduction unit 320 and a resolution configuration unit 322. To reduce power consumption at signal processing unit 316 under certain conditions, resolution configuration unit 322 may configure a resolution reduction that may be implemented by resolution reduction unit 320. Resolution reduction unit 320 may be implemented as hardware as described above in connection with FIGs. 1A and IB. Alternatively, resolution reduction unit 320 may be implemented as software and performed by a processor using instructions stored in a memory. Resolution configuration unit 322 may be configured to determine when performance requirement reaches a threshold level and/or the battery power of apparatus 300 reaches a threshold level and/or a draining rate associated with a particular resolution reduction. Once one of these thresholds is met, resolution configuration unit 322 may send a signal indicating a first resolution reduction or a desired resolution to resolution reduction unit 320.

[0060] Resolution reduction unit 320 may have access to one or more resolution reduction functions. In some embodiments, resolution configuration unit 322 may send the resolution reduction function to resolution reduction unit 320. In some other embodiments, upon receipt of the signal indicating the first resolution reduction, resolution reduction unit 320 may access the resolution reduction function maintained locally by the resolution reduction unit 320 or externally on on-chip memory 318, external memory 308, or another memory and/or register.

[0061] Once the resolution reduction function has been obtained, resolution reduction unit 320 may apply the resolution reduction function to an TV-bit signal to reduce its resolution before the signal is output to signal processing unit 316. For example, when resolution configuration unit 322 indicates a resolution reduction of N-N’ (or a desired resolution of A’), resolution reduction unit 320 may apply a first resolution reduction function that reduces the resolution of the TV-bit signal to N’, where N’ may include any integer between 1 and N. Each resolution reduction N- N’ may correspond to a different condition at the apparatus 300, e.g., such as performance requirement level and/or battery power level and/or battery power depletion rate. By way of example, when the fixed bit-width signal includes sixteen bits, there may be fifteen different conditions that trigger a resolution reduction. The TV-bit signal may be input to resolution reduction unit 320, which may use the resolution reduction function to reduce the resolution to the signal to N’. Then, the TV-bit signal with a resolution of N’ may be input to signal processing unit 316. Signal processing unit 316 may consume less power processing an TV-bit signal with a resolution of N’ than it would processing an TV-bit signal with a resolution of N.

[0062] In this way, apparatus 300 may achieve a tradeoff between power and performance and with a higher degree of granularity and smaller footprint/cost, as compared with known approaches, thereby improving the user experience. Additional descriptions for the operations performed by signal processing unit 316, resolution reduction unit 320, and resolution configuration unit 322 are set forth above, e.g., in connection with FIGs. 1 A and IB.

[0063] FIG. 4A illustrates a flowchart of a first exemplary method 400 of resolution reduction, according to embodiments of the disclosure. Exemplary method 400 may be performed by an apparatus for wireless communication, e.g., such as UE 202, apparatus 300, baseband chip 302, signal processing unit 316, on-chip memory 318, external memory 308, resolution reduction unit 320, resolution configuration unit 322, first resolution reduction circuit 102a, first signal processing circuit 104a, second resolution reduction circuit 102b, second signal processing circuit 104b, memory 110, first resolution converter 112a, signal processor 114, second resolution converter 112b, register 116, arbitrator 118, and/or node 500. Method 400 may include steps 402- 410 as described below. It is to be appreciated that some of the steps may be optional, and some of the steps may be performed simultaneously, or in a different order than shown in FIG. 4A.

[0064] At 402, the apparatus may process first signals with a first bit-width. For example, referring to FIG. 1 A, first signal processing circuit 104a may be a fixed bit- width processing circuit configured to process signals with a bit-width of N.

[0065] At 404, the apparatus may receive a first resolution configuration signal configuring a first resolution reduction. For example, referring to FIG. 1A, under certain power threshold condition(s), first resolution reduction circuit 102a may receive a first resolution configuration signal 111 from resolution configuration unit 322. First resolution configuration signal 111 may indicate a resolution reduction of N- N’. In other words, first resolution configuration signal 111 configures a resolution of N’. Here, first resolution reduction circuit 102a may obtain a first resolution reduction function (which may be implemented as Equation (1) or Equation (2) shown above) to implement the indicated resolution reduction.

[0066] At 406, the apparatus may receive a first signal with the first bit-width and a first resolution. For example, referring to FIG. 1A, first resolution reduction circuit 102a may receive a first A -bit signal 101 from, e.g., on-chip memory 318, external memory 308, or from another unit (e.g., processing circuit, register, etc.).

[0067] At 408, the apparatus may generate a second signal with the first bit-width and a second resolution by applying a first resolution reduction function to the first signal. In certain aspects, the first resolution reduction function may be associated with the first resolution reduction. In certain other aspects, the second resolution may be lower than the first resolution. For example, referring to FIG. 1A, first resolution reduction circuit 102a may generate a second TV-bit signal 103 that has a resolution of N’ by applying the first resolution reduction function (e.g., Equation (1) or Equation (2)) to first TV-bit signal 101 to reduce its resolution by N- N’. Second TV-bit signal 103 may then be input to signal processing circuit 104a, which may process the second TV-bit signal 103 using less power than processing first TV-bit signal 101 with a higher resolution of TV. By way of example and not limitation, assume TV = 16 and TV’ = 13. Moreover, assume the bit-sequence of first TV-bit signal 101 with full resolution is, e.g., 1111011011011111. Then, first resolution reduction circuit 102a may apply the function implemented using Equation (1), which changes the last TV- TV’ number of least significant bits (LSBs) in the signal to ‘O’. By changing the last TV- TV’ number of LSBs to ‘O’, the signal’s resolution may be reduced to TV’. Using the same example, the second TV-bit signal 103 may be generated with first resolution reduction circuit 102a may generate a signal with a bit sequence of, e.g., 1111011011011000.

[0068] At 410, the apparatus may output the second signal to the first signal processing circuit. For example, referring to FIG. 1A, second TV-bit signal 103 may be input to first signal processing circuit 104a, which may process the second TV-bit signal 103 using less power than processing first TV-bit signal 101 with a higher resolution of N.

[0069] FIG. 4B illustrates a flowchart of a second exemplary method 401 of resolution reduction and/or bit width reduction, according to embodiments of the disclosure. Exemplary method 401 may be performed by an apparatus for wireless communication, e.g., such as UE 202, apparatus 300, baseband chip 302, signal processing unit 316, on-chip memory 318, external memory 308, resolution reduction unit 320, resolution configuration unit 322, memory 110, first resolution converter 112a, signal processor 114, second resolution converter 112b, register 116, arbitrator 118, and/or node 500. Method 401 may include steps 422-430 as described below. It is to be appreciated that some of the steps may be optional, and some of the steps may be performed simultaneously, or in a different order than shown in FIG. 4B.

[0070] At 422, the apparatus may process first signals with a first bit-width. For example, referring to FIG. IB, signal processor 114 may be a fixed bit-width processing circuit configured to process signals with a bit-width of N.

[0071] At 424, the apparatus may receive a first resolution configuration signal configuring a first resolution reduction. For example, referring to FIG. IB, under certain power threshold condition(s), first resolution converter 112a may receive a first resolution configuration signal 129 from a resolution configuration unit which may configure a resolution reduction at DSP apparatus 150 based on the instantaneous or intermittent power conditions of the device. The resolution configuration unit 322 described above in connection with FIG. 3 is one example of such a resolution configuration unit. First resolution configuration signal 129 may indicate a resolution reduction of N-N’ (or a desired resolution of A’). Here, first resolution converter 112a may apply a first resolution reduction function, e.g., such as Equation (1) or Equation (2) described above in connection with FIG. 1 A. Similar operations may be implemented at second resolution converter 112b when second configuration signal 131 is received.

[0072] At 426, the apparatus may receive a first signal with the first bit-width and a first resolution from a signal processors. For example, referring to FIG. IB, , signal processor 114 may perform signal processing to generate signal 123, e.g., with a bit width of N and a resolution of N, which may be received by first signal converter 112a.

[0073] At 428, the apparatus may generate a second signal with a second resolution by applying a first resolution reduction function to the first signal. In certain aspects, the first resolution reduction function may be associated with the first resolution reduction. In certain other aspects, the second resolution may be lower than the first resolution. For example, referring to FIG. IB, in a first write embodiment, resolution converter 112a may apply the resolution reduction of A- A’ to signal 123 to generate signal 121 that has a bit width of A and a resolution of A’, which is then written to memory 110 using less power than if signal 123 with a bit width of A and resolution of A were written to memory 110. Still referring to the first write embodiment, second resolution converter 112b may reduce the resolution of signal 125 such that signal 127 is written to register 116 using less power than if signal 125 were written to register 116. For example, signal processor 114 may perform signal processing to generate signal 125, e.g., with a bit width of A and a resolution of A. Second resolution converter 112b may apply the resolution reduction of A - A’ to signal 125 to generate signal 127 that has a bit width of A and a resolution of A’, which may then be written to register 116 using less power than if signal 125 with a bit width of A and resolution of A were written to register 116. In the second write embodiment, first resolution converter 112a may reduce both the bit width and the resolution of signal 123 to generate signal 121. Thus, signal 121 may be written to memory 110 using less power and less space within the corresponding memory address than if signal 123 were written to memory 110. For example, signal processor 114 may perform signal processing to generate signal 123, e.g., with a bit width of A and a resolution of A. First resolution converter 112a may apply the resolution reduction of A- A’ to signal 123 to generate signal 121 that has a bit width of A and a resolution of A’. For example, the last A - A’ LSB of signal 123 may be changed to zero using, e.g., Equation (1) or Equation (2), which reduces the resolution of signal 123. Then, the A- A’ LSB may be removed such that signal 121 has a bit width and a resolution of N’. Here, K number of parallel TV ’-bit signals may be stored in a T’ number of TV-bit memory addresses of memory 110, where K' ⁼[~] and function [x] means the smallest integer that is larger than or equal to x. In so doing, the memory access power consumption of DSP apparatus 150 may be reduced as compared with saving TV-bit signals with a resolution of TV’ at memory 110. Referring to the second write embodiment, second resolution converter 112b may perform the same or similar operations as those described in connection with first resolution converter 112a such that signal 127 may be stored at register 116 using reduced power and less space within the memory address than if signal 125 were stored in register 116.

[0074] At 430, the apparatus may output the second signal to a memory. For example, referring to FIG. IB, signal 121 with a bit width of TV and a resolution of TV’ or a bit width of TV’ and a resolution of TV’ may be stored in memory 110.

[0075] To reduce power consumption, and hence, improve the overall performance of a UE, the techniques described above in connection with FIGs. 1 A- 5 reduce the resolution of a fixed bit-width signal prior to being input into the signal processing circuit and/or processor rather than include additional fixed bit-width signal processing circuits and/or processors that are used in low power scenarios. Moreover, the resolution reduction described herein may be configurable such that there are A- 1 number of possible resolution reductions that may be implemented depending on the power conditions, where N is the fixed number of bits. Using the techniques described above, the DSP apparatus of the present disclosure may achieve a desired tradeoff between power and performance and with a higher degree of granularity and smaller footprint/cost, as compared with known approaches.

[0076] In various aspects of the present disclosure, the functions described herein may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored on or encoded as instructions or code on a non-transitory computer-readable medium. Computer-readable media includes computer storage media. Storage media may be any available media that can be accessed by a computing device, such as node 500 in FIG. 5. By way of example, and not limitation, such computer-readable media can include RAM, ROM, EEPROM, CD-ROM or other optical disk storage, HDD, such as magnetic disk storage or other magnetic storage devices, Flash drive, SSD, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a processing system, such as a mobile device or a computer. Disk and disc, as used herein, includes CD, laser disc, optical disc, digital video disc (DVD), and floppy disk where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media. [0077] According to one aspect of the present disclosure, a first apparatus for digital signal processing is disclosed. The apparatus may include a first signal processing circuit, a first resolution reduction circuit, and a second signal processing circuit. The first signal processing circuit may be configured to process signals with a first bit-width. The first resolution reduction circuit may be configured to receive a first resolution configuration signal configuring a first resolution reduction. The first resolution reduction circuit may be further configured to receive a first signal with the first bit-width and a first resolution. The first resolution reduction circuit may be further configured to generate a second signal with the first bit-width and a second resolution by applying a first resolution reduction function to the first signal. The first resolution reduction function may be associated with the first resolution reduction. The second resolution may be lower than the first resolution. The first resolution reduction circuit may be further configured to output the second signal to the first signal processing circuit.

[0078] In some embodiments, the first resolution reduction circuit may be further configured to access the first resolution reduction function upon receipt of the first resolution configuration signal.

[0079] In some embodiments, the first bit-width may include N number of bits. In some embodiments, the first resolution reduction function may be configured to implement TV- 1 number of resolution reductions.

[0080] In some embodiments, the first set of resolution reduction functions may include one or more of an adder, a subtractor, or a multiplier.

[0081] In some embodiments, the first signal may include N number of bits and a resolution of N. In some embodiments, the first resolution reduction may include a reduction of N- N’. In some embodiments, the second signal may include N number of bits and a resolution of N’.

[0082] In some embodiments, the first signal processing circuit may be configured to output a third signal with a second bit-width and a third resolution. In some embodiments, the second signal processing circuit may be configured to process second signals with the second bitwidth. In some embodiments, the second resolution reduction circuit may be configured to receive a second resolution configuration signal configuring a second resolution reduction. In some embodiments, the second resolution reduction circuit may be configured to receive the third signal with the second bit-width and the third resolution. In some embodiments, the second resolution reduction circuit may be configured to generate a fourth signal with the second bit-width and a fourth resolution by applying a second resolution reduction function to the third signal. The second resolution reduction function may be associated with the second resolution reduction. The fourth resolution may be lower than the third resolution. In some embodiments, the second resolution reduction circuit may be configured to output the fourth signal to the second signal processing circuit.

[0083] In some embodiments, the second resolution reduction circuit may be configured to access the second resolution reduction function upon receipt of the second resolution configuration signal.

[0084] According to another aspect of the present disclosure, a second apparatus for digital signal processing is disclosed. The second apparatus may include a memory, a first signal processor coupled to the memory, and a first resolution converter coupled to the memory. The first signal processor may be configured to process first signals with a first bit-width. The first resolution converter may be configured to receive a first resolution configuration signal configuring a first resolution reduction. The first resolution converter may be further configured to receive a first signal with the first bit-width and a first resolution from the first signal processor. The first resolution converter may be configured to generate a second signal with a second resolution by applying a first resolution reduction function to the first signal. The first resolution reduction function may be associated with the first resolution reduction. The second resolution may be lower than the first resolution. The first resolution converter may be further configured to output the second signal to the memory.

[0085] In some embodiments, the second signal generated by the first resolution reduction converter includes a second bit width smaller than the first bit width.

[0086] In some embodiments, the first signal may include N number of bits and a resolution of N. In some embodiments, the first resolution reduction includes a reduction of N- N In some embodiments, the second signal includes N’ number of bits and a resolution of N’.

[0087] In some embodiments, the first bit-width may include N number of bits. In some embodiments, the first resolution reduction function may be configured to implement N- 1 number of resolution reductions.

[0088] In some embodiments, the first set of resolution reduction functions may include one or more of an adder, a subtractor, or a multiplier. [0089] In some embodiments, the first signal may include N number of bits and a resolution of N. In some embodiments, the first resolution reduction may include a reduction of N- N’. In some embodiments, the second signal may include N number of bits and a resolution of N’.

[0090] In some embodiments, the first signal processor may be configured to output a third signal with a second bit-width and a third resolution. In some embodiments, a second signal processor may be configured to process second signals with the second bit-width. In some embodiments, the second resolution converter may be configured to receive a second resolution configuration signal configuring a second resolution reduction. In some embodiments, the second resolution converter may be configured to receive the third signal with the second bit-width and the third resolution. In some embodiments, the second resolution converter may be configured to generate a fourth signal with the second bit-width and a fourth resolution by applying a second resolution reduction function to the third signal. In some embodiments, the second resolution reduction function may be associated with the second resolution reduction. The fourth resolution may be lower than the third resolution. In some embodiments, the second resolution converter may be configured to output the fourth signal to the second signal processor.

[0091] In some embodiments, the second resolution converter may be configured to access the second resolution reduction function upon receipt of the second resolution configuration signal. [0092] According to another aspect of the present disclosure, a method of digital signal processing is disclosed. The method may include processing, using a first signal processor, first signals with a first bit-width. The method may further include receiving, using a first resolution converter, a first resolution configuration signal configuring a first resolution reduction. The method may further include receiving, using the first resolution converter, a first signal with the first bit-width and a first resolution. The method may further include generating, using the first resolution converter, a second signal with the first bit-width and a second resolution by applying a first resolution reduction function to the first signal. The first resolution reduction function may be associated with the first resolution reduction. The second resolution may be lower than the first resolution. The method may further include outputting, using the first resolution converter, the second signal to the first signal processor.

[0093] In some embodiments, the method may further include accessing, using the first resolution converter, the first resolution reduction function upon receipt of the first resolution configuration signal.

[0094] In some embodiments, the first bit-width may include N number of bits. In some embodiments, the first resolution reduction function may be configured to implement TV- 1 number of resolution reductions.

[0095] In some embodiments, the first set of resolution reduction functions may include one or more of an adder, a subtractor, or a multiplier.

[0096] In some embodiments, the first signal may include N number of bits and a resolution of N. In some embodiments, the first resolution reduction may include a reduction of N- N’. In some embodiments, the second signal may include N number of bits and a resolution of N’.

[0097] In some embodiments, the method may include outputting, using the first signal processor, a third signal with a second bit-width and a third resolution. In some embodiments, the method may include processing, using a second signal processor, second signals with the second bit-width. In some embodiments, the method may include receiving, using a second resolution converter, a second resolution configuration signal configuring a second resolution reduction. In some embodiments, the method may include receiving, using the second resolution converter, the third signal with the second bit-width and the third resolution. In some embodiments, the method may include generating, using the second resolution converter, a fourth signal with the second bitwidth and a fourth resolution by applying a second resolution reduction function to the third signal. In some embodiments, the second resolution reduction function may be associated with the second resolution reduction. In some embodiments, the fourth resolution may be lower than the third resolution. In some embodiments, the method may include outputting, using the second resolution converter, the fourth signal to the second signal processor.

[0098] The foregoing description of the specific embodiments will so reveal the general nature of the present disclosure that others can, by applying knowledge within the skill of the art, readily modify and/or adapt for various applications such specific embodiments, without undue experimentation, without departing from the general concept of the present disclosure. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments, based on the teaching and guidance presented herein. It is to be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, such that the terminology or phraseology of the present specification is to be interpreted by the skilled artisan in light of the teachings and guidance.

[0099] Embodiments of the present disclosure have been described above with the aid of functional building blocks illustrating the implementation of specified functions and relationships thereof. The boundaries of these functional building blocks have been arbitrarily defined herein for the convenience of the description. Alternate boundaries can be defined so long as the specified functions and relationships thereof are appropriately performed.

[0100] The Summary and Abstract sections may set forth one or more but not all exemplary embodiments of the present disclosure as contemplated by the inventor(s), and thus, are not intended to limit the present disclosure and the appended claims in any way.

[0101] Various functional blocks, modules, and steps are disclosed above. The particular arrangements provided are illustrative and without limitation. Accordingly, the functional blocks, modules, and steps may be re-ordered or combined in different ways than in the examples provided above. Likewise, some embodiments include only a subset of the functional blocks, modules, and steps, and any such subset is permitted.

[0102] The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

Claims

- 27 - WHAT IS CLAIMED IS:

1. An apparatus for digital signal processing, comprising: a first signal processing circuit configured to process signals with a first bit-width; a first resolution reduction circuit configured to: receive a first resolution configuration signal configuring a first resolution reduction; receive a first signal with the first bit-width and a first resolution; generate a second signal with the first bit-width and a second resolution by applying a first resolution reduction function to the first signal, the first resolution reduction function being associated with the first resolution reduction, and the second resolution being lower than the first resolution; and output the second signal to the first signal processing circuit.

2. The apparatus of claim 1, wherein the first resolution reduction circuit is further configured to: access the first resolution reduction function upon receipt of the first resolution configuration signal.

3. The apparatus of claim 2, wherein: the first bit- width includes N number of bits, and the first resolution reduction function is configured to implement N - 1 number of resolution reductions.

4. The apparatus of claim 3, wherein the first resolution reduction function includes one or more of an adder, a subtractor, or a multiplier.

5. The apparatus of claim 1, wherein: the first signal includes N number of bits and a resolution of N, the first resolution reduction includes a reduction of A - A’, and the second signal includes A number of bits and a resolution of A’.

6. The apparatus of claim 1, wherein the first signal processing circuit is configured to output a third signal with a second bit-width and a third resolution, the apparatus further comprising: a second signal processing circuit configured to process signals with the second bit-width; a second resolution reduction circuit configured to: receive a second resolution configuration signal configuring a second resolution reduction; receive the third signal with the second bit-width and the third resolution; generate a fourth signal with the second bit-width and a fourth resolution by applying a second resolution reduction function to the third signal, the second resolution reduction function being associated with the second resolution reduction, and the fourth resolution being lower than the third resolution; and output the fourth signal to the second signal processing circuit.

7. The apparatus of claim 6, wherein the second resolution reduction circuit is further configured to: access the second resolution reduction function upon receipt of the second resolution configuration signal.

8. An apparatus for digital signal processing, comprising: a memory; a first signal processor coupled to the memory and configured to process signals with a first bit-width; a first resolution converter coupled to the memory and configured to: receive a first resolution configuration signal configuring a first resolution reduction; receive a first signal with the first bit- width and a first resolution from the first signal processor; generate a second signal with a second resolution by applying a first resolution reduction function to the first signal, the first resolution reduction function being associated with the first resolution reduction, and the second resolution being lower than the first resolution; and output the second signal to the memory.

9. The apparatus of claim 8, wherein the second signal generated by the first resolution reduction converter includes a second bit width less than the first bit width.

10. The apparatus of claim 9, wherein: the first signal includes N number of bits and a resolution of N, the first resolution reduction includes a reduction ofN-N’, and the second signal includes N’ number of bits and a resolution of N’.

11. The apparatus of claim 8, wherein: the first signal includes N number of bits and a resolution of N, the first resolution reduction includes a reduction ofN-N’, and the second signal includes N number of bits and a resolution of N’.

12. The apparatus of claim 8, wherein: the first bit- width includes N number of bits, and the first resolution reduction function is configured to implement N - 1 number of resolution reductions.

13. The apparatus of claim 12, wherein the first resolution reduction function includes one or more of an adder, a subtractor, or a multiplier.

14. The apparatus of claim 8, wherein the first signal processor is configured to output a third signal with a second bit-width and a third resolution, the apparatus further comprising: a second signal processor configured to process signals with the second bit-width; a second resolution converter configured to: receive a second resolution configuration signal configuring a second resolution reduction; receive the third signal with the second bit-width and the third resolution; generate a fourth signal with the second bit-width and a fourth resolution by applying a second resolution reduction function to the third signal, the second resolution reduction function being associated with the second resolution reduction, and the fourth resolution being lower than the third resolution; and output the fourth signal to the second signal processor.

15. A method of digital signal processing, comprising: processing, using a first signal processor, signals with a first bit-width; receiving, using a first resolution converter, a first resolution configuration signal configuring a first resolution reduction; receiving, using the first resolution converter, a first signal with the first bit-width and a first resolution; generating, using the first resolution converter, a second signal with the first bit-width and a second resolution by applying a first resolution reduction function to the first signal, the first resolution reduction function being associated with the first resolution reduction, and the second resolution being lower than the first resolution; and outputting, using the first resolution converter, the second signal to the first signal processor.

16. The method of claim 15, further comprising:: accessing, using the first resolution converter, the first resolution reduction function upon receipt of the first resolution configuration signal.

17. The method of claim 16, wherein: the first bit- width includes N number of bits, and the first resolution reduction function is configured to implement N - 1 number of resolution reductions.

18. The method of claim 17, wherein the first resolution reduction function includes one or more of an adder, a subtractor, or a multiplier.

19. The method of claim 15, wherein: the first signal includes N number of bits and a resolution of N, the first resolution reduction includes a reduction of N - N and the second signal includes N number of bits and a resolution of N'. - 31 -

20. The method of claim 15, further comprising: outputting, using the first signal processor, a third signal with a second bit- width and a third resolution; processing, using a second signal processor, second signals with the second bit-width; receiving, using a second resolution converter, a second resolution configuration signal configuring a second resolution reduction; receiving, using the second resolution converter, the third signal with the second bit-width and the third resolution; generating, using the second resolution converter, a fourth signal with the second bit-width and a fourth resolution by applying a second resolution reduction function to the third signal, the second resolution reduction function being associated with the second resolution reduction, and the fourth resolution being lower than the third resolution; and outputting, using the second resolution converter, the fourth signal to the second signal processor.