WO2022143809A1 - 超导量子芯片结构以及超导量子芯片制备方法 - Google Patents

超导量子芯片结构以及超导量子芯片制备方法 Download PDF

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Publication number
WO2022143809A1
WO2022143809A1 PCT/CN2021/142676 CN2021142676W WO2022143809A1 WO 2022143809 A1 WO2022143809 A1 WO 2022143809A1 CN 2021142676 W CN2021142676 W CN 2021142676W WO 2022143809 A1 WO2022143809 A1 WO 2022143809A1
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structural member
connection terminal
superconducting quantum
signal transmission
transmission line
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PCT/CN2021/142676
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English (en)
French (fr)
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赵勇杰
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合肥本源量子计算科技有限责任公司
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Priority claimed from CN202011637469.8A external-priority patent/CN114692881A/zh
Priority claimed from CN202011641465.7A external-priority patent/CN114692882B/zh
Application filed by 合肥本源量子计算科技有限责任公司 filed Critical 合肥本源量子计算科技有限责任公司
Priority to EP21914541.4A priority Critical patent/EP4227862A4/en
Publication of WO2022143809A1 publication Critical patent/WO2022143809A1/zh
Priority to US18/314,386 priority patent/US20240037438A1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N10/00—Quantum computing, i.e. information processing based on quantum-mechanical phenomena
    • G06N10/40—Physical realisations or architectures of quantum processors or components for manipulating qubits, e.g. qubit coupling or qubit control
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N60/00—Superconducting devices
    • H10N60/01—Manufacture or treatment
    • H10N60/0268—Manufacture or treatment of devices comprising copper oxide
    • H10N60/0661—Processes performed after copper oxide formation, e.g. patterning
    • H10N60/0688—Etching
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N60/00—Superconducting devices
    • H10N60/01—Manufacture or treatment
    • H10N60/0912—Manufacture or treatment of Josephson-effect devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N60/00—Superconducting devices
    • H10N60/80—Constructional details
    • H10N60/805—Constructional details for Josephson-effect devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N69/00—Integrated devices, or assemblies of multiple devices, comprising at least one superconducting element covered by group H10N60/00
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N60/00—Superconducting devices
    • H10N60/01—Manufacture or treatment
    • H10N60/0241—Manufacture or treatment of devices comprising nitrides or carbonitrides

Definitions

  • the present application belongs to the technical field of quantum computing and chip preparation, and particularly relates to a superconducting quantum chip structure and a superconducting quantum chip preparation method.
  • a quantum computer is a kind of physical device that follows the laws of quantum mechanics to perform high-speed mathematical and logical operations, store and process quantum information.
  • Quantum computers are mainly characterized by fast running speed, strong ability to handle information, and wide application range.
  • the core of a quantum computer is a quantum processor, also known as a superconducting quantum chip.
  • a classical integrated circuit chip constructs classical bits through transistors, and a binary information unit is a classical bit, while superconducting quantum chips use different physical systems to construct qubits, such as Superconducting quantum chips use Josephson junctions to realize two-level systems.
  • the state of a bit is unique, while quantum mechanics allows a qubit to be a superposition of two states at the same time.
  • Quantum computing technology uses two Quantum states are superimposed and entangled to perform qubit-based operations. The more qubits there are, the more computing power a quantum computer has.
  • Superconducting quantum chips are equipped with qubits, reading cavities, microwave circuits and signal ports, etc., and these components are integrated on the surface of a substrate, but with the improvement of the computing power requirements of quantum computers, the number of qubits is increasing.
  • the size of superconducting quantum chips prepared on a single substrate with a two-dimensional structure will become larger and larger, making it difficult to integrate.
  • the present application provides a superconducting quantum chip structure, which can reduce the plane size of the superconducting quantum chip and improve the integration degree of a multi-bit superconducting quantum chip, thereby at least solving the problem of deficiencies in related technologies.
  • a superconducting quantum chip structure which may include a first structural member, a second structural member, and a supporting connection member; wherein the first structural member is provided with qubits, a reading cavity and a A first connection terminal, wherein the qubit and the read cavity are coupled and connected, and the qubit and the first connection terminal are electrically connected; the second structural member is provided with an electrically connected signal transmission line and a first connection terminal; Two connection terminals; the two ends of the support connector are respectively electrically connected to the first connection terminal and the second connection terminal, and the support connector is used to transmit the control signal received on the signal transmission line to the described qubits.
  • the qubit and the read cavity may be located on the first surface of the first structure member
  • the first connection terminal may be located on the second surface of the first structure member
  • the first structure The component is also provided with a first through hole penetrating the first surface and the second surface of the first structural component, the first through hole is filled with a first metal layer, and the first metal layer is used to electrically connect all the components. the quantum bit and the first connection terminal.
  • the first connection terminals may be distributed along the circumference of the first through hole on the second surface of the first structural member and be coaxial with the first through hole.
  • the quantum bit, the read cavity and the first connection terminal may be located on the second surface of the first structural member, and the signal transmission line and the second connection terminal may be located on the second surface The first surface of the structural member, wherein the second surface of the first structural member is disposed opposite to the first surface of the second structural member.
  • the qubit, the read cavity and the first connection terminal may all be located on the second surface of the first structural member, and the second connection terminal is located on the second surface of the second structural member.
  • a surface, the signal transmission line is located on the second surface of the second structural member, and the second structural member is provided with a second through hole penetrating the first surface and the second surface of the second structural member, so The second through hole is filled with a first metal layer, and the first metal layer is used to electrically connect the second connection terminal and the signal transmission line.
  • the shape of the axial cross-section of the first through hole and the second through hole may be trapezoidal.
  • the material of the first metal layer may be a superconducting material.
  • the superconducting material may be titanium nitride, and the material of the supporting connector may be indium.
  • the surface of the first metal layer may be filled with a protective film.
  • the support connector may be cylindrical in shape.
  • the superconducting quantum chip structure of the present application may include a first structural member, a second structural member and a supporting connecting member; wherein, the first structural member is provided with a quantum bit, a reading cavity and a first structural member. a connection terminal, wherein the qubit and the read cavity are coupled and connected, and the qubit and the first connection terminal are electrically connected; the second structural member is provided with an electrically connected signal transmission line and a second a connection terminal; two ends of the support connection piece are respectively electrically connected to the first connection terminal and the second connection terminal, and the support connection piece is used for transmitting the control signal received on the signal transmission line to the qubits.
  • the quantum bits disposed on the first structural part are The bit and the signal transmission line of the second structural member are electrically connected to form a complete superconducting quantum chip structure, which greatly reduces the plane size of the superconducting quantum chip and improves the integration of multi-bit superconducting quantum chips. Spend.
  • the present application also provides a method for preparing a superconducting quantum chip, and the method for preparing a superconducting quantum chip can provide a method for preparing a superconducting quantum chip with a highly integrated three-dimensional structure.
  • inventions of the present application provide a method for preparing a superconducting quantum chip, the method may include:
  • a quantum bit, a read cavity and a first connection terminal are formed on the first structural member, wherein the quantum bit and the read cavity are coupled and connected, and the quantum bit and the first connection terminal are electrically connected;
  • a signal transmission line and a second connection terminal are formed on the two structural members, wherein the signal transmission line and the second connection terminal are electrically connected;
  • a support connection member is formed, and two ends of the support connection member are respectively electrically connected to the first connection a terminal and the second connection terminal, and the support connector is used for transmitting the control signal received on the signal transmission line to the quantum bit.
  • the step of forming the qubit, the read cavity and the first connection terminal on the first structural member may include: forming a first pass through the first surface and the second surface of the first structural member a hole; filling the first metal layer in the first through hole; forming the first connection terminal on the second surface of the first structural member; forming the quantum on the first surface of the first structural member bit and the read cavity; wherein, the first metal layer is used to electrically connect the quantum bit and the first connection terminal.
  • the method may include: forming a first protection on the second surface of the first structural member membrane.
  • the step of forming a first through hole penetrating the first surface and the second surface of the first structural member may include: etching the first structural member by inductively coupled plasma to form the first through hole. a through hole.
  • the step of filling the first metal layer in the first through hole may include: forming the first metal layer in the first through hole by using an atomic layer deposition technique.
  • a second protective film may be formed on the surface of the first metal layer.
  • the step of forming the qubit, the read cavity and the first connection terminal on the first structural member may include: forming the qubit, the readout cavity on the second surface of the first structural member The cavity and the first connection terminal are taken; the step of forming the signal transmission line and the second connection terminal on the second structural member includes: forming the signal transmission line and the second connection terminal on the first surface of the second structural member The second connection terminal; wherein, the first surface and the second surface are oppositely arranged.
  • the step of forming the signal transmission line and the second connection terminal on the second structural member may include: forming a second through hole penetrating the first surface and the second surface of the second structural member; The second through hole is filled with a second metal layer; the second connection terminal is formed on the first surface of the second structural member; the signal transmission line is formed on the second surface of the second structural member; wherein, The second metal layer is used to electrically connect the signal transmission line and the second connection terminal.
  • the step of forming a support connector may include: forming on the surface of the second connection terminal a support connector; and the other end of the support connector is electrically connected to the first connection terminal.
  • the step of electrically connecting the other end of the support connector to the first connection terminal may include: using flip-chip bonding technology to connect the other end of the support connector to the first connection Terminals are soldered.
  • the present application forms a quantum bit, a reading cavity and a first connection terminal on the first structural member, wherein the quantum bit and the reading cavity are coupled and connected, and the quantum bit and the
  • the first connection terminal is electrically connected; and a signal transmission line and a second connection terminal are formed on the second structural member, wherein the signal transmission line and the second connection terminal are electrically connected; and a support connection is formed, and the support Two ends of the connecting piece are respectively electrically connected to the first connecting terminal and the second connecting terminal, and the supporting connecting piece is used to transmit the control signal received on the signal transmission line to the qubit, which constitutes a complete circuit structure of a superconducting quantum chip.
  • the present application provides a method for preparing a highly integrated superconducting quantum chip.
  • FIG. 1 is a structural diagram of a superconducting quantum chip with a two-dimensional structure in the related art
  • Fig. 2 is a kind of three-dimensional structure diagram of superconducting quantum chip of the application
  • Fig. 3 is the flow chart of the preparation method of the superconducting quantum chip of the application.
  • FIG. 5 is a structural diagram of the lower surface (second surface) of the first structural member of the application.
  • FIG. 6 is a structural diagram of the upper surface (first surface) of the second structural member of the application.
  • FIG. 7 is a flowchart of a method for forming a first structural member of the present application.
  • FIG. 8 is a schematic structural diagram of forming a first through hole in the present application.
  • FIG. 9 is a schematic structural diagram of the first metal layer formed on the surface of the first through hole according to the present application.
  • FIG. 10 is a schematic structural diagram of forming a second protective film in the present application.
  • FIG. 11 is a schematic diagram of removing the first protective film from the first structural member of the present application.
  • 15 is a schematic structural diagram of the second connection terminal of the second structural member of the present application.
  • 16 is a schematic structural diagram of the signal transmission line of the second structural member of the application.
  • 17 is a three-dimensional structural diagram of the third superconducting quantum chip of the application.
  • FIG. 19 is a schematic diagram of the structure of a chip prepared by the third method for preparing a superconducting quantum chip in the present application.
  • FIG. 20 is a schematic flowchart of the application for forming a support connector
  • FIG. 21 is a schematic structural diagram of forming a support connector according to the present application.
  • the structure diagram of the superconducting quantum chip shown in FIG. 1 is a two-dimensional structure commonly used at present. Specifically, qubits 101 are prepared on a substrate 1 through the process flow of exposure, development, etching, film deposition, etc.
  • the reading cavity 12 for reading the qubits 11 the signal transmission line 13 for controlling the qubits 11 , and the external signal ports of each qubit 11 .
  • Each quantum bit 11 corresponds to a circuit structure, and the superconducting quantum chip shown in FIG. 1 is only 6 bits. It is conceivable that when the bits are increased to hundreds or even thousands, in order to integrate the circuit structure of so many qubits 11 on one substrate, it is conceivable that the plane size of the superconducting quantum chip needs to be very large.
  • the present application provides a superconducting quantum chip structure
  • the superconducting quantum chip structure includes a first structural member 10, a second structural member 20 and a supporting connecting member 30; wherein, the first structural member 10 is provided with a qubit 101, a reading cavity 102, and a first connection terminal 103, wherein the qubit 101 and the reading cavity 102 are coupled and connected, and the qubit 101 and the first connection terminal 103 are electrically connected.
  • the second structural member 20 is provided with a signal transmission line 201 and a second connection terminal 202 that are electrically connected; the two ends of the support connection member 30 are respectively electrically connected to the first connection terminal 103 and the second connection
  • the terminal 202 is used to transmit the control signal received on the signal transmission line 201 to the qubit 101, so as to construct a complete superconducting quantum circuit.
  • the superconducting quantum chip includes: the quantum bit 101 for performing quantum computation, the reading cavity 102 for reading the quantum state of the quantum bit 101 , and the signal for regulating the quantum bit 101
  • the first structural member 10 may be a substrate or wafer that uses a substrate or wafer and prepares the qubit 101 , the read cavity 102 and the first connection terminal 103 on the surface structure; similarly, the second structure member 20 may be a structure in which the signal transmission line 201 and the second connection terminal 202 are prepared on the surface of a substrate or wafer.
  • the embodiment of the present application provides a multi-layer superconducting quantum chip three-dimensional structure, which is used to arrange each circuit structure of the superconducting quantum chip in layers.
  • the qubit 101 and the read cavity 102 for running quantum computing are arranged on the first layer (ie, the first structural member 10 ), wherein the read cavity 102 needs to perform the operation with the qubit 101 Coupling is used to read the quantum state of the qubit 101 . Therefore, in order to ensure the effect of signal coupling, the reading cavity 102 and the qubit 101 are arranged on the same layer and close to each other.
  • the signal transmission line 201 for regulating the quantum state of the qubit 101 is provided on the second layer (ie, the second structural member 20 ).
  • this layer is only used for setting the signal transmission line 201 , the When wiring, it can be planned reasonably to reduce the crosstalk between the signal transmission lines 201 .
  • the signal transmission lines 201 corresponding to the qubits 101 with larger frequency intervals may be adjacently arranged through the frequency parameters of the qubits 101, thereby reducing mutual influence.
  • the first connection terminal 103 electrically connected to the qubit 101 is formed on the first structural member 10 respectively, and the first connection terminal 103 is formed on the first structural member 10 respectively.
  • the second connecting terminal 202 electrically connected to the signal transmission line 201 is formed on the two structural members 20 , and the first structural member 10 and the second structural member 20 are opposed to each other by disposing the supporting connecting member 30 .
  • the qubit 101 and the signal transmission line 201 can be realized by electrically connecting the first connection terminal 103 and the second connection terminal 202 through the two ends of the support connector 30 .
  • the reading cavity 102 is coupled to the qubit 101, and the quantum state of the qubit 101 can also be read through the signal transmission line 201, so as to finally improve the circuit structure of the superconducting quantum chip.
  • the superconducting quantum chip structure of the present application is provided with a first structural member 10, a second structural member 20 and a supporting connector 30; wherein, the first structural member 10 is provided with a quantum bit 101, a reading cavity 102 and a first structural member 101.
  • the second structural member 20 is provided with an electrical connection
  • the signal transmission line 201 and the second connection terminal 202 of the The control signal received on the signal transmission line 201 is transmitted to the qubit 101 .
  • the qubit 101, the reading cavity 102 and the signal transmission line 201 are electrically connected to form a complete superconducting quantum chip structure, which significantly reduces the plane size of the superconducting quantum chip and improves the performance of the superconducting quantum chip.
  • the integration of multi-bit superconducting quantum chips is very important.
  • the present application also provides a method for preparing a superconducting quantum chip corresponding to the above-mentioned superconducting quantum chip structure.
  • the method for forming a superconducting quantum chip may include the following steps:
  • Step S10 forming a qubit 101, a reading cavity 102 and a first connection terminal 103 on the first structural member 10, wherein the qubit 101 and the reading cavity 102 are coupled and connected, and the qubit 101 and the the first connection terminal 103 is electrically connected;
  • the qubit 101 , the read cavity 102 and the first connection terminal 103 are first formed on the first structural member 10 .
  • the qubit 101 and the read cavity 102 for performing quantum computing are formed on the first layer (ie, the first structural member 10 ), wherein the read cavity 102 is coupled with the qubit 101 to realize the Therefore, the read cavity 102 and the qubit 101 are arranged in the same layer and close to each other, which ensures the effect of signal coupling.
  • an electrical connection is required between the qubit 101 and the first connection terminal 103, so as to ensure part of the superconducting circuit structure formed on the first structural member 10 (the qubit 101, the reading cavity 102 and the A connection terminal 103) is turned on, and the first connection terminal 103 is used as a connection medium for the circuit structure on the first structural member 10, and further communicates with the transmission line formed on the second structural member 20 for transmitting control signals. electrical connection.
  • Step S20 forming a signal transmission line 201 and a second connection terminal 202 on the second structural member 20, wherein the signal transmission line 201 and the second connection terminal 202 are electrically connected;
  • the signal transmission line 201 and the second connection terminal 202 that are electrically connected are formed on the second structural member 20 , and the second connection terminal 202 is used as the circuit structure on the second structural member 20 .
  • the signal transmission line 201 for regulating the quantum state of the qubit 101 is formed on the second layer (ie, the second structural member 20 ). Since this layer is only used for setting the signal transmission line 201 , when wiring , a reasonable plan can be made to reduce the crosstalk between the signal transmission lines 201 .
  • the signal transmission lines 201 corresponding to the qubits 101 with larger frequency intervals may be adjacently arranged by using the frequency parameters of the qubits 101, thereby reducing the mutual influence.
  • both the first structural member 10 and the second structural member 20 refer to substrates for processing superconducting quantum chips, and more specifically, substrates of semiconductor materials, such as sapphire, Silicon, silicon carbide, etc.
  • Step S30 forming a support connector, two ends of the support connector are electrically connected to the first connection terminal 103 and the second connection terminal 202 respectively, and the support connector is used to connect the signal transmission line 201 to the The received control signal is transmitted to the qubits 101 .
  • the second structural member A signal transmission line 201 is formed on the 20
  • the second connection terminal 202 is used as a connection medium for the second structural member 20
  • the step of forming the support connection member 30 is performed.
  • the supporting connector 30 may be formed on the surface of the second connection terminal 202 by using an atomic layer deposition technique, and the supporting connector 30 may be peeled off the substrate.
  • the support connector is not only used to support the first structural member 10 and the second structural member 20 , but also used to electrically connect the first connection terminal 103 and the second connection terminal 202 , and the support connector is used to transmit the control signal received on the signal transmission line 201 to the quantum bit 101 .
  • the quantum bits 101 and the reading cavity 102 are formed on the first structural member 10, and the signal transmission line 201 is formed on the second structural member 20; 101 and the reading cavity 102) and the signal transmission line 201 for implementing the regulation of the qubit 101 are layered and formed separately; and the first connection terminal 103 electrically connected to the qubit 101 is formed on the first structural member 10 respectively.
  • a second connection terminal 202 electrically connected to the signal transmission line 201 is formed on the second structural member 20, and then the support connection member 30 is formed, and the two ends of the support connection member 30 are electrically connected to each other.
  • the first connection terminal 103 and the second connection terminal 202 realize the transmission of the control signal received on the signal transmission line 201 to the qubit 101, thereby forming a complete circuit structure of a superconducting quantum chip.
  • the superconducting quantum chip prepared by the method of the present application has a high degree of integration.
  • this embodiment provides a superconducting quantum chip structure.
  • the quantum bit 101 and the reading cavity 102 are located on the first surface of the first structural member 10 , so
  • the first connection terminal 103 is located on the second surface of the first structural member 10 , and the first structural member 10 is further provided with a first pass through the first surface and the second surface of the first structural member 10 .
  • the hole 104 is filled with a first metal layer 105 , and the first metal layer 105 is used to electrically connect the qubit 101 and the first connection terminal 103 .
  • the first structural member 10 and the second structural member 20 are double-sided structures and are arranged in parallel, and are supported and fixed by the support connecting member 30 , the first structural member 10 and the second structural member 20 are Both the first surface (ie the upper surface) and the second surface (ie the lower surface) of the two structural members 20 can be provided with superconducting quantum circuits.
  • the qubits 101 and the read cavity 102 are disposed on the first surface of the first structural member 10 , wherein the first surface of the first structural member is away from the second structural member 20.
  • the vertical distance between the qubit 101 and the read cavity 102 and the signal transmission line 201 of the second layer ie, the second structural member 20
  • the signal transmission line 201 of the second layer ie, the second structural member 20
  • the first through hole 104 By arranging the first through hole 104 on the first structural member 10, the first through hole 104 communicates the first surface and the second surface of the first structural member 10, and the first through hole 104 connects the first and second surfaces of the first structural member 10.
  • the first connection terminal 103 is disposed on the second surface of the 10 where the first through hole 104 is located, and the first metal layer 105 is filled in the first through hole at the same time.
  • the electrical connection between the qubits 101 on the first surface of the first structural member 10 and the first connection terminals 103 on the second surface of the first structural member 10 is realized.
  • the second connection terminal 202 and the signal transmission line 201 are electrically connected on the first surface of the second structural member 20 , and the first structural member 10 and the second structural member 20 are connected to each other.
  • a support connector 30 is provided between, and while the first structure member 10 and the second structure member 20 are supported and fixed by the support connector 30, the first connection terminal 103 and the second connection terminal 202 are realized. electrical connection. That is, the signal transmission line 201 and the qubit 101 are electrically connected through the second connection terminal 202 , the support connector 30 , the first connection terminal 103 and the first through hole 104 , thereby The effect of layered design of superconducting quantum chip structure is realized.
  • the first connection terminals 103 are provided on the second surface of the first structural member 10 , the first connection terminals 103 are located on the second surface of the first structural member 10 .
  • the surface is distributed along the circumference of the first through hole 104 and the first connection terminal 103 is coaxially disposed with the first through hole 104 .
  • the second connection terminals 202 are provided at positions corresponding to the first connection terminals 103 on the first surface of the second structural member 20 .
  • the first structural member 10 is arranged in parallel directly above the second structural member 20 , so as to form a structure in which the first through hole 104 , the first connection terminal 103 and the second connection terminal 202 are arranged coaxially , when preparing the first connecting terminal 103 of the first structural member 10 and the second connecting terminal 202 of the second structural member 20 , the same processing flow can be used, thereby simplifying the processing flow.
  • the connection between the first connecting terminal 103 and the second connecting terminal 202 and the first through hole 104 can be easily realized.
  • the alignment ensures the consistency of each of the qubit 101 circuits on the superconducting quantum chip.
  • each of the qubits 101 on the superconducting quantum chip needs to be applied with a first regulation signal for regulating frequency parameters and a second regulation signal for regulating quantum state parameters signal, and the first regulation signal and the second regulation signal need to be applied through different signal transmission lines, that is, each of the qubits 101 needs to set up two corresponding signal transmission routes, and between the two signal transmission lines They are isolated from each other, and each signal transmission path needs to pass through one of the first through holes 104, one of the first connection terminals 103, one of the second connection terminals 202, one of the support connectors 30, and one of the
  • the second connection terminal 202 forms an electrically connected signal conduction path, and constitutes a circuit structure for regulating the frequency parameter or quantum state parameter of one of the quantum bits 101 .
  • the first metal layer on each of the qubits and the two first through holes 104 105 are electrically connected, and the first metal layers 105 in the two first through holes 104 are respectively connected with the two first connection terminals 103 located on the second surface of the first structural member 10; Therefore, each of the first connection terminals 103 is electrically connected to one of the supporting connectors 30 , and the other end of the supporting connectors 30 is connected to the second surface of the first surface of the second structural member 20 .
  • the terminals 202 are electrically connected, one of the second connection terminals 202 is connected to a corresponding one of the signal transmission lines 201 , and one of the signal transmission lines 201 receives one of the first regulation signal or the second regulation signal.
  • each of the qubits 101 is correspondingly provided with two of the first through holes 104 , two of the first connection terminals 103 , two of the support connectors 30 , and two of the second The connection terminal 202 and the two signal transmission lines 201 are connected.
  • Embodiment 1 of the method for preparing a superconducting quantum chip corresponding to Embodiment 1 of the structure of the superconducting quantum chip according to the present application will be described in detail below with reference to the accompanying drawings.
  • the step of forming the qubit 101 , the reading cavity 102 and the first connection terminal 103 on the first structural member 10 includes:
  • the first structural member 10 is a double-sided substrate, and circuit structures can be provided on both the first surface and the second surface.
  • the first surface refers to the horizontally upward surface of the substrate. Two surfaces are the horizontal downward facing surface of the substrate.
  • the substrate for forming the superconducting quantum chip is usually made of materials such as sapphire, silicon, etc. Therefore, the first surface and the second surface of the first structural member 10 are isolated.
  • the first through hole 104 on the first structural member 10 penetrating the first surface and the second surface, the first surface and the second surface of the first structural member 10 can be communicated, so as to facilitate the connection between the two surfaces.
  • the circuit structure of the superconducting quantum chip is arranged on each surface.
  • the shape of the axial section of the first through hole 104 may be a trapezoid. Setting the shape of the axial section of the first through hole 104 as a trapezoid can facilitate the formation of a conductive layer on the surface of the first through hole 104 . Specifically, when the conductive layer is formed on the surface of the first through hole 104 , metal particles are hit on the surface of the first through hole 104 by using a spray gun, and the trapezoidal shape can be used to make the surface of the first through hole 104 . Metal particles can be deposited at all locations, and the conductive layer formed after metal particle deposition is more uniform.
  • a first protective film 106 needs to be formed on the second surface of the first structural member 10 . .
  • part of the processing process may also refer to the processing flow of the semiconductor chip, and the first through holes 104 penetrating the first surface and the second surface of the first structural member 10 are formed by using processed by etching process.
  • the formation of the first through holes 104 penetrating the first surface and the second surface of the first structural member 10 is achieved by etching the first surface of the first structural member 10 , so the Before the etching, the first through holes 104 are patterned on the first surface of the first structural member 10 to ensure that the shape and size of the etching are consistent with the desired shape and size.
  • a first protective film 106 is formed on the second surface of the first structural member 10 to prevent the second surface of the first structural member 10 from being etched when the first surface of the first structural member 10 is etched surface contamination.
  • the first protective film 106 can be a silicon dioxide thin film, and the first protective film 106 can be formed on the second surface of the first structural member 10 by using an electron beam evaporation coating technology.
  • the first through hole 104 when forming the first through hole 104 penetrating the first surface and the second surface of the first structure member 10 , the first through hole can be formed by using inductively coupled plasma to etch the first structure member 10 104.
  • the etching methods for the substrate include physical bombardment etching and chemical reaction etching.
  • the physical bombardment etching may include ion beam etching
  • the chemical reaction etching may include inductively coupled plasma etching.
  • chemical reactive etching is usually used for deep silicon etching.
  • the first through holes 104 to be etched in the present application penetrate through the first surface and the second surface of the first structural member 10 , that is, the first through holes 104 to be etched in the present application are relatively deep Therefore, chemical reaction etching, that is, inductively coupled plasma etching, is used to ensure that the aspect ratio of the first through hole 104 is better.
  • the first through hole 104 penetrates the first surface and the second surface of the first structural member 10 , in order to realize the electrical connection between the circuit structures on the two surfaces of the first structural member 10 .
  • An electrical connection can be achieved between the first surface and the second surface, so that when a circuit structure is formed on the first surface and the second surface, an electrical connection is formed between the circuit structures on the two surfaces.
  • the step of filling the first metal layer 105 in the first through hole 104 also needs to be performed, including: using atomic layer deposition technology in The first metal layer 105 is formed in the first through hole 104 .
  • the first metal layer 105 electrically connects the qubit 101 and the first connection terminal 103 .
  • the superconducting quantum chip has relatively high requirements on the precision of the signal. Therefore, it is necessary to ensure the performance of the circuit structure in the superconducting quantum chip, especially some structures that realize electrical connection (such as the first metal layer 105, the support connector 30) performance.
  • the atomic layer deposition technology has a high degree of controllability of deposition parameters (thickness, composition, structure), so that the first metal layer 105 formed by depositing the first metal on the surface of the first through hole 104 by using the atomic layer deposition technology is uniform. The stability and consistency are guaranteed, which in turn helps to ensure better performance and better consistency of superconducting quantum chips.
  • a second protective film 107 needs to be formed on the surface of the first metal layer 105 .
  • the first metal layer 105 is a conductive layer formed on the surface of the first through hole 104 using atomic layer deposition technology and used to electrically connect the qubit 101 and the first connection terminal 103 .
  • the first through hole 104 is first formed, and then the first metal layer 105 is formed on the inner surface of the first through hole 104 by using the atomic layer deposition technique, Then, the circuit structure of the quantum bit 101 , the read cavity 102 and the first connection terminal 103 is formed on the first structure member 10 , and then the two ends of the support connection member 30 and the first connection terminal 103 are connected together.
  • the structural member 10 and the second structural member 20 are respectively fixedly connected.
  • the first metal film is deposited on the surface of the first through hole 104 by using the atomic layer deposition technology, there are several subsequent process flows.
  • a protective film ie, the second protective film 107
  • the first metal layer 105 can be effectively prevented from being oxidized, peeled off, etc. 105 conductance characteristics.
  • the material of the second protective film 107 is preferably parylene.
  • the second protective film 107 is formed on the surface of the first through hole, in order to facilitate the formation of a corresponding circuit structure on the second surface of the first structural member 10 in the following steps, it is necessary to First, remove the first protective film 106 formed on the second surface of the first structural member 10 .
  • the silicon dioxide film ie, the first protective film 106
  • the first protective film 106 is removed by wet etching.
  • the first connection terminal 103 may be formed on the second surface of the first structural member 10 by using an atomic layer deposition technique.
  • the first connection terminals 103 are distributed along the circumferential direction of the first through holes 104 on the second surface of the first structural member 10 and the first The connection terminal 103 is coaxially disposed with the first through hole 104 , and the first connection terminal 103 is electrically connected to the first metal layer 105 filled in the first through hole 104 . Therefore, it can be ensured that when the support connector 30 is electrically connected to the first connection terminal 103 , alignment is easy and consistency is ensured.
  • S104 Form the quantum bit 101 and the read cavity 102 on the first surface of the first structural member 10 .
  • the qubit 101 is the core structure for quantum computing
  • the reading cavity 102 is a microwave resonator that reads the quantum state of the qubit 101.
  • the cavity 102 needs to be adjacent to the qubit 101, so the qubit 101 and the reading cavity 102 are arranged on the same surface (ie, the first surface) of the first structural member 10, and the first connection terminal 103 is arranged on the first structural member 10. the other surface (ie the second surface).
  • the qubit 101 when the qubit 101 is formed, the qubit 101 needs to be electrically connected to the first metal layer 105 in the first through hole 104 , and then the quantum bit 105 needs to be electrically connected to the first metal layer 105
  • the bit 101 and the first connection terminal 103 are electrically connected, that is, the purpose of connecting the read cavity 102, the qubit 101 and the first connection terminal 103 is achieved, and the first connection terminal 103 is used as the first connection terminal 103.
  • the circuit shapes of the qubit 101 and the reading cavity 102 are first formed by using ultraviolet lithography technology.
  • a patterned mask wherein the pattern structure is the specific circuit structure of the qubit 101 and the read cavity 102; and then the metal of the superconducting material is deposited in the patterned mask by using the electron beam evaporation coating technology to obtain Circuit structure of the quantum bit 101 and the read cavity 102 .
  • aluminum, niobium, tantalum, or niobium-titanium nitride, etc. can be selected. In the present application, aluminum material is preferred because of its low cost and easy formation.
  • step S103 that is, the first connection terminal is formed first
  • step S104 the quantum bit 101 and the read cavity are formed later
  • the first structural member 10 has The formation work has been preliminarily completed, and then the signal transmission line 201 and the second connection terminal 202 that are electrically connected are formed on the second structural member 20 , and the first connection terminal is electrically connected by the support connection member 30 103 and the second connection terminal 202 constitute a complete superconducting quantum chip structure.
  • the first superconducting quantum chip structure prepared by the preparation method of this embodiment includes a first structural member 10 , a second structural member 20 and a supporting connecting member 30 ;
  • a quantum bit 101, a reading cavity 102, and a first connection terminal 103 are formed, and the quantum bit 101 and the reading cavity 102 are coupled and connected, and the quantum bit 101 and the first connection terminal 103 are electrically connected;
  • the second structural member 20 is formed with a signal transmission line 201 and a second connection terminal 202 that are electrically connected; two ends of the support connection member 30 are electrically connected to the first connection terminal 103 and the second connection terminal 202 respectively.
  • the support connector is used to transmit the control signal received on the signal transmission line 201 to the quantum bit 101 to construct a complete superconducting quantum circuit.
  • the first connection terminal 103 is formed on the first structural member 10 to electrically connect the qubit 101
  • the first connection terminal 103 is formed on the first structural member 10.
  • the second connecting terminal 202 is formed on the second structural member 20 to electrically connect the signal transmission line 201
  • the supporting connecting member 30 is used to support and fix the first structural member 10 and the second structural member 20 relative to each other. And using both ends of the support connector 30 to electrically connect the first connection terminal 103 and the second connection terminal 202, the electrical connection between the quantum bit 101 and the signal transmission line 201 can be realized, Thus, the purpose of receiving a control signal through the signal transmission line 201 and regulating and controlling the qubit 101 is achieved.
  • the reading cavity 102 is coupled to the qubit 101, and the quantum state of the qubit 101 can also be read through the signal transmission line 201, so as to finally improve the circuit structure of the superconducting quantum chip.
  • each of the quantum bits 101 on the superconducting quantum chip needs to be applied with a first regulation signal for regulating frequency parameters and a second regulation signal for regulating quantum state parameters, and the The first regulation signal and the second regulation signal need to be applied through different signal transmission lines 201, that is, each of the qubits 101 needs to set up two corresponding signal transmission routes, and the two signal transmission lines 201 are isolated from each other,
  • Each signal transmission path needs to pass through one of the first through holes 104 , one of the first connection terminals 103 , one of the second connection terminals 202 , one of the support connectors 30 , and one of the second
  • the connection terminal 202 forms an electrically connected signal conduction path, and constitutes a circuit structure for regulating the frequency parameter or quantum state parameter of one of the qubits 101 .
  • the first metal layer 105 on the inner surface of the first through hole 104 is connected to the first connection terminals 103 on the second surface of the structural member 10 ; further, each of the first connection terminals 103 is electrically connected to one of the support connection members 30 , continuing with the second structural member shown in FIG. 6 .
  • the other end of the support connector 30 is electrically connected to the second connection terminal 202 on the first surface of the second structural member 20, and finally connected to a corresponding one of the signal transmission lines 201 is connected to receive one of the first regulation signal or the second regulation signal, and the support connector 30 is coaxially disposed with the second connection terminal 202 .
  • the structure directly or indirectly electrically connected to each of the qubits 101 includes two of the first through holes 104, two of the first connection terminals 103, two of the support connectors 30, Two of the second connection terminals 202 and two of the signal transmission lines 201 .
  • Embodiment 2 of the superconducting quantum chip structure is shown in FIG. 13 .
  • This embodiment provides a second superconducting quantum chip structure.
  • the qubit 101 , the reading cavity 102 and the first connection terminal 103 are all Located on the second surface of the first structural member 10
  • the signal transmission line 201 and the second connection terminal 202 are located on the first surface of the second structural member 20 .
  • the two surfaces are disposed opposite to the first surface of the second structural member 20 .
  • the superconducting quantum chip structure includes the first structural member 10 and the second structural member 20 arranged in parallel, and the qubit 101 and the reading cavity 102 are arranged on the first structural member
  • the signal transmission line 201 is arranged on the first surface of the second structural member 20 to achieve a symmetrical arrangement, and the first structural member 10 and the second structural member 10 are supported by the supporting connector 30.
  • the structural member 20 is electrically connected to the first connection terminal 103 and the second connection terminal 202 through the two ends of the support connection member 30, so as to realize the connection of the superconducting quantum circuit.
  • the qubit 101 , the read cavity 102 and the signal transmission line 201 are connected along the second surface of the first structure member 10 and the second structure by supporting the connecting member 30 .
  • the first surface of the component 20 is symmetrically arranged, and the distance between the qubit 101 and the signal transmission line 201 is pulled apart by the supporting connector 30, and the first through hole 104 does not need to be provided in the first structural component 10 , the crosstalk effect of the control signal applied on the signal transmission line 201 on the qubit 101 can be reduced, and the three-dimensional structure of the superconducting quantum chip can be realized at the same time, and the integration degree and performance of the superconducting quantum chip can be significantly improved.
  • Embodiment 2 of the method for fabricating a superconducting quantum chip corresponding to Embodiment 2 of the superconducting quantum chip structure according to the present application will be described in detail with reference to the accompanying drawings.
  • the steps of forming the qubit 101 , the reading cavity 102 and the first connecting terminal 103 on the first structural member 10 and the steps of forming the signal transmission line 201 and the second connecting terminal 202 on the second structural member 20 include:
  • Step S111 forming the qubit 101 , the reading cavity 102 and the first connection terminal 103 on the second surface of the first structural member 10 ;
  • the The qubits 101 , the read cavity 102 and the first connection terminal 103 are all processed on the same surface (ie, the second surface) of the first substrate.
  • the specific process for preparing the quantum bit 101 , the reading cavity 102 and the first connection terminal 103 is the same as that in the method embodiment 1, and will not be repeated here.
  • Step S112 forming the signal transmission line 201 and the second connection terminal 202 on the first surface of the second structural member 20 ; wherein the first surface and the second surface are disposed opposite to each other.
  • the second connection terminal 202 is formed on the first surface of the second structural member 20 , the same procedure as the step S103 (preparing the second connection terminal 202 on the second surface of the first structural member 10 is performed) The same process flow as in the first connection terminal 103); and when the signal transmission line 201 is formed on the first surface of the second structural member 20, the current common process flow in the field of chip preparation is adopted, namely exposure, development, Etching, cleaning and other processes.
  • the third metal layer 205 is formed on the first surface of the second structure member 20 , and then the signal transmission line 201 is prepared on the surface of the third metal layer 205 by a patterning process such as photolithography.
  • the third metal layer 205 electrically connects the signal transmission line 201 and the second connection terminal 202 .
  • the material of the third metal layer 205 may be a superconducting material, and specifically, the material of the third metal layer 205 may be aluminum.
  • the third metal layer 205 other than the signal transmission line 201 needs to be removed, so that the third metal layer 205 needs to be removed on the third metal layer 205.
  • the first surface of the second structure member 20 only forms the circuit structure corresponding to the signal transmission line 201 and the second connection terminal 202 .
  • FIG. 13 shows a second superconducting quantum chip structure prepared according to the method provided in this embodiment.
  • the superconducting quantum chip structure includes the first structural member 10 and the second structural member 20 , forming the quantum bit 101 , the reading cavity 102 and the first connection terminal 103 on the second surface of the first structural member 10 , and connecting the signal transmission line 201 and the second connection terminal 202 It is arranged on the first surface of the second structural member 20 to achieve symmetrical arrangement, and the first structural member 10 and the second structural member 20 are supported by the supporting connecting member 30, and the two supporting connecting member 30 are used to support the first structural member 10 and the second structural member 20.
  • the terminals are respectively electrically connected to the first connection terminal 103 and the second connection terminal 202 to realize the connection of the superconducting quantum circuit.
  • the qubit 101 , the read cavity 102 and the signal transmission line 201 are connected along the second surface of the first structural member 10 and the second structural member by using the supporting connector 30
  • the first surface of the 20 is symmetrically arranged, and the distance between the qubit 101 and the signal transmission line 201 is widened by the supporting connector 30, and the first through hole 104 does not need to be provided in the first structural member 10, In this way, the influence of the control signal applied on the signal transmission line 201 on the crosstalk of the qubit 101 can be reduced, and the three-dimensional structure of the superconducting quantum chip can be realized at the same time, and the integration degree and performance of the superconducting quantum chip can be significantly improved.
  • this embodiment provides a third superconducting quantum chip structure, and the qubit 101 , the reading cavity 102 and the first connection terminal 103 can all be located on the first structural member 10
  • the second connection terminal 202 may be located on the first surface of the second structure member 20
  • the signal transmission line 201 may be located on the second surface of the second structure member 20, and all
  • the second structural member 20 is provided with a second through hole 204 penetrating the first surface and the second surface of the second structural member 20 , the second through hole 204 is filled with the first metal layer 105 , and the second through hole 204 is filled with the first metal layer 105 .
  • a metal layer 105 is used to electrically connect the second connection terminal 202 and the signal transmission line 201 .
  • the second connecting terminal 202 of the second structural member 20 is disposed on the first surface of the second structural member 20, and the signal transmission line 201 is disposed on the first surface of the second structural member 20.
  • the second through holes 204 penetrating the first surface and the second surface of the second structural member 20 are disposed, and further formed in the second through holes 204
  • the second metal layer 203 connects the second connection terminal 202 and the signal transmission line 201 by virtue of the conductivity of the second metal layer 203 .
  • the substrate materials are usually sapphire, silicon, silicon carbide and other materials, and these materials themselves have insulating effects. Therefore, the above three structures are implemented
  • the superconducting quantum chip structures of structural embodiment 1 and structural embodiment 3 are preferentially selected, and the quantum bits 101 and 20 are separated by the insulating properties of the materials of the first structural member 10 and the second structural member 20
  • the signal transmission line 201 is isolated, and the first structural member 10 and the second structural member 20 are separated in layers through the support connector 30, which significantly reduces the control signal applied to the signal transmission line 201 Crosstalk effects on other said qubits 101 .
  • the superconducting quantum chip structure of Embodiment 1 is preferably selected, that is, the qubit 101 and the reading cavity 102 are arranged on the first structural member.
  • the first connection terminal 103 is disposed on the second surface of the first structural member 10
  • the first connecting terminal 103 is disposed through the first surface and the second surface of the first structural member 10.
  • a through hole 104 is formed, and the qubit 101 and the first connection terminal 103 are electrically connected through the first metal layer 105 filled in the first through hole 104 . This can ensure that the circuit structures of the qubits 101 and the reading cavity 102 will not be damaged when the first structural member 10 , the second structural member 20 and the supporting connecting member 30 are fixed.
  • the shape of the axial section of the first through hole 104 of the first structure body is a trapezoid.
  • the shape of the axial cross-section of the first through hole 104 is a trapezoid.
  • the shape of the axial section of the first through hole 104 is set as a trapezoid, which can facilitate the preparation of a conductive layer on the surface of the first through hole 104 by atomic deposition technology.
  • metal particles are hit on the surface of the first through hole 104 by a spray gun, and a trapezoidal shape can be used to make the first through hole 104
  • Metal particles can be deposited at all positions on the surface, and the conductive layer formed after the deposition of metal particles is more uniform.
  • the material of the first metal layer 105 is a superconducting material.
  • the chip prepared in the embodiment of the present application is a superconducting quantum chip, so the conductive structure (ie the first metal layer 105 on the surface of the first through hole 104 , the first connection between the qubit 101 and the signal transmission line 201 ) is arranged.
  • the terminal 103, the support connector 30, and the second connection terminal 202 the materials of these components all need to use superconducting materials to meet the power consumption requirements of the superconducting quantum chip.
  • the superconducting material of the first metal layer 105 is titanium nitride
  • the material of the supporting connector 30 is indium.
  • titanium nitride is used. Titanium nitride has high conductivity and high temperature resistance.
  • the supporting connector 30 is not only used to support the first structural member 10 and the second structural member 20 , but also used to support the first connecting terminal to be provided on the second surface of the first structural member 10 .
  • the material of the supporting connecting member 30 is also selected from a superconducting material.
  • the steps of preparing the supporting connector 30 include: forming the supporting connector 30 on the surface of the second connecting terminal 202 provided on the first surface of the second structural component 20 by electron beam evaporation coating technology; and forming the supporting connector 30 The other end of the connecting member 30 is fixedly connected to the first connecting terminal 103 of the first structural member 10 by welding.
  • indium is selected as the material for supporting the connecting member 30 , and the melting point of indium is lower than other superconducting materials, which is convenient for welding and avoids the influence of high temperature on the first metal layer 105 .
  • a second metal layer is provided on the first surface of the second structure member 20 .
  • the materials of the second structure member 20 are all semiconductor materials, and when the signal transmission line 201 is in the form of a microstrip transmission line, the signal transmission line 201 cannot be directly fabricated on the surface of the second structure member 20 .
  • a conductive metal layer ie, a second metal layer
  • the signal transmission line 201 is prepared on the surface of the second metal layer through a patterning process such as photolithography .
  • the second metal layer other than the signal transmission line 201 needs to be removed, so that on the first surface of the second structure member 20 Only the circuit structure corresponding to the signal transmission line 201 and the second connection terminal 202 is formed.
  • the surface of the first metal layer 105 is filled with a protective film 107 (ie, the second protective film 107 ).
  • the first metal layer 105 is a conductive layer prepared on the inner surface of the first through hole 104 by metal deposition technology for electrically connecting the qubit 101 and the first connection terminal 103 .
  • the first through hole 104 is first prepared, and then the first metal layer 105 is deposited on the inner surface of the first through hole 104 , and then continues The read cavity 102, the qubit 101 and other structures are prepared on the first surface of the first structural member 10, and two ends of the supporting connector 30 and the first structural member 10, the The second structural members 20 are respectively fixedly connected. It can be found that after the first metal film is deposited on the surface of the first through hole 104 , there are several subsequent process processes, and the support connector 30 is still in a high temperature environment when soldering. When a protective film (ie, the second protective film 107 ) is filled on the surface of the first metal layer 105 , the first metal layer 105 can be effectively prevented from being oxidized, peeled off, etc. 105 conductance characteristics.
  • a protective film ie, the second protective film 107
  • the support connector 30 is cylindrical in shape. Both ends of the support connector 30 need to be connected and fixed with the first connection terminal 103 and the second connection terminal 202 respectively by welding, and the first connection terminal 103 is on the first structural member 10 .
  • the second surface is disposed around the first through hole 104
  • the second connection terminal 202 is formed on the first surface of the second structural member 20 at a position corresponding to the first connection terminal 103
  • the connecting terminal 103 and the second connecting terminal 202 are both cylindrical, so the shape of the supporting connecting piece 30 is set to be cylindrical, and the supporting connecting piece 30 is connected to the first connecting end and the second connecting terminal 202
  • the contact area is large, and the welding effect and conduction effect can be guaranteed during welding.
  • the superconducting quantum chip structure of the present application includes a first structural member 10, a second structural member 20, and a supporting connecting member 30; wherein, the first structural member 10 is provided with qubits 101, read A cavity 102 and a first connection terminal 103, wherein the qubit 101 and the read cavity 102 are coupled and connected, and the qubit 101 and the first connection terminal 103 are electrically connected; on the second structural member 20 A signal transmission line 201 and a second connection terminal 202 are provided which are electrically connected; both ends of the support connector 30 are electrically connected to the first connection terminal 103 and the second connection terminal 202 respectively, and the support connector is used for The control signal received on the signal transmission line 201 is transmitted to the quantum bit 101 .
  • the The qubit 101 of the first structural member 10 is electrically connected to the signal transmission line 201 of the second structural member 20 to form a complete superconducting quantum chip structure, which greatly reduces the plane size of the superconducting quantum chip and improves the performance of the superconducting quantum chip.
  • the integration of multi-bit superconducting quantum chips is very important.
  • the step of forming the signal transmission line 201 and the second connection terminal 202 on the second structural member 20 includes:
  • Step S201 forming a second through hole 204 penetrating the first surface and the second surface of the second structural member 20 ;
  • the second structure member 20 is selected to form the second structure penetrating the first surface and the second surface of the second structure member 20 .
  • the through hole 204 , the second through hole 204 penetrates the first surface and the second surface of the second structural member 20 , so as to facilitate the communication between the first surface and the second surface of the second structural member 20 .
  • the method of forming the second through hole 204 on the second structural member 20 may also use inductively coupled plasma etching, which is the same as the method of forming the first through hole 104 on the first structural member 10 . The method is the same and will not be repeated here.
  • Step S202 filling the second metal layer 203 in the second through hole 204;
  • the circuit structure on the first surface of the second structure member 20 is electrically connected with the circuit structure on the second surface.
  • the method of filling the second metal layer 203 in the second through hole 204 can also use atomic layer deposition technology, which is the same as the method of forming the first metal layer 105 in the first through hole 104 , and will not be repeated here.
  • the material used for the metal layer 205 may also be the same as the material of the first metal layer 105 .
  • a third protective film 206 is also formed on the surface of the second metal layer 203 by using the atomic layer deposition technique. Wherein, the formation method and effect of the third protective film 206 are the same as the formation method and effect of the second protective film 107 , which will not be repeated here.
  • Step S203 forming the second connection terminal 202 on the first surface of the second structural member 20 ;
  • the second connection terminal 202 is directly formed on the first surface of the second structure member 20 by using atomic layer deposition technology.
  • the second connection terminal is provided corresponding to the first connection terminal 103 on the first structural member 10 , so that the support connection member 30 is used to electrically connect the first connection terminal 103 and the second connection terminal 103 .
  • Connection terminal 202 Moreover, the second connection terminals 203 are distributed along the circumference of the second through hole 204 on the second surface of the second structural member 20 , and the second connection terminal 203 is the same as the second through hole 204 .
  • the shaft is disposed, and the second connection terminal 203 is electrically connected to the second metal layer 203 filled in the second through hole 204 .
  • Step S204 forming the signal transmission line 201 on the second surface of the second structural member 20 .
  • the third metal layer 205 is firstly formed on the second surface of the second structure member 20 by atomic layer deposition technology, and the signal is formed on the third metal layer 205
  • the transmission line 201 is removed, and the third metal layer 205 except the signal transmission line 201 is removed.
  • the signal transmission line 201 and the second connection terminal 202 may be formed on different surfaces of the second structural member 20 , specifically, the second connection may be formed on the first surface of the second structural member 20
  • the terminal 202, the signal transmission line 201 is formed on the second surface of the second structure member 20, and relies on the second through hole 204 penetrating the first surface and the second surface of the second structure member 20 and the first
  • the second metal layer 203 filled in the two through holes 204 is electrically connected to the second connection terminal 202 to form a complete superconducting quantum chip circuit.
  • the qubit 101 , the reading cavity 102 and the qubit 101 are formed on the second surface of the first structural member 10
  • the first connecting terminal 103, the second connecting terminal 202 is formed on the first surface of the second structural member 20
  • the signal transmission line 201 is formed on the second surface of the second structural member 20
  • the A second through hole 204 is formed on the second structural member 20 penetrating the first surface and the second surface of the second structural member 20
  • the second through hole 204 is filled with the second metal layer 203 .
  • the second metal layer 203 electrically connects the second connection terminal 202 and the signal transmission line 201 .
  • the signal transmission line 201 is formed on the second structural member 20 while the second connection terminal 202 is formed on the first surface of the second structural member 20 .
  • the second surface of the second structure member 20 is provided with the second through hole 204 penetrating the first surface and the second surface of the second structural member 20, and the second metal layer 203 is filled in the second through hole 204,
  • the second connection terminal 202 and the signal transmission line 201 are electrically connected. Not only the distance between the signal transmission line 201 and the qubit 101 is increased, but also the insulating effect of the second structural member 20 is used, so that the crosstalk of the superconducting quantum circuit is weakened to almost negligible.
  • the substrate materials are usually sapphire, silicon, silicon carbide and other materials, and these materials themselves have insulating effects. Therefore, in the above three implementations In the example, the superconducting quantum chip structure of Method Embodiment 1 and Method Embodiment 3 is preferentially selected, and the qubit 101 and the qubit 101 and the The signal transmission line 201 is isolated, and the first structural member 10 and the second structural member 20 are separated in layers by using the support connector 30, which significantly reduces the control signal applied to the signal transmission line 201 Crosstalk effects on other said qubits 101 .
  • the method for preparing a superconducting quantum chip of Method Embodiment 1 is preferably selected, that is, the qubits 101 are formed on the first surface of the first structural member 10 .
  • the reading cavity 102 , the first connection terminal 103 is formed on the second surface of the first structural member 10 , and the first connection terminal 103 is formed through the first surface and the second surface of the first structural member 10
  • the qubit 101 and the first connection terminal 103 are electrically connected by filling the first metal layer 105 in the first through hole 104 . In this way, damage to the circuit structures of the qubits 101 and the reading cavity 102 can be avoided when the first structural member 10 , the second structural member 20 and the supporting connecting member 30 are fixedly connected.
  • the qubit 101 , the read cavity 102 and the first connection terminal 103 are respectively formed on the first structural member 10 by the previous steps, and the signal transmission line 201 is formed on the second structural member 20 . and the second connection terminal 202, that is, the step of forming the support connector can be performed.
  • the steps of forming a support connector two ends of which are electrically connected to the first connection terminal 103 and the second connection terminal 202 respectively, include:
  • Step S301 forming the support connector 30 on the surface of the second connection terminal 202;
  • Step S302 electrically connect the other end of the support connector 30 to the first connection terminal 103 .
  • the support connector 30 may be formed on the surface of the first connection terminal 103 or on the surface of the second connection terminal 202 using atomic layer deposition technology, and the support connector 30 may be formed separately.
  • the supporting connector 30 is formed on the surface of the two connecting terminals 202 by atomic layer deposition technology, it is easy to cause damage to the circuit structure of the qubit 101 and the reading cavity 102 on the first surface; After the supporting connector 30 is formed, it is difficult to fix the supporting connector 30 to the first structural member 10 and the second structural member 20 respectively, and it is difficult to ensure alignment and welding processes during the fixing and welding process . Therefore, in the present application, the supporting connector 30 is preferably formed on the surface of the second connecting terminal 202 .
  • the second connection terminal 202 is formed by an ultraviolet lithography process.
  • a pattern of the support and connector 30 is formed on the surface; and metal particles are filled in the pattern of the support and connector 30 by electron beam evaporation coating to form a cylindrical fourth metal layer (ie, the support and connector 30 ) with a specified size. .
  • the supporting connector 30 can not only be used to support the first structural member 10 and the second structural member 20 , but also can be used to provide the first connection on the second surface of the first structural member 10 .
  • the terminal 103 is electrically connected to the second connecting terminal 202 provided on the first surface of the second structural member 20 , so the material of the supporting connecting member 30 may also be a superconducting material.
  • step S301 the support connector 30 is directly formed on the surface of the second connection terminal 202 , that is, one end has been electrically connected to the second connection terminal 202 , and then the other end of the support connector 30 is electrically connected. One end is electrically connected to the first connection terminal 103 .
  • the first structure and the second structure can be supported, and the first structure and the second structure 20 can also be electrically connected, so as to connect the circuit of the superconducting quantum chip.
  • the structures ie, the qubit 101, the reading cavity 102, and the signal transmission line 201 are connected to form a complete superconducting quantum circuit.
  • the step of electrically connecting the other end of the support connector 30 to the first connection terminal 103 may include: soldering the other end of the support connector 30 to the first connection terminal 103 using flip-chip bonding technology fixed.
  • the supporting connector 30 is formed by using the electron beam evaporation coating technology, and the supporting connector 30 is formed on the surface of the second connection terminal 202 provided on the first surface of the second structural member 20 .
  • the other end of the support connector 30 and the first connection terminal 103 of the first structural member 10 also need to be fixedly connected by flip-chip welding.
  • the material indium is selected as the material for supporting the connector 30 .
  • the melting point of indium is lower than that of other superconducting materials, which is convenient for welding and avoids the influence of high temperature on the first metal layer 105 .
  • the shape of the support connector 30 is formed into a cylindrical shape, which is adapted to the shape of the first connection terminal 103 provided around the first through hole 104 to ensure that the support connector 30 and the first connection are
  • the terminal 103 and the second connection terminal 202 are arranged coaxially, and it is easy to realize the alignment of the first connection terminal 103 and the second connection terminal 202 and the first through hole 104 during fixed welding.
  • the first connecting terminal 103 is disposed around the first through hole 104 on the second surface of the first structural member 10
  • the second connecting terminal 202 is formed on the second structural member 20
  • the position of the first surface corresponding to the first connection terminal 103, the first connection terminal 103 and the second connection terminal 202 are both cylindrical in shape, therefore, the shape of the support connector 30 is set as a cylinder
  • the supporting connector 30 has a large contact area with the first connecting end and the second connecting terminal 202, which can ensure the welding effect and the conduction effect during welding. Thus, the consistency of each quantum bit 101 circuit on the superconducting quantum chip is guaranteed.
  • the present application by forming a quantum bit 101 and a reading cavity 102 on the first structural member 10, and forming a signal transmission line 201 on the second structural member 20; 101 and the reading cavity 102) and the signal transmission line 201 for implementing the regulation of the qubit 101 are layered and formed separately; and the first connection terminal 103 electrically connected to the qubit 101 is formed on the first structural member 10 respectively, and the A second connection terminal 202 electrically connected to the signal transmission line 201 is formed on the second structural member 20 , and the first connection terminal 103 and the second connection terminal 202 are electrically connected by the support connection member 30 . connected to form the circuit structure of a complete superconducting quantum chip.
  • the superconducting quantum chip prepared by the method of the present application has a high degree of integration.
  • the present application provides a superconducting quantum chip structure and a method for preparing a superconducting quantum chip, wherein the superconducting quantum chip structure includes a first structural member, a second structural member and a supporting connector; wherein, the first structural member is on the A quantum bit, a reading cavity and a first connection terminal are provided, wherein the quantum bit and the reading cavity are coupled and connected, and the quantum bit and the first connection terminal are electrically connected; A signal transmission line and a second connection terminal that are electrically connected are provided; both ends of the support connector are respectively electrically connected to the first connection terminal and the second connection terminal, and the support connector is used to connect the signal transmission line The control signal received on the qubit is transmitted to the qubit.
  • the plane size of the superconducting quantum chip structure is reduced, and the integration degree of the multi-bit superconducting quantum chip is improved.
  • a superconducting quantum chip structure and a method for fabricating a superconducting quantum chip of the present application are reproducible and can be used in various industrial applications.
  • a superconducting quantum chip structure and a superconducting quantum chip preparation method of the present application can be used in the technical fields of quantum computing and chip preparation.

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Abstract

本申请公开了一种超导量子芯片结构以及超导量子芯片制备方法，所述超导量子芯片结构包括第一结构件、第二结构件和支撑连接件；其中，所述第一结构件上设置有量子比特、读取腔和第一连接端子，其中，所述量子比特和所述读取腔耦合连接，所述量子比特和所述第一连接端子电连接；所述第二结构件上设置有电连接的信号传输线和第二连接端子；所述支撑连接件的两端分别电连接所述第一连接端子和所述第二连接端子，所述支撑连接件用于将所述信号传输线上接收到的控制信号传输至所述量子比特。通过本申请的技术方案，减小了超导量子芯片结构的平面尺寸，提高了多位的超导量子芯片的集成度。

Description

超导量子芯片结构以及超导量子芯片制备方法
相关申请的交叉引用
本申请要求于2020年12月31日提交中国国家知识产权局的申请号为202011637469.8、名称为“一种超导量子芯片结构”的中国专利申请的优先权，要求于2020年12月31日提交中国国家知识产权局的申请号为202011641465.7、名称为“一种超导量子芯片制备方法”的中国专利申请的优先权，这些专利的全部内容通过引用结合在本申请中。
技术领域
本申请属于量子计算以及芯片制备的技术领域，特别地涉及一种超导量子芯片结构以及一种超导量子芯片制备方法。
背景技术
量子计算机是一类遵循量子力学规律进行高速数学和逻辑运算、存储及处理量子信息的物理装置。量子计算机的特点主要有运行速度较快、处置信息能力较强、应用范围较广等。量子计算机的核心是量子处理器，也称作超导量子芯片，经典集成电路芯片通过一个个晶体管构建经典比特，二进制信息单元即经典比特，而超导量子芯片采用不同物理体系构建量子比特，例如超导量子芯片利用约瑟夫森结来实现二能级系统，在经典力学系统中，一个比特的状态是唯一的，而量子力学允许量子比特是同一时刻两个状态的叠加，量子计算技术用2个量子状态来叠加及纠缠，用以执行以量子比特为基础的运算。量子比特越多，量子计算机的计算能力越强。
超导量子芯片上设置有量子比特、读取腔、微波线路和信号端口等，而这些部件均集成在一块基片表面，但随着对量子计算机计算能力要求的提升，量子比特数量越来越多，在一块基片上制备二维结构的超导量子芯片的尺寸会越来越大，难以集成。
目前如何制备集成度高的超导量子芯片，成为本领域亟待解决的技术问题。
发明内容
本申请提供了一种超导量子芯片结构，所述超导量子芯片结构能够减小了所述超导量子芯片的平面尺寸，提高了多位的超导量子芯片的集成度，从而至少解决了相关技术中的不足。
本申请的一些实施方式提供了一种超导量子芯片结构，可以包括第一结构件、第二结构件和支撑连接件；其中，所述第一结构件上设置有量子比特、读取腔和第一连接端子，其中，所述量子比特和所述读取腔耦合连接，所述量子比特和所述第一连接端子电连接；所述第二结构件上设置有电连接的信号传输线和第二连接端子；所述支撑连接件的两端分别电连接所述第一连接端子和所述第二连接端子，所述支撑连接件用于将所述信号传输线上接收到的控制信号传输至所述量子比特。
可选地，所述量子比特和所述读取腔可以位于所述第一结构件的第一表面，所述第一连接端子位于所述第一结构件的第二表面，所述第一结构件还设置有贯穿所述第一结构件的第一表面和第二表面的第一通孔，所述第一通孔内填充有第一金属层，所述第一金属层用于电连接所述量子比特和所述第一连接端子。
可选地，所述第一连接端子在所述第一结构件的第二表面可以沿着所述第一通孔的周向分布且与所述第一通孔同轴。
可选地，所述量子比特、所述读取腔和所述第一连接端子可以位于所述第一结构件的第二表面，所述信号传输线和所述第二连接端子位于所述第二结构件的第一表面，其中，所述第一结构件的第二表面与所述第二结构件的第一表面相对设置。
可选地，所述量子比特、所述读取腔和所述第一连接端子可以均位于所述第一结构件的第二表面，所述第二连接端子位于所述第二结构件的第一表面，所述信号传输线位于所述第二结构件的第二表面，且所述第二结构件设置有贯穿所述第二结构件的第一表面和第二表面的第二通孔，所述第二通孔内填充有第一金属层，所述第一金属层用于电连接所述第二连接端子和所述信号传输线。
可选地，所述第一通孔和所述第二通孔的轴向截面的形状可以为梯形。
可选地，所述第一金属层的材料可以为超导材料。
可选地，所述超导材料可以为氮化钛，所述支撑连接件的材料可以为铟。
可选地，所述第一金属层的表面可以填充保护膜。
可选地，所述支撑连接件形状可以为圆柱形。
与相关技术相比，本申请的超导量子芯片结构，可以包括第一结构件、第二结构件和支撑连接件；其中，所述第一结构件上设置有量子比特、读取腔和第一连接端子，其中，所述量子比特和所述读取腔耦合连接，所述量子比特和所述第一连接端子电连接；所述第二结构件上设置有电连接的信号传输线和第二连接端子；所述支撑连接件的两端分别电连 接所述第一连接端子和所述第二连接端子，所述支撑连接件用于将所述信号传输线上接收到的控制信号传输至所述量子比特。通过在不同的结构件上设置所述量子比特、读取腔和信号传输线，并借助所述第一连接端子、第二连接端子以及所述支撑连接件将设置于所述第一结构件的量子比特和所述第二结构件的信号传输线电连接，构成了完整的超导量子芯片结构，大大的减小了所述超导量子芯片的平面尺寸，提高了多位的超导量子芯片的集成度。
本申请还提供了一种超导量子芯片制备方法，所述超导量子芯片制备方法能够提供一种制备集成度高的立体结构的超导量子芯片的方法。
本申请的另一些实施方式提供了一种超导量子芯片制备方法，所述方法可以包括：
在第一结构件上形成量子比特、读取腔和第一连接端子，其中，所述量子比特和所述读取腔耦合连接，所述量子比特和所述第一连接端子电连接；在第二结构件上形成信号传输线和第二连接端子，其中，所述信号传输线和所述第二连接端子电连接；形成支撑连接件，所述支撑连接件的两端分别电连接所述第一连接端子和所述第二连接端子，所述支撑连接件用于将所述信号传输线上接收到的控制信号传输至所述量子比特。
可选地，所述在第一结构件上形成量子比特、读取腔和第一连接端子的步骤，可以包括：形成贯穿所述第一结构件的第一表面和第二表面的第一通孔；在所述第一通孔内填充第一金属层；在所述第一结构件的第二表面形成所述第一连接端子；在所述第一结构件的第一表面形成所述量子比特和所述读取腔；其中，所述第一金属层用于电连接所述量子比特和所述第一连接端子。
可选地，在所述形成贯穿所述第一结构件的第一表面和第二表面的第一通孔的步骤之前，可以包括：在所述第一结构件的第二表面形成第一保护膜。
可选地，所述形成贯穿所述第一结构件的第一表面和第二表面的第一通孔的步骤，可以包括：利用电感耦合等离子体刻蚀所述第一结构件形成所述第一通孔。
可选地，所述在所述第一通孔内填充第一金属层的步骤，可以包括：利用原子层沉积技术在所述第一通孔内形成所述第一金属层。
可选地，在所述利用原子层沉积技术在所述第一通孔内形成所述第一金属层的步骤之后，可以在所述第一金属层表面形成第二保护膜。
可选地，所述在第一结构件上形成量子比特、读取腔和第一连接端子的步骤，可以包括：在所述第一结构件的第二表面形成所述量子比特、所述读取腔和所述第一连接端子；所述在第二结构件上形成信号传输线和第二连接端子的步骤，包括：在所述第二结构件的第一表面形成所述信号传输线和所述第二连接端子；其中，第一表面和第二表面相对设置。
可选地，所述在第二结构件上形成信号传输线和第二连接端子的步骤，可以包括：形成贯穿所述第二结构件的第一表面和第二表面的第二通孔；在所述第二通孔内填充第二金属层；在所述第二结构件的第一表面形成所述第二连接端子；在所述第二结构件的第二表面形成所述信号传输线；其中，所述第二金属层用于电连接所述信号传输线和所述第二连接端子。
可选地，所述形成支撑连接件，所述支撑连接件的两端分别电连接所述第一连接端子和所述第二连接端子的步骤，可以包括：在所述第二连接端子表面形成支撑连接件；将所述支撑连接件的另一端与所述第一连接端子电连接。
可选地，所述将所述支撑连接件的另一端与所述第一连接端子电连接的步骤，可以包括：利用倒装焊接技术将所述支撑连接件的另一端与所述第一连接端子焊接。
与相关技术相比，本申请通过在第一结构件上形成量子比特、读取腔和第一连接端子，其中，所述量子比特和所述读取腔耦合连接，所述量子比特和所述第一连接端子电连接；并在第二结构件上形成信号传输线和第二连接端子，其中，所述信号传输线和所述第二连接端子电连接；以及形成支撑连接件，并将所述支撑连接件的两端分别电连接所述第一连接端子和所述第二连接端子，所述支撑连接件用于将所述信号传输线上接收到的控制信号传输至所述量子比特，构成了完整的超导量子芯片的电路结构。本申请提供了一种制备高集成度的超导量子芯片的方法。
附图说明
图1为相关技术中的二维结构的超导量子芯片结构图；
图2为本申请的一种超导量子芯片立体结构图；
图3为本申请的超导量子芯片制备方法流程图；
图4为本申请的第一结构件的上表面(第一表面)的结构图；
图5为本申请的第一结构件的下表面(第二表面)的结构图；
图6为本申请的第二结构件的上表面(第一表面)结构图；
图7为本申请的第一结构件形成方法流程图；
图8为本申请形成第一通孔的结构示意图；
图9为本申请形成第一通孔表面的第一金属层的结构示意图；
图10为本申请形成第二保护膜的结构示意图；
图11为本申请的第一结构件去除第一保护膜示意图；
图12为本申请的第一结构件的整体结构示意图；
图13为本申请的第二种超导量子芯片立体结构图；
图14为本申请第二种超导量子芯片制备方法流程图；
图15为本申请的第二结构件的第二连接端子结构示意图；
图16为本申请的第二结构件的信号传输线结构示意图；
图17为本申请第三种超导量子芯片立体结构图；
图18为本申请的第三种超导量子芯片制备方法流程图；
图19为本申请采用第三种超导量子芯片制备方法制备的芯片结构示意图；
图20为本申请形成支撑连接件的流程示意图；
图21为本申请形成支撑连接件的结构示意图。
附图标记说明：1-衬底，11-量子比特，12-读取腔，13-信号传输线，14-信号端口，10-第一结构件，20-第二结构件，30-支撑连接件，101-量子比特，102-读取腔，103-第一连接端子，104-第一通孔，105-第一金属层，106-第一保护膜，107-第二保护膜，201-信号传输线，202-第二连接端子，203-第二金属层，204-第二通孔，205-第三金属层，206-第三保护膜。
具体实施方式
下面通过参考附图描述的实施例是示例性的，仅用于解释本申请，而不能解释为对本申请的限制。
如图1所示的超导量子芯片结构图，是目前普遍采用的二维结构，具体为在一块衬底1上通过曝光、显影、刻蚀、薄膜沉积等工艺流程制备量子比特101、用于对量子比特11进行读取的读取腔12、用于对量子比特11进行控制的信号传输线13、以及各量子比特11对外的信号端口。每一个量子比特11均对应一个电路结构，而图1所示的仅为6比特位的超导量子芯片。可以想象的是，当比特位提高到百位、甚至千位时，要想在一片衬底上集成这么多量子比特11的电路结构，可以想象的是超导量子芯片的平面尺寸需要非常大。
如图2所示，本申请提供了一种超导量子芯片结构，该超导量子芯片结构包括第一结构件10、第二结构件20和支撑连接件30；其中，所述第一结构件10上设置有量子比特101、读取腔102、第一连接端子103，其中，所述量子比特101和所述读取腔102耦合连接，所述量子比特101和所述第一连接端子103电连接；所述第二结构件20上设置有电连接的信号传输线201和第二连接端子202；所述支撑连接件30的两端分别电连接所述第一连接端子103和所述第二连接端子202，所述支撑连接件用于将所述信号传输线201上接收到的控制信号传输至所述量子比特101，从而构建完整的超导量子电路。
超导量子芯片包括：运行量子计算的所述量子比特101、对所述量子比特101的量子态进行读取的所述读取腔102、用于对所述量子比特101进行调控的所述信号传输线201、以及用于输出信号的信号端口；此外，相邻的所述量子比特101之间还可以设置耦合结构，即在有限尺寸的超导量子芯片上设置有大量的电路结构、传输线，针对多位的超导量子芯片，不仅在集成方面，难度很大，而且当对其中一个所述量子比特101进行调控时，由于传输线过于密集，还会引起信号串扰，降低超导量子芯片的性能。
在本申请的一实施例中，所述第一结构件10可以为采用一个衬底或者晶圆并在表面制备所述量子比特101、所述读取腔102和所述第一连接端子103的结构；同理，所述第二结构件20可以为采用一个衬底或者晶圆并在表面制备所述信号传输线201和所述第二连接端子202的结构。
本申请实施例提供一种多层的超导量子芯片立体结构，用于分层设置超导量子芯片的各个电路结构。具体而言，在第一层(即第一结构件10)设置运行量子计算的所述量子比特101和所述读取腔102，其中所述读取腔102是需要与所述量子比特101进行耦合作用以读取所述量子比特101的量子态，因此，为保证信号耦合的效果，所述读取腔102与所述量子比特101设置于同一层且相互靠近的位置。此外，在第二层(即第二结构件20)设置用于对所述量子比特101的量子态进行调控的所述信号传输线201，由于此层仅用于设置所述信号传输线201，因此在布线时，可以合理的规划，降低所述信号传输线201之间的串扰。例如，可以通过所述量子比特101的频率参数，将频率间隔较大的所述量子比特101对应的所述信号传输线201相邻设置，从而降低相互之间的影响。
当所述量子比特101与所述信号传输线201设置在不同层之后，分别在所述第一结构件10上形成与所述量子比特101电连接的所述第一连接端子103、在所述第二结构件20上形成与所述信号传输线201电连接的所述第二连接端子202，进而通过设置所述支撑连接件30，将所述第一结构件10和所述第二结构件20相对的支撑固定，且通过所述支撑连接件30的两端将所述第一连接端子103和所述第二连接端子202之间电连接，即可实现所述量子比特101与所述信号传输线201的电连接，来实现通过所述信号传输线201接收控制信号并对所述量子比特101进行调控的目的。同时，所述读取腔102与所述量子比特101耦合连接，也可以通过所述信号传输线201对所述量子比特101的量子态进行读取，最终完善超导量子芯片的电路结构。
本申请的超导量子芯片结构，通过设置第一结构件10、第二结构件20和支撑连接件30；其中，所述第一结构件10上设置有量子比特101、读取腔102和第一连接端子103，其中，所述量子比特101和所述读取腔102耦合连接，所述量子比特101和所述第一连接端子103电连接；所述第二结构件20上设置有电连接的信号传输线201和第二连接端子202；所述支撑连接件30的两端分别电连接所述第一连接端子103和所述第二连接端子202，所述支撑连接件30用于将所述信号传输线201上接收到的控制信号传输至所述量子比特101。通过在不同的结构件上设置所述量子比特101、读取腔102和信号传输线201，并借助所述第一连接端子103、第二连接端子202以及所述支撑连接件30将设置于所述第一结构件10的量子比特101和所述第二结构件20的信号传输线201电连接，构成了完整的超导量子芯片结构，显著地减小了所述超导量子芯片的平面尺寸，提高了多位的超导量子芯片的集成度。
本申请还提供了一种与上述超导量子芯片结构相对应的超导量子芯片制备方法。如图3所示该超导量子芯片形成方法，所述方法可以包括以下步骤：
步骤S10：在第一结构件10上形成量子比特101、读取腔102和第一连接端子103，其中，所述量子比特101和所述读取腔102耦合连接，所述量子比特101和所述第一连接端子103电连接；
具体而言，先在第一结构件10上形成量子比特101、读取腔102和第一连接端子103。在第一层(即第一结构件10)形成运行量子计算的所述量子比特101和所述读取腔102，其中，所述读取腔102与所述量子比特101进行耦合作用以实现所述量子比特101的量子态的读取，因此，所述读取腔102与所述量子比特101设置于同一层且相互靠近的位置，这保证了信号耦合的效果。此外，所述量子比特101和所述第一连接端子103之间需要电连接，这样能保证所述第一结构件10上形成的部分超导电路结构(量子比特101、读取腔102和第一连接端子103)是导通的，并将所述第一连接端子103作为第一结构件10上电路结构的连接中介，进而与第二结构件20上形成的用于传输调控信号的传输线进行电连接。
步骤S20：在第二结构件20上形成信号传输线201和第二连接端子202，其中，所述信号传输线201和所述第二连接端子202电连接；
具体而言，在所述第二结构件20上形成电连接的所述信号传输线201和所述第二连接端子202，并将所述第二连接端子202作为第二结构件20上电路结构的连接中介。在第二层(即第二结构件20)形成用于对所述量子比特101的量子态进行调控的所述信号传输线201，由于此层仅用于设置所述信号传输线201，因此在布线时，可以合理的规划，降低所述信号传输线201之间的串扰。例如，可以利用所述量子比特101的频率参数，将频率间隔较大的所述量子比特101对应的所述信号传输线201相邻设置，从而降低相互之间的影响。
需要补充的是，所述第一结构件10和所述第二结构件20均是指用于加工超导量子芯片的衬底，更具体而言，可以采用半导体材料的衬底，例如蓝宝石、硅、碳化硅等。
步骤S30：形成支撑连接件，所述支撑连接件的两端分别电连接所述第一连接端子103和所述第二连接端子202，且所述支撑连接件用于将所述信号传输线201上接收到的控制信号传输至所述量子比特101。
当分别在所述第一结构件10上形成了量子比特101和读取腔102，并将所述第一连接端子103作为第一结构件10的连接中介之后，再在所述第二结构件20上形成信号传输线201，并将所述第二连接端子202作为第二结构件20的连接中介，然后进行形成所述支撑连接件30的步骤。可以利用原子层沉积技术在第二连接端子202的表面形成所述支撑连接件30，并将所述支撑连接件30剥离所述衬底。所述支撑连接件不仅用于支撑所述第一结构件10和所述第二结构件20，所述支撑连接件还用于电连接所述第一连接端子103和所述第二连接端子202，并且所述支撑连接件用于将所述信号传输线201上接收到的控制信号传输至所述量子比特101。
本申请通过在第一结构件10上形成量子比特101和读取腔102，并在第二结构件20上形成信号传输线201；将超导量子芯片的用于实施量子计算的电路结构(量子比特101和读取腔102)与用于实施量子比特101调控的信号传输线201进行分层并单独形成；并分别在所述第一结构件10上形成与量子比特101电连接的第一连接端子103、在所述第二结构件20上形成与所述信号传输线201进行电连接的第二连接端子202，再形成所述支撑连接件30并利用所述支撑连接件 30的两端分别电连接所述第一连接端子103和所述第二连接端子202，实现了将所述信号传输线201上接收到的控制信号传输至所述量子比特101，从而构成了完整的超导量子芯片的电路结构。利用本申请的方法制备的超导量子芯片具有高集成度。
接下来首先将参照附图对根据本申请的超导量子芯片结构实施例1进行详细的描述
如图2所示，本实施例提供了一种超导量子芯片结构，具体而言，所述量子比特101和所述读取腔102位于所述第一结构件10的第一表面上，所述第一连接端子103位于所述第一结构件10的第二表面上，所述第一结构件10还设置有贯穿所述第一结构件10的第一表面和第二表面的第一通孔104，所述第一通孔104内填充有第一金属层105，所述第一金属层105用于电连接所述量子比特101和所述第一连接端子103。
由于所述第一结构件10和所述第二结构件20均为双面的结构且平行设置，并通过所述支撑连接件30进行支撑固定，因此所述第一结构件10和所述第二结构件20的第一表面(即上表面)和第二表面(即下表面)均可以设置超导量子电路。本实施例将所述量子比特101和所述读取腔102设置在所述第一结构件10上的第一表面，其中，所述第一结构件的第一表面远离所述第二结构件20。通过这样设置，可以将所述量子比特101和所述读取腔102与第二层(即第二结构件20)的所述信号传输线201的垂直距离增大，从而进一步降低所述信号传输线201上施加的控制信号对其他所述量子比特101的影响。
通过在所述第一结构件10上设置所述第一通孔104，第一通孔104将所述第一结构件10的第一表面和第二表面连通，并在所述第一结构件10的第二表面上所述第一通孔104所在位置设置所述第一连接端子103，同时在所述第一通孔内填充所述第一金属层105，借助所述第一金属层105的导电性来实现所述第一结构件10的第一表面上的所述量子比特101与所述第一结构件10的第二表面上的所述第一连接端子103的电连接。
同时，在所述第二结构件20的第一表面上设置电连接的所述第二连接端子202和所述信号传输线201，并在所述第一结构件10和所述第二结构件20之间设置支撑连接件30，通过支撑连接件30将所述第一结构件10和所述第二结构件20支撑固定的同时，所述第一连接端子103和所述第二连接端子202实现了电连接。即通过所述第二连接端子202、所述支撑连接件30、所述第一连接端子103以及所述第一通孔104实现了所述信号传输线201与所述量子比特101的电连接，从而实现了分层设计超导量子芯片结构的效果。
如图2和图5所示，在所述第一结构件10的第二表面上设置所述第一连接端子103时，所述第一连接端子103在所述第一结构件10的第二表面沿着所述第一通孔104的周向分布且所述第一连接端子103与所述第一通孔104同轴设置。同时，在第二结构件20的第一表面与第一连接端子103对应的位置设置所述第二连接端子202。第一结构件10平行地设置于第二结构件20的正上方，从而形成所述第一通孔104、所述第一连接端子103和所述第二连接端子202三者同轴设置的结构，在制备所述第一结构件10的所述第一连接端子103和所述第二结构件20的所述第二连接端子202时，可采用同样的加工流程，从而简化了工艺流程。此外，在通过支撑连接件30固定第一结构件10和第二结构件20时，可以轻松的实现所述第一连接端子103和所述第二连接端子202以及所述第一通孔104的对准，保证了超导量子芯片上每个所述量子比特101电路的一致性。
继续如图4和图5所示，所述超导量子芯片上的每一个所述量子比特101上均需要施加用于调控频率参数的第一调控信号和用于调控量子态参数的第二调控信号，而所述第一调控信号和所述第二调控信号需要通过不同的信号传输线施加，即每一个所述量子比特101均需要设置对应的两路信号传输路线，而且两路信号传输线之间相互隔离，而每一路信号传输路径均需要通过一个所述第一通孔104、一个所述第一连接端子103、一个所述第二连接端子202、一个所述支撑连接件30、以及一个所述第二连接端子202形成电连接的信号传导路径，构成对一个所述量子比特101的频率参数或者量子态参数进行调控的电路结构。在具体实施时，如图4所示的所述第一结构件的第一表面的结构图，每一个所述量子比特上与两个所述第一通孔104内的所述第一金属层105电连接，而该两个所述第一通孔104内的所述第一金属层105与位于所述第一结构件10的第二表面的两个所述第一连接端子103分别连接；因而，每一个所述第一连接端子103均电连接一个所述支撑连接件30，而所述支撑连接件30的另一端与所述第二结构件20的第一表面的所述第二连接端子202电连接，一个所述第二连接端子202与对应的一个所述信号传输线201连接，一个所述信号传输线201接收一个所述第一调控信号或所述第二调控信号。
简而言之，每一个所述量子比特101对应设置有2个所述第一通孔104、2个所述第一连接端子103、两个所述支撑连接件30、两个所述第二连接端子202和两个所述信号传输线201。
下面将参照附图对根据本申请的与上述超导量子芯片结构实施例1相对应的超导量子芯片制备方法实施例1进行详细的描述。
如图7所示，在所述第一结构件10上形成所述量子比特101、所述读取腔102和所述第一连接端子103的步骤，包括：
S101：形成贯穿所述第一结构件10的第一表面和第二表面的第一通孔104；
如图8所示，第一结构件10为双面的衬底，第一表面和第二表面均可以设置电路结构，具体而言，第一表面是指衬底的水平朝上的表面，第二表面所述衬底的水平朝下的表面。其中，形成超导量子芯片的衬底通常选用蓝宝石、硅等材料，因此，所述第一结构件10的第一表面和第二表面是隔离的。通过在所述第一结构件10上形成贯穿第一表面和第二表面的所述第一通孔104，可以将所述第一结构件10的第一表面和第二表面连通，便于在两个表面均设置超导量子芯片的电路结构。
需要补充的是，所述第一通孔104的轴向截面的形状可以为梯形。将所述第一通孔104的轴向截面的形状设置为梯形可以便于在所述第一通孔104表面形成导电层。具体而言，在所述第一通孔104表面形成导电层时，是利用喷枪将金属粒子打到所述第一通孔104表面，采用梯形的形状，可以使得所述第一通孔104表面所有位置都能沉积金属粒子，而且金属粒子沉积之后形成的导电层更均匀。
在所述形成贯穿所述第一结构件10的第一表面和第二表面的第一通孔104的步骤之前，还需要在所述第一结构件10的第二表面形成第一保护膜106。
如图8所示，本申请在具体实施时，部分加工工艺也可以参照半导体芯片的加工流程，形成贯穿所述第一结构件10的第一表面和第二表面的第一通孔104是利用刻蚀工艺加工的。具体而言，形成贯穿所述第一结构件10的第一表面和第二表面的第一通孔104是通过对所述第一结构件10的第一表面进行刻蚀来实现的，因此在刻蚀之前，在所述第一结构件10的第一表面上对第一通孔104进行图案化，保证刻蚀的形状、尺寸与期望的形状、尺寸相符合。并且在所述第一结构件10的第二表面形成第一保护膜106，从而防止在对所述第一结构件10的第一表面进行刻蚀时对所述第一结构件10的第二表面造成污染。具体而言，所述第一保护膜106可以为二氧化硅薄膜，可以利用电子束蒸发镀膜的技术在所述第一结构件10的第二表面形成所述第一保护膜106。
本申请在形成贯穿所述第一结构件10的第一表面和第二表面的第一通孔104时，可以利用电感耦合等离子体刻蚀所述第一结构10件形成所述第一通孔104。
在芯片加工流程中，对衬底的刻蚀方法有物理轰击刻蚀和化学反应刻蚀，具体地，物理轰击刻蚀可以包括离子束刻蚀，化学反应刻蚀可以包括电感耦合等离子体刻蚀。相比较而言，化学反应刻蚀通常用来做深硅刻蚀。本申请中需要刻蚀的第一通孔104是贯穿所述第一结构件10的第一表面和第二表面的，也就是说，本申请中需要刻蚀的第一通孔104是比较深的孔，因此采用化学反应刻蚀，即电感耦合等离子体刻蚀，这样可以保证所述第一通孔104的深宽比更好。
S102：在所述第一通孔104内填充第一金属层105。
如图9所示，所述第一通孔104贯穿所述第一结构件10的第一表面和第二表面，为了实现所述第一结构件10的两个表面上的电路结构之间电连通，还需要在所述第一通孔104内填充导电层(即第一金属层105)，借助所述第一金属层105的导电性，使得在所述第一结构件10的第一表面和第二表面之间能够实现电连接，以便在第一表面和第二表面形成电路结构时，使得两个表面的电路结构之间形成电连接。
在利用电感耦合等离子体刻蚀形成出所述第一通孔104之后，还需要进行在所述第一通孔104内填充所述第一金属层105的步骤，包括：利用原子层沉积技术在所述第一通孔104内形成所述第一金属层105。
所述第一金属层105将所述量子比特101和所述第一连接端子103电连接。超导量子芯片对信号的精度要求比较高，因此，需要保证所述超导量子芯片中的电路结构的性能，尤其是一些实现电连接的结构(如所述第一金属层105、所述支撑连接件30)的性能。而原子层沉积技术由于其沉积参数具有高度可控性(厚度、成份、结构)，使得利用原子层沉积技术在所述第一通孔104表面沉积第一金属形成的第一金属层105的均匀性和一致性得到保证，进而有助于保证超导量子芯片的性能更优、一致性更好。
在利用原子层沉积技术在所述第一通孔104内形成所述第一金属层105之后，还需要在所述第一金属层105表面形成第二保护膜107。
如图10所示，所述第一金属层105是利用原子层沉积技术在所述第一通孔104表面形成的用于电连接所述量子比特101和所述第一连接端子103的导电层。本申请的超导量子芯片的加工工艺过程中，是先形成所述第一通孔104、进而在所述第一通孔104的内表面利用原子层沉积技术形成所述第一金属层105，然后在所述第一结构件10上形成所述量子比特101、所述读取腔102和所述第一连接端子103的电路结构，再通过将支撑连接件30的两端和所述第一结构件10、所述第二结构件20分别固定连接。可以发现，在所述第一通孔104表面利用原子层沉积技术沉积第一金属膜之后，后续还有多个工艺流程。当在所述第一金属层105的表面形成一层保护膜(即第二保护膜107)，可以有效的防止所述第一金属层105出现氧化、脱落等情况，保证所述第一金属层105的电导特性。具体而言，所述第二保护膜107的材料优先选择聚对二甲苯。
如图11所示，在所述第一通孔表面形成所述第二保护膜107之后，为了便于后面步骤中在所述第一结构件10的所述第二表面形成相应的电路结构，需要先将在所述第一结构件10的所述第二表面形成的所述第一保护膜106去除。具体而言，利用湿法刻蚀去除所述二氧化硅薄膜(即第一保护膜106)。
S103：在所述第一结构件10的所述第二表面形成所述第一连接端子103；
如图5所示，可以利用原子层沉积技术在所述第一结构件10的第二表面形成所述第一连接端子103。此外，在形成所述第一连接端子103时，所述第一连接端子103在所述第一结构件10的第二表面沿着所述第一通孔104的周向分布且所述第一连接端子103与所述第一通孔104同轴设置，且所述第一连接端子103与所述第一通孔内104内填充的所述第一金属层105电连接。从而能够保证在将所述支撑连接件30与所述第一连接端子103电连接时，容易对准，确保一致性。
S104：在所述第一结构件10的第一表面形成所述量子比特101和所述读取腔102。
如图4所示，在超导量子芯片的电路结构中，量子比特101是进行量子计算的核心结构，而读取腔102是对量子比特101的量子态进行读取的微波谐振器，读取腔102需要与量子比特101近邻，因此将量子比特101和读取腔102设置于第一结构件10的同一个表面(即第一表面)，将第一连接端子103设置于第一结构件10的另一个表面(即第二表面)。其中，在形成所述量子比特101时，所述量子比特101需要与所述第一通孔104内的所述第一金属层105电连接，进而通过所述第一金属层105将所述量子比特101和所述第一连接端子103电连接，即实现了将所述读取腔102、量子比特101和所述第一连接端子103连通的目的，且将所述第一连接端子103作为第一结构件10的连接中介，以与所述第二结构件20上的第二连接端子202电连接。
在所述第一结构件10的第一表面形成所述量子比特101和所述读取腔102时，先利用紫外光刻技术将所述量子比特101和所述读取腔102的电路形状形成图案化的掩膜，其中的图形结构即具体的所述量子比特101和所述读取腔102的电路结构；进而利用电子束蒸发镀膜技术在图案化的掩膜内沉积超导材料的金属获得所述量子比特101和所述读取腔102的电路结构。具体而言，可以选择铝、铌、钽，或者铌钛的氮化物等，本申请优优先选择铝材料，其成本低、易于形成。
如图12所示，由于所述第一结构件10的第一表面和第二表面都需要形成电路结构，而且所述量子比特101和所述读取腔102的电路结构相对所述第一连接端子103来说，更脆弱，在形成过程中需要严格控制工艺流程，因此本申请在形成所述第一结构件10上的电路结构时，先进行步骤S103(即先形成所述第一连接端子)、进而再进行步骤S104(后形成所述量子比特101和所述读取腔)。若是调换了先后顺序，在形成所述第一连接端子103时容易损坏所述量子比特101和所述读取腔102的电路结构。
如图6所示，当利用上述步骤在所述第一结构件10上形成所述量子比特101、所述读取腔102和所述第一连接端子103之后，所述第一结构件10的形成工作已初步完成，进而在所述第二结构件20上形成电连接的所述信号传输线201和所述第二连接端子202，并借助所述支撑连接件30电连接所述第一连接端子103和所述第二连接端子202，构成完整的超导量子芯片结构。
如图2所示，采用本实施例的制备方法制备的第一种超导量子芯片结构，包括第一结构件10、第二结构件20和支撑连接件30；所述第一结构件10上形成有量子比特101、读取腔102、第一连接端子103，而且，所述量子比特101和所述读取腔102耦合连接，所述量子比特101和所述第一连接端子103电连接；所述第二结构件20上形成有电连接的信号传输线201和第二连接端子202；所述支撑连接件30的两端分别电连接所述第一连接端子103和所述第二连接端子202，并所述支撑连接件用于将所述信号传输线201上接收到的控制信号传输至所述量子比特101，构建完整的超导量子电路。
当所述量子比特101与所述信号传输线201设置在不同层之后，分别实现了在所述第一结构件10上形成所述第一连接端子103电连接所述量子比特101、在所述第二结构件20上形成所述第二连接端子202电连接所述信号传输线201，再利用所述支撑连接件30将所述第一结构件10和所述第二结构件20相对的支撑固定，且利用所述支撑连接件30的两 端将所述第一连接端子103和所述第二连接端子202之间电连接，即可实现所述量子比特101与所述信号传输线201的电连接，从而实现通过所述信号传输线201接收控制信号并对所述量子比特101进行调控的目的。同时，所述读取腔102与所述量子比特101耦合连接，也可以通过所述信号传输线201对所述量子比特101的量子态进行读取，最终完善超导量子芯片的电路结构。
需要说明的是，所述超导量子芯片上的每一个所述量子比特101上均需要施加用于调控频率参数的第一调控信号和用于调控量子态参数的第二调控信号，而所述第一调控信号和所述第二调控信号需要通过不同的信号传输线201施加，即每一个所述量子比特101均需要设置对应的两路信号传输路线，而且两路信号传输线201之间相互隔离，而每一路信号传输路径均需要通过一个所述第一通孔104、一个所述第一连接端子103、一个所述第二连接端子202、一个所述支撑连接件30、以及一个所述第二连接端子202形成电连接的信号传导路径，构成对一个所述量子比特101的频率参数或者量子态参数进行调控的电路结构。
具体实施时，如图4所示的所述第一结构件10的第一表面的结构图，每一个所述量子比特101上与两个所述第一通孔104内表面的所述第一金属层105电连接，再如图5所示的所述第一结构件10的第二表面的结构图，所述第一通孔104内表面的所述第一金属层105与所述第一结构件10的第二表面的所述第一连接端子103连接；进而，所述第一连接端子103均电连接一个所述支撑连接件30，继续如图6所示的所述第二结构件20的第一表面的结构图，所述支撑连接件30的另一端与所述第二结构件20的第一表面的所述第二连接端子202电连接，最终与对应的一个所述信号传输线201连接，接收一个所述第一调控信号或所述第二调控信号，并且所述支撑连接件30与所述第二连接端子202同轴设置。
简而言之，与每一个所述量子比特101直接或间接电连接的结构包括2个所述第一通孔104、2个所述第一连接端子103、两个所述支撑连接件30、两个所述第二连接端子202和两个所述信号传输线201。
下面参照附图对根据本申请的超导量子芯片结构实施例2进行详细的描述。
超导量子芯片结构的实施例2如图13所示，本实施例提供了第二种超导量子芯片结构，所述量子比特101、所述读取腔102和所述第一连接端子103均位于所述第一结构件10的第二表面，所述信号传输线201和所述第二连接端子202位于所述第二结构件20的第一表面，其中，所述第一结构件10的第二表面与所述第二结构件20的第一表面相对设置。
具体而言，超导量子芯片结构包括平行设置的所述第一结构件10和所述第二结构件20，将所述量子比特101和所述读取腔102设置在所述第一结构件10的第二表面，同时将所述信号传输线201设置于所述第二结构件20的第一表面，实现对称设置，并通过支撑连接件30支撑所述第一结构件10和所述第二结构件20，并通过支撑连接件30的两端分别电连接所述第一连接端子103和所述第二连接端子202，实现超导量子电路的连接。
在本实施例中，通过支撑连接件30，将所述量子比特101、所述读取腔102和所述信号传输线201沿着所述第一结构件10的第二表面和所述第二结构件20的第一表面对称设置，且通过支撑连接件30将所述量子比特101和所述信号传输线201的距离拉开，不需要在所述第一结构件10设置所述第一通孔104，即可降低所述信号传输线201上施加的调控信号对所述量子比特101的串扰影响，同时又实现了超导量子芯片的立体结构，显著地提高了超导量子芯片的集成度和性能。
接下来将参照附图对根据本申请的与超导量子芯片结构实施例2相对应的超导量子芯片制备方法实施例2进行详细的描述。
如图14所示，在第一结构件10上形成量子比特101、读取腔102和第一连接端子103以及在在第二结构件20上形成信号传输线201和第二连接端子202的步骤，包括：
步骤S111：在所述第一结构件10的第二表面形成所述量子比特101、所述读取腔102和所述第一连接端子103；
与方法实施例1中在所述第一结构件10上形成所述量子比特101、所述读取腔102和所述第一连接端子103的步骤不同是，本方法实施例2中，所述量子比特101、所述读取腔102和所述第一连接端子103均加工在所述第一衬底的同一个表面(即第二表面)。其中，具体制备所述量子比特101、所述读取腔102和所述第一连接端子103的工艺方法与方法实施例1中的相同，此处不再赘述。
步骤S112：在所述第二结构件20的所述第一表面形成所述信号传输线201和所述第二连接端子202；其中，所述第一表面和所述第二表面相对设置。
通过将所述信号传输线201和所述第二连接端子202形成在所述第二结构件20的同一个表面上，即与所述第一结构件10的第二表面相对的第一表面上，这使得所述第二连接端子202和所述第一连接端子103相对设置，这样便于在所述第二连接端子202上形成的所述支撑连接件30与所述第一连接端子103固定连接。
具体而言，在所述第二结构件20的所述第一表面形成所述第二连接端子202时，采用与所述步骤S103(在所述第一 结构件10的第二表面制备所述第一连接端子103)中相同的工艺流程；而在所述第二结构件20的所述第一表面形成所述信号传输线201时，采用目前芯片制备领域通用的工艺流程，即曝光、显影、刻蚀、清洗等工艺流程。
如图15所示，在所述第二结构件20的表面形成所述信号传输线201和所述第二连接端子202时，需要先在所述第二结构件的表面利用原子层沉积技术形成一层导电层(即第三金属层205)。因为所述第二结构件20的材料均为半导体材料，而所述信号传输线201采用微带传输线形式时，所述信号传输线201是无法直接在所述第二结构件20的表面制备的。首先在所述第二结构件20的第一表面形成所述第三金属层205，进而在所述第三金属层205的表面利用光刻等图案化工艺制备所述信号传输线201，而且可以借助所述第三金属层205使得所述信号传输线201和所述第二连接端子202电连接。其中，所述第三金属层205的材料可以选择超导材料，具体而言，所述第三金属层205的材料可以采用铝。
此外，如图16所示，当在所述第三金属层205上形成所述信号传输线201之后，需要将除所述信号传输线201以外的所述第三金属层205去除，使得在所述第二结构件20的第一表面仅形成所述信号传输线201和所述第二连接端子202对应的电路结构。
如图13所示，图13示出了按照本实施例提供的方法制备的第二种超导量子芯片结构，超导量子芯片结构包括所述第一结构件10和所述第二结构件20，在所述第一结构件10的第二表面形成所述量子比特101、所述读取腔102和所述第一连接端子103，同时将所述信号传输线201和所述第二连接端子202设置于所述第二结构件20的第一表面上，实现对称设置，并利用支撑连接件30支撑所述第一结构件10和所述第二结构件20，且利用支撑连接件30的两端分别电连接所述第一连接端子103和所述第二连接端子202以实现超导量子电路的连接。
在本实施例中，利用支撑连接件30将所述量子比特101、所述读取腔102和所述信号传输线201沿着所述第一结构件10的第二表面和所述第二结构件20的第一表面对称设置，且利用支撑连接件30将所述量子比特101和所述信号传输线201的距离拉开，不需要在所述第一结构件10设置所述第一通孔104，即可降低所述信号传输线201上施加的调控信号对所述量子比特101的串扰影响，同时又实现了超导量子芯片的立体结构，显著地提高了超导量子芯片的集成度和性能。
下面将参照附图对根据本申请的超导量子芯片结构实施例3进行详细的描述。
如图17所示，本实施例提供了第三种超导量子芯片结构，所述量子比特101、所述读取腔102和所述第一连接端子103均可以位于所述第一结构件10的第二表面上，所述第二连接端子202可以位于所述第二结构件20的第一表面上，所述信号传输线201可以位于所述第二结构件20的第二表面上，且所述第二结构件20设置有贯穿所述第二结构件20的第一表面和第二表面的第二通孔204，所述第二通孔204内填充有第一金属层105，所述第一金属层105用于电连接所述第二连接端子202和所述信号传输线201。
与结构实施例2相比，本实施例将所述第二结构件20的第二连接端子202设置于所述第二结构件20的第一表面上的同时，将所述信号传输线201设置于所述第二结构件20第二表面上，并设置贯穿所述第二结构件20的第一表面和第二表面的所述第二通孔204，进而在所述第二通孔204内形成第二金属层203，借助所述第二金属层203的导电性，使得所述第二连接端子202和所述信号传输线201进行连接。通过这种结构设计，不仅增加了所述信号传输线201与所述量子比特101的距离，也通过第二结构件20本身的绝缘效果使得超导量子电路的串扰削弱到近乎忽略不计。
需要说明的是，在芯片制备领域，尤其是超导量子芯片制备领域，衬底材料通常为蓝宝石、硅、碳化硅等材料，而这些材料本身就具有绝缘效果，因此，在上述3个结构实施例中，优先选择结构实施例1和结构实施例3的超导量子芯片结构，通过所述第一结构件10、所述第二结构件20的材料的绝缘特性来将所述量子比特101和所述信号传输线201进行隔离，并通过支撑连接件30将所述第一结构件10和所述第二结构件20进行分层隔离，非常显著地降低了所述信号传输线201上施加的控制信号对其他所述量子比特101的串扰影响。
更可选地，在结构实施例1和结构实施例3中，优先选择实施例1的超导量子芯片结构，即将所述量子比特101、所述读取腔102设置于所述第一结构件10的第一表面，将所述第一连接端子103设置于所述第一结构件10的第二表面，进而设置贯穿所述第一结构件10的第一表面和第二表面的所述第一通孔104，并通过所述第一通孔104内填充的所述第一金属层105实现所述量子比特101和所述第一连接端子103的电连接。这样可以确保在对所述第一结构件10、所述第二结构件20和所述支撑连接件30进行固定时，不会损坏所述量子比特101和所述读取腔102的电路结构。
回到图2所示，第一结构体所述第一通孔104的轴向截面的形状为梯形。本申请在所述第一结构件10上设置所述第一通孔104时，所述第一通孔104的轴向截面的形状为梯形。将所述第一通孔104的轴向截面的形状设置为梯形，可以便于在所述第一通孔104表面通过原子沉积技术制备导电层。具体而言，在所述第一通孔104表面进行导电层沉积时， 是通过喷枪将金属粒子打到所述第一通孔104表面，采用梯形的形状，可以使得所述第一通孔104表面所有位置都能沉积金属粒子，而且金属粒子沉积之后形成的导电层更均匀。
在所述第一通孔104表面设置金属层时，所述第一金属层105的材料为超导材料。本申请实施例制备的芯片为超导量子芯片，因此在设置所述量子比特101和所述信号传输线201之间的导电结构(即第一通孔104表面的第一金属层105、第一连接端子103、支撑连接件30、第二连接端子202)时，这些组成部分的材料均需要采用超导材料，满足超导量子芯片的功耗需求。
其中，所述第一金属层105的超导材料选择氮化钛，所述支撑连接件30的材料为铟。本申请在具体实施时，采用氮化钛，氮化钛的导电性能高且耐高温，当在所述第一通孔104表面制备了氮化钛材料的所述第一金属层105之后，在后续的超导量子芯片加工的工艺流程中，通过控制加工温度，可以有效的保证所述第一金属层105的性能。此外，支撑连接件30不仅用于支撑所述第一结构件10和所述第二结构件20，还用于将在所述第一结构件10的第二表面设置的所述第一连接端子103和在所述第二结构件20的第一表面设置的所述第二连接端子202电连接，因此，所述支撑连接件30的材料也选择超导材料。支撑连接件30的制备步骤包括：通过电子束蒸发镀膜技术在所述第二结构件20的第一表面设置的所述第二连接端子202的表面上生成所述支撑连接件30；以及将支撑连接件30的另一端与所述第一结构件10的第一连接端子103通过焊接的方式进行固定连接。本申请实施例选择铟作为支撑连接件30的材料，铟的熔点相对其他超导材料低一些，便于焊接，同时避免高温对所述第一金属层105的影响。
此外，在所述第二结构件20的第一表面设置有第二金属层。所述第二结构件20的材料均为半导体材料，而所述信号传输线201采用微带传输线形式时，所述信号传输线201是无法直接在所述第二结构件20的表面制备的。首先在所述第二结构件20的第一表面形成一层导电金属层(即第二金属层)，进而在所述第二金属层的表面通过光刻等图案化工艺制备所述信号传输线201。不过当在所述第二金属层上制备好所述信号传输线201之后，需要将除所述信号传输线201以外的所述第二金属层去除，使得在所述第二结构件20的第一表面仅形成所述信号传输线201和所述第二连接端子202对应的电路结构。
如图2和图4所示的超导量子芯片结构，所述第一金属层105的表面填充保护膜107(即第二保护膜107)。如前面所述，所述第一金属层105是通过金属沉积技术在所述第一通孔104的内表面制备的用于电连接所述量子比特101和所述第一连接端子103的导电层。本申请实施例涉及的超导量子芯片在加工工艺过程中，是先制备所述第一通孔104，进而在所述第一通孔104的内表面沉积所述第一金属层105，然后继续在所述第一结构件10的第一表面制备所述读取腔102、所述量子比特101等结构，以及通过焊接技术将支撑连接件30的两端和所述第一结构件10、所述第二结构件20分别固定连接。可以发现，在所述第一通孔104表面沉积第一金属膜之后，后续还有多个工艺流程，而且在焊接支撑连接件30时，还处于高温环境中。当在所述第一金属层105的表面填充一层保护膜(即第二保护膜107)，可以有效的防止所述第一金属层105出现氧化、脱落等情况，保证所述第一金属层105的电导特性。
如图2、图5和图6所示，所述支撑连接件30形状为圆柱形。所述支撑连接件30的两端需要分别与所述第一连接端子103、所述第二连接端子202通过焊接方式连接固定，而所述第一连接端子103在所述第一结构件10的第二表面环绕所述第一通孔104设置，所述第二连接端子202形成在所述第二结构件20的第一表面与所述第一连接端子103对应的位置，且所述第一连接端子103和所述第二连接端子202均为圆柱状，因此，将所述支撑连接件30的形状设置为圆柱形，所述支撑连接件30与第一连接端、第二连接端子202的接触面积大，在进行焊接时可以保证焊接效果以及导电效果。
与相关技术相比，本申请的超导量子芯片结构包括第一结构件10、第二结构件20和支撑连接件30；其中，所述第一结构件10上设置有量子比特101、读取腔102和第一连接端子103，其中，所述量子比特101和所述读取腔102耦合连接，所述量子比特101和所述第一连接端子103电连接；所述第二结构件20上设置有电连接的信号传输线201和第二连接端子202；所述支撑连接件30的两端分别电连接所述第一连接端子103和所述第二连接端子202，所述支撑连接件用于将所述信号传输线201上接收到的控制信号传输至所述量子比特101。通过在不同的结构件上设置所述量子比特101、读取腔102和信号传输线201，并借助所述第一连接端子103、第二连接端子202以及所述支撑连接件30将设置于所述第一结构件10的量子比特101和所述第二结构件20的信号传输线201电连接，构成了完整的超导量子芯片结构，大大的减小了所述超导量子芯片的平面尺寸，提高了多位的超导量子芯片的集成度。
下面将参照附图对根据本申请的与超导量子芯片结构实施例3相对应的超导量子芯片制备方法实施例3进行详细的描述。
如图18所示，在第二结构件20上形成信号传输线201和第二连接端子202的步骤，包括：
步骤S201：形成贯穿所述第二结构件20的第一表面和第二表面的第二通孔204；
与方法实施例1中的步骤S101相比，在本实施例中，选择在所述第二结构件20上形成贯穿所述第二结构件20的第一表面和第二表面的所述第二通孔204，所述第二通孔204将所述第二结构件20的第一表面和第二表面打通，从而便于实现所述第二结构件20的第一表面和第二表面的连通。其中，在所述第二结构件20上形成所述第二通孔204的方法也可以采用电感耦合等离子体刻蚀，与在所述第一结构件10上形成所述第一通孔104的方法相同，此处不再赘述。
步骤S202：在所述第二通孔204内填充第二金属层203；
通过在所述第二通孔204内填充所述第二金属层203，将所述第二结构件20的第一表面上的电路结构和第二表面的电路结构的电连接。其中，在所述第二通孔204内填充所述第二金属层203的方法也可以采用原子层沉积技术，与在所述第一通孔104内形成所述第一金属层105的方法相同，此处不再赘述。而且，所述金属层205采用的材料也可以与所述第一金属层105的材料相同。此外，所述第二金属层203的表面也会利用原子层沉积技术形成一层第三保护膜206。其中，所述第三保护膜206的形成方法和效果与所述第二保护膜107的形成方法和效果相同，此处不再赘述。
步骤S203：在所述第二结构件20的第一表面形成所述第二连接端子202；
采用原子层沉积技术直接在所述第二结构件20的第一表面形成所述第二连接端子202。其中，所述第二连接端子与所述第一结构件10上的所述第一连接端子103对应设置，便于利用所述支撑连接件30电连接所述第一连接端子103和所述第二连接端子202。而且所述第二连接端子203在所述第二结构件20的第二表面沿着所述第二通孔204的周向分布且所述第二连接端子203与所述第二通孔204同轴设置，进而所述第二连接端子203与所述第二通孔内204内填充的所述第二金属层203电连接。
步骤S204：在所述第二结构件20的所述第二表面形成所述信号传输线201。
采用与步骤S112相同的工艺流程，先在所述第二结构件20的第二表面利用原子层沉积技术形成所述第三金属层205，并在所述第三金属层205上形成所述信号传输线201，并将除所述信号传输线201之外的所述第三金属层205去除。
可以在所述第二结构件20的不同的表面形成所述信号传输线201和所述第二连接端子202，具体而言，在所述第二结构件20的第一表面形成所述第二连接端子202，在所述第二结构件20的第二表面形成所述信号传输线201，并依靠贯穿所述第二结构件20的第一表面和第二表面的第二通孔204以及所述第二通孔204内填充的第二金属层203与所述第二连接端子202电连接，构成完整的超导量子芯片电路。
如图19所示，为按照本实施例提供的方法制备的超导量子芯片结构，在所述第一结构件10的第二表面形成所述量子比特101、所述读取腔102和所述第一连接端子103，在所述第二结构件20的第一表面形成所述第二连接端子202、并在所述第二结构件20的第二表面形成所述信号传输线201，且在所述第二结构件20上形成贯穿所述第二结构件20的第一表面和第二表面的第二通孔204，所述第二通孔204内填充有第二金属层203，利用所述第二金属层203电连接所述第二连接端子202和所述信号传输线201。
与方法实施例2相比，本实施例将所述第二连接端子202形成于所述第二结构件20的第一表面的同时，将所述信号传输线201形成于所述第二结构件20的第二表面，并设置贯穿所述第二结构件20的第一表面和第二表面的所述第二通孔204，并在所述第二通孔204内填充的第二金属层203，借助所述第二金属层203的导电性，使得所述第二连接端子202和所述信号传输线201实现电连接。不仅增加了所述信号传输线201与所述量子比特101的距离，也利用第二结构件20本身的绝缘效果，使得超导量子电路的串扰削弱到近乎忽略不计。
需要说明的是，在芯片制备领域，尤其是在超导量子芯片制备领域，衬底材料通常为蓝宝石、硅、碳化硅等材料，而这些材料本身就具有绝缘效果，因此，在上述3个实施例中，优先选择方法实施例1和方法实施例3的超导量子芯片结构，利用所述第一结构件10、所述第二结构件20的材料的绝缘特性，将所述量子比特101和所述信号传输线201进行隔离，并利用支撑连接件30将所述第一结构件10和所述第二结构件20进行分层隔离，非常显著地降低了所述信号传输线201上施加的控制信号对其他所述量子比特101的串扰影响。
更可选地，在方法实施例1和方法实施例3中，优先选择方法实施例1的超导量子芯片制备方法，即在所述第一结构件10的第一表面形成所述量子比特101、所述读取腔102，在所述第一结构件10的第二表面形成所述第一连接端子103，并形成贯穿所述第一结构件10的第一表面和第二表面的所述第一通孔104，通过在所述第一通孔104内填充所述第一金属层105实现所述量子比特101和所述第一连接端子103的电连接。这样可以避免在对所述第一结构件10、所述第二结构件20和所述支撑连接件30进行固定连接时损坏所述量子比特101和所述读取腔102的电路结构。
利用前面步骤分别在所述第一结构件10上形成所述量子比特101、所述读取腔102和所述第一连接端子103，在所述第二结构件20上形成所述信号传输线201和所述第二连接端子202，即可以进行形成所述支撑连接件的步骤。
如图20所示，形成支撑连接件，所述支撑连接件的两端分别电连接所述第一连接端子103和所述第二连接端子202的步骤，包括：
步骤S301：在所述第二连接端子202表面形成所述支撑连接件30；
步骤S302：将所述支撑连接件30的另一端与所述第一连接端子103电连接。
具体而言，所述支撑连接件30可以利用原子层沉积技术在所述第一连接端子103的表面形成或者在所述第二连接端子202的表面形成，以及单独形成所述支撑连接件30。
相比较而言，由于所述第一结构件10的第一表面需要形成所述量子比特101和所述读取腔102，当在位于所述第一结构件10的第二表面的所述第二连接端子202的表面利用原子层沉积技术形成所述支撑连接件30时，容易对所述第一表面的所述量子比特101和所述读取腔102的电路结构造成破坏影响；此外，单独形成所述支撑连接件30之后，难以将所述支撑连接件30分别与所述第一结构件10和所述第二结构件20固定，在固定及焊接过程中，难以确保对准和焊接工艺。因此，本申请优选在所述第二连接端子202表面上形成支撑连接件30。
如图21所示，当在所述第二结构件20的第一表面上形成所述信号传输线201和所述第二连接端子202之后，利用紫外光刻工艺在所述第二连接端子202的表面形成所述支撑连接件30的图案；并利用电子束蒸发镀膜在所述支撑连接件30的图案内填充金属颗粒，形成具有指定尺寸的圆柱状的第四金属层(即支撑连接件30)。
其中，支撑连接件30不仅可以用于支撑所述第一结构件10和所述第二结构件20，还可以用于将所述第一结构件10的第二表面设置的所述第一连接端子103和所述第二结构件20的第一表面设置的所述第二连接端子202电连接，因此，所述支撑连接件30的材料也可以选择超导材料。
在步骤S301中，所述支撑连接件30是在所述第二连接端子202表面上直接形成的，即一端已经与所述第二连接端子202电连接，进而将所述支撑连接件30的另一端与所述第一连接端子103进行电连接。利用所述支撑连接件30，既可以将所述第一结构和所述第二结构进行支撑，也可以将所述第一结构和第二结构件20电连接，进而将超导量子芯片的电路结构(即量子比特101、读取腔102、信号传输线201)连通，从而组成完整的超导量子电路。
将所述支撑连接件30的另一端与所述第一连接端子103电连接的步骤，可以包括：利用倒装焊接技术将所述支撑连接件30的另一端与所述第一连接端子103焊接固定。
利用电子束蒸发镀膜技术形成支撑连接件30，在所述第二结构件20的第一表面设置的所述第二连接端子202的表面上生成所述支撑连接件30。同时，还需要所述将支撑连接件30的另一端与所述第一结构件10的第一连接端子103利用倒装焊接的方式进行固定连接。本申请选择材料铟作为支撑连接件30的材料，铟的熔点相对其他超导材料低一些，便于焊接，同时避免高温对所述第一金属层105的影响。
此外，不仅所述支撑连接件30的另一端需要与所述第一连接端子103利用焊接进行固定，所述支撑连接件30与所述第二连接端子202接触的表面，也需要利用倒装焊接的方式进行固定。将所述支撑连接件30的形状形成为圆柱形，与环绕所述第一通孔104设置的所述第一连接端子103的形状适配，保证所述支撑连接件30、所述第一连接端子103和所述第二连接端子202三者同轴设置，固定焊接时容易实现所述第一连接端子103和所述第二连接端子202以及所述第一通孔104的对准。
不仅如此，所述第一连接端子103在所述第一结构件10的第二表面是环绕所述第一通孔104设置的，所述第二连接端子202形成在所述第二结构件20的第一表面与所述第一连接端子103对应的位置，所述第一连接端子103和所述第二连接端子202均为圆柱形状，因此，将所述支撑连接件30的形状设置为圆柱形，所述支撑连接件30与第一连接端、第二连接端子202的接触面积大，在进行焊接时可以保证焊接效果以及导电效果。从而保证了超导量子芯片上每个所述量子比特101电路的一致性。
本申请通过在第一结构件10上形成量子比特101、读取腔102，并在第二结构件20上形成信号传输线201；将超导量子芯片的用于实施量子计算的电路结构(量子比特101和读取腔102)与用于实施量子比特101调控的信号传输线201进行分层并单独形成；并分别在第一结构件10上形成与量子比特101电连接的第一连接端子103、在所述第二结构件20上形成与所述信号传输线201进行电连接的第二连接端子202，并利用所述支撑连接件30将所述第一连接端子103和所述第二连接端子202电连接，从而构成了完整的超导量子芯片的电路结构。通过本申请的方法制备的超导量子芯片具有高集成度。
以上依据图式所示的实施例详细说明了本申请的构造、特征及作用效果，以上所述仅为本申请的较佳实施例，但本申请不以图面所示限定实施范围，凡是依照本申请的构想所作的改变，或修改为等同变化的等效实施例，仍未超出说明书与图示所涵盖的精神时，均应在本申请的保护范围内。
工业实用性
本申请提供了一种超导量子芯片结构以及超导量子芯片制备方法，所述超导量子芯片结构包括第一结构件、第二结构件和支撑连接件；其中，所述第一结构件上设置有量子比特、读取腔和第一连接端子，其中，所述量子比特和所述读取腔耦合连接，所述量子比特和所述第一连接端子电连接；所述第二结构件上设置有电连接的信号传输线和第二连接端子；所述支撑连接件的两端分别电连接所述第一连接端子和所述第二连接端子，所述支撑连接件用于将所述信号传输线上接收到的控制信号传输至所述量子比特。通过本申请的技术方案，减小了超导量子芯片结构的平面尺寸，提高了多位的超导量子芯片的集成度。
此外，可以理解的是，本申请的一种超导量子芯片结构以及超导量子芯片制备方法是可以重现的，并且可以用在多种工业应用中。例如，本申请的一种超导量子芯片结构以及超导量子芯片制备方法可以用于量子计算以及芯片制备的技术领域。

Claims (20)

  1. 一种超导量子芯片结构，其特征在于，包括第一结构件、第二结构件和支撑连接件；其中，
    所述第一结构件上设置有量子比特、读取腔和第一连接端子，其中，所述量子比特和所述读取腔耦合连接，所述量子比特和所述第一连接端子电连接；
    所述第二结构件上设置有电连接的信号传输线和第二连接端子；
    所述支撑连接件的两端分别电连接所述第一连接端子和所述第二连接端子，所述支撑连接件用于将所述信号传输线上接收到的控制信号传输至所述量子比特。
  2. 根据权利要求1所述的超导量子芯片结构，其特征在于，所述量子比特和所述读取腔位于所述第一结构件的第一表面，所述第一连接端子位于所述第一结构件的第二表面，所述第一结构件还设置有贯穿所述第一结构件的第一表面和第二表面的第一通孔，所述第一通孔内填充有第一金属层，所述第一金属层用于电连接所述量子比特和所述第一连接端子。
  3. 根据权利要求2所述的超导量子芯片结构，其特征在于，所述第一连接端子在所述第一结构件的第二表面沿着所述第一通孔的周向分布且与所述第一通孔同轴。
  4. 根据权利要求1至3中任一项所述的超导量子芯片结构，其特征在于，所述量子比特、所述读取腔和所述第一连接端子均位于所述第一结构件的第二表面，所述信号传输线和所述第二连接端子位于所述第二结构件的第一表面，其中，所述第一结构件的第二表面与所述第二结构件的第一表面相对设置。
  5. 根据权利要求1至3中任一项所述的超导量子芯片结构，其特征在于，所述量子比特、所述读取腔和所述第一连接端子均位于所述第一结构件的第二表面，所述第二连接端子位于所述第二结构件的第一表面，所述信号传输线位于所述第二结构件的第二表面，且所述第二结构件设置有贯穿所述第二结构件的第一表面和第二表面的第二通孔，所述第二通孔内填充有第一金属层，所述第一金属层用于电连接所述第二连接端子和所述信号传输线。
  6. 根据权利要求2或5任一项所述的超导量子芯片结构，其特征在于，所述第一通孔和所述第二通孔的轴向截面的形状为梯形。
  7. 根据权利要求2或5所述的超导量子芯片结构，其特征在于，所述第一金属层的材料为超导材料。
  8. 根据权利要求7所述的超导量子芯片结构，其特征在于，所述超导材料为氮化钛，所述支撑连接件的材料为铟。
  9. 根据权利要求2或5所述的超导量子芯片结构，其特征在于，所述第一金属层的表面填充保护膜。
  10. 根据权利要求1至9中任一项所述的超导量子芯片结构，其特征在于，所述支撑连接件形状为圆柱形。
  11. 一种超导量子芯片制备方法，其特征在于，包括：
    在第一结构件上形成量子比特、读取腔和第一连接端子，其中，所述量子比特和所述读取腔耦合连接，所述量子比特和所述第一连接端子电连接；
    在第二结构件上形成信号传输线和第二连接端子，其中，所述信号传输线和所述第二连接端子电连接；
    形成支撑连接件，所述支撑连接件的两端分别电连接所述第一连接端子和所述第二连接端子，所述支撑连接件用于将所述信号传输线上接收到的控制信号传输至所述量子比特。
  12. 根据权利要求11所述的超导量子芯片制备方法，其特征在于，所述在第一结构件上形成量子比特、读取腔和第一连接端子的步骤，包括：
    形成贯穿所述第一结构件的第一表面和第二表面的第一通孔；
    在所述第一通孔内填充第一金属层；
    在所述第一结构件的第二表面形成所述第一连接端子；
    在所述第一结构件的第一表面形成所述量子比特和所述读取腔；
    其中，所述第一金属层用于电连接所述量子比特和所述第一连接端子。
  13. 根据权利要求12所述的超导量子芯片制备方法，其特征在于，在所述形成贯穿所述第一结构件的第一表面和第二表面的第一通孔的步骤之前，包括：
    在所述第一结构件的第二表面形成第一保护膜。
  14. 根据权利要求12或13所述的超导量子芯片制备方法，其特征在于，所述形成贯穿所述第一结构件的第一表面和第二表面的第一通孔的步骤，包括：
    利用电感耦合等离子体刻蚀所述第一结构件形成所述第一通孔。
  15. 根据权利要求12至14中任一项所述的超导量子芯片制备方法，其特征在于，所述在所述第一通孔内填充第一金属层的步骤，包括：
    利用原子层沉积技术在所述第一通孔内形成所述第一金属层。
  16. 根据权利要求15所述的超导量子芯片制备方法，其特征在于，在所述利用原子层沉积技术在所述第一通孔内形成所述第一金属层的步骤之后，在所述第一金属层表面形成第二保护膜。
  17. 根据权利要求11至16中任一项所述的超导量子芯片制备方法，其特征在于，所述在第一结构件上形成量子比特、读取腔和第一连接端子的步骤，包括：在所述第一结构件的第二表面形成所述量子比特、所述读取腔和所述第一连接端子；
    所述在第二结构件上形成信号传输线和第二连接端子的步骤，包括：在所述第二结构件的第一表面形成所述信号传输线和所述第二连接端子；其中，所述第一结构的第二表面和所述第二结构的第一表面相对设置。
  18. 根据权利要求11至16中任一项所述的超导量子芯片制备方法，其特征在于，所述在第二结构件上形成信号传输线和第二连接端子的步骤，包括：
    形成贯穿所述第二结构件的第一表面和第二表面的第二通孔；
    在所述第二通孔内填充第二金属层；
    在所述第二结构件的第一表面形成所述第二连接端子；
    在所述第二结构件的第二表面形成所述信号传输线；
    其中，所述第二金属层用于电连接所述信号传输线和所述第二连接端子。
  19. 根据权利要求11至18中任一项所述的超导量子芯片制备方法，其特征在于，所述形成支撑连接件，所述支撑连接件的两端分别电连接所述第一连接端子和所述第二连接端子的步骤，包括：
    在所述第二连接端子表面形成支撑连接件；
    将所述支撑连接件的另一端与所述第一连接端子电连接。
  20. 根据权利要求19所述的超导量子芯片制备方法，其特征在于，所述将所述支撑连接件的另一端与所述第一连接端子电连接的步骤，包括：
    利用倒装焊接技术将所述支撑连接件的另一端与所述第一连接端子焊接。
PCT/CN2021/142676 2020-12-31 2021-12-29 超导量子芯片结构以及超导量子芯片制备方法 WO2022143809A1 (zh)

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