WO2022143586A1 - Finfet device and forming method therefor, and electronic device - Google Patents

Finfet device and forming method therefor, and electronic device Download PDF

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Publication number
WO2022143586A1
WO2022143586A1 PCT/CN2021/141851 CN2021141851W WO2022143586A1 WO 2022143586 A1 WO2022143586 A1 WO 2022143586A1 CN 2021141851 W CN2021141851 W CN 2021141851W WO 2022143586 A1 WO2022143586 A1 WO 2022143586A1
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Prior art keywords
fins
group
etching
fin structure
forming
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PCT/CN2021/141851
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French (fr)
Chinese (zh)
Inventor
张峰溢
苏廷锜
黄崇哲
苏韦菘
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广州集成电路技术研究院有限公司
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Publication of WO2022143586A1 publication Critical patent/WO2022143586A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/66803—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with a step of doping the vertical sidewall, e.g. using tilted or multi-angled implants
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Definitions

  • the present invention relates to the field of semiconductor technology, and in particular, to a FinFET device, a method for forming the same, and an electronic device.
  • FET Field Effect Transistor
  • SRAM static random access memory
  • IC semiconductor integrated circuit
  • functional density ie, the number of interconnected devices per chip area
  • geometry size ie, the smallest component or line that can be made using a manufacturing process
  • This scaling down process generally provides benefits by increasing production efficiency and reducing associated costs.
  • Such scaling down has also increased the complexity of handling and manufacturing ICs, and to achieve such advancements, similar developments in semiconductor manufacturing are required.
  • Fin Field Effect Transistors FinFETs
  • the process of using the Fin Cut-last solution is to form an array of fin structures first, and then remove the redundant part of the fin structure by horizontal cutting and vertical cutting to form a preset fin structure.
  • the preset mask pattern is formed by photolithography, due to the optical proximity effect, the ideal image spectrum is easily distorted to a certain extent, resulting in the preset right-angle area becoming a rounded area.
  • the intersection of the horizontal cutting and the vertical cutting after the cutting is easily rounded, resulting in incomplete removal of the fin structure, thereby affecting the performance of the final formed FinFET device.
  • An object of the present invention is to provide a FinFET device, a method for forming the same, and an electronic device.
  • the technical solution adopted in the present invention is: constructing a method for forming a FinFET device, which is characterized in that it includes the following steps:
  • the isotropic etching continues to remove the remaining first fin structure, and a concave structure is formed on the substrate corresponding to the first group of fins.
  • the remaining protective film on the first set of fins is removed.
  • the second group of fins is etched through the second etching pattern, the second fin structure is removed and a second group of preset fins is formed, and meanwhile, a convex structure is formed on the substrate corresponding to the second group of fins.
  • the etching direction for etching the first group of fins and the etching direction for etching the second group of fins are perpendicular to each other.
  • a FinFET device comprising:
  • the FinFET device and the method for forming the same and the electronic device of the present invention have the following beneficial effects: in the method for forming the FinFET device provided by the present invention, before etching, a protective film is used to cover the fins, and then the fins are photoetched to forming a first etching pattern on the first group of fins, the first group of fins including the first fin structure to be removed; then etching the first group of fins and the corresponding protective film by using the first etching pattern; Then, the remaining first fin structures are removed by isotropic etching, and concave structures are formed on the substrate corresponding to the first group of fins. Therefore, the problem of rounded corners left after etching in the prior art is avoided; at the same time, the concave structure formed is beneficial to maintain the horizontal line and will not cause the bending of the device.
  • FIG. 1 is a flowchart of a method for forming an SRAM provided by an embodiment of the present invention
  • FIGS. 2-11 are top views and schematic cross-sectional views of various stages of a method for forming a FinFET device according to the present invention.
  • the first feature is formed on the second feature, which includes embodiments in which the first feature and the second feature are in direct contact, and also includes other features between the first feature and the second feature.
  • Embodiments of the features that is, the first feature and the second feature are not in direct contact.
  • repeated reference numerals or symbols may be used in different embodiments, and these repetitions are only for the purpose of simply and clearly describing the embodiments of the present invention, and do not represent a specific relationship between the different embodiments and/or structures discussed.
  • spatially relative terms such as “below”, “below”, “lower”, “above”, “higher” and similar terms may be used therein, which For convenience in describing the relationship between one element or feature(s) and another element or feature(s) in the figures, these spatially relative terms include different orientations of the device in use or operation, as well as the described orientation. When the device is turned in a different orientation (rotated 90 degrees or other orientations) , the spatially relative adjectives used therein will also be interpreted in terms of the turned orientation.
  • steps in some of the described embodiments are performed in a particular order, the steps may also be performed in other logical orders. In different embodiments, some of the described steps may be replaced or omitted, and some other operations may also be performed before, during, and/or after the steps described in the embodiments of the present invention. Other features may be added to the semiconductor device structure in the embodiments of the present invention. In different embodiments, some features may be replaced or omitted.
  • An embodiment of the present invention provides a method for forming a FinFET device.
  • a protective film is used to cover the fins, and then photolithography is performed on the fins to form a first etching pattern on the first group of fins, so that the The first group of fins includes the first fin structure to be removed; then the first group of fins and the corresponding protective film are etched by using a first etching pattern; then the remaining first fin structure is removed by isotropic etching, and A concave structure is formed on the substrate corresponding to the first group of fins.
  • the present invention removes the filleted area where the horizontal cutting and the vertical cutting intersect by wet etching, so as to avoid the problem of incomplete removal of the fin structure;
  • the structure increases the space between the contact plug and the substrate, reducing the risk of the contact plug abutting the substrate; moreover, the concave structure and the convex structure formed higher than the horizontal line of the substrate cooperate with each other to improve the stability of the device structure , reducing the risk of tilting or bending of the fin structure.
  • FIG. 1 shows a flowchart of a method 10 for forming a FinFET device according to an embodiment of the present invention
  • FIGS. 2-10 are top views and schematic cross-sectional views of various stages of the method for forming a FinFET device according to the present invention. The following describes the embodiment of the present invention by combining the flowchart of FIG. 1 with the schematic diagrams of FIGS. 2 to 10 .
  • the method 10 begins with step 101 , forming a plurality of fins 202 ( 202 a - 202 f ) on the semiconductor substrate 201 ;
  • the substrate 201 in FIG. 2 may be a semiconductor substrate, which may include elemental semiconductors, such as silicon (Si), germanium (Ge), etc.; compound semiconductors, such as gallium nitride (GaN), carbide, etc.
  • elemental semiconductors such as silicon (Si), germanium (Ge), etc.
  • compound semiconductors such as gallium nitride (GaN), carbide, etc.
  • SiC Silicon
  • GaAs gallium Arsenide
  • GaP gallium phosphide
  • InP indium phosphide
  • InAs indium antimonide
  • alloy semiconductors such as silicon germanium alloy (SiGe), gallium arsenide phosphorous (GaAsP), arsenic Aluminum Indium Alloy (AlInAs), Aluminum Gallium Arsenide (AlGaAs), Gallium Indium Arsenide (GaInAs), Gallium Indium Phosphorus (GaInP), Gallium Indium Arsenide Phosphorus (GaInAsP), or a combination thereof.
  • the fin structure (including the plurality of fins 202a-202f) is formed by any suitable process, eg, a photolithography process and an etching process.
  • the fin structure is formed by: depositing a mixed resist layer on a semiconductor substrate; patterning the resist to form gaps in the mixed resist layer; performing etching to form the Fin structure.
  • the fin structure is formed by exposing the photoresist layer to a pattern, performing a post-exposure bake process, and developing the photoresist layer to form a mask including the photoresist layer and the mask layer module components.
  • the photoresist layer patterning may include the following processing steps: photoresist coating, soft bake, mask alignment, exposure pattern, post exposure bake, developing photoresist, and hard bake.
  • patterning may also be performed or replaced by other suitable methods, such as maskless lithography, electron beam writing, ion beam writing, and molecular imprinting.
  • the masking elements (including the photoresist layer and the masking layer) can then be used in an etching process to etch the fin structure into the semiconductor substrate 201 .
  • the etch process uses a patterned mask layer to define the area to be etched and to protect other areas of the CMOSFinFET device.
  • the etching process is a dry etching process.
  • the dry etching process used to etch the semiconductor substrate 201 includes a chemical species containing a halogen gas.
  • the dry etch chemistry includes halogen-containing molecules such as Cl2, HBr, CF4, SF6, or NF3.
  • the fin structure is formed by a double patterned lithography (DPL) process.
  • DPL is a method of structuring a pattern on a semiconductor substrate by dividing the pattern into two staggered patterns. DPL allows for increased component (eg, fin) density.
  • Various DPLs available Methods include double exposure (eg, using two mask sets).
  • the method of forming the plurality of fins is merely exemplary, and is not limited to the above method.
  • the method 10 then proceeds to step 102 , covering the surfaces of the plurality of fins 202 with a protective film 203 .
  • the constituent material of the protective film 203 may vary with a particular application, as it may be composed of various materials such as silicon dioxide, silicon nitride, silicon oxynitride, and the like.
  • the protective film 203 may be composed of multiple layers of materials, such as a material stack including a silicon dioxide layer (eg, pad oxide), a silicon nitride layer (eg, pad nitride), and a silicon dioxide protective layer.
  • the method 10 then proceeds to step 103 of performing a photolithography process on the plurality of fins 202 so as to form the first set of fins (eg, the fins 202c and 202d) forming a first etching pattern 204 on the first set of fins including the first fin structure to be removed.
  • the first set of fins eg, the fins 202c and 202d
  • a photoresist layer 205 is formed over the protective film 203 , and then a first etch is formed on the first group of fins by exposing, developing and cleaning with pure water. Pattern 204 .
  • the photoresist layer 205 may be a structure made of multiple layers of different materials.
  • the method 10 then proceeds to step 104 , etching a first group of fins and a corresponding protective film through the first etching pattern, removing the first fin structure and forming a first group of predetermined fins
  • the photoresist layer 205 is removed after the shapes (210a and 210b).
  • FIGS. 5 and 6 after the fins 202c and 202d are etched using the first etch pattern, residual portions 206a and 206b of the first fin structure remain at the cut intersections.
  • the etching process may be a dry etching process (eg reactive ion etching, anisotropic plasma etching); in some embodiments, the dry etching process may be oxygen-containing gas, halogen-containing Gases (eg, CF4, SF6 , CH2F2 , CHF3 , HBr , N2 , and/or Cl2 ) , other suitable gases and/or plasmas, and/or combinations of the above are implemented.
  • halogen-containing Gases eg, CF4, SF6 , CH2F2 , CHF3 , HBr , N2 , and/or Cl2
  • the method 10 then proceeds to step 105 , isotropic etching to remove the remaining portions 206 a and 206 b of the first fin structure, and forming concave structures 207 a and 206 b on the substrate corresponding to the first group of fins 207b.
  • the first fin structure after the first group of fins is etched in the above step 104, due to the problem of rounded corners, the first fin structure still has residual portions 206a and 206b. Therefore, an isotropic etching process is performed. , the residual portions 206a and 206b are removed. In the isotropic etching process, the remaining parts of the first group of fins ( 202 c and 202 d ) are removed to form concave structures 207 a and 207 b with arc-shaped cross sections. In order to achieve isotropic etching, the isotropic etching process may be performed by a dry or wet process.
  • the concave structure of the semiconductor device is formed by controlling factors such as etching time and etching gas. But more preferably, the wet process is adopted, and the removal effect of the residual parts 206a and 206b is better.
  • the wet process may use an etchant such as ammonia water, tetramethylammonium hydroxide, TMAH, or the like.
  • the method 10 proceeds to step 106 , after the isotropic etching process, the remaining protective film on the first set of fins is removed.
  • the processing of the first group of fins (202c and 202d) is completed, and a first group of preset fins and concave structures are formed.
  • the first group of fins includes two fins ( 202c and 202d ), those skilled in the art can understand that the first group of fins may also include other numbers of fins, which is not specifically limited in the present invention.
  • Fig. 2-8 when the first group of fins is processed, the cutting process is performed in the horizontal direction. Those skilled in the art can understand that the cutting process in the vertical direction can also be performed. This is not limited.
  • step 107 performing a photolithography process on the plurality of fins to form a second set of fins (eg, fins 202e and 202f ) A second etch pattern is formed thereon, the second set of fins including the second fin structure to be removed.
  • a photolithography process on the plurality of fins to form a second set of fins (eg, fins 202e and 202f )
  • a second etch pattern is formed thereon, the second set of fins including the second fin structure to be removed.
  • a photoresist layer 208 is coated, followed by exposure, development, and pure water cleaning to form a second etch pattern on the second set of fins.
  • the method 10 then proceeds to step 108 , etching a second set of fins through the second etching pattern, removing the second fin structure and forming a second set of predetermined fins (211a and 211b), while forming convex structures 209a and 209b on the substrate corresponding to the second group of fins.
  • the etching process may be a dry etching process (eg, reactive ion etching, anisotropic plasma etching).
  • the method 10 then proceeds to step 109 of stripping the photoresist layer.
  • the processing of the second group of fins (202e and 202f) adjacent to the first group of fins is completed.
  • the vertical cutting process is performed.
  • the first group of fins the are horizontal cuts, so vertical cuts are used when processing the second group of fins; in other embodiments, vertical cuts are used when processing the first group of fins, and vertical cuts are used when processing the second group of fins Horizontal cutting is adopted when the object is processed, which is not limited in the present invention.
  • a concave structure lower than the horizontal line of the substrate is formed in a device structure, and fin structures (not shown here) are respectively provided on both sides of the concave structure in the device structure. Thereafter, contact plugs are formed over the fin structures on both sides of the concave structure.
  • the space between the contact plug and the substrate is increased, and the risk of the contact plug abutting the substrate is reduced.
  • the present invention also provides an electronic device including a FinFET device fabricated according to the method of an exemplary embodiment of the present invention.
  • the electronic device can be any electronic product or equipment such as mobile phone, tablet computer, notebook computer, netbook, game console, TV, VCD, DVD, navigator, camera, video recorder, voice recorder, MP3, MP4, PSP, etc. is any intermediate product that includes the FinFET device.
  • the electronic device has better performance due to the use of the FinFET device.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)

Abstract

The present invention provides a FinFET device and a forming method therefor. The forming method comprises: covering, before etching, fins with a protective film, and then performing photoetching on the fins to form a first etched pattern on a first set of fins, wherein the first set of fins includes a first fin structure to be removed; etching the first set of fins and a corresponding protective film according to the first etched pattern, and removing the first fin structure to form a first set of preset fins; and removing the remains of the first fin structure by means of isotropic etching to form a concave structure in a portion of a substrate that corresponds to the first set of fins. Therefore, the problem in the prior art of fillets being left after etching is avoided; in addition, the formed concave structure is beneficial for maintaining a horizontal line and does not cause bending of the device.

Description

一种FinFET器件及其形成方法和电子装置A FinFET device and its formation method and electronic device 技术领域technical field
本发明涉及半导体技术领域，尤其涉及一种FinFET器件及其形成方法和电子装置。The present invention relates to the field of semiconductor technology, and in particular, to a FinFET device, a method for forming the same, and an electronic device.
背景技术Background technique
在半导体集成电路器件领域中，场效应晶体管 (Field Effect Transistor 缩写(FET))简称场效应管一直是用来制造专用集成电路芯片、静态随机存储器 (SRAM)芯片等产品的主要半导体器件。In the field of semiconductor integrated circuit devices, Field Effect Transistor (FET) for short has always been the main semiconductor device used to manufacture application-specific integrated circuit chips, static random access memory (SRAM) chips and other products.
半导体集成电路(IC)工业已经经历了快速的成长。在IC演变的进程中，功能密度(即，每个芯片面积上互相连接的器件的数量)已经普遍增加，同时几何尺寸(即，可以使用制造处理做出的最小的组件或线)已经减小。此按比例缩小处理一般通过增加生产效率和降低相关联的成本来提供效益。这样的按比例缩小还已经增加了处理和制造IC的复杂性，而为了实现这样的先进性，需要半导体制造中的类似发展。The semiconductor integrated circuit (IC) industry has experienced rapid growth. Over the course of IC evolution, functional density (ie, the number of interconnected devices per chip area) has generally increased while geometry size (ie, the smallest component or line that can be made using a manufacturing process) has decreased . This scaling down process generally provides benefits by increasing production efficiency and reducing associated costs. Such scaling down has also increased the complexity of handling and manufacturing ICs, and to achieve such advancements, similar developments in semiconductor manufacturing are required.
例如，随着半导体工业已经进展到追求更高的器件密度、更高的性能和更低的成本的纳米技术处理节点，来自制造和设计二者的挑战已经导致了鳍型场效应晶体管(FinFET)器件的发展。在传统方法制作FinFET器件时，采用鳍结构后去除（Fin Cut-last）方案的过程为，先形成阵列状的鳍结构，再通过水平方向切割和垂直方向切割去除多余部分鳍结构以形成预设的鳍结构。但是，在通过光刻形成预设掩膜版图案时，由于光学近邻效应，容易发生理想像频谱一定程度上的畸变，导致预设直角区域变为圆角化区域。特别地，在切割鳍结构时，切割完成后水平方向切割和垂直方向切割的交汇点容易产生圆角，造成鳍结构不完全去除，进而影响最终形成的FinFET器件的性能。For example, as the semiconductor industry has progressed to nanotechnology processing nodes in pursuit of higher device density, higher performance, and lower cost, challenges from both fabrication and design have led to Fin Field Effect Transistors (FinFETs) device development. When the FinFET device is fabricated by the traditional method, the process of using the Fin Cut-last solution is to form an array of fin structures first, and then remove the redundant part of the fin structure by horizontal cutting and vertical cutting to form a preset fin structure. However, when the preset mask pattern is formed by photolithography, due to the optical proximity effect, the ideal image spectrum is easily distorted to a certain extent, resulting in the preset right-angle area becoming a rounded area. In particular, when the fin structure is cut, the intersection of the horizontal cutting and the vertical cutting after the cutting is easily rounded, resulting in incomplete removal of the fin structure, thereby affecting the performance of the final formed FinFET device.
技术解决方案technical solutions
本发明的目的在于，提供一种FinFET器件及其形成方法和电子装置。An object of the present invention is to provide a FinFET device, a method for forming the same, and an electronic device.
本发明所采用的技术方案是：构造一种FinFET器件的形成方法，其特征在于，包括以下步骤：The technical solution adopted in the present invention is: constructing a method for forming a FinFET device, which is characterized in that it includes the following steps:
在半导体基板上形成多个鳍状物；forming a plurality of fins on a semiconductor substrate;
用保护膜覆盖所述多个鳍状物的表面；covering the surfaces of the plurality of fins with a protective film;
对所述多个鳍状物进行光刻处理，以在第一组鳍状物上形成第一蚀刻图案，所述第一组鳍状物包含待去除的第一鳍结构；performing a photolithography process on the plurality of fins to form a first etching pattern on a first group of fins, the first group of fins including the first fin structure to be removed;
通过所述第一蚀刻图案蚀刻第一组鳍状物和相应的保护膜,去除第一鳍结构并形成第一组预设鳍状物；Etching a first group of fins and a corresponding protective film through the first etching pattern, removing the first fin structure and forming a first group of preset fins;
各向同性蚀刻继续去除残留的第一鳍结构，并在对应第一组鳍状物的基板上形成凹结构。The isotropic etching continues to remove the remaining first fin structure, and a concave structure is formed on the substrate corresponding to the first group of fins.
在本发明提供的FinFET器件的形成方法中，还包括：In the method for forming a FinFET device provided by the present invention, it also includes:
在各向同性蚀刻过程后，移除所述第一组鳍状物上剩余的保护膜。After the isotropic etching process, the remaining protective film on the first set of fins is removed.
在本发明提供的FinFET器件的形成方法中，还包括：In the method for forming a FinFET device provided by the present invention, it also includes:
对所述多个鳍状物进行光刻处理，以在第二组鳍状物上形成第二蚀刻图案，所述第二组鳍状物包含待去除的第二鳍结构；performing a photolithography process on the plurality of fins to form a second etching pattern on a second group of fins, the second group of fins including the second fin structure to be removed;
通过所述第二蚀刻图案蚀刻第二组鳍状物，去除第二鳍结构并形成第二组预设鳍状物，同时在对应第二组鳍状物的基板上形成凸结构。The second group of fins is etched through the second etching pattern, the second fin structure is removed and a second group of preset fins is formed, and meanwhile, a convex structure is formed on the substrate corresponding to the second group of fins.
在本发明提供的FinFET器件的形成方法中，蚀刻第一组鳍状物的蚀刻方向与蚀刻第二组鳍状物的蚀刻方向彼此垂直。In the method for forming a FinFET device provided by the present invention, the etching direction for etching the first group of fins and the etching direction for etching the second group of fins are perpendicular to each other.
根据本发明的另一方面，还提供一种FinFET器件，包括：According to another aspect of the present invention, a FinFET device is also provided, comprising:
半导体基板；以及semiconductor substrates; and
在所述半导体基板上形成的多个鳍状物；a plurality of fins formed on the semiconductor substrate;
一个或多个凸结构和一个或多个凹结构，所述凸结构和所述凸结构分别对应于从所述半导体基板上移除的一组鳍状物。One or more convex structures and one or more concave structures, the convex structures and the convex structures respectively corresponding to a set of fins removed from the semiconductor substrate.
根据本发明的又一方面，还提供一种子装置，包括如上所述的FinFET器件。According to yet another aspect of the present invention, there is also provided a sub-device comprising the FinFET device as described above.
有益效果beneficial effect
本发明的FinFET器件及其形成方法和电子装置，具有以下有益效果：本发明提供的FinFET器件的形成方法，在进行蚀刻之前，利用保护膜覆盖鳍状物，然后对鳍状物进行光刻以在第一组鳍状物上形成第一蚀刻图案，所述第一组鳍状物包含待去除的第一鳍结构；之后利用第一蚀刻图案蚀刻第一组鳍状物和对应的保护膜；之后通过各向同性蚀刻去除残留的第一鳍结构，并在对应第一组鳍状物的基板上形成凹结构。因而避免了现有技术中蚀刻后留下的圆角问题；同时形成的凹结构有利于维持水平线，不会造成器件的弯曲。The FinFET device and the method for forming the same and the electronic device of the present invention have the following beneficial effects: in the method for forming the FinFET device provided by the present invention, before etching, a protective film is used to cover the fins, and then the fins are photoetched to forming a first etching pattern on the first group of fins, the first group of fins including the first fin structure to be removed; then etching the first group of fins and the corresponding protective film by using the first etching pattern; Then, the remaining first fin structures are removed by isotropic etching, and concave structures are formed on the substrate corresponding to the first group of fins. Therefore, the problem of rounded corners left after etching in the prior art is avoided; at the same time, the concave structure formed is beneficial to maintain the horizontal line and will not cause the bending of the device.
附图说明Description of drawings
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据提供的附图获得其他的附图：In order to explain the embodiments of the present invention or the technical solutions in the prior art more clearly, the following briefly introduces the accompanying drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only It is an embodiment of the present invention. For those of ordinary skill in the art, other drawings can also be obtained according to the provided drawings without creative work:
图1是本发明一实施例提供的SRAM的形成方法的流程图；1 is a flowchart of a method for forming an SRAM provided by an embodiment of the present invention;
图2-图11是根据本发明的FinFET器件的形成方法的各阶段俯视图和剖面示意图。2-11 are top views and schematic cross-sectional views of various stages of a method for forming a FinFET device according to the present invention.
本发明的实施方式Embodiments of the present invention
以下公开许多不同的实施方法或是例子来实行本发明实施例的不同特征，以下描述具体的元件及其排列的实施例以阐述本发明实施例。当然这些实施例仅用以例示，且不该以此限定本发明实施例的范围。例如，在说明书中提到第一特征形成于第二特征之上，其包括第一特征与第二特征是直接接触的实施例，另外也包括于第一特征与第二特征之间另外有其他特征的实施例，亦即，第一特征与第二特征并非直接接触。此外，在不同实施例中可能使用重复的标号或标示，这些重复仅为了简单清楚地叙述本发明实施例，不代表所讨论的不同实施例及/或结构之间有特定的关系。Many different implementation methods or examples are disclosed below to implement different features of the embodiments of the present invention, and embodiments of specific elements and their arrangements are described below to illustrate the embodiments of the present invention. Of course, these embodiments are only for illustration, and should not limit the scope of the embodiments of the present invention. For example, it is mentioned in the specification that the first feature is formed on the second feature, which includes embodiments in which the first feature and the second feature are in direct contact, and also includes other features between the first feature and the second feature. Embodiments of the features, that is, the first feature and the second feature are not in direct contact. In addition, repeated reference numerals or symbols may be used in different embodiments, and these repetitions are only for the purpose of simply and clearly describing the embodiments of the present invention, and do not represent a specific relationship between the different embodiments and/or structures discussed.
此外，其中可能用到与空间相关用词，例如“在……下方”、“下方”、“较低的”、“上方”、“较高的”及类似的用词，这些空间相关用词是为了便于描述图示中一个(些)元件或特征与另一个(些)元件或特征之间的关系，这些空间相关用词包括使用中或操作中的装置的不同方位，以及图式中所描述的方位。当装置被转向不同方位时(旋转90度或其他方位) ，则其中所使用的空间相关形容词也将依转向后的方位来解释。In addition, spatially relative terms such as "below", "below", "lower", "above", "higher" and similar terms may be used therein, which For convenience in describing the relationship between one element or feature(s) and another element or feature(s) in the figures, these spatially relative terms include different orientations of the device in use or operation, as well as the described orientation. When the device is turned in a different orientation (rotated 90 degrees or other orientations) , the spatially relative adjectives used therein will also be interpreted in terms of the turned orientation.
虽然所述的一些实施例中的步骤以特定顺序进行，这些步骤亦可以其他合逻辑的顺序进行。在不同实施例中，可替换或省略一些所述的步骤，亦可于本发明实施例所述的步骤之前、之中、及/或之后进行一些其他操作。本发明实施例中的半导体元件结构可加入其他的特征。在不同实施例中，可替换或省略一些特征。Although the steps in some of the described embodiments are performed in a particular order, the steps may also be performed in other logical orders. In different embodiments, some of the described steps may be replaced or omitted, and some other operations may also be performed before, during, and/or after the steps described in the embodiments of the present invention. Other features may be added to the semiconductor device structure in the embodiments of the present invention. In different embodiments, some features may be replaced or omitted.
本发明实施例提供一种FinFET器件的形成方法，在进行蚀刻之前，利用保护膜覆盖鳍状物，然后对鳍状物进行光刻以在第一组鳍状物上形成第一蚀刻图案，所述第一组鳍状物包含待去除的第一鳍结构；之后利用第一蚀刻图案蚀刻第一组鳍状物和对应的保护膜；之后通过各向同性蚀刻去除残留的第一鳍结构，并在对应第一组鳍状物的基板上形成凹结构。本发明在保护膜覆盖鳍结构的基础上，通过湿法刻蚀去除水平方向切割和垂直方向切割交汇的圆角化区域，避免鳍结构去除不完全的问题；同时通过形成低于基板水平线的凹结构，增加接触插塞与衬底之间的空间，降低了接触插塞抵接衬底的风险；而且，所述凹结构与形成高于基板水平线的凸结构，相互配合，提高器件结构的稳定，降低鳍结构倾斜或弯曲的风险。An embodiment of the present invention provides a method for forming a FinFET device. Before etching, a protective film is used to cover the fins, and then photolithography is performed on the fins to form a first etching pattern on the first group of fins, so that the The first group of fins includes the first fin structure to be removed; then the first group of fins and the corresponding protective film are etched by using a first etching pattern; then the remaining first fin structure is removed by isotropic etching, and A concave structure is formed on the substrate corresponding to the first group of fins. On the basis that the protective film covers the fin structure, the present invention removes the filleted area where the horizontal cutting and the vertical cutting intersect by wet etching, so as to avoid the problem of incomplete removal of the fin structure; The structure increases the space between the contact plug and the substrate, reducing the risk of the contact plug abutting the substrate; moreover, the concave structure and the convex structure formed higher than the horizontal line of the substrate cooperate with each other to improve the stability of the device structure , reducing the risk of tilting or bending of the fin structure.
图1所示为本发明一实施例提供的FinFET器件的形成方法10的流程图；图2-图10是根据发发明的FinFET器件的形成方法的各阶段的俯视图和剖面示意图。以下将图1的流程图搭配图2至图10的示意图说明本发明实施例。1 shows a flowchart of a method 10 for forming a FinFET device according to an embodiment of the present invention; FIGS. 2-10 are top views and schematic cross-sectional views of various stages of the method for forming a FinFET device according to the present invention. The following describes the embodiment of the present invention by combining the flowchart of FIG. 1 with the schematic diagrams of FIGS. 2 to 10 .
如图1及图2所绘示，方法10以步骤101开始，在半导体基板201上形成多个鳍状物202（202a-202f）；As shown in FIG. 1 and FIG. 2 , the method 10 begins with step 101 , forming a plurality of fins 202 ( 202 a - 202 f ) on the semiconductor substrate 201 ;
具体地，在一些实施例中，图2中的基板201可为半导体基板，其可包括元素半导体，例如硅(Si) 、锗(Ge)等；化合物半导体，例如氮化镓(GaN) 、碳化硅(SiC) 、砷化镓(GaAs) 、磷化镓(GaP)、磷化铟(InP)、砷化铟(InAs)、锑化铟(InSb)等；合金半导体，例如硅锗合金(SiGe)、磷砷镓合金(GaAsP)、砷铝铟合金(AlInAs)、砷铝镓合金(AlGaAs)、砷铟镓合金(GaInAs)、磷铟镓合金(GaInP)、磷砷铟镓合金(GaInAsP)、或上述材料的组合。Specifically, in some embodiments, the substrate 201 in FIG. 2 may be a semiconductor substrate, which may include elemental semiconductors, such as silicon (Si), germanium (Ge), etc.; compound semiconductors, such as gallium nitride (GaN), carbide, etc. Silicon (SiC), Gallium Arsenide (GaAs) , gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), indium antimonide (InSb), etc.; alloy semiconductors, such as silicon germanium alloy (SiGe), gallium arsenide phosphorous (GaAsP), arsenic Aluminum Indium Alloy (AlInAs), Aluminum Gallium Arsenide (AlGaAs), Gallium Indium Arsenide (GaInAs), Gallium Indium Phosphorus (GaInP), Gallium Indium Arsenide Phosphorus (GaInAsP), or a combination thereof.
具体地，在一些实施例中，鳍结构(包括多个鳍状物202a-202f)通过任何合适的工艺形成，例如，光刻工艺和蚀刻工艺。例如，在本实施方式中，鳍结构通过以下方式形成：在半导体基板上沉积混合抗蚀剂层；图形化抗蚀剂以在所述混合抗蚀剂层中形成间隙；执行蚀刻以形成所述鳍结构。Specifically, in some embodiments, the fin structure (including the plurality of fins 202a-202f) is formed by any suitable process, eg, a photolithography process and an etching process. For example, in this embodiment, the fin structure is formed by: depositing a mixed resist layer on a semiconductor substrate; patterning the resist to form gaps in the mixed resist layer; performing etching to form the Fin structure.
在一些实施方式中，鳍结构通过以下方式形成：将光刻胶层曝光在一图案下，进行曝光后烘烤工艺，以及显影光刻胶层以形成包括光刻胶层和掩模层的掩模元件。光刻胶层图案化可包括以下处理步骤：光刻胶涂布，软烘烤，掩模对准，曝光图案，曝光后烘烤，显影光刻胶剂，以及硬烘烤。在一些实施方式中，图案化还可由其他适当的方法实施或者替代，例如，无掩模光刻，电子束写入，离子束写入，以及分子烙印。然后，掩模元件(包括光刻胶层和掩模层) 可用在蚀刻工艺中以将鳍结构蚀刻入半导体基板201。蚀刻工艺使用图案化掩模层来限定被蚀刻的区域并且来保护CMOSFinFET 器件的其他区域。在一些实施方式中，蚀刻工艺为干法蚀刻工艺。在一实例中，用于蚀刻半导体基板201 的干法蚀刻工艺包括含卤素气体的化学物质。在又一实例中，干法蚀刻的化学物质包括Cl2，HBr，CF4，SF6，或者NF3等含有卤素的分子。可选地，鳍结构通过双重图案化光刻(DPL) 工艺形成。DPL 是一种通过将图案分成两个交错图案来在半导体基板上构造图案的方法。DPL允许提高部件(例如，鳍状件)密度。可使用的各种DPL 方法包括双重曝光( 例如，使用两个掩模组)。In some embodiments, the fin structure is formed by exposing the photoresist layer to a pattern, performing a post-exposure bake process, and developing the photoresist layer to form a mask including the photoresist layer and the mask layer module components. The photoresist layer patterning may include the following processing steps: photoresist coating, soft bake, mask alignment, exposure pattern, post exposure bake, developing photoresist, and hard bake. In some embodiments, patterning may also be performed or replaced by other suitable methods, such as maskless lithography, electron beam writing, ion beam writing, and molecular imprinting. The masking elements (including the photoresist layer and the masking layer) can then be used in an etching process to etch the fin structure into the semiconductor substrate 201 . The etch process uses a patterned mask layer to define the area to be etched and to protect other areas of the CMOSFinFET device. In some embodiments, the etching process is a dry etching process. In one example, the dry etching process used to etch the semiconductor substrate 201 includes a chemical species containing a halogen gas. In yet another example, the dry etch chemistry includes halogen-containing molecules such as Cl2, HBr, CF4, SF6, or NF3. Optionally, the fin structure is formed by a double patterned lithography (DPL) process. DPL is a method of structuring a pattern on a semiconductor substrate by dividing the pattern into two staggered patterns. DPL allows for increased component (eg, fin) density. Various DPLs available Methods include double exposure (eg, using two mask sets).
具体地，需要注意的是，形成多个鳍状物的方法仅仅是示例性的，并不局限于上述方法。Specifically, it should be noted that the method of forming the plurality of fins is merely exemplary, and is not limited to the above method.
如图1及图3所绘示，方法10接着进行步骤102，用保护膜203覆盖所述多个鳍状物202的表面。As shown in FIGS. 1 and 3 , the method 10 then proceeds to step 102 , covering the surfaces of the plurality of fins 202 with a protective film 203 .
具体地，在一些实施例中，保护膜203的构成材料可随着特定应用而变，因为其可由例如二氧化硅、氮化硅、氮氧化硅等各种材料所构成。此外，保护膜203可由多层材料所构成，例如包含二氧化硅层(例如：垫氧化物)、氮化硅层(例如：垫氮化物)及二氧化硅保护层的材料堆叠。Specifically, in some embodiments, the constituent material of the protective film 203 may vary with a particular application, as it may be composed of various materials such as silicon dioxide, silicon nitride, silicon oxynitride, and the like. In addition, the protective film 203 may be composed of multiple layers of materials, such as a material stack including a silicon dioxide layer (eg, pad oxide), a silicon nitride layer (eg, pad nitride), and a silicon dioxide protective layer.
如图1及图4和图5所绘示，方法10接着进行步骤103，对所述多个鳍状物202进行光刻处理，以在第一组鳍状物（例如，鳍状物202c和202d）上形成第一蚀刻图案204，所述第一组鳍状物包含待去除的第一鳍结构。As shown in FIGS. 1 and 4 and 5 , the method 10 then proceeds to step 103 of performing a photolithography process on the plurality of fins 202 so as to form the first set of fins (eg, the fins 202c and 202d) forming a first etching pattern 204 on the first set of fins including the first fin structure to be removed.
具体地，在一些实施例中，如图4所示，在保护膜203上方形成光致抗蚀层205，接着通过曝光、显影和纯水清洗而形成在第一组鳍状物形成第一蚀刻图案204。所述光致抗蚀层205可为多层不同材料制成的结构。Specifically, in some embodiments, as shown in FIG. 4 , a photoresist layer 205 is formed over the protective film 203 , and then a first etch is formed on the first group of fins by exposing, developing and cleaning with pure water. Pattern 204 . The photoresist layer 205 may be a structure made of multiple layers of different materials.
如图1及图6所绘示，方法10接着进行步骤104，通过所述第一蚀刻图案蚀刻第一组鳍状物和相应的保护膜，去除第一鳍结构并形成第一组预设鳍状物（210a和210b）之后移除光致抗蚀层205。如图5和图6所示，在利用第一蚀刻图案对鳍状物202c和202d进行蚀刻后，在切割交汇处留有第一鳍结构的残余部分206a和206b。As shown in FIG. 1 and FIG. 6 , the method 10 then proceeds to step 104 , etching a first group of fins and a corresponding protective film through the first etching pattern, removing the first fin structure and forming a first group of predetermined fins The photoresist layer 205 is removed after the shapes (210a and 210b). As shown in FIGS. 5 and 6 , after the fins 202c and 202d are etched using the first etch pattern, residual portions 206a and 206b of the first fin structure remain at the cut intersections.
具体地，在一些实施例中，蚀刻工艺可为干蚀刻工艺(例如反应离子刻蚀、非等向性等离子体刻蚀)；在一些实施例中，干刻蚀工艺可以含氧气体、含卤素气体(例如CF 4、SF 6、CH 2F 2、CHF 3、HBr、N 2及/或Cl 2)、其他适合的气体及/或等离子体、及/ 或上述的组合实施。 Specifically, in some embodiments, the etching process may be a dry etching process (eg reactive ion etching, anisotropic plasma etching); in some embodiments, the dry etching process may be oxygen-containing gas, halogen-containing Gases (eg, CF4, SF6 , CH2F2 , CHF3 , HBr , N2 , and/or Cl2 ) , other suitable gases and/or plasmas, and/or combinations of the above are implemented.
如图1及图7所绘示，方法10接着进行步骤105，各向同性蚀刻去除第一鳍结构的残余部分206a和206b，并在对应第一组鳍状物的基板上形成凹结构207a和207b。As shown in FIG. 1 and FIG. 7 , the method 10 then proceeds to step 105 , isotropic etching to remove the remaining portions 206 a and 206 b of the first fin structure, and forming concave structures 207 a and 206 b on the substrate corresponding to the first group of fins 207b.
具体地，在一些实施例中，在上述步骤104蚀刻第一组鳍状物之后，由于圆角问题，因此，第一鳍结构还残存有残余部分206a和206b，因此，通过各向同性蚀刻程序，去除残余部分206a和206b。在各向同性蚀刻工序中，移除第一组鳍状物（202c和202d）的剩余部分形成剖面形状为圆弧状的凹结构207a、207b。为实现各向同性的蚀刻，可以通过干法或湿法工艺进行各向同性蚀刻工序。在一干法工艺实施例中，通过控制诸如蚀刻时间和蚀刻气体等因素形成半导体器件的凹结构。但更优选地，采用湿法工艺，其残余部分206a和206b的去除效果更佳。在一实施例中，湿法工艺可以采用氨水、四甲基氢氧化铵TMAH等蚀刻剂。Specifically, in some embodiments, after the first group of fins is etched in the above step 104, due to the problem of rounded corners, the first fin structure still has residual portions 206a and 206b. Therefore, an isotropic etching process is performed. , the residual portions 206a and 206b are removed. In the isotropic etching process, the remaining parts of the first group of fins ( 202 c and 202 d ) are removed to form concave structures 207 a and 207 b with arc-shaped cross sections. In order to achieve isotropic etching, the isotropic etching process may be performed by a dry or wet process. In a dry process embodiment, the concave structure of the semiconductor device is formed by controlling factors such as etching time and etching gas. But more preferably, the wet process is adopted, and the removal effect of the residual parts 206a and 206b is better. In one embodiment, the wet process may use an etchant such as ammonia water, tetramethylammonium hydroxide, TMAH, or the like.
如图1及图8所绘示，方法10接着进行步骤106，在各向同性蚀刻过程后，移除所述第一组鳍状物上剩余的保护膜。As shown in FIGS. 1 and 8 , the method 10 proceeds to step 106 , after the isotropic etching process, the remaining protective film on the first set of fins is removed.
经过如上步骤101-106，完成了对第一组鳍状物（202c和202d）的处理，形成了第一组预设鳍状物和凹结构，在这里，第一组鳍状物包含了两个鳍状物（202c和202d），本领域技术人员可以理解的是，第一组鳍状物还可以包含其他数量的鳍状物，本发明对此并不做具体限定。如图2-8所示，在对第一组鳍状物进行处理时，进行的是水平方向的切割处理，本领域技术人员可以理解的是，也可以进行垂直方向的切割处理，本发明在此并不做限定。After the above steps 101-106, the processing of the first group of fins (202c and 202d) is completed, and a first group of preset fins and concave structures are formed. Here, the first group of fins includes two fins ( 202c and 202d ), those skilled in the art can understand that the first group of fins may also include other numbers of fins, which is not specifically limited in the present invention. As shown in Fig. 2-8, when the first group of fins is processed, the cutting process is performed in the horizontal direction. Those skilled in the art can understand that the cutting process in the vertical direction can also be performed. This is not limited.
接着，如图1及图9所绘示，方法10接着进行步骤107，对所述多个鳍状物进行光刻处理，以在第二组鳍状物（例如，鳍状物202e和202f）上形成第二蚀刻图案，所述第二组鳍状物包含待去除的第二鳍结构。Next, as shown in FIGS. 1 and 9 , the method 10 proceeds to step 107 , performing a photolithography process on the plurality of fins to form a second set of fins (eg, fins 202e and 202f ) A second etch pattern is formed thereon, the second set of fins including the second fin structure to be removed.
具体地，在一些实施例中，涂覆光致抗蚀层208，接着通过曝光、显影和纯水清洗而形成在第二组鳍状物形成第二蚀刻图案。Specifically, in some embodiments, a photoresist layer 208 is coated, followed by exposure, development, and pure water cleaning to form a second etch pattern on the second set of fins.
如图1及图10所绘示，方法10接着进行步骤108，通过所述第二蚀刻图案蚀刻第二组鳍状物，去除第二鳍结构并形成第二组预设鳍状物（211a和211b），同时在对应第二组鳍状物的基板上形成凸结构209a和209b。As shown in FIGS. 1 and 10 , the method 10 then proceeds to step 108 , etching a second set of fins through the second etching pattern, removing the second fin structure and forming a second set of predetermined fins (211a and 211b), while forming convex structures 209a and 209b on the substrate corresponding to the second group of fins.
具体地，在一些实施例中，蚀刻工艺可为干蚀刻工艺(例如反应离子刻蚀、非等向性等离子体刻蚀)。Specifically, in some embodiments, the etching process may be a dry etching process (eg, reactive ion etching, anisotropic plasma etching).
如图1及图11所绘示，方法10接着进行步骤109，剥离光致抗蚀层。As shown in FIGS. 1 and 11 , the method 10 then proceeds to step 109 of stripping the photoresist layer.
经过如上步骤107-109，完成了对与第一组鳍状物相邻的第二组鳍状物（202e和202f）的处理。如图9-11所示，在对第二组鳍状物进行处理时，进行的是垂直方向的切割处理，本领域技术人员可以理解的是，在对第一组鳍状物进行处理时采用的是水平切割，因此在对第二组鳍状物进行处理时就采用垂直切割；在其他实施例中，在对第一组鳍状物进行处理时采用垂直切割，而在对第二组鳍状物进行处理时就采用水平切割，本发明在此并不做限定。After steps 107-109 as above, the processing of the second group of fins (202e and 202f) adjacent to the first group of fins is completed. As shown in Figures 9-11, when the second group of fins is processed, the vertical cutting process is performed. Those skilled in the art can understand that when processing the first group of fins, the are horizontal cuts, so vertical cuts are used when processing the second group of fins; in other embodiments, vertical cuts are used when processing the first group of fins, and vertical cuts are used when processing the second group of fins Horizontal cutting is adopted when the object is processed, which is not limited in the present invention.
在一些实施例中，依照上述制备方法，在一器件结构中形成低于基板水平线的凹结构，所述器件结构中凹结构两侧分别设有鳍结构（本文未示处）。其后，在所述凹结构两侧的鳍结构上方形成接触插塞。由此，通过凹结构，增加接触插塞与衬底之间的空间，降低了接触插塞抵接衬底的风险。In some embodiments, according to the above-mentioned preparation method, a concave structure lower than the horizontal line of the substrate is formed in a device structure, and fin structures (not shown here) are respectively provided on both sides of the concave structure in the device structure. Thereafter, contact plugs are formed over the fin structures on both sides of the concave structure. Thus, through the concave structure, the space between the contact plug and the substrate is increased, and the risk of the contact plug abutting the substrate is reduced.
本发明还提供一种电子装置，其包括根据本发明示例性实施例的方法制造的FinFET器件。所述电子装置可以是手机、平板电脑、笔记本电脑、上网本、游戏机、电视机、VCD、DVD、导航仪、照相机、摄像机、录音笔、MP3、MP4、PSP 等任何电子产品或设备，也可以是任何包括所述FinFET器件的中间产品。所述电子装置，由于使用了所述FinFET器件，因而具有更好的性能。The present invention also provides an electronic device including a FinFET device fabricated according to the method of an exemplary embodiment of the present invention. The electronic device can be any electronic product or equipment such as mobile phone, tablet computer, notebook computer, netbook, game console, TV, VCD, DVD, navigator, camera, video recorder, voice recorder, MP3, MP4, PSP, etc. is any intermediate product that includes the FinFET device. The electronic device has better performance due to the use of the FinFET device.
本发明已经通过上述实施例进行了说明，但应当理解的是，上述实施例只是用于举例和说明的目的，而非意在将本发明限制于所描述的实施例范围内。此外本领域技术人员可以理解的是，本发明并不局限于上述实施例，根据本发明的教导还可以做出更多种的变型和修改，这些变型和修改均落在本发明所要求保护的范围以内。本发明的保护范围由附属的权利要求书及其等效范围所界定。The present invention has been described by the above-mentioned embodiments, but it should be understood that the above-mentioned embodiments are only for the purpose of illustration and description, and are not intended to limit the present invention to the scope of the described embodiments. In addition, those skilled in the art can understand that the present invention is not limited to the above-mentioned embodiments, and more variations and modifications can also be made according to the teachings of the present invention, and these variations and modifications all fall within the protection claimed in the present invention. within the range. The protection scope of the present invention is defined by the appended claims and their equivalents.

Claims (6)

  1. 一种FinFET器件的形成方法，其特征在于，包括以下步骤：A method for forming a FinFET device, comprising the following steps:
    在半导体基板上形成多个鳍状物；forming a plurality of fins on a semiconductor substrate;
    用保护膜覆盖所述多个鳍状物的表面；covering the surfaces of the plurality of fins with a protective film;
    对所述多个鳍状物进行光刻处理，以在第一组鳍状物上形成第一蚀刻图案，所述第一组鳍状物包含待去除的第一鳍结构；performing a photolithography process on the plurality of fins to form a first etching pattern on a first group of fins, the first group of fins including the first fin structure to be removed;
    通过所述第一蚀刻图案蚀刻第一组鳍状物和相应的保护膜,去除第一鳍结构并形成第一组预设鳍状物；Etching a first group of fins and a corresponding protective film through the first etching pattern, removing the first fin structure and forming a first group of preset fins;
    各向同性蚀刻继续去除残留的第一鳍结构，并在对应第一组鳍状物的基板上形成凹结构。The isotropic etching continues to remove the remaining first fin structure, and a concave structure is formed on the substrate corresponding to the first group of fins.
  2. 根据权利要求1所述的FinFET器件的形成方法，其特征在于，还包括：The method for forming a FinFET device according to claim 1, further comprising:
    在各向同性蚀刻过程后，移除所述第一组鳍状物上剩余的保护膜。After the isotropic etching process, the remaining protective film on the first set of fins is removed.
  3. 根据权利要求2所述的FinFET器件的形成方法，其特征在于，还包括：The method for forming a FinFET device according to claim 2, further comprising:
    对所述多个鳍状物进行光刻处理，以在第二组鳍状物上形成第二蚀刻图案，所述第二组鳍状物包含待去除的第二鳍结构；performing a photolithography process on the plurality of fins to form a second etching pattern on a second group of fins, the second group of fins including the second fin structure to be removed;
    通过所述第二蚀刻图案蚀刻第二组鳍状物，去除第二鳍结构并形成第二组预设鳍状物，同时在对应第二组鳍状物的基板上形成凸结构。The second group of fins is etched through the second etching pattern, the second fin structure is removed and a second group of preset fins is formed, and meanwhile, a convex structure is formed on the substrate corresponding to the second group of fins.
  4. 根据权利要求3所述的FinFET器件的形成方法，其特征在于，蚀刻第一组鳍状物的蚀刻方向与蚀刻第二组鳍状物的蚀刻方向彼此垂直。The method for forming a FinFET device according to claim 3, wherein the etching direction of the first group of fins and the etching direction of the second group of fins are perpendicular to each other.
  5. 一种FinFET器件，其特征在于，包括：A FinFET device, comprising:
    半导体基板；以及semiconductor substrates; and
    在所述半导体基板上形成的多个鳍状物；a plurality of fins formed on the semiconductor substrate;
    一个或多个凸结构和一个或多个凹结构，所述凸结构和所述凸结构分别对应于从所述半导体基板上移除的一组鳍状物。One or more convex structures and one or more concave structures, the convex structures and the convex structures respectively corresponding to a set of fins removed from the semiconductor substrate.
  6. 一种电子装置，其特征在于，包括权利要求5中任一项所述的FinFET器件。An electronic device, comprising the FinFET device according to any one of claims 5 .
PCT/CN2021/141851 2020-12-29 2021-12-28 Finfet device and forming method therefor, and electronic device WO2022143586A1 (en)

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