WO2022143434A1 - 一种存储设备和计算机设备 - Google Patents

一种存储设备和计算机设备 Download PDF

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Publication number
WO2022143434A1
WO2022143434A1 PCT/CN2021/141015 CN2021141015W WO2022143434A1 WO 2022143434 A1 WO2022143434 A1 WO 2022143434A1 CN 2021141015 W CN2021141015 W CN 2021141015W WO 2022143434 A1 WO2022143434 A1 WO 2022143434A1
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Prior art keywords
pcm
controller
storage device
main memory
data
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PCT/CN2021/141015
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English (en)
French (fr)
Inventor
朱晓明
景蔚亮
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华为技术有限公司
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Priority to EP21914171.0A priority Critical patent/EP4266183A1/en
Priority to KR1020237025763A priority patent/KR20230122154A/ko
Publication of WO2022143434A1 publication Critical patent/WO2022143434A1/zh
Priority to US18/342,252 priority patent/US20230342312A1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/005—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0004—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0035—Evaluating degradation, retention or wearout, e.g. by counting writing cycles
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/04—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding disturbances due to temperature effects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0026—PCI express
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/04—Supports for storage elements, e.g. memory modules; Mounting or fixing of storage elements on such supports

Definitions

  • the present application relates to the field of computer technology, and in particular, to a storage device and a computer device.
  • DRAM dynamic random access memory
  • SRAM and DRAM have low latency, the storage density of SRAM is very low, the area occupied in the storage device is too large, and the capacity is also very limited, and SRAM and DRAM are both volatile memories and need to be set to The electrical protection mechanism will greatly increase the cost.
  • the embodiments of the present application provide a storage device and a computer device, which can solve the problems of low cache capacity and high cost of the storage device.
  • the technical solution is as follows:
  • a storage device in a first aspect, includes a first PCM1 , a main memory 2 and a controller 3 .
  • the first PCM1 and the controller 3 are packaged in the same chip.
  • the time delay of the first PCM1 is smaller than that of the main memory 2, and the storage density of the main memory 2 is larger than that of the first PCM1.
  • the first PCM1 is the cache of the main memory 2 .
  • the controller 3 is used for storing the data in the first PCM1 and the main memory 2 based on the read/write temperature of the data.
  • the storage device can be a memory or solid state drive.
  • the first PCM 1 and the controller 3 may adopt a 2D package or a 3D package.
  • the first PCM 1 and the main memory 2 are respectively connected to the controller 3 through lines.
  • the first PCM1 and the controller 3 are connected by on-chip lines, and in the case of 3D packaging, are connected by vertical lines between Dies.
  • the main memory 2 and the controller 3 can be connected by a circuit on the PCB.
  • the PCB that provides the circuit connection can be the PCB inside the storage device, or the PCB of other devices or components outside the storage device, or, at the same time. Including the internal and external PCB of the storage device.
  • the main memory 2 and the controller 3 may not be connected by lines through the PCB, and the main memory 2, the first PCM1 and the controller 3 may also be packaged in the same chip, and the main memory 2 and the first PCM1 and the controller 3 may be encapsulated in the same chip.
  • 2D packaging can be used, or 3D packaging can be used.
  • the controller 3 may perform storage scheduling in the first PCM 1 and the main memory 2 based on the read/write heat of the data, the data to be stored and/or the stored data.
  • the read/write heat of the data of the first PCM1 is higher than the read/write heat of the data of the main memory 2 .
  • the low-latency PCM medium can achieve a high storage density while the latency is as low as 20ns, and can reach GB-level storage capacity, which can effectively trade off the latency. , area occupancy and amount of cached data. And it can keep data for several days after a power failure. In this way, for some enterprise-level application scenarios (devices will be powered on again after a short period of power failure), there is no need to set a power failure protection mechanism, which can reduce the storage device power consumption. manufacturing cost.
  • the controller 3 stores the data with higher read/write heat into the first PCM 1 , and stores the data with lower read/write heat into the main memory 2 .
  • the data frequently read and written by the CPU is the data with high read and write heat, and the data with low read and write heat is rarely read and written
  • the read and write heat of the data of the first PCM1 is higher than that of the first PCM1.
  • the read and write heat of the data in the main memory 2 so the delay reflected by the storage device is mainly the delay of the first PCM1, and the delay of the main memory 2 is basically not detected by the outside of the storage device. In this way, the advantages of high storage density and large capacity of the main memory 2 can be well utilized, and it can also be ensured that the problem of high delay of the main memory 2 will not have a great impact on the external delay of the entire storage device.
  • the first PCM1 and the controller 3 are packaged in 3D, and the first PCM1 and the controller 3 are in different Dies of the chip.
  • the 3D packaged chip may be composed of two or more Dies, the controller 3 may be set in one or more Dies, and the first PCM 1 may also be set in one or more Dies.
  • the controller 3 may be arranged on the upper side and the first PCM 1 on the lower side, or the first PCM 1 may be arranged on the upper side and the controller on the lower side, and so on.
  • the 3D packaging method is adopted, the PCM and the controller are located in different Dies, the PCM and the controller are overlapped, and the area will not be repeatedly occupied, which can reduce the area occupied, and the PCM and the controller are connected by vertical lines, and the vertical direction Compared with the horizontal line, the occupied area is much smaller, and it can basically be considered that it does not occupy the area, which further reduces the area occupied.
  • the controller 3 is configured to perform read and write operations on the first PCM1.
  • the controller 3 may include the operation circuit of the first PCM1, and the operation circuit may be an independent unit in the controller 3, or, the operation circuit may not be set as an independent unit, and the processing logic of the operation circuit of the first PCM1 integrated into the processing logic of the controller 3.
  • the PCM and the controller are connected at the chip level, and a large number of lines are connected, and the controller can directly perform read and write operations on the data in the storage medium of the PCM.
  • the PCM There is no need to set a conventional operation circuit inside, and further, in the process of data reading and writing, the protocol communication between the controller and the operation circuit is also omitted, and the data reading and writing of the PCM is not affected by the conventional controller and the operation circuit. Protocol restrictions, data read and write is more flexible and efficient.
  • the main memory 2 is the second PCM or NAND memory.
  • the second PCM may be a PCM with a high storage density, and may also be called a high-density PCM. Both the high-density PCM and the NAND memory have high storage density, so they can provide a large amount of storage in a limited space occupation.
  • the first PCM1 is a GB-level memory
  • the main memory 2 is a TB-level memory
  • the first PCM1 is a MB-level memory
  • the main memory 2 is a GB-level memory.
  • the storage levels of the first PCM1 and the main memory 2 can be flexibly set according to requirements, and here are just some possible examples.
  • the first PCM1 and the controller 3 are packaged in the CPU4.
  • the whole composed of the first PCM1 and the controller 2 may be a physically relatively independent unit in the CPU 4 .
  • the first PCM1 can also be used as a cache of the CPU4, such as an L4 cache, and the controller 2 can be a storage control unit of the CPU4.
  • the storage device further includes a PCB5 with a DDR interface 51, and the main memory 2 is arranged on the PCB5.
  • the product form of the main memory 2 can be designed in the form of a standard DIMM stick, so that it can be compatible with the DIMM slots of general motherboards, and the main memory 2 can be used as an independent memory stick.
  • the storage device further includes a PCB6, and the chip and the main memory 2 are arranged on the PCB6.
  • the storage device is a complete and integrated hardware module, and the chips encapsulated by the first PCM1 and the controller 3 and the main memory 2 are both connected on the same PCB.
  • the controller 3 and the main memory 2 are connected through a circuit on the PCB6 for communication, and the controller 3 and the first PCM1 are connected through an on-chip circuit for communication.
  • the product has better integrity.
  • the PCB 6 has a DDR interface 61 .
  • the product form of the entire memory is a DIMM strip, and the DDR interface 61 can be well compatible with standard DIMM slots.
  • the PCB 6 has a PCIe interface 62 .
  • the product form of the entire memory is a PCIe card, and the PCIe interface 62 can be well compatible with a standard PCIe slot.
  • the communication protocol between the controller 3 and the CPU 4 is the PCIe protocol or the CXL protocol.
  • the storage device and the CPU 4 can communicate through the PCIe protocol, and the storage device supports I/O semantic access, that is, supports block addressing.
  • the storage device and the CPU4 can also communicate through the CXL protocol, and the storage device supports both memory semantics and I/O semantic access, that is, supports both byte addressing and block addressing.
  • the communication protocol between the controller 3 and the CPU 4 is a proprietary protocol.
  • the storage device communicates with the CPU4 through a proprietary protocol, which has stronger data read and write flexibility.
  • the controller 3 supports a parallel bus communication standard, a serial bus communication standard or a custom bus communication standard.
  • the communication protocol between the controller 3 and the main memory 2 is an ONFI protocol, a toggle protocol or a proprietary protocol.
  • a computer device comprising the storage device as described in the first aspect and possible implementations thereof.
  • a low-latency PCM is used as a cache, and the low-latency PCM medium can achieve a high storage density while the latency is as low as 20ns, and can reach a large storage capacity of GB level. , and can retain data for several days after a power failure, without setting a power failure protection mechanism, thereby reducing costs.
  • the controller stores the data with high read/write heat in the PCM, and stores the data with low read/write heat in the main memory. In this way, the advantages of high storage density and large capacity of the main memory can be well used, and the main memory can be guaranteed. The problem of high latency will not have a great impact on the external latency of the entire storage device.
  • the 3D packaging method is adopted, the PCM and the controller are located in different Dies, the PCM and the controller will not occupy the area repeatedly, which can reduce the area occupation, and the PCM and the controller are connected by vertical lines, and the vertical lines are not It will occupy the area and further reduce the area occupied.
  • the PCM and the controller are packaged in the same chip.
  • the PCM and the controller are connected at the chip level, and a large number of lines can be connected.
  • the controller can directly read and write the data in the PCM. In this way, there is no need to set the internal PCM.
  • the conventional operation circuit correspondingly, the data reading and writing of the PCM is not restricted by the agreement between the conventional controller and the operation circuit, and the data reading and writing is more flexible and efficient.
  • FIG. 1 is a schematic structural diagram of a storage device provided by an embodiment of the present application.
  • FIG. 2 is a schematic structural diagram of a storage device provided by an embodiment of the present application.
  • FIG. 3 is a schematic structural diagram of a storage device provided by an embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of a storage device provided by an embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of a storage device provided by an embodiment of the present application.
  • FIG. 6 is a schematic diagram of the internal structure of a computer device provided by an embodiment of the present application.
  • FIG. 7 is a schematic diagram of an internal structure of a computer device provided by an embodiment of the present application.
  • FIG. 8 is a schematic diagram of an internal structure of a computer device provided by an embodiment of the present application.
  • the first PCM 2. Main memory
  • An embodiment of the present application provides a storage device, where the storage device is applied to a computer device, and the computer device may be a server or a terminal or the like.
  • the storage device may be an external device of the computer device, or may be a built-in component of the computer device.
  • the storage device may be a complete integrated device, or may be a device composed of multiple separate components.
  • the storage device can be an independent component that can be plugged and connected to the computer device, or can be a component that is integrally processed with other components of the computer device. From the product function point of view, the storage device can be used as a supplementary memory for conventional DRAM memory, as an independent memory, as a hard disk, or as a cache for a hard disk, and so on.
  • Phase change memory stores data by using the difference in conductivity exhibited by special materials when they transform between crystalline and amorphous states.
  • Phase change memory is usually an information storage device that utilizes the huge difference in conductivity between chalcogenides in crystalline and amorphous states to store data.
  • materials for the storage medium of PCM There are many kinds of materials for the storage medium of PCM, and the property parameters of various materials are different.
  • DRAM is a kind of semiconductor memory.
  • the main working principle is to use the relationship between the amount of stored charge in the capacitor and the threshold to represent a binary bit (bit), which takes a value of 1 or 0. Due to the phenomenon of leakage current in the transistor in reality, the amount of charge stored on the capacitor is not enough to correctly discriminate the data, resulting in data corruption. Therefore, for DRAM, periodic charging (also called refresh) is an unavoidable condition. Because of this feature that requires periodic refresh, it is called “dynamic" random access memory. Relatively speaking, as long as the data is stored in the static random access memory, the data will not be lost even if it is not refreshed.
  • SRAM is a type of random access memory.
  • the so-called “static” means that as long as the memory is kept powered on, the data stored in it can be kept constantly. Relatively speaking, the data stored in DRAM needs to be refreshed periodically. However, when the power supply stops, the data stored in the SRAM will still disappear, that is, both SRAM and DRAM are volatile memory (volatile memory), which is different from the read-only memory (read- only memory, ROM) or flash memory is different.
  • Dual in-line memory module refers to a series of modules composed of DRAM. DIMMs are usually in the form of several to dozens of DRAM chips welded and mounted on a printed circuit board that has already been fabricated, and are used in computer equipment such as personal computers, workstations, and servers. Computer equipment is generally provided with DIMM slots for connecting DIMM memory sticks.
  • Three-dimensional (3-dimension, 3D) packaging is a chip packaging technology. More than two bare die (Dies) are stacked in the vertical direction in the same chip, and each die is connected by a large number of vertical lines. data transmission. Each Die can be thought of as a layer of the chip. Relatively speaking, two-dimension (2D) package does not have multiple Dies stacked vertically. The 2D packaged chips are connected by horizontal lines. Compared with vertical lines, Lines in the horizontal direction waste more chip area.
  • High-speed serial computer expansion bus standard (peripheral component interconnect express, PCIe), is a high-speed serial computer expansion bus standard, used for data transmission between CPU and other components of computer equipment, replacing the traditional peripheral component interconnection standard (peripheral component interconnect, PCI), with higher transmission bandwidth and transmission rate.
  • PCIe peripheral component interconnect express
  • Double Data Rate (DDR) Joint Electron Device Engineering Council (JEDEC) standard is a parallel bus communication standard, which includes the physical specifications of the connection interface and related protocols for data transmission, etc. .
  • Read and write heat is quantitative information used to indicate the read and write frequency of data. The higher the read and write frequency of data, the higher the read and write heat, and the lower the data read and write frequency, the lower the read and write heat.
  • the specific quantification method can be arbitrarily set based on actual needs.
  • the read and write heat includes three values: hot, warm and cold. Hot, warm and cold are divided by the threshold of read and write frequency. If the reading and writing frequency is greater than the first frequency threshold, it is determined as hot data, if the reading and writing frequency of the data is less than the second frequency threshold, it is determined as cold data, and the reading and writing heat of the data is between the first frequency threshold and the second frequency. Between the thresholds, it is judged as warm data.
  • Latency is an attribute of the storage medium in the memory. It is the time required to read and write data to the storage medium. Generally, a storage medium with a low delay can reach several nanoseconds (ns), and a storage medium with a high delay can There are hundreds of ns or several milliseconds (ms), for example, the delay of DRAM is generally about 80 ns.
  • Storage density is an attribute of the storage medium in the memory. It can be considered as the number of storage units in a unit volume of storage medium.
  • a storage unit is a storage medium used to store 1bit data.
  • Storage density can also be considered as a unit volume of storage medium can store amount of data.
  • PCB also known as printed circuit board
  • PCB is an important electronic component, a support for electronic components, and a carrier for electrical connection of electronic components. Because it is made using electronic printing, it is called a "printed" circuit board. A large number of wires are printed on the PCB, which are used as connection lines for different electronic components.
  • a solid state disk is a hard disk made of an array of solid-state electronic memory chips.
  • An embodiment of the present application provides a storage device.
  • the structure of the storage device may be as follows:
  • the storage device includes a first PCM 1 , a main memory 2 and a controller 3 .
  • the first PCM1 and the controller 3 are packaged in the same chip.
  • the time delay of the first PCM1 is smaller than that of the main memory 2, and the storage density of the main memory 2 is larger than that of the first PCM1.
  • the storage medium of the first PCM1 has many materials to choose from, and a material with a lower delay can be selected, for example, the delay is about 20ns or less than 20ns.
  • the first PCM1 can also be called a low-latency PCM. Scandium (Sc)-antimony (Sb)-tellurium (Te) can be selected as the material of low-latency PCM.
  • the material delay of the PCM storage medium is within 20ns, and the storage density is generally lower. However, the first PCM1 can still reach the gigabyte (gigabyte, GB) level when it meets the 20ns delay and reasonable area size. Storage capacity. In actual use, the first PCM1 may be a GB-level memory or a megabyte (mbyte, MB) level memory.
  • the low-latency PCM medium can achieve a high storage density while the latency is as low as 20ns, and can reach GB-level storage capacity, which can effectively trade off the latency. , area occupancy and amount of cached data. And it can keep data for several days after a power failure. In this way, for some enterprise-level application scenarios (devices will be powered on again after a short period of power failure), there is no need to set a power failure protection mechanism, which can reduce the storage device power consumption. manufacturing cost.
  • the main memory 2 may be a second PCM, a NAND (not and, NAND) memory, etc., or may be a memory using other storage media with higher storage density.
  • the second PCM can be called a high-density PCM, and the material of the high-density PCM can be selected from germanium (Ge)-antimony-tellurium material.
  • the main memory 2 can reach a storage amount of terabyte (terabyte, TB) level. In actual use, the main memory 2 may be a TB-level memory or a GB-level memory.
  • the first PCM1 can be regarded as a buffer, the delay of the first PCM1 and the delay of the main memory 2 can satisfy a certain proportional relationship, and the delay of the first PCM1 and the storage capacity of the main memory 2 can satisfy a certain proportion. ratio.
  • the ratio between the time delay of the first PCM1 and the time delay of the main memory 2 may be in the range of 15-30, and the ratio between the time delay of the first PCM1 and the storage capacity of the main memory 2 may be 1/500 within the range of ⁇ 1/1000.
  • the controller 3 may be an independent controller for controlling the reading and writing of data in the storage device, and the control logic therein is only used for controlling the reading and writing of data in the first PCM1 and the main memory 2 .
  • the controller 3 can also be a comprehensive controller with more control functions, and the data read and write control of the storage device is only a part of the functions of the controller 3, and the control logic of various functions in the controller 3 is It is deployed uniformly and is not physically divided into different units.
  • the controller 3 may include the operation circuit of the first PCM1, and the operation circuit may be an independent unit in the controller 3, or, the operation circuit may not be set as an independent unit, and the processing logic of the operation circuit of the first PCM1 integrated into the processing logic of the controller 3.
  • the first PCM 1 and the controller 3 may adopt a 2D package or a 3D package, and the embodiments of the present application take the 3D package as an example to describe the solution in detail.
  • 3D packaging the first PCM1 and the controller 3 are in different Dies of the chip.
  • the 3D packaged chip may be composed of two or more Dies, the controller 3 may be set in one or more Dies, and the first PCM 1 may also be set in one or more Dies.
  • the controller 3 may be arranged on the upper side and the first PCM 1 on the lower side, or the first PCM 1 may be arranged on the upper side and the controller on the lower side, and so on.
  • the chip includes two Dies, one Die is the controller 3 and the other Die is the first PCM1, or the chip includes three Dies, the upper one is the controller 3, and the middle and lower two Dies are the first PCM1 PCM1, etc.
  • the first PCM 1 and the main memory 2 are respectively connected to the controller 3 through lines.
  • the first PCM1 and the controller 3 are connected by vertical lines between Dies within the same chip.
  • the main memory 2 and the controller 3 can be connected by a circuit on the PCB.
  • the PCB that provides the circuit connection can be the PCB inside the storage device, or the PCB of other devices or components outside the storage device, or, at the same time. Including the internal and external PCB of the storage device.
  • the main memory 2 and the controller 3 may not be connected by lines through the PCB, and the main memory 2, the first PCM1 and the controller 3 may also be packaged in the same chip, and the main memory 2 and the first PCM1 and the controller 3 may be encapsulated in the same chip. 2D packaging can be used, or 3D packaging can be used.
  • the main memory 2 and the packaged chip may be arranged on the same PCB, so that the storage device is an integral device, for example, the storage device may be an SSD disk, or the storage device may be a PCIe interface memory.
  • the chip and main memory 2 are arranged separately, so that the storage device is made into two separate sub-components.
  • the external connection forms of storage devices can be various, and can use parallel bus interfaces, serial bus interfaces, or custom bus interfaces, or, without using pluggable interfaces, when processing other devices, directly process the storage device. in other devices.
  • the 3D packaging method is adopted, the PCM and the controller are located in different Dies, the PCM and the controller are overlapped, and the area will not be repeatedly occupied, which can reduce the area occupied, and the PCM and the controller are connected by vertical lines, and the vertical direction Compared with the horizontal line, the occupied area is much smaller, and it can basically be considered that it does not occupy the area, which further reduces the area occupied.
  • the conventional PCM will be provided with an operating circuit, because the PCM and the controller are not connected at the chip level, and the number of connecting lines is small, so the controller cannot directly read and write the data in the PCM storage medium.
  • There is an operating circuit to help the PCM to read and write data that is, the operating circuit and the storage medium are encapsulated in the PCM, and they are connected to each other at the chip level.
  • the operating circuit can directly read and write data to the storage medium.
  • a corresponding protocol is set between the operating circuits, and they communicate with each other through the protocol to issue instructions and feedback results.
  • the protocol generally stipulates the unit data volume of data reading and writing.
  • the PCM and the controller are connected at the chip level, and a large number of lines are connected, and the controller can directly read and write the data in the storage medium of the PCM.
  • No conventional operation circuit is set up, and further, in the process of data reading and writing, the protocol communication between the controller and the operation circuit is also omitted, and the data reading and writing of the PCM is not subject to the agreement between the conventional controller and the operation circuit. Restrictions, data read and write is more flexible and efficient.
  • the controller 3 is configured to store data in the first PCM 1 and the main memory 2 based on the read/write temperature of the data.
  • the technician can set the corresponding read and write heat for the first PCM1 and the main memory 2 in advance.
  • the corresponding read and write heat can be set according to the delay of different memories, and the memory with lower delay can be set to store the data with higher read and write heat.
  • the delay of the first PCM1 is smaller than that of the main memory 2, so the first PCM1 is set to store data with a high read/write heat, and the main memory 2 is set to store data with a low read/write heat.
  • the read/write heat includes hot, warm, and cold.
  • the first PCM1 can be set to store hot data, and the main memory 2 can be set to store warm data and cold data, or the first PCM1 can be set to store hot data and warm data, and the main memory 2 can be set to store Cold data, etc.
  • the specific setting can be determined by comprehensively considering the ratio of hot data, warm data, and cold data of the application scenario and the storage capacity ratio of the first PCM 1 and the main memory 2 .
  • storage scheduling may be performed in the first PCM 1 and the main memory 2 based on the read/write heat of the data, the data to be stored and/or the stored data.
  • the controller 3 When the controller 3 receives the data to be stored from the CPU 4, it determines the data as hot data, and stores it in the first PCM1. For all the stored data, the controller 3 determines the read/write heat of the data as hot, warm, or cold based on the read/write frequency of the data in the current cycle time, and further, based on the read/write heat of the data , re-determine the storage of the data, and if the newly determined storage is different from the storage where the data is currently located, migrate the data to the newly determined storage. For example, if the data in the first PCM1 becomes cold data, it is migrated into the main memory 2, and if the cold data in the main memory 2 becomes hot data, it is migrated into the first PCM1.
  • the CPU 4 When the CPU 4 sends the data to be stored to the controller 3, it also sends the read and write heat corresponding to the data. After receiving the data and the corresponding read and write heat, the controller 3 determines that the memory corresponding to the data is the first memory based on the read and write heat. A PCM1 or main memory 2, which stores the data in the corresponding memory. For all the stored data, the controller 3 determines the read/write heat of the data as hot, warm, or cold based on the read/write frequency of the data in the current cycle time, and further, based on the read/write heat of the data , re-determine the storage of the data, and if the newly determined storage is different from the storage where the data is currently located, migrate the data to the newly determined storage.
  • the controller 3 When the controller 3 receives the data to be stored from the CPU4, it temporarily determines the read/write heat of the data, and stores it in a pre-designated memory (the first PCM1 or the main memory 2 can be designated). For all the stored data, the controller 3 determines the read/write heat of the data as hot, warm, or cold based on the read/write frequency of the data in the current cycle time, and further, based on the read/write heat of the data , re-determine the storage of the data, and if the newly determined storage is different from the storage where the data is currently located, migrate the data to the newly determined storage. In this way, the read/write temperature can be determined after a period of newly stored data, and then it can be stored in the first PCM 1 or migrated to the main memory 2 .
  • controller 3 is used to: when receiving the device to be shut down instruction, migrate the data in the first PCM1 to the main memory 2, and feed back a notification of completion after the migration; when the device is started, it will migrate to the data in the main memory 2 Migrate back to the first PCM1.
  • a corresponding wear leveling algorithm can also be set in the control logic of the controller 3, that is, when assigning addresses to the data to be stored in the first PCM1 or the main memory 2, address allocation is performed based on the principle of wear leveling, that is, select write The storage unit with the least number of entries is assigned its address to the data to be stored.
  • the controller 3 can support various bus communication standards, and communicate based on corresponding bus communication standards, such as parallel bus communication standards, serial bus communication standards, or custom bus communication standards.
  • various communication protocols can be used between the controller 3 and the main memory 2, such as an open NAND flash interface (ONFI) protocol, a toggle (a communication standard name) protocol or a proprietary protocol, etc. .
  • ONFI open NAND flash interface
  • toggle a communication standard name protocol or a proprietary protocol, etc.
  • the controller 3 stores the data with higher read/write heat into the first PCM 1 , and stores the data with lower read/write heat into the main memory 2 .
  • the external delay reflected by the storage device is mainly the first.
  • the delay of PCM1 and the delay of main memory 2 are basically not noticed by the outside of the storage device.
  • the first PCM1 and the main memory 2 can be fully utilized. of storage space. In this way, the advantages of high storage density and large capacity of the main memory 2 can be well utilized, and it can also ensure that the problem of high latency of the main memory 2 will not have a great impact on the external delay of the entire storage device, that is, it can play a role.
  • the first PCM1 has the advantage of low latency.
  • technicians can set the delay of the first PCM1, the delay of the main memory 2, the storage capacity of the first PCM1, the main memory of the first PCM1 based on the actual application scenario and the cost requirements 2, as well as the read and write heat corresponding to the first PCM1, and the read and write heat corresponding to the main memory 2.
  • the storage device is used as a memory in a server of an application, or the storage device is used as a memory in a user terminal, and so on.
  • the data volume and proportion of hot data, warm data, and cold data in the memory are generally relatively stable. Determine the data volume and proportion of hot data, warm data, and cold data in the memory under normal conditions. In addition, based on cost and business requirements, determine whether the warm data is stored in the first PCM1 or in the main memory 2, assuming that it is determined to store the warm data. In the first PCM1, that is to say, it is set to store hot data and warm data in the first PCM1, and store cold data in the main memory 2.
  • the storage capacity of the first PCM 1 may be determined based on the above-stated data volumes of the application hot data and warm data, and the storage volume of the main memory 2 may be determined based on the above-stated data volumes of the application cold data. If the application does not require very high memory delay, the first PCM1 can be made of materials with a delay of about 20ns.
  • the main memory 2 stores cold data, so the delay of the main memory 2 has no effect on the delay of the entire storage device.
  • the main memory 2 can be made of materials with a delay of 300-500ns.
  • a low-latency PCM is used as a cache, and the low-latency PCM medium can achieve a high storage density while the latency is as low as 20ns, and can reach a large storage capacity of GB level. , and can retain data for several days after a power failure, without setting a power failure protection mechanism, thereby reducing costs.
  • the controller stores the data with high read/write heat in the PCM, and stores the data with low read/write heat in the main memory. In this way, the advantages of high storage density and large capacity of the main memory can be well used, and the main memory can be guaranteed. The problem of high latency will not have a great impact on the external latency of the entire storage device.
  • the 3D packaging method is adopted, the PCM and the controller are located in different Dies, the PCM and the controller will not occupy the area repeatedly, which can reduce the area occupation, and the PCM and the controller are connected by vertical lines, and the vertical lines are not It will occupy the area and further reduce the area occupied.
  • a large number of lines can be connected between the PCM and the controller. In this way, there is no need to set a conventional operating circuit inside the PCM.
  • the controller can directly read and write the data in the PCM. The agreement between the controller and the operating circuit is limited, and the data read and write is more flexible and efficient.
  • An embodiment of the present application provides a storage device.
  • the structure of the storage device may be as follows:
  • the storage device includes a first PCM1, a main memory 2, a controller 3 and a PCB5.
  • the main memory 2 is the second PCM (the second PCM has a higher storage density and can be called a high-density PCM).
  • the first PCM1 and the controller 3 are packaged in the CPU4 by 3D packaging, and the first PCM1 and the controller 3 are in different Dies of the CPU4.
  • the PCB 5 has a DDR interface 51 .
  • the main memory 2 is provided on the PCB5.
  • the time delay of the first PCM1 is smaller than that of the second PCM, and the storage density of the second PCM is greater than that of the first PCM1.
  • the storage device is divided into two independent parts.
  • the first part includes the second PCM and the PCB5.
  • the second part includes the first PCM1 and the controller 2, which are packaged in the CPU4 by means of 3D packaging.
  • the second PCM is arranged on the PCB5, the PCB5 has a DDR interface 51, and the second PCM is connected to the DDR interface 51 through a line on the PCB5.
  • the second PCM and the controller 3 may be compatible with the DDR JEDEC standard.
  • the second PCM and the PCB5 form a standard DDR interface memory module.
  • the traditional memory module adopts DRAM particles
  • the memory module of the embodiment of the present application adopts PCM particles.
  • the memory stick can be inserted into the DIMM slot on the motherboard of the computer equipment. In this way, the second PCM can communicate with the controller 2 in the CPU 4 through the parallel bus.
  • the second PCM may include a storage medium and an operation circuit, the operation circuit can directly read and write data in the storage medium, the controller 3 communicates with the operation circuit through a corresponding protocol, and the operation circuit is carried out under the instruction of the controller 3 Corresponding read and write operations, and feedback the results to the controller 3.
  • this PCM memory module does not have to be used with the second part, that is, it does not have to be used with the CPU4 encapsulated with the first PCM1 and the controller 2. It can also be used with the CPU4.
  • the PCM memory module is equivalent to an ordinary memory module, but the memory particles use PCM particles.
  • the whole composed of the first PCM1 and the controller 2 may be a physically relatively independent unit in the CPU 4 .
  • the first PCM1, the second PCM and the controller 3 together form a memory
  • the controller 2 can work under the instruction of the memory control unit of the CPU4, manage the first PCM1 and the second PCM, and the second PCM
  • the PCM is the main memory in the memory and exists in the form of a memory stick.
  • the first PCM1 is a cache in the memory and is embedded in the CPU4. There is an on-chip connection line between the memory control unit of the CPU 4 and the controller 2, and communication can be performed through the on-chip connection line.
  • the memory control unit can send the data to be stored or the data read address to the controller 2 inside the CPU4, and the controller 2 sends the read data or response message to the memory control unit inside the CPU4. In this way, the time delay of the communication between the memory control unit and the controller 2 can be greatly reduced, and the transmission efficiency can be improved.
  • the first PCM1 can also be used as a cache of the CPU4, such as a level 4 (L4) cache, and the controller 2 can be a storage control unit of the CPU4.
  • L4 level 4
  • each level of cache has an independent cache control unit, and there is also a memory control unit in the CPU4.
  • the combination of the memory control unit and the cache control unit corresponding to the first PCM1 can be called the controller 2. , they are responsible for the control of the first PCM1 and the second PCM respectively.
  • the storage device can completely replace the standard DRAM memory stick. Compared with general DRAM memory sticks, the storage device has a low-latency cache, and the cache has a large storage capacity. The entire storage device adopts non-volatile memory, which has a good ability to prevent power failure.
  • the controller stores data with high read/write heat into low-latency PCM, and stores data with low read/write heat into high-density PCM.
  • the controller and other units in the CPU use on-chip communication, and the low-latency PCM and the controller also use on-chip communication, which can effectively reduce the latency of reading and writing data to the low-latency PCM, that is, The latency of reading and writing data of the entire storage device can be effectively reduced.
  • the 3D packaging method is adopted, the PCM and the controller are located in different Dies, the PCM and the controller will not occupy the area repeatedly, which can reduce the area occupation, and the PCM and the controller are connected by vertical lines, and the vertical lines are not It will occupy the chip area, further reducing the area occupation.
  • the 3D packaging method there is a chip-level connection between the PCM and the controller, and a large number of lines can be connected, so the controller can directly read and write the data in the PCM. In this way, there is no need to set a conventional operating circuit inside the PCM.
  • the data reading and writing of the PCM is not limited by the agreement between the conventional controller and the operating circuit, and the data reading and writing is more flexible and efficient.
  • high-density PCM is used as the main memory.
  • NAND memory can also be used as the main memory.
  • the characteristics of the NAND memory are relatively close to those of the high-density PCM, and the embodiments of this application do not describe in detail.
  • the communication protocol between the controller 3 and the CPU 4 can be a general protocol or a proprietary protocol.
  • An embodiment of the present application provides a storage device, and the structure of the storage device may be as follows:
  • the storage device includes a first PCM1, a main memory 2, a controller 3 and a PCB6.
  • the main memory 2 is the second PCM.
  • the first PCM1 and the controller 3 are packaged in the same chip by 3D packaging, and the first PCM1 and the controller 3 are in different Dies of the chip. Both the 3D packaged chip and the second PCM are arranged on the PCB6.
  • PCB6 has serial bus interface or custom bus interface.
  • the time delay of the first PCM1 is smaller than that of the second PCM, and the storage density of the second PCM is greater than that of the first PCM1.
  • the storage device is a complete and integrated hardware module, and the chips packaged by the first PCM1 and the controller 3 and the second PCM are both connected on the same PCB.
  • the controller 3 and the second PCM are connected through a circuit on the PCB for communication, and the controller 3 and the first PCM1 are connected through a vertical circuit in the chip for communication.
  • the second PCM may include a storage medium and an operation circuit, the operation circuit can directly read and write data in the storage medium, the controller 3 communicates with the operation circuit through a corresponding protocol, and the operation circuit is carried out under the instruction of the controller 3 Corresponding read and write operations, and feedback the results to the controller 3.
  • a DDR interface 61 is provided on the PCB 6 .
  • the controller 3 supports a serial bus communication standard or a custom bus communication standard, and the storage device can communicate with the CPU 4 based on the serial bus communication standard or the custom bus communication standard.
  • the hardware module of the entire storage device is a DIMM strip, which is different from ordinary DIMM strips in that ordinary DIMM strips use DRAM particles and use parallel bus communication standards, while this storage device uses high-density PCM particles and uses serial Bus communication standard or custom bus communication standard.
  • This solution can customize the design of the CPU4, so that the CPU4 and the DIMM can communicate through the serial bus communication standard or the custom bus communication standard, and enable the CPU4 to support the serial bus or the custom bus through the memory. Semantics or custom semantics to access the DIMM strip.
  • the storage device using this module form can use the DIMM slot on the standard motherboard, which can be well compatible with the existing motherboard.
  • This storage device can be used as a supplemental memory to RAM or DRAM memory.
  • a PCIe interface 62 is provided on the PCB 6 .
  • the controller 3 supports a serial bus communication standard or a custom bus communication standard, and the storage device communicates with the CPU 4 based on the serial bus communication standard or the custom bus communication standard.
  • the hardware module of the entire storage device is a PCIe disk.
  • PCIe disks have many different forms. Figure 4 and Figure 5 show two specific forms respectively. The difference from ordinary PCIe disks is that ordinary PCIe disks use DRAM to store the address mapping table and use NAND particles, while this storage device can use low-latency PCM to store the address mapping table and high-density PCM particles. as main memory.
  • the storage device and the CPU 4 can communicate through the PCIe protocol, and the storage device supports input/output (input/output, I/O) semantic access, that is, supports block addressing. In this way, the storage device can be used as a solid state drive.
  • the storage device and CPU4 can also communicate through the compute express link (CXL) protocol, and the storage device supports both memory semantics and I/O semantic access, that is, byte addressing and block addressing. In this way, the storage device can be used as a solid state drive or as a supplementary memory.
  • CXL compute express link
  • the storage device can display low latency to the outside world through the use of low-latency PCM and the mechanism of controller 3 to store and schedule data based on read and write heat.
  • the average access Latency is reduced to 1 microsecond ( ⁇ s).
  • the storage device has a high storage density, which can reach TB-level storage capacity, and the corresponding control logic can be set in the system program or application program.
  • the storage scheduling can be considered as the first-level scheduling, and the storage scheduling controlled by the controller 3 inside the storage device can be considered as the second-level scheduling. Stores data with low read/write heat. In this way, although the inherent latency of the PCIe interface is high, the above solution can ensure that the external latency of the overall memory composed of memory and supplementary memory is not affected by the inherent latency of the PCIe interface.
  • high-density PCM is used as the main memory.
  • NAND memory can also be used as the main memory.
  • the characteristics of the NAND memory are relatively close to those of the high-density PCM, and the embodiments of this application do not describe in detail.
  • the communication protocol between the controller 3 and the CPU 4 may adopt a private protocol in addition to a general protocol.
  • An embodiment of the present application further provides a computer device, where the computer device includes the storage device in the foregoing embodiments.
  • the computer equipment After the computer equipment is equipped with the storage device, it can be equipped with DRAM or not.
  • Figure 6 shows the case where the computer device is not equipped with DRAM, where the storage device can act as memory.
  • FIG. 7 shows a situation in which a computer device is equipped with DRAM, wherein the DRAM is used as memory, and the storage device can be used as a supplementary memory, or can also be used as an SSD.
  • FIG 8 shows the situation that the computer equipment is equipped with DRAM, SSD and the above-mentioned storage devices at the same time, wherein DRAM is used as memory, and the storage device can supplement the memory, can also be used as SSD together with the original SSD, and can also be used as the cache of the original SSD disk use.

Abstract

本申请实施例公开了一种存储设备和计算机设备，属于计算机技术领域。所述存储设备包括第一PCM1、主存储器2和控制器3，其中：所述第一PCM1和所述控制器3封装在同一芯片中；所述第一PCM1的时延小于所述主存储器2，所述主存储器2的存储密度大于所述第一PCM1；所述控制器3，用于基于数据的读写热度，将数据存储在所述第一PCM1和所述主存储器2中，其中，所述第一PCM1为所述主存储器2的缓存。采用本申请实施例，可以提高存储设备缓存容量并减小设备成本。

Description

一种存储设备和计算机设备 技术领域
本申请涉及计算机技术领域，特别涉及一种存储设备和计算机设备。
背景技术
随着计算机技术的发展，中央处理器(central processing unit，CPU)的处理能力呈现持续不断快速增长的趋势。然而，动态随机存取存储器(dynamic random access memory，DRAM)作为内存受物理特性和工艺的限制，已经无法满足CPU的需求。许多针对DRAM的补充存储方案应运而生。
这些补充存储方案，一般都采用大容量的主存储器，配合静态随机存储器(static random access memory，SRAM)或DRAM缓存使用。
在实现本申请的过程中，发明人发现相关技术至少存在以下问题：
SRAM和DRAM虽然具有较低的时延，但是，SRAM的存储密度很低，在存储设备中占用的面积过大的同时容量也非常有限，且SRAM和DRAM都属于易失性存储器，需要设置掉电保护机制，会大大增加成本。
发明内容
本申请实施例提供了一种存储设备和计算机设备，可以解决存储设备缓存容量低、成本高的问题。所述技术方案如下：
第一方面，提供了一种存储设备，该存储设备包括第一PCM1、主存储器2和控制器3。第一PCM1和控制器3封装在同一芯片中。第一PCM1的时延小于主存储器2，主存储器2的存储密度大于第一PCM1。第一PCM1为主存储器2的缓存。控制器3，用于基于数据的读写热度，将数据存储在第一PCM1和主存储器2中。
存储设备可以为内存或固态硬盘。第一PCM1和控制器3可以采用2D封装或者3D封装。
第一PCM1和主存储器2分别与控制器3通过线路连接。第一PCM1和控制器3通过片内的线路连接，3D封装的情况，通过Die之间的垂直线路连接。主存储器2和控制器3之间可以通过PCB上的线路连接，此提供线路连接的PCB可以是存储设备内部的PCB，也可以是存储设备外的其他设备或部件的PCB，或者，也可以同时包括存储设备内部和外部的PCB。主存储器2和控制器3之间也可以不通过PCB进行线路连接，可以也将主存储器2与第一PCM1、控制器3封装在同一芯片中，主存储器2与第一PCM1、控制器3之间可以采用2D封装的方式，也可以采用3D封装的方式。
控制器3可以基于数据的读写热度，对待存储的数据和/或已存储的数据，在第一PCM1和主存储器2中进行存储调度。第一PCM1的数据的读写热度高于主存储器2的数据的读写热度。
采用较低时延的PCM作为缓存，低时延的PCM介质可以做到在时延低至20ns的同时，仍然具有较高的存储密度，可以达到GB级的存储量，能够有效的权衡时延、面积占用和缓存数据量。而且在断电后能够保持数据几天，这样，对于一些企业级的应用场景(设备掉电 后短时间内就会重新上电)，完全无需设置掉电保护机制，可以很好的降低存储设备的制造成本。
在上述控制器3的控制逻辑中，控制器3将读写热度较高的数据存入第一PCM1，将读写热度较低的数据存入主存储器2。这样，因为CPU频繁读写的数据是那些读写热度较高的数据，而很少会对那些读写热度较低的数据进行读写操作，而且，第一PCM1的数据的读写热度高于主存储器2的数据的读写热度，所以存储设备对外反映出来的时延主要是第一PCM1的时延，主存储器2的时延基本不会被存储设备外部所察觉。这样，既能够很好的发挥主存储器2存储密度高容量大的优点，又可以保证主存储器2时延较高的问题不会对整个存储设备对外的时延产生太大的影响。
在一种可能的实现方式中，第一PCM1和控制器3采用3D封装，第一PCM1和控制器3在芯片的不同Die中。
3D封装的芯片，可以由两个或两个以上的Die组成，控制器3可以设置在一个或多个Die中，第一PCM1也可以设置在一个或多个Die中。可以将控制器3设置在上、第一PCM1设置在下，或者将第一PCM1设置在上、控制器设置在下，等等。
采用3D封装方式，PCM和控制器位于不同的Die中，PCM和控制器重叠放置，不会重复占用面积，可以减小面积占用，而且PCM和控制器之间通过垂直方向的线路连接，垂直方向的线路相对于水平方向的线路来说，占用面积少很多，基本可以认为不占用面积，进一步减小了面积占用。
在一种可能的实现方式中，控制器3用于对第一PCM1进行读写操作。
控制器3中可以包括第一PCM1的操作电路，操作电路在控制器3中可以为独立的单元，或者，也可以不将操作电路设置为独立的单元，将第一PCM1的操作电路的处理逻辑融入到控制器3的处理逻辑中。
本申请实施例中，通过封装成芯片的方式，PCM和控制器之间是芯片级连接，连接有大量的线路，控制器可以直接对PCM的存储介质中的数据进行读写操作，这样，PCM内部可以不设置常规的操作电路，进而，在数据读写过程中，也省去了控制器与操作电路之间的协议通信，对PCM的数据读写不受常规的控制器与操作电路之间的协议限制，数据读写更加灵活高效。
在一种可能的实现方式中，主存储器2为第二PCM或NAND存储器。
第二PCM可以是具有高存储密度的PCM，也可称作高密度PCM，高密度PCM和NAND存储器都具有较高的存储密度，所以可以在有限的空间占用下提供很大的存储量。
在一种可能的实现方式中，第一PCM1为GB级存储器，主存储器2为TB级存储器，或者，第一PCM1为MB级存储器，主存储器2为GB级存储器。第一PCM1和主存储器2的存储级别可以根据需求灵活设置，这里也只是举出了一些可能的例子。
在一种可能的实现方式中，第一PCM1和控制器3封装在CPU4中。
第一PCM1和控制器2组成的整体在CPU4中可以是一个在物理上相对独立的单元。或者，第一PCM1也可以作为CPU4的缓存，如L4缓存，控制器2可以是CPU4的存储控制单元。
控制器3与CPU4的其他单元之间存在片内连接线路，可以通过片内连接线路进行通信。属于芯片级连接，可以大大减小控制器3与CPU4的其他单元之间通信的时延，可以提高存储设备的传输效率。
在一种可能的实现方式中，存储设备还包括具有DDR接口51的PCB5，主存储器2设置 在PCB5上。
主存储器2的产品形式可以设计成标准的DIMM条形式，这样，可以兼容一般主板的DIMM插槽，而且主存储器2可以作为独立的内存条使用。
在一种可能的实现方式中，存储设备还包括PCB6，芯片和主存储器2设置在PCB6上。
该结构中，存储设备是一个完整一体的硬件模组，第一PCM1和控制器3封装的芯片与主存储器2都连接在同一PCB上。控制器3和主存储器2通过PCB6上的线路相连接，以进行通信，控制器3与第一PCM1通过片内的线路连接，以进行通信。这种结构，产品具有更好的完整性。
在一种可能的实现方式中，PCB6具有DDR接口61。
这样，整个存储器的产品形态为一个DIMM条，采用DDR接口61可以很好的兼容标准的DIMM插槽。
在一种可能的实现方式中，PCB6具有PCIe接口62。
这样，整个存储器的产品形态为一个PCIe卡，采用PCIe接口62可以很好的兼容标准的PCIe插槽。
在一种可能的实现方式中，控制器3与CPU4的通信协议为PCIe协议或CXL协议。
存储设备与CPU4之间可以通过PCIe协议通信，存储设备支持I/O语义访问，即支持块寻址。存储设备与CPU4之间也可以通过CXL协议通信，存储设备同时支持内存语义和I/O语义访问，即同时支持字节寻址和块寻址。
在一种可能的实现方式中，控制器3与CPU4的通信协议为私有协议。
存储设备与CPU4之间通过私有协议通信，具有更强的数据读写灵活性。
在一种可能的实现方式中，控制器3支持并行总线通信标准、串行总线通信标准或自定义总线通信标准。
在一种可能的实现方式中，控制器3与主存储器2的通信协议为ONFI协议、toggle协议或私有协议。
第二方面，提供了一种计算机设备，该计算机设备包括如第一方面及其可能的实现方式所述的存储设备。
本申请实施例提供的技术方案带来的有益效果是：
本申请实施例中，采用较低时延的PCM作为缓存，低时延的PCM介质可以做到在时延低至20ns的同时，仍然具有较高的存储密度，可以达到GB级的大存储量，而且在断电后能够保持数据几天，无需设置掉电保护机制，从而降低成本。控制器将读写热度较高的数据存入PCM，将读写热度较低的数据存入主存储器，这样，既能够很好的利用主存储器存储密度高容量大的优点，又可以保证主存储器时延较高的问题不会对整个存储设备对外的时延产生太大的影响。采用3D封装方式，PCM和控制器位于不同的Die中，PCM和控制器不会重复占用面积，可以减小面积占用，而且PCM和控制器之间通过垂直方向的线路连接，垂直方向的线路不会占用面积，进一步减小了面积占用。另外，将PCM和控制器封装在同一芯片中，PCM和控制器之间是芯片级连接，可以连接大量的线路，控制器可以直接对PCM中的数据进行读写操作，这样，PCM内部无需设置常规的操作电路，相应的，对PCM的数据读写不受常规的控制器与操作电路之间的协议限制，数据读写更加灵活高效。
附图说明
图1是本申请实施例提供的一种存储设备的结构示意图；
图2是本申请实施例提供的一种存储设备的结构示意图；
图3是本申请实施例提供的一种存储设备的结构示意图；
图4是本申请实施例提供的一种存储设备的结构示意图；
图5是本申请实施例提供的一种存储设备的结构示意图；
图6是本申请实施例提供的一种计算机设备的内部结构示意图；
图7是本申请实施例提供的一种计算机设备的内部结构示意图；
图8是本申请实施例提供的一种计算机设备的内部结构示意图。
图例说明
1、第一PCM              2、主存储器
3、控制器               4、CPU
5、PCB                  51、DDR接口
6、PCB                  61、DDR接口
62、PCIe接口
具体实施方式
本申请实施例提供了一种存储设备，该存储设备应用于计算机设备中，该计算机设备可以是服务器或终端等。该存储设备可以是计算机设备的外置设备，也可以是计算机设备的内置部件。该存储设备可以是一个完整的一体设备，也可以是由多个分离部件组成的设备。该存储设备可以是一个独立的可与计算机设备插拔连接的部件，也可以是与计算机设备的其它部件一体加工的部件。从产品功能角度来说，该存储设备可以作为常规的DRAM内存的补充内存，也可以作为独立使用的内存，还可以作为硬盘，或者作为硬盘的缓存，等等。
下面首先对本申请涉及的一些技术术语进行解释。
相变存储器(phase change memory，PCM)，是利用特殊材料在晶态和非晶态之间相互转化时所表现出来的导电性差异来存储数据的。相变存储器通常是利用硫族化合物在晶态和非晶态巨大的导电性差异来存储数据的一种信息存储装置。PCM的存储介质的材料有很多种，各种材料的属性参数各不相同。
DRAM，是一种半导体存储器，主要的工作原理是利用电容内存储电荷的数量于阈值的大小关系代表一个二进制比特(bit)，取值为1或0。由于在现实中晶体管会有漏电电流的现象，导致电容上所存储的电荷数量并不足以正确的进行数据判别，而导致数据毁损。因此对于DRAM来说，周期性地充电(也可称刷新)是一个不可避免的条件。由于这种需要定时刷新的特性，因此被称为“动态”随机存储器。相对来说，静态随机存储器只要存入数据，纵使不刷新也不会丢失数据。
SRAM，是随机存取存储器的一种。所谓的“静态”，是指这种存储器只要保持通电，里面储存的数据就可以恒常保持。相对来说，DRAM里面所储存的数据就需要周期性地刷新。然而，当电力供应停止时，SRAM储存的数据还是会消失，也即，SRAM和DRAM均为易失性存储器(volatile memory)，这与在断电后还能储存资料的只读存储器(read-only memory，ROM) 或闪存是不同的。
双线存储器模块(dual in-line memory module，DIMM)，是指一系列由DRAM组成的模块。DIMM通常是数颗至数十颗DRAM芯片焊接安装于一块已制作好电路的印刷电路板的形式，用于个人电脑、工作站、服务器等计算机设备。计算机设备上一般设置有DIMM插槽，用于连接DIMM内存条。
三维(three dimension，3D)封装，是一种芯片封装技术，在同一个芯片内于垂直方向叠放两个以上的裸晶(Die)，各个Die之间通过大量的垂直方向的线路连接，进行数据传输。每个Die可以认为是芯片的一层。相对来说，二维(two dimension，2D)封装就不存在垂直叠放的多个Die，2D封装而成的芯片，多个部分之间通过水平方向的线路连接，相对于垂直方向的线路，水平方向的线路会浪费更多的芯片面积。
高速串行计算机扩展总线标准(peripheral component interconnect express，PCIe),是一种高速串行计算机扩展总线标准，用于CPU与计算机设备的其他部件进行数据传输，替代了传统的外设部件互连标准(peripheral component interconnect，PCI)，具有更高的传输带宽和传输速率。
双倍数据速率(double data rate，DDR)电子工程设计发展联合协会(joint electron device engineering council，JEDEC)标准，是并行总线通信标准，该标准中包括连接接口的物理规格和数据传输的相关协议等。
读写热度，是用于表示数据的读写频度的量化信息，数据的读写频度越高则读写热度越高，数据的读写频度越低则读写热度越低。具体的量化方式可以基于实际需求任意设置，例如，一种常用的量化方式，读写热度包括热、温、冷三种数值，热、温、冷通过读写频度的阈值来划分，数据的读写频度大于第一频度阈值则判定为热数据，数据的读写频度小于第二频度阈值则判定为冷数据，数据的读写热度在第一频度阈值和第二频度阈值之间则判定为温数据。
时延，是存储器中存储介质的属性，是对存储介质进行一次数据读写所需的时长，一般时延较低的存储介质可以达到几纳秒(ns)，时延较高的存储介质可以有几百ns或者几毫秒(ms)，例如，DRAM的时延一般为80ns左右。
存储密度，是存储器中存储介质的属性，可以认为是单位体积的存储介质中存储单元的数量，存储单元是用于存储1bit数据的存储介质，存储密度也可以认为是单位体积的存储介质能够存储的数据量。
印制电路板(printed circuit board，PCB)，又称印刷线路板，是重要的电子部件，是电子元器件的支撑体，是电子元器件电气连接的载体。由于它是采用电子印刷术制作的，故被称为“印刷”电路板。PCB上印制有大量的导线，用作不同电子元器件的连接线路。
固态硬盘(solid state disk，SSD)，是用固态电子存储芯片阵列制成的硬盘。
本申请实施例提供了一种存储设备，参见图1，存储设备的结构可以如下：
存储设备包括第一PCM1、主存储器2和控制器3。第一PCM1和控制器3封装在同一芯片中。其中，第一PCM1的时延小于主存储器2，主存储器2的存储密度大于第一PCM1。
下面介绍一下存储设备中的各部件。
第一PCM1，其存储介质有很多可供选择的材料，可以选用时延较低的材料，如时延在20ns左右或低于20ns，相应的，第一PCM1也可以称作低时延PCM。低时延PCM的材料可以 选用钪(Sc)-锑(Sb)-碲(Te)材料。PCM存储介质选用的材料时延在20ns以内，一般存储密度会偏低一些，不过，第一PCM1在满足20ns时延和合理面积大小的情况下依然可以达到吉字节(gigabyte，GB)级的存储量。在实际使用中，第一PCM1可以是GB级存储器也可以是兆字节(mbyte，MB)级存储器。
采用较低时延的PCM作为缓存，低时延的PCM介质可以做到在时延低至20ns的同时，仍然具有较高的存储密度，可以达到GB级的存储量，能够有效的权衡时延、面积占用和缓存数据量。而且在断电后能够保持数据几天，这样，对于一些企业级的应用场景(设备掉电后短时间内就会重新上电)，完全无需设置掉电保护机制，可以很好的降低存储设备的制造成本。
主存储器2，可以是第二PCM、与非(not and，NAND)存储器等，或者可以是采用其他具有较高存储密度的存储介质的存储器。第二PCM可称作高密度PCM，高密度PCM的材料可以选用锗(Ge)-锑-碲材料。主存储器2可以达到太字节(terabyte，TB)级的存储量。在实际使用中，主存储器2可以是TB级存储器也可以是GB级存储器。
第一PCM1可以认为是缓存器，第一PCM1的时延与主存储器2的时延之间可以满足一定的比例关系，第一PCM1的时延与主存储器2的存储量之间可以满足一定的比例关系。例如，第一PCM1的时延与主存储器2的时延之间的比值可以在15～30的范围内，第一PCM1的时延与主存储器2的存储量之间的比值可以在1/500～1/1000的范围内。
控制器3，可以是一个独立的用于对存储设备的数据读写进行控制的控制器，其中的控制逻辑仅用于对第一PCM1和主存储器2中的数据读写进行控制。或者，控制器3也可以是一个具有更多控制功能的综合性控制器，对该存储设备的数据读写进行控制仅仅是控制器3的一部分功能，控制器3中各种功能的控制逻辑是统一部署的，在物理上没有分割到不同的单元中。控制器3中可以包括第一PCM1的操作电路，操作电路在控制器3中可以为独立的单元，或者，也可以不将操作电路设置为独立的单元，将第一PCM1的操作电路的处理逻辑融入到控制器3的处理逻辑中。
下面介绍一下存储设备的具体结构。
第一PCM1和控制器3可以采用2D封装或者3D封装，本申请实施例以3D封装为例进行方案详细说明。在3D封装时，第一PCM1和控制器3在芯片的不同Die中。3D封装的芯片，可以由两个或两个以上的Die组成，控制器3可以设置在一个或多个Die中，第一PCM1也可以设置在一个或多个Die中。可以将控制器3设置在上、第一PCM1设置在下，或者将第一PCM1设置在上、控制器设置在下，等等。例如，芯片包括两个Die，一个Die为控制器3，另一个Die为第一PCM1，或者，芯片包括三个Die，上面的一个Die为控制器3，中间和下面的两个Die为第一PCM1，等等。
第一PCM1和主存储器2分别与控制器3通过线路连接。第一PCM1和控制器3在同一芯片内通过Die之间的垂直线路连接。主存储器2和控制器3之间可以通过PCB上的线路连接，此提供线路连接的PCB可以是存储设备内部的PCB，也可以是存储设备外的其他设备或部件的PCB，或者，也可以同时包括存储设备内部和外部的PCB。主存储器2和控制器3之间也可以不通过PCB进行线路连接，可以也将主存储器2与第一PCM1、控制器3封装在同一芯片中，主存储器2与第一PCM1、控制器3之间可以采用2D封装的方式，也可以采用3D封装的方式。
主存储器2和封装的芯片可以设置在同一PCB上，这样，存储设备是一个整体的器件， 例如，存储设备可以是一个SSD盘，或者存储设备可以是一个PCIe接口的内存。芯片和主存储器2分离设置，这样，存储设备做成两个分离的子部件。
存储设备对外连接形式可以多种多样，可以采用并行总线接口、串行总线接口、或自定义总线接口，或者，也可以不采用可插拔的接口，在加工其他设备时，直接将存储设备加工在其他设备中。
采用3D封装方式，PCM和控制器位于不同的Die中，PCM和控制器重叠放置，不会重复占用面积，可以减小面积占用，而且PCM和控制器之间通过垂直方向的线路连接，垂直方向的线路相对于水平方向的线路来说，占用面积少很多，基本可以认为不占用面积，进一步减小了面积占用。
另外，常规的PCM中会设置有操作电路，因为PCM与控制器之间不是芯片级的连接，连接线路数量较少，所以控制器无法直接对PCM的存储介质中的数据进行读写，必须要有一个操作电路来帮助PCM进行数据读写，即PCM中封装有操作电路和存储介质，他们相互之间是芯片级连接，操作电路可以做到直接对存储介质进行数据读写操作，控制器和操作电路之间设置有相应的协议，他们通过协议相互通信，以下达指令和反馈结果。协议中一般会规定数据读写的单位数据量，这样，假如想要读取的数据量小于单位数据量，那也必须要读取单位数据量的数据，然后再在其中获取真正想要的数据，对于高频率小数据量的应用场景，会严重影响处理效率。
本申请实施例中，通过3D封装方式，PCM和控制器之间是芯片级连接，连接有大量的线路，控制器可以直接对PCM的存储介质中的数据进行读写操作，这样，PCM内部可以不设置常规的操作电路，进而，在数据读写过程中，也省去了控制器与操作电路之间的协议通信，对PCM的数据读写不受常规的控制器与操作电路之间的协议限制，数据读写更加灵活高效。
下面介绍一下存储设备中各部件的功能。
控制器3，用于基于数据的读写热度，将数据存储在所述第一PCM1和所述主存储器2中。
技术人员可以预先为第一PCM1和主存储器2设置对应的读写热度，这里可以根据不同存储器的时延设置对应的读写热度，设置时延较低的存储器存储读写热度较高的数据。第一PCM1的时延小于主存储器2的时延，所以设置第一PCM1存储读写热度较高的数据，主存储器2存储读写热度较低的数据。例如，读写热度包括热、温、冷，可以设置第一PCM1存储热数据，主存储器2存储温数据和冷数据，或者，也可以设置第一PCM1存储热数据和温数据，主存储器2存储冷数据，等等。具体如何设置可以综合考虑应用场景的热数据、温数据、冷数据的比例以及第一PCM1和主存储器2的存储量比例来确定。
基于上述设置，可以基于数据的读写热度，对待存储的数据和/或已存储的数据，在第一PCM1和主存储器2中进行存储调度。进行存储调度的方法可以有很多种，以下对几种可行的方法进行简单介绍。
方法一
控制器3在接收到CPU4发来的待存储的数据时，将该数据判定为热数据，将其存入第一PCM1中。对于已存储的所有数据，控制器3每经过一个周期时长，基于当前周期时长内数据的读写频度，确定数据的读写热度为热、温、或冷，进而，基于数据的读写热度，重新确定数据的存储器，如果新确定的存储器与数据当前所在的存储器不同，则将数据迁移至新确定的存储器。例如，如果第一PCM1中的数据变为冷数据，则将其迁移到主存储器2中， 如果主存储器2中的冷数据变为热数据，则将其迁移到第一PCM1中。
方法二
CPU4向控制器3发送待存储的数据时，同时发送该数据对应的读写热度，控制器3接收到该数据和对应的读写热度后，基于该读写热度确定该数据对应的存储器为第一PCM1或主存储器2，将该数据存入相应的存储器中。对于已存储的所有数据，控制器3每经过一个周期时长，基于当前周期时长内数据的读写频度，确定数据的读写热度为热、温、或冷，进而，基于数据的读写热度，重新确定数据的存储器，如果新确定的存储器与数据当前所在的存储器不同，则将数据迁移至新确定的存储器。
方法三
控制器3在接收到CPU4发来的待存储的数据时，暂不确定该数据的读写热度，将其存入预先指定的存储器(可以指定第一PCM1或主存储器2)中。对于已存储的所有数据，控制器3每经过一个周期时长，基于当前周期时长内数据的读写频度，确定数据的读写热度为热、温、或冷，进而，基于数据的读写热度，重新确定数据的存储器，如果新确定的存储器与数据当前所在的存储器不同，则将数据迁移至新确定的存储器。这样，新存入的数据经过一个周期时长之后就可以确定出读写热度，进而可以继续存储在第一PCM1中或迁移到主存储器2中。
另外，对于某些消费级的应用场景(设备有时会长时间关闭)，在控制器3中可以设置一些正常断电情况下的数据保护机制。控制器3用于：当接收到设备待关闭指令时，将第一PCM1中的数据迁移到主存储器2中，迁移结束后反馈完成通知；当设备启动后，将迁移到主存储器2中的数据迁移回到第一PCM1中。
另外，在控制器3的控制逻辑中还可以设置相应的磨损均衡算法，即在为待存入第一PCM1或主存储器2的数据分配地址时，基于磨损均衡的原则进行地址分配，即选择写入次数最少的存储单元，将其地址分配给待存入的数据。
在实际应用中，控制器3可以支持各种总线通信标准，基于相应的总线通信标准进行通信，如并行总线通信标准、串行总线通信标准或自定义总线通信标准等。
在实际应用中，控制器3与主存储器2之间可以采用各种通信协议，如开放与非闪存接口(open NAND flash interface，ONFI)协议、toggle(一种通信标准名称)协议或私有协议等。
在上述控制器3的控制逻辑中，控制器3将读写热度较高的数据存入第一PCM1，将读写热度较低的数据存入主存储器2。这样，因为CPU频繁读写的数据是那些读写热度较高的数据，而很少会对那些读写热度较低的数据进行读写操作，所以存储设备对外反映出来的时延主要是第一PCM1的时延，主存储器2的时延基本不会被存储设备外部所察觉。而且，只要在一定程度上保证第一PCM1与主存储器2之间的总容量比与计算机设备热数据、温数据、冷数据的比例较为匹配，就能够较为充分的利用第一PCM1和主存储器2的存储空间。这样，既能够很好的发挥主存储器2存储密度高容量大的优点，又可以保证主存储器2时延较高的问题不会对整个存储设备对外的时延产生太大的影响，即可以发挥第一PCM1时延低的优点。
基于上述对存储设备各部件及其功能的介绍，技术人员可以基于实际应用场景以及对成本的要求来设置第一PCM1的时延、主存储器2的时延、第一PCM1的存储量、主存储器2的存储量、以及第一PCM1对应的读写热度、主存储器2对应的读写热度。相应的应用场景有 很多种可能，例如，该存储设备用作某应用的服务器中的内存，或者，该存储设备用作某用户终端中的内存，等等。
以某应用的服务器的内存为例，对于应用的服务器来说，在其运行过程中，内存中热数据、温数据、冷数据的数据量和比例一般是比较稳定的，技术人员可以通过历史统计确定一般状态下内存中热数据、温数据、冷数据的数据量和比例，另外，基于成本和业务需求考虑确定温数据是存储于第一PCM1还是存储于主存储器2，假设确定将温数据存储于第一PCM1中，也就是说，设置将热数据和温数据存储于第一PCM1，将冷数据存储于主存储器2。进一步，可以基于上述统计的该应用热数据和温数据的数据量，确定第一PCM1的存储量，基于上述统计的应用冷数据的数据量，确定主存储器2的存储量。如果应用对内存时延要求不是非常高的话，可以采用20ns左右时延的材料制作第一PCM1。主存储器2存储的是冷数据，所以主存储器2的时延对整个存储设备的时延没有什么影响，可以采用300-500ns时延的材料制作主存储器2。
本申请实施例中，采用较低时延的PCM作为缓存，低时延的PCM介质可以做到在时延低至20ns的同时，仍然具有较高的存储密度，可以达到GB级的大存储量，而且在断电后能够保持数据几天，无需设置掉电保护机制，从而降低成本。控制器将读写热度较高的数据存入PCM，将读写热度较低的数据存入主存储器，这样，既能够很好的利用主存储器存储密度高容量大的优点，又可以保证主存储器时延较高的问题不会对整个存储设备对外的时延产生太大的影响。采用3D封装方式，PCM和控制器位于不同的Die中，PCM和控制器不会重复占用面积，可以减小面积占用，而且PCM和控制器之间通过垂直方向的线路连接，垂直方向的线路不会占用面积，进一步减小了面积占用。另外，通过3D封装方式，PCM和控制器之间可以连接大量的线路，这样，PCM内部无需设置常规的操作电路，相应的，控制器可以直接对PCM中的数据进行读写操作，不受常规的控制器与操作电路之间的协议限制，数据读写更加灵活高效。
本申请实施例提供了一种存储设备，参见图2，存储设备的结构可以如下：
存储设备包括第一PCM1、主存储器2、控制器3和PCB5。主存储器2为第二PCM(第二PCM具有较高的存储密度，可称作高密度PCM)。第一PCM1和控制器3通过3D封装方式封装在CPU4中，第一PCM1和控制器3在CPU4的不同Die中。PCB5具有DDR接口51。主存储器2设置在PCB5上。第一PCM1的时延小于第二PCM，第二PCM的存储密度大于第一PCM1。
上述结构中，存储设备分成了两个独立的部分。第一部分包括第二PCM和PCB5。第二部分包括第一PCM1和控制器2，通过3D封装的方式封装在CPU4中。
第一部分
第二PCM设置在PCB5上，PCB5具有DDR接口51，第二PCM通过PCB5上的线路与DDR接口51连接。第二PCM和控制器3可以兼容DDR JEDEC标准。这样，第二PCM和PCB5则组成一个标准的DDR接口的内存条，与传统DDR接口的内存条不同的是，传统内存条采用DRAM颗粒，而本申请实施例的内存条采用的是PCM颗粒。该内存条可以插在计算机设备主板的DIMM插槽中。这样，第二PCM就可以通过并行总线与CPU4中的控制器2通信。
第二PCM中可以包括存储介质和操作电路，操作电路可以直接对存储介质中的数据进行读写，控制器3与操作电路之间通过相应的协议通信，操作电路在控制器3的指示下进行相应的读写操作，并将结果反馈给控制器3。
需要说明一下，在第二PCM兼容DDR JEDEC标准的情况下，此PCM内存条不是必须与第二部分配合使用，即不是必须与封装有第一PCM1和控制器2的CPU4配合使用，也可以与普通的CPU配合使用，在于普通的CPU配合使用时，PCM内存条就相当于一个普通的内存条，只不过内存颗粒采用了PCM颗粒。
第二部分
第一PCM1和控制器2组成的整体在CPU4中可以是一个在物理上相对独立的单元。这种情况，可以认为第一PCM1、第二PCM和控制器3共同组成内存，控制器2可以在CPU4的内存控制单元指示下进行工作，并对第一PCM1和第二PCM进行管理，第二PCM是内存中的主存，以内存条的形式存在，第一PCM1是内存中的高速缓存，嵌入在CPU4中。CPU4的内存控制单元与控制器2之间存在片内连接线路，可以通过片内连接线路进行通信。内存控制单元可以在CPU4内部向控制器2发送待存储的数据或发送数据读取地址等，控制器2在CPU4内部向内存控制单元发送读取的数据或应答消息等。这样可以大大减小内存控制单元和控制器2之间通信的时延，可以提高传输效率。
或者，第一PCM1也可以作为CPU4的缓存，如4级(L4)缓存，控制器2可以是CPU4的存储控制单元。存在多种具体的实施方式，例如，每级缓存都有独立的缓存控制单元，另外CPU4中还有内存控制单元，内存控制单元和第一PCM1对应的缓存控制单元的组合可以称为控制器2，他们分别负责第一PCM1和第二PCM的控制。
关于控制器3的功能，可以参见本申请实施例上面的内容。
本申请实施例中，存储设备可以完全替代标准的DRAM内存条。与一般的DRAM内存条相比，该存储设备具有低延时的缓存，而且该缓存具有很大的存储量，整个存储设备均采用非易失性存储器，具有很好的防掉电能力。控制器将读写热度较高的数据存入低时延PCM，将读写热度较低的数据存入高密度PCM，这样，既能够很好的利用主存储器存储密度高容量大的优点，又可以保证主存储器时延较高的问题不会对整个存储设备对外的时延产生太大的影响，存储设备对外体现出的时延主要取决于低时延PCM的时延。而且，控制器与CPU中的其它单元采用片内通信，低时延PCM与控制器之间也是采用片内通信，可以有效的降低对低时延PCM的数据读写的时延，也即，能够有效的降低整个存储设备的数据读写的时延。采用3D封装方式，PCM和控制器位于不同的Die中，PCM和控制器不会重复占用面积，可以减小面积占用，而且PCM和控制器之间通过垂直方向的线路连接，垂直方向的线路不会占用芯片面积，进一步减小了面积占用。另外，通过3D封装方式，PCM和控制器之间是芯片级连接，可以连接大量的线路，所以控制器可以直接对PCM中的数据进行读写操作，这样，PCM内部无需设置常规的操作电路，相应的，对PCM的数据读写不受常规的控制器与操作电路之间的协议限制，数据读写更加灵活高效。
上述实施例内容中采用高密度PCM作为主存储器，当然也可以采用NAND存储器作为主存储器，NAND存储器的特性与高密度PCM的特性比较接近，本申请实施例不做具体介绍。另外，基于上述各种结构，控制器3与CPU4的通信协议可以采用通用协议或私有协议。
本申请实施例提供了一种存储设备，存储设备的结构可以如下：
存储设备包括第一PCM1、主存储器2、控制器3和PCB6。主存储器2为第二PCM。第一PCM1和控制器3通过3D封装方式封装在同一芯片中，第一PCM1和控制器3在芯片的不同Die中。3D封装的芯片和第二PCM都设置在PCB6上。PCB6具有串行总线接口或自定义总线 接口。第一PCM1的时延小于第二PCM，第二PCM的存储密度大于第一PCM1。
关于控制器3的功能，可以参见本申请实施例上面的内容。
该结构中，存储设备是一个完整一体的硬件模组，第一PCM1和控制器3封装的芯片与第二PCM都连接在同一PCB上。控制器3和第二PCM通过PCB上的线路相连接，以进行通信，控制器3与第一PCM1通过芯片内的垂直方向的线路连接，以进行通信。第二PCM中可以包括存储介质和操作电路，操作电路可以直接对存储介质中的数据进行读写，控制器3与操作电路之间通过相应的协议通信，操作电路在控制器3的指示下进行相应的读写操作，并将结果反馈给控制器3。
该结构有很多可能的模组形态，以下给出了几种可能的模组形态。
模组形态一，DIMM条，如图3所示。
PCB6上设置有DDR接口61。控制器3支持串行总线通信标准或自定义总线通信标准，存储设备可基于串行总线通信标准或自定义总线通信标准与CPU4通信。整个存储设备的硬件模组是一个DIMM条，与普通DIMM条不同之处在于，普通DIMM条上采用DRAM颗粒，并采用并行总线通信标准，而本存储设备采用高密度PCM颗粒，并采用串行总线通信标准或自定义总线通信标准。这种方案可以对CPU4进行定制化的设计，使CPU4与该DIMM条之间通过串行总线通信标准或自定义总线通信标准进行通信，并使CPU4支持在串行总线或自定义总线上通过内存语义或自定义语义访问该DIMM条。
存储设备采用该模组形态可以使用标准主板上的DIMM插槽，可以很好的兼容已有的主板。该存储设备可以用作内存或DRAM内存的补充内存。
模组形态二，PCIe盘，如图4或图5所示。
PCB6上设置有PCIe接口62。控制器3支持串行总线通信标准或自定义总线通信标准，存储设备基于串行总线通信标准或自定义总线通信标准与CPU4通信。整个存储设备的硬件模组是一个PCIe盘，PCIe盘有很多种不同的形态，图4和图5分别给出了两种具体形态。与普通的PCIe盘不同之处在于，普通的PCIe盘采用DRAM来保存地址映射表，而且采用的是NAND颗粒，而本存储设备可以采用低时延PCM保存地址映射表，并且采用高密度PCM颗粒作为主存储器。
这种模组形态下，存储设备与CPU4之间可以通过PCIe协议通信，存储设备支持输入/输出(input/output，I/O)语义访问，即支持块寻址。这样，存储设备可以作为固态硬盘使用。
这种模组形态下，存储设备与CPU4之间也可以通过计算表达链接(compute express link，CXL)协议通信，存储设备同时支持内存语义和I/O语义访问，即同时支持字节寻址和块寻址。这样，存储设备可以作为固态硬盘使用，也可以作为补充内存使用。
存储设备作为固态硬盘，通过低时延PCM的使用，以及控制器3基于读写热度对数据进行存储调度的机制，存储设备对外可以呈现出较低的时延，作为固态硬盘，可以将平均访问时延降低至1微秒(μs)。存储设备作为补充内存，具有很高的存储密度，可以达到TB级的存储量，而且可以在系统程序或应用程序中设置相应的控制逻辑，基于数据的读写热度在DRAM内存和该存储设备之间进行存储调度(该存储调度可以认为是一级调度，存储设备内部由控制器3控制进行的存储调度可以认为是二级调度)，使DRAM内存存储读写热度较高的数据、该存储设备存储读写热度较低的数据，这样，虽然PCIe接口的固有时延较高，但是上述方案可以保证内存和补充内存组成的整体内存对外的时延不受PCIe接口的固有时延影响。
上述实施例内容中采用高密度PCM作为主存储器，当然也可以采用NAND存储器作为主存储器，NAND存储器的特性与高密度PCM的特性比较接近，本申请实施例不做具体介绍。另外，基于上述各种结构，控制器3与CPU4的通信协议除了可以采用通用协议还可以采用私有协议。
本申请实施例还提供了一种计算机设备，该计算机设备包括上述实施例中的存储设备。计算机设备在配备该存储设备后，可以配备DRAM也可以不配备DRAM。图6示出了计算机设备未配备DRAM的情况，其中，该存储设备可以作为内存。图7示出了计算机设备配备DRAM的情况，其中，DRAM作为内存，该存储设备可以作为补充内存、或者也可以作为SSD。图8示出了计算机设备同时配备DRAM、SSD和上述存储设备的情况，其中，DRAM作为内存，该存储设备可以补充内存、也可以作为SSD与原SSD一起使用、还可以作为原SSD的高速缓存盘使用。
本领域普通技术人员可以理解实现上述实施例的全部或部分步骤可以通过硬件来完成，也可以通过程序来指令相关的硬件完成，所述的程序可以存储于一种计算机可读存储介质中，上述提到的存储介质可以是只读存储器，磁盘或光盘等。
以上所述仅为本申请一个实施例，并不用以限制本申请，凡在本申请的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本申请的保护范围之内。

Claims (15)

  1. 一种存储设备，其特征在于，所述存储设备包括第一相变存储器PCM(1)、主存储器(2)和控制器(3)，其中：
    所述第一PCM(1)和所述控制器(3)封装在同一芯片中；
    所述第一PCM(1)的时延小于所述主存储器(2)，所述主存储器(2)的存储密度大于所述第一PCM(1)；
    所述控制器(3)，用于基于数据的读写热度，将数据存储在所述第一PCM(1)和所述主存储器(2)中，其中，所述第一PCM(1)为所述主存储器(2)的缓存。
  2. 根据权利要求1所述的存储设备，其特征在于，所述封装为三维3D封装，所述第一PCM(1)和所述控制器(3)在所述芯片的不同裸晶Die中。
  3. 根据权利要求1所述的存储设备，其特征在于，所述控制器(3)，用于对所述第一PCM(1)进行读写操作。
  4. 根据权利要求1所述的存储设备，其特征在于，所述主存储器(2)为第二PCM或与非NAND存储器。
  5. 根据权利要求1所述的存储设备，其特征在于，所述第一PCM(1)为吉字节GB级存储器，所述主存储器(2)为太字节TB级存储器；或者，
    所述第一PCM(1)为兆字节MB级存储器，所述主存储器(2)为GB级存储器。
  6. 根据权利要求1-5任一项所述的存储设备，其特征在于，所述第一PCM(1)和所述控制器(3)封装在中央处理器CPU(4)中。
  7. 根据权利要求6所述的存储设备，其特征在于，所述存储设备还包括具有双倍数据速率DDR接口(51)的印制电路板PCB(5)，所述主存储器(2)设置在所述PCB(5)上。
  8. 根据权利要求1-5任一项所述的存储设备，其特征在于，所述存储设备还包括PCB(6)，所述芯片和所述主存储器(2)设置在所述PCB(6)上。
  9. 根据权利要求8所述的存储设备，其特征在于，所述PCB(6)具有DDR接口(61)。
  10. 根据权利要求8所述的存储设备，其特征在于，所述PCB(6)具有高速串行计算机扩展总线标准PCIe接口(62)。
  11. 根据权利要求10所述的存储设备，其特征在于，所述控制器(3)与CPU(4)的通信协议为PCIe协议或计算表达链接CXL协议。
  12. 根据权利要求1-10任一项所述的存储设备，其特征在于，所述控制器(3)与CPU(4)的通信协议为私有协议。
  13. 根据权利要求1-10任一项所述的存储设备，其特征在于，所述控制器(3)支持并行总线通信标准、串行总线通信标准或自定义总线通信标准。
  14. 根据权利要求1-13任一项所述的存储设备，其特征在于，所述控制器(3)与所述主存储器(2)的通信协议为开放与非闪存接口ONFI协议、toggle协议或私有协议。
  15. 一种计算机设备，其特征在于，所述计算机设备包括如权利要求1-14所述的存储设备。
PCT/CN2021/141015 2020-12-30 2021-12-24 一种存储设备和计算机设备 WO2022143434A1 (zh)

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