WO2022141798A1 - Read/write window calibration circuit and method, memory, and fpga chip - Google Patents

Abstract

The embodiments of the present application relate to the technical field of integrated circuits. Provided are a read/write window calibration circuit and method, a memory and an FPGA chip. A read window and a write window can be automatically adjusted, such that in cases where the working frequency of the read/write window calibration circuit satisfies a preset frequency, read data can pass through the read window, and write data can pass through the write window. The read/write window calibration circuit comprises: a calibration verification circuit which verifies, within a current clock period, whether read data and write data can pass through a write window and a read window; a read/write control timing generation circuit which increases the read window when the read data cannot pass through the read window, and increases the write window when the write data cannot pass through the write window; and a calibration verification circuit which acquires the working frequency of the read/write window calibration circuit, and when the working frequency is less than a preset frequency, controls the read/write control timing generation circuit to decrease the read window and/or the write window, and repeatedly verifies, within a next clock period, whether the read data can pass through the read window and whether the write data can pass through the write window.

Description

Read-write window calibration circuit and method, memory, FPGA chip

cross reference

This application claims the priority of the prior application with the title of "Reading and Writing Window Calibration Circuit and Method, Memory, FPGA Chip" filed on December 31, 2020, and the priority of the prior application No. 2020116337909, the contents of the aforementioned prior application are incorporated by reference into this text.

technical field

The present application relates to the technical field of integrated circuits, and in particular, to a read-write window calibration circuit and method, a memory, and an FPGA chip.

Background technique

Field-Programmable Gate Array (FPGA) contains a large amount of memory, and the reading and writing of each storage unit of the memory are completed in a single clock cycle.

As the scale of FPGA chips reaches tens of millions of gates, the risk of process drift and manufacturing defects is also getting higher and higher, and the problem of mismatch between the read/write window of the memory cell and the read/write data often occurs, resulting in read and write functions. Failure, affecting the functional realization of the entire FPGA chip.

SUMMARY OF THE INVENTION

Embodiments of the present application provide a read-write window calibration circuit and method, a memory, and an FPGA chip to solve the above problems.

In a first aspect, a read-write window calibration circuit is provided, including a calibration verification circuit and a read-write control sequence generation circuit. The calibration verification circuit is configured to verify whether the read data can pass the read window and the write data can pass the write window in the current clock cycle. The read-write control timing generation circuit is configured to increase the read window when the read data cannot pass through the read window. The read and write control timing generation circuit is further configured to increase the write window when the write data cannot pass through the write window. The calibration verification circuit is further configured to obtain the operating frequency of the read-write window calibration circuit, and when the operating frequency is less than the preset frequency, controls the read-write control sequence generation circuit to reduce the read window and/or the write window, and at the next clock cycle, and repeatedly verify whether the read data can pass the read window and whether the write data can pass the write window.

In a second aspect, a memory is provided, comprising a plurality of storage units and the read/write window calibration circuit described in the first aspect, where the read/write window calibration circuit is used to calibrate a read window and a write window of the storage unit.

In a third aspect, an FPGA chip is provided, including the memory described in the second aspect.

In a fourth aspect, a method for calibrating a read-write window is provided, comprising: a calibration verification circuit verifies, within a current clock cycle, whether read data can pass the read window and whether write data can pass the write window; when the read data cannot pass the read window When the read-write control sequence generation circuit is used to increase the read window; when the write data cannot pass the write window, the read-write control sequence generation circuit increases the write window; the calibration verification circuit obtains the operating frequency of the read-write window calibration circuit. When the frequency is set, the read and write control sequence generation circuit is controlled to reduce the read window and/or the write window, and in the next clock cycle, it is repeatedly verified whether the read data can pass the read window and whether the write data can pass the write window.

In the read-write window calibration circuit and method, the memory, and the FPGA chip provided by the embodiments of the present application, the read-write window calibration circuit includes a calibration verification circuit and a read-write control sequence generation circuit. Use the calibration verification circuit to verify whether the read data can pass the read window and whether the write data can pass the write window; when the read data cannot pass the read window, the read window can be increased to make the read data pass through the read window as much as possible. When the write window cannot be passed, the write window can be increased to make the write data pass through the write window as much as possible; after that, due to the increase of the read window and/or the write window, the operating frequency of the read and write window calibration circuit is reduced. If the frequency is less than the preset frequency, the read window and/or the write window can be appropriately reduced, so that the read data can pass through the read window and the write data can pass through the write window, and the operating frequency meets the preset frequency, so that the read and write window calibration circuit can operate normally. At the working frequency, read and write data. The above process can be automatically completed by the read-write window calibration circuit, which is convenient and reliable, and can improve user experience.

Description of drawings

In order to illustrate the technical solutions of the embodiments of the present application more clearly, the following drawings will briefly introduce the drawings that need to be used in the embodiments. It should be understood that the following drawings only show some embodiments of the present application, and therefore do not It should be regarded as a limitation of the scope, and for those of ordinary skill in the art, other related drawings can also be obtained according to these drawings without any creative effort.

1 is a circuit connection diagram of a read-write window calibration circuit provided by an embodiment of the present application;

2 is a working process diagram of a read-write window calibration circuit provided by an embodiment of the present application;

3 is a working process diagram of a read-write window calibration circuit provided by an embodiment of the present application;

4 is a working process diagram of a read-write window calibration circuit provided by an embodiment of the present application;

5 is a working process diagram of a read-write window calibration circuit provided by an embodiment of the present application;

6 is a working process diagram of a read-write window calibration circuit provided by an embodiment of the present application;

FIG. 7 is a relationship diagram of each module of a memory provided by an embodiment of the present application;

FIG. 8 is a relationship diagram of each module of an FPGA chip provided by an embodiment of the present application;

FIG. 9 is a schematic flowchart of a read-write window calibration method provided by an embodiment of the present application.

Reference number:

10000-FPGA chip; 1000-memory; 100-read-write window calibration circuit; 10-calibration verification circuit; 20-read-write control sequence generation circuit; 30-status register; 40-environmental monitoring circuit; 50-read-write window configuration adjustment circuit; 60-configuration memory; 200-storage unit.

Detailed ways

In order to make the purposes, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments It is a part of the embodiments of the present application, but not all of the embodiments. The components of the embodiments of the present application generally described and illustrated in the drawings herein may be arranged and designed in a variety of different configurations. It should be noted that the features in the embodiments of the present application may be combined with each other under the condition of no conflict.

As shown in FIG. 1 , an embodiment of the present application provides a read-write window calibration circuit 100 , which includes a calibration verification circuit 10 and a read-write control sequence generation circuit 20 .

The calibration verification circuit 10 is configured to verify whether the read data can pass the read window and whether the write data can pass the write window in the current clock cycle. The read/write control timing generation circuit 20 is configured to increase the read window when the read data cannot pass the read window, and to increase the write window when the write data cannot pass the write window. The calibration verification circuit 10 is further configured to obtain the operating frequency of the read-write window calibration circuit 100, and when the operating frequency is less than the preset frequency, control the read-write control sequence generation circuit to reduce the read window and/or the write window, and at the next clock cycle, and repeatedly verify whether the read data can pass the read window and whether the write data can pass the write window.

On this basis, the read-write window calibration circuit 100 may further include a status register 30 for storing the verification result of the calibration verification circuit 10 .

Specifically, as shown in FIG. 1 and FIG. 2 , after the configuration programming is completed, the read/write control sequence generation circuit 20 can send the Verify_en signal to the calibration verification circuit 10. When the Verify_en signal is at a high level, under the action of the Verify_en signal, The calibration verification circuit 10 starts to verify whether the read data can pass the read window and whether the write data can pass the write window.

When the read data cannot pass through the read window, it means that the read window is too small, resulting in that the read data cannot completely pass through the read window. The calibration verification circuit 10 can send the Adjust_en signal and the Adjust_rd signal to the read-write control sequence generation circuit 20. When the Adjust_en signal and the Adjust_rd signal When the level is high, the read/write control timing generation circuit 20 is ready to work when receiving the Adjust_en signal, and when the read/write control timing generation circuit 20 receives the Adjust_rd signal, it starts to adjust the timing of the read window to increase the read window.

When the write data cannot pass the read window, it means that the write window is too small, so that the write data cannot pass through the write window completely. The calibration verification circuit 10 can send the Adjust_en signal and the Adjust_wr signal to the read and write control timing generation circuit 20. When the Adjust_en signal and the Adjust_wr signal When the level is high, the read/write control sequence generation circuit 20 is ready to work when receiving the Adjust_en signal, and when the read/write control sequence generation circuit 20 receives the Adjust_wr signal, it starts to adjust the timing of the write window and increase the write window.

After the read window and/or the write window is increased, the time occupied by the read window and/or the write window becomes longer, resulting in a decrease in the operating frequency of the read/write window calibration circuit 100. When the operating frequency is less than the preset frequency, the calibration verification circuit 10 receives the Freq_overflow signal, when the Freq_overflow signal is at a high level, the calibration verification circuit 10 can control the read and write control sequence generation circuit 20 to reduce the read window and/or the write window, and in the next clock cycle, repeatedly verify whether the read data can pass through. Whether the read window and write data can pass through the write window. If the read data can pass the read window and the write data can pass the write window, as shown in FIG. 3 , the output calibration is successful, and the verification is stopped. The calibration verification circuit 10 sends the Verify_successed signal to the status register 30, and the status register 30 will verify the successful The state is stored; if the read data cannot pass through the read window, and/or the write data cannot pass through the write window, continue to increase the read window and/or the write window according to the process shown in FIG. 1 . When the calibration is successful, the Verify_en signal goes from high to low.

In the above-mentioned process, the calibration verification circuit 10 and the read-write control sequence generation circuit 20 both start to work under a high-level signal, which is related to the characteristics of the calibration verification circuit 10 and the read-write control sequence generation circuit 20. Of course, it can also be The characteristics of the calibration verification circuit 10 and the read/write control sequence generation circuit 20 are changed, so that the calibration verification circuit 10 and the read/write control sequence generation circuit 20 work when receiving a low-level signal, which is not particularly limited in the embodiment of the present application. The same applies below.

In some embodiments, when the operating frequency is less than the preset frequency, the calibration verification circuit 10 can control the read and write control timing generation circuit 20 to reduce the read window and/or the write window, including:

When the read data cannot pass the read window, the read/write control sequence generation circuit 20 increases the read window, and if the operating frequency is less than the preset frequency, the calibration verification circuit 10 can control the read/write control sequence generation circuit 20 to reduce the read window. Wherein, the width of the increased read window (the duration of the read window is increased) is greater than the width of the decreased read window.

When the read data cannot pass the read window, the read/write control sequence generation circuit 20 increases the read window, and if the operating frequency is less than the preset frequency, the calibration verification circuit 10 can control the read/write control sequence generation circuit 20 to reduce the write window. Due to the current clock cycle, the write data can pass through the write window, but the read data cannot pass through the read window. Therefore, when the operating frequency is lower than the preset frequency due to the increase of the read window, the write window can be reduced, and the increase of the read window can be reduced. After that, the read data still fails to pass the read window.

When the read data cannot pass the read window, and the read/write control sequence generation circuit 20 increases the read window, if the operating frequency is less than the preset frequency, the calibration verification circuit 10 may control the read/write control sequence generation circuit 20 to reduce the read window and write window. Wherein, the width of the increased read window is greater than the width of the decreased read window.

When the write data cannot pass the write window and the read/write control sequence generation circuit 20 increases the write window, if the operating frequency is lower than the preset frequency, the calibration verification circuit 10 can control the read/write control sequence generation circuit 20 to reduce the write window. Wherein, the width of the increased write window (the duration of the write window is increased) is greater than the width of the decreased write window.

When the write data cannot pass the write window, and the read/write control sequence generation circuit 20 increases the write window, if the operating frequency is less than the preset frequency, the calibration verification circuit 10 may control the read/write control sequence generation circuit 20 to reduce the read window. Due to the current clock cycle, the read data can pass through the read window, but the write data cannot pass through the write window. Therefore, when the operating frequency is lower than the preset frequency due to the increase of the write window, the read window can be reduced. The probability that the read data still fails to pass the write window.

When the write data cannot pass through the write window, in the case where the read/write control sequence generation circuit 20 increases the write window, if the operating frequency is less than the preset frequency, the calibration verification circuit 10 can control the read/write control sequence generation circuit 20 to reduce the read window and write window. Wherein, the width of the increased write window is greater than the width of the decreased write window.

In some embodiments, the adjustment gears of the read window and the write window can be stored in advance, and each gear is correspondingly increased or decreased by a certain width.

For example, assuming that the adjustment gear is coded in 3-bit binary, the adjustment gear of the read window is represented by RD_Pn, the adjustment gear of the write window is represented by WR_Pn, WR_P0 and RD_P0 are 000, WR_P1 and RD_P1 are 001, WR_P2 and RD_P2 is 010, WR_P3 and RD_P3 are 011, WR_P4 and RD_P4 are 100, WR_P5 and RD_P5 are 101, WR_P6 and RD_P6 are 110, and WR_P7 and RD_P7 are 111. The operating frequency (unit MHz) corresponding to the adjustment gear of the read window and the adjustment gear of the write window can be as follows:

	WR_P0	WR_P1	WR_P2	WR_P3	WR_P4	WR_P5	WR_P6	WR_P7
RD_P0	600	550	500	450	400	350	320	300
RD_P1	550	500	450	400	360	320	300	280
RD_P2	500	450	400	360	330	300	280	260
RD_P3	450	400	360	330	300	280	260	240
RD_P4	400	360	330	300	280	260	240	230
RD_P5	350	330	300	280	260	240	230	220
RD_P6	320	300	280	260	240	230	220	210
RD_P7	300	280	260	240	230	220	210	200

When the read-write control sequence generation circuit 20 adjusts the read window or the write window, one or more adjustment gears can be increased or decreased each time. Of course, the adjustment gears for adjusting the read window and the write window can also be coded with other bits binary, and the adjustment gears can also be divided into more gears or less gears, which is not specifically limited in this application.

In some embodiments, in order to prevent the operating frequency from being too low to meet normal operating requirements, only one gear may be adjusted at a time when the read window and/or the write window is increased. For example, the initial gear position corresponding to the read window in the current clock cycle is RD_P4. When increasing the read window, the read window can be adjusted to the timing corresponding to RD_P5. If the read window is RD_P5, the read data still cannot pass through the read window. Then adjust the read window to RD_P6.

In some embodiments, the aforementioned solution includes: firstly increasing the read window, and then decreasing the read window because the operating frequency is lower than the preset frequency; or, first increasing the write window, and then decreasing the read window because the operating frequency is smaller than the preset frequency write window. In this case, the number of gears adjusted when the read window or the write window is increased is greater than the number of gears adjusted when the read window or the write window is reduced.

For example, the initial gear position corresponding to the read window in the current clock cycle is RD_P0. When increasing the read window, you can first adjust the read window to RD_P2; then, when reducing the read window, you can adjust the read window from RD_P2 to RD_P1. .

In some embodiments, the preset frequency may be the frequency of the read-write window calibration circuit 100 set by the user as required. When the read-write window calibration circuit 100 is applied to the FPGA chip, the preset frequency may also be the frequency of the FPGA chip set by the user as required.

In some embodiments, when the read/write control timing generation circuit 20 increases the read window, or increases the write window, or decreases the read window, or decreases the write window, it actually changes the read window or the timing of the write window.

In some embodiments, the read and write window calibration circuit 100 may calibrate the read window and the write window one or more times until the calibration is successful or the calibration is in error.

In some embodiments, before calibrating the read window and the write window for the first time, the adjustment gear of the initial read window may be a non-minimum gear, that is, non-RD_P0, and the adjustment gear of the initial write window may be a non-minimum gear, That is, not WR_P0.

For example, the adjustment gear of the initial read window and the adjustment gear of the initial write window may be the maximum adjustment gear. If the adjustment gear of the initial read window and the initial write window is the maximum gear, the read data still fails to pass the read window, and/or the write data still fails to pass the write window, an output calibration error occurs.

In some embodiments, the read data cannot pass through the read window, which means that all the read data cannot pass through the read window, or part of the read data cannot pass through the read window.

The write data cannot pass through the write window, which means that all the write data cannot pass through the write window, or part of the write data cannot pass through the write window.

The embodiment of the present application provides a read-write window calibration circuit 100 . The read-write window calibration circuit 100 includes a calibration verification circuit 10 and a read-write control sequence generation circuit 20 . Use the calibration verification circuit 10 to verify whether the read data can pass the read window and whether the write data can pass the write window; when the read data cannot pass the read window, the read window can be increased to make the read data pass through the read window as much as possible. When the data cannot pass through the write window, the write window can be increased to make the write data pass through the write window as much as possible; after that, due to the increase in the read window and/or the write window, the operating frequency of the read and write window calibration circuit 100 is reduced. If the operating frequency is less than the preset frequency, the read window and/or the write window can be appropriately reduced, so that the read data can pass through the read window and the write data can pass through the write window, and the operating frequency satisfies the preset frequency, so that the read and write window calibration circuit 100 Data can be read and written at normal operating frequency. The above process can be automatically completed by the read-write window calibration circuit 100, which is convenient and reliable, and can improve user experience.

Optionally, as shown in FIG. 2 , the calibration verification circuit 10 is also configured to repeatedly verify whether the read data can pass the read window and whether the write data can pass in the next clock cycle when the operating frequency is greater than or equal to the preset frequency. write window.

That is, since the read window and/or write window is increased, it is not yet certain whether the read data can pass the read window and the write data can pass the write window after the read window and/or write window is increased. The operating frequency of the window calibration circuit 100 satisfies the preset frequency, and it is also possible to verify again whether the read data can pass the read window and whether the write data can pass the write window.

Optionally, as shown in FIG. 4 , the calibration verification circuit 10 is also configured to determine the clock cycle before the current clock cycle when the verification read data cannot pass the read window within the current clock cycle, and the read-write control sequence is generated. Whether circuit 20 reduces the read window.

The calibration verification circuit 10 is further configured to control the read/write control sequence generation circuit 20 to increase the read window if the read/write control sequence generation circuit 20 does not reduce the read window in the clock cycle before the current clock cycle.

The calibration verification circuit 10 is also configured to output a calibration error in the clock cycle before the current clock cycle if the read-write control sequence generation circuit 20 has reduced the read window.

Specifically, if the read and write control sequence generation circuit 20 does not reduce the read window in the clock cycle before the current clock cycle, it means that the operating frequency in the clock cycle before the current clock cycle meets the preset frequency. If the data cannot pass through the read window, the read data can pass through the read window by increasing the read window. Otherwise, in the clock cycle before the current clock cycle, the over-read window may be reduced because the operating frequency is lower than the preset frequency. In this case, even if the read window is increased, the read window may increase, causing the operating frequency to be less than Preset frequency, therefore, without increasing the read window, directly output calibration error, simplifying logic steps.

Optionally, the calibration verification circuit 10 is further configured to determine whether the read and write control sequence generation circuit 20 reduces the write time in the clock cycle before the current clock cycle when verifying that the write data cannot pass the write window within the current clock cycle. window.

The calibration verification circuit 10 is further configured to control the read/write control sequence generation circuit 20 to increase the write window if the read/write control sequence generation circuit 20 does not reduce the write window in the clock cycle before the current clock cycle.

The calibration verification circuit 10 is further configured to output a calibration error in the clock cycle before the current clock cycle if the read-write control sequence generation circuit has reduced the write window. Specifically, if the read and write control sequence generation circuit 20 does not reduce the read window in the clock cycle before the current clock cycle, it means that the clock cycle before the current clock cycle, the operating frequency meets the preset frequency, in this case, if the write If the data cannot pass through the write window, the write data can pass through the write window by increasing the write window. Otherwise, in the clock cycle before the current clock cycle, the overwrite window may be reduced because the operating frequency is lower than the preset frequency. In this case, even if the write window is increased, the operating frequency may be lower than the preset frequency again due to the increase in the write window. Set the frequency, therefore, without increasing the write window, the calibration error is directly output, and the logic steps are simplified.

In the embodiment of the present application, when it is verified that the read data cannot pass the read window and the write data cannot pass the write window, it may be determined whether the read window or the write window has been reduced in the clock cycle before the current clock cycle, and if the clock cycle has not been reduced The read window or write window indicates that the operating frequency meets the preset frequency, and the read window or write window can be increased to allow the read data or write data to pass; if the read window or write window is reduced, it indicates the clock cycle before the current clock cycle , because the operating frequency is lower than the preset frequency, the over-read window or write window is reduced. In this case, even if the write window is increased, the read window or write window may increase, causing the operating frequency to be lower than the preset frequency again. Therefore, there is no need to Increase the read window or write window, directly output calibration errors, and simplify the logic steps.

Optionally, as shown in FIG. 5 , the calibration verification circuit 10 is also configured to, when the operating frequency is less than the preset frequency, determine whether the read and write control sequence generation circuit 20 increases the read window in the clock cycle before the current clock cycle. and write window.

The calibration verification circuit 10 is further configured to determine whether the read window and/or the write window can be reduced if both the read window and the write window are not increased in a clock cycle before the current clock cycle.

The calibration verification circuit 10 is further configured to control the read and write control timing generation circuit to reduce the read window and/or the write window when the read window and/or the write window can be reduced.

The calibration verification circuit 10 is further configured to output a calibration error in the clock cycle before the current clock cycle if the read and write control sequence generation circuit has increased the read window and the write window.

Specifically, when the operating frequency is less than the preset frequency, the calibration verification circuit 10 receives the Freq_overflow signal, and the Freq_overflow signal is at a high level, and the calibration verification circuit 10 determines whether the read window and the write window are increased in the clock cycle before the current clock cycle. big.

If both the read window and the write window are increased in the clock cycle before the current clock cycle, it means that in the previous clock cycle, because the read data cannot pass the read window and the write data cannot pass the write window, the read window and the write window are increased respectively. Write window, in this case, if the read window and/or write window is reduced in the current clock cycle, the read data may not pass the read window, and/or the write data may not pass the write window. Therefore, the direct output calibration Error, no longer reduce the read window and/or write window.

If both the read window and the write window are not increased in the clock cycle before the current clock cycle, it means that in the current clock cycle, the operating frequency can at least be increased by reducing the read window or the write window. Therefore, the calibration verification The circuit 10 can determine whether the read window and/or the write window can be reduced, and if the read window and/or the write window can be reduced, the calibration verification circuit 10 controls the read and write control timing generation circuit 20 to reduce the read window and/or the write window ;If the read window and write window cannot be reduced, the output calibration is wrong.

In some embodiments, neither the read window nor the write window is increased in a clock cycle prior to the current clock cycle, including: in a clock cycle prior to the current clock cycle, the read window is increased but the write window is not increased; or, In the clock cycle before the current clock cycle, the write window is increased, but the read window is not increased; or, in the clock cycle before the current clock cycle, neither the read window nor the write window is increased.

In the embodiment of the present application, when it is determined that the operating frequency is less than the preset frequency, it may also be determined whether the read window and the write window have both increased in the clock cycle before the current clock cycle, and if both the read window and the write window have increased , the calibration error can be output directly, simplifying the logic steps; if both the read window and the write window have not been enlarged, it can be determined whether the read window and/or the write window can be further reduced, and if so, reduce the read window and/or the write window. Or write windows, otherwise, the output calibration is wrong, simplifying the logic steps.

Optionally, as shown in FIG. 1 and FIG. 6 , the read/write window calibration circuit 100 further includes an environment monitoring circuit 40 . The environmental monitoring circuit 40 is configured to acquire the environmental monitoring signal, and send the environmental monitoring signal to the calibration verification circuit 10 when the environmental monitoring signal does not satisfy the preset signal. The calibration verification circuit 10 is further configured to receive the environmental monitoring signal, and to verify whether the read data can pass the read window and whether the write data can pass the write window in a new clock cycle.

In some embodiments, the environment monitoring signal may be the temperature and voltage of the current working environment of the read/write window calibration circuit 100, and the preset signal may be the corresponding preset temperature and preset voltage.

When the temperature of the current working environment does not meet the preset temperature, and/or the voltage of the current working environment does not meet the preset voltage, the environment monitoring signal can be sent to the calibration verification circuit 10, and the calibration verification circuit 10 can be used to verify whether the read data is The read window or the write window can be adjusted through the read window and whether the write data can pass through the write window.

Here, the preset temperature may have a certain preset temperature range, and the temperature of the current working environment does not meet the preset temperature, including: the temperature of the current working environment is greater than the upper limit of the preset temperature range, or the temperature of the current working environment is lower than the preset temperature. Sets the lower limit of the temperature range.

The preset voltage may have a certain preset voltage range, and the voltage of the current working environment does not meet the preset voltage, including: the voltage of the current working environment is greater than the upper limit of the preset voltage range, or the voltage of the current working environment is less than the preset voltage range lower limit of .

In some embodiments, the environment monitoring signal does not meet the preset signal, it may also be that the difference between the current working environment temperature and the previously measured ambient temperature exceeds the preset signal, or the current working environment voltage and the previously measured The difference in ambient voltage exceeds the preset signal.

In this case, the environment monitoring circuit 40 may include a temperature detection circuit, a voltage detection circuit, and a comparator. The temperature detection circuit is used to detect the temperature of the current working environment, the voltage detection circuit is used to detect the voltage of the current environment, and the comparator is used to detect the current environment. The temperature of the current working environment is compared with the previously measured ambient temperature. If the difference between the two is greater than the preset signal, the environment monitoring signal does not meet the preset signal, or the comparator is used to compare the voltage of the current working environment with the previous one. The ambient voltages measured once are compared, and if the difference between the two is greater than the preset signal, the environment monitoring signal does not meet the preset signal.

In the embodiment of the present application, when the temperature, voltage and other factors of the current working environment of the read-write window calibration circuit 100 change, the timing of the read window and the write window may also be affected, or the transmission of read data or write data may be affected. Therefore, in the environment When the monitoring signal does not meet the preset signal, the environmental monitoring signal can be sent to the calibration verification circuit 10, and the calibration verification circuit 10 is used to verify whether the read data can pass the read window and whether the write data can pass the write window, and then the read window or write window can be verified. Make adjustments.

Optionally, as shown in FIG. 1 , the read-write window calibration circuit further includes a user calibration circuit. The user calibration circuit is configured to send the user calibration signal to the read-write control timing generation circuit 20 . The read-write control timing generation circuit 20 is further configured to receive a user calibration signal, and adjust the read window and/or the write window according to the user calibration signal.

Specifically, the foregoing embodiment describes an embodiment in which the read and write window calibration circuit 100 automatically adjusts the read window and the write window, but in this embodiment of the present application, the user can also manually adjust the read window and the write window. The user can trigger the user calibration circuit to send the user calibration signals User_adjust_en and User_adjust_wrrd to the read/write control sequence generation circuit 20. When the user calibration signals User_adjust_en and User_adjust_wrrd are at a high level, the read/write control sequence generation circuit 20 starts to work and adjusts according to User_adjust_wrrd Read window and/or write window.

The user calibration signal User_adjust_wrrd includes increasing the read window, increasing the write window, decreasing the read window, and decreasing the write window.

In some embodiments, when the user sends a user calibration signal to the read/write control sequence generation circuit 20 through the user calibration circuit, the calibration verification circuit 10 also controls the read/write control sequence generation circuit 20 to adjust the read window and/or the write window, then The read-write control sequence generation circuit 20 adjusts the read window and/or the write window according to the user calibration signal sent by the user calibration circuit, or the read-write control sequence generation circuit 20 adjusts the read window and/or the write window according to the Adjust_en signal, the adjust_rd signal, and the Adjust_wr signal sent by the calibration verification circuit 10 Adjust the read window and/or write window.

In this embodiment of the present application, the user can also manually adjust the read window and/or the write window according to his wishes.

Optionally, as shown in FIG. 1 , the read/write window calibration circuit 100 further includes a read/write window configuration adjustment circuit 50 and a configuration memory 60 .

The read-write window configuration adjustment circuit 50 is configured to receive the adjustment signal sent by the calibration verification circuit 10 when the read data cannot pass the read window, and/or the write data cannot pass through the write window, and call the adjustment information according to the adjustment signal , the adjustment information is sent to the configuration memory 60 .

The configuration memory 60 is configured to receive the adjustment information, call the configuration information corresponding to the adjustment information, and send the configuration information to the read-write control sequence generation circuit 20 .

The read and write control timing generation circuit 20 is further configured to adjust the read window and/or the write window according to the configuration information.

Specifically, when the read data cannot pass the read window, and/or the write data cannot pass the write window, the calibration verification circuit 10 sends an adjustment signal Adjust_en to the read and write window configuration adjustment circuit 50, when the adjustment signal Adjust_en is at a high level , the read-write window configuration adjustment circuit 50 works and calls the adjustment information, and then sends the adjustment information to the configuration memory 60; after the configuration memory 60 receives the adjustment information, it calls the configuration information corresponding to the adjustment information, and sends the configuration information to the read-write The control timing generation circuit 20 is controlled, and the read and write control timing generation circuit 20 adjusts the timing of the read window and/or the write window according to the configuration information, so as to adjust the read window and/or the write window.

In some embodiments, the adjustment information may be the adjustment gears of the read window and the write window. For example, the adjustment gear corresponding to the initial adjustment information of the read window is RD_P0. After the read/write window configuration adjustment circuit 50 receives the adjustment signal Adjust_en, It is determined that the adjustment gear corresponding to the adjusted adjustment information is RD_P1.

The configuration information may be information corresponding to the adjustment information for adjusting the timing of the read window and the write window.

The adjustment information may be stored in the read/write window configuration adjustment circuit 50 in advance, and the configuration information may be stored in the configuration memory 60 in advance.

In this embodiment of the present application, when it is determined that the read data cannot pass the read window, and/or the write data cannot pass the write window, the adjustment information may be called from the read/write window configuration adjustment circuit 50, and the configuration may be called from the configuration memory 60. information, and then use the read/write control timing generation circuit 20 to adjust the timing of the read window and/or the write window according to the configuration information.

As shown in FIG. 7 , an embodiment of the present application further provides a memory 1000. The memory 1000 includes a plurality of storage units 200 and the read-write window calibration circuit 100 described in any of the foregoing embodiments. The read-write window calibration circuit 100 is used for calibration The read window and the write window of the storage unit 200 .

In some embodiments, the memory cells 200 may correspond to the read/write window calibration circuits 100 one-to-one, and one read/write window calibration circuit 100 is used to calibrate the read window and the write window of one memory cell.

In some embodiments, as shown in FIG. 1 , the memory cell 200 may include a read control circuit, a write control circuit, and a memory array.

When the word line between the read control circuit and the storage array is at a high level, the read control circuit and the storage array are turned on, and the read control circuit stores the read data into the storage array through the bit line; When the word line is at a high level, the write control circuit conducts with the storage array, and the write control circuit stores the write data into the storage array through the bit line.

When the word line between the storage array and the calibration verification circuit 10 is at a high level, the storage array sends the stored read data and write data to the calibration verification circuit 10 through the bit line between the storage array and the calibration verification circuit 10 for calibration The verification circuit 10 verifies whether the read data can pass through the read window and whether the write data can pass through the write window.

In some embodiments, the memory may be a static random-access memory (Static Random-Access Memory, SRAM), and the plurality of storage units 200 of the SRAM are programmable block memory (Block RAM, BRAM for short).

An embodiment of the present application provides a memory 1000. For other explanations and beneficial effects, reference may be made to the foregoing embodiments, which will not be repeated here.

As shown in FIG. 8 , an embodiment of the present application may further provide an FPGA chip 10000 including the memory 1000 described in any of the foregoing embodiments.

On this basis, the FPGA chip 10000 may further include a logic circuit 2000 . The logic circuit 200 can store data in the memory 1000 and can also retrieve data from the memory 1000 .

Embodiments of the present application provide an FPGA chip 10000. For other explanations and beneficial effects, reference may be made to the foregoing embodiments, which will not be repeated here.

As shown in FIG. 9 , an embodiment of the present application provides a method for calibrating a read-write window, including:

S110, the calibration verification circuit 10 verifies whether the read data can pass the read window and whether the write data can pass the write window in the current clock cycle.

S120. When the read data cannot pass through the read window, the read-write control sequence generation circuit 20 increases the read window.

S130. When the write data cannot pass through the write window, the read/write control sequence generation circuit 20 increases the write window.

S140, the calibration verification circuit 10 obtains the operating frequency of the read-write window calibration circuit, and when the operating frequency is less than the preset frequency, controls the read-write control sequence generation circuit 20 to reduce the read window and/or the write window, and repeats in the next clock cycle Verify that read data can pass the read window and write data can pass the write window.

On this basis, in the case of step S120, step S140 may include controlling the read/write control sequence generation circuit 20 to reduce the write window when the operating frequency is less than the preset frequency.

In the case of step S130, step S140 may include controlling the read/write control sequence generation circuit 20 to reduce the read window when the operating frequency is less than the preset frequency.

When the operating frequency is greater than or equal to the preset frequency, after steps S120 and S130, the read-write window calibration method may further include: in the next clock cycle, repeatedly verifying whether the read data can pass the read window and whether the write data can pass Able to write through the window.

In the current clock cycle, when it is verified that the read data cannot pass the read window, after step S110 and before step S120 and step S130, the read-write window calibration method may further include: determining a clock cycle before the current clock cycle, Whether the read-write control sequence generation circuit 20 reduces the read window; in the clock cycle before the current clock cycle, if the read-write control sequence generation circuit 20 does not reduce the read window, then the read-write control sequence generation circuit 20 is controlled to increase the read window; In the clock cycle before the current clock cycle, if the read-write control timing generation circuit 20 has reduced the read window, the output calibration is in error.

In the current clock cycle, when verifying that the write data cannot pass the write window, after step S110 and before step S120 and step S130, the read-write window calibration method may further include: determining a clock cycle before the current clock cycle, Whether the read-write control sequence generation circuit 20 reduces the write window; in the clock cycle before the current clock cycle, if the read-write control sequence generation circuit 20 does not reduce the write window, then the read-write control sequence generation circuit 20 is controlled to increase the write window; In the clock cycle before the current clock cycle, if the read-write control sequence generation circuit 20 has reduced the write window, the output calibration is in error.

When the operating frequency is less than the preset frequency, after step S120 and step S130 and before step S140, the read-write window calibration method may further include: determining a clock cycle before the current clock cycle, whether the read-write control sequence generation circuit 20 is Increase the read window and the write window; in the clock cycle before the current clock cycle, if both the read window and the write window are not increased, determine whether the read window and/or the write window can be reduced; During the read window and/or the write window, control the read/write control sequence generation circuit 20 to reduce the read window and/or write; in the clock cycle before the current clock cycle, if the read/write control sequence generation circuit 20 has increased the read window and the write window, the output calibration error.

After step S110 and before step S120 and step S130, when the read data can pass the read window and the write data can pass the write window, the output calibration is successful.

For other explanations and beneficial effects of the embodiments of the present application, reference may be made to the foregoing embodiments, which will not be repeated here.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, but not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand: it can still be Modifications are made to the technical solutions described in the foregoing embodiments, or some technical features thereof are equivalently replaced; and these modifications or replacements do not drive the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims (14)

1. A read-write window calibration circuit, comprising:

   The calibration verification circuit is configured to verify whether the read data can pass the read window and whether the write data can pass the write window within the current clock cycle;

   a read-write control sequence generation circuit, configured to increase the read window when the read data cannot pass through the read window;

   The read-write control sequence generation circuit is further configured to increase the write window when the write data cannot pass through the write window;

   The calibration verification circuit is further configured to obtain the operating frequency of the read-write window calibration circuit, and when the operating frequency is less than a preset frequency, control the read-write control sequence generation circuit to reduce the read window and/or or the write window, and in the next clock cycle, it is repeatedly verified whether the read data can pass through the read window and whether the write data can pass through the write window.
2. The read/write window calibration circuit according to claim 1, wherein the read/write control timing generation circuit is configured to increase the read/write window when the read data cannot pass through the read window. In this case, the calibration verification circuit is further configured to control the read-write control sequence generation circuit to reduce the write window when the operating frequency is less than a preset frequency.
3. The read-write window calibration circuit according to claim 1, wherein the read-write control timing generation circuit is configured to increase the write window when the read data cannot pass the write window. In this case, the calibration verification circuit is further configured to control the read-write control sequence generation circuit to reduce the read window when the operating frequency is less than a preset frequency.
4. The read-write window calibration circuit according to claim 1, wherein,

   The calibration verification circuit is further configured to repeatedly verify whether the read data can pass the read window and whether the write data can pass the write window in the next clock cycle when the operating frequency is greater than or equal to the preset frequency.
5. The read-write window calibration circuit according to claim 1, wherein,

   The calibration verification circuit is further configured to determine whether the read-write control sequence generation circuit decrements the clock cycle before the current clock cycle when it is verified that the read data cannot pass the read window within the current clock cycle. Small said reading window;

   The calibration verification circuit is further configured to control the read-write control sequence generation circuit to increase the read window in the clock cycle before the current clock cycle if the read-write control sequence generation circuit does not reduce the read window. read window;

   The calibration verification circuit is further configured to output a calibration error in a clock cycle before the current clock cycle if the read-write control sequence generation circuit has reduced the read window.
6. The read-write window calibration circuit according to claim 1, wherein,

   The calibration verification circuit is further configured to determine whether the read-write control sequence generation circuit decrements the clock cycle before the current clock cycle when verifying that the write data cannot pass the write window within the current clock cycle. Small said writing window;

   The calibration verification circuit is further configured to control the read-write control sequence generation circuit to increase the write window in the clock cycle before the current clock cycle if the read-write control sequence generation circuit does not reduce the write window. write window;

   The calibration verification circuit is further configured to output a calibration error in a clock cycle before the current clock cycle if the read-write control sequence generation circuit has reduced the write window.
7. The read-write window calibration circuit according to claim 1, wherein,

   The calibration verification circuit is further configured to, when the operating frequency is less than a preset frequency, determine whether the read-write control sequence generation circuit increases the read window and the write-in clock cycle before the current clock cycle. window;

   The calibration verification circuit is further configured to determine whether the read window and/or the write window can be reduced if both the read window and the write window are not increased in a clock cycle before the current clock cycle window;

   The calibration verification circuit is further configured to control the read-write control sequence generation circuit to reduce the read window and/or write when the read window and/or the write window can be reduced;

   The calibration verification circuit is further configured to output a calibration error in a clock cycle before the current clock cycle if the read and write control sequence generation circuit has increased the read window and the write window.
8. The read-write window calibration circuit according to claim 1, wherein,

   The calibration verification circuit is further configured to output a successful calibration when the read data can pass through the read window and the write data can pass through the write window.
9. The read-write window calibration circuit according to any one of claims 1-8, wherein the read-write window calibration circuit further comprises an environmental monitoring circuit;

   The environmental monitoring circuit is configured to acquire the environmental monitoring signal, and send the environmental monitoring signal to the calibration verification circuit when the environmental monitoring signal does not meet the preset signal;

   The calibration verification circuit is further configured to receive the environment monitoring signal, and to verify whether the read data can pass the read window and whether the write data can pass the write window in a new clock cycle.
10. The read-write window calibration circuit according to any one of claims 1-8, wherein the read-write window calibration circuit further comprises a user calibration circuit;

    the user calibration circuit, configured to send a user calibration signal to the read-write control sequence generation circuit;

    The read-write control timing generation circuit is further configured to receive the user calibration signal and adjust the read window and/or the write window according to the user calibration signal.
11. The read-write window calibration circuit according to any one of claims 1-8, wherein the read-write window calibration circuit further comprises a read-write window configuration adjustment circuit and a configuration memory;

    The read-write window configuration adjustment circuit is configured to receive an adjustment signal sent by the calibration verification circuit when the read data cannot pass through the read window, and/or when the write data cannot pass through the write window , and call adjustment information according to the adjustment signal, and send the adjustment information to the configuration memory;

    The configuration memory is configured to receive the adjustment information, call the configuration information corresponding to the adjustment information, and send the configuration information to the read-write control sequence generation circuit;

    The read-write control timing generation circuit is further configured to adjust the read window and/or the write window according to the configuration information.
12. A memory is characterized by comprising a plurality of storage units and the read-write window calibration circuit according to claims 1-11, wherein the read-write window calibration circuit is used for calibrating a read window and a write window of the storage unit.
13. An FPGA chip, characterized by comprising the memory of claim 12 .
14. A read-write window calibration method, comprising:

    The calibration verification circuit verifies whether the read data can pass the read window and whether the write data can pass the write window within the current clock cycle;

    When the read data cannot pass the read window, the read-write control sequence generation circuit increases the read window;

    When the write data cannot pass the write window, the read-write control sequence generation circuit increases the write window;

    The calibration verification circuit obtains the operating frequency of the read-write window calibration circuit, and when the operating frequency is less than a preset frequency, controls the read-write control sequence generation circuit to reduce the read window and/or the write window , and in the next clock cycle, it is repeatedly verified whether the read data can pass through the read window and whether the write data can pass through the write window.

Images