TWI780810B - Non-volatile memory apparatus and a method for determining a read verification voltage - Google Patents

Abstract

A non-volatile memory apparatus including a non-volatile memory and a memory controller is provided. At a first temperature, the memory controller performs a read operation on the non-volatile memory by using a first reference verification voltage to obtain a failure bit count of memory cells. At a second temperature different from the first temperature, the memory controller performs the read operation on the non-volatile memory many times and adjusts the first reference verification voltage to obtain the same failure bit count. The reference verification voltage used in the read operation that the same failure bit count is obtained is a second reference verification voltage. The memory controller compares the first reference verification voltage and the second reference verification voltage to obtain a difference value thereof. In addition, a method for determining a read verification voltage of the non-volatile memory is also provided.

Description

Non-volatile memory device and method for determining read verification voltage thereof

The present invention relates to a memory device and its operating voltage determination method, and in particular to a non-volatile memory device and its read verification voltage determination method.

With the evolution of electronic technology, electronic devices have become a necessary tool in people's lives. Non-volatile memory devices such as flash memory can provide long-term and large-scale data storage functions, and have become important data storage media. After the write operation of the non-volatile memory, the minimum value of its threshold voltage distribution curve is usually greater than the write verification voltage. However, after the non-volatile memory is baked, the threshold voltage of a part of the memory unit cells may be lower than the read verification voltage, and this part of the memory unit cells is called a retention failure bit (retention). failure bit). If there are too many memory cells whose threshold voltage is lower than the read verification voltage, the non-volatile memory device may fail to pass the read verification, indicating that its data retention performance (retention performance) is poor and the reliability is insufficient.

In addition, the critical voltage distribution curve of the memory unit cell will change its peak position due to the influence of temperature. Compared with the critical voltage distribution curve at room temperature, the peak value of the critical voltage distribution curve at different temperatures will change. At this time, if the read verification voltage is not adjusted accordingly, the number of memory cells determined to be invalid may increase, resulting in inconsistent verification results.

The invention provides a non-volatile memory device and a method for determining the read verification voltage, which can make the read verification results consistent at different temperatures.

The non-volatile memory device of the present invention includes a non-volatile memory and a memory controller. Non-volatile memory includes multiple memory cells. The memory controller is coupled to the non-volatile memory. At the first temperature, the memory controller uses the first reference verification voltage to perform a read operation on the non-volatile memory to obtain the number of failed bits of the memory unit cell. When the second temperature is different from the first temperature, the memory controller performs multiple read operations on the non-volatile memory, and adjusts the first reference verification voltage successively to obtain the same number of failed bits. The reference verification voltage used when obtaining the same number of failed bits in the read operation is the second reference verification voltage. The memory controller compares the first reference verification voltage and the second reference verification voltage to obtain a difference between them.

In an embodiment of the present invention, the above-mentioned second temperature is higher than the first temperature. At the second temperature, the memory controller gradually reduces the first reference verification voltage to perform multiple read operations on the non-volatile memory.

In an embodiment of the present invention, at the first temperature, before the memory controller performs a read operation on the non-volatile memory, the memory controller first performs an erase operation on the non-volatile memory, and then Write operation to non-volatile memory.

In an embodiment of the present invention, the above memory controller determines the first reference verification voltage according to the write verification voltage.

In an embodiment of the present invention, the above-mentioned memory controller adds the writing verification voltage to the reference voltage difference to determine the first reference verification voltage.

In an embodiment of the present invention, the above-mentioned first reference verification voltage is the central threshold voltage of the threshold voltage distribution curve of the memory cell at the first temperature.

In an embodiment of the present invention, the number of memory cells whose threshold voltage is less than or equal to the first reference verification voltage is the number of failed bits of the memory cell.

In an embodiment of the present invention, the memory controller uses a first read verification voltage to perform a read operation on the non-volatile memory at a first temperature. The memory controller uses the second read verification voltage to perform a read operation on the non-volatile memory at the second temperature. The second read verify voltage is the first read verify voltage plus a difference.

The method for determining the read verification voltage of the non-volatile memory device of the present invention includes: at the first temperature, using the first reference verification voltage to perform a read operation on the non-volatile memory to obtain failure of the memory unit cell number of bits; When the first temperature is the second temperature, multiple read operations are performed on the non-volatile memory, and the first reference verification voltage is adjusted successively to obtain the same number of failed bits. The reference verification voltage used when obtaining the read operation with the same number of failed bits is the second reference verification voltage; comparing the first reference verification voltage and the second reference verification voltage to obtain a difference between the two; and according to The difference between the first reference verification voltage and the second reference verification voltage and the read verification voltage at the first temperature determine the read verification voltage at the second temperature.

In an embodiment of the present invention, the above-mentioned second temperature is higher than the first temperature. At the second temperature, the first reference verification voltage is gradually reduced to perform multiple read operations on the non-volatile memory.

In an embodiment of the present invention, the method for determining the read verification voltage of the non-volatile memory device further includes: at the first temperature, before performing the read operation on the non-volatile memory, The volatile memory is erased, and then the non-volatile memory is written.

In an embodiment of the present invention, the method for determining the read verification voltage of the non-volatile memory device further includes: determining a first reference verification voltage according to the write verification voltage.

In an embodiment of the present invention, in the step of determining the first reference verification voltage according to the writing verification voltage, the writing verification voltage is added to the reference voltage difference to determine the first reference verification voltage.

In an embodiment of the present invention, the above-mentioned first reference verification voltage is the central threshold voltage of the threshold voltage distribution curve of the memory cell at the first temperature.

In an embodiment of the present invention, the number of memory cells whose critical voltage is less than or equal to the first reference verification voltage is the number of failed bits of the memory cell.

In an embodiment of the present invention, in the step of determining the read verification voltage at the second temperature according to the difference between the first reference verification voltage and the second reference verification voltage and the read verification voltage at the first temperature, the The difference is added to the read verification voltage at the first temperature to determine the read verification voltage at the second temperature.

Based on the above, in the embodiment of the present invention, the non-volatile memory device and the method for determining the read verification voltage compensate the read verification voltage at the second temperature, so that the read verification results at different temperatures have the same consistency.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail together with the accompanying drawings.

100: Non-volatile memory device

110: Non-volatile memory

112: Memory cell

120: memory controller

200, 300, 400, 500: critical voltage distribution curve

210, 310: area

600: read voltage

BL: bit line

DV: Difference

DV_ref: Reference voltage difference

PV, PV1, PV2, PV3, PV4: write verification voltage

RV1, RV2: read verification voltage

S100, S110, S120, S130, S140, S200, S210, S220, S230: Method steps

SL: source line

T1, T2: temperature

Vt, Vt1, Vt2: critical voltage

Vt_c: central critical voltage

WL: character line

"00": information

FIG. 1 shows a schematic diagram of a non-volatile memory device according to an embodiment of the present invention.

FIG. 2 and FIG. 3 respectively show the threshold voltage distribution diagrams of the memory unit cell in the embodiment of FIG. 1 at different temperatures.

FIG. 4 is a graph showing the threshold voltage distribution of a memory unit cell at room temperature according to an embodiment of the present invention.

Figure 5 shows the threshold voltage of the memory unit cell at high temperature according to an embodiment of the present invention Distribution.

FIG. 6 is a flow chart showing the steps of the method for determining the compensation difference of the non-volatile memory device according to an embodiment of the present invention.

FIG. 7 is a flow chart showing the steps of a method for determining a read verification voltage of a non-volatile memory device according to an embodiment of the present invention.

FIG. 1 shows a schematic diagram of a non-volatile memory device according to an embodiment of the present invention. Fig. 2 and Fig. 3 respectively depict the critical voltage distribution diagram of the memory unit cell of the embodiment of Fig. 1 at different temperatures, the horizontal axis is the critical voltage Vt of the memory unit cell, and the vertical axis is the number of bits (bit count), That is, the number of memory cells. Please refer to FIG. 1 to FIG. 3 , the non-volatile memory device 100 of this embodiment includes a non-volatile memory 110 and a memory controller 120 . The memory controller 120 is coupled to the non-volatile memory 110 . The memory controller 120 is used for writing and reading operations on the non-volatile memory 110 .

The non-volatile memory 110 includes a plurality of memory cells 112 . FIG. 1 only depicts one memory unit cell 112 for illustration, and the number thereof is not used to limit the present invention. The memory cell 112 includes a first terminal, a second terminal and a control terminal. The first terminal is coupled to the bit line BL, the second terminal is coupled to the source line SL, and the control terminal is coupled to the word line WL. During the read operation, the memory controller 120 applies the read voltage 600 to the memory cell 112 and verifies whether its threshold voltage is greater than the read verification voltage RV1 or RV2 , as shown in FIGS. 2 and 3 .

Specifically, FIG. 2 shows the threshold voltage distribution diagram of the memory unit cell at room temperature T1 (the first temperature). In this example, the memory controller 120 uses the read verification voltage RV1 (first read verification voltage) to perform a read operation on the non-volatile memory 110 at the room temperature T1. That is, the memory controller 120 performs a read operation on the memory cell 112 at the room temperature T1, and verifies whether its threshold voltage is greater than the read verification voltage RV1. When reading at room temperature, in the region 210 where the critical voltage is less than or equal to the read verification voltage RV1, the memory unit cell 112 will be judged as a failure bit (failure bit), and its number is called the failure bit number (failure bit). count, FBC). In this embodiment, the room temperature T1 is, for example, 25° C., but the present invention is not limited thereto.

Similarly, FIG. 3 shows the distribution diagram of the threshold voltage of the memory cell at the high temperature T2 (the second temperature). In this example, the memory controller 120 uses the read verification voltage RV2 (second read verification voltage) to perform a read operation on the non-volatile memory 110 at a high temperature T2 higher than the room temperature T1. That is to say, the memory controller 120 performs a read operation on the memory cell 112 at a high temperature T2, and its read verification voltage is adjusted to the read verification voltage RV2, so as to ensure that the memory cell 112 is read at a high temperature. The number of failed bits for cell 112 (region 310) will be about the same as when reading at room temperature. Therefore, when reading at high temperature, in the region 310 where the threshold voltage is less than or equal to the read verification voltage RV2 , the memory cell 112 will be determined as a failed bit. In this embodiment, the high temperature T2 is, for example, 90° C., but the present invention is not limited thereto. That is, the second temperature T2 is higher than the first temperature T1.

Generally speaking, the critical voltage distribution curve of the memory cell will be affected by the temperature The influence changes the position of its peak value. Compared with the threshold voltage distribution curve 200 at room temperature, the peak value of the threshold voltage distribution curve 300 at high temperature will shift to the left, as shown in FIG. 3 . If the read verification voltage is not adjusted accordingly, the number of memory cells determined to be invalid may increase, resulting in inconsistent verification results. Therefore, in order to make the read verification results consistent at different temperatures, the memory controller 120 will compensate the read verification voltage when reading at high temperature, and adjust the verification reference from the read verification voltage RV1 to the read verification Voltage RV2. For example, in this embodiment, at high temperature, the memory controller 120 adds a difference DV to the read verification voltage RV1 to obtain the read verification voltage RV2 , wherein the difference DV is a negative value. That is to say, the memory controller 120 will reduce the value of the read verification voltage when the temperature is high.

In one embodiment, if the second temperature T2 is lower than the first temperature T1, the memory controller 120 adjusts the read verification voltage by adding a difference DV to the read verification voltage RV1 to obtain the read verification voltage. Voltage RV2, where the difference DV is positive. That is to say, the memory controller 120 will increase the value of the read verification voltage when the temperature is low. In addition, in the embodiments shown in FIGS. 1 to 3 , although the second temperature T2 is higher than the first temperature T1 to illustrate the concept of the present invention, the second temperature T2 is lower than the first temperature T1. And so on.

The following describes how to obtain the difference DV that compensates the read verification voltage.

FIG. 4 is a graph showing the threshold voltage distribution of a memory unit cell at room temperature according to an embodiment of the present invention. Please refer to FIG. 4, before the memory controller 120 performs a read operation on the non-volatile memory 110, the memory controller 120 first performs an erase operation on the non-volatile memory, and then performs an erase operation on the non-volatile memory 110 write operation to the The data “00” is written into the non-volatile memory 110 . The data "00" is used for illustration only, and the present invention is not limited. Next, at the room temperature T1 (the first temperature), the memory controller 120 uses the first reference verification voltage PV1 to perform a read operation on the non-volatile memory 110 to obtain the number of failed bits of the memory unit cell 112 .

In this embodiment, the memory controller 120 determines the first reference verification voltage PV1 according to the writing verification voltage PV. For example, the memory controller 120 adds the write verification voltage PV to the reference voltage difference DV_ref to determine the first reference verification voltage PV1. In this example, the first reference verification voltage PV1 is the central threshold voltage Vt_c of the threshold voltage distribution curve 400 of the memory cell 112 at the room temperature T1. Therefore, at room temperature T1, the number of memory cells 112 whose critical voltage is less than or equal to the first reference verification voltage PV1 (ie, the number of failed bits of the memory cell) accounts for about 50% of the total number of memory cells 112 %. The memory controller 120 can store the failed bit number in a fuse block in the non-volatile memory device 100 .

In this embodiment, setting the first reference verification voltage PV1 as the central threshold voltage Vt_c of the threshold voltage distribution curve 400 is only for illustration and not for limiting the present invention. The first reference verification voltage PV1 can be set to any value between the threshold voltages Vt1 to Vt2. The first reference verification voltage PV1 can be set differently according to different memory chips, which is not limited by the present invention.

FIG. 5 is a graph showing the threshold voltage distribution of a memory unit cell at high temperature according to an embodiment of the present invention. Please refer to FIG. 5, when the high temperature T2 (second temperature), the memory controller 120 performs multiple read operations on the non-volatile memory 110, and adjusts the Adjust the reference verify voltage to achieve the same number of failed bits as at room temperature. For example, in FIG. 5 , the memory controller 120 decreases the reference verification voltage successively to perform multiple read operations on the non-volatile memory. Therefore, the memory controller 120 decreases the reference verification voltage from PV1 to PV4 successively. The memory controller 120 sets the reference verification voltage PV3 used in the read operation to obtain the same number of failed bits as the second reference verification voltage.

That is to say, at the high temperature T2, the memory controller 120 sequentially uses the reference verification voltages PV1, PV2, PV3 and PV4 to perform a read operation on the non-volatile memory 110 to obtain the failure bit of the memory unit cell 112 , where the same number of failed bits as at room temperature can be obtained at the third read operation. Therefore, the memory controller 120 sets the reference verification voltage PV3 as the second reference verification voltage. Therefore, at the high temperature T2, the number of memory cells 112 whose threshold voltage is less than or equal to the second reference verification voltage PV3 also accounts for about 50% of the total number of memory cells 112 .

Next, the memory controller 120 compares the first reference verification voltage PV1 and the second reference verification voltage PV3 to calculate and obtain a difference DV therebetween. For example, the memory controller 120 subtracts the first reference verification voltage PV1 from the second reference verification voltage PV3 to obtain a difference DV between the two, wherein the difference DV is a negative value. In another embodiment, the first reference verification voltage PV1 may be subtracted from the second reference verification voltage PV3 to obtain a difference between the two, wherein the difference is a positive value.

Therefore, referring to the disclosed content of the embodiments of FIG. 4 and FIG. 5 , the difference DV of the compensating read verification voltage can be obtained.

FIG. 6 illustrates compensation of a non-volatile memory device according to an embodiment of the present invention Flowchart of the steps for determining the difference. Please refer to FIG. 1 and FIG. 6 , the method for determining the compensation difference in this embodiment is at least applicable to the non-volatile memory device 100 in FIG. 1 , but the present invention is not limited thereto. Taking the non-volatile memory device 100 in FIG. 1 as an example, in step S100 , the memory controller 120 performs an erase operation on the non-volatile memory 110 at the first temperature T1 . In step S110, the memory controller 120 performs a write operation on the non-volatile memory 110 at the first temperature T1.

In step S120 , the memory controller 120 uses the first reference verification voltage PV1 to perform a read operation on the non-volatile memory 110 at the first temperature T1 to obtain the number of failed bits of the memory unit cell 112 . In step S130 , the memory controller 120 performs multiple read operations on the non-volatile memory 110 at the second temperature T2 , and adjusts the first reference verification voltage PV1 successively to obtain the same number of failed bits. In this step, the second reference verification voltage PV3 is used as the reference verification voltage for obtaining the same number of failed bits in the read operation. In step S140 , the memory controller 120 compares the first reference verification voltage PV1 and the second reference verification voltage PV3 to obtain a difference DV therebetween. The difference DV can compensate the read verification voltage at the second temperature T2. In addition, the method for determining the compensation difference in this embodiment can obtain sufficient teachings, suggestions and implementation instructions from the description of the embodiments in FIGS. 1 to 5 .

FIG. 7 is a flow chart showing the steps of a method for determining a read verification voltage of a non-volatile memory device according to an embodiment of the present invention. Please refer to FIG. 1 and FIG. 7 , the method for determining the read verification voltage in this embodiment is at least applicable to the non-volatile memory device 100 in FIG. 1 , but the present invention is not limited thereto. The non-volatile memory device shown in Figure 1 100 as an example, in step S200, at the first temperature T1, the memory controller 120 uses the first reference verification voltage PV1 to perform a read operation on the non-volatile memory 110 to obtain the failure bit of the memory cell 112 arity. In step S210, the memory controller 120 performs multiple read operations on the non-volatile memory 110 at a second temperature T2 different from the first temperature T1, and adjusts the first reference verification voltage PV1 successively to obtain Same number of invalid bits. In this step, the second reference verification voltage PV3 is used as the reference verification voltage for obtaining the same number of failed bits in the read operation.

In step S220 , the memory controller 120 compares the first reference verification voltage PV1 and the second reference verification voltage PV3 to obtain a difference DV therebetween. Next, in step S230, the memory controller 120 determines the read verification at the second temperature T2 according to the difference PV3 between the first reference verification voltage PV1 and the second reference verification voltage and the read verification voltage RV1 at the first temperature T1. Voltage RV2. For example, the memory controller 120 compensates the read verification voltage at the second temperature T2, and reduces the verification reference from the read verification voltage RV1 to the read verification voltage RV2, and the reduction range is the absolute value of the difference DV . In addition, the method for determining the read verification voltage of this embodiment can obtain sufficient teachings, suggestions and implementation descriptions from the descriptions of the embodiments in FIGS. 1 to 6 .

To sum up, in the embodiment of the present invention, when the memory controller performs a read operation on the non-volatile memory at a temperature other than room temperature, it will compensate the read verification voltage, so as to adjust the read verification voltage , allowing consistent read verification results across temperatures. In addition, the read verify voltage of the embodiment of the present invention determines the The method can be executed on individual memory chips to determine respective read verify voltages for the individual memory chips.

Although the present invention has been disclosed above with the embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field may make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention should be defined by the scope of the appended patent application.

S200, S210, S220, S230: method steps

Claims (16)

A non-volatile memory device comprising: a non-volatile memory including a plurality of memory cells; and a memory controller coupled to the non-volatile memory, wherein at a first temperature, the The memory controller uses a first reference verification voltage to perform a read operation on the non-volatile memory to obtain a failure bit number of the memory cells; at a second temperature different from the first temperature , the memory controller performs multiple read operations on the non-volatile memory, and adjusts the first reference verification voltage successively to obtain the same number of failed bits, wherein the same number of failed bits is obtained The reference verification voltage used in the read operation is a second reference verification voltage; and the memory controller compares the first reference verification voltage and the second reference verification voltage to obtain a difference between them. The non-volatile memory device as claimed in claim 1, wherein the second temperature is higher than the first temperature, and at the second temperature, the memory controller gradually reduces the first reference verification voltage to The non-volatile memory performs multiple read operations. The non-volatile memory device according to claim 1, wherein at the first temperature, before the memory controller reads the non-volatile memory, the memory controller first The memory is erased, and then the non-volatile memory is written. The non-volatile memory device as claimed in claim 1, wherein the memory controller determines the first reference verification voltage according to a write verification voltage. The non-volatile memory device as claimed in claim 4, wherein the memory controller adds a reference voltage difference to the write verification voltage to determine the first reference verification voltage. The non-volatile memory device as claimed in claim 5, wherein the first reference verification voltage is a central threshold voltage of a threshold voltage distribution curve of the memory cells at the first temperature. The non-volatile memory device as claimed in claim 1, wherein the number of the memory cells whose threshold voltage is less than or equal to the first reference verification voltage is the number of failed bits of the memory cells. The non-volatile memory device as claimed in claim 1, wherein the memory controller uses a first read verification voltage to perform a read operation on the non-volatile memory at the first temperature; and the memory controller When the device is at the second temperature, a second read verification voltage is used to perform a read operation on the non-volatile memory, wherein the second read verification voltage is the first read verification voltage plus the difference. A method for determining a read verification voltage of a non-volatile memory device, wherein the non-volatile memory includes a plurality of memory cells, and the determination method includes: using a first reference verification voltage at a first temperature The non-volatile note performing a read operation on the memory to obtain a failure bit number of the memory cells; performing multiple read operations on the non-volatile memory at a second temperature different from the first temperature, and adjusting the first reference verification voltage successively to obtain the same number of failed bits, wherein the reference verification voltage used in the read operation to obtain the same number of failed bits is a second reference verification voltage; comparing the first reference verification voltage and the second reference verification voltage to obtain a difference therebetween; and a read verification according to the difference between the first reference verification voltage and the second reference verification voltage and the first temperature voltage to determine a read verification voltage at the second temperature. The method for determining the read verification voltage of a non-volatile memory device as claimed in claim 9, wherein the second temperature is higher than the first temperature, and at the second temperature, the first reference verification voltage is gradually reduced , to perform multiple read operations on the non-volatile memory. The method for determining the read verification voltage of a non-volatile memory device as described in Claim 9 further includes: at the first temperature, before performing a read operation on the non-volatile memory, The memory is erased, and then the non-volatile memory is written. The method for determining the read verification voltage of the non-volatile memory device as claimed in Claim 9 further includes: determining the first reference verification voltage according to a write verification voltage. The method for determining the read verification voltage of a non-volatile memory device as described in claim 12, wherein in the step of determining the first reference verification voltage according to the write verification voltage, the write verification voltage is added to The last reference voltage difference to determine the first reference verification voltage. The method for determining the read verification voltage of a non-volatile memory device as claimed in claim 13, wherein the first reference verification voltage is the central threshold of the threshold voltage distribution curve of the memory cells at the first temperature Voltage. The method for determining the read verification voltage of a non-volatile memory device according to claim 9, wherein the number of the memory cells whose critical voltage is less than or equal to the first reference verification voltage is the memory cells The number of invalid bits. The method for determining the read verification voltage of a non-volatile memory device as described in claim 9, wherein the read is based on the difference between the first reference verification voltage and the second reference verification voltage and the first temperature In the step of determining the read verification voltage at the second temperature by verifying the voltage, the difference is added to the read verification voltage at the first temperature to determine the read verification voltage at the second temperature.

Images