JP2023549200A - Read/write window calibration circuit, method, memory and FPGA chip - Google Patents

Abstract

Embodiments of the present invention provide a read/write window calibration circuit and method, a memory, an FPGA chip, and relate to the technical field of integrated circuits, which can adjust the read window and write window spontaneously, and provide a read/write window calibration circuit. When the operating frequency satisfies a predetermined frequency, read data is caused to pass through the read window, and write data is caused to pass through the write window. The read/write window calibration circuit includes a calibration verification circuit that verifies whether or not read data and write data can pass through the read window and write window in the current clock cycle, and a calibration verification circuit that verifies whether or not read data and write data can pass through the read window and write window. The calibration verification circuit includes a read/write control timing generation circuit that increases the read window when the write data cannot pass through the write window and increases the write window when the write data cannot pass through the write window. If the operating frequency is lower than a predetermined frequency, the read/write control timing generation circuit is controlled to reduce the read window and/or the write window, and the read data passes through the read window in the next clock cycle. It is repeatedly verified whether the write data can pass through the write window. [Selection diagram] Figure 1

Description

The present invention relates to the technical field of integrated circuits, and more particularly to read/write window calibration circuits, methods, memories, and FPGA chips.

A field-programmable gate array (abbreviated as FPGA) includes a large amount of memory, and each storage unit of the memory is read and written within a single clock period. be.

As the scale of FPGA chips reaches the 10 million gate level, the risk of process drift and manufacturing defects is also increasing, and there is always a problem of mismatch between the read/write window of the storage unit and the read/write data. This causes the read and write functions to become invalid, which affects the realization of the entire FPGA chip function.

Embodiments of the present invention provide a read/write window calibration circuit, method, memory, and FPGA chip to solve the above problems.

According to a first aspect, the read/write window calibration circuit determines whether read data can pass through the read window and whether write data can pass through the write window in the current clock cycle. and a read/write control timing generation circuit configured to enlarge the read window if the read data cannot pass through the read window, The read/write control timing generation circuit is configured to enlarge the write window when write data cannot pass through the write window, and the calibration verification circuit acquires an operating frequency of the read/write window calibration circuit. If the operating frequency is lower than a predetermined frequency, the read/write control timing generation circuit is controlled to reduce the read window and/or the write window, and the read data is A read/write window calibration circuit configured to repeatedly verify whether the read window can be passed through and whether the write data can pass through the write window is provided.

According to a second aspect, there is provided a memory including a plurality of storage units and the read/write window calibration circuit according to the first aspect for calibrating read windows and write windows of the storage units.

According to a third aspect, there is provided an FPGA chip including the memory according to the second aspect.

According to a fourth aspect, in the read/write window calibration method, the calibration verification circuit determines whether or not read data can pass through the read window in the current clock cycle, and whether write data can pass through the write window. a step of verifying whether or not the read data is possible to pass through the read window; a step in which a read/write control timing generation circuit enlarges the read window; and a step of causing the write data to pass through the write window. If it is not possible, the read/write control timing generation circuit enlarges the write window, and the calibration verification circuit obtains an operating frequency of the read/write window calibration circuit, and if the operating frequency is smaller than a predetermined frequency, controlling the read/write control timing generation circuit to reduce the read window and/or the write window, and determining whether or not the read data can pass through the read window in the next clock cycle; There is provided a read/write window calibration method characterized by including the step of repeatedly verifying whether or not write data can pass through the write window.

In the read/write window calibration circuit, method, memory, and FPGA chip according to embodiments of the present invention, the read/write window calibration circuit includes a calibration verification circuit and a read/write control timing generation circuit. A calibration verification circuit is used to verify whether read data can pass through the read window and whether write data can pass through the write window, and it is determined that read data cannot pass through the read window. If it is impossible for write data to pass through the write window, increase the write window and make the write data pass through the write window as much as possible. Since the read window and/or write window are made larger, the operating frequency of the read/write window calibration circuit becomes smaller, and if the operating frequency is lower than the predetermined frequency, the read window and/or write By appropriately reducing the window, read data can pass through the read window, write data can pass through the write window, and the operating frequency satisfies a predetermined frequency, so that the read/write window calibration circuit can operate normally. Data can be read/written at the same operating frequency. The above process can be completed autonomously by the read/write window calibration circuit 100, which is convenient and reliable, and can improve the user experience.

In order to more clearly explain the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings that need to be used in the embodiments, and for your understanding, the following drawings are some of the drawings of the present invention. It shows only examples of the drawings and therefore should not be considered as limiting the scope, and it is not for those skilled in the art to further obtain other relevant drawings based on these drawings without creative labor. Can be done.

FIG. 3 is a circuit connection diagram of a read/write window calibration circuit according to an embodiment of the present invention. FIG. 3 is an operation process diagram of a read/write window calibration circuit according to an embodiment of the present invention. FIG. 3 is an operation process diagram of a read/write window calibration circuit according to an embodiment of the present invention. FIG. 3 is an operation process diagram of a read/write window calibration circuit according to an embodiment of the present invention. FIG. 3 is an operation process diagram of a read/write window calibration circuit according to an embodiment of the present invention. FIG. 3 is an operation process diagram of a read/write window calibration circuit according to an embodiment of the present invention. FIG. 3 is a relationship diagram of each module of the memory according to the embodiment of the present invention. FIG. 3 is a relationship diagram of each module of the FPGA chip according to the embodiment of the present invention. 3 is a flowchart of a read/write window calibration method according to an embodiment of the present invention.

In order to make the objectives, technical solutions and advantages of the embodiments of the present invention more clear, the following will refer to the drawings of the embodiments of the present invention to make the technical solutions of the embodiments of the present invention clear and complete. Obviously, the described embodiments are some but not all embodiments of the invention. Generally, the components of the embodiments of the invention described and illustrated herein may be arranged and designed in a variety of different configurations. Note that the features in the embodiments of the present invention can be combined with each other as long as there is no contradiction.

As shown in FIG. 1, according to an embodiment of the present invention, a read/write window calibration circuit 100 is provided. The read/write window calibration circuit 100 includes a calibration verification circuit 10 and a read/write control timing generation circuit 20.

The calibration verification circuit 10 is configured to verify whether read data can pass through the read window and whether write data can pass through the write window in the current clock cycle. The read/write control timing generation circuit 20 is configured to enlarge the read window when read data cannot pass through the read window, and to enlarge the write window when write data cannot pass through the write window. The calibration verification circuit 10 acquires the operating frequency of the read/write window calibration circuit 100, and if the operating frequency is lower than a predetermined frequency, controls the read/write control timing generation circuit to reduce the read window and/or write window. , is configured to repeatedly verify whether read data can pass through the read window and whether write data can pass through the write window in the next clock cycle.

Based on this, the read/write window calibration circuit 100 may further include a status register 30 that stores the verification results of the calibration verification circuit 10.

Specifically, as shown in FIGS. 1 and 2, after the programming of the settings is completed, the read/write control timing generation circuit 20 can send the Verify_en signal to the calibration verification circuit 10, and the Verify_en signal goes high. level, the Verify_en signal causes the calibration verification circuit 10 to verify whether the read data can pass through the read window and whether the write data can pass through the write window. Start.

If the read data cannot pass through the read window, the read window is too small and the read data cannot pass through the read window completely. Then, the calibration verification circuit 10 can transmit the Adjust_en signal and the Adjust_rd signal to the read/write control timing generation circuit 20, and when the Adjust_en signal and the Adjust_rd signal are at high level, the read/write control timing generation circuit 20 transmits the Adjust_en signal and the Adjust_rd signal to the read/write control timing generation circuit 20. When it receives a signal, it prepares for action. When the read/write control timing generation circuit 20 receives Adjust_rd, it starts adjusting the read window timing and enlarges the read window.

If the write data cannot pass through the light window, the write window is too small and the write data cannot pass through the light window completely. Then, the calibration verification circuit 10 can transmit the Adjust_en signal and the Adjust_wr signal to the read/write control timing generation circuit 20, and when the Adjust_en signal and the Adjust_wr signal are at high level, the read/write control timing generation circuit 20 transmits the Adjust_en signal and the Adjust_wr signal to the read/write control timing generation circuit 20. When it receives a signal, it prepares for action. When the read/write control timing generation circuit 20 receives the Adjust_wr signal, it starts adjusting the timing of the write window and enlarges the write window.

After increasing the read window and/or write window, the time occupied by the read window and/or write window becomes longer, causing a reduction in the operating frequency of the read/write window calibration circuit 100. If the operating frequency is lower than a predetermined frequency, the calibration verification circuit 10 receives the Freq_overflow signal, and if the Freq_overflow signal is at a high level, the calibration verification circuit 10 performs read operation to reduce the read window and/or write window. Control a write control timing generation circuit 20 to repeatedly verify whether read data can pass through a read window and whether write data can pass through a write window in the next clock cycle. Can be done. If the read data can pass through the read window and the write data can pass through the write window, as shown in FIG. 3, a calibration success is output and the verification is stopped. The calibration verification circuit 10 then sends a Verify_successed signal to the status register 30, and the status register 30 stores the verification success status. If read data cannot pass through the read window and/or if write data cannot pass through the write window, the read window and/or write window are continuously enlarged according to the flow shown in FIG. . When the calibration is successful, the Verify_en signal goes from high level to low level.

In the above process, both the calibration verification circuit 10 and the read/write control timing generation circuit 20 start operating with a high level signal. This relates to the self-characteristics of the calibration verification circuit 10 and the read/write control timing generation circuit 20. Of course, the characteristics of the calibration verification circuit 10 and the read/write control timing generation circuit 20 may be changed so that the calibration verification circuit 10 and the read/write control timing generation circuit 20 operate when receiving a low level signal. The embodiments of the present invention are not particularly limited thereto, and the same applies hereinafter.

In the embodiment, when the operating frequency is lower than a predetermined frequency, the calibration verification circuit 10 can control the read/write control timing generation circuit 20 to reduce the read window and/or write window.
When the read/write control timing generation circuit 20 enlarges the read window when the read data cannot pass through the read window, the calibration verification circuit 10 reduces the read window when the operating frequency is lower than a predetermined frequency. The read/write control timing generation circuit 20 may be controlled in this manner. Here, the increased read window width (increase in read window time) is greater than the decreased read window width.

When the read/write control timing generation circuit 20 enlarges the read window when read data cannot pass through the read window, the calibration verification circuit 10 reduces the write window if the operating frequency is lower than a predetermined frequency. The read/write control timing generation circuit 20 may be controlled in this manner. In the current clock cycle, write data can pass through the write window, but read data cannot pass through the read window. Therefore, if increasing the read window causes the operating frequency to be lower than a predetermined frequency, decreasing the write window will reduce the probability that the read data will still not be able to pass through the read window after increasing the read window. can do.

If the read/write control timing generation circuit 20 enlarges the read window when the read data cannot pass through the read window, the calibration verification circuit 10 enlarges the read window and the write window if the operating frequency is lower than the predetermined frequency. The read/write control timing generation circuit 20 may be controlled so as to make the value smaller. Here, the width of the enlarged read window is greater than the width of the reduced read window.

When the read/write control timing generation circuit 20 enlarges the write window when write data cannot pass through the write window, the calibration verification circuit 10 reduces the write window when the operating frequency is lower than a predetermined frequency. The read/write control timing generation circuit 20 may be controlled in this way. Here, the width of the increased light window (increase in time of the light window) is greater than the width of the decreased light window.

If the read/write control timing generation circuit 20 enlarges the write window when write data cannot pass through the write window, the calibration verification circuit 10 reduces the read window if the operating frequency is lower than a predetermined frequency. The read/write control timing generation circuit 20 may be controlled in this way. In the current clock cycle, read data can pass through the read window, but write data cannot pass through the write window. Therefore, if increasing the write window causes the operating frequency to be lower than a predetermined frequency, decreasing the read window will reduce the probability that the write data will still not be able to pass through the write window after increasing the write window. can do.

If the write data cannot pass through the write window, the read/write control timing generation circuit 20 enlarges the write window, and if the operating frequency is lower than a predetermined frequency, the calibration verification circuit 10 enlarges the read window and the write window. The read/write control timing generation circuit 20 may be controlled to reduce the timing. Here, the width of the enlarged light window is greater than the width of the reduced light window.

In embodiments, read window and write window adjustment steps may be pre-stored, each step corresponding to increasing or decreasing a certain width.

For example, if the adjustment stage is encoded in 3-bit binary, and the read window adjustment stage is denoted by RD_Pn and the write window adjustment stage is denoted by WR_Pn, WR_P0 and RD_P0 are 000, and WR_P1 and RD_P1 are 001. , WR_P2 and RD_P2 are 010, WR_P3 and RD_P3 are 011, WR_P4 and RD_P4 are 100, WR_P5 and RD_P5 are 101, WR_P6 and RD_P6 are 110, and WR_P7 and RD_P7 are 111. The operating frequencies (in MHz) corresponding to the read window adjustment stage and the write window adjustment stage are shown in the table below.

When adjusting the read window or write window, the read/write control timing generation circuit 20 can increase or decrease the read window or the write window by one or more adjustment steps at a time. Of course, the adjustment stage of adjusting the read window and the write window may be binary encoded with other bits, and the adjustment stage may be divided into more or fewer stages, and the present invention Not particularly limited.

In embodiments, only one step at a time may be adjusted when increasing the read window and/or write window to prevent the operating frequency from being too low to meet normal operating requirements. can. For example, the initial stage corresponding to the read window in the current clock cycle is RD_P4. When increasing the read window, the read window can first be adjusted to the timing corresponding to RD_P5. If the read window is RD_P5, the read window is adjusted to RD_P6 when the read data still cannot pass through the read window.

In embodiments, the above-mentioned solution first increases the read window and then decreases the read window because the operating frequency is lower than a predetermined frequency, or first increases the write window and then decreases the operating frequency. Since it is smaller than a predetermined frequency, it includes making the light window smaller. In this case, the number of steps adjusted when enlarging the read window or write window is greater than the number of steps adjusted when making the read window or write window smaller.

Exemplarily, the initial stage corresponding to the read window in the current clock period is RD_P0, when increasing the read window, the read window can be adjusted to RD_P2 first, and then when decreasing the read window, The read window can be adjusted from RD_P2 to RD_P1.

In the embodiment, the predetermined frequency may be a frequency of the read/write window calibration circuit 100 set by the user as necessary. When the read/write window calibration circuit 100 is applied to an FPGA chip, the predetermined frequency may be a frequency of the FPGA chip set by the user as necessary.

In the embodiment, when the read/write control timing generation circuit 20 enlarges the read window, enlarges the write window, makes the read window smaller, or makes the write window smaller, the actual timing of the read window or the write window It is to change.

In embodiments, the read/write window calibration circuit 100 may calibrate the read and write windows one or more times until a calibration success or calibration error is output.

In embodiments, before first calibrating the read window and write window, the initial read window adjustment stage may be a non-minimum stage, that is, non-RD_P0, and the initial write window adjustment stage may be a non-minimum stage. , that is, it may be non-WR_P0.

Illustratively, the initial read window adjustment stage and the initial write window adjustment stage may be maximum adjustment stages. If the adjustment stage of the initial read window and initial write window is at the maximum stage, output a calibration error if the read data still cannot pass through the read window and/or the write data cannot pass through the write window yet. do.

In the embodiment, the fact that the read data cannot pass through the read window means that all of the read data cannot pass through the read window, or that some of the read data cannot pass through the read window.

The fact that the write data cannot pass through the light window means that all of the write data cannot pass through the write window, or that some of the write data cannot pass through the light window.

Embodiments of the present invention provide a read/write window calibration circuit 100, which includes a calibration verification circuit 10 and a read/write control timing generation circuit 20. The calibration verification circuit 10 is used to verify whether read data can pass through the read window and whether write data can pass through the write window. If so, increase the read window so that the read data passes through the read window as much as possible, and if the write data cannot pass through the write window, increase the write window and make sure that the write data passes through the write window as much as possible. Since the read window and/or the write window are made larger, the operating frequency of the read/write window calibration circuit 100 becomes smaller, and when the operating frequency is lower than a predetermined frequency, the read window and/or the write window are Or, by appropriately reducing the write window, read data can pass through the read window, write data can pass through the write window, and the operating frequency satisfies a predetermined frequency to calibrate the read/write window. Circuit 100 can read/write data at normal operating frequencies. The above process can be completed autonomously by the read/write window calibration circuit 100, which is convenient and reliable, and can improve the user experience.

Optionally, as shown in FIG. 2, the calibration verification circuit 10 determines whether read data can pass through the read window in the next clock cycle if the operating frequency is equal to or higher than a predetermined frequency; It is configured to iteratively verify whether the write data can pass through the light window.

In other words, the read window and/or write window has been enlarged, but after enlarging the read window and/or write window, it is difficult to determine whether read data can pass through the read window and whether write data can pass through the write window. Therefore, even if the operating frequency of the read/write window calibration circuit 100 satisfies the predetermined frequency, it cannot be determined whether the read data can pass through the read window and whether the write data It may be possible to re-verify whether or not it is possible to pass through the light window.

Optionally, as shown in FIG. 4, when the calibration verification circuit 10 verifies that the read data cannot pass through the read window in the current clock period, it , the read/write control timing generation circuit 20 is configured to determine whether or not the read window has been reduced.

The calibration verification circuit 10 causes the read/write control timing generation circuit 20 to enlarge the read window when the read/write control timing generation circuit 20 has not made the read window smaller in a clock cycle before the current clock cycle. configured to control.

The calibration verification circuit 10 is configured to output a calibration error when the read/write control timing generation circuit 20 reduces the read window in a clock cycle earlier than the current clock cycle.

Specifically, when the read/write control timing generation circuit 20 does not reduce the read window in a clock cycle before the current clock cycle, the operating frequency is set to a predetermined value in a clock cycle before the current clock cycle. meets the frequency. In this case, when the read data cannot pass through the read window, the read window is enlarged so that the read data can pass through the read window. Otherwise, the read window may have been made smaller because the operating frequency was lower than the predetermined frequency in a clock cycle before the current clock cycle. In this case, even if the read window is enlarged, the operating frequency may become lower than the predetermined frequency again because the read window has become larger. Therefore, there is no need to enlarge the read window, calibration errors can be directly output, and logic steps can be simplified.

Optionally, when the calibration verification circuit 10 verifies that the write data cannot pass through the write window in the current clock period, the calibration verification circuit 10 adjusts the read/write control timing generation circuit in a clock period earlier than the current clock period. 20 is configured to determine whether the light window has been reduced.

The calibration verification circuit 10 causes the read/write control timing generation circuit 20 to enlarge the write window when the read/write control timing generation circuit 20 has not made the write window smaller in a clock cycle before the current clock cycle. configured to control.

The calibration verification circuit 10 is configured to output a calibration error when the read/write control timing generation circuit reduces the write window in a clock cycle earlier than the current clock cycle. Specifically, when the read/write control timing generation circuit 20 does not reduce the read window in a clock cycle before the current clock cycle, the operating frequency is set to a predetermined value in a clock cycle before the current clock cycle. meets the frequency. In this case, when the write data cannot pass through the write window, the write window is enlarged so that the write data can pass through the light window. Otherwise, the write window may have been made smaller because the operating frequency was lower than the predetermined frequency in a clock cycle before the current clock cycle. In this case, even if the write window is enlarged, the operating frequency may become lower than the predetermined frequency again because the write window has become larger. Therefore, there is no need to enlarge the write window, calibration errors can be directly output, and logic steps can be simplified.

In an embodiment of the present invention, when it is verified that the read data cannot pass through the read window and the write data cannot pass through the write window, the read It may be determined first whether the window or light window has been made smaller. When the read window or write window is not made small, the operating frequency satisfies the predetermined frequency. Enlarge the read window or write window to allow read data or write data to pass through. When the read window or write window is made smaller, the operating frequency is smaller than the predetermined frequency in a clock cycle before the current clock cycle, so the read window or write window is made smaller. In this case, even if the write window is enlarged, the operating frequency may become lower than the predetermined frequency again because the read window or write window has become larger. Therefore, there is no need to enlarge the read window or write window, the calibration error can be directly output, and the logic steps can be simplified.

Optionally, as shown in FIG. 5, when the operating frequency is lower than a predetermined frequency, the read/write control timing generation circuit 20 performs a read window in a clock cycle earlier than the current clock cycle. and configured to determine whether to enlarge the light window.

The calibration verification circuit 10 determines whether it is possible to make the read window and/or the write window smaller when neither the read window nor the write window is made larger in the clock cycle before the current clock cycle. configured to determine.

The calibration verification circuit 10 is configured to control the read/write control timing generation circuit to reduce the read window and/or write window if it is possible to make the read window and/or write window smaller.

The calibration verification circuit 10 is configured to output a calibration error when the read/write control timing generation circuit enlarges the read window and write window in a clock cycle earlier than the current clock cycle.

Specifically, when the operating frequency is lower than the predetermined frequency, the calibration verification circuit 10 receives the Freq_overflow signal that is at a high level. Then, the calibration verification circuit 10 determines whether both the read window and the write window have been increased in a clock cycle before the current clock cycle.

When both the read window and write window are enlarged in a clock cycle before the current clock cycle, read data cannot pass through the read window in the previous clock cycle, and write data passes through the write window. Therefore, the read window and write window are both made larger. In this case, in the current clock cycle, when the read window and/or the write window are further made smaller, the read data cannot pass through the read window and/or the write data cannot pass through the write window again. there is a possibility. Therefore, it directly outputs the calibration error and does not further reduce the read window and/or write window.

If neither the read window nor the write window has been increased in a clock period before the current clock period, the operating frequency can be increased by at least decreasing the read window or the write window in the current clock period. There is. Therefore, the calibration verification circuit 10 can determine whether it is possible to make the read window and/or write window smaller. When it is possible to make the read window and/or the write window smaller, the calibration verification circuit 10 controls the read/write control timing generation circuit 20 to make the read window and/or the write window smaller; Outputs a calibration error when it is impossible to make the light window smaller.

In the embodiment, the fact that neither the read window nor the write window is increased in a clock period earlier than the current clock period means that the read window is increased in a clock period earlier than the current clock period; The write window has not been increased, or the write window has been increased but the read window has not been increased in a clock period earlier than the current clock period, or the read window has not been increased in a clock period earlier than the current clock period. This includes not increasing both the read window and the write window in the cycle.

In an embodiment of the present invention, when it is determined that the operating frequency is lower than a predetermined frequency, it is first determined whether both the read window and the write window were increased in a clock cycle before the current clock cycle. You can. When both the read window and the write window are made large, calibration errors can be output directly, simplifying the logic steps. When neither the read window nor the write window is enlarged, it may be determined whether to further reduce the read window and/or the write window. If so, the read window and/or write window can be made smaller, otherwise a calibration error can be output and the logic steps can be simplified.

Optionally, as shown in FIGS. 1 and 6, the read/write window calibration circuit 100 further includes an environmental monitoring circuit 40. The environmental monitoring circuit 40 is configured to acquire an environmental monitoring signal and transmit the environmental monitoring signal to the calibration verification circuit 10 if the environmental monitoring signal does not satisfy a predetermined signal. The calibration verification circuit 10 receives the environmental monitoring signal and verifies whether read data can pass through the read window and whether write data can pass through the write window in a new clock cycle. configured to do so.

In embodiments, the environmental monitoring signal may be the temperature, voltage, etc. of the current operating environment of the read/write window calibration circuit 100. The predetermined signals may be a corresponding predetermined temperature and a predetermined voltage.

If the temperature of the current operating environment does not meet the predetermined temperature and/or if the voltage of the current operating environment does not meet the predetermined voltage, an environmental monitoring signal may be sent to the calibration verification circuit 10. Then, the calibration verification circuit 10 is used to verify whether the read data can pass through the read window and whether the write data can pass through the write window. Can be adjusted.

Here, the predetermined temperature may have a constant predetermined temperature range. The fact that the temperature of the current operating environment does not meet the predetermined temperature includes that the temperature of the current operating environment exceeds the upper limit of the predetermined temperature range, or that the temperature of the current operating environment falls below the lower limit of the predetermined temperature range. .

The predetermined voltage may have a constant predetermined voltage range. The fact that the voltage of the current operating environment does not meet the predetermined voltage includes that the voltage of the current operating environment is greater than the upper limit of the predetermined voltage range, or that the voltage of the current operating environment is less than the lower limit of the predetermined voltage range. .

In embodiments, the failure of the environmental monitoring signal to meet the predetermined signal may mean that the difference between the current operating environment temperature and the previous measured environment temperature exceeds the predetermined signal; It may be that the difference between the voltage and the previously measured environmental voltage exceeds a predetermined signal.

In this case, the environment monitoring circuit 40 may include a temperature detection circuit, a voltage detection circuit, and a comparator. The temperature detection circuit is used to detect the temperature of the current operating environment. The voltage detection circuit is used to detect the voltage of the current environment. The comparator is used to compare the current operating environment temperature and the previously measured environmental temperature, and if the difference between the two is greater than a predetermined signal, the environmental monitoring signal does not meet the predetermined signal, or the comparator , is used to compare the current operating environment voltage and the previously measured environmental voltage, and if the difference between the two is greater than the predetermined signal, the environmental monitoring signal does not meet the predetermined signal.

In embodiments of the present invention, when factors such as temperature and voltage of the current operating environment of the read/write window calibration circuit 100 change, it may affect the timing of the read window and the write window, or the transmission of read data or write data. may affect. Therefore, if the environmental monitoring signal does not satisfy the predetermined signal, the environmental monitoring signal is sent to the calibration verification circuit 10, and the calibration verification circuit 10 is used to determine whether or not the read data can pass through the read window, and to determine whether or not the read data can pass through the read window. It may be verified whether data can pass through the write window, and the read window or write window may be adjusted.

Optionally, as shown in FIG. 1, the read/write window calibration circuit further includes a user calibration circuit. The user calibration circuit is configured to send a user calibration signal to the read/write control timing generation circuit 20. The read/write control timing generation circuit 20 is configured to receive a user calibration signal and adjust the read window and/or write window based on the user calibration signal.

Specifically, the above embodiment describes an embodiment in which the read/write window calibration circuit 100 adjusts the read window and the write window spontaneously, but in the embodiment of the present invention, the user further manually adjusts the read/write window. Windows and light windows may be adjusted. The user sends user calibration signals User_adjust_en and User_adjust_wrrd to the read/write control timing generation circuit 20 by triggering the user calibration circuit. When the user calibration signals User_adjust_en and User_adjust_wrrd are at high level, the read/write control timing generation circuit 20 starts operating and adjusts the read window and/or the write window based on User_adjust_wrrd.

Here, the user calibration signal User_adjust_wrrd includes increasing the read window, increasing the write window, decreasing the read window, and decreasing the write window.

In the embodiment, the read/write control timing is generated so that the user sends a user calibration signal to the read/write control timing generation circuit 20 via the user calibration circuit, and the calibration verification circuit 10 also adjusts the read window and/or the write window. When controlling the circuit 20, the read/write control timing generation circuit 20 adjusts the read window and/or the write window based on the user calibration signal sent by the user calibration circuit, or the read/write control timing generation circuit 20 adjusts the read window and/or the write window based on the user calibration signal transmitted by the user calibration circuit. The read window and/or write window is adjusted based on the Adjust_en signal, the djust_rd signal, and the Adjust_wr signal sent by the calibration verification circuit 10.

In embodiments of the present invention, the user may also manually adjust the read window and/or write window based on his/her wishes.

Optionally, as shown in FIG. 1, the read/write window calibration circuit 100 may further include a read/write window configuration adjustment circuit 50 and a configuration memory 60.

The read/write window configuration adjustment circuit 50 adjusts the adjustment signal sent by the calibration verification circuit 10 when read data cannot pass through the read window and/or when write data cannot pass through the write window. is configured to receive, retrieve adjustment information based on the adjustment signal, and send the adjustment information to configuration memory 60 .

The configuration memory 60 is configured to receive adjustment information, retrieve configuration information corresponding to the adjustment information, and transmit the configuration information to the read/write control timing generation circuit 20.

The read/write control timing generation circuit 20 is configured to adjust the read window and/or the write window based on configuration information.

Specifically, when read data cannot pass through the read window and/or when write data cannot pass through the write window, the calibration verification circuit 10 uses the adjustment signal Adjust_en to adjust the read/write window configuration. to circuit 50. When the adjustment signal Adjust_en is at a high level, the read/write window configuration adjustment circuit 50 operates, reads adjustment information, and transmits the adjustment information to the configuration memory 60. After receiving the adjustment information, the configuration memory 60 calls up the configuration information corresponding to the adjustment information and transmits the configuration information to the read/write control timing generation circuit 20. The read/write control timing generation circuit 20 can adjust the read window and/or write window by adjusting the timing of the read window and/or write window based on the configuration information.

In an embodiment, the adjustment information may be the adjustment stage of the read window and the write window, for example, the adjustment stage corresponding to the initial adjustment information of the read window is RD_P0. After receiving the adjustment signal Adjust_en, the read/write window configuration adjustment circuit 50 determines the adjustment stage corresponding to the adjusted adjustment information as RD_P1.

The configuration information may be information for adjusting the timing of the read window and the write window, which corresponds to the adjustment information.

Here, the adjustment information may be stored in the read/write window configuration adjustment circuit 50 in advance, and the configuration information may be stored in the configuration memory 60 in advance.

In an embodiment of the present invention, when it is determined that read data cannot pass through the read window and/or write data cannot pass through the write window, the read/write window configuration adjustment circuit 50 adjusts the The read window and/or write window timing may be adjusted based on the configuration information by calling the adjustment information from the configuration memory 60 and using the read/write control timing generation circuit 20. .

As shown in FIG. 7, a memory 1000 is further provided according to an embodiment of the invention. Memory 1000 includes a plurality of storage units 200 and read/write window calibration circuit 100 described in any of the embodiments described above. The read/write window calibration circuit 100 is used to calibrate the read window and write window of the storage unit 200.

In the embodiment, a storage unit 200 corresponds to each read/write window calibration circuit 100. The single read/write window calibration circuit 100 is used to calibrate the read and write windows of a single storage unit.

In embodiments, as shown in FIG. 1, the storage unit 200 may include a read control circuit, a write control circuit, and a memory array.

When the word line between the read control circuit and the memory array is at a high level, the read control circuit conducts with the memory array, and the read control circuit stores read data in the memory array via the bit line. When the word line between the write control circuit and the memory array is at a high level, the write control circuit is electrically connected to the memory array, and the write control circuit stores write data in the memory array via the bit line.

When the word line between the memory array and the calibration verification circuit 10 is at a high level, the memory array calibrates the read data and write data stored via the bit line between the memory array and the calibration verification circuit 10. It is transmitted to the verification circuit 10. The calibration verification circuit 10 is used to verify whether read data can pass through a read window and whether write data can pass through a write window.

In embodiments, the memory may be Static Random-Access Memory (SRAM). The SRAM storage units 200 are programmable block memories (BRAM).

According to an embodiment of the invention, a memory 1000 is provided. For other explanations and beneficial effects, reference can be made to the above-mentioned embodiments, and the explanation will be omitted here.

As shown in FIG. 8, embodiments of the present invention may provide an FPGA chip 10000 that includes a memory 1000 as described in any of the previously described embodiments.

Based on this, the FPGA chip 10000 may further include a logic circuit 2000. Logic circuit 2000 can store data in memory 1000 and read data from memory 1000.

According to an embodiment of the invention, an FPGA chip 10000 is provided. For other explanations and beneficial effects, reference can be made to the above-mentioned embodiments, and the explanation will be omitted here.

As shown in FIG. 9, according to an embodiment of the present invention:
Step S110 in which the calibration verification circuit 10 verifies whether read data can pass through the read window and whether write data can pass through the write window in the current clock cycle;
If the read data cannot pass through the read window, the read/write control timing generation circuit 20 enlarges the read window in step S120;
If the write data cannot pass through the write window, the read/write control timing generation circuit 20 enlarges the write window in step S130;
The calibration verification circuit 10 acquires the operating frequency of the read/write window calibration circuit, and if the operating frequency is lower than a predetermined frequency, controls the read/write control timing generation circuit 20 to reduce the read window and/or the write window. , step S140 of repeatedly verifying whether read data can pass through the read window and whether write data can pass through the write window in the next clock cycle; A method is provided.

Based on this, in the case of step S120, step S140 may include controlling the read/write control timing generation circuit 20 to reduce the write window when the operating frequency is lower than the predetermined frequency.

In the case of step S130, step S140 may include controlling the read/write control timing generation circuit 20 to reduce the read window when the operating frequency is lower than the predetermined frequency.

If the operating frequency is equal to or higher than the predetermined frequency, after steps S120 and S130 are executed, the read/write window calibration method determines whether read data can pass through the read window in the next clock cycle; The method may further include the step of repeatedly verifying whether the write data can pass through the write window.

When it is verified that the read data cannot pass through the read window in the current clock period, after step S110 is executed and before steps S120 and S130, the read/write window calibration method includes: A step of determining whether or not the read/write control timing generation circuit 20 has made the read window smaller in a clock cycle before the current clock cycle; controlling the read/write control timing generation circuit 20 to enlarge the read window when the generation circuit 20 has not made the read window smaller; and generating read/write control timing in a clock cycle earlier than the current clock cycle; The method may further include outputting a calibration error when the circuit 20 reduces the read window.

When it is verified that the write data cannot pass through the write window in the current clock cycle, after step S110 is executed and before steps S120 and S130, the read/write window calibration method includes: A step in which the read/write control timing generation circuit 20 determines whether or not to reduce the write window in a clock cycle before the current clock cycle; controlling the read/write control timing generation circuit 20 to enlarge the write window when the generation circuit 20 has not made the write window smaller; and generating read/write control timing in a clock cycle earlier than the current clock cycle; The method may further include outputting a calibration error when the circuit 20 reduces the light window.

If the operating frequency is lower than the predetermined frequency, after steps S120 and S130 are performed and before step S140, the read/write window calibration method performs the following steps: The step of determining whether the read/write control timing generation circuit 20 has enlarged the read window and the write window, and the step of determining whether or not the read window and the write window have been enlarged in the clock cycle before the current clock cycle. , determining whether the read window and/or the write window can be made smaller; and if the read window and/or the write window can be made smaller, the read window and/or the write window are or controlling the read/write control timing generation circuit 20 to make the write smaller; and the read/write control timing generation circuit 20 enlarges the read window and the write window in a clock cycle earlier than the current clock cycle. The method may further include the step of outputting a calibration error.

After step S110 is executed and before steps S120 and S130, if the read data can pass through the read window and the write data can pass through the write window, a successful calibration is output.

For other explanations and beneficial effects of the embodiments of the present invention, reference can be made to the above-mentioned embodiments, and the description will be omitted here.

Finally, it should be noted that the above embodiments are used to explain the technical solution of the present invention, and are not intended to limit it, and although the present invention has been explained in detail with reference to the above embodiments, As a person skilled in the art will understand, it is still possible to modify the technical solutions described in each of the above-mentioned embodiments or to equivalently replace some technical features thereof, and these modifications or replacements does not cause the essence of the corresponding technical solution to depart from the spirit and scope of the technical solution of each embodiment of the present invention.

10000 FPGA chip 1000 Memory 100 Read/write window calibration circuit 10 Calibration verification circuit 20 Read/write control timing generation circuit 30 Status register 40 Environment monitoring circuit 50 Read/write window configuration adjustment circuit 60 Configuration memory 200 Storage unit

Claims (14)

A read/write window calibration circuit,
a calibration verification circuit configured to verify whether read data can pass through a read window and whether write data can pass through a write window in a current clock cycle;
a read/write control timing generation circuit configured to enlarge the read window when the read data cannot pass through the read window;
The read/write control timing generation circuit is configured to enlarge the write window when write data cannot pass through the write window,
The calibration verification circuit obtains the operating frequency of the read/write window calibration circuit, and when the operating frequency is lower than a predetermined frequency, generates the read/write control timing to reduce the read window and/or the write window. Controlling the circuit, and repeatedly verifying whether the read data can pass through the read window and whether the write data can pass through the write window in the next clock cycle. configured as,
It features a read/write window calibration circuit. When the read/write control timing generation circuit is configured to enlarge the read window when the read data cannot pass through the read window, the calibration verification circuit is configured to increase the operating frequency to a predetermined frequency. If the write window is smaller than , the read/write control timing generation circuit is controlled to reduce the write window.
2. The read/write window calibration circuit according to claim 1. When the read/write control timing generation circuit is configured to enlarge the write window when the write data cannot pass through the write window, the calibration verification circuit is configured to increase the operating frequency to a predetermined frequency. If the read window is smaller than , the read/write control timing generation circuit is controlled to reduce the read window.
2. The read/write window calibration circuit according to claim 1. The calibration verification circuit determines whether read data can pass through a read window and whether write data can pass through a write window in the next clock cycle when the operating frequency is equal to or higher than the predetermined frequency. configured to repeatedly verify whether or not
2. The read/write window calibration circuit according to claim 1. The calibration verification circuit includes:
When it is verified that the read data cannot pass through the read window in the current clock cycle, does the read/write control timing generation circuit reduce the read window in a clock cycle earlier than the current clock cycle? decide whether or not to
In a clock cycle before the current clock cycle, when the read/write control timing generation circuit has not made the read window smaller, controlling the read/write control timing generation circuit to enlarge the read window;
configured to output a calibration error when the read/write control timing generation circuit reduces the read window in a clock cycle earlier than the current clock cycle;
2. The read/write window calibration circuit according to claim 1. The calibration verification circuit includes:
When it is verified that the write data cannot pass through the write window in the current clock cycle, does the read/write control timing generation circuit reduce the write window in a clock cycle earlier than the current clock cycle? decide whether or not to
When the read/write control timing generation circuit has not made the write window smaller in a clock cycle earlier than the current clock cycle, the read/write control timing generation circuit is controlled to enlarge the write window. configured,
configured to output a calibration error when the read/write control timing generation circuit reduces the write window in a clock cycle earlier than the current clock cycle;
2. The read/write window calibration circuit according to claim 1. The calibration verification circuit includes:
If the operating frequency is lower than a predetermined frequency, determining whether the read/write control timing generation circuit enlarges the read window and the write window in a clock cycle earlier than the current clock cycle;
When neither the read window nor the write window has been enlarged in a clock cycle before the current clock cycle, determine whether it is possible to make the read window and/or the write window smaller. configured to
If the read window and/or the write window can be made smaller, the read/write control timing generation circuit is configured to be controlled to make the read window and/or the write smaller;
configured to output a calibration error when the read/write control timing generation circuit enlarges the read window and the write window in a clock cycle earlier than the current clock cycle;
2. The read/write window calibration circuit according to claim 1. The calibration verification circuit is configured to output a calibration success when the read data can pass through the read window and the write data can pass through the write window.
2. The read/write window calibration circuit according to claim 1. further comprising an environmental monitoring circuit configured to obtain an environmental monitoring signal and send an environmental monitoring signal to the calibration verification circuit if the environmental monitoring signal does not meet a predetermined signal;
The calibration verification circuit receives the environmental monitoring signal and determines whether read data can pass through the read window and whether write data can pass through the write window in a new clock cycle. configured to verify,
The read/write window calibration circuit according to any one of claims 1 to 8. further comprising a user calibration circuit configured to send a user calibration signal to the read/write control timing generation circuit;
The read/write control timing generation circuit is configured to receive the user calibration signal and adjust the read window and/or the write window based on the user calibration signal.
The read/write window calibration circuit according to any one of claims 1 to 8. further including a read/write window configuration adjustment circuit and a configuration memory;
The read/write window configuration adjustment circuit is configured to adjust the read/write window configuration adjustment circuit to determine whether the read data is transmitted by the calibration verification circuit when the read data cannot pass through the read window, and/or when the write data cannot pass through the write window. configured to receive an adjustment signal, retrieve adjustment information based on the adjustment signal, and send the adjustment information to the configuration memory;
The configuration memory is configured to receive the adjustment information, recall configuration information corresponding to the adjustment information, and send the configuration information to the read/write control timing generation circuit,
The read/write control timing generation circuit is configured to adjust the read window and/or the write window based on the configuration information.
The read/write window calibration circuit according to any one of claims 1 to 8. comprising a plurality of storage units and a read/write window calibration circuit according to any one of claims 1 to 11 for calibrating read windows and write windows of the storage units;
It is characterized by memory. comprising a memory according to claim 12;
FPGA chip with this feature. A read/write window calibration method, comprising:
The calibration verification circuit verifies whether the read data can pass through the read window and whether the write data can pass through the write window in the current clock cycle;
If the read data cannot pass through the read window, a read/write control timing generation circuit enlarges the read window;
If the write data cannot pass through the write window, the read/write control timing generation circuit enlarges the write window;
The calibration verification circuit obtains the operating frequency of the read/write window calibration circuit, and if the operating frequency is smaller than a predetermined frequency, the read/write control timing generation circuit is configured to reduce the read window and/or the write window. and repeatedly verifying whether the read data can pass through the read window and whether the write data can pass through the write window in the next clock cycle. A read/write window calibration method comprising:

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