WO2022138050A1 - Radiation detection sensor and radiation image detector - Google Patents

Abstract

In this invention, a semiconductor sensor 1 comprises an n-type semiconductor substrate 2 and an n-type semiconductor layer 3 that is formed on the semiconductor substrate 2, and a plurality of pillars 5 are formed on the semiconductor layer 3. Electrodes 7 are formed on the upper surfaces of each pillar 5, and a rear surface electrode 8 is formed on the rear surface of the semiconductor substrate 2. The electrodes 7 are separated from each other. Each pillar 5 has a p-n junction or Schottky junction on the upper and lateral surfaces thereof.

Description

Radiation detection sensor and radiation image detector

The present invention relates to a radiation detection sensor and a radiation image detector, for example, a semiconductor sensor for radiation detection and a radiation detector using the same.

As a radiation detection sensor for detecting radiation, a semiconductor sensor (semiconductor detector) using a semiconductor is known. Radiation can be detected by generating an electric charge when radiation passes through the semiconductor sensor and converting it into an electrical signal.

As a background technique in this technical field, for example, there is Non-Patent Document 1. Non-Patent Document 1 describes a technique for separately manufacturing a sensor for radiation detection and a reading chip and joining them by using a bump technique.

Patent Document 1 describes a technique related to a photodiode of a CMOS image sensor. Patent Document 2 describes a technique relating to a Schottky barrier diode. Patent Document 3 describes a technique relating to a neutron detector.

Japanese Unexamined Patent Publication No. 2000-31455 JP-A-2017-201724 US Pat. No. 8,787,715

The present inventor is studying a semiconductor sensor for radiation detection. The semiconductor sensor has a PN junction or a Schottky junction. Radiation can be detected by enlarging the depletion layer in the semiconductor sensor by applying a voltage, generating an electric charge by passing the radiation through the depletion layer, and detecting the electric charge. When the voltage for depleting a semiconductor sensor is high, a high voltage power supply for applying a high voltage is required. This is not desirable as it increases the overall cost. On the other hand, if the depletion of the semiconductor sensor is insufficient, the detection sensitivity of the radiation passing through the semiconductor sensor will decrease. Therefore, in order to improve the performance of the semiconductor sensor, a technique capable of efficiently depleting the semiconductor sensor even at a low voltage is desired.

Other issues and new features will become apparent from the description and accompanying drawings herein.

According to one embodiment, the radiation detection sensor is provided in a first conductive type semiconductor substrate, a plurality of pillars provided on the semiconductor substrate, each having an upper flat surface and a side surface, and each of the plurality of pillars. It includes a PN junction or a Schottky junction provided on the upper flat surface and the side surface. The radiation detection sensor is a plurality of first electrodes each formed on the upper flat surface of the plurality of pillars, the plurality of first electrodes separated from each other, and the plurality of the semiconductor substrate. A second electrode provided on the main surface opposite to the side on which the pillar is formed is provided.

According to one embodiment, the performance of the radiation detection sensor can be improved.

It is a main part plan view of the semiconductor sensor of one Embodiment. It is sectional drawing of the main part of the semiconductor sensor of one Embodiment. It is sectional drawing of the main part of the semiconductor sensor of one Embodiment. It is sectional drawing of the main part of the radiation detector of one Embodiment. It is sectional drawing in the manufacturing process of the semiconductor sensor of one Embodiment. It is sectional drawing in the manufacturing process of the semiconductor sensor following FIG. It is sectional drawing in the manufacturing process of the semiconductor sensor following FIG. It is sectional drawing in the manufacturing process of the semiconductor sensor following FIG. It is sectional drawing in the manufacturing process of the semiconductor sensor following FIG. It is sectional drawing in the manufacturing process of the semiconductor sensor following FIG. It is sectional drawing of the main part of the semiconductor sensor of the study example. It is sectional drawing of the main part of the semiconductor sensor of the 1st modification. It is sectional drawing of the main part of the semiconductor sensor of the 2nd modification. It is a main part plan view of the semiconductor sensor of the 3rd modification. It is sectional drawing of the main part of the semiconductor sensor of the 3rd modification. It is sectional drawing of the main part of the semiconductor sensor of another embodiment. It is sectional drawing of the main part of the semiconductor sensor of the 4th modification.

Hereinafter, embodiments will be described in detail based on the drawings. In all the drawings for explaining the embodiment, the members having the same function are designated by the same reference numerals, and the repeated description thereof will be omitted. Further, in the following embodiments, the same or similar parts will not be repeated in principle unless it is particularly necessary.

(Embodiment 1)
<About semiconductor sensors>
A semiconductor sensor according to an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a plan view of a main part of the semiconductor sensor 1 according to the embodiment of the present invention, and FIGS. 2 and 3 are cross-sectional views of the main part of the semiconductor sensor 1. The cross-sectional view at the position of line A1-A1 in FIG. 1 substantially corresponds to FIG. 2, and the cross-sectional view at the position of line A2-A2 in FIG. 1 substantially corresponds to FIG. Since the cross-sectional view at the position of line A3-A3 in FIG. 1 is the same as that of FIG. 2, the illustration is omitted here, and the cross-sectional view at the position of line A4-A4 in FIG. 1 is shown in FIG. Since it is the same as the above, the illustration is omitted here. FIG. 1 is a plan view of the semiconductor sensor 1 as viewed from above, through which the insulating film 9 is seen through, and the electrode 7 is shown by a dotted line.

The semiconductor sensor 1 of the present embodiment is a semiconductor sensor (semiconductor detector) for radiation detection, and is therefore a radiation detection sensor.

As shown in FIGS. 1 to 3, the semiconductor sensor 1 of the present embodiment, which is a radiation detection sensor, has a semiconductor substrate 2 and a semiconductor layer 3 formed on the semiconductor substrate 2. The semiconductor substrate 2 is an n-type semiconductor substrate into which n-type impurities have been introduced. As the semiconductor substrate 2, it is more preferable to use a SiC substrate made of single crystal SiC (silicon carbide). The semiconductor layer 3 is an epitaxial semiconductor layer formed by epitaxial growth on the main surface (upper surface) 2a of the semiconductor substrate 2, and is an n-type semiconductor layer into which n-type impurities are introduced. The semiconductor layer 3 is made of the same material as the semiconductor substrate 2, and when a SiC substrate is used as the semiconductor substrate 2, the semiconductor layer 3 is a SiC layer made of single crystal SiC (silicon carbide). The impurity concentration (n-type impurity concentration) of the semiconductor layer 3 is preferably lower than the impurity concentration (n-type impurity concentration) of the semiconductor substrate 2. A combination of the semiconductor substrate 2 and the semiconductor layer 3 on the semiconductor substrate 2 can also be regarded as a semiconductor substrate. Although not particularly limited, the impurity concentration of the SiC semiconductor substrate 2 is about 1X10 ^ 17 to 1X10 ^ 20 (cm ^ -3), and the impurity concentration of the SiC semiconductor layer 3 is 1X10 ^ 13 to 1X10 ^ 16 (cm ^ -3). ) Degree is assumed.

A groove (trench) 4 is formed in the semiconductor layer 3. Since the groove 4 is formed in the semiconductor layer 3, a plurality of pillars (columnar portions, convex portions) 5 are formed in the semiconductor layer 3. The groove 4 is a groove for partitioning a plurality of pillars 5. That is, the semiconductor layer 3 is divided into a plurality of pillars 5 by the grooves 4, and the grooves 4 exist between the adjacent pillars 5. The pillar 5 is a columnar convex portion and projects in a direction substantially perpendicular to the main surface 2a of the semiconductor substrate 2.

In the case of FIG. 1, the grooves 4 are formed in a grid pattern extending in the X direction and the Y direction in a plan view. Here, the X direction and the Y direction are directions substantially parallel to the main surface 2a or the back surface 2b of the semiconductor substrate 2, and the X direction and the Y direction intersect each other (more specifically, orthogonal to each other). Direction). Further, the plan view corresponds to the case where the semiconductor substrate 2 is viewed in a plane substantially parallel to the main surface 2a or the back surface 2b. In FIG. 1, the pillars 5 are not particularly limited, but are arranged in the X direction and the Y direction with the same repetition period (same pitch), and are isotropic with respect to the X direction and the Y direction. Of course, the period for arranging the pillars 5 may be slightly different between the X direction and the Y direction.

In the case of FIG. 1, the planar shape of the pillar 5 is a square shape (more specifically, a rectangular shape or a square shape). When the planar shape of the pillar 5 is a square shape, the three-dimensional shape of the pillar 5 is a square columnar shape. The planar shape of the pillar 5 may be other than a square shape, and may be, for example, a circular shape. When the planar shape of the pillar 5 is circular, the three-dimensional shape of the pillar 5 is cylindrical. Further, the three-dimensional shape of the pillar 5 may have a tapered shape (tapered shape). Here, the planar shape corresponds to the shape in a planar view.

Each pillar 5 is a part of the semiconductor layer 3, and the pillars 5 are separated (separated) by a groove 4. The bottom surface of the groove 4 is located in the middle of the thickness of the semiconductor layer 3. Therefore, the semiconductor layer 3 also exists under the bottom surface of the groove 4, and the plurality of pillars 5 are connected by the lower layer portion of the semiconductor layer 3. As another form, the groove 4 may reach the semiconductor substrate 2, but in that case, a plurality of pillars 5 are directly arranged on the main surface of the semiconductor substrate 2.

Each pillar 5 has an upper surface (upper flat surface) and a side surface. The upper surface of the pillar 5 corresponds to the upper flat surface (tip surface) of the pillar 5.

A p-type semiconductor region (p-type semiconductor layer) 6 is formed on the upper surface and the side surface of each pillar 5. That is, in each pillar 5, the p-type semiconductor region 6 is formed over the upper surface and the side surface. That is, the p-type semiconductor region 6 is formed on the surface layer portions on the upper surface and the side surface of each pillar 5.

Here, a portion of the p-type semiconductor region 6 formed on the upper surface (surface layer portion) of each pillar 5 is referred to as a p-type semiconductor region 6a, and the side surface of each pillar 5 in the p-type semiconductor region 6 is referred to as a p-type semiconductor region 6a. The portion formed in (the surface layer portion of) is referred to as a p-type semiconductor region 6b. The p-type semiconductor region 6a and the p-type semiconductor region 6b are connected as a p-type region semiconductor region and are electrically connected. The p-type semiconductor region 6a and the p-type semiconductor region 6b may have the same or different impurity concentrations (p-type impurity concentrations). Further, the p-type semiconductor region 6a and the p-type semiconductor region 6b may be formed in the same step or may be formed in different steps. Further, the side surface of each pillar may be completely covered by the p-type semiconductor region 6b, or a part thereof may be covered. Further, when the p-type semiconductor region 6a has a higher impurity concentration than the p-type semiconductor region 6b, it is easy to reduce the contact resistance between the electrode 7 and the p-type semiconductor region 6a.

Further, in the semiconductor layer 3, the region that is not the p-type semiconductor region 6 (the region that maintains the n-type) is referred to as the n-type semiconductor region 3a. In each pillar 5, the surface layer portions on the upper surface and the side surface are composed of the p-type semiconductor region 6, and the other pillars 5 are configured by the n-type semiconductor region 3a. Therefore, in each pillar 5, the p-type semiconductor region 6 is adjacent to the n-type semiconductor region 3a, and a PN junction is formed between the p-type semiconductor region 6 and the n-type semiconductor region 3a (interface). .. Since the p-type semiconductor region 6 is thin and the pillar 5 is mainly formed by the n-type semiconductor region 3a, the p-type semiconductor region 6 is formed on the upper surface and the side surface of the n-type semiconductor region 3a constituting the pillar 5. It can also be considered to be.

In the present embodiment, the p-type semiconductor region 6 is not formed in the semiconductor layer 3 between the adjacent pillars 5, that is, at the bottom of the groove 4. Therefore, the p-type semiconductor region 6 formed on the upper surface and the side surface (surface layer portion) of a certain pillar 5 and the p-type semiconductor region 6 formed on the upper surface and the side surface (surface layer portion) of the pillar 5 adjacent to the pillar 5 are formed. The type semiconductor region 6 is not connected to each other, but is separated from each other via the n-type semiconductor region 3a. That is, the p-type semiconductor region 6 formed in each pillar 5 is not connected to the p-type semiconductor region 6 formed in the other pillars 5, and is separated via the n-type semiconductor region 3a. ..

Electrodes 7 are formed on the upper surface of each pillar 5. Therefore, the electrode 7 is formed on the p-type semiconductor region 6 (more specifically, on the p-type semiconductor region 6a), and is in contact with the p-type semiconductor region 6 and electrically connected to the p-type semiconductor region 6. Has been done. The electrode 7 is preferably ohmic-connected to the p-type semiconductor region 6.

The electrode 7 is made of a metal material, for example, a laminated film of a titanium (Ti) layer and an aluminum (Al) layer on the titanium layer. The electrode 7 formed on the upper surface of each pillar 5 and the electrode 7 formed on the upper surface of the other pillar 5 are not connected and are separated from each other. That is, independent electrodes 7 are provided for each pillar 5, and the electrodes 7 are separated from each other.

A back surface electrode 8 is formed as an electrode on the back surface (main surface) 2b of the semiconductor substrate 2. The back surface electrode 8 is formed over almost the entire back surface 2b of the semiconductor substrate 2. The back surface electrode 8 is electrically connected to the semiconductor substrate 2. The back surface electrode 8 is ohmic contacted with the semiconductor substrate 2. As another form, the back surface electrode 8 and the semiconductor substrate 2 may be shotki-connected. The back surface electrode 8 is made of a metal material, for example, a laminated film of a nickel (Ni) layer and a titanium (Ti) layer on the nickel layer.

Here, the back surface 2b of the semiconductor substrate 2 corresponds to the main surface on the side opposite to the main surface 2a on the side where the semiconductor layer 3 is formed, out of the two main surfaces located on opposite sides of the semiconductor substrate 2. is doing. The semiconductor layer 3 is formed on the main surface 2a of the semiconductor substrate 2, which is one of the two main surfaces of the semiconductor substrate 2. The main surface 2a and the back surface 2b of the semiconductor substrate 2 are located on opposite sides of each other.

The semiconductor sensor 1 of the present embodiment further has an insulating film 9 that fills the space between the plurality of pillars 5. The groove 4 is embedded by the insulating film 9. That is, the insulating film 9 is formed on the semiconductor substrate 2 (semiconductor layer 3) so as to fill the groove 4. The insulating film 9 is made of, for example, a resin film (such as a polyimide resin film). The insulating film 9 may be a single-layer insulating film or a laminated insulating film in which a plurality of insulating films are laminated. For example, the insulating film 9 may be a laminated film of a thin silicon oxide film and a thick resin film on the thin silicon oxide film. The electrode 7 is not covered with the insulating film 9, but is exposed from the opening of the insulating film 9. The insulating film 9 can function as a protective film. The insulating film 9 is not electrically essential, but by providing the insulating film 9, a plurality of pillars 5 can be stabilized, and the semiconductor sensor 1 can be easily handled. Further, by providing the insulating film 9, the reliability of the semiconductor sensor 1 can be improved.

When detecting radiation using the semiconductor sensor 1, a predetermined voltage is applied between the back surface electrode 8 and the plurality of electrodes 7 in the semiconductor sensor 1. For example, a predetermined high potential is applied to the back surface electrode 8, and a predetermined low potential is applied to the plurality of electrodes 7. As a result, in each pillar 5, the depletion layer expands from the PN junction surface between the p-type semiconductor region 6 and the n-type semiconductor region 3a, and each pillar 5 is depleted. That is, the n-type semiconductor region 3a constituting each pillar 5 is depleted. In this state, when radiation is incident on the depletion layer (depleted pillar 5) of the semiconductor sensor 1, electrons and holes are generated by ionization. The generated electrons move to the back surface electrode 8, and the generated holes move to the electrode 7. As a result, a current flows between the electrode 7 of the semiconductor sensor 1 and the back electrode 8, so that the radiation incident on the semiconductor sensor 1 can be detected by detecting this current.

<About radiation detection device>
Next, a radiation detector (radiation image detector, semiconductor detector, radiation detector) 11 using the semiconductor sensor 1 will be described with reference to the drawings. FIG. 4 is a cross-sectional view of a main part of the radiation detector 11 of the present embodiment. The cross section of the semiconductor sensor 1 shown in FIG. 4 substantially corresponds to the cross section of the semiconductor sensor 1 shown in FIG.

The radiation detector 11 of the present embodiment includes the above-mentioned semiconductor sensor 1 and a semiconductor chip (semiconductor chip for reading) 12. The semiconductor chip 12 is mounted (arranged) on the semiconductor sensor 1.

The semiconductor chip 12 has a semiconductor substrate 12a and a multilayer wiring structure 12b formed on the semiconductor substrate 12a. A semiconductor element (not shown) such as a MISFET (Metal Insulator Semiconductor Field Effect Transistor) is formed on the semiconductor substrate 12a. The multilayer wiring structure 12b has a plurality of insulating films and a plurality of wiring layers. Various circuits can be formed by the semiconductor element formed on the semiconductor substrate 12a and the wiring included in the multilayer wiring structure 12b.

The semiconductor chip 12 is a semiconductor chip in which various circuits are formed, but includes a circuit for reading out a current generated by the incident of radiation by the semiconductor sensor 1. The semiconductor sensor 1 corresponds to a semiconductor chip for radiation detection, and the semiconductor chip 12 corresponds to a semiconductor chip for reading.

The semiconductor chip 12 has a plurality of electrodes (pad electrodes) 13 on its main surface. The plurality of electrodes 13 are electrically connected to a circuit formed in the semiconductor chip 12 through internal wiring (wiring included in the multilayer wiring structure 12b) of the semiconductor chip 12.

The plurality of electrodes 13 of the semiconductor chip 12 and the plurality of electrodes 7 of the semiconductor sensor 1 are bonded and electrically connected via bumps (bump electrodes) 14, respectively. That is, the plurality of electrodes 13 of the semiconductor chip 12 and the plurality of electrodes 7 of the semiconductor sensor 1 are bump-connected. The bump 14 is, for example, a solder bump or a gold bump.

The radiation detector 11 can be mounted on, for example, a wiring board (not shown), in which case the back electrode 8 of the semiconductor sensor 1 is electrically connected to the electrode of the wiring board or the like.

As described above, when radiation is incident on the depletion layer (depleted pillar 5) of the semiconductor sensor 1 constituting the radiation detector 11, electrons and holes are generated by ionization. The generated electrons move to the back surface electrode 8, and the generated holes move to the electrode 7. As a result, a current flows between the electrode 7 of the semiconductor sensor 1 and the back electrode 8. The electrons transferred to the electrode 7 can be conducted to the circuit in the semiconductor chip 12 via the bump 14 and the electrode 13 connected to the electrode 7. As a result, the current (charge) generated by the radiation incident on the semiconductor sensor 1 can be read out (detected) by the circuit in the semiconductor chip 12. By detecting which of the plurality of electrodes 7 of the semiconductor sensor 1 the current has flowed through the circuit in the semiconductor chip 12, which pillar 5 of the plurality of pillars 5 of the semiconductor sensor 1 has the current flowed. It is possible to detect whether or not radiation is incident, and it is possible to determine the intensity of radiation from the magnitude of the current. This makes it possible to detect (analyze) a two-dimensional distribution (two-dimensional image) of the position and intensity of the radiation incident on the semiconductor sensor 1. Therefore, the radiation detector 11 can be regarded as a radiation image detector. Each pillar 5 constitutes a pixel.

<Manufacturing method of semiconductor sensor>
Next, an example of the manufacturing method of the semiconductor sensor 1 of the present embodiment will be described with reference to FIGS. 5 to 10. 5 to 10 are cross-sectional views of the semiconductor sensor 1 of the present embodiment during the manufacturing process, and the cross-sectional views corresponding to FIG. 2 are shown.

First, as shown in FIG. 5, a semiconductor substrate 2 having a main surface (upper surface) 2a and a back surface (lower surface) 2b is prepared. At this stage, the semiconductor substrate 2 is not fragmented into chips and is in the state of a semiconductor wafer. The semiconductor substrate 2 is an n-type SiC (silicon carbide) substrate into which an n-type impurity such as nitrogen (N) has been introduced.

Next, as shown in FIG. 5, an n-type semiconductor layer 3 made of SiC (silicon carbide) is formed on the main surface 2a of the semiconductor substrate 2 by an epitaxial growth method. The impurity concentration of the semiconductor layer 3 can be lower than the impurity concentration of the semiconductor substrate 2. A SiC epitaxial substrate in which the semiconductor layer 3 is formed on the n-type semiconductor substrate 2 may be purchased in advance.

Next, as shown in FIG. 6, a groove 4 is formed in the semiconductor layer 3. The groove 4 can be formed by using, for example, a photolithography technique and an etching technique. By forming the groove 4 in the semiconductor layer 3, a plurality of pillars 5 are formed in the semiconductor layer 3.

Next, as shown in FIG. 7, the back surface electrode 8 is formed on the back surface 2b of the semiconductor substrate 2. The back surface electrode 8 can be formed by using, for example, a sputtering method. The timing for forming the back surface electrode 8 is arbitrary and can be changed as needed.

Next, as shown in FIG. 8, a p-type semiconductor region 6 is formed by introducing (injecting) a p-type impurity such as aluminum (Al) into the upper surface and the side surface of the pillar 5. The method for forming the p-type semiconductor region 6 is arbitrary, but for example, an ion implantation method can be used. For example, if oblique ion implantation is used, p-type impurities can be implanted not only on the upper surface of the pillar 5 but also on the side surface of the pillar 5. Further, when the pillar 5 has a tapered shape, p-type impurities can be implanted into the upper surface and the side surface of the pillar 5 even when vertical ion implantation is used. In oblique ion implantation, by appropriately adjusting the implantation angle, it is possible to form a separation region in which p-type impurities are not implanted at the bottom of the groove 4 (especially effective in the strip shape shown in FIG. 14). The removal of p-type impurities at the bottom of the groove 4 can be dealt with by providing a mask at the bottom of the groove 4 before ion implantation or selectively etching the p-type impurity region at the bottom of 4 after ion implantation.

Next, as shown in FIG. 9, an insulating film 9 is formed on the semiconductor layer 3 so as to fill the groove 4. After the insulating film 9 is formed, the insulating film 9 can be flattened if necessary.

Next, as shown in FIG. 10, a plurality of openings 10 are formed in the insulating film 9. The opening 10 can be formed using, for example, photolithography and etching techniques. Since the opening 10 is formed at a position consistent with the pillar 5, the upper surface of the pillar 5 is exposed from each opening 10.

Next, as shown in FIG. 10, an electrode 7 is formed on the upper surface of the pillar 5 exposed from the opening 10. The method for forming the electrode 7 is arbitrary, but for example, a plating method or a sputtering method can be used. Further, the electrode 7 may be formed by locally forming a metal film on the upper surface of the pillar 5 exposed from the opening 10, or the electrode 7 may be formed on the upper surface of the pillar 5 exposed from the opening 10. The electrode 7 can also be formed by forming a metal film for the electrode 7 on the insulating film 9 including the above and then patterning the metal film. In any case, the electrode 7 is locally formed on the upper surface of the pillar 5, and the electrode 7 formed on the upper surface of each pillar 5 is an electrode 7 formed on the upper surface of the other pillar 5. It is not connected to and is separated.

Next, the semiconductor substrate 2 and the structure on it (semiconductor layer 3 and insulating film 9) are diced (cut) to be individualized into chips (semiconductor chips). The individualized chip becomes the semiconductor sensor 1.

In this way, the semiconductor sensor 1 can be manufactured. Although an example of the manufacturing process of the semiconductor sensor 1 has been described here, the semiconductor sensor 1 can be manufactured by using various methods without limitation.

When the semiconductor chip 12 is mounted on the semiconductor sensor 1, as shown in FIG. 4, the main surface on the side where the electrode 7 of the semiconductor sensor 1 is formed and the electrode 13 of the semiconductor chip 12 are formed. The semiconductor chip 12 is mounted on the semiconductor sensor 1 so as to face the main surface on the side, and the plurality of electrodes 13 of the semiconductor chip 12 and the plurality of electrodes 7 of the semiconductor sensor 1 are respectively via the bump 14. Join.

<Background of examination>
The present inventor has a semiconductor sensor chip for detecting radiation (corresponding to the semiconductor sensor 1) and a reading chip for reading the electric charge (current) generated in the semiconductor sensor chip by radiation (corresponding to the semiconductor chip 12). ) Is electrically connected to form a radiation detector. The semiconductor sensor chip and the reading chip are electrically connected via bumps (corresponding to the bump 14).

FIG. 11 is a cross-sectional view of a main part of the semiconductor sensor 101 of the study example examined by the present inventor, and corresponds to FIG. 2 above.

The semiconductor sensor 101 of the study example shown in FIG. 11 has an n-type semiconductor substrate 102 and an n-type semiconductor layer 103 formed on the semiconductor substrate 102. A plurality of p-type semiconductor regions 106 are formed on the surface (surface layer portion) of the semiconductor layer 103 so as to be separated from each other, and an electrode 107 is formed on each p-type semiconductor region 106. A PN junction is formed between each p-type semiconductor region 106 and the n-type semiconductor layer 103 (interface). A back surface electrode 108 is formed on the back surface of the semiconductor substrate 102.

When detecting radiation using the semiconductor sensor 101 of the study example shown in FIG. 11, a predetermined voltage is applied between the back surface electrode 108 and the plurality of electrodes 107 in the semiconductor sensor 101. For example, a predetermined high potential is applied to the back surface electrode 108, and a predetermined low potential is applied to the plurality of electrodes 107. As a result, in the semiconductor layer 103, the depletion layer expands downward (in the direction approaching the back surface electrode 108) from the PN junction surface between the p-type semiconductor region 106 and the n-type semiconductor layer 103. In this state, when radiation is incident on the depletion layer of the semiconductor sensor 101, electrons and holes are generated by ionization. The generated electrons move to the back surface electrode 108, and the generated holes move to the electrode 107. By reading this as a current with a reading chip (corresponding to the semiconductor chip 12), radiation incident on the semiconductor sensor 101 can be detected. By detecting which electrode 107 of the plurality of electrodes 107 of the semiconductor sensor 101 the current has flowed, it is possible to detect at which position of the semiconductor sensor 101 the radiation is incident, and the magnitude of the current is large. Thereby, the intensity of radiation can be determined. This makes it possible to detect the two-dimensional distribution of the position and intensity of the radiation incident on the semiconductor sensor 101.

However, it was found by the study of the present inventor that the following problems arise in the semiconductor sensor 101 of the study example shown in FIG.

That is, in the semiconductor sensor 101 of the study example shown in FIG. 11, it is necessary to considerably increase the voltage applied between the back surface electrode 108 and the plurality of electrodes 107. When a voltage is applied between the back surface electrode 108 and the plurality of electrodes 107, the PN between the p-type semiconductor region 106 formed on the surface layer portion of the semiconductor layer 103 and the n-type semiconductor layer 103 existing below the p-type semiconductor region 106. From the junction, the depletion layer spreads downward. That is, under each p-type semiconductor region 106, the depletion layer extends in the thickness direction of the semiconductor layer 103. The higher the applied voltage, the wider the depletion layer, but in order to increase the length of the formed depletion layer (corresponding to the dimension of the depletion layer in the thickness direction of the semiconductor layer 103) to some extent, the applied voltage is considerably high. There is a need to.

If radiation is incident on the semiconductor sensor 101 in a state where the length of the depletion layer formed under the p-type semiconductor region 106 in the semiconductor layer 103 is increased to some extent, the radiation incident on the depletion layer causes the depletion layer to be exposed to radiation. Since electrons and holes are generated, it is possible to accurately detect the presence or absence of radiation incident.

However, if the voltage applied between the back surface electrode 108 and the plurality of electrodes 107 is high, a high voltage power supply for applying the high voltage is required, which increases the overall cost. , Not desirable. On the other hand, when the voltage applied between the back surface electrode 108 and the plurality of electrodes 107 is lowered, the length of the depletion layer formed on the semiconductor layer 103 (the dimension of the depletion layer in the thickness direction of the semiconductor layer 103) becomes large. Due to the shortage, the radiation detection sensitivity of the semiconductor sensor 101 is lowered.

Further, when a SiC (silicon carbide) substrate is used for the semiconductor sensor 101, since SiC has high radiation durability, there is an advantage that the reliability of the semiconductor sensor 101 can be improved. However, on the other hand, when the SiC substrate is used for the semiconductor sensor 101, the applied voltage (voltage applied between the back surface electrode 108 and the plurality of electrodes 107) required for depletion becomes higher. ..

Therefore, it is desired to be able to efficiently deplete without increasing the voltage applied to the semiconductor sensor.

<Main features and effects>
One of the main features of the present embodiment is that in the semiconductor sensor 1, a plurality of pillars 5 are provided on the semiconductor layer 3 on the semiconductor substrate 2, and the upper surfaces (upper flat surface) of the plurality of pillars 5 are respectively provided. The plurality of electrodes 7 are formed, and the back surface electrode 8 is formed on the back surface 2b of the semiconductor substrate 2. The plurality of electrodes 7 are separated from each other.

In the present embodiment, PN junctions are provided on the upper surface and the side surface of each of the plurality of pillars 5 of the semiconductor sensor 1. As a result, when a voltage is applied between the back surface electrode 8 of the semiconductor sensor 1 and the plurality of electrodes 7 to deplete the plurality of pillars 5, each pillar 5 can be efficiently depleted.

That is, in the present embodiment, in each of the plurality of pillars 5 included in the semiconductor sensor 1, PN junctions are provided not only on the upper surface side but also on the side surface side. Specifically, in the case of the semiconductor sensor 1 of the present embodiment, the p-type semiconductor region 6 is formed not only on the upper surface side of each pillar 5 but also on the side surface side of each pillar 5. Therefore, in the case of the semiconductor sensor 1 of the present embodiment, when a voltage is applied between the back surface electrode 8 and the plurality of electrodes 7, the pillar 5 is located downward from the PN junction on the upper surface side (toward the root of the pillar 5). Not only does the depletion layer expand toward the inside of the pillar 5, but the depletion layer also expands from the PN junction on the side surface side of each pillar 5 toward the inside of the pillar 5. Since the depletion layer can be efficiently depleted by the amount that the depletion layer can be expanded from the PN junction on the side surface side of each pillar 5 toward the inside of the pillar 5, the entire pillar 5 is depleted. The applied voltage required for the above (voltage applied between the back surface electrode 8 and the plurality of electrodes 7) can be reduced.

As described above, in the present embodiment, it is possible to achieve both suppression of the voltage applied between the back electrode 8 of the semiconductor sensor 1 and the plurality of electrodes 7 and depletion of each pillar 5. By suppressing the voltage applied between the back electrode 8 of the semiconductor sensor 1 and the plurality of electrodes 7, a high voltage power supply for applying a high voltage becomes unnecessary, and the overall cost of the device including the semiconductor sensor is suppressed. can do. Further, since each pillar 5 can be efficiently depleted without increasing the voltage applied between the back surface electrode 8 and the plurality of electrodes 7, the entire pillar 5 can be depleted easily and accurately. The radiation detection sensitivity of the semiconductor sensor 1 can be improved. Therefore, the performance of the semiconductor sensor 1 and the radiation detector 11 using the semiconductor sensor 1 can be improved.

Further, when SiC (silicon carbide) is used as the material (semiconductor material) constituting the semiconductor substrate 2 and the semiconductor layer 3, since SiC has high radiation durability, the reliability of the semiconductor sensor 1 is improved. be able to. However, when SiC is used as the material constituting the semiconductor substrate 2 and the semiconductor layer 3, the applied voltage required for depleting each pillar 5 (a plurality of back electrodes 8 and a plurality) is compared with the case where Si is used. The voltage applied between the electrode 7 and the electrode 7) becomes high. On the other hand, in the present embodiment, as described above, each pillar 5 can be efficiently depleted, so that the applied voltage required to deplete each pillar 5 as a whole (the back electrode 8 and a plurality of applied voltages). The voltage applied between the electrode 7 and the electrode 7) can be reduced. Therefore, even when SiC is used as the material constituting the semiconductor substrate 2 and the semiconductor layer 3, the applied voltage required for depleting the entire pillar 5 can be suppressed. Therefore, if the present embodiment is applied when the semiconductor substrate 2 and the semiconductor layer 3 are made of SiC, the effect is extremely large.

Further, as the semiconductor substrate 12a constituting the semiconductor chip 12, a silicon substrate made of single crystal silicon can be used. In this case, it becomes easy to form a desired circuit in the semiconductor chip 12, and the semiconductor chip 12 having the desired circuit can be easily and accurately manufactured.

Further, if the width W1 of each pillar 5 is reduced, the applied voltage (voltage applied between the back surface electrode 8 and the plurality of electrodes 7) required for depleting the entire pillar 5 can be reduced. .. Here, the width W1 of the pillar 5 corresponds to the dimension in the X direction or the Y direction, and is shown in FIG. Further, if the impurity concentration (n-type impurity concentration) of the semiconductor layer 3 is lowered, the applied voltage required for depleting the entire pillar 5 (voltage applied between the back surface electrode 8 and the plurality of electrodes 7). Can be lowered. Therefore, for example, the width W1 of each pillar 5 is such that the applied voltage (voltage applied between the back surface electrode 8 and the plurality of electrodes 7) required to deplete the entire pillar 5 is 300 V or less. And the impurity concentration of the semiconductor layer 3 can be set.

However, if the width W1 of each pillar 5 is made too small, the planar dimension (flat area) of the electrode 7 formed on the pillar 5 also becomes small, so that it becomes difficult to bump-connect the semiconductor sensor 1 and the semiconductor chip 12 and also. Since the plane dimension (flat area) of each pillar 5 becomes smaller, the effective detectable area of radiation in the semiconductor sensor 1 becomes narrower. Therefore, it is more preferable that the width W1 of each pillar 5 is within the range of 5 μm to 100 μm. Further, the height H1 of each pillar 5 (see FIG. 2) can be, for example, about 50 μm to 1000 μm.

Further, if the distance S1 (see FIG. 1) between adjacent pillars 5 is too narrow, it becomes difficult to form the pillars 5, and if it is too wide, the number of pillars 5 (corresponding to the number of pixels) of the semiconductor sensor 1 decreases. .. Therefore, the distance S1 between the adjacent pillars 5 can be preferably about 1 μm to 300 μm.

Further, unlike the present embodiment, a PN junction (p-type semiconductor region 6) is formed on the upper surface of each pillar 5, but a PN junction (p-type semiconductor region 6) is formed on the side surface of each pillar 5. Suppose it is not formed. In this case, in order to deplete the entire pillar 5, a voltage is applied to the back surface electrode 8 from the PN junction on the upper surface of the pillar 5 so that the depletion layer can be expanded by the height H1 of the pillar 5. It is necessary to apply it between the plurality of electrodes 7. On the other hand, in the present embodiment, a PN junction is formed not only on the upper surface of each pillar 5 but also on the side surface of each pillar 5. Therefore, in order to deplete the entire pillar 5, the depletion layer can be expanded from the PN junction on the side surface of the pillar 5 by a distance of half the width W1 of the pillar 5 (that is, W1 × 1/2). A voltage may be applied between the back surface electrode 8 and the plurality of electrodes 7. As a result, the depletion layers extending inward of the pillars 5 are connected to each other from the PN junctions on both side surfaces of the pillars 5, so that the entire pillars 5 can be depleted. Therefore, the applied voltage required to deplete each pillar 5 as a whole can be reduced.

From this point of view, the distance of half the width W1 of the pillar 5 (ie W1 × 1/2) is preferably smaller than the height H1 of the pillar 5, that is, W1 × 1/2 <H1 holds, and thus W1. It is preferable that / H1 <2 holds, and this accurately reduces the applied voltage (applied voltage required to deplete each pillar 5 as a whole) by providing a PN junction on the side surface of each pillar 5. Can be obtained. Further, it is more preferable that W1 / H1 <1/2 is satisfied, and it is further preferable that W1 / H1 <1/5 is satisfied, and the applied voltage required to deplete each pillar 5 as a whole is more preferable. Can be further effectively reduced.

<About the first modification>
FIG. 12 is a cross-sectional view of a main part showing a first modification of the semiconductor sensor 1 of the present embodiment, and corresponds to FIG. 2 above. Here, the semiconductor sensor 1 of the first modification shown in FIG. 12 will be referred to as a semiconductor sensor 1a below.

The semiconductor sensor 1a of the first modification shown in FIG. 12 differs from the semiconductor sensor 1 shown in FIGS. 1 to 3 between adjacent pillars 5 (that is, at the bottom of the groove 4). The p-type semiconductor region 6 is formed on the surface (surface layer portion) of the semiconductor layer 3.

Here, in the semiconductor sensor 1a of the first modification shown in FIG. 12, the surface (surface layer portion) of the semiconductor layer 3 is located between the adjacent pillars 5 (that is, at the bottom of the groove 4) in the p-type semiconductor region 6. The p-type semiconductor region 6 of the portion formed in the above is referred to as a p-type semiconductor region 6c.

Therefore, in the semiconductor sensor 1a of the first modification shown in FIG. 12, the p-type semiconductor regions 6 (6a, 6b) formed on the upper surface and the side surface (surface layer portion) of a pillar 5 and the pillar 5 thereof. The p-type semiconductor region 6 (6a, 6b) formed on the upper surface and the side surface (surface layer portion) of the pillar 5 adjacent to the pillar 5 is formed on the surface (surface layer portion) of the semiconductor layer 3 between the adjacent pillars 5. It is in a state of being connected to each other via the p-type semiconductor region 6 (6c). That is, the p-type semiconductor region 6 (6a, 6b) formed in each pillar 5 is between the p-type semiconductor region 6 (6a, 6b) formed in the other pillars 5 and the adjacent pillars 5. It is connected via a p-type semiconductor region 6c formed on the semiconductor layer 3.

Since the other configurations of the semiconductor sensor 1a of the first modification shown in FIG. 12 are substantially the same as those of the semiconductor sensor 1 shown in FIGS. 1 to 3, the repeated description thereof will be omitted here.

Similar to the semiconductor sensor 1 shown in FIGS. 1 to 3, in the case of the semiconductor sensor 1a of the first modification shown in FIG. 12, in each of the plurality of pillars 5, not only on the upper surface side but also on the side surface side. Is also provided with a PN junction. Therefore, the applied voltage (voltage applied between the back surface electrode 8 and the plurality of electrodes 7) required for depleting the entire pillar 5 can be reduced. Therefore, also in the case of the semiconductor sensor 1a of the first modification shown in FIG. 12, the suppression of the voltage applied between the back surface electrode 8 of the semiconductor sensor 1a and the plurality of electrodes 7 and the depletion of each pillar 5 are performed. , Can be compatible.

Further, in the case of the semiconductor sensor 1a of the first modification shown in FIG. 12, when a voltage is applied between the back surface electrode 8 and the plurality of electrodes 7, the p-type semiconductor region 6c is formed between the adjacent pillars 5. The depletion layer expands downward (in the direction toward the semiconductor substrate 2) from the PN junction with the n-type semiconductor region 3a. Therefore, in the case of the semiconductor sensor 1a of the first modification shown in FIG. 12, a depletion layer is also formed in the semiconductor layer 3 between the adjacent pillars 5. When the depletion layer is formed below the p-type semiconductor region 6c, electrons and holes may be generated by the incident radiation in the depletion layer below the p-type semiconductor region 6c. However, since the electrodes 7 are provided for each pillar 5 and the electrodes 7 are separated from each other, the electric charge generated by the radiation incident on the depletion layer below the p-type semiconductor region 6c is the largest from there. It can be detected from the electrode 7 located at a close position. Therefore, the electric signal between the pixels can be separated.

On the other hand, in the case of the semiconductor sensors 1 shown in FIGS. 1 to 3, since the p-type semiconductor region 6c is not formed, the depletion layer is unlikely to be formed in the semiconductor layer 3 between the adjacent pillars 5. Therefore, the electric charge generated by the radiation incident on the depleted pillar 5 may be detected from the electrode 7 provided for the pillar 5, and the electric signal generated in each pillar 5 is generated in the other pillar 5. Easy to separate from the electrical signal. This makes it easier to separate the electrical signals between the pixels more clearly, which makes it easier to improve the resolution of the semiconductor sensor.

<About the second modification>
FIG. 13 is a cross-sectional view of a main part showing a second modification of the semiconductor sensor 1 of the present embodiment, and corresponds to FIG. 2 above. Here, the semiconductor sensor 1 of the second modification shown in FIG. 13 will be referred to as a semiconductor sensor 1b below.

The semiconductor sensor 1b of the second modification shown in FIG. 13 differs from the semiconductor sensor 1 shown in FIGS. 1 to 3 in that the semiconductor substrate 2 and the semiconductor layer 3 are combined as a whole. Is the semiconductor substrate 2. That is, in the case of the semiconductor sensor 1b of the second modification shown in FIG. 13, the semiconductor layer 3 is not formed on the semiconductor substrate 2, and the plurality of pillars 5 are provided on the semiconductor substrate 2. .. The back surface electrode 8 is formed on the back surface 2b, which is the main surface of the semiconductor substrate 2 opposite to the side on which the plurality of pillars 5 are formed. In the step before forming the back surface electrode 8, for example, a high-concentration n-type impurity semiconductor layer may be formed by ion implantation of the n-type impurity to form an ohmic connection.

Since the other configurations of the semiconductor sensor 1b of the second modification shown in FIG. 13 are substantially the same as those of the semiconductor sensor 1 shown in FIGS. 1 to 3, the repeated description thereof will be omitted here.

In the case of the second modification shown in FIG. 13, since it is not necessary to form a thick semiconductor layer, the manufacturing cost of the semiconductor sensor can be suppressed. The semiconductor substrate 2 used in the second modification is, for example, a substrate that can be depleted with an applied voltage similar to that of the semiconductor layer 3 (preferably a semi-insulating SiC substrate or an impurity concentration of 1X10 ^ 13 to 1X10 ^ 16 (preferably a semi-insulating SiC substrate). cm ^ -3) n-type SiC substrate) can be used.

On the other hand, in the case of the semiconductor sensor 1 shown in FIGS. 1 to 3, the optimum impurity concentration can be set for each of the semiconductor substrate 2 and the semiconductor layer 3. For example, the semiconductor layer 3 can be set with an impurity concentration in consideration of the depletion of the pillar 5, and the semiconductor substrate 2 can be set with an impurity concentration in consideration of contact with the back surface electrode 8. .. Therefore, it is easy to improve the overall performance of the semiconductor sensor.

The second modification includes the semiconductor sensor 1 of FIGS. 1 to 3, the semiconductor sensor 1a of the first modification, the semiconductor sensor 1c of the third modification described later, and the semiconductor sensor 1d of the second embodiment described later. , And the semiconductor sensor 1e of the fourth modification described later can be applied.

<About the third modification>
14 and 15 are a main part plan view (FIG. 14) and a main part cross-sectional view (FIG. 15) showing a third modification of the semiconductor sensor 1 of the present embodiment. FIG. 14 corresponds to FIG. 1 above. Whereas FIG. 1 is a two-dimensional sensor, FIG. 14 is a one-dimensional line sensor. FIG. 15 corresponds to the cross-sectional view at the position of line B2-B2 in FIG. Since the cross-sectional view at the position of line B1-B1 in FIG. 14 is the same as that of FIG. 2, the illustration is omitted here, and the cross-sectional view at the position of line B3-B3 in FIG. 14 is described above. Since it is the same as FIG. 3, the illustration is omitted here.

In the case of the third modification of FIGS. 14 and 15, in the plan view, each pillar 5 extends in the Y direction, and a plurality of pillars 5 extending in the Y direction are arranged side by side in the X direction. .. An electrode 7 is provided for each pillar 5, and the electrode 7 extending in the Y direction is arranged on the pillar 5 extending in the Y direction in a plan view. In this case, each pillar 5 has an upper surface shape with the Y direction as the longitudinal direction (major axis direction), and the pillar 5 may have a strip shape. The shape of the pillar 5 can be changed in various ways, and the shape of the electrode 7 formed on the pillar 5 can be changed accordingly. Therefore, the pillar 5 can be regarded as a convex portion protruding in the thickness direction of the semiconductor substrate 2. Further, the back surface electrode 8 can be divided into a plurality of parts.

Also in the case of the third modification of FIGS. 14 and 15, when a voltage is applied between the back surface electrode 8 and the plurality of electrodes 7, the depletion layer only expands downward from the PN junction on the upper surface side of each pillar 5. Instead, the depletion layer spreads toward the inside of the pillar 5 from the PN junction formed on both side surfaces of each pillar 5 (both side surfaces located on opposite sides in the X direction). As a result, each pillar 5 can be efficiently depleted, so that the applied voltage (voltage applied between the back surface electrode 8 and the plurality of electrodes 7) required for depleting the entire pillar 5 is reduced. can do. Therefore, it is possible to achieve both suppression of the voltage applied between the back surface electrode 8 and the plurality of electrodes 7 and depletion of each pillar 5.

The third modification is the semiconductor sensor 1 of FIGS. 1 to 3, the semiconductor sensors of the first and second modifications, the semiconductor sensor 1d of the second embodiment described later, and the fourth modification described later. It can be applied to any of the semiconductor sensors 1e.

(Embodiment 2)
The semiconductor sensor 1 of the second embodiment will be described with reference to the drawings. FIG. 16 is a cross-sectional view of a main part showing the semiconductor sensor 1 of the second embodiment, and corresponds to FIG. 2 above. Here, the semiconductor sensor 1 of the second embodiment shown in FIG. 16 will be referred to as a semiconductor sensor 1d below.

In the semiconductor sensor 1d of the second embodiment, the p-type semiconductor region 6 is not formed. Instead, Schottky electrodes 21 are formed on the upper surface and side surfaces of each pillar 5. That is, in each pillar 5, the Schottky electrode 21 is formed on the upper surface and the side surface. The Schottky electrode 21 is made of a metal material, for example, a nickel (Ni) film or a titanium (Ti) film. A silicide (a compound layer of a metal constituting the Schottky electrode 21 and a semiconductor constituting the semiconductor layer 3) may be formed in a region between the Schottky electrode 21 and the pillar 5 (semiconductor layer 3). The Schottky electrode 21 can be formed by a material and a forming method such that a Schottky bond is formed between the Schottky electrode 21 and the pillar 5 (semiconductor layer 3).

In the semiconductor sensor 1d of the second embodiment, since the p-type semiconductor region 6 is not formed, almost the entire pillar 5 is an n-type semiconductor region. Therefore, the Schottky electrode 21 is formed on the upper surface and the side surface of the pillar 5 composed of the n-type semiconductor region. A Schottky bond is formed between the Schottky electrode 21 and the pillar 5 (interface). Therefore, in the semiconductor sensor 1d of the second embodiment, the Schottky joint is formed on the upper surface and the side surface of each pillar 5.

In the case of FIG. 16, the Schottky electrode 21 is not formed on the surface of the semiconductor layer 3 between the adjacent pillars 5, that is, at the bottom of the groove 4. Therefore, the Schottky electrode 21 formed on the upper surface and the side surface of a certain pillar 5 and the Schottky electrode 21 formed on the upper surface and the side surface of the pillar 5 adjacent to the pillar 5 are not connected to each other. , Separated from each other. That is, the Schottky electrodes 21 formed for each pillar 5 are not connected to the Schottky electrodes 21 formed for the other pillars 5, and are separated from each other.

An electrode 7 is formed on the upper surface of each pillar 5, but in the case of the semiconductor sensor 1d of the second embodiment, the electrode 7 is on the Schottky electrode 21 (more specifically, on the upper surface of the pillar 5). It is formed on the Schottky electrode 21) of the portion located in. Therefore, the electrode 7 is in contact with the Schottky electrode 21 and is electrically connected to the Schottky electrode 21. The electrode 7 is preferably ohmic connected to the Schottky electrode 21.

Since the other configurations of the semiconductor sensor 1d of the second embodiment shown in FIG. 16 are substantially the same as those of the semiconductor sensor 1 of the first embodiment shown in FIGS. 1 to 3, the repetition thereof is described here. The explanation is omitted.

In the case of the semiconductor sensor 1d of the second embodiment, since the Schottky junction is formed between the Schottky electrode 21 and the pillar 5 composed of the n-type semiconductor region, the Schottky junction is formed on the upper surface and the side surface of each pillar 5. It will be formed. Therefore, in the case of the semiconductor sensor 1d of the second embodiment, when a voltage is applied between the back surface electrode 8 and the plurality of electrodes 7, the pillar 5 is located downward from the Schottky junction on the upper surface side (the root direction of the pillar 5). ), The depletion layer not only expands toward the inside of the pillar 5 from the Schottky joint on the side surface side of each pillar 5. Since the depletion layer can be efficiently expanded from the shot joint on the side surface side of each pillar 5 toward the inside of the pillar 5, each pillar 5 can be efficiently depleted, so that the entire pillar 5 is depleted. The applied voltage required for the above (voltage applied between the back surface electrode 8 and the plurality of electrodes 7) can be reduced. Also in the case of the semiconductor sensor 1d of the second embodiment, it is possible to achieve both suppression of the voltage applied between the back surface electrode 8 of the semiconductor sensor 1c and the plurality of electrodes 7 and depletion of each pillar 5. ..

FIG. 17 is a cross-sectional view of a main part showing a modified example (hereinafter referred to as a fourth modified example) of the semiconductor sensor 1 (1d) of the second embodiment, and corresponds to FIG. 16 above. Here, the semiconductor sensor 1 of the fourth modification shown in FIG. 17 will be referred to as a semiconductor sensor 1e below.

The semiconductor sensor 1e of the fourth modification shown in FIG. 17 differs from the semiconductor sensor 1d shown in FIG. 16 between the adjacent pillars 5 (that is, at the bottom of the groove 4) in the semiconductor layer. The Schottky electrode 21 is formed on the surface of 3.

Therefore, in the semiconductor sensor 1e of the fourth modification shown in FIG. 17, the Schottky electrodes 21 formed on the upper surface and the side surface of a certain pillar 5 are formed on the upper surface and the side surface of the pillar 5 adjacent to the pillar 5. The Schottky electrodes 21 are connected to each other via the Schottky electrodes 21 formed on the surface of the semiconductor layer 3 between the adjacent pillars 5. That is, the Schottky electrode 21 formed for each pillar 5 is a Schottky formed on the surface of the semiconductor layer 3 between the Schottky electrode 21 formed for the other pillars 5 and the adjacent pillars 5. They are connected via electrodes 21.

Since the other configurations of the semiconductor sensor 1e of the fourth modification shown in FIG. 17 are substantially the same as those of the semiconductor sensor 1d shown in FIG. 16, the repeated description thereof will be omitted here.

Similar to the semiconductor sensor 1d shown in FIG. 16, in the case of the semiconductor sensor 1e of the fourth modification shown in FIG. 17, when a voltage is applied between the back surface electrode 8 and the plurality of electrodes 7, each pillar 5 Not only the depletion layer expands downward from the Schottky junction on the upper surface side, but also the depletion layer expands from the Schottky junction on the side surface side of each pillar 5 toward the inside of the pillar 5. Since the depletion layer can be efficiently expanded from the Schottky joint on the side surface side of each pillar 5 toward the inside of the pillar 5, each pillar 5 can be efficiently depleted, so that the entire pillar 5 is depleted. The applied voltage required for the above (voltage applied between the back surface electrode 8 and the plurality of electrodes 7) can be reduced. Therefore, also in the case of the semiconductor sensor 1e of the fourth modification shown in FIG. 17, the suppression of the voltage applied between the back surface electrode 8 of the semiconductor sensor 1a and the plurality of electrodes 7 and the depletion of each pillar 5 are performed. , Can be compatible.

Further, in the case of the semiconductor sensor 1e of the fourth modification shown in FIG. 17, when a voltage is applied between the back surface electrode 8 and the plurality of electrodes 7, the semiconductor layer 3 and the Schottky electrode are placed between the adjacent pillars 5. The depletion layer expands downward (in the direction toward the semiconductor substrate 2) from the Schottky junction with 21. Therefore, in the case of the semiconductor sensor 1e of the fourth modification shown in FIG. 17, a depletion layer is also formed in the semiconductor layer 3 between the adjacent pillars 5, and the radiation incident on the depletion layer is formed. Can generate electrons and holes. However, since the electrodes 7 are provided for each pillar 5 and the electrodes 7 are separated from each other, the electric charge generated by radiation in the depletion layer formed in the semiconductor layer 3 between the adjacent pillars 5 is generated. , Can be detected from the electrode 7 closest to it. Therefore, the electric signal between the pixels can be separated.

On the other hand, in the case of the semiconductor sensor 1d shown in FIG. 16, since the Schottky electrode 21 is not formed on the semiconductor layer 3 between the adjacent pillars 5, the semiconductor layer 3 between the adjacent pillars 5 is formed. The depletion layer is difficult to form. Therefore, it becomes easier to separate the electric signals between the pixels more clearly, and it is easy to improve the resolution of the semiconductor sensor.

Although the invention made by the present inventor has been specifically described above based on the embodiment thereof, the present invention is not limited to the embodiment and can be variously modified without departing from the gist thereof. Needless to say.

1,1a, 1b, 1c, 1d, 1e Semiconductor sensor 2 Semiconductor substrate 2a Main surface 2b Back surface 3 Semiconductor layer 3an type semiconductor region 4 Groove 5 Pillars 6, 6a, 6b, 6cp type semiconductor region 7 Electrode 8 Backside electrode 9 Insulation film 10 Opening 11 Radiation detector 12 Semiconductor chip 12a Semiconductor substrate 12b Multilayer wiring structure 13 Electrode 14 Bump 21 Schottky electrode 101 Semiconductor sensor 102 Semiconductor substrate 103 Semiconductor layer 106 P-type semiconductor region 107 Electrode 108 Backside electrode

Claims (14)

1. The first conductive type semiconductor substrate and
   A plurality of pillars provided on the semiconductor substrate, each having an upper flat surface and a side surface,
   In each of the plurality of pillars, the PN junction or the Schottky junction provided on the upper flat surface and the side surface thereof,
   A plurality of first electrodes each formed on the upper flat surface of the plurality of pillars, the plurality of first electrodes separated from each other, and the plurality of first electrodes.
   A second electrode provided on the main surface of the semiconductor substrate opposite to the side on which the plurality of pillars are formed, and
   A radiation detection sensor.
2. In the radiation detection sensor according to claim 1,
   A radiation detection sensor in each of the plurality of pillars, wherein the PN junction has a second conductive type semiconductor region opposite to the first conductive type provided on the upper flat surface and the side surface.
3. In the radiation detection sensor according to claim 2,
   A radiation detection sensor in which a first electrode is formed in a part of the semiconductor region of the second conductive type in each of the plurality of pillars.
4. In the radiation detection sensor according to claim 2 or 3.
   A radiation detection sensor in which the semiconductor region of the second conductive type is not formed on the semiconductor substrate between adjacent pillars.
5. In the radiation detection sensor according to claim 2 or 3.
   A radiation detection sensor in which the semiconductor region of the second conductive type is also formed on the semiconductor substrate between adjacent pillars.
6. In the radiation detection sensor according to claim 1,
   In each of the plurality of pillars, the Schottky junction is a radiation detection sensor having Schottky electrodes provided on the upper flat surface and the side surfaces.
7. In the radiation detection sensor according to claim 6,
   A radiation detection sensor in which the first electrode is formed on a part of the Schottky electrode in each of the plurality of pillars.
8. In the radiation detection sensor according to claim 6 or 7.
   A radiation detection sensor in which the Schottky electrode is not formed on the semiconductor substrate between adjacent pillars.
9. In the radiation detection sensor according to claim 6 or 7.
   A radiation detection sensor in which the Schottky electrode is also formed on the semiconductor substrate between adjacent pillars.
10. In the radiation detection sensor according to any one of claims 1 to 9.
    A radiation detection sensor further comprising an insulating film that fills the space between the plurality of pillars.
11. In the radiation detection sensor according to any one of claims 1 to 10.
    The semiconductor substrate has a first semiconductor substrate and a semiconductor layer formed on the first semiconductor substrate.
    The plurality of pillars are radiation detection sensors provided in the semiconductor layer.
12. In the radiation detection sensor according to claim 11,
    A radiation detection sensor in which the semiconductor substrate and the semiconductor layer are each made of silicon carbide.
13. In the radiation detection sensor according to any one of claims 1 to 10.
    The semiconductor substrate is a radiation detection sensor made of silicon carbide.
14. The radiation detection sensor according to any one of claims 1 to 13.
    A semiconductor chip for reading and
    Equipped with
    The reading semiconductor chip has a plurality of third electrodes arranged at positions corresponding to the plurality of first electrodes of the radiation detection sensor.
    A radiation image detector in which the plurality of third electrodes are bump-connected to the plurality of first electrodes.

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