JP7099017B2 - Semiconductor equipment - Google Patents

Description

The present invention relates to a semiconductor device.

Conventionally, semiconductor devices such as insulated gate bipolar transistors (IGBTs) are known (see, for example, Patent Document 1).
Patent Document 1 Japanese Patent Application Laid-Open No. 2010-283205 Patent Document 2 Japanese Patent Application Laid-Open No. 2009-11188

In semiconductor devices, it is preferable to suppress heat generation during reverse recovery.

In the first aspect of the present invention, a semiconductor device including a semiconductor substrate is provided. The semiconductor device may include a well region provided in contact with the upper surface of the semiconductor substrate. The semiconductor device may include an active region in which a current flows between the upper and lower surfaces of the semiconductor substrate. The semiconductor device may include a transistor portion provided in the active region. The semiconductor device may include a diode portion provided in the active region and arranged adjacent to the transistor portion along a predetermined arrangement direction in a top view of the semiconductor substrate. The semiconductor device may include a protective film provided above the active region. The protective film may be provided with a plurality of openings in a region sandwiched between the well regions in a top view. At least one opening may be provided above both the transistor and diode sections.

The active region may have a plurality of divided regions surrounded by a well region. Two or more openings may be provided above at least one split region.

The diode portion may have a first conductive type cathode region provided in contact with the lower surface of the semiconductor substrate. In each of the plurality of divided regions, the area where the opening and the cathode region overlap may be larger than the area where the protective film and the cathode region overlap.

A plurality of openings may be arranged above the at least one divided region in the extending direction orthogonal to the arrangement direction.

At least one diode portion may be continuously provided over two or more openings in the stretching direction.

The semiconductor device may include a gate runner unit that supplies a gate voltage to the transistor unit. In the top view of the semiconductor substrate, at least one divided region may be arranged so as to be sandwiched between the gate runner portions.

The semiconductor device may include temperature sense wiring provided above the active region. The at least one divided region may be arranged so as to be sandwiched between at least one of the gate runner portion and the temperature sense wiring.

The end portion of the opening in the arrangement direction may be arranged above the transistor portion.

The protective film may have a first separation region that separates the openings between two adjacent openings in the arrangement direction. The first separation region is arranged above the transistor portion, and the width of the first separation region in the arrangement direction may be smaller than the width of the transistor portion.

A protective film may be arranged above at least a part of the at least one diode portion in the arrangement direction.

The protective film may have a first separation region that separates the openings between two adjacent openings in the arrangement direction. The width of the first separation region in the arrangement direction may be smaller than the width of the diode portion.

The semiconductor device may include a bonding pad arranged in each opening.

The semiconductor device may include a solder portion that electrically connects the plurality of bonding pads above the plurality of bonding pads.

In the top view of the semiconductor substrate, the end portion of the solder portion may be arranged between the end portion of the bonding pad and the outer peripheral end of the semiconductor substrate.

The outline of the above invention does not list all the necessary features of the present invention. A subcombination of these feature groups can also be an invention.

It is a figure which shows an example of the upper surface of the semiconductor device 100 which concerns on this embodiment. It is a figure which shows an example of the structure provided above the well area 11. It is a figure which shows the arrangement example of the division area 72. It is a figure explaining the width in the arrangement direction and the extension direction of the opening 84. It is a figure explaining the separation area which separates each opening 84. It is a figure which shows the upper surface in another example of a semiconductor device 100. It is a figure which shows the upper surface of the semiconductor device 150 of the comparative example. It is an enlarged view of the region A in FIG. 1b. It is an enlarged view of the region B in FIG. 1b. It is a figure which shows an example of the aa'cross section in FIG. It is a figure which shows an example of the bb'cross section in FIG. It is a figure which shows an example of the upper surface of the semiconductor device 100 which concerns on this embodiment. It is a figure which adds the solder part 99 to the structure shown in FIG. 6a. It is a figure which adds the solder part 99 to the structure shown in FIG. 6b.

Hereinafter, the present invention will be described through embodiments of the invention, but the following embodiments do not limit the invention to which the claims are made. Also, not all combinations of features described in the embodiments are essential to the means of solving the invention.

In the present specification, one side in the direction parallel to the depth direction of the semiconductor substrate is referred to as "upper", and the other side is referred to as "lower". Of the two main surfaces of the substrate, layer or other member, one surface is referred to as the upper surface and the other surface is referred to as the lower surface. The "up" and "down" directions are not limited to the gravity direction or the mounting direction to the substrate or the like at the time of mounting the semiconductor device.

In the present specification, technical matters may be described using orthogonal coordinate axes of X-axis, Y-axis, and Z-axis. In the present specification, the plane parallel to the upper surface of the semiconductor substrate is defined as the XY plane, and the depth direction of the semiconductor substrate is defined as the Z axis. In the present specification, the view from the direction perpendicular to the upper surface of the semiconductor substrate is referred to as a top view, and the view in the top view is referred to as a top view.

In each embodiment, an example in which the first conductive type is N-type and the second conductive type is P-type is shown, but the first conductive type may be P-type and the second conductive type may be N-type. In this case, the conductive types such as the substrate, the layer, and the region in each embodiment have opposite polarities.

As used herein, the doping concentration refers to the concentration of a donor or accepted impurity. In the present specification, the concentration difference between the donor and the acceptor may be referred to as a doping concentration. Further, the peak value of the doping concentration distribution in the doping region may be used as the doping concentration in the doping region.

FIG. 1a is a diagram showing an example of the upper surface of the semiconductor device 100 according to the present embodiment. The semiconductor device 100 of this example is a semiconductor chip including a transistor unit 70 and a diode unit 80. The transistor unit 70 includes a transistor such as an IGBT. The diode section 80 includes a diode such as a FWD (Free Wheel Diode) provided adjacent to the transistor section 70 on the upper surface of the semiconductor substrate 10.

The semiconductor substrate 10 is provided with an active region 120. The active region 120 is a region in which a current flows between the upper surface and the lower surface of the semiconductor substrate 10 when the semiconductor device 100 is controlled to be in the ON state. That is, it is a region in which a current flows in the depth direction inside the semiconductor substrate 10 from the upper surface to the lower surface or from the lower surface to the upper surface of the semiconductor substrate 10. The region provided with the transistor portion 70 or the diode portion 80 may be the active region 120. Further, the region surrounded by the gate runner portion arranged along the outer peripheral end 140 of the semiconductor substrate 10 in the top view may be the active region 120. The gate runner unit supplies a gate voltage to the transistor unit 70.

In the top view of the semiconductor substrate 10, the region between the active region 120 and the outer peripheral end 140 of the semiconductor substrate 10 is defined as the outer peripheral region 90. The outer peripheral region 90 is provided so as to surround the active region 120 in the top view of the semiconductor substrate 10. The above-mentioned gate runner portion may be provided in the outer peripheral region 90. The outer peripheral region 90 may be provided with an edge termination structure portion for relaxing the electric field concentration on the upper surface side of the semiconductor substrate 10. The edge termination structure portion is arranged between the gate runner portion and the outer peripheral end 140. The edge termination structure may have at least one of a guard ring, a field plate and a resurf, and may have a structure in which these are combined.

The active region 120 is provided with one or more transistor portions 70 and one or more diode portions 80. In the active region 120 of this example, the transistor portion 70 and the diode portion 80 are alternately arranged along a predetermined arrangement direction (Y-axis direction in the example of FIG. 1a). In the present specification, the arrangement direction may be referred to as a Y-axis direction. The transistor portion 70 and the diode portion 80 are provided so as to be stretched in a stretching direction (X-axis direction in the example of FIG. 1a) perpendicular to the arrangement direction. In the present specification, the stretching direction may be referred to as an X-axis direction. The stretching direction of the transistor portion 70 and the diode portion 80 may be the longitudinal direction.

The transistor portion 70 is a region in which a unit structure including a gate structure such as a gate trench portion and an N + type emitter region is periodically provided on the upper surface side of the semiconductor substrate 10. The transistor unit 70 includes a region inside the semiconductor substrate 10 through which the region is projected when the region in which the unit structure is periodically provided is projected to the lower surface of the semiconductor substrate 10.

The diode portion 80 is a region provided with an N + type cathode region 82 on the lower surface side of the semiconductor substrate. The diode portion 80 may include a region in which the cathode region 82 is extended in the stretching direction perpendicular to the arrangement direction (X-axis direction in the example of FIG. 1a) to a position where it comes into contact with the well region 11 described later. The diode unit 80 includes a region inside the semiconductor substrate 10 through which the cathode region 82 and the region extending the cathode region 82 are projected to the lower surface of the semiconductor substrate 10. The cathode region 82 may be provided in a range not in contact with the well region 11 as shown by the dotted line frame in FIG. 1a. In FIG. 1a, the positions of the end portion of the cathode region 82 and the end portion of the diode portion 80 in the Y-axis direction are shifted, but the end portion position of the cathode region 82 and the diode portion 80 in the Y-axis direction are shown. It coincides with the position of the end of. Of the active region 120, a region other than the diode portion 80 may be used as the transistor portion 70.

A protective film 36 is provided above the semiconductor substrate 10. The protective film 36 may be provided above the active region 120, or may be provided above the active region 120 and the outer peripheral region 90. The end portion of the protective film 36 in top view may be arranged closer to the outer peripheral end 140 side than the end portion of the active region 120. The protective film 36 may be formed of an organic material such as polyimide. The protective film 36 may be formed of a silicon-based resin material. At least a part of the protective film 36 is arranged above an upper surface electrode such as an emitter electrode provided on the upper surface of the semiconductor substrate 10.

The protective film 36 is provided with a plurality of openings 84. The term "protective film" as used herein does not include the region of the opening 84. For example, the area of the protective film 36 in the top view does not include the area of the opening 84. In FIG. 1a, the protective film 36 is hatched with diagonal lines. The opening 84 is a region surrounded by the protective film 36. The opening 84 may be located above the emitter electrode.

At least one opening 84 is arranged above the active region 120, straddling both the transistor portion 70 and the diode portion 80 in the arrangement direction (Y-axis direction). One opening 84 may be arranged across a plurality of transistor portions 70 in the arrangement direction (Y-axis direction). One opening 84 may be arranged across a plurality of diode portions 80 in the arrangement direction (Y-axis direction). In the example of FIG. 1a, all openings 84 are arranged above the active region 120, straddling both the transistor portion 70 and the diode portion 80 in the arrangement direction (Y-axis direction).

The semiconductor substrate 10 is provided with a second conductive type well region 11. The well region 11 is provided from the upper surface of the semiconductor substrate 10 to a position deeper than the lower end of the base region 14 described later. The well region 11 may have a higher doping concentration than the base region 14. The well region 11 of this example is P + type.

The well region 11 of this example has a portion provided in an annular shape along the outer peripheral end 140 of the semiconductor substrate 10. The well region 11 may be arranged so as to surround the active region 120 in top view. The well region 11 may be provided below the gate metal layer 50 along the gate metal layer 50 described later. The well region 11 may be provided below the gate metal layer 50 in a wider range than the range overlapping the gate metal layer 50.

The well region 11 of this example may have a portion provided in the active region 120. The well region 11 may have a portion provided so as to cross the active region 120 from one end to the other end of the active region 120 in a top view, and may be provided from one end of the active region 120 to the inside of the active region 120. May be good. As an example, the well region 11 may be provided below the gate runner 53 along the gate runner 53 described later. The well region 11 may be provided below the gate runner 53 in a wider range than the range overlapping the gate runner 53. Further, the well region 11 may be provided below the temperature sense unit 78 and the temperature sense wiring 92 along the temperature sense unit 78 and the temperature sense wiring 92 described later. The well region 11 may be provided below the temperature sense unit 78 and the temperature sense wiring 92 in a wider range than the range in which the temperature sense unit 78 and the temperature sense wiring 92 overlap. The position where the well region 11 is provided is not limited to the above-mentioned position.

The protective film 36 is provided with a plurality of openings 84 in a single region sandwiched between the well regions 11 in a top view. The region sandwiched between the well regions 11 may refer to a region sandwiched between the well regions 11 in at least one of the arrangement direction (Y-axis direction) and the stretching direction (X-axis direction). For example, for each position in the active region 120, for at least one of a straight line parallel to the arrangement direction passing through the position and a straight line parallel to the stretching direction, the straight line intersects the well region 11 on both sides of the position. If so, it is assumed that the position is sandwiched between the well regions 11. When the well area 11 is further arranged between the two well areas 11, the area between the well areas 11 is regarded as a single area.

For example, in the example of FIG. 1a, a plurality of openings 84-1, 84-2, 84-3, 84-4 are arranged in one region sandwiched by the well region 11 in the arrangement direction (and extension direction). There is. The direction in which the well region 11 sandwiches the one region may or may not coincide with the direction in which the plurality of openings 84 provided in the one region are arranged. The entire circumference of the region sandwiched between the well regions 11 may be surrounded by the well regions 11.

A bonding pad made of metal is provided inside each opening 84. Above each bonding pad, a solder portion for connecting a plurality of bonding pads is provided. A metal plate for electrodes such as a lead frame or wiring such as a wire may be connected on the solder portion.

As described above, by providing the plurality of openings 84 in a single region sandwiched between the well regions 11, a plurality of bonding pads can be discretely arranged in the single region. When the bonding pad thermally expands due to the heat generated during the operation of the transistor portion 70 and the diode portion 80, the pressure distribution between the solder portion in contact with the upper surface of the bonding pad and the metal plate for electrodes of the package in contact with the upper surface of the solder portion. Bias may occur. In the semiconductor device 100 of this example, the opening 84 and the bonding pad are dispersedly arranged in the above-mentioned single region. As a result, the bias of the pressure distribution generated in the contact surface between the bonding pad and the solder portion and a part of the contact surface between the solder portion and the metal plate for the electrode is dispersed, and the pressure distribution on each contact surface becomes uniform. be able to. As described above, it is possible to suppress the characteristic defect of the semiconductor device 100 and reduce the assembly defect of the semiconductor device 100.

Further, since the opening 84 is provided above both the transistor portion 70 and the diode portion 80 and straddling both the transistor portion 70 and the diode portion 80, each bonding pad is provided for both the transistor portion 70 and the diode portion 80. Can be placed on top. Therefore, regardless of which of the transistor section 70 and the diode section 80 is in a conductive state, the heat from the transistor section 70 and the diode section 80 can be easily dissipated.

FIG. 1b is a diagram showing an example of a configuration provided above the well region 11. In FIG. 1b, the protective film 36 and the opening 84 shown in FIG. 1a are omitted. In this example, a gate metal layer 50, a gate runner 53, a temperature sense unit 78, a temperature sense wiring 92, and one or more control pads are provided above the well region 11. A wire or the like connecting the semiconductor device 100 and an external device is fixed to the control pad. The control pad may be a terminal for gate control or a sensing terminal for overheated temperature or overcurrent. The semiconductor device 100 of this example includes a temperature measuring pad 94, a gate pad 55, a current sense pad 58, and a Kelvin pad 57 as control pads. The region where one or more control pads are formed is referred to as a control electrode unit 102. The control electrode portion 102 is provided in the outer peripheral region 90.

Further, in FIG. 1b, the range in which the emitter electrode 52 provided above the upper surface of the semiconductor substrate 10 is provided is shown by a thick broken line. The emitter electrode 52 may be provided so as to cover the active region 120. At least a portion of the end of the emitter electrode 52 may be located above the well region 11 between the gate metal layer 50 and the active region 120.

An emitter electrode 52 is provided above the active region 120. In FIG. 1b, the range in which the emitter electrode 52 is provided (that is, the end of the emitter electrode 52) is shown by a thick broken line portion 101 in the top view of the semiconductor substrate 10. The emitter electrode 52 is provided in the inner region surrounded by the broken line portion. A plurality of emitter electrodes 52 may be formed in the top view of the semiconductor substrate 10. For example, the emitter electrode 52 may be provided for each of the divided regions described later. All the transistor portions 70 and the diode portions 80 provided in the active region 120 may be provided so as to be covered with the emitter electrode 52. The plurality of emitter electrodes 52 are electrically connected to each other by a wire, a lead frame, or the like to maintain the same potential.

In the example of FIG. 1b, the emitter electrode 52 is provided so as not to overlap the temperature sense portion 78 and the temperature sense wiring 92 described later. In another example, the emitter electrode 52 may be provided so as to overlap the temperature sense portion 78 and the temperature sense wiring 92. In this case, an insulating film is provided between the emitter electrode 52, the temperature sense unit 78, and the temperature sense wiring 92.

The gate metal layer 50 and the gate runner 53 are examples of the gate runner portion. The gate metal layer 50 and the emitter electrode 52 are made of a material containing metal. The gate metal layer 50 is arranged above the upper surface of the semiconductor substrate 10. An insulating film is arranged between the gate metal layer 50 and the semiconductor substrate 10. The gate metal layer 50 and the emitter electrode 52 may be formed of aluminum or an aluminum-silicon alloy. The gate metal layer 50 is electrically connected to the transistor portion 70 and supplies a gate voltage to the transistor portion 70. The emitter electrode 52 may be electrically connected to an external device via a bonding pad provided in the opening 84 shown in FIG. 1a.

The gate metal layer 50 is provided so as to surround the active region 120 in the top view of the semiconductor substrate 10. The gate metal layer 50 may be provided along the outer peripheral end 140 of the semiconductor substrate 10. The gate metal layer 50 is electrically connected to a gate pad 55 provided outside the active region 120. The gate pad 55 may be arranged between the gate metal layer 50 and the active region 120 in the stretching direction (X-axis direction).

The gate runner 53 is electrically connected to the gate metal layer 50 and extends above the active region 120. The gate runner 53 electrically connects the gate metal layer 50 and a conductive portion such as polysilicon provided in the trench of the gate trench portion of the transistor portion 70. The gate runner 53 is made of a conductive material such as polysilicon. The gate runner 53 may be arranged above the upper surface of the semiconductor substrate 10, or may be arranged in a trench formed on the upper surface of the semiconductor substrate 10. An insulating film is arranged between the gate runner 53 and the semiconductor substrate 10.

The gate runner 53 may be arranged across the active region 120 in the arrangement direction (Y-axis direction). Both ends of the gate runner 53 may be connected to the gate metal layer 50. A plurality of gate runners 53 that cross the active region 120 in the Y-axis direction may be arranged in the stretching direction (X-axis direction). Further, the gate runner 53 may have an annular portion arranged around the active region 120 along the gate metal layer 50. The gate runner 53 that traverses the active region 120 may be connected to an annular gate runner 53 that surrounds the active region 120. The annular portion of the gate runner 53 may be connected to the gate metal layer 50 via a contact hole.

The gate runner 53 may also be provided between at least one control pad and the active region 120 in the outer peripheral region 90. The gate runner 53 provided in the outer peripheral region 90 may intersect the temperature sense wiring 92 in the top view of the semiconductor substrate 10. The gate runner 53 is provided so as to pass below the temperature sense wiring 92 in the Y-axis direction. Both ends of the gate runner 53 are connected to the gate metal layer 50.

The temperature sense unit 78 is provided above the semiconductor substrate 10 in the active region 120. The temperature sense unit 78 may be provided in the center of the active region 120 in the top view of the semiconductor substrate 10. The temperature sense unit 78 detects the temperature of the active region 120. The temperature sense unit 78 may be a pn type temperature sense diode formed of single crystal or polycrystalline silicon. The temperature sense unit 78 of this example is provided above the well region 11.

The temperature sense wiring 92 is provided above the active region 120 in the top view of the semiconductor substrate 10. The temperature sense wiring 92 is connected to the temperature sense unit 78. The temperature sense wiring 92 extends to the outer peripheral region 90 in a predetermined direction (X-axis direction in this example), and is connected to the temperature measuring pad 94 provided in the outer peripheral region 90.

The temperature sense wiring 92 may include a wiring 89 electrically connected to the p-type layer of the pn-type temperature sense diode and a wiring 91 electrically connected to the n-type layer. The wiring 89 is connected to the anode pad 94-2 for temperature measurement, and the wiring 91 is connected to the cathode pad 94-1 for temperature measurement. The temperature sense is measured by measuring the characteristics such as the voltage and the current of the temperature sense unit 78 through the temperature measurement pad 94 (in this example, the temperature measurement cathode pad 94-1 and the temperature measurement anode pad 94-2). The temperature of unit 78 can be detected.

In FIG. 1b, the temperature sense wiring 92 is schematically represented by a solid rectangular wire, but the temperature sense wiring 92 is for the anode wiring and the cathode like the wiring 89 and the wiring 91 shown by the dotted line in FIG. 1b. May have wiring. The temperature sense wiring 92 of this example is arranged above the well region 11.

The current sense pad 58 detects the current flowing through the transistor unit 70. The semiconductor device 100 of this example further includes a current sense unit 59 through which a current corresponding to the current flowing through the transistor unit 70 flows. As an example, the current sense unit 59 has the same structure as the transistor unit 70, and the area on the XY surface is smaller than that of the transistor unit 70. The current sense unit 59 may be arranged in the outer peripheral region 90. The well region 11 is not provided in the region where the current sense unit 59 is arranged. The Kelvin pad 57 is connected to the emitter electrode 52.

FIG. 1c is a diagram showing an arrangement example of the divided region 72. In FIG. 1c, the protective film 36, the emitter electrode 52, the transistor portion 70, and the diode portion 80 are omitted. The split region 72 refers to a portion of the active region 120 surrounded by the well region 11 in top view. The active region 120 may have a plurality of divided regions 72. The active region 120 of this example has a plurality of divided regions 72 in the X-axis direction. The active region 120 may have a plurality of divided regions 72 in the Y-axis direction.

The active region 120 of this example is divided into a plurality of divided regions 72-1, 72-2, 72-3, 72-4 by the well region 11. A plurality of openings 84 may be provided in at least one divided region 72. In this example, a plurality of openings 84 are provided in all the divided regions 72. The number of openings 84 provided in each divided region 72 may be the same or may be different. The larger the area of the divided region 72 in the top view, the larger the number of openings 84 provided in the divided region 72 may be.

The at least one divided region 72 may be sandwiched between the gate runner portion, and may be sandwiched between at least one of the gate runner portion, the temperature sense portion 78, and the temperature sense wiring 92. The divided region 72-1 is a divided region 72 arranged farthest from the control electrode portion 102 in the stretching direction (X-axis direction). The temperature sense unit 78 and the temperature sense wiring 92 are not arranged in the divided region 72-1. The divided region 72-1 is sandwiched between the gate metal layer 50 in the arrangement direction (Y-axis direction), and is sandwiched between the gate metal layer 50 and the gate runner 53 in the stretching direction (X-axis direction).

The division region 72-2 is a division region 72 arranged between the other two division regions 72 in the stretching direction (X-axis direction). The divided region 72-2 of this example is a region including the center of the upper surface of the semiconductor substrate 10 in the X-axis direction. A temperature sense unit 78 and a temperature sense wiring 92 are arranged in the divided region 72-2. The divided region 72-2 has a portion sandwiched between the gate metal layer 50 and the temperature sense portion 78 (and the temperature sense wiring 92) in the arrangement direction (Y-axis direction). .. The divided region 72-2 has a portion sandwiched between the gate runner 53 and the temperature sense portion 78 in the stretching direction (X-axis direction). The divided region 72-2 may be the divided region 72 having the largest area in the top view. The number of openings 84 provided in the divided region 72-2 may be larger than the number of openings 84 provided in any of the other divided regions 72.

The divided region 72-3 and the divided region 72-4 are divided regions arranged closest to the control electrode portion 102 in the stretching direction (X-axis direction). The divided region 72-3 and the divided region 72-4 are arranged so as to sandwich the temperature sense wiring 92 in the Y-axis direction. The divided region 72-3 and the divided region 72-4 are sandwiched between the gate metal layer 50 and the temperature sense wiring 92 in the arrangement direction (Y-axis direction), and the gate metal layer 50 and the gate in the stretching direction (X-axis direction). It is sandwiched between runners 53.

In this example, a plurality of openings 84 are arranged in each divided region 72. A bonding pad 98 is provided in each opening 84. That is, a plurality of bonding pads 98 are dispersedly provided in each of the divided regions 72. The bonding pad 98 is a region where wiring such as a metal wire that electrically connects the semiconductor device 100 and the outside of the semiconductor device 100 is bonded when the semiconductor device 100 is mounted on the package. The bonding pad 98 may be formed by plating a conductive metal on the emitter electrode 52 exposed by the opening 84. As the conductive metal, Ni (nickel) is used as an example.

The portion of the emitter electrode 52 exposed at the opening 84 may be used as the bonding pad 98. For example, the exposed surface of the emitter electrode 52 in the opening 84 when a wire such as aluminum is bonded to the surface of the emitter electrode 52 exposed by the opening 84 by ultrasonic bonding may be used as a bonding pad 98.

Like the division region 72-1, the plurality of openings 84 in one division region 72 may be arranged in a row along a predetermined direction (arrangement direction in the example of FIG. 1c). Further, as in the division region 72-2, the plurality of openings 84 in one division region 72 may be arranged along two or more directions (arrangement direction and extension direction in the example of FIG. 1c). The area of the opening 84 provided in one divided region 72 in the top view may be the same or different. The opening 84 provided in a certain division region 72 may be arranged at a position facing the opening 84 provided in another division region 72 adjacent to the division region 72 in the X-axis direction.

Further, the divided regions 72 arranged at both ends in the X-axis direction may be provided with one opening 84 in the X-axis direction. At least one divided region 72 arranged at other than both ends in the X-axis direction may be provided with two or more openings 84 in the X-axis direction. Further, in the divided region 72 provided with the temperature sense portion 78, two or more openings 84 may be arranged in the X-axis direction.

The width Wh1 is the width of the divided region 72-1 in the stretching direction (X-axis direction). The width Wh3 is the width of the divided region 72-3 and the divided region 72-4 in the X-axis direction. The width Wh1 and the width Wh3 may be equal.

The width Wh2 is the width of the divided region 72-2 in the X-axis direction. The width Wh2 may be larger than the width Wh1 and the width Wh3. The width Wh2, the width Wh1 and the width Wh3 may be the same.

FIG. 1d is a diagram illustrating the width of the openings 84 in the arrangement direction and the stretching direction. The width Wcx4 is the width of the opening 84 provided in the division region 72-1 in the X-axis direction. The width Wcx3 is the width of the opening 84 arranged on the side farthest from the control electrode portion 102 in the X-axis direction among the openings 84 provided in the divided region 72-2. The width Wcx2 is the width of the opening 84 arranged on the side closest to the control electrode portion 102 in the X-axis direction among the openings 84 provided in the divided region 72-2. The width Wcx1 is the width of the opening 84 provided in the divided region 72-3 and the divided region 72-4 in the X-axis direction.

The width Wcx1, the width Wcx2, the width Wcx3 and the width Wcx4 may all be equal. FIG. 1d is an example in which the width Wcx1, the width Wcx2, the width Wcx3, and the width Wcx4 are all equal. The width Wcx1, the width Wcx2, the width Wcx3 and the width Wcx4 may be partially or completely different. The width Wcx1 and the width Wcx4 may be equal, the width Wcx2 and the width Wcx3 may be equal, and the width Wcx1 and the width Wcx2 may be different. The width Wcx1, the width Wcx2, the width Wcx3 and the width Wcx4 may be 1000 μm or more and 3000 μm or less.

The width Wcy1 and the width Wcy4 are the widths of the openings 84 arranged at both ends in the Y-axis direction in the Y-axis direction. The width Wcy2 is the width of the opening 84 arranged next to the opening 84 of the width Wcy1 in the Y-axis direction. The width Wcy3h is the width in the Y-axis direction of the opening 84 arranged next to the opening 84 of the width Wcy4.

The width Wcy1, the width Wcy2, the width Wcy3 and the width Wcy4 may all be equal. FIG. 1d is an example in which the width Wcy1, the width Wcy2, the width Wcy3, and the width Wcy4 are all equal. The width Wcy1, the width Wcy2, the width Wcy3 and the width Wcy4 may be partially or completely different. The width Wcy1 and the width Wcy4 may be equal, the width Wcy2 and the width Wcy3 may be equal, and the width Wcy1 and the width Wcy2 may be different. The width Wcy1, width Wcy2, width Wcy3 and width Wcy4 may be 1500 μm or more and 5000 μm or less.

In the divided region 72 (divided region 72-2 in this example) sandwiched between the gate runners 53, three or more openings 84 are arranged in the direction sandwiched by the gate runner 53 (in the example, the stretching (X-axis) direction). May be done. The widths of the three or more openings 84 in the X-axis direction may be equal or different.

FIG. 1e is a diagram illustrating a separation region for separating each opening 84. In this example, the protective film 36 provided between the two openings 84 adjacent to each other in the arrangement direction (Y-axis direction) is referred to as the first separation region 86. The first separation region 86 may be provided so as to extend along the X-axis direction across the active region 120 in the X-axis direction.

The first separation region 86 may be provided over a plurality of openings 84 in the X-axis direction. In this example, the first separation region 86 is provided over four openings 84 in the X-axis direction. The first separation region 86 may be a part of the protective film 36 that remains after forming the opening 84 in the protective film 36. In this example, a plurality of first separation regions 86 are provided at different positions in the Y-axis direction. Each first separation region 86 separates openings 84 provided adjacent to each other in the arrangement direction in the XY plane.

In this example, in the top view of the semiconductor substrate 10, the protective film 36 provided between two openings 84 adjacent to each other in the stretching direction (X-axis direction in this example) orthogonal to the arrangement direction is provided in the second separation region 88. And. The second separation region 88 may be provided so as to extend along the Y-axis direction across the active region 120 in the Y-axis direction. The second separation region 88 may intersect the first separation region 86. The first separation region 86 and the second separation region 88 may be arranged in a grid pattern. The second separation region 88 may be provided over the plurality of openings 84 in the Y-axis direction. In this example, the second separation region 88 is provided over the four openings 84 in the Y-axis direction.

The second separation region 88 may be provided so as to be sandwiched between two openings 84 adjacent to each other in the stretching direction. The second separation region 88 may be a part of the protective film 36 that remains after forming the opening 84 in the protective film 36. In this example, a plurality of second separation regions 88 are provided at different positions in the X-axis direction. Each second separation region 88 separates two openings 84 provided adjacent to each other in the stretching direction in the XY plane.

The second separation region 88 may be at least partly arranged above the transistor portion 70 and the diode portion 80, and at least partly above the gate runner 53 or the gate metal layer 50, at least one. The portion may be arranged above the well region 11 (see FIG. 1b).

In this example, the second separation region 88 that separates the opening 84 of the division region 72-1 and the opening 84 of the division region 72-2 is arranged above the well region 11 (and the gate runner 53). And, it extends in the Y-axis direction along the well region 11 (and the gate runner 53). Further, the second separation region 88 that separates the opening 84 of the division regions 72-3 and 72-4 and the opening 84 of the division region 72-2 is arranged above the well region 11 (and the gate runner 53). And extends in the Y-axis direction along the well region 11 (and the gate runner 53). The second separation region 88 that crosses the division region 72-2 is arranged above the transistor portion 70 and the diode portion 80. In another example, all second separation regions 88 may be located along well regions 11. As a result, the area of the transistor portion 70 and the diode portion 80 covered by the opening 84 (that is, the bonding pad 98) can be increased.

The width Wdx1 is the width in the X-axis direction of the second separation region 88 that separates the opening 84 of the division regions 72-3 and 72-4 and the opening 84 of the division region 72-2. The width Wdx2 is the width of the second separation region 88 across the division region 72-2 in the X-axis direction. The width Wdx3 is the width in the X-axis direction of the second separation region 88 that separates the opening 84 of the division region 72-1 and the opening 84 of the division region 72-2.

The width Wdy1 and the width Wdy3 are the widths of the first separation regions 86 arranged at both ends in the Y-axis direction in the Y-axis direction among the plurality of first separation regions 86. The width Wdy2 is the width in the Y-axis direction of the first separation region 86 arranged at other than both ends in the Y-axis direction among the plurality of first separation regions 86. The width Wdy2 may be the width in the Y-axis direction of the first separation region 86 arranged in the center in the Y-axis direction among the plurality of first separation regions 86.

The width Wdx1 and the width Wdx3 may be equal, and the width Wdx1 and the width Wdx2 may be different. FIG. 1e is an example in which the width Wdx1 and the width Wdx3 are equal, but the width Wdx1 and the width Wdx2 are different. The width Wdx1, the width Wdx2 and the width Wdx3 may all be equal, and some or all may be different. The width Wdx1, the width Wdx2 and the width Wdx3 may be 100 μm or more and 400 μm or less.

The width Wdy1, the width Wdy2 and the width Wdy3 may all be equal. FIG. 1c is an example in which the width Wdy1, the width Wdy2, and the width Wdy3 are all equal. The width Wdy1, the width Wdy2 and the width Wdy3 may be partially or completely different. The width Wdy1 and the width Wdy3 may be equal, and the width Wdy1 and the width Wdy2 may be different. The width Wdy1 and the width Wdy2 may be equal, and the width Wdy1 and the width Wdy3 may be different. The width Wdy1, the width Wdy2 and the width Wdy3 may be 100 μm or more and 400 μm or less.

The width Wdy1, the width Wdy2, and the width Wdy3 may be smaller than the width WF of the diode portion 80 in the arrangement direction. Since the width Wdy1, the width Wdy2, and the width Wdy3 are smaller than the width WF, in the top view of the semiconductor substrate 10, the entire diode portion 80 in the Y-axis direction is formed regardless of the position of the first separation region 86 in the Y-axis direction. , It is not covered with the protective film 36 (first separation region 86). Therefore, the heat generated by the diode portion 80 during conduction or reverse recovery of the diode portion 80 can be easily dissipated to the emitter electrode 52.

The first separation region 86 may be arranged above the transistor portion 70. The first separation region 86 does not have to be arranged above the diode portion 80. Further, the first separation region 86 (that is, the protective film 36) may be sandwiched between adjacent openings 84, and the protective film 36 may be arranged above the transistor portion 70, and the transistor portion 70 may further be arranged. , May be sandwiched between two adjacent diode portions 80.
The width Wdy of the first separation region 86 in the Y-axis direction may be smaller than the width WI of the transistor unit 70 in the Y-axis direction. The width Wdy of the first separation region 86 in the Y-axis direction may be smaller than the width WF of the diode portion 80 in the Y-axis direction. In the semiconductor device 100 of this example, since the first separation region 86 is arranged above the transistor portion 70 and not above the diode portion 80, it is easy to release heat during reverse recovery of the diode portion 80.

In each of the divided regions 72, the first area where the opening 84 and the cathode region 82 overlap may be larger than the second area where the protective film 36 and the cathode region 82 overlap in the top view of the semiconductor substrate 10. The case where the first area is larger than the second area may include the case where the second area is zero, that is, the case where the region where the protective film 36 and the cathode region 82 overlap does not exist. Further, the second area where the protective film 36 and the cathode region 82 overlap may have a finite value which is not zero, and in this case, the first area where the opening 84 and the cathode region 82 overlap is the protective film 36 and the cathode. It may be larger than the second area where the region 82 overlaps. The area where the opening 84 and the cathode region 82 overlap may be 5 times or more the area where the protective film 36 and the cathode region 82 overlap, and may be 2 times or more.

In the example of FIG. 1e, among the plurality of divided regions 72, the divided regions 72 (divided regions 72-1, 72-3, 72-4) arranged at both ends in the X-axis direction are protected by the top view of the semiconductor substrate 10. The film 36 and the cathode region 82 do not overlap, but the opening 84 and the entire cathode region 82 overlap. In another example, in these divided regions 72, the protective film 36 and the cathode region 82 (or the diode portion 80) may overlap at least partially in the arrangement direction. In at least one divided region 72, the second separated region 88 may intersect the cathode region 82 in the top view of the semiconductor substrate 10. In this example, the second separation region 88 overlaps with the cathode region 82 in the division region 72-2.

In at least one divided region 72, the first area where the opening 84 and the cathode region 82 overlap is larger than the second area where the protective film 36 and the cathode region 82 overlap. The first area may be 10 times or more, or 20 times or more, the second area.

In this example, in each of the divided regions 72, the first area where the opening 84 and the cathode region 82 overlap is larger than the second area where the protective film 36 and the cathode region 82 overlap. Therefore, the heat generated at the time of reverse recovery of the diode portion 80 or the like can be easily dissipated through the bonding pad 98 or the like.

In the semiconductor device 100 of this example, the bonding pad 98 is arranged in each of the plurality of openings 84 provided in the protective film 36. The bonding pad 98 may be provided in all openings 84. The bonding pad 98 is separated in the XY plane by the first separation region 86 and the second separation region 88.

A plurality of bonding pads 98 may be arranged above at least one divided region 72 in the stretching direction (in this example, the X-axis direction). In this example, in the divided region 72-2, a plurality of bonding pads 98 are arranged along the stretching direction (X-axis direction).

At least one diode portion 80 may be provided below the plurality of openings 84. That is, one diode portion 80 continuously formed in the stretching direction (X-axis direction) may be arranged so as to overlap with two or more openings 84 discretely arranged in the X-axis direction. In this example, in the divided region 72-2, the diode portions 80 are provided below each of the plurality of bonding pads 98 provided along the X-axis direction. In the divided regions 72-1, 72-3, and 72-4 of this example, one diode portion 80 is provided so as to overlap with one bonding pad 98 in the X-axis direction.

In the arrangement direction (Y-axis direction), one or more diode portions 80 are provided so as to overlap with one opening 84. The end portion of the opening portion 84 in the arrangement direction may be provided at a position where the opening portion 84 does not overlap with the diode portion 80 but overlaps with the transistor portion 70. Each opening 84 may be arranged so as to cover the entire width of at least one diode portion 80 in the arrangement direction. Further, in each of the divided regions 72, each of the plurality of diode portions 80 provided in the arrangement direction may be arranged at least partially below the opening 84.

Further, in at least one divided region 72, the number of the diode portions 80 discretely provided in the arrangement direction may be larger than the number of the first separation regions 86 discretely provided in the arrangement direction. For example, in the division region 72-1, eight diode portions 80 are provided in the arrangement direction, and three first separation regions 86 are provided in the arrangement direction. In all the divided regions 72, the number of the diode portions 80 discretely provided in the arrangement direction may be larger than the number of the first separated regions 86 discretely provided in the arrangement direction. As a result, heat generated during reverse recovery of the diode portion 80 and the like can be easily dissipated above the semiconductor substrate 10.

In FIG. 1e, the width WI is the width of the transistor portions 70 in the arrangement direction (Y-axis direction). The width WF is the width of the diode portions 80 in the arrangement direction. The width WI may be larger than the width WF. The width WI may be 2 times or more and 5 times or less the width WF. The width WI is, for example, three times the width WF.

The width WI may be 1200 μm or more and 1800 μm or less. The width WI is 1500 μm as an example. The width WF may be 100 μm or more and 900 μm or less. The width WF is, for example, 500 μm.

If the widths of the transistor portion 70 and the diode portion 80 arranged in the arrangement direction in the stretching direction are the same, the ratio of the width WI to the width WF is the area ratio of all the transistor portions 70 and all the diode portions 80. The area ratio of all the diode portions 80 to all the transistor portions 70 may be 1/12 or more and 1/2 or less.

On the other hand, when the diode portion 80 is arranged so as to be surrounded by the inside of the transistor portion 70, the area ratio of the diode portion 80 to the transistor portion 70 and the ratio of the width WI and the width WF may be different. Even in such a case, the area ratio of all the diode portions 80 to the area of all the transistor portions 70 may be 1/12 or more and 1/2 or less.

FIG. 2 is a diagram showing an upper surface in another example of the semiconductor device 100. In the semiconductor device 100 of this example, the arrangement of the openings 84 provided in the protective film 36 is different from the examples described in FIGS. 1a to 1e. With the arrangement of the openings 84, the arrangement of the bonding pad 98 and the arrangement of the first separation region 86 and the second separation region 88 are also different from the examples described in FIGS. 1a to 1e. Other structures are similar to the examples described in FIGS. 1a-1e.

In this example, the width of the opening 84 provided in the divided region 72-2 in the stretching direction (X-axis direction) is smaller than the width of the opening 84 provided in the other divided region 72 in the stretching direction. The width of each opening 84 provided in the divided region 72-2 may be the same or different. The width of each opening 84 in the arrangement direction (Y-axis direction) is the same as the example described in FIGS. 1a to 1e. Further, the width of the second separation region 88 provided in the division region 72-2 in the stretching direction (X-axis direction) may be smaller than the width of the other second separation region 88.

With such a configuration, the opening 84 and the bonding pad 98 having a relatively small area can be arranged in the divided region 72-2. Therefore, the above-mentioned bias of the pressure distribution in the divided region 72-2 having a relatively large area can be further dispersed, and the contact surface between the bonding pad 98 and the solder portion and the contact surface between the solder portion and the metal plate for the electrode. The pressure distribution can be made uniform. As described above, it is possible to suppress the characteristic defect of the semiconductor device 100 and reduce the assembly defect of the semiconductor device 100.

FIG. 3 is a diagram showing the upper surface of the semiconductor device 150 of the comparative example. In FIG. 3, components having the same structure as the semiconductor device 100 are designated by the same reference numerals as those of the semiconductor device 100. The semiconductor device 150 includes a protective film 236 provided with a plurality of openings 284. Further, the semiconductor device 150 includes a plurality of divided regions 172 surrounded by the well region 11.

In the semiconductor device 150, one opening 284 is provided in one division region 172. Therefore, when the bonding pad thermally expands due to heat generated during the operation of the transistor portion 70 and the diode portion 80, the solder portion in contact with the upper surface of the bonding pad, the metal plate for the electrode of the package in contact with the upper surface of the solder portion, and the like. The pressure distribution tends to be biased. On the other hand, in the semiconductor device 100, since the plurality of openings 84 are provided in one divided region 72, the pressure distribution can be made more uniform.

FIG. 4 is an enlarged view of the region A in FIG. 1b. The region A is a region including the active region 120 to the outer peripheral end 140 in the X-axis direction. The region A includes a part on the outer peripheral end 140 side of two diode portions 80 adjacent to each other in the Y-axis direction and a part on the outer peripheral end 140 side of the transistor portion 70 sandwiched between the two diode portions 80 in the Y-axis direction. Area containing.

The semiconductor device 100 of this example is provided inside the semiconductor substrate 10 and is exposed on the upper surface of the semiconductor substrate 10, a gate trench portion 40, a dummy trench portion 30, a well region 11, an emitter region 12, a base region 14, and a contact. A region 15 is provided. Further, the semiconductor device 100 of this example includes an emitter electrode 52 and a gate metal layer 50 provided above the upper surface of the semiconductor substrate 10. The emitter electrode 52 and the gate metal layer 50 are provided separately from each other.

An interlayer insulating film is provided between the emitter electrode 52 and the gate metal layer 50 and the upper surface of the semiconductor substrate 10, but this is omitted in FIG. The interlayer insulating film of this example is provided with a contact hole 56, a contact hole 49, and a contact hole 54 penetrating the interlayer insulating film.

The emitter electrode 52 is connected to the dummy conductive portion in the dummy trench portion 30 through the contact hole 56. A connecting portion 25 made of a conductive material such as polysilicon doped with impurities may be provided between the emitter electrode 52 and the dummy conductive portion. An insulating film such as an oxide film is provided between the connection portion 25 and the upper surface of the semiconductor substrate 10.

The gate metal layer 50 passes through the contact hole 49 and comes into contact with the gate runner 48. The gate runner 48 may be provided so as to overlap the gate metal layer 50 in the top view of the semiconductor substrate 10. The gate runner 48 may be provided in a circumferential shape around the active region 120 so as to overlap with the circumferential gate metal layer 50 provided surrounding the active region 120 in a top view of the semiconductor substrate 10.

The gate runner 48 is formed of polysilicon or the like doped with impurities. The gate runner 48 is connected to the gate conductive portion in the gate trench portion 40 on the upper surface of the semiconductor substrate 10. The gate runner 48 is not connected to the dummy conductive portion in the dummy trench portion 30.

The gate runner 48 of this example is formed from below the contact hole 49 to the tip of the gate trench portion 40. An insulating film such as an oxide film is formed between the gate runner 48 and the upper surface of the semiconductor substrate 10.

At the tip of the gate trench portion 40, the upper surface side of the semiconductor substrate 10 is exposed in the gate conductive portion. The gate trench portion 40 comes into contact with the gate runner 48 at the exposed portion of the gate conductive portion.

The emitter electrode 52 and the gate metal layer 50 may have a barrier metal formed of titanium, a titanium compound, or the like in the lower layer of a region formed of aluminum or the like. The barrier metal will be described later. Further, the emitter electrode 52 and the gate metal layer 50 may have a plug made of tungsten or the like in the contact hole.

The one or more gate trench portions 40 and the one or more dummy trench portions 30 are arranged at predetermined intervals along a predetermined arrangement direction (Y-axis direction in this example). The gate trench portion 40 of this example has two stretched portions 39 and two stretched portions that are parallel to the upper surface of the semiconductor substrate 10 and stretched along a stretching direction (X-axis direction in this example) perpendicular to the arrangement direction. It may have a connecting portion 41 connecting the 39. It is preferable that at least a part of the connecting portion 41 is formed in a curved shape. By connecting the ends of the two stretched portions 39 of the gate trench portion 40, the electric field concentration at the ends of the stretched portion 39 can be relaxed. In the present specification, each extended portion 39 of the gate trench portion 40 may be treated as one gate trench portion 40. The gate runner 48 may be connected to the gate conductive portion at the connecting portion 41 of the gate trench portion 40.

Like the gate trench portion 40, the dummy trench portion 30 of this example may have a U-shape on the upper surface of the semiconductor substrate 10. That is, the dummy trench portion 30 of this example may have two stretching portions 29 extending along the stretching direction and a connecting portion 31 connecting the two stretching portions 29.

The emitter electrode 52 is formed above the gate trench portion 40, the dummy trench portion 30, the well region 11, the emitter region 12, the base region 14, and the contact region 15. The well region 11 is formed in a predetermined range from the end of the active region 120 on the side where the gate metal layer 50 is provided. The diffusion depth of the well region 11 may be deeper than the depth of the gate trench portion 40 and the dummy trench portion 30. A part of the gate trench portion 40 and the dummy trench portion 30 on the gate metal layer 50 side is formed in the well region 11. The bottoms of the ends of the gate trench portion 40 and the dummy trench portion 30 in the extending direction may be covered with the well region 11.

In the plane parallel to the upper surface of the semiconductor substrate 10, a mesa portion is provided adjacent to each trench portion in the Y-axis direction. The mesa portion is a portion of the semiconductor substrate 10 sandwiched between two adjacent trench portions. The mesa portion may be a portion from the upper surface of the semiconductor substrate 10 to the depth of the deepest bottom portion of each trench portion. The region sandwiched between the extended portions of the two adjacent trench portions may be used as the mesa portion.

In the transistor portion 70, a first mesa portion 60 is provided adjacent to each trench portion. At the boundary portion 71, the second mesa portion 62 is provided in the region sandwiched between the adjacent dummy trench portions 30. In the diode portion 80, the third mesa portion 64 is provided in the region sandwiched between the adjacent dummy trench portions 30.

As an example, both ends of the first mesa portion 60, the second mesa portion 62, and the third mesa portion 64 in the X-axis direction are exposed on the upper surface of the semiconductor substrate 10 and the base region 14-e of the second conductive type is exposed. Is provided. The base region 14 of this example is P-type as an example. Note that FIG. 4 shows only one end of the base region 14 in the X-axis direction.

An emitter region 12 is provided on the upper surface of the first mesa portion 60 in contact with the gate trench portion 40. The emitter region 12 of this example is the first conductive type. The emitter region 12 of this example is N + type as an example. The doping concentration in the emitter region 12 is higher than the doping concentration in the drift region.

The emitter region 12 may be provided in the Y-axis direction from one of the two trench portions extending in the X-axis direction across the first mesa portion 60 to the other. The emitter region 12 is also provided below the contact hole 54.

The emitter region 12 may or may not be in contact with the dummy trench portion 30. In this example, the emitter region 12 is provided in contact with the dummy trench portion 30.

On the upper surface of the first mesa portion 60, a second conductive type contact region 15 having a doping concentration higher than that of the base region 14 is provided. The contact region 15 of this example is a P + type as an example.

In the first mesa portion 60, the emitter region 12 and the contact region 15 may be provided alternately in the stretching direction of the gate trench portion 40. The contact region 15 may be provided in the Y-axis direction from one of the two trench portions extending in the X-axis direction across the first mesa portion 60 to the other. The contact area 15 is also provided below the contact hole 54.

The contact region 15 may or may not be in contact with the gate trench portion 40. Further, the contact region 15 may or may not be in contact with the dummy trench portion 30. In this example, as an example, the contact region 15 is provided in contact with the dummy trench portion 30 and the gate trench portion 40.

A contact region 15 is provided on the upper surface of the second mesa portion 62. The area of the contact region 15 provided on the upper surface of one second mesa portion 62 is larger than the area of the contact region 15 provided on the upper surface of one first mesa portion 60. The area of the contact region 15 provided on the upper surface of one second mesa portion 62 may be larger than the area of the contact region 15 provided on the upper surface of one third mesa portion 64. In the second mesa portion 62, the contact region 15 is also provided below the contact hole 54.

The contact region 15 on the upper surface of the second mesa portion 62 may be provided over the entire region sandwiched between the base regions 14-e provided at both ends of the second mesa portion 62 in the X-axis direction. The second mesa section 62 effectively pulls out the carrier at the time of turn-off as compared with the first mesa section 60.

On the upper surface of the third mesa portion 64, contact regions 15 are provided at both ends in the X-axis direction. Further, on the upper surface of the third mesa portion 64, a base region 14 is provided in a region sandwiched between contact regions 15 provided at both ends of the third mesa portion 64 in the X-axis direction. The base region 14 may be provided over the entire region sandwiched between the contact regions 15 in the X-axis direction. In the third mesa portion 64, the base region 14 is also provided below the contact hole 54. The contact area 15 may also be provided below the contact hole 54.

In the third mesa portion 64, a contact region 15 and a base region 14 are formed from one dummy trench portion 30 sandwiching the third mesa portion 64 to the other dummy trench portion 30. That is, on the upper surface of the semiconductor substrate 10, the width of the third mesa portion 64 in the Y-axis direction and the width of the contact region 15 or the base region 14 provided in the third mesa portion 64 in the Y-axis direction are equal.

The emitter region 12 does not have to be formed in the third mesa portion 64, and may be formed. In this example, the emitter region 12 is not formed in the third mesa portion 64.

In the semiconductor device 100 of this example, a dummy trench portion 30 is provided in the diode portion 80. The linear extending portions 29 of the adjacent dummy trench portions 30 may be connected by the connecting portion 31. The third mesa portion 64 is a region sandwiched between the respective dummy trench portions 30.

The diode portion 80 has a first conductive type cathode region 82 on the lower surface side of the semiconductor substrate 10. The cathode region 82 of this example is N + type as an example. In FIG. 4, a region where the cathode region 82 is provided in the top view of the semiconductor substrate 10 is shown by a broken line portion. The diode portion 80 may be a region in which the cathode region 82 is projected onto the upper surface of the semiconductor substrate 10. Further, the diode portion 80 may include the entire third mesa portion 64 in which the cathode region 82 is partially provided and the dummy trench portion 30 adjacent to the third mesa portion 64. The region in which the cathode region 82 is projected onto the upper surface of the semiconductor substrate 10 may be separated from the contact region 15 on the positive side in the X-axis direction.

The transistor portion 70 has collector regions 22 provided on the lower surface side of the semiconductor substrate 10 at both ends in the Y-axis direction. The collector region 22 of this example is a second conductive type. The collector area 22 of this example is a P + type as an example. The collector region 22 may be provided adjacent to the cathode region 82.

In the transistor portion 70 excluding the boundary portion 71, the contact hole 54 is formed above each region of the contact region 15 and the emitter region 12. In the transistor portion 70 excluding the boundary portion 71, the contact hole 54 is the most in the X-axis direction from above the contact region 15 provided on the most negative side in the X-axis direction of the first mesa portion 60 in the top view of the semiconductor substrate 10. It may be continuously provided up to the upper part of the contact area 15 provided on the positive side. The contact hole 54 may be provided so as to overlap with at least a part of the contact region 15 provided on the most negative side in the X-axis direction of the first mesa portion 60 in the top view of the semiconductor substrate 10. The contact hole 54 may be provided so as to overlap with at least a part of the contact region 15 provided on the most positive side in the X-axis direction of the first mesa portion 60 in the top view of the semiconductor substrate 10.

At the boundary portion 71, the contact hole 54 is formed above the contact region 15. At the boundary portion 71, the contact hole 54 may be continuously provided in the X-axis direction above the contact region 15 provided in the second mesa portion 62 in the top view of the semiconductor substrate 10.

In the diode portion 80, the contact hole 54 is formed above the base region 14 and the contact region 15. In the diode portion 80, the contact hole 54 is provided on the most positive side in the X-axis direction from above the contact region 15 provided on the most negative side in the X-axis direction of the third mesa portion 64 in the top view of the semiconductor substrate 10. It may be continuously provided up to the upper part of the contact area 15. The contact hole 54 may be provided so as to overlap with at least a part of the contact region 15 provided on the negative side in the X-axis direction of the third mesa portion 64 in the top view of the semiconductor substrate 10. The contact hole 54 may be provided so as to overlap with at least a part of the contact region 15 provided on the positive side in the X-axis direction of the third mesa portion 64 in the top view of the semiconductor substrate 10.

Inside the semiconductor substrate 10, a first conductive type storage region 16 may be provided below the base region 14. The storage region 16 is a region in which the dopant is stored at a higher concentration than the drift region. That is, the doping concentration in the accumulation region 16 is higher than the doping concentration in the drift region. The storage area 16 of this example is N + type as an example. By providing the storage region 16, it is possible to enhance the carrier injection promoting effect (IE effect) and reduce the on-voltage of the transistor portion 70. In FIG. 4, the range in which the storage region 16 is formed is shown by a broken line. The storage region 16 may be formed on the −X axis direction side from the region where the contact region 15 at the end in the + X axis direction and the contact hole 54 overlap in the top view of the semiconductor substrate 10.

A guard ring 93 is provided in the outer peripheral region 90. The guard ring 93 is a second conductive type. The guard ring 93 of this example is a P + type as an example. The guard ring 93 relaxes the electric field concentration on the upper surface side of the semiconductor substrate 10.

A plurality of guard rings 93 may be provided. In this example, three guard rings 93-1, guard ring 93-2, and guard ring 93-3 are provided as an example. The guard ring 93 may be provided in a circumferential shape so as to overlap with the outer peripheral region 90 provided so as to surround the active region 120 in the top view of the semiconductor substrate 10.

In FIG. 4, the boundary position between the protective film 36 and the opening 84 is shown by a alternate long and short dash line. The protective film 36 may be provided from the well region 11 to the emitter region 12 side. The protective film 36 of this example covers at least one emitter region 12 in the X-axis direction, but in another example, the protective film 36 may be provided at a position that does not overlap with the emitter region 12. The protective film 36 of this example covers at least one contact region 15 in the X-axis direction, but in another example, the protective film 36 may be provided at a position that does not overlap with the contact region 15. The end of the protective film 36 in the X-axis direction may be located above the base region 14-e.

Further, in the example of FIG. 4, the protective film 36 is provided up to a position overlapping with the cathode region 82 in the stretching direction (X-axis direction). That is, the end portion of the cathode region 82 on the outer peripheral end 140 side in the stretching direction may be located inside the protective film 36 in a top view. In another example, the protective film 36 may be provided at a position that does not overlap with the cathode region 82 as schematically shown in FIG. 1a and the like.

FIG. 5 is an enlarged view of the region B in FIG. 1b. FIG. 5 shows an enlarged view of the vicinity of the transistor portion 70 and the diode portion 80 provided on both sides of the gate runner 53 in the X-axis direction. On both sides of the gate runner 53 in the X-axis direction, the transistor portion 70 and the diode portion 80 have the same structure as the vicinity of the gate runner 48 shown in FIG. For example, the connection portion 41 of the gate trench portion 40 is provided at a position overlapping the gate runner 53.

In the region B, the well region 11 is provided so as to extend in the Y-axis direction along the gate runner 53. The gate runner 53 is connected to the conductive portion of the gate trench portion 40 and supplies a gate voltage to the gate trench portion 40. The gate runner 53 of this example is connected to a circular gate runner 48 provided surrounding the active region 120.

The positions of the ends of the protective film 36 and the opening 84 in the X-axis direction may be the same as those of the opening 84 in FIG. That is, the protective film 36 may be provided from the well region 11 to the emitter region 12 side. The protective film 36 of this example covers at least one emitter region 12 in the X-axis direction, but in another example, the protective film 36 may be provided at a position that does not overlap with the emitter region 12. The protective film 36 of this example covers at least one contact region 15 in the X-axis direction, but in another example, the protective film 36 may be provided at a position that does not overlap with the contact region 15. The end of the protective film 36 in the X-axis direction may be located above the base region 14-e.

The positions of the ends of the protective film 36 and the opening 84 in the Y-axis direction may be provided at positions overlapping with the transistor portion 70. The end portion of the opening 84 in the Y-axis direction may be arranged above the second mesa portion 62 or above the first mesa portion 60, with the second mesa portion 62 and the first mesa portion 60. It may be placed above the trench portion between.

FIG. 6a is a diagram showing an example of a'a'cross section in FIG. The aa'cross section is an XZ plane passing through a part of two openings 84 adjacent to each other in the X-axis direction in the transistor portion 70 and a second separation region 88 arranged between the two openings 84.

The semiconductor substrate 10 includes a first conductive type drift region 18. The drift region 18 of this example is N-type as an example. The drift region 18 may be a region remaining in the semiconductor substrate 10 without being provided with another doping region.

The semiconductor substrate 10 may be a silicon substrate, a silicon carbide substrate, a nitride semiconductor substrate such as gallium nitride, a gallium oxide substrate, or the like. The semiconductor substrate 10 of this example is a silicon substrate.

A first conductive type buffer region 20 may be provided below the drift region 18. The buffer area 20 of this example is an N + type as an example. The doping concentration in the buffer region 20 is higher than the doping concentration in the drift region 18. The buffer region 20 may function as a field stop layer that prevents the depletion layer extending from the lower surface side of the base region 14 from reaching the P + type collector region 22 and the N + type cathode region 82.

Below the buffer region 20, a collector region 22 is provided exposed on the lower surface 23 of the semiconductor substrate 10. A collector electrode 24 is provided on the lower surface 23. The collector electrode 24 is made of a conductive material such as metal.

Above the drift region 18, a well region 11 and a base region 14-e are provided exposed on the upper surface 21 of the semiconductor substrate 10. The well region 11 is provided so as to be sandwiched between the two base regions 14-e in the X-axis direction.

An interlayer insulating film 38 is provided above the well region 11 in contact with the upper surface 21. The width of the interlayer insulating film 38 in the X-axis direction may be smaller than the width of the well region 11 in the X-axis direction.

A gate runner 53 is provided above the well region 11 at a distance from the upper surface 21. The gate runner 53 may be provided so as to be surrounded by the interlayer insulating film 38 in the XZ plane. The gate runner 53 may be provided in a trench shape inside the well region 11.

Emitter electrodes 52 are provided above the upper surface 21 on both sides of the interlayer insulating film 38 in the X-axis direction. The emitter electrode 52 may also be provided on the interlayer insulating film 38.

A protective film 36 is provided above the emitter electrode 52. The protective film 36 may also be provided in a region sandwiched between the two emitter electrodes 52.

A bonding pad 98 is arranged in contact with the upper surface of the emitter electrode 52 in the opening 84 provided in the protective film 36. The opening 84 may be provided above the emitter electrode 52. The bonding pad 98 may be formed by plating the upper surface of the emitter electrode 52 with a conductive metal such as Ni (nickel).

An antioxidant film 28 made of a metal such as Au may be provided on the upper surface of the bonding pad 98. The antioxidant film 28 prevents oxidation of the bonding pad 98. The antioxidant film 28 may be formed by plating the upper surface of the bonding pad 98 with a metal such as Au.

The width WE is the thickness of the emitter electrode 52 in the Z-axis direction. The width Wp is the thickness of the protective film 36 provided on the upper surface of the emitter electrode 52 in the Z-axis direction. The width Wmk is the thickness of the bonding pad 98 provided on the upper surface of the emitter electrode 52 in the Z-axis direction.

The widths Wmk of the two bonding pads 98 arranged so as to sandwich the protective film 36 in the X-axis direction in the Z-axis direction may be equal. The widths Wmk of all the bonding pads 98 arranged in the respective openings 84 in the Z-axis direction may be equal. In another example, the width Wmk of at least some of the bonding pads 98 in the Z-axis direction may be different from the width Wmk of the other bonding pads 98.

The width WE may be equal to or different from the width Wp. The width Wmk may be smaller than the width Wp. The width WE and the width Wp may be 2 μm or more and 10 μm or less. The width WE and the width Wp are, for example, 5 μm. The width Wmk may be 1 μm or more and 8 μm or less. The width Wmk is 4 μm as an example.

A plating portion 110 may be provided below the collector electrode 24 in contact with the lower surface of the collector electrode 24. The width, that is, the thickness of the plating portion 110 in the Z-axis direction may be equal to the width Wmk of the bonding pad 98.

FIG. 6b is a diagram showing an example of a bb'cross section in FIG. The bb'cross section is a YZ plane that passes through the emitter region 12 of the transistor portion 70. The semiconductor device 100 of this example has a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, and a collector electrode 24 in a bb'cross section. The emitter electrode 52 is provided above the upper surface 21 and the upper surface of the interlayer insulating film 38. The emitter electrode 52 may be connected to the semiconductor substrate 10 via the contact hole 54. The contact hole 54 may be provided with a barrier metal 26 in which one or more titanium films and one or more titanium nitride films are laminated. Further, the contact hole 54 may be provided with a plug made of tungsten.

The upper surface 21 of the semiconductor substrate 10 is provided with one or more gate trench portions 40 and one or more dummy trench portions 30. Each trench portion is provided from the upper surface 21 through the base region 14 and reaches the drift region 18.

The gate trench portion 40 has a gate trench provided on the upper surface 21, a gate insulating film 42, and a gate conductive portion 44. The gate insulating film 42 is provided so as to cover the inner wall of the gate trench. The gate insulating film 42 may be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench. The gate conductive portion 44 is provided inside the gate trench inside the gate insulating film 42. That is, the gate insulating film 42 insulates the gate conductive portion 44 and the semiconductor substrate 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon.

The gate conductive portion 44 includes a region facing at least the adjacent base region 14 with the gate insulating film 42 interposed therebetween in the depth direction. The gate trench portion 40 in the cross section is covered with the interlayer insulating film 38 on the upper surface 21. When a predetermined voltage is applied to the gate conductive portion 44, a channel due to an electron inversion layer is formed on the surface layer of the interface of the base region 14 in contact with the gate trench portion 40.

The dummy trench portion 30 may have the same structure as the gate trench portion 40 in the cross section. The dummy trench portion 30 has a dummy trench, a dummy insulating film 32, and a dummy conductive portion 34 provided on the upper surface 21 side. The dummy insulating film 32 is provided so as to cover the inner wall of the dummy trench. The dummy conductive portion 34 is provided inside the dummy trench and inside the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 and the semiconductor substrate 10.

The dummy conductive portion 34 may be formed of the same material as the gate conductive portion 44. For example, the dummy conductive portion 34 is formed of a conductive material such as polysilicon. The dummy conductive portion 34 may have the same length as the gate conductive portion 44 in the depth direction. The dummy trench portion 30 in the cross section is covered with the interlayer insulating film 38 on the upper surface 21. The bottom portions of the dummy trench portion 30 and the gate trench portion 40 may be curved downward (curved in cross section).

In the first mesa portion 60, an accumulation region 16 may be provided above the drift region 18 in contact with the gate trench portion 40. The storage region 16 is a region in which the dopant is stored at a higher concentration than the drift region 18. By providing the storage region 16, it is possible to enhance the carrier injection promoting effect (IE effect) and reduce the on-voltage of the transistor portion 70.

In the first mesa portion 60, the accumulation region 16 may be in contact with the dummy trench portion 30, but may be separated from the dummy trench portion 30. FIG. 6b shows an example in which the storage region 16 is provided in contact with the dummy trench portion 30.

The first mesa portion 60 is provided with an emitter region 12 in contact with the upper surface 21 and in contact with the gate trench portion 40. As shown in FIG. 5, the first mesa portion 60 may be provided with the emitter region 12 and the contact region 15 alternately along the X-axis direction.

A protective film 36 is provided on the upper surface of the emitter electrode 52. A bonding pad 98 is arranged in contact with the upper surface of the emitter electrode 52 in the opening 84 provided in the protective film 36. An antioxidant film 28 may be provided on the upper surface of the bonding pad 98. The bonding pad 98 is nickel-plated as an example.

FIG. 7 is a diagram showing an example of the upper surface of the semiconductor device 100 according to the present embodiment. FIG. 7 shows a solder portion 99 provided above the protective film 36 in the semiconductor device 100 shown in FIG. 1a. In FIG. 7, the solder portion 99 is hatched with diagonal lines. Further, in FIG. 7, the hatching of the protective film 36 is omitted. Further, the illustration of the divided region 72 is omitted. Further, the position where the opening 84 is provided in the top view of the semiconductor substrate 10 is indicated by the alternate long and short dash line portion.

The semiconductor device 100 of this example further includes a solder portion 99 for electrically connecting the plurality of bonding pads 98 above the bonding pads 98 arranged in the plurality of openings 84. The solder portion 99 is connected to the emitter electrode terminal of the package. The emitter electrode terminal of the package may be, for example, a lead frame or a metal plate such as copper or molybdenum molded to a predetermined thickness.

In this example, as an example, the solder portion 99 electrically connects all of the bonding pads 98 provided in the semiconductor device 100. In another example, the semiconductor device 100 may include a plurality of solder portions 99. Each solder portion 99 is connected to one or more bonding pads 98. Each of the bonding pads 98 provided in the semiconductor device 100 may be connected to any solder portion 99.

The end portion E is an end portion of the opening portion 84 arranged at the end of the plurality of openings 84 in the Y-axis direction on the outer peripheral end 140 side in the Y-axis direction. The end E may be the end of the bonding pad 98. When the bonding pad 98 is formed by plating, the end portion E may be the end portion of the plating portion provided at the end in the Y-axis direction.

The end portion F is an end portion of the opening portion 84 arranged at the end of the plurality of openings 84 in the X-axis direction on the outer peripheral end 140 side in the X-axis direction. The end portion F may be the end portion of the bonding pad 98. When the bonding pad 98 is formed by plating, the end portion F may be the end portion of the plating portion provided at the end in the X-axis direction.

The end portion G is an end portion of the solder portion 99 in the Y-axis direction. The end portion H is an end portion of the solder portion 99 in the X-axis direction.

The end portion G may be arranged between the end portion E and the outer peripheral end 140 in the top view of the semiconductor substrate 10. The end portion H may be arranged between the end portion F and the outer peripheral end 140 in the top view of the semiconductor substrate 10. Further, the end portion G and the end portion H may be arranged on the inner peripheral side of the inner end 95 of the edge termination region. The edge termination region is an region provided with a pressure resistant structure such as a guard ring, a field plate, and a resurf.

The end portion G is arranged between the end portion E and the outer peripheral end 140, and the end portion H is arranged between the end portion F and the outer peripheral end 140, so that the solder portion 99 is provided on the lower surface 23 side. It becomes difficult to come into contact with the portion 110. Therefore, it is possible to prevent a short circuit between the solder portion 99 and the plating portion 110. Further, the edge end region has a voltage higher than that of the emitter electrode 52 toward the outer peripheral end 140. Therefore, if the solder portion 99 protrudes from the edge end region to the outer peripheral side, there is a risk of electric discharge. Therefore, by locating the solder portion 99 on the inner peripheral side of the inner end 95 of the edge end region, discharge can be suppressed.

Further, the end portion H on the control electrode portion 102 side may be located on the inner peripheral side of the control electrode portion 102. The control electrode unit 102 is connected to each control terminal of the package. Therefore, the solder portion 99 may be provided so as to be retracted to the inner peripheral side from the control electrode portion 102 so that the solder portion 99 does not come into contact with the control electrode portion 102 and cause a short circuit.

FIG. 8a is a diagram showing the structure shown in FIG. 6a with the solder portion 99 added. As described with reference to FIG. 7, the solder portion 99 of this example is provided above the protective film 36 and the bonding pad 98.

The width Whd is the thickness of the solder portion 99 in the Z-axis direction. The width Whd may be 20 times or more, 10 times or more, or 5 times or more the width Wp.

The width Whd may be equal at different positions in the XY plane of the solder section 99. That is, the thickness of the solder portion 99 may be the same over the entire solder portion 99 in FIG. 7.

The width Whd may be 100 μm or more, 50 μm or more, or 25 μm or more. The width Whd of this example is 100 μm as an example.

FIG. 8b is a diagram showing the structure shown in FIG. 6b with the solder portion 99 added. As described with reference to FIG. 7, the solder portion 99 of this example is provided above the protective film 36 and the bonding pad 98.

In this example, the case where the semiconductor device 100 is a trench type gate has been described, but the same effect as in this example is also obtained in the case of a planar type gate semiconductor device in which the gate electrode and the channel are provided in the direction parallel to the upper surface 21. Can be obtained.

Although the present invention has been described above using the embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various changes or improvements can be made to the above embodiments. It is clear from the description of the claims that the form with such changes or improvements may be included in the technical scope of the present invention.

The order of execution of each process such as operation, procedure, step, and step in the apparatus, system, program, and method shown in the claims, specification, and drawings is particularly "before" and "prior to". It should be noted that it can be realized in any order unless the output of the previous process is used in the subsequent process. Even if the scope of claims, the specification, and the operation flow in the drawings are explained using "first", "next", etc. for convenience, it means that it is essential to carry out in this order. It's not a thing.

10 ... Semiconductor substrate, 11 ... Well region, 12 ... Emitter region, 14 ... Base region, 15 ... Contact region, 16 ... Storage region, 18 ... Drift region, 20 ... Buffer area, 21 ... Top surface, 22 ... Collector area, 23 ... Bottom surface, 24 ... Collector electrode, 25 ... Connection part, 26 ... Barrier metal, 28 ... Antioxidant film, 29 ... Stretched part, 30 ... Dummy trench part, 31 ... Connection part, 32 ... Dummy insulating film, 34 ... Dummy conductive part, 36 ... Protective film, 38 ... Interlayer insulating film, 39 ... Stretched part, 40 ... Gate trench part, 41 ... Connection part, 42 ... Gate insulating film, 44 ... Gate conductive part, 48 ... Gate Runner, 49 ... contact hole, 50 ... gate metal layer, 52 ... emitter electrode, 53 ... gate runner, 54 ... contact hole, 55 ... gate pad, 56 ... contact Hall, 57 ... Kelvin pad, 58 ... Current sense pad, 59 ... Current sense part, 60 ... 1st mesa part, 62 ... 2nd mesa part, 64 ... 3rd mesa Unit, 70 ... Transistor part, 71 ... Boundary part, 72 ... Divided region, 78 ... Temperature sense part, 80 ... Diode part, 82 ... Cathode region, 84 ... Opening Unit, 86 ... 1st separation area, 88 ... 2nd separation area, 89 ... wiring, 90 ... outer peripheral area, 91 ... wiring, 92 ... temperature sense wiring, 93 ...・ Guard ring, 93-1 ・ ・ ・ guard ring, 93-2 ・ ・ ・ guard ring, 93-3 ・ ・ ・ guard ring, 94 ・ ・ ・ temperature measurement pad, 95 ・ ・ ・ inner end, 96 ・ ・Detection unit, 98 ... bonding pad, 99 ... solder part, 100 ... semiconductor device, 101 ... broken line part, 102 ... control electrode part, 110 ... plating part, 120 ... -Active region, 140 ... outer peripheral edge, 150 ... semiconductor device, 172 ... divided region, 200 ... semiconductor device, 236 ... protective film, 284 ... opening

Claims (13)

With a semiconductor substrate
A well region provided in contact with the upper surface of the semiconductor substrate and
An active region in which a current flows between the upper surface and the lower surface of the semiconductor substrate, and
The transistor section provided in the active region and
A diode portion provided in the active region and arranged adjacent to the transistor portion along a predetermined arrangement direction in a top view of the semiconductor substrate, and a diode portion.
A protective film provided above the active region and
Equipped with
The protective film is provided with a plurality of openings in a region sandwiched between the well regions in a top view, and at least one opening is provided above both the transistor portion and the diode portion.
The active region has a plurality of divided regions surrounded by the well region.
Two or more of the openings are provided above the at least one split region.
Semiconductor device. The diode portion has a first conductive type cathode region provided in contact with the lower surface of the semiconductor substrate.
The semiconductor device according to claim 1 , wherein in each of the plurality of divided regions, the area where the opening and the cathode region overlap is larger than the area where the protective film and the cathode region overlap. The semiconductor device according to claim 1 or 2 , wherein a plurality of the openings are arranged above the at least one divided region in a stretching direction orthogonal to the arrangement direction. The semiconductor device according to claim 3 , wherein at least one diode portion is continuously provided over the two or more openings in the stretching direction. A gate runner unit that supplies a gate voltage to the transistor unit is further provided.
The semiconductor device according to claim 1 or 4 , wherein at least one of the divided regions is arranged between the gate runner portions in a top view of the semiconductor substrate. Further provided with a temperature sense wiring provided above the active region,
The semiconductor device according to claim 5 , wherein the divided region is arranged so as to be sandwiched between at least one of the gate runner portion and the temperature sense wiring. The semiconductor device according to any one of claims 1 to 6 , wherein the end portion of the opening portion in the arrangement direction is arranged above the transistor portion. With a semiconductor substrate
A well region provided in contact with the upper surface of the semiconductor substrate and
An active region in which a current flows between the upper surface and the lower surface of the semiconductor substrate, and
The transistor section provided in the active region and
A diode portion provided in the active region and arranged adjacent to the transistor portion along a predetermined arrangement direction in a top view of the semiconductor substrate, and a diode portion.
A protective film provided above the active region and
Equipped with
The protective film is provided with a plurality of openings in a region sandwiched between the well regions in a top view, and at least one opening is provided above both the transistor portion and the diode portion.
Two or more openings are provided in the arrangement direction.
Semiconductor device. The protective film has a first separation region that separates the openings between two adjacent openings in the arrangement direction.
The semiconductor device according to claim 8, wherein the first separation region is arranged above the transistor portion, and the width of the first separation region is smaller than the width of the transistor portion in the arrangement direction. The protective film is arranged above at least a part of the diode portion in the arrangement direction of the at least one diode portion.
The semiconductor device according to any one of claims 1 to 6 . The protective film has a first separation region that separates the openings between two adjacent openings in the arrangement direction.
The semiconductor device according to any one of claims 1 to 10, wherein the width of the first separation region is smaller than the width of the diode portion in the arrangement direction. With a semiconductor substrate
A well region provided in contact with the upper surface of the semiconductor substrate and
An active region in which a current flows between the upper surface and the lower surface of the semiconductor substrate, and
The transistor section provided in the active region and
A diode portion provided in the active region and arranged adjacent to the transistor portion along a predetermined arrangement direction in a top view of the semiconductor substrate, and a diode portion.
A protective film provided above the active region and
Equipped with
The protective film is provided with a plurality of openings in a region sandwiched between the well regions in a top view, and at least one opening is provided above both the transistor portion and the diode portion.
Further equipped with a bonding pad arranged in each of the openings,
Above the plurality of the bonding pads, a solder portion for electrically connecting the plurality of the bonding pads is further provided.
Semiconductor device. The semiconductor device according to claim 12 , wherein the end portion of the solder portion is arranged between the end portion of the bonding pad and the outer peripheral end of the semiconductor substrate in a top view of the semiconductor substrate.

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