WO2022127913A1 - 游程解码电路、控制方法、电子装置及可读存储介质 - Google Patents
游程解码电路、控制方法、电子装置及可读存储介质 Download PDFInfo
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- 238000000034 method Methods 0.000 title claims abstract description 30
- 239000012536 storage buffer Substances 0.000 claims abstract description 77
- 238000010586 diagram Methods 0.000 description 8
- 230000006870 function Effects 0.000 description 8
- 238000004891 communication Methods 0.000 description 3
- 238000007906 compression Methods 0.000 description 3
- 230000006835 compression Effects 0.000 description 3
- 239000000872 buffer Substances 0.000 description 2
- 230000003139 buffering effect Effects 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- 238000004590 computer program Methods 0.000 description 1
- 238000013144 data compression Methods 0.000 description 1
- 230000006837 decompression Effects 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
- H03M7/30—Compression; Expansion; Suppression of unnecessary data, e.g. redundancy reduction
- H03M7/40—Conversion to or from variable length codes, e.g. Shannon-Fano code, Huffman code, Morse code
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- the present invention relates to the technical field of data compression and decoding, and in particular, to a run-length decoding circuit, a control method, an electronic device and a readable storage medium.
- Run-Length Encoding technology is particularly widely used for loading overlay images or characters that implement the OSD (On-Screen Display) function.
- OSD On-Screen Display
- software is mostly used for direct decoding or a SoC circuit with MCU or CPU is used for direct hard decoding.
- the decoded graphics information is discontinuous in time sequence, discontinuous breakpoints appear in the process of superimposing images, which affects the OSD function of the image signal.
- FIG. 1 is a schematic diagram of an error in obtaining overlay information by a software-based run-length decoding method in the prior art.
- the data output rate of the decoder cannot be resolution, etc.), which may cause data loss.
- lengthen the decoding time to accommodate the decoding time of data types with longer data packets, but this will affect the smoothness and flexibility of image output.
- the present invention provides a run-length decoding circuit, a control method, an electronic device and a readable storage medium, which can obtain continuous and smooth overlay information in the process of overlaying images or characters, and realize decompression from a storage unit (such as sram) to lossless Data, delay-free overlay image function, improve the flexibility of overlay image.
- a storage unit such as sram
- It includes a storage unit, a control module, a first storage buffer, a second storage buffer and a decoding module; the control module is connected to the storage unit and the first storage buffer, and the decoding module is connected to the first storage a buffer and the second storage buffer;
- the control module is configured to acquire encoded data from the storage unit, and store the encoded data in the first storage buffer;
- the decoding module is configured to obtain the encoded data from the first storage buffer, decode to obtain the decoded data, and store it in the second storage buffer;
- the decoding module is further configured to acquire the decoded data from the second storage buffer to acquire and output overlay information.
- the decoding module is configured to decode the encoded data to obtain decoded data, including:
- the decoding module is used to identify the data type of each data packet in the encoded data, and according to the data type, extract the length of the overlay information and the overlay information data to obtain the decoded data;
- the decoded data includes several data packets of uniform bit width.
- the decoding module is configured to obtain overlay information according to the decoded data, including:
- the decoding module is configured to, according to the length of the overlay information and the overlay information data contained in each of the data packets, when determining that the decoded data of the data type is complete, sort out the The overlay information data in the several data packets of uniform bit width is obtained to obtain the overlay information.
- a control method of a run-length decoding circuit includes:
- S2 Acquire the encoded data from the first storage buffer, decode to obtain the decoded data, and store it in the second storage buffer;
- S3 Acquire the decoded data from the second storage buffer, acquire and output overlay information according to the decoded data.
- step S1 specifically includes:
- step S2 specifically includes:
- the decoded data includes several A single-bit-width packet.
- step S3 specifically includes:
- the length of the overlay information and the overlay information data contained in each of the data packets when it is determined that the decoded data of the data type is complete, sort the several uniform bit widths The overlay information data in the data packet is obtained to obtain the overlay information.
- step S2 also includes:
- an electronic device provided by the present invention includes the run-length decoding circuit described in any one of the above;
- the electronic device includes a processor and a memory, the processor is suitable for implementing each instruction, the memory is suitable for storing a plurality of instructions, and the instructions are suitable for being loaded by the processor and executed by the run-length decoding circuit in any of the above. Control Method.
- the present invention provides a computer-readable storage medium on which computer-executable instructions are stored, characterized in that the above-mentioned computer-executable instructions are implemented when the computer-executable instructions are executed.
- the control method of the run-length decoding circuit provided by the present invention is simple in logic, can be realized by software or software combined with hardware circuit or hardware logic circuit, etc., and can meet the requirements of different working conditions, and has strong adaptability and wide application range.
- Fig. 1 is a schematic diagram of overlay information obtained by decoding a run-length decoder in the prior art
- FIG. 2 is a schematic structural diagram of a decoding circuit provided in Embodiment 1 of the present invention.
- FIG. 3 is a schematic diagram of data packets of various overlay compression run-length encoded data types in one of the media data used in the embodiment of the present invention
- FIG. 4 is a schematic diagram of overlay information obtained by decoding a run-length decoding circuit according to an embodiment of the present invention
- FIG. 5 is a schematic flowchart of a control method of a run-length decoding circuit according to Embodiment 2 of the present invention.
- 100-storage unit 200-control module, 310-first storage buffer, 320-second storage buffer, 400-decoding module.
- FIG. 2 it is a schematic structural diagram of a decoding circuit provided in this embodiment.
- the run-length decoding circuit provided in this example includes a storage unit 100 , a control module 200 , a first storage buffer 310 , a second storage buffer 320 and a decoding module 400 .
- the control module 200 is connected to the storage unit 100 and the first storage buffer 310
- the decoding module 400 is connected to the first storage buffer 310 and the second storage buffer 320 .
- control module 200 is configured to acquire encoded data from the storage unit 100 and store the encoded data in the first storage buffer 310 .
- the present invention does not impose any limitation on the storage unit 100, that is, the storage unit 100 can be selected according to actual working conditions, including but not limited to SRAM memory and the like.
- the storage unit can be implemented by one or more combinations of any type of volatile or non-volatile storage devices, etc., including but not limited to static random access memory (Static Random Access Memory, SRAM), magnetic memory , flash memory, magnetic disk or optical disk.
- SRAM static random access memory
- those skilled in the art can configure the storage space sizes of the storage unit 100 , the first storage buffer 310 and the second storage buffer 320 according to actual operating conditions, and the present invention does not make any limit.
- the decoding module 400 is configured to obtain the encoded data from the first storage buffer 310, decode the encoded data to obtain decoded data, and store the decoded data into the second storage buffer 320 .
- the decoding module 400 is further configured to obtain the decoded data from the second storage buffer 320, and to obtain overlay information and output the overlay information according to the decoded data.
- the overlay information includes the original overlay data before the encoding data is encoded, and the overlay information includes, but is not limited to, overlay image and/or text character data for implementing the OSD.
- the encoded data includes overlay compression run-length encoded data, and the decoded data includes overlay decoded data, which will not be described in detail below.
- the first buffer storage area 310 is used for buffering the encoded data
- the control module 200 obtains the encoded data from the storage unit 100 and stores it in the first storage buffer area 310
- the decoding module 400 obtains the encoded data from the first storage buffer area 310.
- a storage buffer 310 acquires the encoded data to reduce the number of times the decoding module 400 accesses the storage unit 100.
- the decoding module 400 can acquire more encoded data at one time, improve data reading efficiency, and thereby improve decoding efficiency;
- the second storage buffer 320 is used for buffering the decoded data, and the decoding module 400 is also used to obtain the decoded data from the second storage buffer 320, and to obtain the decoded data according to the decoded data. Overlay information and output the overlay information.
- This configuration is used to avoid the discontinuity of graphics information in timing caused by the different lengths of data packets of different data types, resulting in different clock lengths consumed by decoding.
- the size is superimposed to ensure the OSD function of the image signal; in addition, the double storage buffer and the setting of the control module 200 and the decoding module 400 realize the data reading function and decoding function, and improve the flexibility of the run-length decoding circuit during multiplexing sex.
- the decoding speed of the run-length decoding circuit provided by the present invention is consistent with the input clock, the overlay operation is completed without affecting the frame rate of the output image, and the dependency on the performance of the MCU is low.
- the second storage buffer 320 may also be used to cache the overlay information. Configured in this way, the overlay information to be output has been stored in the second storage buffer 320, so that the run-length decoding circuit outputs based on the desired frame rate and/or desired resolution, so as to avoid data loss of the overlay information. , data packets to ensure the smoothness of image output and provide flexible output timing.
- the decoding module 400 is configured to decode the encoded data to obtain decoded data, and the decoding module 400 is configured to identify the encoded data type of each data packet in the encoded data, and extract the encoded data according to the encoded data type.
- the length of the overlay information and the overlay information data are used to obtain the decoded data; wherein the decoded data includes several data packets with a uniform bit width.
- FIG. 3 is a schematic diagram of data packets of various overlay compression run-length encoded data types in media data according to the present invention. As shown in Figure 3, the front 2 bits of the data packet of each data type are the flag bits, the back end is the overlay information data, and the length of the overlay information is between the flag bits and the overlay information data.
- the data type 1 has a total of 2 bytes (that is, 2 data packets with a uniform bit width), wherein the flag bit occupies 2 bits, the length of the overlay information occupies 10 bits, and the overlay information data0 occupies 4 bits.
- data type 2 has a total of 3 bytes (that is, 3 data packets with a uniform bit width), wherein the flag bit occupies 2 bits, the length of the overlay information is 18 bits, and the overlay information data0 occupies 4 bits.
- the data type 3 has a total of 1 byte, wherein the flag bit occupies 2 bits, the length of the overlay information is 2 bits, and the overlay information data0 occupies 4 bits.
- n is greater than or equal to 0.
- the data packet has a total of ((n+1)/2) bytes; if n is an even number, the data packet has a total of (n/2+2) bytes, as shown in data type 4. It is shown that the flag bit occupies 2 bits, the length of the overlay information occupies 10 bits, each overlay information data occupies 4 bits, and there are a total of n+1 overlay information data.
- the decoded data of various run-length encoded data types can be stored in the second storage buffer 320 before output; to avoid the loss of decoded data, the overlapping image information is not continuous in time sequence, and to ensure the OSD function of the graphics .
- the flag bit corresponds to a data type
- the overlay information data corresponds to a color number
- the color number can be determined by finding a value.
- data type 1-3 it includes one overlay information data, corresponding to a color number.
- data type 4 it includes multiple overlay information data corresponding to multiple color numbers.
- the length of the overlay information corresponds to the number of the overlay information data; when the number is large, the length of the overlay information may be as shown in data types 1-2, such as 10 bits, 18 bits, and 18 bits. When the number is small, the length of the overlay information can be as shown in data type 3, for example, 2 bits.
- the decoding module 400 is configured to obtain overlay information according to the decoded data, including, for any of the run-length encoded data types, the decoding module is configured to obtain overlay information according to the length of the overlay information and each The length of the overlay information data contained in the data packets, when it is determined that the decoded data of the data type is complete, arrange the overlay information data in the several uniform bit-width data packets to obtain the overlay information. graph information. As shown in FIG.
- the second storage buffer 320 includes decoded data of data type 2 and data type 4, and it is currently necessary to output the overlay information of data type 2 and then output the overlay information of data type 4 , firstly judging that the decoded data of data type 2 is complete, and then sorting to obtain the overlay information of data type 2; and then using the same judgment method and output method to obtain the decoded data of data type 4. vice versa.
- 4 is a schematic diagram of overlay information obtained by decoding the run-length decoding circuit according to an embodiment of the present invention. As shown in FIG. 4 , the overlay information obtained by the run-length decoding circuit provided by the present invention is continuous and complete without discontinuous data breakpoints.
- the run-length decoding circuit provided by the present invention adopts dual fifo (storage buffer) circuits, the front-stage fifo (such as the first storage buffer 310) controls the SRAM (such as the storage unit 100) to read, and the intermediate Decoder circuit (such as the decoding module) 400) Run-length decoding is implemented, and the post-stage fifo (eg, the second storage buffer 320) controls and outputs overlay information.
- the run-length decoding circuit provided by the present invention can obtain continuous overlay information in time sequence and ensure the OSD function of the image signal.
- control method of the run-length decoding circuit provided in this embodiment includes:
- S1 Acquire encoded data from the storage unit 100 and store the encoded data in the first storage buffer 310 .
- S2 Acquire the encoded data from the first storage buffer 310, decode to obtain the decoded data, and store the encoded data in the second storage buffer 320.
- S3 Acquire the decoded data from the second storage buffer 320, acquire and output overlay information according to the decoded data.
- Step S1 specifically includes: when the encoded data in the first storage buffer 310 reaches a first preset threshold, stopping reading the encoded data from the storage unit 100 .
- the first preset threshold is 0%-100% of the capacity of the first storage buffer 310, such as 20%, 50%, 60%, 80%, and so on.
- the first storage buffer 310 feeds back to the control unit 200 to stop reading the encoded data from the storage unit 100 .
- step S2 it specifically includes: identifying the data type of each data packet in the encoded data, and extracting the length of the overlay information and the overlay information data according to the data type to obtain the decoded data; wherein , the decoded data includes several data packets of uniform bit width.
- Step S2 further includes: when the decoded data in the second storage buffer 320 reaches a second preset threshold, stopping writing the decoded data into the second storage buffer 320 .
- the second preset threshold is 0%-100% of the capacity of the second storage buffer 320, such as 20%, 50%, 60%, 80%, and so on.
- the second storage buffer 320 feeds back to the decoding unit 400 to stop writing the decoded data.
- step S3 it specifically includes: for any of the data types, according to the length of the overlay information and the overlay information data contained in each of the data packets, when it is determined that the decoded data of the data type is complete, sorting The overlay information data in the plurality of uniform bit-width data packets is obtained to obtain the overlay information. Based on the bit length of the data packet, if the bit length is equal to the total bit length corresponding to the data type, the decoded data of the data type is complete. Or, when the overlay information data of one data type is incomplete, reading the overlay information data of another data type from the second storage buffer 320 may be suspended.
- the automatic triggering method is more efficient and reasonable, which significantly reduces the complexity of process control and saves operating resources and costs.
- This embodiment provides an electronic device, where the electronic device includes the run-length decoding circuit described in any one of the above.
- the electronic devices include, but are not limited to, mobile phones, video players, and desktop computers.
- the electronic device includes a processor and a memory
- the processor is adapted to implement each instruction
- the memory is adapted to store a plurality of instructions
- the instructions are adapted to be loaded by the processor and execute any of the above.
- the control method of the run-length decoding circuit is described.
- the electronic device also includes one or more of a multimedia component, an input/output interface (I/O interface), and a communication component.
- the memory is used for storing various types of data to support the control method for executing the run-length decoding circuit on the electronic device, and the data may include related data such as instructions for any application program or method.
- the multimedia components may include, but are not limited to, screen and audio components.
- the input/output interface provides an interface between the processor and other interface modules.
- the communication component is used for wired or wireless communication between the electronic device and other devices.
- This embodiment provides a computer-readable storage medium, where computer-executable instructions are stored on the computer-readable storage medium, and when the computer-executable instructions are executed, the run-length decoding described in any of the foregoing embodiments is implemented circuit control method.
- the computer-readable storage medium may be a tangible device capable of holding and storing instructions for use by the instruction execution device.
- electronic circuits that can execute computer-readable program instructions to implement various aspects of the present invention are personalized by utilizing state information of a computer program.
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Abstract
本发明公开一种游程解码电路、控制方法、电子装置及可读存储介质。其中，游程解码电路包括存储单元、控制模块、第一存储缓冲区、第二存储缓冲区和解码模块；所述控制模块用于从所述存储单元获取编码数据，并将所述编码数据存储至所述第一存储缓冲区；所述解码模块用于从所述第一存储缓冲区获取所述编码数据并解码得到解码数据，存储至所述第二存储缓冲区；所述解码模块还用于从所述第二存储缓冲区获取所述解码数据，以获取叠图信息并输出。本发明得到的叠图信息在时序上连续，在叠加图像的过程中保证图像信号的OSD功能。
Description
交叉引用
本申请要求2020年12月18日提交的申请号为CN 202011510957.2的中国专利申请的优先权。上述申请的内容以引用方式被包含于此。
本发明涉及数据压缩解码技术领域，尤其是涉及一种游程解码电路、控制方法、电子装置及可读存储介质。
游程编码(RLE，Run-Length Encoding)技术用于实现OSD(On-Screen Display)功能的加载叠加图或字符的应用尤为广泛。现有技术中，大多采用软件直接解码或采用带MCU或CPU的SoC电路直接硬解码。然而，由于解码得到的图形信息在时序上不连续，导致在叠加图像的过程中出现不连续的断点，影响图像信号的OSD功能。如图1所示，图1为现有技术中软件方式的游程解码方法获取叠图信息的出错示意图，当解码器的数据输出速率不能以一种期望的方式(例如，期望的帧速率、期望的分辨率等)，可能造成数据丢失。为避免数据丢失，拉长解码时间以适应数据包的长度较长的数据类型的解码时长，但会影响图像输出的流畅度和灵活性。
因此，需要提供一种用于游程解码器的游程解码电路，以解决现有技术的上述问题。
发明概要
本发明的提供一种游程解码电路、控制方法、电子装置及可读存储介质，能够在叠加图像或字符的过程中获得连续、流畅的叠图信息，实现从存储单元(比如sram)解压出无损数据、无延时的叠加图像功能，提高叠加图像的灵活性。
为实现上述目的，本发明通过以下技术方案予以实现：一种游程解码电路，
包括存储单元、控制模块、第一存储缓冲区、第二存储缓冲区和解码模块；所述控制模块连接所述存储单元和所述第一存储缓冲区，所述解码模块连接所述第一存储缓冲区和所述第二存储缓冲区；
所述控制模块用于从所述存储单元获取编码数据，并将所述编码数据存储至所述第一存储缓冲区；
所述解码模块用于从所述第一存储缓冲区获取所述编码数据并解码得到解码数据，存储至所述第二存储缓冲区；
所述解码模块还用于从所述第二存储缓冲区获取所述解码数据，以获取叠图信息并输出。
可选地，所述解码模块用于对所述编码数据解码得到解码数据，包括：
所述解码模块用于识别所述编码数据中各个数据包的数据类型，并根据所述数据类型，提取所述叠图信息的长度与叠图信息数据，以得到所述解码数据；其中，所述解码数据包括若干个统一位宽的数据包。
可选地，所述解码模块用于根据所述解码数据，获取叠图信息，包括：
对于任一所述数据类型，所述解码模块用于根据所述叠图信息的长度和各个所述数据包中包含的叠图信息数据，当判定所述数据类型的解码数据完 整时，整理所述若干个统一位宽的数据包中的所述叠图信息数据，以得到所述叠图信息。基于同一发明构思，本发明提供的一种游程解码电路的控制方法包括：
S1：从存储单元获取编码数据，并存储至第一存储缓冲区；
S2：从所述第一存储缓冲区获取所述编码数据，并解码得到解码数据，存储至第二存储缓冲区；
S3：从所述第二存储缓冲区获取所述解码数据，根据所述解码数据获取叠图信息并输出。
可选地，步骤S1具体包括：
当所述第一存储缓冲区中的所述编码数据达到第一预设阈值时，停止从所述存储单元读取所述编码数据。
可选地，步骤S2具体包括：
识别所述编码数据中各个数据包的数据类型，并根据所述数据类型，提取所述叠图信息的长度与所述叠图信息数据，得到所述解码数据；其中，所述解码数据包括若干个统一位宽的数据包。
可选地，步骤S3具体包括：
对于任一所述数据类型，根据所述叠图信息的长度和各个所述数据包中包含的叠图信息数据，当判定所述数据类型的解码数据完整时，整理所述若干个统一位宽的数据包中的所述叠图信息数据，得到所述叠图信息。
可选地，步骤S2中还包括：
当所述第二存储缓冲区中的解码数据达到第二预设阈值时，停止向所述第二存储缓冲区写入所述解码数据。
基于同一发明构思，本发明提供的一种电子装置包括上述任一项所述的游程解码电路；
和/或
所述电子装置包括处理器以及存储器，所述处理器适于实现各指令，所述存储器适于存储多条指令，所述指令适于由处理器加载并上述任一项所述游程解码电路的控制方法。
基于同一发明构思，本发明提供的一种计算机可读存储介质，所述计算机可读存储介质上存储有计算机可执行的指令，其特征在于，当所述计算机可执行的指令被执行时实现上述任一项所述的游程解码电路的控制方法。
本发明提供的游程解码电路控制方法逻辑简单，可以通过软件或软件结合硬件电路或硬件逻辑电路等实现，满足不同的工况需求，适应性强、应用范围广。
图1为现有技术中游程解码器解码得到的叠图信息示意图；
图2为本发明实施例一提供的解码电路结构示意图；
图3为本发明实施例使用的其中一种媒体数据中具有的各种叠图压缩游程编码数据类型的数据包示意图；
图4为本发明实施例的游程解码电路解码得到的叠图信息示意图；
图5为本发明实施例二提供的游程解码电路的控制方法流程示意图；
其中，附图标记说明如下：
100-存储单元，200-控制模块，310-第一存储缓冲区，320-第二存储缓冲区，400-解码模块。
发明内容
为使本发明的特征更清楚，以下结合附图对本发明提出的游程解码电路、控制方法、电子装置及可读存储介质作详细说明。需说明的是，附图均采用非常简化的形式且使用非精准的比例，以方便、明晰地辅助说明本发明实施例。
<实施例一>
本实施例提供了一种游程解码电路，参见附图2，为本实施例提供的一种解码电路结构示意图。如图2所示，本实例提供的所述游程解码电路包括存储单元100、控制模块200、第一存储缓冲区310、第二存储缓冲区320和解码模块400。所述控制模块200连接所述存储单元100和所述第一存储缓冲区310，所述解码模块400连接所述第一存储缓冲区310和所述第二存储缓冲区320。
具体地，所述控制模块200用于从所述存储单元100获取编码数据，并将所述编码数据存储至所述第一存储缓冲区310。本发明对所述存储单元100不作任何限制，即所述存储单元100可以根据实际工况选择，包括但不限于SRAM存储器等。所述存储单元可以由任何类型的易失性或非易失性存储设备等中的一种或几种组合实现，包括但不限于静态随机存取存储器(Static Random Access Memory，SRAM)，磁存储器，快闪存储器，磁盘或光盘。在实际应用中，本领域技术人员可以根据实际工况需要配置所述存储单元100、所述第一存储缓冲区310以及所述第二存储缓冲区320的存储空间大小，本发明对此不作任何限制。
所述解码模块400用于从所述第一存储缓冲区310获取所述编码数据， 并用于对所述编码数据解码得到解码数据，并将所述解码数据存储至所述第二存储缓冲区320。所述解码模块400还用于从所述第二存储缓冲区320获取所述解码数据，并用于根据所述解码数据，获取叠图信息并输出所述叠图信息。所述叠图信息包括所述编码数据编码前的原始叠图数据，所述叠图信息包括但不限于用于实现OSD的叠加图像和/或文本字符数据。所述编码数据包括叠图压缩游程编码数据，所述解码数据包括叠图解码数据，下文不再赘述。
所述第一缓冲存储区310用于缓存所述编码数据，所述控制模块200从所述存储单元100获取编码数据存储至所述第一存储缓冲区310，所述解码模块400从所述第一存储缓冲区310获取所述编码数据，以减少所述解码模块400访问所述存储单元100的次数，所述解码模块400能够一次性获取更多的编码数据，提高数据读取效率，从而提高解码效率；进一步地，第二存储缓冲区320用于缓存解码数据，所述解码模块400还用于从所述第二存储缓冲区320获取所述解码数据，并用于根据所述解码数据，获取叠图信息并输出所述叠图信息。该配置用以避免由于不同数据类型的数据包长度不同，导致解码消耗的时钟长度不同引起的图形信息在时序上不连续性现象，能够准确完成叠图叠字功能，根据使用者配置的叠加区域大小进行叠加，以保证图像信号的OSD功能；此外，双存储缓冲区及所述控制模块200与解码模块400的设置，实现数据读取功能与解码功能，提高游程解码电路在复用时的灵活性。本发明提供的游程解码电路的解码速度与输入时钟保持一致，在不影响输出图像帧率的情况下完成叠图操作，对MCU性能的依赖性较低。
进一步地，所述第二存储缓冲区320也可以用于缓存所述叠图信息。如 此配置，待输出的叠图信息已存储在所述第二存储缓冲区320，使所述游程解码电路基于期望的帧速率和/或期望的分辨率等方式输出，避免叠图信息的数据丢失，数据包以保证图像输出的流畅度，提供灵活的输出时机。
优选地，所述解码模块400用于解码所述编码数据得到解码数据，所述解码模块400用于识别所述编码数据中每一数据包的编码数据类型，并根据所述编码数据类型，提取所述叠图信息的长度与叠图信息数据，以得到所述解码数据；其中，所述解码数据包括若干个统一位宽的数据包。图3为本发明的一种媒体数据中的各种叠图压缩游程编码数据类型的数据包示意图。如图3所示，每一个数据类型的数据包前端2bit为标志位，后端为叠图信息数据，标志位和叠图信息数据之间为叠图信息的长度。数据类型1共有2byte(即2个统一位宽的数据包)，其中，标志位占2bit，所述叠图信息的长度占10bit，叠图信息数据data0占4bit。类似地，数据类型2共有3byte(即3个统一位宽的数据包)，其中，标志位占2bit，所述叠图信息的长度为18bit，叠图信息数据data0占4bit。数据类型3共有1byte，其中，标志位占2bit，所述叠图信息的长度为2bit，叠图信息数据data0占4bit。图3所示n大于等于0，若n为奇数，数据包共有((n+1)/2)byte；若n为偶数，数据包共有(n/2+2)byte，如数据类型4所示，其中标志位占2bit，叠图信息的长度占10bit，每个叠图信息数据占4bit，共有n+1个叠图信息数据。如此配置，可以在输出前将各种游程编码数据类型的解码数据存储在所述第二存储缓冲区320；避免因解码数据的丢失而导致叠图信息在时序上不连续，保证图形的OSD功能。
如图3所示，所述标志位对应数据类型，所述叠图信息数据对应色号， 可以通过寻值确定色号。如数据类型1-3所示，包括一个叠图信息数据，对应一个色号。如数据类型4所示，包括多个叠图信息数据，对应多个色号。所述叠图信息的长度对应所述叠图信息数据的个数；当个数较多时，叠图信息的长度可以如数据类型1-2所示，例如10bit、、18bit。当个数较少时，叠图信息的长度可以如数据类型3所示，例如2bit。
优选地，所述解码模块400用于根据所述解码数据，获取叠图信息，包括，对于任一所述游程编码数据类型，所述解码模块用于根据所述叠图信息的长度和各个所述数据包中包含的叠图信息数据的长度，当判定所述数据类型的解码数据完整时，整理所述若干个统一位宽的数据包中的所述叠图信息数据，以得到所述叠图信息。如图3所示，若所述第二存储缓冲区320中包括数据类型2和数据类型4的解码数据，且当前需要先输出数据类型2的叠图信息再输出数据类型4的叠图信息时，先判断所述数据类型2的解码数据完整时进行整理，以得到所述数据类型2的叠图信息；然后再采用相同的判断方法和输出方法得到数据类型4的解码数据。反之亦然。附图4为本发明实施例的游程解码电路解码得到的叠图信息示意图，如图4所示，本发明提供的游程解码电路得到的叠图信息，连续完整，没有不连续的数据断点。
综上，本发明提供的游程解码电路采用双fifo(存储缓冲区)电路，前级fifo(如第一存储缓冲区310)控制SRAM(如存储单元100)读取，中间Decoder电路(如解码模块400)实现游程解码，后级fifo(如第二存储缓冲区320)控制输出叠图信息。本发明提供的游程解码电路，能够得到在时序上连续的叠图信息，保证图像信号的OSD功能。
<实施例二>
如图5所示，为本实施例提供的游程解码电路的控制方法流程图。结合图1-图5说明，本实施例提供的游程解码电路的控制方法，包括：
S1：从存储单元100获取编码数据，并将所述编码数据存储至第一存储缓冲区310。S2：从所述第一存储缓冲区310获取所述编码数据，并解码得到解码数据，存储至第二存储缓冲区320。
S3：从所述第二存储缓冲区320获取所述解码数据，根据所述解码数据获取叠图信息并输出。
步骤S1中，具体包括：当所述第一存储缓冲区310中的所述编码数据达到第一预设阈值时，停止从所述存储单元100读取所述编码数据。所述第一预设阈值为所述第一存储缓冲区310容量的0％-100％，如20％、50％、60％、80％等。当所述编码数据达到第一预设阈值时，所述第一存储缓冲区310反馈至所述控制单元200停止从所述存储单元100中读取所述编码数据。
步骤S2中，具体包括：识别所述编码数据中各个数据包的数据类型，并根据所述数据类型，提取所述叠图信息的长度与所述叠图信息数据，得到所述解码数据；其中，所述解码数据包括若干个统一位宽的数据包。步骤S2中，又包括：当所述第二存储缓冲区320中的解码数据达到第二预设阈值时，停止向所述第二存储缓冲区320写入所述解码数据。所述第二预设阈值为所述第二存储缓冲区320容量的0％-100％，如20％、50％、60％、80％等。当所述解码数据达到第二预设阈值时，所述第二存储缓冲区320反馈至所述解码单元400停止写入所述解码数据。
步骤S3中，具体包括：对于任一所述数据类型，根据所述叠图信息的长度和各个所述数据包中包含的叠图信息数据，当判定所述数据类型的解码 数据完整时，整理所述若干个统一位宽的数据包中的所述叠图信息数据，得到所述叠图信息。基于数据包的位长，若位长等于该数据类型对应的总位长，则该数据类型的解码数据完整。或，当一种所述数据类型的叠图信息数据未完整时，可以暂停从所述第二存储缓冲区320读取另一数据类型的叠图信息数据。
所述第一存储缓冲区310达到第一预设阈值时，反馈至所述控制模块200，所述第二存储缓冲区320达到第二预设阈值时，反馈至所述解码模块400，本实施例自动触发的方式更高效合理，显著降低流程控制的复杂度，节约运行资源和成本。
<实施例三>
本实施例提供一种电子装置，所述电子装置包括上述任一项所述的游程解码电路。所述电子装置包括但不限于移动电话、视频播放器以及台式机。
和/或，所述电子装置包括处理器和存储器，所述处理器适于实现各指令，所述存储器适于存储多条指令，所述指令适于由处理器加载并执行上述任一项所述游程解码电路的控制方法。
所述电子装置还包括多媒体组件，输入/输出接口(I/O接口)，以及通信组件中的一个或多个。所述存储器用于存储各种类型的数据，以支持在所述电子装置上执行所述游程解码电路的控制方法，所述数据可以包括用于任意应用程序或方法的指令等相关数据。所述多媒体组件可以包括但不限于屏幕和音频组件。输入/输出接口为所述处理器和其他接口模块之间提供接口。所述通信组件用于所述电子装置与其他设备之间进行有线或无线通信。
<实施例四>
本实施例提供一种计算机可读存储介质，所述计算机可读存储介质上存储有计算机可执行的指令，当所述计算机可执行的指令被执行时实现上述任一实施方式所述的游程解码电路的控制方法。
所述计算机可读存储介质可以是能够保持和存储由指令执行设备使用的指令的有形设备。在一些实施例中，通过利用计算机程序的状态信息来个性化定制电子电路，所述电子电路可以执行计算机可读程序指令，以实现本发明的各个方面。
以上所述仅为本发明的优选实施例，所述实施例并非用于限制本发明的专利保护范围，因此凡是运用本发明的说明书及附图内容所作的等同结构变化，同理均应包含在本发明所附权利要求的保护范围内。
Claims (10)
- 一种游程解码电路，其特征在于，包括存储单元、控制模块、第一存储缓冲区、第二存储缓冲区和解码模块；所述控制模块连接所述存储单元和所述第一存储缓冲区，所述解码模块连接所述第一存储缓冲区和所述第二存储缓冲区；所述控制模块用于从所述存储单元获取编码数据，并将所述编码数据存储至所述第一存储缓冲区；所述解码模块用于从所述第一存储缓冲区获取所述编码数据并解码得到解码数据，存储至所述第二存储缓冲区；所述解码模块还用于从所述第二存储缓冲区获取所述解码数据，以获取叠图信息并输出。
- 根据权利要求1所述的游程解码电路，其特征在于，所述解码模块用于对所述编码数据解码得到解码数据，包括：所述解码模块用于识别所述编码数据中各个数据包的数据类型，并根据所述数据类型，提取所述叠图信息的长度与叠图信息数据，以得到所述解码数据；其中，所述解码数据包括若干个统一位宽的数据包。
- 根据权利要求2所述的游程解码电路，其特征在于，所述解码模块用于根据所述解码数据，获取叠图信息，包括：对于任一所述数据类型，所述解码模块用于根据所述叠图信息的长度和各个所述数据包中包含的叠图信息数据，当判定所述数据类型的解码数据完整时，整理所述若干个统一位宽的数据包中的所述叠图信息数据，以得到所述叠图信息。
- 一种游程解码电路的控制方法，其特征在于，包括：S1：从存储单元获取编码数据，并存储至第一存储缓冲区；S2：从所述第一存储缓冲区获取所述编码数据，并解码得到解码数据，存储至第二存储缓冲区；S3：从所述第二存储缓冲区获取所述解码数据，根据所述解码数据获取叠图信息并输出。
- 根据权利要求4所述的游程解码电路的控制方法，其特征在于，步骤S1具体包括：当所述第一存储缓冲区中的所述编码数据达到第一预设阈值时，停止从所述存储单元读取所述编码数据。
- 根据权利要求4所述的游程解码电路的控制方法，其特征在于，步骤S2具体包括：识别所述编码数据中各个数据包的数据类型，并根据所述数据类型，提取所述叠图信息的长度与叠图信息数据，得到所述解码数据；其中，所述解码数据包括若干个统一位宽的数据包。
- 根据权利要求6所述的游程解码电路的控制方法，其特征在于，步骤S3具体包括：对于任一所述数据类型，根据所述叠图信息的长度和各个所述数据包中包含的叠图信息数据，当判定所述数据类型的解码数据完整时，整理所述若干个统一位宽的数据包中的所述叠图信息数据，得到所述叠图信息。
- 根据权利要求4所述的游程解码电路的控制方法，其特征在于，步骤S2中还包括：当所述第二存储缓冲区中的解码数据达到第二预设阈值时，停止向所述第二存储缓冲区写入所述解码数据。
- 一种电子装置，其特征在于，包括权利要求1-3任一项所述的游程解码电路；和/或包括处理器以及存储器，所述处理器适于实现各指令，所述存储器适于存储多条指令，所述指令适于由处理器加载并执行权利要求4至8任一项所述的游程解码电路的控制方法。
- 一种计算机可读存储介质，所述计算机可读存储介质上存储有计算机可执行的指令，其特征在于，当所述计算机可执行的指令被执行时实现权利要求4至8任一项所述的游程解码电路的控制方法。
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