WO2022126358A1 - Circuit de mesure du temps de vol, puce correspondante et appareil électronique - Google Patents

Circuit de mesure du temps de vol, puce correspondante et appareil électronique Download PDF

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Publication number
WO2022126358A1
WO2022126358A1 PCT/CN2020/136413 CN2020136413W WO2022126358A1 WO 2022126358 A1 WO2022126358 A1 WO 2022126358A1 CN 2020136413 W CN2020136413 W CN 2020136413W WO 2022126358 A1 WO2022126358 A1 WO 2022126358A1
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Prior art keywords
pixel
coupled
output
time
gate
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PCT/CN2020/136413
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English (en)
Chinese (zh)
Inventor
林奇青
范铨奇
杨富强
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深圳市汇顶科技股份有限公司
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Priority to PCT/CN2020/136413 priority Critical patent/WO2022126358A1/fr
Publication of WO2022126358A1 publication Critical patent/WO2022126358A1/fr

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
    • G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
    • G01S7/48—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S17/00
    • G01S7/483—Details of pulse systems
    • G01S7/486—Receivers
    • G01S7/4861—Circuits for detection, sampling, integration or read-out
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
    • G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
    • G01S7/48—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S17/00
    • G01S7/483—Details of pulse systems
    • G01S7/486—Receivers
    • G01S7/4861—Circuits for detection, sampling, integration or read-out
    • G01S7/4863—Detector arrays, e.g. charge-transfer gates
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
    • G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
    • G01S7/48—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S17/00
    • G01S7/483—Details of pulse systems
    • G01S7/486—Receivers
    • G01S7/4865—Time delay measurement, e.g. time-of-flight measurement, time of arrival measurement or determining the exact position of a peak

Definitions

  • the present application relates to a measurement circuit, and in particular, to a time-of-flight measurement circuit and related chips and electronic devices.
  • the time-of-flight measurement technology includes direct time-of-flight measurement technology and indirect time-of-flight measurement technology.
  • the direct time-of-flight measurement technology is to transmit a light pulse, and then measure the time interval between the reflected light pulse and the transmitted light pulse.
  • the flight time of light can be obtained, and then the depth information can be calculated using the measured flight time.
  • One of the objectives of the present application is to disclose a time-of-flight measurement circuit and related chips and electronic devices to solve the above problems.
  • An embodiment of the present application discloses a time-of-flight measurement circuit, including: a pixel array, including p rows ⁇ q columns of pixel groups, wherein each pixel group includes m rows ⁇ n columns of pixel units, wherein p, q, m , n is a positive integer, the pixel array further includes p*m row selection lines corresponding to p*m pixel rows, and q*n column selection lines corresponding to q*n pixel columns, and p*m row shift lines
  • the control line corresponds to p*m rows of pixel rows, wherein at least one pixel unit in the pixel array includes: a photosensitive sensor, the photosensitive sensor has a dead time after sensing a photon and cannot perform sensing; an AND gate, wherein all The first input terminal of the AND gate is coupled to the photosensitive sensor, and the second input terminal of the AND gate is coupled to the p*m row selection lines, corresponding to the pixel row where the at least one pixel unit is located the row select line
  • the multiplexer When the output of the output terminal of the OR gate is a high logic level, the multiplexer The first input terminal of the multiplexer is coupled to the output terminal of the multiplexer, and when the output of the output terminal of the OR gate is at a low logic level, the second input terminal of the multiplexer is coupled to an output terminal of the multiplexer; and an XOR gate, wherein the first input terminal of the XOR gate is coupled to the output terminal of the latch circuit, and the second input terminal of the XOR gate is coupled to The output end of the multiplexer, the output end of the XOR gate is coupled to the output end of the at least one pixel unit; p*q*n waveform shaping circuits, wherein the p*q*n waveforms The input terminals of the shaping circuit are correspondingly coupled to the n output terminals of the n pixel units in the mth row of the p*q pixel groups, and the output terminals of the p*q*n waveform shaping circuits are correspondingly
  • An embodiment of the present application discloses a chip including the above-mentioned time-of-flight measurement circuit.
  • An embodiment of the present application discloses an electronic device including the above-mentioned chip.
  • the time-of-flight measurement circuit of the present application can avoid possible output errors when photons are simultaneously sensed by pixel units in different rows in the same column, so as to improve the accuracy of the time-of-flight measurement circuit.
  • FIG. 1 is a light spot formed on a pixel array of a time-of-flight measurement circuit of the present application by an optical signal emitted at a first time.
  • FIG. 2 is a light spot formed on the pixel array of the time-of-flight measurement circuit of the present application by the light signal emitted at the second time.
  • FIG. 3 is an enlarged view of a pixel group in the pixel array of FIGS. 1 and 2 .
  • FIG. 4 is a schematic diagram of an embodiment of a pixel unit of the present application.
  • FIG. 5 is a schematic diagram of an embodiment of a pixel group and some pixel units of an adjacent pixel group.
  • FIG. 6 is a schematic diagram of photons sensed by some pixel units of a pixel group.
  • FIG. 7 is a schematic diagram illustrating that some pixel units of a pixel group sense photons.
  • FIG. 8 is a signal waveform diagram corresponding to FIG. 6 and FIG. 7 .
  • FIG. 9 is an embodiment of a pixel group in the pixel array of FIGS. 1 and 2 and its corresponding waveform shaping circuit, logic circuit and time-to-digital converter.
  • FIG. 10 is a schematic diagram of an embodiment of the waveform shaping circuit of the present application.
  • FIG. 11 is a diagram showing the waveform shaping circuit of FIG. 10 corresponding to the signal waveform of FIG. 8 .
  • FIG. 12 is a schematic diagram of an embodiment of a logic circuit of the present application.
  • first and second features are in direct contact with each other; and may also include Certain embodiments may have additional components formed between the first and second features described above, such that the first and second features may not be in direct contact.
  • present disclosure may reuse reference numerals and/or reference numerals in various embodiments. Such reuse is for brevity and clarity, and does not in itself represent a relationship between the different embodiments and/or configurations discussed.
  • spatially relative terms such as “below”, “below”, “below”, “above”, “above” and the like, may be used to facilitate the description of the drawings. relationship between one component or feature shown with respect to another component or feature.
  • These spatially relative terms are intended to encompass many different orientations of the device in use or operation in addition to the orientation depicted in the figures.
  • the device may be positioned in other orientations (eg, rotated 90 degrees or at other orientations) and these spatially relative descriptors should be interpreted accordingly.
  • the direct time-of-flight measurement technology uses the light-emitting unit to emit a light signal, which is reflected back to the time-of-flight measurement circuit by the target to form a light spot on the pixel array.
  • the pixel unit in the pixel array irradiated by the light spot will transmit the sensing signal to the time digital Converter to calculate flight time.
  • the same lattice light-emitting unit will produce different patterns in stages, and form light spots of different patterns on the same pixel array. Different patterns are produced at two times to illuminate different photosensitive areas of the pixel array.
  • the pattern of the light signal emitted by the light-emitting unit is not randomly distributed, but repeats with a specific rule.
  • the pixel array of the sensor can be divided according to the distribution of the light spots. Multiple minimum repeating units, so that the number of light spots contained in each minimum repeating unit is the same. For example, in this embodiment, each minimum repeating unit only contains A spot of light.
  • the divided minimum repeating units are referred to as pixel groups in this application.
  • the pixel array of FIGS. 1 and 2 has 48 rows and 48 columns of pixel units, which are divided into pixel groups of 6 rows and 6 columns, ie, pixel groups U00 to U55.
  • Figures 1 and 2 are for illustrative purposes only, in fact, the same light-emitting unit can also be printed at a third time other than the first time and the second time according to the rules of the minimum repeating unit. Different from Figures 1 and 2 The third pattern of the pattern, even more than 3 patterns. In addition, the size of the light spot, the pattern, the size and number of the pixel unit and the pixel group are for illustrative purposes only.
  • each column of pixels in a conventional pixel array can share one readout circuit, so that the total number of readout circuits is equal to the number of columns in the pixel array, but when the time-of-flight measurement circuit is implemented, the total number of readout circuits The number will be greater than the number of columns of the pixel array. For example, it may be necessary to configure a separate readout circuit for each pixel unit.
  • each pixel group is regarded as a basic unit and corresponds to a time-to-digital converter to reduce the complexity of connection lines and the number of time-to-digital converters. Therefore, taking FIG. 1 and FIG. 2 as examples, each column of pixel groups It only needs to correspond to 6 time-to-digital converters, the details of which are explained later.
  • FIG. 3 is an enlarged view of a pixel group Uxy in the pixel array of FIGS. 1 and 2 , where x and y are integers between 0 and 5.
  • FIG. The pixel group Uxy includes 8 rows by 8 columns of pixel units xyP00 to xyP77, wherein the light spot area formed on the pixel array reflected back to the light signal emitted for the first time is the pixel unit xyP11, xyP12, xyP21, xyP22;
  • the light spot areas formed on the light signal reflected back to the pixel array are pixel units xyP55, xyP56, xyP65, and xyP66.
  • the specific method is to select and output only the sensing results of the pixel units xyP11, xyP12, xyP21, and xyP22 in the pixel group Uxy by using the row selection lines xyRS0-xyRS7 and the column selection lines xyCS0-xyCS7 for the optical signal emitted at the first time, and The sensing results of the remaining pixels in the pixel group Uxy are not output; for the light signal emitted at the second time, the row selection lines xyRS0-xyRS7 and the column selection lines xyCS0-xyCS7 can be used to select and output only the pixel unit xyP55 in the pixel group Uxy , xyP56 , xyP65 , xyP66 , and the sensing results of the remaining pixels in the pixel group Uxy are not output. In this way, a misjudgment caused by the accidental hitting of the non-preset light spot area by ambient light can be avoided, and power consumption
  • the outputs of all pixel units in any pixel column of the pixel group Uxy are connected in series and output in the last row of pixel units, so that the pixel group Uxy has 8 output lines xyC0-xyC7 corresponding to 8 pixel columns.
  • the present application does not need to set a time-to-digital converter for each pixel unit, which can greatly reduce hardware cost and complexity.
  • the pixel group Uxy in FIG. 3 further includes 8 row movement control lines S0 - S7 corresponding to 8 rows of pixel rows, the use of which will be described later.
  • FIG. 4 is a schematic diagram of an embodiment of a pixel unit 11P01, wherein the pixel unit 11P01 is a pixel unit in the first row and second column of the pixel group U11, and the pixel unit 11P01 includes a photosensitive sensor D01. Photon quantum efficiency, but after detecting photons, the photosensitive sensor must rest for a period of time before it can be detected again, this period is called rest time or dead time (Dead time). In this embodiment, the photosensor D01 cannot perform sensing again within a period of dead time T after sensing photons, and within the dead time T, the photosensor D01 will output a high logic potential.
  • the photosensitive sensor D01 can be implemented by a single photon avalanche diode, but the present application is not limited to this.
  • the pixel unit 11P01 further includes an AND gate A01, the first input terminal of the AND gate A01 is coupled to one end of the photosensitive sensor D01, the second input terminal of the AND gate A01 is coupled to the row select line 11RS0, and the third input terminal of the AND gate A01 is coupled to the row select line 11RS0.
  • the input terminal is coupled to the column select line 11CS1.
  • the pixel unit 11P01 also includes a latch circuit L01, the implementation of which is not limited. For example, as shown in FIG. Phase output It is coupled to the data input terminal D, and the non-inverting output terminal Q of the flip-flop is used as the output terminal of the latch circuit L01.
  • the pixel unit 11P01 further includes an OR gate G01, wherein the first input terminal of the OR gate G01 is coupled to the output terminal of the AND gate A01 to receive the signal CP01, and the second input terminal of the OR gate G01 is coupled to the p*m row movement control The row corresponding to the pixel unit 11P01 in the line moves the control line S0.
  • the pixel unit 11P01 further includes a multiplexer M01, wherein the first input terminal of the multiplexer M01 is coupled to a predetermined voltage, which is a low logic level 0 in this embodiment, and the second input terminal of the multiplexer M01 is coupled to To the output end of the pixel unit in the previous row and the same column of the pixel unit 11P01, since in the example of FIG. Will be the last row of pixel group U01 and the same column of pixel units 01P71.
  • a multiplexer M01 wherein the first input terminal of the multiplexer M01 is coupled to a predetermined voltage, which is a low logic level 0 in this embodiment, and the second input terminal of the multiplexer M01 is coupled to To the output end of the pixel unit in the previous row and the same column of the pixel unit 11P01, since in the example of FIG. Will be the last row of pixel group U01 and the same column of pixel units 01P71.
  • the multiplexer M01 selectively couples the first input terminal or the second input terminal of the multiplexer M01 to the output terminal of the multiplexer M01 according to the output of the OR gate G01, for example, when the OR gate G01 When the output is at a high logic level, the first input end of the multiplexer M01 is coupled to the output end of the multiplexer M01, and when the output end of the OR gate G01 is at a low logic level, the second input end of the multiplexer M01 coupled to the output of the multiplexer M01.
  • the pixel unit 11P01 further includes an exclusive OR gate X01, wherein the first input terminal of the exclusive OR gate X01 is coupled to the output terminal of the latch circuit L01, and the second input terminal of the exclusive OR gate X01 is coupled to the output terminal of the multiplexer M01 , the output terminal of the XOR gate X01 is coupled to the output terminal of the pixel unit 11P01, in other words, the output terminal of the XOR gate X01 is used as the output terminal of the pixel unit 11P01 to output the signal PO.
  • an exclusive OR gate X01 wherein the first input terminal of the exclusive OR gate X01 is coupled to the output terminal of the latch circuit L01, and the second input terminal of the exclusive OR gate X01 is coupled to the output terminal of the multiplexer M01 , the output terminal of the XOR gate X01 is coupled to the output terminal of the pixel unit 11P01, in other words, the output terminal of the XOR gate X01 is used as the output terminal of the pixel unit 11
  • the row shift control line S0 is at a high logic level, so that the output of the OR gate of the pixel is kept at a high logic level, so
  • the first input terminal of the multiplexer of the pixel can be controlled to be coupled to the output terminal of the multiplexer (ie, the preset voltage of the first input terminal of the multiplexer is used as the output signal of the multiplexer), so that each The pixel group does not receive the output signal of the previous row of pixel groups.
  • the row shift control lines S1-S7 are low logic level, when the pixel has not sensed a photon, the output of the AND gate of the pixel For a low logic level, the output of the OR gate of the pixel is kept at a low logic level, so the second input terminal of the multiplexer of the pixel can be controlled to be coupled to the output terminal of the multiplexer, so that the second Each pixel of the pixel row of the row to the eighth row may receive the output signal of each pixel of the pixel row of the first row to the seventh row correspondingly, that is, for each of the pixel row of the second row to the eighth row.
  • the multiplexer included in the multiplexer is controlled by S1-S7, and the output signal of the pixel unit in the previous row is used as the output of the multiplexer.
  • the output of the AND gate of the pixel changes from a low logic level to a high logic level, so that the output of the OR gate of the pixel changes from a low logic level to a high logic level
  • the first input terminal of the multiplexer of the pixel can be controlled to be coupled to the output terminal of the multiplexer (that is, the preset voltage of the first input terminal of the multiplexer is used as the output signal of the multiplexer), so that Each pixel group does not receive the output signal of the previous row of pixel groups.
  • FIG. 5 is a schematic diagram of an embodiment of some pixel units of the pixel group U11 and the adjacent pixel group U21 , and the thick black lines in FIG. 5 are used to indicate the manner of signal transmission.
  • the pixel units 11P01 to 11P71 of the pixel group U11 and the pixel unit 21P01 of the pixel group U21 are located in the same column of the pixel array, and the pixel unit 11P01 is located in the pixel row of the first row of the pixel group U11; the pixel unit 21P01 is located in the first row of the pixel group U21 pixel row.
  • none of the pixel units in FIG. 5 sense photons, that is, the signals CP01, CP11, . . .
  • the line S0 controls the multiplexer M01 of the pixel unit 11P01 and the pixel unit 21P01 to output the preset voltage.
  • the multiplexers M11 to M71 of the remaining pixel units 11P11 to 11P71 correspondingly output the output signals of the pixel units 11P01 to 11P61.
  • the output signal of the pixel unit 11P71 located in the last pixel row of the pixel group U11 is also output to the rear waveform shaping circuit 9111, the logic circuit 411 and the time-to-digital converter TDC (shown in FIG. 9 ) via the output line 11C1.
  • the output signal of the pixel unit 21P71 located in the last pixel row of the pixel group U21 is output to the waveform shaping circuit 9211 and the logic circuit 421 through the output line 21C1.
  • FIGS. 6 and 7 are schematic diagrams of embodiments of some pixel units of the pixel group U11, with thick black lines used to illustrate the change in the signal transmission method when the pixel unit 11P11 and the pixel unit 11P21 sense photons at the same time, Please also refer to Figure 8.
  • the pixel unit 11P11 and the pixel unit 11P21 sense photons simultaneously at time T1
  • both the signal CP11 and the signal CP21 will change from a low logic level to a high logic level, and after the dead time T, return to a low logic level at time T2 level.
  • the latch circuit of the pixel unit 11P11 makes the signal LP11 change from a low logic level to a high logic level, and It remains at the high logic level after the dead time T; similarly, when the signal CP21 changes from the low logic level to the high logic level, the latch circuit of the pixel unit 11P21 will make the signal LP21 change from the low logic level to the high logic level level, and remains at a high logic level after dead time T.
  • the signal CP11 is at a high logic level, so that the output of the OR gate G11 of the pixel unit 11P11 is at a high logic level, so that the multiplexer M11 of the pixel unit 11P11 outputs the preset voltage (low Similarly, at time T1-T2, the signal CP21 is at a high logic level, so that the output of the OR gate G21 of the pixel unit 11P21 is at a high logic level, so that the multiplexer M21 of the pixel unit 11P21 outputs all the the preset voltage (low logic level), as shown in FIG. 6 .
  • the output of the exclusive OR gate X21 of the pixel unit 11P21 is the same as the signal LP21, and is transmitted to the output line 11C1 through the pixel units 11P31 to 11P71.
  • the output of the pixel unit 11P21 is not affected by the pixel unit 11P11 at this time.
  • the output of the pixel unit 11P11 cannot be output, because the pixel unit 11P11 and the pixel unit 11P21 belong to the same light spot area, when the pixel unit 11P11 and the pixel unit 11P21 are hit at the same time, it is only necessary to calculate the flight time of one of them.
  • the signal CP11 has passed the dead time T and returns to the low logic level, so the signal G11 also returns to the low logic level, so that the multiplexer M11 outputs the output of the XOR gate X01 of the pixel unit 11P01, Because pixel unit 11P01 does not sense photons, the output of XOR gate X01 is a low logic level. Since the signal LP11 is at the high logic level at this time, the output of the exclusive OR gate X11 of the pixel unit 11P11 is at the high logic level.
  • the signal CP21 has passed the dead time T and returns to the low logic level, so the signal G21 also returns to the low logic level, causing the multiplexer M21 to output the output of the exclusive OR gate X11 of the pixel unit 11P11 (the high logic level ), since the signal LP21 is at a high logic level at this time, the output of the XOR gate X21 of the pixel unit 11P21 changes to a low logic level, and is transmitted to the output line 11C1 through the pixel units 11P31 to 11P71. In other words, the output of the pixel unit 11P21 at this time is influenced by the pixel unit 11P11.
  • FIG. 9 is an embodiment of pixel groups U01 to U51 in the pixel array of FIGS. 1 and 2 and their corresponding time-to-digital converters.
  • the waveform shaping circuits 9010-9017 and the logic circuit 401 correspond to the pixel group U01; the waveform shaping circuits 9110-9117 and the logic circuit 411 correspond to the pixel group U11; the waveform shaping circuits 9210-9217 and the logic circuit 421 correspond to the pixel group U21; the waveform shaping circuit 9310-9317 and logic circuit 431 correspond to pixel group U31; waveform shaping circuits 9410-9417 and logic circuit 441 correspond to pixel group U41; waveform shaping circuits 9510-9517 and logic circuit 451 correspond to pixel group U51.
  • the column selection lines 11CS1 and 11CS2 and the row selection lines 11RS1 and 11RS2 are set to high logic levels. 1.
  • the remaining column select lines 11CS0, 11CS3 to 11CS7 and the row select lines 11RS0, 11RS3 to 11RS7 are set to low logic level 0.
  • the light spot at the second time (as shown in Fig. 2), that is, the light spot in the lower left corner of Fig.
  • the column selection lines 11CS5, 11CS6 and the row selection lines 11RS5, 11RS6 are set to high logic level 1, and the remaining column selection lines 11CS0 ⁇ 11CS4, 11CS7 and row select lines 11RS0 ⁇ 11RS4, 11RS7 are set to low logic level 0.
  • the input terminals of the waveform shaping circuits 9010-9017 are correspondingly coupled to the output terminals 11C0-11C7 of the pixel units in the last row of the pixel group U01, and the output terminals of the waveform shaping circuits 9010-9017 are correspondingly coupled to eight output lines and constitute output bus.
  • FIG. 10 is a schematic diagram of an embodiment of the waveform shaping circuit of the present application.
  • the waveform shaping circuit 9111 includes an edge detection circuit 902, which is used to detect the logic level transition of the signal received by the waveform shaping circuit 9111 from the output terminal 11C1, and every time the logic level is detected During the horizontal conversion, the trigger signal 11CE1 is correspondingly generated.
  • One embodiment of the edge detection circuit 902 may be shown in FIG. 10 , including a first flip-flop 904 , a second flip-flop 906 and an exclusive OR gate 908 .
  • the data input terminal D of the first flip-flop 904 is used as the input terminal of the waveform shaping circuit 9111; the data input terminal D of the second flip-flop 906 is coupled to the output terminal Q of the first flip-flop 904; the first input of the XOR gate 908 The terminal is coupled to the output terminal Q of the first flip-flop 904, the second input terminal of the XOR gate 908 is coupled to the output terminal Q of the second flip-flop 906, and the output terminal of the XOR gate 908 is used as the output of the waveform shaping circuit 9111 end.
  • trigger signals 11CE1 are generated at times T1 and T2 respectively, wherein the first trigger signal 11CE1 (times T1 to T1 ′) represents that the pixel unit 11P21 of FIG. 6 senses photons, and the second trigger signal 11CE1 ( The time T2 to T2') is generated because the pixel unit 11P11 and the pixel unit 11P21 sense photons at the same time, rather than actually sensing photons at time T2, so this embodiment additionally uses de-glitch Circuit 910 filters out this redundant information.
  • the deglitch circuit 910 is coupled to the edge detection circuit 902.
  • the deglitch circuit 9111 receives the first trigger signal 11CE1 at time T1, it will faithfully output the trigger signal 11CE1 and receive the first trigger signal 11CE1
  • the length of the predetermined time T' is not less than the dead time T, in order to completely eliminate the second A trigger signal 11CE1 (time T2 to T2').
  • the predetermined time T' is equal to the dead time T.
  • the logic circuit 411 corresponding to the pixel group U01 receives at least the output bus from the waveform shaping circuits 9010-9017, and integrates the output bus s11 into a single signal and transmits it to the corresponding time-to-digital converter TDC. In the embodiment of FIG. 9 , the logic circuit 411 also generates the pixel output s11 of a single signal according to the eight column selection lines 11CS0 ⁇ 11CS7 corresponding to the pixel group U11 . For an example, refer to FIG. 12 . As shown in FIG.
  • the The output lines 11C0-11C7 and the corresponding column selection lines 11CS0-11CS7 are allocated to the first input terminal and the second input terminal of the eight AND gates A110-A17, and then the output terminals of the eight AND gates A110-A17 are coupled to the OR
  • the output of the eight input terminals of the gate O11, or the output terminal of the OR gate O11, is the signal s11.
  • the sensing result of the preset spot area in the pixel group U11 is output as the pixel output s11 , that is, the pixel output s11 is not affected by other non-preset Image of pixels in the spot area.
  • the present application also provides a chip, which includes the above-mentioned time-of-flight measurement circuit.
  • the present application also provides an electronic device, including the above-mentioned time-of-flight measurement circuit or the chip.
  • the electronic device may be any electronic device such as a smart phone, a personal digital assistant, a handheld computer system, a tablet computer or a digital camera.

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  • Physics & Mathematics (AREA)
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Abstract

L'invention concerne un circuit de mesure du temps de vol, une puce correspondante et un appareil électronique. Le circuit de mesure du temps de vol comprend un réseau de pixels. Au moins une unité de pixel comprend : un capteur photosensible (D01), qui ne peut pas effectuer de détection dans une période de temps mort après avoir détecté un photon ; une porte ET (A01), dont une première extrémité d'entrée est couplée au capteur photosensible, dont une deuxième extrémité d'entrée est couplée à une ligne de sélection de rangée (11RS0), et dont une troisième extrémité d'entrée est couplée à une ligne de sélection de colonne (11CS1) ; un circuit de verrouillage (L01), dont une extrémité d'entrée est couplée à une extrémité de sortie de la porte ET ; une porte OU (G01), dont une première extrémité d'entrée est couplée à l'extrémité de sortie de la porte ET, et dont une seconde extrémité d'entrée est couplée à une ligne de commande de déplacement de rangée (S0) ; un multiplexeur (M01), dont une première extrémité d'entrée est couplée à une tension préréglée (0), et dont une seconde extrémité d'entrée est couplée à une extrémité de sortie d'une unité de pixel qui se trouve dans la rangée précédente et dans la même colonne que l'unité de pixel ; et une porte XOR (X01), dont une première extrémité d'entrée est couplée à une extrémité de sortie du circuit de verrouillage, et dont une seconde extrémité d'entrée est couplée à une extrémité de sortie du multiplexeur.
PCT/CN2020/136413 2020-12-15 2020-12-15 Circuit de mesure du temps de vol, puce correspondante et appareil électronique WO2022126358A1 (fr)

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CN105739584A (zh) * 2014-08-20 2016-07-06 全视科技有限公司 用于飞行时间3d图像传感器的可编程电流源
CN109510955A (zh) * 2018-10-17 2019-03-22 天津大学 应用于三维图像传感器的背景噪声抑制像素结构
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CN102740012A (zh) * 2011-04-13 2012-10-17 半导体器件-埃尔法特系统-拉法合伙公司 检测器像素信号读出电路及其成像方法
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CN105739584A (zh) * 2014-08-20 2016-07-06 全视科技有限公司 用于飞行时间3d图像传感器的可编程电流源
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