WO2022121126A1 - 高清视频数据的发送、接收方法及设备 - Google Patents

高清视频数据的发送、接收方法及设备 Download PDF

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Publication number
WO2022121126A1
WO2022121126A1 PCT/CN2021/079016 CN2021079016W WO2022121126A1 WO 2022121126 A1 WO2022121126 A1 WO 2022121126A1 CN 2021079016 W CN2021079016 W CN 2021079016W WO 2022121126 A1 WO2022121126 A1 WO 2022121126A1
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Prior art keywords
protocol
definition video
video data
data
interface
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PCT/CN2021/079016
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English (en)
French (fr)
Inventor
高炳海
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深圳市朗强科技有限公司
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Priority to US17/442,629 priority Critical patent/US12010379B2/en
Publication of WO2022121126A1 publication Critical patent/WO2022121126A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/20—Servers specifically adapted for the distribution of content, e.g. VOD servers; Operations thereof
    • H04N21/23—Processing of content or additional data; Elementary server operations; Server middleware
    • H04N21/234—Processing of video elementary streams, e.g. splicing of video streams or manipulating encoded video stream scene graphs
    • H04N21/2343—Processing of video elementary streams, e.g. splicing of video streams or manipulating encoded video stream scene graphs involving reformatting operations of video signals for distribution or compliance with end-user requests or end-user device requirements
    • H04N21/234309—Processing of video elementary streams, e.g. splicing of video streams or manipulating encoded video stream scene graphs involving reformatting operations of video signals for distribution or compliance with end-user requests or end-user device requirements by transcoding between formats or standards, e.g. from MPEG-2 to MPEG-4 or from Quicktime to Realvideo
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/003—Details of a display terminal, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G09G5/006—Details of the interface to the display terminal
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
    • H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
    • H04N21/44—Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream or rendering scenes according to encoded video stream scene graphs
    • H04N21/4402—Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream or rendering scenes according to encoded video stream scene graphs involving reformatting operations of video signals for household redistribution, storage or real-time display
    • H04N21/440218—Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream or rendering scenes according to encoded video stream scene graphs involving reformatting operations of video signals for household redistribution, storage or real-time display by transcoding between formats or standards, e.g. from MPEG-2 to MPEG-4
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/60—Network structure or processes for video distribution between server and client or between remote clients; Control signalling between clients, server and network components; Transmission of management data between server and client, e.g. sending from server to client commands for recording incoming content stream; Communication details between server and client 
    • H04N21/61—Network physical structure; Signal processing
    • H04N21/6106—Network physical structure; Signal processing specially adapted to the downstream path of the transmission network
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/60—Network structure or processes for video distribution between server and client or between remote clients; Control signalling between clients, server and network components; Transmission of management data between server and client, e.g. sending from server to client commands for recording incoming content stream; Communication details between server and client 
    • H04N21/61—Network physical structure; Signal processing
    • H04N21/6156—Network physical structure; Signal processing specially adapted to the upstream path of the transmission network
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/60—Network structure or processes for video distribution between server and client or between remote clients; Control signalling between clients, server and network components; Transmission of management data between server and client, e.g. sending from server to client commands for recording incoming content stream; Communication details between server and client 
    • H04N21/63—Control signaling related to video distribution between client, server and network components; Network processes for video distribution between server and clients or between remote clients, e.g. transmitting basic layer and enhancement layers over different transmission paths, setting up a peer-to-peer communication via Internet between remote STB's; Communication protocols; Addressing
    • H04N21/643—Communication protocols
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/60—Network structure or processes for video distribution between server and client or between remote clients; Control signalling between clients, server and network components; Transmission of management data between server and client, e.g. sending from server to client commands for recording incoming content stream; Communication details between server and client 
    • H04N21/63—Control signaling related to video distribution between client, server and network components; Network processes for video distribution between server and clients or between remote clients, e.g. transmitting basic layer and enhancement layers over different transmission paths, setting up a peer-to-peer communication via Internet between remote STB's; Communication protocols; Addressing
    • H04N21/643—Communication protocols
    • H04N21/6437—Real-time Transport Protocol [RTP]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2350/00—Solving problems of bandwidth in display systems
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2370/00—Aspects of data communication
    • G09G2370/12—Use of DVI or HDMI protocol in interfaces along the display data pipeline

Definitions

  • the present application relates to the field of communication technologies, and in particular, to methods and devices for sending and receiving high-definition video data.
  • the present application provides a method and device for sending and receiving high-definition video data. Ultra-low latency transmission of high-definition video with lossless quality.
  • the present application provides a method for sending high-definition video data, and the sending method includes:
  • the sending device obtains high-definition video data in different color space formats through the input interface
  • the sending device processes the high-definition video data into data packets
  • the sending device sends the data packet to a first communication module; the transmission rate of the first communication module is not lower than a first threshold; the first communication module is configured to send the data packet.
  • the present application provides a method for receiving high-definition video data, the receiving method comprising:
  • the receiving device obtains the data packet through the second communication module; the transmission rate of the second communication module is not lower than the second threshold;
  • the receiving device processes the data packets to obtain high-definition video data.
  • the present application provides a device, comprising: a memory and a processor connected to the memory, the memory is used to store application code, the processor is configured to call the application code, The method for sending high-definition video data described in the first aspect is performed.
  • the present application provides a device, comprising: a memory and a processor connected to the memory, the memory is used to store application code, the processor is configured to call the application code, The method for receiving high-definition video data described in the second aspect is performed.
  • the present application provides a method and device for sending and receiving high-definition video data.
  • the sending method includes: the sending device obtains high-definition video data in different color space formats through an input interface, processes the high-definition video data into data packets, and sends the data packets to a first communication module to be used by the first communication module for data transmission. packets are sent to the receiving device.
  • the sending device can transmit the high-definition video data to the receiving device through the first communication module and based on the network cable or optical fiber, and can realize the ultra-low-latency transmission of the high-definition video with lossless quality.
  • FIG. 1 is a schematic flowchart of a method for sending high-definition video data provided by the present application
  • FIG. 5 is a schematic flowchart of a method for receiving high-definition video data provided by the present application
  • 6-9 are schematic structural diagrams of a device for sending high-definition video data provided by the present application.
  • 10-13 are schematic structural diagrams of a device for receiving high-definition video data provided by the present application.
  • FIG. 1 it is a schematic flowchart of a method for sending high-definition video data provided by the present application. As shown in FIG. 1, the sending method may include but is not limited to the following steps:
  • the sending device obtains high-definition video data in different color space formats through an input interface.
  • the sending device obtains high-definition video data in different color space formats through the input interface, which may include but not be limited to the following methods:
  • the sending device receives high-definition video data in different color space formats based on the HDMI (High Definition Multimedia Interface) protocol; specifically,
  • the sending device can receive high-definition video data in different color space formats from video source devices (such as DVDs, set-top boxes, cameras, etc.) through the HDMI protocol. It should be noted that the high-definition video data in the embodiments of the present application is source data or raw data.
  • High-definition video data may include, but is not limited to, multimedia data such as text, data, sound, graphics, images or video (such as high-definition video with 1080P, 4K or 8K resolution, and a frame rate of 30FPS, 60FPS, 100FPS or 120FPS).
  • High-definition video data may also include but not limited to the following features: High Dynamic Range HDR (High Dynamic Range Imaging), different color space formats can be 4:2:2 YUV, 4:2:0 YUV, 4:2:0 4:4 YUV mode or 8bit depth RGB mode.
  • Mode 2 The sending device receives high-definition video data in different color space formats through the Type-C protocol;
  • Mode 3 The sending device receives high-definition video data in different color space formats through the USB (Universal Serial Bus) protocol;
  • the sending device receives high-definition video data in different color space formats through the VGA (Video Graphics Array, video graphics array) protocol;
  • VGA Video Graphics Array, video graphics array
  • the sending device receives high-definition video data in different color space formats through the DP (DisplayPort) protocol;
  • the sending device receives high-definition video data in different color space formats through the MIPI (Mobile Industry Processor Interface) protocol;
  • MIPI Mobile Industry Processor Interface
  • Mode 7 The sending device receives and obtains high-definition video data in different color space formats through the LVDS (Low-Voltage Differential Signaling, low-voltage differential signaling) protocol.
  • LVDS Low-Voltage Differential Signaling, low-voltage differential signaling
  • Mode 8 The sending device receives and obtains high-definition video data in different color space formats through the TTL (Transistor Transistor Logic) protocol.
  • TTL Transistor Transistor Logic
  • Mode 9 The sending device receives and obtains high-definition video data in different color space formats through the DVI (Digital Visual Interface) protocol.
  • DVI Digital Visual Interface
  • the sending device processes the high-definition video data into data packets.
  • the sending device processes the high-definition video data into data packets, which may include the following methods:
  • the sending device further includes: a conversion chip; the conversion chip and the first integrated circuit are separately integrated in the sending device; specifically,
  • the sending device transmits the high-definition video data to the conversion chip in the FPGA chip based on the first interface protocol, and for the high-definition video data transmitted by the conversion chip based on the second interface protocol, the FPGA chip is based on UDP (User Datagram Protocol, user datagram protocol). ) communication protocol for encapsulation to obtain UDP data packets;
  • UDP User Datagram Protocol, user datagram protocol.
  • the first interface protocol includes: HDMI protocol, DVI protocol, Type-C protocol, DP protocol, USB protocol, MIPI protocol or VGA protocol;
  • the second interface protocol includes: TTL protocol, LVDS protocol, MIPI protocol or custom interface protocol ;
  • Custom interface protocol can be used to realize the mixed transmission of audio and video in high-definition video data;
  • TTL protocol and LVDS protocol can respectively realize the separate transmission of audio and video in high-definition video data;
  • the sending device transmits the high-definition video data to the conversion chip in the FPGA chip based on the first interface protocol, and sends the high-definition video data transmitted by the conversion chip based on the second interface protocol to the FPGA chip integrated in the sending device.
  • the above-mentioned high-definition video data is added with a UDP data packet header and a UDP data packet tail, wherein the UDP data packet header or the UDP data packet tail may include control information such as destination address, source address, port number, and flag bit.
  • the sending device transmits the high-definition video data to the conversion chip in the FPGA chip based on the first interface protocol.
  • the FPGA chip is based on TCP (Transmission Control Protocol, transmission control protocol).
  • the communication protocol is encapsulated to obtain TCP data packets; more specifically,
  • the sending device transmits the high-definition video data to the conversion chip in the FPGA chip based on the first interface protocol, and sends the high-definition video data transmitted by the conversion chip based on the second interface protocol to the above-mentioned first interface through the FPGA chip integrated in the sending device
  • the data is added with a TCP data packet header and a TCP data packet tail, wherein the TCP data packet header or the TCP data packet tail may include control information such as destination address, source address, port number, and flag bit.
  • the sending device transmits the high-definition video data to the conversion chip in the FPGA chip based on the first interface protocol, and encapsulates the high-definition video data transmitted by the conversion chip based on the second interface protocol through the FPGA chip based on the second custom communication protocol to obtain custom data package;; more specific,
  • the sending device transmits the high-definition video data to the conversion chip in the FPGA chip based on the first interface protocol, and sends the high-definition video data transmitted by the conversion chip based on the second interface protocol to the above-mentioned first interface through the FPGA chip integrated in the sending device Add a custom data packet header and a custom data packet tail to the data, wherein the custom data packet header or custom data packet tail may include control information such as destination address, source address, port number, and flag bit.
  • the first integrated circuit is an ASIC chip
  • the sending device transmits the high-definition video data to the conversion chip in the ASIC chip based on the first interface protocol, and for the high-definition video data transmitted by the conversion chip based on the second interface protocol, the ASIC chip is based on UDP (User Datagram Protocol, User Datagram Protocol). ) communication protocol to encapsulate to obtain UDP data packets; or,
  • the sending device transmits the high-definition video data to the conversion chip in the ASIC chip based on the first interface protocol.
  • the FPGA chip is based on TCP (Transmission Control Protocol, transmission control protocol).
  • the communication protocol is encapsulated to obtain a TCP packet; or,
  • the sending device transmits the high-definition video data to the conversion chip in the FPGA chip based on the first interface protocol, and encapsulates the high-definition video data transmitted by the conversion chip based on the second interface protocol through the FPGA chip based on the second custom communication protocol to obtain custom data package; .
  • the communication protocol may include, but is not limited to: UDP communication protocol, TCP communication protocol or custom communication protocol.
  • the first integrated circuit is an FPGA chip
  • the sending device transmits the high-definition video data to the conversion chip in the FPGA chip based on the first interface protocol, and encapsulates the high-definition video data transmitted by the conversion chip based on the second interface protocol through the FPGA chip based on the UDP communication protocol to obtain UDP data packets ;
  • the sending device transmits the high-definition video data to the conversion chip in the FPGA chip based on the first interface protocol, and encapsulates the high-definition video data transmitted by the conversion chip based on the second interface protocol through the FPGA chip based on the TCP communication protocol to obtain TCP data packets ;
  • the sending device transmits the high-definition video data to the conversion chip in the FPGA chip based on the first interface protocol, and encapsulates the high-definition video data transmitted by the conversion chip based on the second interface protocol based on the custom communication protocol through the FPGA chip to obtain a custom data pack;
  • the first integrated circuit is an ASIC chip
  • the sending device transmits the high-definition video data to the conversion chip in the ASIC chip based on the first interface protocol, and encapsulates the high-definition video data transmitted by the conversion chip based on the second interface protocol through the ASIC chip based on the UDP communication protocol to obtain UDP data packets ;or,
  • the sending device transmits the high-definition video data to the conversion chip in the ASIC chip based on the first interface protocol, and encapsulates the high-definition video data transmitted by the conversion chip based on the second interface protocol through the ASIC chip based on the TCP communication protocol to obtain TCP data packets ;or,
  • the sending device transmits the high-definition video data to the conversion chip in the ASIC chip based on the first interface protocol, and encapsulates the high-definition video data transmitted by the conversion chip based on the second interface protocol based on the custom communication protocol through the ASIC chip to obtain a custom data pack;
  • the sending device encapsulates the high-definition video data into UDP data packets based on the UDP communication protocol through the FPGA chip integrated in the sending device; more specifically,
  • the sending device adds a UDP data packet header and a UDP data packet tail to the above-mentioned high-definition video data through an FPGA chip integrated in the sending device, wherein the UDP data packet header or the UDP data packet tail may include: destination address, source address, port number, marker bit and other control information.
  • the sending device encapsulates the high-definition video data into TCP packets based on the TCP communication protocol through the FPGA chip;
  • the sending device adds a TCP data packet header and a TCP data packet tail to the above-mentioned high-definition video data through an FPGA chip integrated in the sending device, wherein the TCP data packet header or the TCP data packet tail may include: destination address, source address, port number, marker bit and other control information.
  • the sending device encapsulates the high-definition video data into a custom data packet based on a custom communication protocol through the FPGA chip.
  • the sending device adds a custom data packet header and a custom data packet tail to the above-mentioned high-definition video data through an FPGA chip integrated in the sending device, wherein the custom data packet header or custom data packet tail may include: destination address, source address, port control information such as number, flag bit, etc.
  • the sending device encapsulates the high-definition video data into UDP data packets based on the UDP communication protocol through the ASIC chip integrated in the sending device.
  • Approach 7 The sending device encapsulates the high-definition video data into TCP data packets based on the TCP communication protocol through the ASIC chip.
  • the sending device encapsulates the high-definition video data into a custom data packet based on a custom communication protocol through an ASIC chip.
  • the sending device includes: a first integrated circuit
  • the first integrated circuit is an FPGA chip
  • the sending device compresses the high-definition video data through an FPGA chip based on a distortion-free coding algorithm to obtain first data, and encapsulates the first data through a communication protocol to obtain a data packet;
  • the first integrated circuit is an ASIC chip
  • the sending device compresses the high-definition video data through an ASIC chip based on a distortion-free coding algorithm to obtain first data, and encapsulates the first data through a communication protocol to obtain a data packet;
  • the communication protocol includes: UDP communication protocol, TCP communication protocol or second custom communication protocol;
  • Distortionless coding algorithms which may include but are not limited to:
  • Run-length coding algorithm Huffman coding algorithm, constant block coding algorithm for binary images, quadtree coding algorithm, wavelet transform coding algorithm or custom arithmetic coding algorithm.
  • the first integrated circuit can compress the redundant data in the high-definition video data based on the custom arithmetic coding algorithm to obtain the first data, and encapsulate the first data through the communication protocol to obtain the first data. data pack.
  • the first integrated circuit compresses the redundant data in the high-definition video data based on a self-defined arithmetic coding algorithm, and can obtain only the The first data (0600) occupying 2 bytes realizes the compression of redundant data in the high-definition video data.
  • the sending device sends the data packet to the first communication module.
  • the transmission rate of the first communication module is not lower than the first threshold; the first threshold may include, but is not limited to: 1 Gbps, 2.5 Gbps, 5 Gbps, 10 Gbps, or 25 Gbps.
  • sending device sending the data packet to the first communication module may include but not be limited to the following methods:
  • the first communication module includes: an electrical module; the electrical module includes: a PHY chip and an RJ-45 interface;
  • the sending device transmits the data packet to the PHY chip (Ethernet physical layer data transceiver) through the MAC unit based on the third interface protocol, the PHY chip is used to output the data packet to the RJ-45 interface, and the RJ-45 interface is used to transmit the data packet.
  • the third interface protocol includes: XFI protocol, MII (Media Independent Interface) protocol, GMII (Gigabit Media Independent Interface) protocol, RGMII (Reduced Gigabit Media Independent Interface) protocol, SGMII (Serial Gigabit Media Independent Interface) protocol , Serdes protocol, XAUI protocol or RXAUI protocol; data packets include: UDP data packets, TCP data packets or custom data packets.
  • the first communication module includes: an optical module;
  • the sending device transmits the data packet to the optical module based on the third interface protocol through the MAC unit; the optical module is used to convert the data packet into an optical signal, and transmit the optical signal based on the optical fiber.
  • the above-mentioned optical module may include but is not limited to: single-fiber bidirectional Optical modules (specifically, may include: single-mode optical modules for long-distance transmission and multi-mode optical modules for short-distance transmission).
  • the first communication module is an electrical module
  • the sending device sends the data packet to the first communication module
  • the following process may also be performed:
  • the sending device modulates the data packet through the PHY chip and outputs it to the RJ-45 interface, and sends it to the receiving device through the RJ-45 interface; or,
  • the sending device modulates the data packet through the PHY chip and outputs it to the RJ-45 interface, and sends it to the switch through the RJ-45 interface, and the switch is used to forward the data packet to the receiving device;
  • the data packets include: UDP data packets, TCP data packets or custom data packets.
  • FIG. 2 exemplarily shows a schematic diagram of a transmission scenario of high-definition video data.
  • the sending device transmits the above-mentioned data packet to the receiving device through the first communication module based on a network cable or an optical fiber.
  • FIG. 3 exemplarily shows a scene diagram of transmission of high-definition video data.
  • the sending device transmits the above-mentioned data packet to the switch based on the network cable or optical fiber through the first communication module, and then uses the switch to forward the above-mentioned data packet to the receiving device.
  • the first communication module is an optical module
  • the sending device sends the data packet to the first communication module
  • the following process may also be performed:
  • the sending device converts the data packet into an optical signal through the optical module, and sends the optical signal to the receiving device; or,
  • the sending device converts the data packet into an optical signal through the optical module, and sends the optical signal to the switch, and the switch is used to forward the optical signal to the receiving device;
  • the data packets include: UDP data packets, TCP data packets or custom data packets.
  • the receiving device includes: a first receiving device and a second receiving device;
  • the data packet includes: a UDP data packet or a TCP data packet;
  • the sending device sends the data packet to the first communication module
  • the following process may also be performed:
  • the sending device modulates the UDP data packet through the PHY chip and outputs it to the RJ-45 interface, and sends it to the switch through the RJ-45 interface, and the switch is used to forward the UDP data packet to the first receiving device and the second receiving device respectively; or,
  • the sending device modulates the TCP data packet through the PHY chip and outputs it to the RJ-45 interface, and sends it to the switch through the RJ-45 interface, and the switch is used to forward the TCP data packet to the first receiving device and the second receiving device respectively.
  • the receiving device includes: a first receiving device and a second receiving device
  • the data packet includes: a UDP data packet or a TCP data packet
  • the sending device sends the data packet to the first communication module
  • the following process may also be performed:
  • the sending device converts the UDP data packet or the TCP data packet into an optical signal through the optical module, and sends the optical signal to the switch, and the switch is used for forwarding the optical signal to the first receiving device and the second receiving device.
  • FIG. 4 exemplarily shows another scenario diagram of high-definition video data transmission.
  • the receiving device includes: a first receiving device and a second receiving device;
  • the sending device transmits the UDP data packet to the switch based on the network cable or the optical fiber through the first communication module, and then uses the switch to forward the UDP data packet to the receiving device.
  • the sending device transmits the TCP data packet to the switch based on the network cable or the optical fiber through the first communication module, and then uses the switch to forward the TCP data packet to the receiving device.
  • FIG. 5 it is a schematic flowchart of a method for receiving high-definition video data provided by the present application. As shown in FIG. 5 , the receiving method may include but is not limited to the following steps:
  • the receiving device acquires the data packet through the second communication module.
  • the transmission rate of the second communication module is not lower than the second threshold, where the second threshold may include but is not limited to: 1 Gbps, 2.5 Gbps, 5 Gbps, 10 Gbps, or 25 Gbps.
  • the receiving device obtains the data packet through the second communication module, which may include but is not limited to the following methods:
  • Mode 1 when the second communication module includes: an electrical module, the electrical module includes: a PHY chip and an RJ-45 interface;
  • the receiving device receives the data packet sent by the sending device or forwarded by the switch through the RJ-45 interface integrated in the receiving device, and transmits it to the PHY chip (Ethernet physical layer data transceiver); specific,
  • the second communication module includes: an optical module
  • the receiving device converts the received optical signal sent by the sending device or forwarded by the switch into data packets through the optical module integrated in the receiving device.
  • the above-mentioned optical modules may include but are not limited to: single-fiber bidirectional optical modules (specifically, may include: single-mode optical modules for long-distance transmission and multi-mode optical modules for short-distance transmission)
  • the receiving device may output the data packet received by the second communication module to the second integrated circuit.
  • the receiving device processes the data packets to obtain high-definition video data.
  • the receiving device processes the data packets to obtain high-definition video data, which may include but are not limited to the following methods:
  • the receiving device further includes: a conversion chip; the conversion chip and the second integrated circuit are independently integrated in the receiving device; specifically,
  • the second integrated circuit is an FPGA chip
  • the receiving device decapsulates the UDP data packets based on the UDP communication protocol through the FPGA chip, obtains high-definition video data, and outputs the high-definition video data to the conversion chip through the fourth interface protocol;
  • the fourth interface protocol includes: TTL protocol, LVDS protocol, MIPI protocol or custom interface protocol; specifically,
  • the sending device removes the UDP data packet header and the UDP data packet tail, etc. from the UDP data packet through the FPGA chip integrated in the sending device based on the UDP protocol to obtain high-definition video data, and outputs the high-definition video data to the conversion chip through the fourth interface protocol.
  • the receiving device decapsulates the TCP data packets based on the TCP communication protocol through the FPGA chip, obtains high-definition video data, and outputs the high-definition video data to the conversion chip through the fourth interface protocol; specifically,
  • the sending device removes the TCP data packet header, TCP data packet tail, etc. from the TCP data packet through the FPGA chip integrated in the sending device based on the TCP protocol to obtain high-definition video data, and outputs the high-definition video data to the conversion chip through the fourth interface protocol.
  • the receiving device decapsulates the custom data packet based on the custom communication protocol through the FPGA chip, obtains high-definition video data, and outputs the high-definition video data to the conversion chip through the fourth interface protocol; specifically,
  • the transmitting device removes the custom data packet header, custom data packet tail, etc. from the custom data packet through the FPGA chip integrated in the transmitting device based on the custom communication protocol, and obtains high-definition video data, and transmits the high-definition video data through the fourth interface protocol. output to the conversion chip.
  • the second integrated circuit is an ASIC chip
  • the receiving device decapsulates the UDP data packet based on the UDP communication protocol through the ASIC chip, obtains high-definition video data, and outputs the high-definition video data to the conversion chip through the fourth interface protocol; or,
  • the receiving device decapsulates the TCP data packets based on the TCP communication protocol through the ASIC chip, obtains high-definition video data, and outputs the high-definition video data to the conversion chip through the fourth interface protocol; or,
  • the receiving device decapsulates the custom data packet based on the custom communication protocol through the ASIC chip, obtains high-definition video data, and outputs the high-definition video data to the conversion chip through the fourth interface protocol.
  • the receiving device further includes: a conversion chip; the conversion chip is integrated inside the second integrated circuit;
  • the second integrated circuit is an FPGA chip
  • the receiving device decapsulates the UDP data packets based on the UDP communication protocol through the FPGA chip, obtains high-definition video data, and outputs the high-definition video data to the conversion chip through the fourth interface protocol; or,
  • the receiving device decapsulates the TCP data packets based on the TCP communication protocol through the FPGA chip to obtain high-definition video data, and outputs the high-definition video data to the conversion chip through the fourth interface protocol; or,
  • the receiving device decapsulates the custom data packet based on the custom communication protocol through the FPGA chip, obtains high-definition video data, and outputs the high-definition video data to the conversion chip through the fourth interface protocol; or,
  • the second integrated circuit is an ASIC chip
  • the receiving device decapsulates the UDP data packets based on the UDP communication protocol through the ASIC chip, obtains high-definition video data, and outputs the high-definition video data to the conversion chip through the fourth interface protocol; or,
  • the receiving device decapsulates the TCP data packets based on the TCP communication protocol through the ASIC chip, obtains high-definition video data, and outputs the high-definition video data to the conversion chip through the fourth interface protocol; or,
  • the receiving device decapsulates the custom data packet based on the custom communication protocol through the ASIC chip, obtains high-definition video data, and outputs the high-definition video data to the conversion chip through the fourth interface protocol.
  • Mode 3 When the receiving device includes: a second integrated circuit, and the second integrated circuit is an FPGA chip, the receiving device processes the UDP data packets based on the UDP communication protocol through the FPGA chip integrated in the receiving device to obtain high-definition video data; specific,
  • the sending device removes the UDP data packet header, the UDP data packet tail, etc. from the UDP data packet based on the UDP protocol through the FPGA chip integrated in the sending device to obtain high-definition video data.
  • Mode 4 When the receiving device includes: a second integrated circuit, and the second integrated circuit is an FPGA chip, the receiving device decapsulates the TCP data packets based on the TCP communication protocol through the FPGA chip to obtain high-definition video data; specifically,
  • the sending device removes the TCP data packet header, TCP data packet tail, etc. from the TCP data packet based on the TCP protocol through the FPGA chip integrated in the sending device to obtain high-definition video data.
  • Mode 5 when the receiving device includes: a second integrated circuit, and the second integrated circuit is an FPGA chip, the receiving device decapsulates the custom data packet through the FPGA chip based on a custom communication protocol to obtain high-definition video data; specifically,
  • the sending device removes the custom data packet header, custom data packet tail, etc. from the custom data packet based on the custom communication protocol through the FPGA chip integrated in the transmitting device, and obtains high-definition video data.
  • Mode 6 when the receiving device includes: a second integrated circuit, and the second integrated circuit is an ASIC chip, the receiving device decapsulates the UDP data packet based on the UDP communication protocol through the ASIC chip integrated in the receiving device to obtain high-definition video data;
  • Mode 7 When the receiving device includes: a second integrated circuit, and the second integrated circuit is an ASIC chip, the receiving device decapsulates the TCP data packets based on the TCP communication protocol through the ASIC chip to obtain high-definition video data;
  • Manner 8 When the receiving device includes: a second integrated circuit, and the second integrated circuit is an ASIC chip, the receiving device decapsulates the custom data packet through the ASIC chip based on a custom communication protocol to obtain high-definition video data.
  • the receiving device includes: a second integrated circuit; when the second integrated circuit is an FPGA chip,
  • the receiving device decapsulates the data packet based on the communication protocol through the FPGA chip to obtain the first data, and decompresses the first data based on the distortion-free decoding algorithm to obtain the high-definition video data;
  • Communication protocols include: UDP communication protocol, TCP communication protocol or custom communication protocol;
  • Distortion-free decoding algorithms including: run-length decoding algorithm, Huffman decoding algorithm, constant block decoding algorithm for binary images, quadtree decoding algorithm, wavelet transform decoding algorithm or self-defined arithmetic decoding algorithm.
  • the receiving device may perform interpolation on the first data based on a user-defined arithmetic decoding algorithm to restore high-definition video data.
  • the receiving device processes the data packets through the second integrated circuit and obtains the high-definition video data, the following process may also be performed:
  • the receiving device outputs the high-definition video data to the display device through the fifth interface protocol;
  • the fifth interface protocol includes: HDMI protocol, DVI protocol, Type-C protocol, DP protocol, USB protocol, MIPI protocol or VGA protocol.
  • the present application provides a sending device, as shown in FIG. 6 , which can be used to implement the method for sending high-definition video data described in the method embodiment of FIG. 1 . specific,
  • the sending device 60 may include, but is not limited to: the input interface 601 , the first integrated circuit 602 , and the first communication module 603 , and may also include a conversion chip. It should be noted that the conversion chip and the first integrated circuit 602 are independently integrated in the sending device; wherein,
  • a conversion chip configured to output the high-definition video data to the first integrated circuit through the first communication timing interface of the conversion chip after receiving the high-definition video data through the interface coupled with the input interface 601;
  • the first communication timing interface includes: LVDS (Low-Voltage Differential Signaling, low voltage differential signaling) interface, TTL (Transistor Transistor Logic) interface, MIPI interface or custom interface.
  • LVDS Low-Voltage Differential Signaling, low voltage differential signaling
  • TTL Transistor Transistor Logic
  • the LVDS interface or the TTL interface may be respectively an interface used for separate transmission of audio and video in high-definition video data; a custom interface is an interface used for mixed transmission of audio and video in high-definition video data.
  • the first integrated circuit 602 can be used to process the high-definition video data into data packets based on the communication protocol;
  • the first communication module 603 is used for sending data packets.
  • high-definition video data in different color space formats in the embodiments of the present application are source data or raw data.
  • High-definition video data in different color space formats may include, but are not limited to, such as text, data, sound, graphics, images or videos (such as 1080P, 4K or 8K resolution, frame rate of 30FPS, 60FPS, 100FPS or 120FPS high-definition video) and other multimedia data.
  • High-definition video data may also include but not limited to the following features: High Dynamic Range HDR (High Dynamic Range Imaging), different color space formats can be 4:2:2 YUV, 4:2:0 YUV, 4:2:0 4:4 YUV mode or 8bit depth RGB mode.
  • the input interface 101 may include, but is not limited to:
  • HDMI High Definition Multimedia Interface
  • Type-C interface DVI interface
  • DP interface DVI interface
  • USB interface USB interface
  • VGA interface VGA interface
  • LVDS interface TTL interface
  • MIPI interface MIPI interface
  • the above-mentioned communication protocol includes: UDP communication protocol, TCP communication protocol or custom communication protocol; the first integrated circuit 602 may include but not limited to: FPGA chip or ASIC chip.
  • the first integrated circuit 602 can be specifically used for:
  • the transmission rate of the first communication module 603 is not lower than the first threshold
  • first integrated circuit 602 can also be specifically used for:
  • the high-definition video data is compressed based on a distortion-free encoding algorithm to obtain first data, and the first data is encapsulated through a communication protocol to obtain a data packet.
  • Distortionless encoding algorithms including:
  • Run-length coding algorithm Huffman coding algorithm, constant block coding algorithm for binary images, quadtree coding algorithm, wavelet transform coding algorithm or custom arithmetic coding algorithm.
  • the first integrated circuit 602 can compress the redundant data in the high-definition video data based on the custom arithmetic coding algorithm to obtain the first data, and encapsulate the first data through the communication protocol, Get packets.
  • the first communication module 603 may include, but is not limited to, an electrical module or an optical module, wherein the electrical module includes: a PHY chip and an RJ-45 interface, the transmission rate of the optical module is not lower than the first threshold; the transmission rate of the electrical module is not lower than the first threshold.
  • the first threshold may include, but is not limited to: 1 Gbps, 2.5 Gbps, 5 Gbps, 10 Gbps, or 25 Gbps.
  • the transmission rate of the electrical module is not lower than the first threshold; the electrical module is used for:
  • the data packet is output to the RJ through the PHY chip -45 interface, sent to the receiving device through the RJ-45 interface, or,
  • the data packet is output to the RJ-45 interface through the PHY chip, and sent to the switch through the RJ-45 interface, and the switch is used to forward the data packet to the receiving device; or,
  • the transmission rate of the optical module is not lower than the first threshold
  • Optical modules are used for:
  • the first integrated circuit 602 After the first integrated circuit 602 outputs the data packet to the MAC unit integrated in the first integrated circuit 602, and outputs the data packet to the optical module through the second communication timing interface of the MAC unit,
  • the second communication timing interface includes: XFI interface, GMII interface, SMII interface, RGMII interface, XGMII interface, Serdes interface, XAUI interface or RXAUI interface; data packets include: UDP data packets, TCP data packets or custom data packets .
  • the sending device 60 can also be used for:
  • the sending device 60 sends the data packet to the first communication module 603, the data packet is output to the receiving device through the first communication module; or,
  • the sending device 60 sends the data packet to the first communication module 603
  • the first communication module outputs the data packet to the switch, and the switch can be used to forward the data packet to the receiving device.
  • the sending device 60 is only an example provided by the embodiments of the present application, and the sending device 60 may have more or less components than those shown, may combine two or more components, or may have a combination of components Different configurations are implemented.
  • the present application provides another sending device, as shown in FIG. 7 , which can be used to implement the method for sending high-definition video data described in the method embodiment of FIG. 1 . specific,
  • the sending device 70 may include, but is not limited to, the input interface 701 , the first integrated circuit 702 and the first communication module 703 , and may also include a conversion chip, wherein the conversion chip is integrated in the first integrated circuit 702 internal;
  • a first integrated circuit 702 which can be used to process high-definition video data into data packets
  • the first integrated circuit 702 can be specifically used for:
  • the high-definition video data is output to the first integrated circuit through the first communication timing interface of the conversion chip, the high-definition video data is encapsulated into a UDP data packet based on the UDP communication protocol; or,
  • the high-definition video data is output to the first integrated circuit through the first communication timing interface of the conversion chip, the high-definition video data is encapsulated into a TCP data packet based on the TCP communication protocol; or,
  • the high-definition video data is output to the first integrated circuit through the first communication timing interface of the conversion chip, the high-definition video data is encapsulated into a custom data packet based on a custom communication protocol.
  • first integrated circuit 702 can also be specifically used for:
  • the high-definition video data is output to the first integrated circuit through the first communication timing interface of the conversion chip, the high-definition video data is compressed based on the distortionless coding algorithm to obtain the first data, and the first data is passed through the above-mentioned communication protocol (such as : UDP communication protocol, TCP communication protocol or custom communication protocol) to encapsulate to obtain data packets.
  • the above-mentioned communication protocol such as : UDP communication protocol, TCP communication protocol or custom communication protocol
  • Distortionless encoding algorithms including:
  • Run-length coding algorithm Huffman coding algorithm, constant block coding algorithm for binary images, quadtree coding algorithm, wavelet transform coding algorithm or custom arithmetic coding algorithm.
  • the first communication module 703 is used for sending data packets.
  • the sending device 70 is only an example provided by the embodiments of the present application, and the sending device 70 may have more or less components than those shown, may combine two or more components, or may have a combination of components Different configurations are implemented.
  • the present application provides another sending device, as shown in FIG. 8 , which can be used to implement the method for sending high-definition video data described in the method embodiment of FIG. 1 . specific,
  • the sending device 80 may include, but is not limited to, an input interface 801 , a first integrated circuit 802 , a first communication module 803 , and a conversion chip, wherein the conversion chip and the first communication module 803 are integrated inside the first integrated circuit 802 .
  • a conversion chip used for outputting the high-definition video data to the first integrated circuit 802 through the first communication timing interface of the conversion chip;
  • the first integrated circuit 802 is used to process the high-definition video data output by the first communication timing interface of the conversion chip in the first integrated circuit 802 to obtain data packets;
  • the first communication module 803 is used for sending data packets.
  • the present application provides another sending device, as shown in FIG. 9 , which can be used to implement the method for sending high-definition video data described in the method embodiment of FIG. 1 . specific,
  • the sending device 90 may include, but is not limited to, an input interface 901 , a first integrated circuit 902 and a first communication module 903 , wherein the input interface 901 , the first integrated circuit 902 and the first communication module 903 are connected in sequence.
  • the first communication module 903 is used for sending data packets.
  • high-definition video data may include, but are not limited to, such as text, data, sound, graphics, images or videos (such as high-definition video with 1080P, 4K or 8K resolution, and a frame rate of 30FPS, 60FPS, 100FPS or 120FPS), etc.
  • the high-definition video data may also include, but not be limited to, the following features: High Dynamic Range HDR (High Dynamic Range Imaging), and the data format is 4:2:2 YUV, 4:2:0 YUV, or 8-bit depth. RGB method.
  • the above communication protocols include: UDP communication protocol, TCP communication protocol or custom communication protocol;
  • the input interface 901 may include, but is not limited to:
  • HDMI interface Type-C interface
  • DP interface USB interface
  • VGA interface VGA interface
  • DVI interface MIPI interface
  • the first integrated circuit 902 may include, but is not limited to, an FPGA chip or an ASIC chip.
  • the first integrated circuit 902 can be specifically used for:
  • first integrated circuit 902 can also be specifically used for:
  • the high-definition video data is compressed based on a distortionless coding algorithm to obtain first data, and the first data is encapsulated through the above communication protocol (eg, UDP communication protocol, TCP communication protocol or self-defined communication protocol) to obtain data packets.
  • the above communication protocol eg, UDP communication protocol, TCP communication protocol or self-defined communication protocol
  • the first communication module 903 may include, but is not limited to, an electrical module or an optical module, wherein the electrical module includes: a PHY chip and an RJ-45 interface, the transmission rate of the optical module is not lower than the first threshold; the transmission rate of the electrical module is not lower than the first threshold.
  • the first threshold may include, but is not limited to: 1 Gbps, 2.5 Gbps, 5 Gbps, 10 Gbps, or 25 Gbps.
  • the sending device 90 can also be used for:
  • the sending device 90 After the sending device 90 sends the data packet to the first communication module 903 whose transmission rate is not lower than the first threshold, the data packet is output to the receiving device through the first communication module; or,
  • the sending device 90 sends the data packet to the first communication module 903 whose transmission rate is not lower than the first threshold
  • the first communication module outputs the data packet to the switch, and the switch can be used to forward the data packet to the receiving device.
  • the sending device 90 is only an example provided by the embodiments of the present application, and the sending device 80 may have more or less components than those shown, may combine two or more components, or may have a combination of components Different configurations are implemented.
  • the present application provides a receiving device, as shown in FIG. 10 , which can be used to implement the high-definition video data receiving method described in the method embodiment of FIG. 5 . specific,
  • the receiving device 100 may include, but is not limited to, the second communication module 1001, the second integrated circuit 1002, and the output interface 1003, and may also include a conversion chip. It should be noted that the conversion chip and the second integrated circuit 1002 are independently integrated. in the sending device; wherein,
  • the second communication module 1001 can be used to: obtain data packets from a sending device, or obtain data packets from a switch;
  • the second integrated circuit 1002 may be used for: processing the data packet to obtain high-definition video data; wherein, the second integrated circuit 1002 may include but not limited to: an FPGA chip or an ASIC chip.
  • the conversion chip is used for outputting the high-definition video data to the output interface 1003 through the third communication timing interface of the conversion chip.
  • the third communication timing interface may include but not limited to: HDMI interface, DVI interface, Type-C interface, DP interface, USB interface, VGA interface or MIPI interface.
  • the electrical module includes: a PHY chip and an RJ-45 interface;
  • Electrical modules can be used for:
  • the fourth communication timing interface includes: : XFI interface, GMII interface, SMII interface, RGMII interface, XGMII interface, Serdes interface, XAUI interface, or RXAUI interface; or,
  • the second communication module 1001 is an optical module; the transmission rate of the optical module is not lower than the second threshold;
  • Optical modules which can be used for:
  • the optical signal forwarded by the switch is received, and the optical signal is converted into a data packet, and the data packet is output to the second integrated circuit 1002 through the fourth communication timing interface of the MAC unit in the second integrated circuit 1002 .
  • the data packets include: UDP data packets, TCP data packets or custom data packets.
  • the second integrated circuit 1002 can be specifically used for:
  • the data packet is a UDP data packet
  • the data packet is a TCP data packet
  • the custom data packet is decapsulated into high-definition video data based on the custom communication protocol.
  • the second integrated circuit 1002 can also be used for:
  • Decapsulate the data packets based on a communication protocol such as a UDP communication protocol, a TCP communication protocol or a custom communication protocol
  • a communication protocol such as a UDP communication protocol, a TCP communication protocol or a custom communication protocol
  • the data packet is a UDP data packet
  • the data packet is a TCP data packet
  • the data packet is a user-defined data packet
  • the user-defined data packet is decapsulated based on the user-defined communication protocol to obtain first data
  • the first data is decompressed based on a distortion-free decoding algorithm to obtain high-definition video data.
  • Distortion-free decoding algorithms including:
  • Run-length decoding algorithm Huffman decoding algorithm, constant block decoding algorithm for binary images, quadtree decoding algorithm, wavelet transform decoding algorithm or custom arithmetic decoding algorithm.
  • the second integrated circuit 1002 can be specifically configured to: interpolate the first data based on a self-defined arithmetic decoding algorithm to restore high-definition video data.
  • the output interface 1003 can be used for: outputting the above-mentioned high-definition video data to an output device (eg, a display device) connected to the receiving device 100
  • an output device eg, a display device
  • the second communication module 1001 may include, but is not limited to: an electrical module or an optical module; the transmission rate of the optical module is not lower than the second threshold; the transmission rate of the electrical module is not lower than the second threshold; Including but not limited to: 1Gbps, 2.5Gbps, 5Gbps, 10Gbps or 25Gbps.
  • the receiving device 100 is only an example provided by the embodiments of the present application, and the receiving device 100 may have more or less components than those shown, may combine two or more components, or may have a combination of components Different configurations are implemented.
  • the present application provides another receiving device, as shown in FIG. 11 , which can be used to implement the high-definition video data receiving method described in the method embodiment of FIG. 5 .
  • the receiving device 110 may include, but is not limited to, the second communication module 1101 , the second integrated circuit 1102 , and the output interface 1103 , and further include: a conversion chip, which is integrated inside the second integrated circuit 1102 ;
  • the second communication module 1101 can be used to: obtain data packets from the sending device, or obtain data packets from the switch;
  • the second integrated circuit 1102 can be specifically used for:
  • the UDP data packet is decapsulated into high-definition video data based on the UDP communication protocol, and the high-definition video data is output to the output interface 203 through the third communication timing interface of the conversion chip through the conversion chip;
  • the third communication timing interface includes: HDMI interface , Type-C interface, DVI interface, DP interface, USB interface, VGA interface or MIPI interface; or,
  • the output interface 1103 can be used to output high-definition video data to a display device (eg, a display).
  • a display device eg, a display
  • the receiving device 110 is only an example provided by the embodiments of the present application, and the receiving device 100 may have more or less components than those shown, may combine two or more components, or may have a combination of components Different configurations are implemented.
  • the present application provides another receiving device, as shown in FIG. 12 , which can be used to implement the high-definition video data receiving method described in the method embodiment of FIG. 5 .
  • the receiving device 120 may include, but is not limited to: the second communication module 1201 , the second integrated circuit 1202 and the output interface 1203 , and also include: a conversion chip, the second communication module 1201 and the conversion chip are integrated in the second integrated circuit 1202 internal;
  • the second communication module 1201 can be used to: obtain data packets from the sending device, or obtain data packets from the switch;
  • the second integrated circuit 1202 can be used for: processing the data packets input to the second integrated circuit 1202 through the fourth communication timing interface of the MAC unit in the second integrated circuit 1202 to obtain high-definition video data, and through the third communication of the conversion chip
  • the timing interface outputs high-definition video data to the output interface 1203;
  • the second integrated circuit 1202 may include, but is not limited to, an FPGA chip or an ASIC chip.
  • the second communication module 1201 may include, but is not limited to: an electrical module or an optical module; the transmission rate of the optical module is not lower than the second threshold; the transmission rate of the electrical module is not lower than the second threshold; Including but not limited to: 1Gbps, 2.5Gbps, 5Gbps, 10Gbps or 25Gbps.
  • the present application provides another receiving device, as shown in FIG. 13 , which can be used to implement the high-definition video data receiving method described in the method embodiment of FIG. 5 .
  • the receiving device 130 may include, but is not limited to, a second communication module 1301, a second integrated circuit 1302, and an output interface 1303, wherein the second communication module 1301, the second integrated circuit 1302, and the output interface 1303 are connected in sequence.
  • the second communication module 1301 can be used to: obtain data packets from the sending device, or obtain data packets from the switch;
  • the second integrated circuit 1302 can be used for: processing the above-mentioned data packets based on the communication protocol to obtain high-definition video data.
  • the output interface 1303 can be used to output high-definition video data to an output device (eg, a display device).
  • an output device eg, a display device
  • the second integrated circuit 1302 can be specifically used for:
  • the UDP data packet is decapsulated based on the UDP communication protocol to obtain high-definition video data; or,
  • the data packet is a TCP data packet
  • the custom data packet is decapsulated based on the custom communication protocol to obtain high-definition video data.
  • the second integrated circuit 1302 can also be specifically used for:
  • the data packet is a UDP data packet
  • the data packet is a TCP data packet
  • the data packet is a user-defined data packet
  • the user-defined data packet is decapsulated based on the user-defined communication protocol to obtain first data
  • the first data is decompressed based on a distortion-free decoding algorithm to obtain high-definition video data.
  • Distortion-free decoding algorithms including:
  • Run-length decoding algorithm Huffman decoding algorithm, constant block decoding algorithm for binary images, quadtree decoding algorithm or wavelet transform decoding algorithm.
  • the above communication protocols include: UDP communication protocol, TCP communication protocol or custom communication protocol;
  • output interface 1303 may include, but is not limited to:
  • HDMI interface DVI interface, Type-C interface, DP interface, USB interface, VGA interface or MIPI interface.
  • the second integrated circuit 1302 may include, but is not limited to, an FPGA chip or an ASIC chip.
  • the transmission rate of the second communication module 1301 is not lower than the second threshold
  • the second communication module 1301 may include but is not limited to: an electrical module or an optical module; the transmission rate of the optical module is not lower than the second threshold; the transmission rate of the electrical module is not lower than the second threshold; wherein the second threshold may include but Not limited to: 1Gbps, 2.5Gbps, 5Gbps, 10Gbps or 25Gbps.
  • the receiving device 110 is only an example provided by the embodiments of the present application, and the receiving device 110 may have more or less components than those shown, may combine two or more components, or may have a combination of components Different configurations are implemented.
  • the division of the modules is only a logical function division. In actual implementation, there may be other division methods. For example, multiple modules or components may be combined or May be integrated into another device, or some features may be omitted, or not implemented.
  • the shown or discussed mutual coupling or direct coupling or communication connection may be indirect coupling or communication connection through some interfaces, devices, devices or modules, and may also be electrical, mechanical or other forms of connection.
  • modules described as separate components may or may not be physically separated, and the components shown as modules may or may not be physical modules, that is, may be located in one place, or may be distributed to multiple network modules. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solutions of the embodiments of the present application.
  • each functional module in each embodiment of the present application may be integrated into one processing module, or each module may exist physically alone, or two or more modules may be integrated into one module.
  • the above-mentioned integrated modules can be implemented in the form of hardware, and can also be implemented in the form of software function modules.
  • the integrated modules are implemented in the form of software functional modules and sold or used as independent products, they may be stored in a computer-readable storage medium.
  • the technical solutions of the present application are essentially or part of contributions to the prior art, or all or part of the technical solutions can be embodied in the form of software products, and the computer software products are stored in a storage medium , including several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present application.
  • the aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (Read-Only Memory, ROM), random access memory (Random Access Memory, RAM), magnetic disk or optical disk and other media that can store program codes .

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Abstract

本申请公开了高清视频数据的发送、接收方法及设备，该发送方法包括：发送设备通过输入接口获取不同色彩空间格式的高清视频数据；发送设备将高清视频数据处理成数据包；发送设备将数据包发送给传输速率不低于第一阈值的第一通信模块；第一通信模块用于将所述数据包进行发送。采用本申请，发送设备可通过第一通信模块及基于网线或光纤将高清视频数据传输给接收设备，可实现质量无损的高清视频超低时延传输。

Description

高清视频数据的发送、接收方法及设备 技术领域
本申请涉及通信技术领域，尤其涉及高清视频数据的发送、接收方法及设备。
背景技术
随着科技的迅猛发展，人们对视频播放时的清晰度、画质或流畅性等方面的要求越来越高，对视频传输距离要求也越来越远，但是高清视频的数据量较大，因而要求较高的传输带宽，目前，市面上可达到上述要求的产品十分稀缺，且效果不尽人意。
发明内容
基于以上存在的问题以及现有技术的缺陷，本申请提供高清视频数据的发送、接收方法及设备，发送设备可通过第一通信模块及基于网线或光纤将高清视频数据传输给接收设备，可实现质量无损的高清视频超低时延传输。
第一方面，本申请提供了高清视频数据的发送方法，该发送方法包括：
发送设备通过输入接口获取不同色彩空间格式的高清视频数据；
所述发送设备将高清视频数据处理成数据包；
所述发送设备将所述数据包发送给第一通信模块；所述第一通信模块的传输速率不低于第一阈值；所述第一通信模块用于将所述数据包进行发送。
第二方面，本申请提供了高清视频数据的接收方法，该接收方法包括：
接收设备通过第二通信模块获取数据包；所述第二通信模块的传输速率不低于第二阈值；
所述接收设备将所述数据包进行处理，获得高清视频数据。
第三方面，本申请提供了一种设备，包括：存储器及与所述存储器相连的处理器，所述存储器用于存储应用程序代码，所述处理器被配置用于调用所述应用程序代码，执行第一方面所述的高清视频数据的发送方法。
第四方面，本申请提供了一种设备，包括：存储器及与所述存储器相连的处理器，所述存储器用于存储应用程序代码，所述处理器被配置用于调用所述应用程序代码，执行第二方面所述的高清视频数据的接收方法。
本申请提供了一种高清视频数据的发送、接收方法及设备。其中，发送方法包括：发送设备通过输入接口获取不同色彩空间格式的高清视频数据，将高清视频数据处理成数据包，将所述数据包发送给第一通信模块通过第一通信模块用于将数据包发送给接收设备。采用本申请，发送设备可通过第一通信模块及基于网线或光纤将高清视频数据传输给接收设备，可实现质量无损的高清视频超低时延传输。
附图说明
为了更清楚地说明本申请实施例技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本申请提供的一种高清视频数据的发送方法的示意流程图；
图2-4是本申请提供的高清视频数据的传输场景示意图；
图5是本申请提供的一种高清视频数据的接收方法的示意流程图；
图6-9是本申请提供的高清视频数据的发送设备的结构示意图；
图10-13是本申请提供的高清视频数据的接收设备的结构示意图。
具体实施方式
下面将结合本申请中的附图，对本申请中的技术方案进行清楚、完整地描述，所描述的实施例是本申请一部分实施例，而不是全部的实施例。
参见图1，是本申请提供的一种高清视频数据发送方法的流程示意图，如图1所示，该发送方法可包括但不限于以下几个步骤：
S101、发送设备通过输入接口获取不同色彩空间格式的高清视频数据。
本申请实施例中，发送设备通过输入接口获取不同色彩空间格式的高清视频数据，可包括但不限于下述方式：
方式1：发送设备基于HDMI(High Definition Multimedia Interface，高清多媒体接口)协议接收不同色彩空间格式的高清视频数据；具体的，
发送设备可通过HDMI协议从视频源设备(如：DVD、机顶盒、摄像头等)接收不同色彩空间格式的高清视频数据。应当说明的，本申请实施例中的高清视频数据为源数据或raw data。
高清视频数据可包括但不限于：如文字、数据、声音、图形、图像或视频(如1080P、4K或8K分辨率、帧率为30FPS、60FPS、100FPS或120FPS的高清视频)等多媒体数据等。高清视频数据还可包括但不限于下述特点：高动态范围HDR(High Dynamic Range Imaging)，不同色彩空间格式可为4：2：2的YUV方式、4：2：0的YUV方式、4：4：4的YUV方式或8bit深度的RGB方式。
方式2：发送设备通过Type-C协议接收不同色彩空间格式的高清视频数据；
方式3：发送设备通过USB(Universal Serial Bus)协议接收不同色彩空间格式的高清视频数据；
方式4：发送设备通过VGA(Video Graphics Array，视频图形阵列)协议接收不同色彩空间格式的高清视频数据；
方式5：发送设备通过DP(DisplayPort)协议接收不同色彩空间格式的高清视频数据；
方式6：发送设备通过MIPI(Mobile Industry Processor Interface)协议接收不同色彩空间格式的高清视频数据；
方式7：发送设备通过LVDS(Low-Voltage Differential Signaling，低电压差分信号)协议接收获取不同色彩空间格式的高清视频数据。
方式8：发送设备通过TTL(Transistor Transistor Logic)协议接收获取不同色彩空间格式的高清视频数据。
方式9：发送设备通过DVI(Digital Visual Interface)协议接收获取不同色彩空间格式的高清视频数据。
S102、发送设备将高清视频数据处理成数据包。
本申请实施例中，发送设备将高清视频数据处理成数据包，可包括下述方式：
途径1：其中，发送设备还包括：转换芯片；转换芯片与第一集成电路分别独立集成在发送设备；具体的，
发送设备基于第一接口协议将高清视频数据传输到FPGA芯片中的转换芯片，对由转换芯片基于第二接口协议所传输的高清视频数据，通过FPGA芯片基于UDP(User Datagram  Protocol，用户数据报协议)通信协议进行封装，获得UDP数据包；
其中，第一接口协议包括：HDMI协议、DVI协议、Type-C协议、DP协议、USB协议、MIPI协议或VGA协议；第二接口协议包括：TTL协议、LVDS协议、MIPI协议或自定义接口协议；自定义接口协议可用于实现高清视频数据中音频与视频混合传输；TTL协议、LVDS协议可分别实现高清视频数据中音频与视频单独分开传输；
更具体的，发送设备基于第一接口协议将高清视频数据传输到FPGA芯片中的转换芯片，对由转换芯片基于第二接口协议所传输的高清视频数据，通过集成在发送设备中的FPGA芯片给上述高清视频数据添加UDP数据包头、UDP数据包尾，其中，UDP数据包头或UDP数据包尾可包括：目的地址、源地址、端口号、标记位等控制信息。
或者，
发送设备基于第一接口协议将高清视频数据传输到FPGA芯片中的转换芯片，对由转换芯片基于第二接口协议所传输的高清视频数据，通过FPGA芯片基于TCP(Transmission Control Protocol，传输控制协议)通信协议进行封装，获得TCP数据包；更具体的，
发送设备基于第一接口协议将高清视频数据传输到FPGA芯片中的转换芯片，对由转换芯片基于第二接口协议所传输的高清视频数据，通过集成在发送设备中的FPGA芯片给上述第一接口数据添加TCP数据包头、TCP数据包尾，其中，TCP数据包头或TCP数据包尾可包括：目的地址、源地址、端口号、标记位等控制信息。
或者，
发送设备基于第一接口协议将高清视频数据传输到FPGA芯片中的转换芯片，对由转换芯片基于第二接口协议所传输的高清视频数据，通过FPGA芯片基于第二自定义通信协议进行封装，获得自定义数据包；；更具体的，
发送设备基于第一接口协议将高清视频数据传输到FPGA芯片中的转换芯片，对由转换芯片基于第二接口协议所传输的高清视频数据，通过集成在发送设备中的FPGA芯片给上述第一接口数据添加自定义数据包头、自定义数据包尾，其中，自定义数据包头或自定义数据包尾可包括：目的地址、源地址、端口号、标记位等控制信息。
或者，
当第一集成电路为ASIC芯片时，
发送设备基于第一接口协议将高清视频数据传输到ASIC芯片中的转换芯片，对由转换芯片基于第二接口协议所传输的高清视频数据，通过ASIC芯片基于UDP(User Datagram Protocol，用户数据报协议)通信协议进行封装，获得UDP数据包；或者，
发送设备基于第一接口协议将高清视频数据传输到ASIC芯片中的转换芯片，对由转换芯片基于第二接口协议所传输的高清视频数据，通过FPGA芯片基于TCP(Transmission Control Protocol，传输控制协议)通信协议进行封装，获得TCP数据包；或者，
发送设备基于第一接口协议将高清视频数据传输到FPGA芯片中的转换芯片，对由转换芯片基于第二接口协议所传输的高清视频数据，通过FPGA芯片基于第二自定义通信协议进行封装，获得自定义数据包；。
通信协议可包括但不限于：UDP通信协议、TCP通信协议或自定义通信协议。
途径2：转换芯片集成在第一集成电路的内部；具体的，
当第一集成电路为FPGA芯片时，
发送设备基于第一接口协议将高清视频数据传输到FPGA芯片中的转换芯片，对由转换芯片基于第二接口协议所传输的高清视频数据，通过FPGA芯片基于UDP通信协议进行封装， 获得UDP数据包；
或者，
发送设备基于第一接口协议将高清视频数据传输到FPGA芯片中的转换芯片，对由转换芯片基于第二接口协议所传输的高清视频数据，通过FPGA芯片基于TCP通信协议进行封装，获得TCP数据包；
或者，
发送设备基于第一接口协议将高清视频数据传输到FPGA芯片中的转换芯片，对由转换芯片基于第二接口协议所传输的高清视频数据，通过FPGA芯片基于自定义通信协议进行封装，获得自定义数据包；
或者，
当第一集成电路为ASIC芯片时，
发送设备基于第一接口协议将高清视频数据传输到ASIC芯片中的转换芯片，对由转换芯片基于第二接口协议所传输的高清视频数据，通过ASIC芯片基于UDP通信协议进行封装，获得UDP数据包；或者，
发送设备基于第一接口协议将高清视频数据传输到ASIC芯片中的转换芯片，对由转换芯片基于第二接口协议所传输的高清视频数据，通过ASIC芯片基于TCP通信协议进行封装，获得TCP数据包；或者，
发送设备基于第一接口协议将高清视频数据传输到ASIC芯片中的转换芯片，对由转换芯片基于第二接口协议所传输的高清视频数据，通过ASIC芯片基于自定义通信协议进行封装，获得自定义数据包；
途径3：发送设备通过集成在发送设备中的FPGA芯片基于UDP通信协议将高清视频数据封装成UDP数据包；更具体的，
发送设备通过集成在发送设备中的FPGA芯片给上述高清视频数据添加UDP数据包头、UDP数据包尾，其中，UDP数据包头或UDP数据包尾可包括：目的地址、源地址、端口号、标记位等控制信息。
途径4：发送设备通过FPGA芯片基于TCP通信协议将高清视频数据封装成TCP数据包；
发送设备通过集成在发送设备中的FPGA芯片给上述高清视频数据添加TCP数据包头、TCP数据包尾，其中，TCP数据包头或TCP数据包尾可包括：目的地址、源地址、端口号、标记位等控制信息。
途径5：发送设备通过FPGA芯片基于自定义通信协议将高清视频数据封装成自定义数据包。更具体的，
发送设备通过集成在发送设备中的FPGA芯片给上述高清视频数据添加自定义数据包头、自定义数据包尾，其中，自定义数据包头或自定义数据包尾可包括：目的地址、源地址、端口号、标记位等控制信息。
途径6：发送设备通过集成在发送设备中的ASIC芯片基于UDP通信协议将高清视频数据封装成UDP数据包。
途径7：发送设备通过ASIC芯片基于TCP通信协议将高清视频数据封装成TCP数据包。
途径8：发送设备通过ASIC芯片基于自定义通信协议将高清视频数据封装成自定义数据包。
途径9：发送设备包括：第一集成电路；
当第一集成电路为FPGA芯片时，
发送设备通过FPGA芯片基于无失真编码算法将高清视频数据通过进行压缩，获得第一数据，将第一数据通过通信协议进行封装，获得数据包；
当第一集成电路为ASIC芯片时，
发送设备通过ASIC芯片基于无失真编码算法将高清视频数据通过进行压缩，获得第一数据，将第一数据通过通信协议进行封装，获得数据包；
通信协议包括：UDP通信协议、TCP通信协议或第二自定义通信协议；
无失真编码算法，可包括但不限于：
游程编码算法、哈夫曼编码算法、二值图像的常数块编码算法、四叉树编码算法、小波变换编码算法或自定义算术编码算法。
以自定义算术编码算法为例，第一集成电路，可基于自定义算术编码算法，将高清视频数据中的冗余数据进行压缩，获得第一数据，将第一数据通过通信协议进行封装，获得数据包。
举例来说，当高清视频数据为占用6个字节的0时，即000000000000时，第一集成电路基于自定义算术编码算法，将高清视频数据中的冗余数据进行压缩后，可得到只需要占用2个字节的第一数据(0600)，实现了对高清视频数据中冗余数据的压缩。
S103、发送设备将数据包发送给第一通信模块。
本申请实施例中，第一通信模块的传输速率不低于第一阈值；第一阈值可包括但不限于：1Gbps、2.5Gbps、5Gbps、10Gbps或25Gbps。
应当说明的，发送设备将数据包发送给第一通信模块，可包括但不限于下述方式：
方式1：
第一通信模块包括：电模块；电模块包括：PHY芯片以及RJ-45接口；
发送设备将数据包通过MAC单元基于第三接口协议传输给PHY芯片(以太网物理层数据收发器)，PHY芯片用于将数据包输出给RJ-45接口，RJ-45接口用于将数据包进行发送；其中，第三接口协议包括：XFI协议、MII(Media Independent Interface)协议、GMII(Gigabit Media Independent Interface)协议、RGMII(Reduced Gigabit Media Independent Interface)协议、SGMII(Serial Gigabit Media Independent Interface)协议、Serdes协议、XAUI协议或RXAUI协议；数据包包括：UDP数据包，TCP数据包或自定义数据包。
方式2：
第一通信模块包括：光模块；
发送设备将数据包通过MAC单元基于第三接口协议传输给光模块；光模块用于将数据包转换为光信号，并将光信号基于光纤进行发送上述光模块可包括但不限于：单纤双向光模块(具体可包括：用于长距离传输的单模光模块以及用于短距离传输的多模光模块)。
应当说明的，当第一通信模块为电模块时，
发送设备将数据包发送给第一通信模块之后，还可执行下述过程：
发送设备通过PHY芯片将数据包经过调制后输出给RJ-45接口，通过RJ-45接口发送给接收设备；或者，
发送设备通过PHY芯片将数据包经过调制后输出给RJ-45接口，通过RJ-45接口发送给交换机，交换机用于将数据包转发给接收设备；
其中，数据包包括：UDP数据包，TCP数据包或自定义数据包。
图2示例性示出了一种高清视频数据的传输场景示意图。如图2所示，在该场景中，发 送设备通过第一通信模块将上述数据包基于网线或光纤，传输到接收设备。
图3示例性示出了一种高清视频数据的传输的场景图。如图3所示，在该场景中，发送设备通过第一通信模块将上述数据包基于网线或光纤，传输到交换机，在利用交换机将上述数据包转发给接收设备。
应当说明的，当第一通信模块为光模块时，
发送设备将数据包发送给第一通信模块之后，还可执行下述过程：
发送设备通过光模块将数据包转换为光信号，并将光信号发送给接收设备；或者，
发送设备通过光模块将数据包转换为光信号，并将光信号发送给交换机，交换机用于将光信号转发给接收设备；
其中，数据包包括：UDP数据包，TCP数据包或自定义数据包。
应当说明的，当接收设备包括：第一接收设备以及第二接收设备；数据包包括：UDP数据包或TCP数据包时；
发送设备将所述数据包发送给第一通信模块之后，还可执行下述过程：
发送设备通过PHY芯片将UDP数据包经过调制后输出给RJ-45接口，通过RJ-45接口发送给交换机，交换机用于将UDP数据包分别转发给第一接收设备以及所述第二接收设备；或者，
发送设备通过PHY芯片将TCP数据包经过调制后输出给RJ-45接口，通过RJ-45接口发送给交换机，交换机用于将TCP数据包分别转发给第一接收设备以及所述第二接收设备。
应当说明的，当接收设备包括：第一接收设备以及第二接收设备，以及数据包包括：UDP数据包或TCP数据包时；
发送设备将数据包发送给第一通信模块之后，还可执行下述过程：
发送设备通过光模块将UDP数据包或TCP数据包转换为光信号，并将光信号发送给交换机，交换机用于将光信号转发给第一接收设备以及第二接收设备。
图4示例性示出了另一种高清视频数据的传输的场景图，如图4所示，在该场景中，接收设备包括：第一接收设备、第二接收设备；
发送设备通过第一通信模块将UDP数据包基于网线或光纤，传输到交换机，在利用交换机将上述UDP数据包转发给接收设备。
或者，
发送设备通过第一通信模块将TCP数据包基于网线或光纤，传输到交换机，在利用交换机将上述TCP数据包转发给接收设备。
参见图5，是本申请提供的一种高清视频数据接收方法的流程示意图，如图5所示，该接收方法可包括但不限于以下几个步骤：
S501、接收设备通过第二通信模块获取数据包。
本申请实施例中，第二通信模块的传输速率不低于第二阈值，其中，第二阈值可包括但不限于：1Gbps、2.5Gbps、5Gbps、10Gbps或25Gbps。
应当说明的，接收设备通过第二通信模块获取数据包，可包括但不限于下述方式：
方式1：当第二通信模块包括：电模块时，电模块包括：PHY芯片以及RJ-45接口；
接收设备通过集成在接收设备中的RJ-45接口接收由发送设备发送的或交换机转发的数据包，并传输给PHY芯片(以太网物理层数据收发器)；。具体的，
方式2：
当第二通信模块包括：光模块时；
接收设备通过集成在接收设备中的光模块将接收的由发送设备发送的或交换机转发的光信号转换成数据包。其中，上述光模块可包括但不限于：单纤双向光模块(具体可包括：用于长距离传输的单模光模块以及用于短距离传输的多模光模块)
应当说明的，接收设备可将第二通信模块所接收到的数据包输出到第二集成电路。
S502、接收设备将数据包进行处理，获得高清视频数据。
本申请实施例中，接收设备将数据包进行处理，获得高清视频数据，可包括但不限于下述方式：
方式1：
接收设备还包括：转换芯片；转换芯片与第二集成电路分别独立集成在接收设备；具体的，
当第二集成电路为FPGA芯片时，
接收设备通过FPGA芯片基于UDP通信协议将UDP数据包解封装，获得高清视频数据，通过第四接口协议将高清视频数据输出到转换芯片；所述第四接口协议包括：TTL协议、LVDS协议、MIPI协议或自定义接口协议；具体的，
发送设备通过集成在发送设备中的FPGA芯片基于UDP协议将UDP数据包去除UDP数据包头、UDP数据包尾等，获得高清视频数据，通过第四接口协议将高清视频数据输出到转换芯片。
或者，
接收设备通过FPGA芯片基于TCP通信协议将TCP数据包解封装，获得高清视频数据，通过第四接口协议将所述高清视频数据输出到所述转换芯片；具体的，
发送设备通过集成在发送设备中的FPGA芯片基于TCP协议将TCP数据包去除TCP数据包头、TCP数据包尾等，获得高清视频数据，通过第四接口协议将高清视频数据输出到转换芯片。
或者，
接收设备通过FPGA芯片基于自定义通信协议将自定义数据包解封装，获得高清视频数据，通过第四接口协议将所述高清视频数据输出到所述转换芯片；；具体的，
发送设备通过集成在发送设备中的FPGA芯片基于自定义通信协议将自定义数据包去除自定义数据包头、自定义数据包尾等，获得高清视频数据，通过第四接口协议将所述高清视频数据输出到所述转换芯片。
或者，
当第二集成电路为ASIC芯片时，
接收设备通过ASIC芯片基于UDP通信协议将UDP数据包解封装，获得高清视频数据，通过第四接口协议将所述高清视频数据输出到所述转换芯片；或者，
接收设备通过ASIC芯片基于TCP通信协议将TCP数据包解封装，获得高清视频数据，通过第四接口协议将所述高清视频数据输出到所述转换芯片；或者，
接收设备通过ASIC芯片基于自定义通信协议将自定义数据包解封装，获得高清视频数据，通过第四接口协议将所述高清视频数据输出到所述转换芯片。
方式2：
接收设备还包括：转换芯片；转换芯片集成在第二集成电路的内部；
当第二集成电路为FPGA芯片时，
接收设备通过FPGA芯片基于UDP通信协议将UDP数据包解封装，获得高清视频数据，通过第四接口协议将高清视频数据输出到所述转换芯片；或者，
接收设备通过FPGA芯片基于TCP通信协议将TCP数据包解封装，获得高清视频数据，通过第四接口协议将高清视频数据输出到所述转换芯片；或者，
接收设备通过FPGA芯片基于自定义通信协议将自定义数据包解封装，获得高清视频数据，通过第四接口协议将高清视频数据输出到所述转换芯片；或者，
当第二集成电路为ASIC芯片时，
接收设备通过ASIC芯片基于UDP通信协议将UDP数据包解封装，获得高清视频数据，通过第四接口协议将高清视频数据输出到所述转换芯片；或者，
接收设备通过ASIC芯片基于TCP通信协议将TCP数据包解封装，获得高清视频数据，通过第四接口协议将高清视频数据输出到所述转换芯片；或者，
接收设备通过ASIC芯片基于自定义通信协议将自定义数据包解封装，获得高清视频数据，通过第四接口协议将高清视频数据输出到所述转换芯片。
方式3：当接收设备包括：第二集成电路，第二集成电路为FPGA芯片时，接收设备通过集成在接收设备中的FPGA芯片基于UDP通信协议将UDP数据包进行处理，获得高清视频数据；更具体的，
发送设备通过集成在发送设备中的FPGA芯片基于UDP协议将UDP数据包去除UDP数据包头、UDP数据包尾等，获得高清视频数据。
方式4：当接收设备包括：第二集成电路，第二集成电路为FPGA芯片时，接收设备通过FPGA芯片基于TCP通信协议将TCP数据包解封装，获得高清视频数据；具体的，
发送设备通过集成在发送设备中的FPGA芯片基于TCP协议将TCP数据包去除TCP数据包头、TCP数据包尾等，获得高清视频数据。
方式5：当接收设备包括：第二集成电路，第二集成电路为FPGA芯片时，接收设备通过FPGA芯片基于自定义通信协议将自定义数据包解封装，获得高清视频数据；具体的，
发送设备通过集成在发送设备中的FPGA芯片基于自定义通信协议将自定义数据包去除自定义数据包头、自定义数据包尾等，获得高清视频数据。
方式6：当接收设备包括：第二集成电路，第二集成电路为ASIC芯片时，接收设备通过集成在接收设备中的ASIC芯片基于UDP通信协议将UDP数据包解封装，获得高清视频数据；
方式7：当接收设备包括：第二集成电路，第二集成电路为ASIC芯片时，接收设备通过ASIC芯片基于TCP通信协议将TCP数据包解封装，获得高清视频数据；
方式8：当接收设备包括：第二集成电路，第二集成电路为ASIC芯片时，接收设备通过ASIC芯片基于自定义通信协议将自定义数据包解封装，获得高清视频数据。
方式9：接收设备包括：第二集成电路；当第二集成电路为FPGA芯片时，
接收设备通过FPGA芯片基于通信协议将数据包解封装，获得第一数据，基于无失真解码算法将第一数据解压缩，获得高清视频数据；其中，
通信协议包括：UDP通信协议、TCP通信协议或自定义通信协议；
无失真解码算法，包括：游程解码算法、哈夫曼解码算法、二值图像的常数块解码算法、四叉树解码算法、小波变换解码算法或自定义算术解码算法。
应当说明的，接收设备可基于自定义算术解码算法将第一数据进行内插，恢复出高清视频数据。
应当说明的，接收设备通过第二集成电路将数据包进行处理，获得高清视频数据之后，还可执行下述过程：
接收设备将高清视频数据通过第五接口协议输出给显示设备；第五接口协议包括：HDMI协议、DVI协议、Type-C协议、DP协议、USB协议、MIPI协议或VGA协议。
本申请提供了一种发送设备，如图6所示，可用于实现图1方法实施例所述的高清视频数据的发送方法。具体的，
发送设备60，可包括但不限于：输入接口601、第一集成电路602、第一通信模块603之外，还可包括转换芯片，应当说明的，所述转换芯片与所述第一集成电路602分别独立集成在所述发送设备；其中，
输入接口601，用于接收不同色彩空间格式的高清视频数据；
转换芯片，用于通过与所述输入接口601耦合的接口接收到高清视频数据之后，通过转换芯片的第一通信时序接口将高清视频数据输出给第一集成电路；
其中，第一通信时序接口，包括：LVDS(Low-Voltage Differential Signaling，低电压差分信号)接口、TTL(Transistor Transistor Logic)接口、MIPI接口或自定义接口。
应当说明的，LVDS接口或TTL接口可分别为用于高清视频数据中音频与视频单独分开传输的接口；自定义接口为用于高清视频数据中音频与视频混合传输的接口。
第一集成电路602，可用于将高清视频数据基于通信协议处理为数据包；
第一通信模块603，用于将数据包进行发送。
应当说明的，本申请实施例中的不同色彩空间格式的高清视频数据为源数据或raw data。
应当说明的，上述不同色彩空间格式的高清视频数据可包括但不限于：如文字、数据、声音、图形、图像或视频(如1080P、4K或8K分辨率、帧率为30FPS、60FPS、100FPS或120FPS的高清视频)等多媒体数据等。高清视频数据还可包括但不限于下述特点：高动态范围HDR(High Dynamic Range Imaging)，不同色彩空间格式可为4：2：2的YUV方式、4：2：0的YUV方式、4：4：4的YUV方式或8bit深度的RGB方式。
应当说明的，输入接口101，可包括但不限于：
HDMI(High Definition Multimedia Interface，高清多媒体接口)接口、Type-C接口、DVI接口、DP接口、USB接口、VGA接口、LVDS接口、TTL接口或MIPI接口。
上述通信协议包括：UDP通信协议、TCP通信协议或自定义通信协议；第一集成电路602，可包括但不限于：FPGA芯片或ASIC芯片。
第一集成电路602，具体可用于：
将高清视频数据基于UDP通信协议封装为UDP数据包；或者
将高清视频数据基于TCP通信协议封装为TCP数据包；或者
将高清视频数据基于自定义通信协议封装为自定义数据包。
应当说明的，第一通信模块603的传输速率不低于第一阈值；
应当说明的，第一集成电路602，具体还可用于：
基于无失真编码算法将高清视频数据通过进行压缩，获得第一数据，将第一数据通过通信协议进行封装，获得数据包。
无失真编码算法，包括：
游程编码算法、哈夫曼编码算法、二值图像的常数块编码算法、四叉树编码算法、小波变换编码算法或自定义算术编码算法。
以自定义算术编码算法为例，第一集成电路602，可基于自定义算术编码算法，将高清视频数据中的冗余数据进行压缩，获得第一数据，将第一数据通过通信协议进行封装，获得数据包。
举例来说，当高清视频数据为占用6个字节的0时，即000000000000时，第一集成电路602基于自定义算术编码算法，将高清视频数据中的冗余数据进行压缩后，可得到只需要占用2个字节的第一数据(0600)，实现了对高清视频数据中冗余数据的压缩。第一通信模块603，可包括但不限于：电模块或光模块，其中，电模块包括：PHY芯片以及RJ-45接口，光模块的传输速率不低于第一阈值；电模块的传输速率不低于第一阈值；第一阈值可包括但不限于：1Gbps、2.5Gbps、5Gbps、10Gbps或25Gbps。
当第一通信模块603为电模块时，电模块的传输速率不低于第一阈值；电模块用于：
在第一集成电路602将数据包输出给集成在第一集成电路602中的MAC单元，通过MAC单元的第二通信时序接口将数据包输出给PHY芯片之后，通过PHY芯片将数据包输出给RJ-45接口，通过RJ-45接口发送给接收设备，或者，
通过PHY芯片将数据包输出给RJ-45接口，通过RJ-45接口发送给交换机，交换机用于将数据包转发给所述接收设备；或者，
当第一通信模块603为光模块时，光模块的传输速率不低于所述第一阈值；
光模块用于：
在第一集成电路602将数据包输出给集成在第一集成电路602中的MAC单元，通过MAC单元的第二通信时序接口将数据包输出给光模块之后，
将数据包转换为光信号，并将光信号发送给接收设备，或者，
将数据包转换为光信号，并将光信号发送给交换机，交换机用于将光信号转发给接收设备；
其中，第二通信时序接口，包括：XFI接口、GMII接口、SMII接口、RGMII接口、XGMII接口、Serdes接口、XAUI接口或RXAUI接口；数据包包括：UDP数据包，TCP数据包或自定义数据包。
发送设备60，还可用于：
在发送设备60将数据包发送给第一通信模块603之后，通过第一通信模块将数据包输出接收设备；或者，
在发送设备60将数据包发送给第一通信模块603之后，通过第一通信模块将数据包输出交换机，交换机可用于将该数据包转发给接收设备。
应当理解，发送设备60仅为本申请实施例提供的一个例子，发送设备60可具有比示出的部件更多或更少的部件，可以组合两个或更多个部件，或者可具有部件的不同配置实现。
可理解的，关于图6的发送设备60包括的功能部件的具体实现方式，可参考图1实施例，此处不再赘述。
本申请提供了另一种发送设备，如图7所示，可用于实现图1方法实施例所述的高清视频数据的发送方法。具体的，
发送设备70，可包括但不限于：输入接口701、第一集成电路702以及第一通信模块703之外，还可包括：转换芯片，其中，所述转换芯片集成在所述第一集成电路702的内部；
输入接口701，用于接收高清视频数据；
第一集成电路702，可用于将高清视频数据处理成数据包；
第一集成电路702，具体可用于：
在通过转换芯片的第一通信时序接口将高清视频数据输出给第一集成电路之后，，将高清视频数据基于UDP通信协议封装为UDP数据包；或者，
在通过转换芯片的第一通信时序接口将高清视频数据输出给第一集成电路之后，，将高清视频数据基于TCP通信协议封装为TCP数据包；或者，
在通过转换芯片的第一通信时序接口将高清视频数据输出给第一集成电路之后，将高清视频数据基于自定义通信协议封装为自定义数据包。
应当说明的，第一集成电路702，具体还可用于：
在通过转换芯片的第一通信时序接口将高清视频数据输出给第一集成电路之后，基于无失真编码算法将高清视频数据通过进行压缩，获得第一数据，将第一数据通过上述通信协议(如：UDP通信协议、TCP通信协议或自定义通信协议)进行封装，获得数据包。
无失真编码算法，包括：
游程编码算法、哈夫曼编码算法、二值图像的常数块编码算法、四叉树编码算法、小波变换编码算法或自定义算术编码算法。
第一通信模块703，用于将数据包进行发送。
应当理解，发送设备70仅为本申请实施例提供的一个例子，发送设备70可具有比示出的部件更多或更少的部件，可以组合两个或更多个部件，或者可具有部件的不同配置实现。
可理解的，关于图7的发送设备70包括的功能部件的具体实现方式、未阐明的定义或说明，可参考图1实施例以及图6实施例，此处不再赘述。
本申请提供了又一种发送设备，如图8所示，可用于实现图1方法实施例所述的高清视频数据的发送方法。具体的，
发送设备80，可包括但不限于：输入接口801、第一集成电路802，第一通信模块803，以及转换芯片，其中，转换芯片及第一通信模块803集成在第一集成电路802的内部。
输入接口801，用于接收高清视频数据；
转换芯片，用于通过转换芯片的第一通信时序接口将高清视频数据输出给第一集成电路802；
第一集成电路802，用于将第一集成电路802中转换芯片的第一通信时序接口输出的高清视频数据进行处理，获得数据包；
第一通信模块803，用于将数据包进行发送。
可理解的，关于图8的发送设备80包括的功能部件的具体实现方式、未阐明的定义或说明，可参考图1实施例以及图6实施例，此处不再赘述。
本申请提供了又一种发送设备，如图9所示，可用于实现图1方法实施例所述的高清视频数据的发送方法。具体的，
发送设备90，可包括但不限于：输入接口901、第一集成电路902以及第一通信模块903，其中，输入接口901、第一集成电路902以及第一通信模块903依次连接。
输入接口901，用于接收不同色彩空间格式的高清视频数据；
第一集成电路902，用于基于通信协议将高清视频数据处理成数据包；
第一通信模块903，用于将数据包进行发送。
应当说明的，高清视频数据可包括但不限于：如文字、数据、声音、图形、图像或视频(如1080P、4K或8K分辨率、帧率为30FPS、60FPS、100FPS或120FPS的高清视频)等感觉 多媒体数据等。所述高清视频数据还可包括但不限于下述特点：高动态范围HDR(High Dynamic Range Imaging)，数据格式为4：2：2的YUV方式、4：2：0的YUV方式或8bit深度的RGB方式。
上述通信协议包括：UDP通信协议、TCP通信协议或自定义通信协议；
应当说明的，输入接口901，可包括但不限于：
HDMI接口、Type-C接口、DP接口、USB接口、VGA接口、DVI接口或MIPI接口。
应当说明的，第一集成电路902，可包括但不限于：FPGA芯片或ASIC芯片。
第一集成电路902，具体可用于：
基于UDP通信协议将高清视频数据封装成UDP数据包；或者，
基于TCP通信协议将高清视频数据封装成TCP数据包；或者，
基于自定义通信协议将高清视频数据封装成自定义数据包。
应当说明的，第一集成电路902，具体还可用于：
基于无失真编码算法将高清视频数据通过进行压缩，获得第一数据，将第一数据通过上述通信协议(如：UDP通信协议、TCP通信协议或自定义通信协议)进行封装，获得数据包。
第一通信模块903，可包括但不限于：电模块或光模块，其中，电模块包括：PHY芯片以及RJ-45接口，光模块的传输速率不低于第一阈值；电模块的传输速率不低于第一阈值；第一阈值可包括但不限于：1Gbps、2.5Gbps、5Gbps、10Gbps或25Gbps。
发送设备90，还可用于：
在发送设备90将数据包发送给传输速率不低于第一阈值的第一通信模块903之后，通过第一通信模块将数据包输出接收设备；或者，
在发送设备90将数据包发送给传输速率不低于第一阈值的第一通信模块903之后，通过第一通信模块将数据包输出交换机，交换机可用于将该数据包转发给接收设备。
应当理解，发送设备90仅为本申请实施例提供的一个例子，发送设备80可具有比示出的部件更多或更少的部件，可以组合两个或更多个部件，或者可具有部件的不同配置实现。
可理解的，关于图9的发送设备90包括的功能部件的具体实现方式、未阐明的定义或说明，可参考图1实施例，此处不再赘述。
本申请提供了一种接收设备，如图10所示，可用于实现图5方法实施例所述的高清视频数据的接收方法。具体的，
接收设备100，可包括但不限于：第二通信模块1001、第二集成电路1002以及输出接口1003之外，还可包括：转换芯片，应当说明的，转换芯片与第二集成电路1002分别独立集成在发送设备；其中，
第二通信模块1001，可用于：从发送设备获取数据包，或者，从交换机获取数据包；
第二集成电路1002，可用于：将所述数据包进行处理，获得高清视频数据；其中，第二集成电路1002，可包括但不限于：FPGA芯片或ASIC芯片。
转换芯片用于通过转换芯片的第三通信时序接口将高清视频数据输出到输出接口1003。其中，第三通信时序接口可包括但不限于：HDMI接口、DVI接口、Type-C接口、DP接口、USB接口、VGA接口或MIPI接口。
当第二通信模块1001为电模块时，电模块包括：PHY芯片以及RJ-45接口；
电模块可用于：
通过RJ-45接口接收由发送设备发送的数据包，通过PHY芯片以及第二集成电路1002 中MAC单元的第四通信时序接口将数据包输出到第二集成电路1002，第四通信时序接口，包括：XFI接口、GMII接口、SMII接口、RGMII接口、XGMII接口、Serdes接口、XAUI接口或RXAUI接口；或者，
通过RJ-45接口接收由交换机转发的数据包，通过PHY芯片以及第二集成电路1002中MAC单元的第四通信时序接口将所述UDP数据包输出到第二集成电路1002，或者，
第二通信模块1001为光模块；光模块的传输速率不低于第二阈值；
光模块，可用于：
接收由发送设备发送的光信号，并将光信号转换为数据包，通过第二集成电路1002中MAC单元的第四通信时序接口将数据包输出到第二集成电路1002，或者，
接收由交换机转发的光信号，并将光信号转换为数据包，通过第二集成电路1002中MAC单元的第四通信时序接口将数据包输出到第二集成电路1002。
其中，数据包包括：UDP数据包、TCP数据包或自定义数据包。第二集成电路1002，具体可用于：
当数据包为UDP数据包时，将UDP数据包基于UDP通信协议解封装为高清视频数据；或者，
当数据包为TCP数据包时，将TCP数据包基于TCP通信协议解封装为高清视频数据；或者，
当数据包为自定义数据包时，将自定义数据包基于自定义通信协议解封装为高清视频数据。
第二集成电路1002，还可用于：
基于通信协议(如：UDP通信协议、TCP通信协议或自定义通信协议)将数据包解封装，获得第一数据，基于无失真解码算法将第一数据解压缩，获得高清视频数据；
更具体的，
当数据包为UDP数据包时，将UDP数据包基于UDP通信协议解封装，获得第一数据，基于无失真解码算法将第一数据解压缩，获得高清视频数据；
或者，
当数据包为TCP数据包时，将TCP数据包基于TCP通信协议解封装，获得第一数据，基于无失真解码算法将第一数据解压缩，获得高清视频数据；
或者，
当数据包为自定义数据包时，将自定义数据包基于自定义通信协议解封装，获得第一数据，基于无失真解码算法将第一数据解压缩，获得高清视频数据。
无失真解码算法，包括：
游程解码算法、哈夫曼解码算法、二值图像的常数块解码算法、四叉树解码算法、小波变换解码算法或自定义算术解码算法。
第二集成电路1002，具体可用于：基于自定义算术解码算法将第一数据进行内插，恢复出高清视频数据。
输出接口1003，可用于：将上述高清视频数据输出到与接收设备100相连接的输出设备(如：显示设备)
应当说明的，第二通信模块1001，可包括但不限于：电模块或光模块；光模块的传输速率不低于第二阈值；电模块的传输速率不低于第二阈值；第二阈值可包括但不限于：1Gbps、2.5Gbps、5Gbps、10Gbps或25Gbps。
应当理解，接收设备100仅为本申请实施例提供的一个例子，接收设备100可具有比示出的部件更多或更少的部件，可以组合两个或更多个部件，或者可具有部件的不同配置实现。
可理解的，关于图10的接收设备100包括的功能部件的具体实现方式、未阐明的定义或说明，可参考图5实施例，此处不再赘述。
本申请提供了又一种接收设备，如图11所示，可用于实现图5方法实施例所述的高清视频数据的接收方法。
接收设备110，可包括但不限于：第二通信模块1101、第二集成电路1102以及输出接口1103之外，还包括：转换芯片，所述转换芯片集成在所述第二集成电路1102的内部；
第二通信模块1101，可用于：从发送设备获取数据包，或者，从交换机获取数据包；
第二集成电路1102，具体可用于：
基于UDP通信协议将UDP数据包解封装为高清视频数据，通过转换芯片将高清视频数据通过转换芯片的第三通信时序接口将高清视频数据输出到输出接口203；第三通信时序接口包括：HDMI接口、Type-C接口、DVI接口、DP接口、USB接口、VGA接口或MIPI接口；或者，
基于TCP通信协议将TCP数据包解封装为高清视频数据，通过转换芯片的第三通信时序接口将高清视频数据输出到输出接口203；或者，
基于自定义通信协议将自定义数据包解封装为高清视频数据，通过转换芯片的第三通信时序接口将高清视频数据输出到输出接口203。
输出接口1103，可用于：将高清视频数据输出到显示设备(如：显示器)。
应当理解，接收设备110仅为本申请实施例提供的一个例子，接收设备100可具有比示出的部件更多或更少的部件，可以组合两个或更多个部件，或者可具有部件的不同配置实现。
可理解的，关于图11的接收设备110包括的功能部件的具体实现方式、未阐明的定义或说明，可参考图5实施例，此处不再赘述。
本申请提供了又一种接收设备，如图12所示，可用于实现图5方法实施例所述的高清视频数据的接收方法。
接收设备120，可包括但不限于：第二通信模块1201、第二集成电路1202以及输出接口1203之外，还包括：转换芯片，第二通信模块1201以及转换芯片都集成在第二集成电路1202的内部；
第二通信模块1201，可用于：从发送设备获取数据包，或者，从交换机获取数据包；
第二集成电路1202，可用于：通过第二集成电路1202中MAC单元的第四通信时序接口将输入到第二集成电路1202的数据包进行处理，获得高清视频数据，通过转换芯片的第三通信时序接口将高清视频数据输出到输出接口1203；
应当说明的，第二集成电路1202，可包括但不限于：FPGA芯片或ASIC芯片。
应当说明的，第二通信模块1201，可包括但不限于：电模块或光模块；光模块的传输速率不低于第二阈值；电模块的传输速率不低于第二阈值；第二阈值可包括但不限于：1Gbps、2.5Gbps、5Gbps、10Gbps或25Gbps。
本申请提供了又一种接收设备，如图13所示，可用于实现图5方法实施例所述的高清视频数据的接收方法。
接收设备130，可包括但不限于：第二通信模块1301、第二集成电路1302以及输出接口1303，其中，第二通信模块1301、第二集成电路1302以及输出接口1303依次连接。
第二通信模块1301，可用于：从发送设备获取数据包，或者，从交换机获取数据包；
第二集成电路1302，可用于：将上述数据包基于通信协议进行处理，获得高清视频数据。
输出接口1303，可用于：将高清视频数据输出到输出设备(如：显示设备)。
第二集成电路1302，具体可用于：
当所述数据包为UDP数据包时，基于UDP通信协议将UDP数据包解封装，获得高清视频数据；或者，
当所述数据包为TCP数据包时，基于TCP通信协议将TCP数据包解封装，获得所述高清视频数据；或者，
当数据包为自定义数据包时，基于自定义通信协议将自定义数据包解封装，获得高清视频数据。
第二集成电路1302，具体还可用于：
当数据包为UDP数据包时，将UDP数据包基于UDP通信协议解封装，获得第一数据，基于无失真解码算法将第一数据解压缩，获得高清视频数据；
或者，
当数据包为TCP数据包时，将TCP数据包基于TCP通信协议解封装，获得第一数据，基于无失真解码算法将第一数据解压缩，获得高清视频数据；
或者，
当数据包为自定义数据包时，将自定义数据包基于自定义通信协议解封装，获得第一数据，基于无失真解码算法将第一数据解压缩，获得高清视频数据。
无失真解码算法，包括：
游程解码算法、哈夫曼解码算法、二值图像的常数块解码算法、四叉树解码算法或小波变换解码算法。
上述通信协议包括：UDP通信协议、TCP通信协议或自定义通信协议；
应当说明的，输出接口1303，可包括但不限于：
HDMI接口、DVI接口、Type-C接口、DP接口、USB接口、VGA接口或MIPI接口。
应当说明的，第二集成电路1302，可包括但不限于：FPGA芯片或ASIC芯片。
应当说明的，第二通信模块1301的传输速率不低于第二阈值；
第二通信模块1301，可包括但不限于：电模块或光模块；光模块的传输速率不低于第二阈值；电模块的传输速率不低于第二阈值；其中，第二阈值可包括但不限于：1Gbps、2.5Gbps、5Gbps、10Gbps或25Gbps。
应当理解，接收设备110仅为本申请实施例提供的一个例子，接收设备110可具有比示出的部件更多或更少的部件，可以组合两个或更多个部件，或者可具有部件的不同配置实现。
可理解的，关于图13的接收设备130包括的功能部件的具体实现方式、未阐明的定义或说明，可参考图5实施例，此处不再赘述。
本领域普通技术人员可以意识到，结合本申请中所公开的实施例描述的各示例的模块及算法步骤，能够以电子硬件、计算机软件或者二者的结合来实现，为了清楚地说明硬件和软件的可互换性，在上述说明中已经按照功能一般性地描述了各示例的组成及步骤。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人 员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本申请的范围。
所属领域的技术人员可以清楚地了解到，为了描述的方便和简洁，上述描述的设备、装置和模块的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
在本申请所提供的几个实施例中，应该理解到，所揭露的设备、装置和方法，可以通过其它的方式实现。例如，以描述了各示例的组成及步骤。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本申请的范围。
上述描述的装置、设备的实施例仅仅是示意性的，例如，所述模块的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个模块或组件可以结合或者可以集成到另一个装置，或一些特征可以忽略，或不执行。另外，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口、设备、装置或模块的间接耦合或通信连接，也可以是电的，机械的或其它的形式连接。
所述作为分离部件说明的模块可以是或者也可以不是物理上分开的，作为模块显示的部件可以是或者也可以不是物理模块，即可以位于一个地方，或者也可以分布到多个网络模块上。可以根据实际的需要选择其中的部分或者全部模块来实现本申请实施例方案的目的。
另外，在本申请各个实施例中的各功能模块可以集成在一个处理模块中，也可以是各个模块单独物理存在，也可以是两个或两个以上模块集成在一个模块中。上述集成的模块既可以采用硬件的形式实现，也可以采用软件功能模块的形式实现。
所述集成的模块如果以软件功能模块的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本申请的技术方案本质上或者说对现有技术做出贡献的部分，或者该技术方案的全部或部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本申请各个实施例所述方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器(Read-Only Memory，ROM)、随机存取存储器(Random Access Memory，RAM)、磁碟或者光盘等各种可以存储程序代码的介质。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到各种等效的修改或替换，这些修改或替换都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以权利要求的保护范围为准。

Claims (23)

  1. 一种高清视频数据的发送方法，其特征在于，包括：
    发送设备获取不同色彩空间格式的高清视频数据；
    所述发送设备将所述高清视频数据处理成数据包；
    所述发送设备将所述数据包发送给第一通信模块；所述第一通信模块的传输速率不低于第一阈值；所述第一通信模块用于将所述数据包进行发送。
  2. 如权利要求1所述的高清视频数据的发送方法，其特征在于，
    发送设备获取不同色彩空间格式的高清视频数据，包括：
    所述发送设备基于第一接口协议接收不同色彩空间格式的高清视频数据；
    所述第一接口协议，包括：HDMI协议、Type-C协议、DP协议、USB协议、MIPI协议、DVI协议或VGA协议。
  3. 如权利要求1所述的高清视频数据的发送方法，其特征在于，
    所述发送设备包括：转换芯片以及第一集成电路；所述转换芯片与所述第一集成电路分别独立集成在所述发送设备；
    当所述第一集成电路为FPGA芯片时，
    所述发送设备将所述高清视频数据处理成数据包，包括：
    所述发送设备基于所述第一接口协议将所述高清视频数据传输到所述转换芯片，并将所述转换芯片获得的所述高清视频数据基于第二接口协议传输给FPGA芯片，通过所述FPGA芯片基于通信协议将所述高清视频数据进行封装，获得数据包；
    当所述第一集成电路为ASIC芯片时，
    所述发送设备将所述高清视频数据处理成数据包，包括：
    所述发送设备基于所述第一接口协议将所述高清视频数据传输到所述转换芯片，并将所述转换芯片获得的所述高清视频数据基于第二接口协议传输给FPGA芯片，通过所述FPGA芯片基于通信协议将所述高清视频数据进行封装，获得数据包；
    其中，所述第一接口协议包括：HDMI协议、Type-C协议、DP协议、USB协议、MIPI协议、DVI协议或VGA协议；所述第二接口协议包括：TTL协议、LVDS协议、所述MIPI协议或自定义接口协议；所述通信协议包括：UDP通信协议、TCP通信协议或自定义通信协议。
  4. 如权利要求1所述的高清视频数据的发送方法，其特征在于，
    所述发送设备包括：转换芯片以及第一集成电路；所述转换芯片集成在所述第一集成电路的内部；
    当所述第一集成电路为FPGA芯片时，
    所述发送设备将所述高清视频数据处理成数据包，包括：
    所述发送设备基于所述第一接口协议将所述高清视频数据传输到所述FPGA芯片中的所述转换芯片，对由所述转换芯片基于所述第二接口协议所传输的高清视频数据通过所述FPGA芯片进行封装，获得数据包；
    当所述第一集成电路为ASIC芯片时，
    所述发送设备将所述高清视频数据处理成数据包，包括：
    所述发送设备基于所述第一接口协议将所述高清视频数据传输到所述ASIC芯片中的所述转换芯片，对所述转换芯片基于所述第二接口协议所传输的高清视频数据通过所述ASIC 芯片进行封装，获得所述数据包；
    其中，所述第一接口协议包括：HDMI协议、Type-C协议、DP协议、USB协议、MIPI协议、DVI协议或VGA协议；所述第二接口协议包括：TTL协议、LVDS协议、所述MIPI协议或自定义接口协议；所述数据包包括：UDP数据包、TCP数据包或自定义数据包。
  5. 如权利要求4所述的高清视频数据的发送方法，其特征在于，
    所述第一通信模块集成在所述第一集成电路；
    当所述第一集成电路为FPGA芯片时，所述发送设备将所述数据包发送给第一通信模块，包括：
    所述发送设备通过所述FPGA芯片获得的数据包通过MAC单元基于第三接口协议传输给所述第一通信模块；或者，
    当所述第一集成电路为ASIC芯片时，所述发送设备将所述数据包发送给第一通信模块，包括：
    所述发送设备通过所述ASIC芯片获得的数据包通过MAC单元基于第三接口协议传输给所述第一通信模块；其中，所述第三接口协议包括：XFI协议、MII协议、GMII协议、RGMII协议、SGMII协议、Serdes协议、XAUI协议或RXAUI协议。
  6. 如权利要求1所述的高清视频数据的发送方法，其特征在于，
    所述发送设备包括：第一集成电路；
    当所述第一集成电路为FPGA芯片时，
    所述发送设备将所述高清视频数据处理成数据包，包括：
    所述发送设备通过所述FPGA芯片基于UDP通信协议将所述高清视频数据封装成UDP数据包；或者，
    所述发送设备通过所述FPGA芯片基于TCP通信协议将所述高清视频数据封装成TCP数据包；或者，
    所述发送设备通过所述FPGA芯片基于自定义通信协议将所述高清视频数据封装成自定义数据包；或者，
    当所述第一集成电路为ASIC芯片时，
    所述发送设备将所述高清视频数据处理成数据包，包括：
    所述发送设备通过所述ASIC芯片基于UDP通信协议将所述高清视频数据封装成UDP数据包；或者，
    所述发送设备通过所述ASIC芯片基于TCP通信协议将所述高清视频数据封装成TCP数据包；或者，
    所述发送设备通过所述ASIC芯片基于自定义通信协议将所述高清视频数据封装成自定义数据包。
  7. 如权利要求1所述的高清视频数据的发送方法，其特征在于，
    所述发送设备包括：第一集成电路；
    当所述第一集成电路为FPGA芯片时，
    所述发送设备将所述高清视频数据处理成数据包，包括：
    所述发送设备通过所述FPGA芯片基于无失真编码算法将所述高清视频数据通过进行压缩，获得第一数据，将所述第一数据通过通信协议进行封装，获得数据包；
    当所述第一集成电路为ASIC芯片时，
    所述发送设备将所述高清视频数据处理成数据包，包括：
    所述发送设备通过所述ASIC芯片基于无失真编码算法将所述高清视频数据通过进行压缩，获得第一数据，将所述第一数据通过通信协议进行封装，获得数据包；
    所述通信协议包括：UDP通信协议、TCP通信协议或第二自定义通信协议；
    所述无失真编码算法，包括：
    游程编码算法、哈夫曼编码算法、二值图像的常数块编码算法、四叉树编码算法、小波变换编码算法或自定义算术编码算法。
  8. 如权利要求1所述的高清视频数据的发送方法，其特征在于，
    所述第一通信模块包括：电模块；所述电模块包括：PHY芯片以及RJ-45接口；
    所述发送设备将所述数据包发送给第一通信模块，包括：
    所述发送设备将所述数据包通过MAC单元基于第三接口协议传输给所述PHY芯片，所述PHY芯片用于将所述数据包输出给所述RJ-45接口，所述RJ-45接口用于将所述数据包进行发送；其中，所述第三接口协议包括：XFI协议、MII协议、GMII协议、RGMII协议、SGMII协议、Serdes协议、XAUI协议或RXAUI协议；
    所述电模块的传输速率不低于所述第一阈值。
  9. 如权利要求1所述的高清视频数据的发送方法，其特征在于，
    所述第一通信模块包括：光模块；
    所述发送设备将所述数据包发送给第一通信模块，包括：
    所述发送设备将所述数据包通过MAC单元基于第三接口协议传输给光模块；
    所述光模块用于将所述数据包转换为光信号，并将所述光信号进行发送；其中，所述第三接口协议包括：XFI协议、MII协议、GMII协议、RGMII协议、SGMII协议、Serdes协议、XAUI协议或RXAUI协议；所述光模块的传输速率不低于所述第一阈值。
  10. 如权利要求8所述的高清视频数据的发送方法，其特征在于，
    所述发送设备将所述数据包发送给第一通信模块之后，还包括：
    所述发送设备通过所述PHY芯片将所述数据包输出给所述RJ-45接口，通过所述RJ-45接口将所述数据包发送给接收设备；或者，
    所述发送设备通过所述PHY芯片将所述数据包输出给所述RJ-45接口，通过所述RJ-45接口将所述数据包发送给交换机，所述交换机用于将所述数据包转发给所述接收设备；
    其中，所述数据包包括：UDP数据包，TCP数据包或自定义数据包。
  11. 如权利要求9所述的高清视频数据的发送方法，其特征在于，
    所述发送设备将所述数据包发送给第一通信模块之后，还包括：
    所述发送设备通过所述光模块将所述数据包转换为光信号，并将所述光信号发送给接收设备；或者，
    所述发送设备通过所述光模块将所述数据包转换为光信号，并将所述光信号发送给交换机，所述交换机用于将所述光信号转发给所述接收设备；
    其中，所述数据包包括：UDP数据包，TCP数据包或自定义数据包。
  12. 如权利要求10所述的高清视频数据的发送方法，其特征在于，
    所述接收设备包括：第一接收设备以及第二接收设备；
    所述数据包包括：UDP数据包或TCP数据包；
    所述发送设备将所述数据包发送给第一通信模块之后，还包括：
    所述发送设备通过所述PHY芯片将所述UDP数据包或所述TCP数据包输出给所述RJ-45接口，通过所述RJ-45接口发送给交换机，所述交换机用于将所述UDP数据包或所述TCP 数据包分别转发给所述第一接收设备以及所述第二接收设备。
  13. 如权利要求11所述的高清视频数据的发送方法，其特征在于，
    所述接收设备包括：第一接收设备以及第二接收设备；
    所述数据包包括：UDP数据包或TCP数据包；
    所述发送设备将所述数据包发送给第一通信模块之后，还包括：
    所述发送设备通过所述光模块将所述UDP数据包或所述TCP数据包转换为光信号，并将所述光信号发送给交换机，所述交换机用于将所述光信号转发给所述第一接收设备以及所述第二接收设备。
  14. 一种高清视频数据的接收方法，其特征在于，包括：
    接收设备通过第二通信模块获取数据包；所述第二通信模块的传输速率不低于第二阈值；
    所述接收设备将所述数据包进行处理，获得高清视频数据。
  15. 如权利要求14所述的高清视频数据的接收方法，其特征在于，
    所述第二通信模块包括：电模块；所述电模块包括：PHY芯片以及RJ-45接口；
    所述接收设备通过第二通信模块获取数据包，包括：
    所述接收设备通过所述RJ-45接口接收由发送设备发送的或交换机转发的数据包，并传输给所述PHY芯片；所述电模块的传输速率不低于所述第二阈值；所述数据包包括：UDP数据包，TCP数据包或自定义数据包。
  16. 如权利要求14所述的高清视频数据的接收方法，其特征在于，
    所述第二通信模块包括：光模块；
    所述接收设备通过第二通信模块获取数据包，包括：
    所述接收设备通过所述光模块将接收的由发送设备发送的或交换机转发的光信号转换成数据包；所述光模块的传输速率不低于所述第二阈值；所述数据包包括：UDP数据包，TCP数据包或自定义数据包。
  17. 如权利要求14所述的高清视频数据的接收方法，其特征在于，
    所述接收设备包括：转换芯片以及第二集成电路；所述转换芯片与所述第二集成电路分别独立集成在所述接收设备；
    当所述第二集成电路为FPGA芯片时，
    所述接收设备将所述数据包进行处理，获得高清视频数据，包括：
    所述接收设备通过所述FPGA芯片基于UDP通信协议将UDP数据包解封装，获得高清视频数据，通过第四接口协议将所述高清视频数据输出到所述转换芯片；所述第四接口协议包括：TTL协议、LVDS协议、MIPI协议或自定义接口协议，
    或者，
    所述接收设备通过所述FPGA芯片基于TCP通信协议将TCP数据包解封装，获得高清视频数据，通过第四接口协议将所述高清视频数据输出到所述转换芯片，或者，
    所述接收设备通过所述FPGA芯片基于自定义通信协议将自定义数据包解封装，获得高清视频数据，通过第四接口协议将所述高清视频数据输出到所述转换芯片，或者，
    当所述第二集成电路为ASIC芯片时，
    所述接收设备将所述数据包进行处理，获得高清视频数据，包括：
    所述接收设备通过所述ASIC芯片基于UDP通信协议将UDP数据包解封装，获得高清视频数据，通过第四接口协议将所述高清视频数据输出到所述转换芯片，或者，
    所述接收设备通过所述ASIC芯片基于TCP通信协议将TCP数据包解封装，获得高清视 频数据，通过第四接口协议将所述高清视频数据输出到所述转换芯片，或者，
    所述接收设备通过所述ASIC芯片基于自定义通信协议将自定义数据包解封装，获得高清视频数据，通过第四接口协议将所述高清视频数据输出到所述转换芯片。
  18. 如权利要求14所述的高清视频数据的接收方法，其特征在于，
    所述接收设备包括：转换芯片以及第二集成电路；所述转换芯片集成在所述第二集成电路的内部；
    当所述第二集成电路为FPGA芯片时，
    所述接收设备将所述数据包进行处理，获得高清视频数据，包括：
    所述接收设备通过所述FPGA芯片基于UDP通信协议将UDP数据包解封装，获得高清视频数据，通过第四接口协议将所述高清视频数据输出到所述转换芯片；所述第四接口协议包括：TTL协议、LVDS协议、MIPI协议或自定义接口协议；
    或者，
    所述接收设备通过所述FPGA芯片基于TCP通信协议将TCP数据包解封装，获得高清视频数据，通过第四接口协议将所述高清视频数据输出到所述转换芯片；或者，
    所述接收设备通过所述FPGA芯片基于自定义通信协议将自定义数据包解封装，获得高清视频数据，通过第四接口协议将所述高清视频数据输出到所述转换芯片；或者，
    当所述第二集成电路为ASIC芯片时，
    所述接收设备将所述数据包进行处理，获得高清视频数据，包括：
    所述接收设备通过所述ASIC芯片基于UDP通信协议将UDP数据包解封装，获得高清视频数据，通过第四接口协议将所述高清视频数据输出到所述转换芯片；或者，
    所述接收设备通过所述ASIC芯片基于TCP通信协议将TCP数据包解封装，获得高清视频数据，通过第四接口协议将所述高清视频数据输出到所述转换芯片；或者，
    所述接收设备通过所述ASIC芯片基于自定义通信协议将自定义数据包解封装，获得高清视频数据，通过第四接口协议将所述高清视频数据输出到所述转换芯片。
  19. 如权利要求14所述的高清视频数据的接收方法，其特征在于，
    所述接收设备包括：第二集成电路；
    当所述第二集成电路为FPGA芯片时，
    所述接收设备将所述数据包进行处理，获得高清视频数据，包括：
    所述接收设备通过所述FPGA芯片基于UDP通信协议将UDP数据包解封装，获得高清视频数据；或者，
    所述接收设备通过所述FPGA芯片基于TCP通信协议将TCP数据包解封装，获得所述高清视频数据；或者，
    所述接收设备通过所述FPGA芯片基于自定义通信协议将自定义数据包解封装，获得所述高清视频数据；或者，
    当所述第二集成电路为ASIC芯片时，
    所述接收设备将所述数据包进行处理，获得高清视频数据，包括：
    所述接收设备通过所述ASIC芯片基于UDP通信协议将UDP数据包解封装，获得所述高清视频数据；或者，
    所述接收设备通过所述ASIC芯片基于TCP通信协议将TCP数据包解封装，获得所述高清视频数据；或者，
    所述接收设备通过所述ASIC芯片基于自定义通信协议将自定义数据包解封装，获得所述 高清视频数据。
  20. 如权利要求14所述的高清视频数据的接收方法，其特征在于，
    所述接收设备包括：第二集成电路；
    当所述第二集成电路为FPGA芯片时，
    所述接收设备将所述数据包进行处理，获得高清视频数据，包括：
    所述接收设备通过所述FPGA芯片基于通信协议将所述数据包解封装，获得第一数据，基于无失真解码算法将所述第一数据解压缩，获得高清视频数据；
    所述通信协议包括：UDP通信协议、TCP通信协议或自定义通信协议；
    所述无失真解码算法，包括：
    游程解码算法、哈夫曼解码算法、二值图像的常数块解码算法、四叉树解码算法、小波变换解码算法或自定义算术解码算法。
  21. 如权利要求14所述的高清视频数据的接收方法，其特征在于，
    所述接收设备将所述数据包进行处理，获得高清视频数据之后，还包括：
    所述接收设备将所述高清视频数据通过第五接口协议输出给显示设备；所述第五接口协议包括：HDMI协议、Type-C协议、DP协议、USB协议、MIPI协议、DVI协议或VGA协议。
  22. 一种设备，其特征在于，包括：
    存储器及与所述存储器相连的处理器，所述存储器用于存储应用程序代码，所述处理器被配置用于调用所述应用程序代码，执行如权利要求1-13任一项所述的高清视频数据的发送方法。
  23. 一种设备，其特征在于，包括：
    存储器及与所述存储器相连的处理器，所述存储器用于存储应用程序代码，所述处理器被配置用于调用所述应用程序代码，执行如权利要求14-21任一项所述的高清视频数据的接收方法。
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