WO2022120800A1 - 一种图形处理方法、装置、设备及介质 - Google Patents

一种图形处理方法、装置、设备及介质 Download PDF

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Publication number
WO2022120800A1
WO2022120800A1 PCT/CN2020/135755 CN2020135755W WO2022120800A1 WO 2022120800 A1 WO2022120800 A1 WO 2022120800A1 CN 2020135755 W CN2020135755 W CN 2020135755W WO 2022120800 A1 WO2022120800 A1 WO 2022120800A1
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value
vertices
primitive
vertex
abscissa
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PCT/CN2020/135755
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English (en)
French (fr)
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金济芳
殷亚云
张涛
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华为技术有限公司
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Priority to PCT/CN2020/135755 priority Critical patent/WO2022120800A1/zh
Priority to CN202080107803.0A priority patent/CN116601662A/zh
Publication of WO2022120800A1 publication Critical patent/WO2022120800A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T3/00—Geometric image transformations in the plane of the image
    • G06T3/20—Linear translation of whole images or parts thereof, e.g. panning

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  • the present application relates to the field of graphics processing, and in particular, to a graphics processing method, apparatus, device and medium.
  • a graphics processing unit is widely used in graphics-related fields such as games, videos, and modeling, and is a dedicated hardware-accelerated processor for image rendering.
  • the coordinates of the primitives need to be used to determine the fragments included in the outline of the primitives.
  • the coordinate range of the primitives that can be directly calculated and processed by the rasterized fixed rendering pipeline in the existing GPU is limited. Primitives (for the convenience of description, such primitives are called very large primitives) cannot be calculated directly.
  • the first prior art provides a 3D clipper for processing super large primitives.
  • the first primitive is completely outside the screen (such as the first primitive)
  • the first primitive does not need to be processed, that is, the GPU
  • the first primitive is directly discarded.
  • the GPU fixed hardware pipeline can use the coordinates of the primitive to determine the fragments included in the outline of the primitive. If some of the primitives are inside the screen and the other part is outside the screen (eg, the third primitive), such primitives are very large primitives that cannot be directly calculated by the rasterized fixed rendering pipeline in a GPU in the prior art.
  • the third primitive is usually clipped by the central processing unit (CPU) or by the shader inside the GPU.
  • the part where the third primitive ⁇ V0V1V2 intersects with the screen (quadrilateral V3V4V5V6) is clipped into two triangular primitives ⁇ V3V4V6 and ⁇ V3V5V6, and used as two new primitives. These two new primitives are then rasterized or fragment shaded, respectively.
  • the CPU also needs to calculate the attribute data corresponding to the intersection of the new primitive and the screen by interpolation according to the attribute data such as the color, normal vector, and texture coordinates of the vertex of the third primitive.
  • the present application provides a graphics processing method, apparatus, device, and medium, which are used to improve the speed of processing primitives and do not require clipping of primitives.
  • the present application provides a graphics processing method, which can be executed by an electronic device.
  • the method specifically includes the following steps: the electronic device obtains the primitive to be processed, wherein the vertex coordinates of the primitive are in floating point format; and then for any two adjacent vertices of the primitive, the electronic device according to the The coordinates of the two vertices determine the equation coefficients in the fixed-point number format corresponding to the straight line where the two vertices are located.
  • the electronic device determines a target fragment in the screen according to equation coefficients corresponding to a plurality of straight lines, where the plurality of straight lines include a straight line where every two adjacent vertices in the primitives are located, and colors the target fragment.
  • the electronic device may determine the equation coefficients in the fixed-point format of the straight line where any adjacent two vertices of the primitive are located according to the vertex coordinates in the floating-point format of the primitive.
  • the electronic device can process primitives of any size without clipping the primitives.
  • the electronic device can determine the target fragments covered by the primitives on the screen according to the equation coefficients in the fixed-point number format of the multiple straight lines corresponding to the primitives, which reduces the calculation amount of the fragments covered by the primitives on the screen, and can improve the Process primitive speed.
  • the fixed-point number calculation has high precision.
  • the electronic device uses the linear coefficient of the fixed-point number format to determine the target fragment, which can also improve the accuracy of determining the fragment covered by the primitive on the screen, which helps to improve the quality of graphics processing.
  • the abscissa value or ordinate value of at least one vertex of the primitive is greater than a preset value, and the maximum ordinate value of all the vertices of the rectangular outline of the primitive is greater than the coordinate range of the screen.
  • the minimum ordinate value, and the minimum ordinate value in all the vertices is smaller than the maximum ordinate value in the coordinate range, and the maximum abscissa value in all the vertices is greater than the minimum abscissa value in the coordinate range, and the The minimum abscissa value in all the vertices is smaller than the maximum abscissa value in the coordinate range; when the electronic device determines the equation coefficient operation in the fixed-point number format corresponding to the straight line where the two vertices are located according to the coordinates of the two vertices, it can The coordinates of the two vertices determine the equation coefficients in the floating-point format corresponding to the straight line where the two vertices are located.
  • the scaling factor is determined according to the equation coefficient in the floating point number format and a target threshold value, wherein the target threshold value is the maximum value that can be represented by the fixed point number format. Then, the equation coefficients in the fixed-point format are determined according to the equation coefficients in the floating-point format and the scaling coefficients.
  • the electronic device may also determine the graphic elements beyond the preset range, that is, the super-large graphic elements, for processing.
  • the electronic device can first determine the equation coefficients in the floating-point format of the straight line where the two adjacent vertices of the primitive are located through floating-point calculation. Since the floating-point format can represent a large range of values, the electronic device can also determine the corresponding edges of the super-large primitive. The equation coefficients in line floating point format. Then, the electronic device scales the coefficients in the floating point format of each straight line according to the scaling coefficients corresponding to the straight lines to obtain the equation coefficients in the fixed point format of each straight line.
  • the calculation amount of the coefficients of the fixed-point number format of the line corresponding to each side of the super-large graphic element determined by the electronic device is less than the calculation amount of the cropping of the super-large graphic element, and the processing time of the super-large graphic element can be shortened and the processing speed of the super-large graphic element can be improved.
  • the value of the abscissa and the value of the ordinate of all the vertices of the primitive are smaller than the preset values, and the value of the maximum ordinate among all the vertices of the rectangular outline of the primitive is greater than that in the coordinate range of the screen.
  • the minimum ordinate value, and the minimum ordinate value in all the vertices is smaller than the maximum ordinate value in the coordinate range, and the maximum abscissa value in all the vertices is greater than the minimum abscissa value in the coordinate range, and the The smallest abscissa value in all vertices is smaller than the largest abscissa value in the coordinate range.
  • the electronic device may convert the coordinates of the two vertices into a fixed-point number format when determining the equation coefficients in the fixed-point number format corresponding to the straight line where the two vertices are located according to the coordinates of the two vertices.
  • the equation coefficients in the fixed-point format are then determined based on the coordinates of the two vertices converted to the fixed-point format.
  • the electronic device may first convert the coordinates of two adjacent vertices of the primitives into a fixed-point number format. Then, the equation coefficient of the straight line where the two vertices are located can be determined through fixed-point calculation, which can improve the accuracy of determining the straight line where each edge of the primitive is located, thereby improving the accuracy of determining the fragment covered by the primitive on the screen, which is helpful for Improve the quality of primitive processing.
  • the equation coefficients include an abscissa coefficient, an ordinate coefficient and a constant term, wherein the abscissa coefficient is based on the ordinate value of the first vertex in the two vertices and the two vertices. It is determined by the difference of the ordinate values of the second vertex among the vertices.
  • the longitudinal variable coefficient is determined according to the difference between the abscissa value of the second vertex and the abscissa value of the first vertex.
  • the constant term is determined according to the difference between the first value and the second value, where the first value is the product of the abscissa value of the first vertex and the ordinate value of the second vertex, and the first value is the product of the abscissa value of the first vertex and the ordinate value of the second vertex.
  • the two values are the product of the abscissa value of the second vertex and the ordinate value of the first vertex.
  • the fixed points of the primitives are sorted according to a preset order, and the first vertex is in front of the second vertex.
  • the relationship between the coordinates of two adjacent vertices of the primitives and the equation coefficients of the straight line where the two vertices are located is the same, which simplifies the processing of primitives and is beneficial to implementation.
  • the electronic device uses the coordinates of the two adjacent vertices in a floating-point format to determine the equation coefficients of the straight line through floating-point calculation.
  • the electronic device may also use the coordinates of two adjacent vertices in a fixed-point format to determine the equation coefficients of the straight line through fixed-point calculation.
  • the electronic device can determine the positional relationship between each fragment and the straight line where each edge of the primitive is located through fixed-point calculation according to the equation coefficients in the fixed-point format of the straight line and the coordinates of each fragment on the screen. Due to the high precision of fixed-point calculation, the electronic device can accurately determine the positional relationship between each fragment and the line where each edge of the primitive is located, so that the electronic device can accurately determine the map according to the preset positional relationship corresponding to each line. The fragment that the element covers on the screen.
  • the electronic device determines the equation coefficients in the fixed-point number format corresponding to the straight line where the two vertices are located according to the coordinates of the two vertices, if the electronic device determines all the coordinate vertices of the rectangular outline of the primitive to be processed.
  • the smallest vertical coordinate value in the screen is greater than the largest vertical coordinate value in the coordinate range of the screen, or the largest vertical coordinate value in all the vertices is smaller than the smallest vertical coordinate value in the coordinate range, or the smallest horizontal coordinate value in all the vertices is greater than If the maximum abscissa value in the coordinate range, or the maximum abscissa value in all the vertices is smaller than the minimum abscissa value in the coordinate range, it is determined to discard the primitive to be processed.
  • the electronic device performs filtering processing on the primitives before determining the equation coefficients in the fixed-point number format of the straight lines where the sides of the primitives are located. If the electronic device determines that any part of the graphic element is not in the coordinate range of the screen, the graphic element is discarded and the graphic element is not processed. Since the graphic element is not in the coordinate range of the screen, the graphic element will not be displayed on the screen, so the electronic device discards the graphic element, which does not affect the display effect on the screen.
  • the electronic device before the electronic device determines the equation coefficients in the fixed-point number format corresponding to the straight line where the two vertices are located according to the coordinates of the two vertices, the electronic device can The coordinates of all vertices of the rectangular outline and the coordinate range of the screen classify the primitives. If the electronic device determines that the value of the abscissa or the value of the ordinate of at least one vertex of the primitive is greater than the preset value, the maximum value of the ordinate among all the vertices of the rectangular outline of the primitive is greater than the smallest value of the ordinate in the coordinate range of the screen.
  • the graphic element is an oversized graphic element. If the electronic device determines that the abscissa value and the ordinate value of all the vertices of the primitive are smaller than the preset value, the maximum ordinate value of all the vertices of the rectangular outline of the primitive is greater than the minimum ordinate value in the coordinate range of the screen.
  • the graphic element is a normal graphic element.
  • the electronic device may classify the graphic elements to be processed. If the electronic device determines that the maximum ordinate value in all vertices of the rectangular outline of the primitive is greater than the minimum ordinate value in the coordinate range of the screen, and the minimum ordinate value in all the vertices is smaller than the maximum ordinate value in the coordinate range value, and the maximum abscissa value in all the vertices is greater than the minimum abscissa value in the coordinate range, and the minimum abscissa value in all the vertices is smaller than the maximum abscissa value in the coordinate range, the primitive and the screen can be determined. There is an intersection.
  • the electronic device may determine that the graphic element intersecting with the screen is a normal graphic element according to the coordinate values of all the vertices of the graphic element being smaller than the preset threshold. Conversely, it can be determined that the primitive that intersects with the screen is an oversized primitive.
  • the electronic device can determine the coefficients of the fixed-point number format equations corresponding to the plurality of straight lines of the primitives in different ways for different types of primitives.
  • the present application provides a graphics processing apparatus including a rasterizer and a shader.
  • a rasterizer used to obtain a primitive to be processed, wherein the vertex coordinates of the primitive are in a floating-point format; and for any two adjacent vertices of the primitive, determine according to the coordinates of the two vertices
  • the equation coefficients in the fixed-point number format corresponding to the straight lines where the two vertices are located; and the target fragment in the screen is determined according to the equation coefficients corresponding to the multiple straight lines, and the multiple straight lines include every two adjacent The line where the vertices lie. shader for shading the target fragment.
  • the abscissa value or ordinate value of at least one vertex of the primitive is greater than a preset value
  • the maximum ordinate value of all the vertices of the rectangular outline of the primitive is greater than the coordinate range of the screen.
  • the minimum ordinate value, and the minimum ordinate value in all the vertices is smaller than the maximum ordinate value in the coordinate range
  • the maximum abscissa value in all the vertices is greater than the minimum abscissa value in the coordinate range
  • the The smallest abscissa value in all vertices is smaller than the largest abscissa value in the coordinate range.
  • the rasterizer determines, according to the coordinates of the two vertices, the equation coefficients in the fixed-point number format corresponding to the straight line where the two vertices are located, the rasterizer is specifically configured to: determine the two vertices according to the coordinates of the two vertices.
  • the equation coefficients in floating-point format corresponding to the line where the vertex is located.
  • the scaling factor is determined according to the equation coefficient in the floating point number format and a target threshold value, wherein the target threshold value is the maximum value that can be represented by the fixed point number format.
  • the equation coefficients in the fixed-point format are determined according to the equation coefficients in the floating-point format and the scaling coefficients.
  • the value of the abscissa and the value of the ordinate of all the vertices of the primitive are smaller than the preset values, and the value of the maximum ordinate among all the vertices of the rectangular outline of the primitive is greater than that in the coordinate range of the screen.
  • the minimum ordinate value, and the minimum ordinate value in all the vertices is smaller than the maximum ordinate value in the coordinate range, and the maximum abscissa value in all the vertices is greater than the minimum abscissa value in the coordinate range, and the The smallest abscissa value in all vertices is smaller than the largest abscissa value in the coordinate range.
  • the rasterizer When determining, according to the coordinates of the two vertices, the equation coefficients in the fixed-point number format corresponding to the straight line where the two vertices are located, the rasterizer is specifically configured to: convert the coordinates of the two vertices into the fixed-point number format. And based on the coordinates of the two vertices converted into the fixed-point format, the equation coefficients in the fixed-point format are determined.
  • the equation coefficients include an abscissa coefficient, an ordinate coefficient and a constant term, wherein the abscissa coefficient is based on the ordinate value of the first vertex in the two vertices and the two vertices. It is determined by the difference of the ordinate values of the second vertex among the vertices.
  • the longitudinal variable coefficient is determined according to the difference between the abscissa value of the second vertex and the abscissa value of the first vertex.
  • the constant term is determined according to the difference between the first value and the second value, where the first value is the product of the abscissa value of the first vertex and the ordinate value of the second vertex, and the first value is the product of the abscissa value of the first vertex and the ordinate value of the second vertex.
  • the two values are the product of the abscissa value of the second vertex and the ordinate value of the first vertex.
  • the fixed points of the primitives are sorted according to a preset order, and the first vertex is in front of the second vertex.
  • the rasterizer determines the target fragment in the screen according to the equation coefficients corresponding to the multiple straight lines, it is specifically used for: for any fragment in the screen, based on the i-th
  • the equation corresponding to the straight line determines whether the fragment satisfies the preset positional relationship corresponding to the i-th straight line, wherein the preset positional relationship of the i-th straight line is that the fragment is in the i-th straight line.
  • the graphics processing apparatus further includes a memory for data required for graphics processing or data generated during graphics processing.
  • the memory stores data such as the coordinate range of the screen, the vertex coordinates of the primitives, etc.
  • an embodiment of the present application provides an electronic device, including a processor, a display screen assembly, and the graphics processing apparatus according to any one of the second aspect.
  • the processor is configured to display the fragment output obtained by the graphics processing device on the display screen component.
  • the embodiments of the present application provide a chip, which can be coupled with a display screen component in an electronic device, and is used to implement the first aspect of the embodiments of the present application and any possible design technical solutions of the first aspect.
  • "Coupling" in the embodiments of the present application means that two components are directly or indirectly combined with each other.
  • the chip can obtain the primitive to be processed, wherein the vertex coordinates of the primitive are in a floating-point format; for any two adjacent vertices of the primitive, the coordinates of the two vertices are used to determine the The equation coefficients in the fixed-point number format corresponding to the straight lines where the two vertices are located; the target fragment in the screen is determined according to the equation coefficients corresponding to the multiple straight lines, and the multiple straight lines include every two adjacent vertices in the primitives The line on which it is located; color the target fragment.
  • the chip may instruct the display screen assembly to display the target fragment.
  • an embodiment of the present application provides a circuit system.
  • the circuitry may be one or more chips, such as a system-on-chip.
  • the circuit system includes: at least one processing circuit; the at least one processing circuit is used for acquiring a primitive to be processed, wherein the vertex coordinates of the primitive are in floating point format.
  • the equation coefficients of the fixed-point number format corresponding to the straight line where the two vertices are located are determined according to the coordinates of the two vertices.
  • the target fragment in the screen is determined according to equation coefficients corresponding to a plurality of straight lines, and the plurality of straight lines include a straight line where every two adjacent vertices in the primitive are located.
  • the target fragment is shaded.
  • an embodiment of the present application provides a computer-readable storage medium, where the computer-readable storage medium includes a computer program, and when the computer program runs on a processor, the processor causes the processor to execute the first embodiment of the present application.
  • a computer program product of the embodiments of the present application when the computer program product runs on an electronic device, enables the electronic device to execute the first aspect of the embodiments of the present application and any possibility of the first aspect thereof designed technical solutions.
  • FIG. 1 is a schematic diagram of a graphics processing process in the prior art one
  • Fig. 2 is a schematic diagram of a graphics processing process in prior art two;
  • FIG. 3 is a graphics processing apparatus provided by an embodiment of the present application.
  • FIG. 4 is a schematic diagram of the relationship between a graphic element and a display range
  • FIG. 5 is a schematic diagram of the relationship between a rectangular outline of a graphic element and a display range
  • FIG. 6 is a schematic structural diagram of a rasterizer according to an embodiment of the present application.
  • FIG. 7 is a schematic structural diagram of a primitive processing pipeline provided by an embodiment of the present application.
  • FIG. 8 is a schematic structural diagram of another primitive processing pipeline provided by an embodiment of the present application.
  • FIG. 9 is a schematic diagram of a primitive vertex provided by an embodiment of the present application.
  • Figure 10 is a schematic diagram of the relationship between the graphic element and the determination range
  • FIG. 11 is a schematic diagram of a preset direction side of a straight line where an outline of a primitive is located;
  • FIG. 12 is a schematic diagram of a graphics processing process provided by an embodiment of the present application.
  • FIG. 13 is a schematic flowchart of a graphics processing method provided by an embodiment of the present application.
  • FIG. 14 is a schematic flowchart of another graphics processing method provided by an embodiment of the present application.
  • FIG. 15 is a schematic structural diagram of a graphics processor according to an embodiment of the present application.
  • FIG. 16 is a chip provided by an embodiment of the present application.
  • FIG. 17 is an electronic device provided by an embodiment of the present application.
  • GPU is widely used in graphics-related fields such as games, video, and modeling. It is a dedicated hardware-accelerated processor for image rendering. GPUs can typically process various two-dimensional (2D) or three-dimensional (3D) models. Models are generally composed of simple geometric primitives such as points, lines, or triangles. For other complex primitives, the GPU can first convert them into simple geometric primitives, and then perform rasterization, fragment shading, etc. on the geometric primitives through fixed hardware pipelines. Due to factors such as design complexity, hardware cost, and computational accuracy, the GPU fixed hardware pipeline is difficult to directly process large primitives.
  • the screen range is configured as the coordinate range of the processing primitives, and the positional relationship between the input primitives and the screen is determined based on the screen range.
  • the fixed hardware pipeline in the GPU provided by the prior art 1 can directly process the primitives that are completely within the screen range. For super large primitives that cannot be directly processed by the fixed hardware pipeline, that is, some primitives are within the screen range and another part is outside the screen range, the prior art clips a pair of super large primitives.
  • the third graphic element in FIG. 1 is a part of the graphic element inside the screen and another part outside the screen, which is a super large graphic element.
  • the CPU when a pair of third primitives is clipped, first, the CPU usually detects the edge of the third primitive ⁇ V0V1V2 and the four boundaries of the screen. Based on the calculation of the straight line equation, the CPU determines that the intersection points of the third graphic element ⁇ V0V1V2 and the screen are the point V3, the point V4, the point V5, and the point V6, respectively.
  • the CPU constructs a new primitive based on the intersection of the third primitive ⁇ V0V1V2 and the screen, for example, determines ⁇ V3V4V6 and ⁇ V3V5V6 as new primitives corresponding to the third primitive.
  • the CPU inputs the new primitives corresponding to the third primitives into the GPU, so the GPU does not process the third primitives, but rasterizes or rasterizes the new primitives ⁇ V3V4V6 and ⁇ V3V5V6 corresponding to the third primitives determined by the CPU. Fragment shader processing.
  • the CPU also needs to use the interpolation method to calculate the attribute data corresponding to the intersection of the third primitive and the screen through the attribute data such as the color, normal vector and texture coordinates of the vertex of the third primitive.
  • the CPU before inputting the super-large primitive into the GPU, the CPU also needs to perform clipping processing on the super-large primitive.
  • the CPU load is aggravated, making the CPU the performance bottleneck of the system.
  • the CPU after the CPU clips the super-large primitive, it also needs to recalculate the attribute data of the intersection of the super-large primitive and the screen. If the number of attribute types in the attribute data is large, the processing speed will be greatly reduced.
  • the new primitives corresponding to the super-large primitives may be multiple primitives, when rendering the super-large primitives, the GPU actually processes multiple primitives, which increases the load of the GPU and causes the loss of GPU performance and power consumption. .
  • the second prior art provides a guard band clipping (GBC) method, which is used for processing super large primitives.
  • GBC guard band clipping
  • the positional relationship between the input graphic element and the guard zone is first determined based on the range of the guard zone.
  • the primitive is completely outside the screen (such as the fourth primitive)
  • the fourth primitive is directly discarded.
  • the GPU fixed hardware pipeline can use the coordinates of the primitive to determine the fragments included in the primitive outline .
  • the prior art 2 performs clipping processing for very large primitives that cannot be directly processed by GPU fixed hardware pipelines, that is, a part of the primitives is within the guard band and another part is outside the guard zone, such as the sixth primitive.
  • the GPU detects the edge of the sixth primitive ⁇ M0M1M2 and the four boundaries of the guard band.
  • the GPU determines that the intersection points of the sixth primitive ⁇ M0M1M2 and the screen are the point M3, the point M4, the point M5, and the point M6, respectively.
  • the GPU constructs a new primitive based on the intersection of the sixth primitive ⁇ M0M1M2 and the screen, for example, ⁇ M3M4M6 and ⁇ M3M5M6 are determined as new primitives corresponding to the sixth primitive.
  • the GPU inputs the new primitive corresponding to the sixth primitive into the GPU.
  • the GPU does not directly process the sixth primitive, but performs rasterization or fragment coloring processing on the new primitives ⁇ M3M4M6 and ⁇ M3M5M6 generated by clipping the sixth primitive.
  • the GPU also needs to use the interpolation method through the attribute data such as the color, normal vector and texture coordinates of the vertices of the sixth primitive to calculate Attribute data corresponding to the intersection of the sixth primitive and the screen. Due to the need to determine the attribute data of new vertices generated after primitive clipping, the GPU processing speed of primitives will be greatly reduced.
  • a GPU is usually used to implement the above-mentioned cropping function. If the clipping function is implemented by the shader in the GPU, it will make the GPU hardware pipeline and programming model more complicated. If implemented by a dedicated hardware circuit in the GPU, clipping and attribute interpolation will introduce a large hardware overhead. In addition, after a primitive like the sixth primitive is cropped by the GPU, multiple primitives may be generated, which also increases the pipeline load such as subsequent rasterization of the GPU, resulting in a decrease in GPU performance and a sharp increase in power consumption.
  • the present application provides a graphics processing method, apparatus, device and medium, which can improve the speed of processing primitives, improve the performance of processing super large primitives, and do not need to clip the primitives.
  • the circuit with the function of rasterization fixed rendering pipeline in the graphics processing device can process any primitive without any restriction on the coordinate range of the primitive.
  • the method and the device are based on the same technical concept. Since the principles of the method and the device for solving the problem are similar, the implementation of the device and the method can be referred to each other, and the repetition will not be repeated.
  • some terms in the present application will be explained so as to facilitate the understanding of those skilled in the art.
  • data in a computer can be expressed in both floating-point and fixed-point formats.
  • a numerical value can be expressed in floating-point format or fixed-point format, neither of which affects the numerical value.
  • the mathematical form of the numerical value N can be recorded as M ⁇ RE , where M is the mantissa, R is the base, and E is the order code.
  • the numerical value N can be represented by a combination of mantissa, base and exponent in the computer. In a computer, the base is generally a fixed number.
  • the floating-point number format can represent a large range of values, for example, IEEE FP32 floating-point numbers can represent a range of the order of 10 38 .
  • the mathematical operations (such as addition, subtraction, multiplication, division, etc.) of data in floating-point format are complicated. Compared to fixed-point arithmetic, floating-point arithmetic has lower precision and is nonlinear.
  • the position of the decimal point in fixed-point format is fixed.
  • the position of the decimal point can be set to any position.
  • fixed-point format can represent pure decimals or pure integers.
  • the decimal point is not stored.
  • the position of the decimal point is fixed.
  • the fixed-point number format can represent a small range of values. For example, a 32-bit fixed-point number format can only represent a range of the magnitude of 10 9 , which is much smaller than a floating-point number of the same bit width.
  • the mathematical operations in the fixed-point format are simple and have high precision, and the precision is linear over the entire representation range.
  • the straight line is recorded in the computer by recording the coefficients in the equation of the straight line.
  • the straight line equation of the line where the outline of the primitive is located is also called the edge equation, and it is also the straight line equation of the straight line where any two adjacent vertices of the primitive are located.
  • An embodiment of the present application provides a graphics processing apparatus, which can process any primitive that expresses vertex coordinates in a floating-point format. For example, a primitive representing vertex coordinates in FP32 floating point format.
  • the graphics processing apparatus may include a rasterizer 30 and a fragment shader 31 .
  • the graphics processing device may also include a vertex shader 32 .
  • Vertex shader 32 may perform vertex transformations on primitives prior to input to rasterizer 30 .
  • the vertex transformation process usually refers to the processing of translation, rotation, and scaling of primitives according to the configuration parameters of graphics processing.
  • the graphics processing configuration parameters may be carried by graphics processing instructions triggered by the user. For example, the translation distance in the primitive processing configuration parameter is x, and the graphics processing device determines the coordinates of the translated primitive according to the translation distance and the coordinates of the primitive.
  • the graphics processing apparatus may further include a drawing layer unit 33, and the drawing layer unit 33 may generate a layer including the colored fragments.
  • Vertex shader 32 may input the transformed coordinates of the vertices of primitives to rasterizer 30 .
  • the rasterizer 30 may then filter the primitives.
  • the rasterizer 30 may detect all the vertices of the primitive to determine whether each vertex is within the display range.
  • the display range may be the presentation range of the display device connected to the graphics processing device. For example, the screen area, or the projection area.
  • the primitives input to the rasterizer 30 may be lines and triangles. Also, the vertex coordinates of the primitives input to the rasterizer 30 are in floating point format.
  • the rasterizer 30 can divide the primitives into primitives outside the display range (such as primitives 1 shown in FIG. 4 ) and primitives in the display range.
  • primitives within the display range there are two types of primitives within the display range (such as primitive 2, primitive 3, and primitive 4 as shown in Figure 4).
  • the graphic elements within the display range can be understood as all or part of the graphic elements within the display range.
  • all the graphic elements 2 are within the display range, and the graphic elements 2 belong to the display range.
  • the graphic element 3 is partially within the display range, and the graphic element 3 belongs to the graphic element type within the display range.
  • the rasterizer 30 can determine the vertex coordinates of the rectangular outline of the primitive based on all the vertex coordinates of the primitive. Rasterizer 30 compares the coordinates of all vertices of the primitive's rectangular outline to a first coordinate threshold.
  • the first coordinate threshold may be determined according to the vertex coordinates of the display range.
  • the first coordinate threshold may include a first abscissa threshold and a first ordinate threshold. As shown in FIG. 5 , the coordinates of the vertices of the display range are (x1, y1), (x1, y2), (x2, y1), (x2, y2) respectively, where x2>x1, y2>y1.
  • the first abscissa thresholds are x1, x2, and the first ordinate thresholds are y1, y2.
  • the vertex coordinates of the rectangular outline are respectively (v1, w1), (v1, w2), (v2, w1), (v2, w2), where , v2>v1, w2>w1.
  • the coordinates of the i-th vertex Pi among all the vertices of the rectangular outline can be recorded as (mi, ni).
  • the rasterizer 30 may compare the abscissas mi of the vertices of the rectangular outline with x1, x2, respectively, and the ordinates ni of the vertices of the rectangular outline with y1, y2 , respectively.
  • Rasterizer 30 compares the coordinates of the rectangular outline of the primitive to a first coordinate threshold.
  • the first coordinate threshold may be determined according to the vertex coordinates of the display range.
  • the vertex coordinates of the display range are (x1, y1), (x1, y2), (x2, y1), (x2, y2) respectively, where x2>x1, y2>y1.
  • the raster The renderer 30 may determine that the primitive is a primitive that is outside the display range. For example, in the primitive 1 shown in FIG. 5, the ordinate of any vertex Pj of the rectangular outline of the primitive 1 satisfies n j ⁇ y2, and the primitive 1 is a primitive outside the display range. Since the primitive is completely outside the display range and has no effect on the display situation within the display range, the rasterizer 30 can discard the primitive.
  • the rasterizer 30 determines that the primitive is not a primitive that is outside the display range, it can determine that the primitive is within the display range.
  • the rasterizer 30 can also determine the maximum abscissa v2 ⁇ x1, or the minimum abscissa v1 ⁇ x2 among all the vertices of the rectangular outline of the primitive. , or the maximum ordinate v2 ⁇ y1, or the minimum ordinate v1 ⁇ y2, the rasterizer 30 can determine that the primitive is a primitive outside the display range.
  • the rasterizer 30 determines that the largest abscissa v2>x1, the smallest abscissa v1 ⁇ x2, the largest ordinate v2>y1, and the smallest ordinate v1 ⁇ y2 among all the vertices of the rectangular outline of the primitive, can determine This element is the element within the display range.
  • the rectangular outline of the primitive includes the entire coverage area of the primitive, so the actual coverage area of the primitive is a subset of the rectangular outline of the primitive. If the rectangular outline of the graphic element does not intersect with the display range, the actual coverage area of the graphic element does not intersect with the display range, and it can be determined that the graphic element is completely outside the display range.
  • the rasterizer 30 does not process the primitive, and does not affect the display condition of the display range. Thus rasterizer 30 may discard primitives that are outside the display range.
  • the rasterizer 30 may include a vertex detection circuit 60 , a primitive processing pipeline 61 , and a rasterization circuit 62 connected in sequence.
  • the input terminal of the vertex detection circuit 60 is also the input terminal of the rasterizer 30 .
  • the output of rasterizer circuit 62 is also the output of rasterizer 30 .
  • the functions or capabilities implemented by the vertex detection circuit 60 , the functions or capabilities implemented by the primitive processing pipeline 61 , and the functions or capabilities implemented by the rasterizer circuit 62 are also the functions or capabilities that can be implemented by the rasterizer 30 . .
  • the functions or capabilities that can be implemented by the vertex detection circuit 60, the primitive processing pipeline 61, and the rasterization circuit 62 are described below.
  • the vertex detection circuit 60 in the embodiment of the present application may perform the aforementioned process of filtering the primitives, and then input the vertex coordinates of the primitives within the display range in the floating point format into the primitive processing pipeline 61 .
  • the primitive processing pipeline 61 can perform graphics processing on any primitive located within the display range, for example, determine the edge equation of the primitive.
  • the primitive processing pipeline 61 provided in this embodiment of the present application may be the first primitive processing pipeline 6110 .
  • the first primitive processing pipeline 6110 may include a first coefficient determination circuit 6111 and a first format conversion circuit 6112 connected in sequence.
  • the input terminal of the first coefficient determination circuit 6111 can be connected to the output terminal of the vertex detection circuit 60, and receives the vertex coordinates of the primitives provided by the vertex detection circuit 60, wherein the vertex coordinates are in floating point format.
  • the output terminal of the first format conversion circuit 6112 can be connected to the input terminal of the rasterizer circuit 62 , and input the coefficients in the fixed-point format of the line equation (edge equation) corresponding to the primitive into the rasterizer circuit 62 .
  • the first coefficient determination circuit 6111 may also be referred to as a floating-point number-based straight-line equation calculation circuit.
  • the first coefficient determination circuit 6111 is used to determine the straight line equation of the straight line where any two adjacent vertices of the primitive are located, that is, to determine the straight line equation of each straight line forming the outline of the primitive, wherein the vertex coordinates are in floating point format.
  • the following formula can be used to determine the coefficient of the straight line equation with the adjacent vertices Pi(m i , n i ) and Pi+1(m i+1 , n i+1 ) in the primitive:
  • the coefficient of the determined straight line equation is also in the floating-point format.
  • the floating-point number format can represent a large range of values, so the embodiments of the present application can directly process any primitive, and do not need to clip the primitive or set a guard band.
  • the primitive processing pipeline 61 provided by the embodiment of the present application does not limit the coordinate range of primitives, and can process primitives with large vertex coordinate values.
  • the first coefficient determination circuit 6111 uses the floating point format in the process of determining the coefficients of the equation of the straight line, which can prevent overflow of the calculation result. And the accuracy can be kept intact during the mathematical operations (such as addition, subtraction, multiplication, division, etc.) in the process of determining the coefficients of the equation of the straight line.
  • the first coefficient determination circuit 6111 may express the result of the multiplication of the coordinates of the vertex of the primitive in the floating point format FP32 in the floating point format FP64.
  • the first format conversion circuit 6112 may also be referred to as a normalizer circuit.
  • the first format conversion circuit 6112 is configured to convert the linear equation coefficients in the floating point format output by the first coefficient determination circuit 6111 into the fixed point format.
  • the fixed-point number format can represent a small range of values. However, the value corresponding to the floating-point number format output by the first coefficient determination circuit 6111 may exceed the maximum value range that can be represented by the fixed-point number format.
  • An embodiment of the present application provides a method for converting a floating-point number format into a fixed-point number format, which is applied in a scenario of converting coefficients of a straight line equation.
  • the straight line L can also use the straight line equation
  • the terms on the left side of the equation are divided by the value q, and the terms on the right side of the equation are also divided by the value q, without changing the equality relationship on both sides of the equation. Since the right side of the equal sign in the equation of a straight line is 0, it is still 0 after dividing by the value q. Therefore the straight line L can be represented by different straight line equations. If the equation coefficients are simultaneously divided by the numerical value q or multiplied by the numerical value q at the same time, the straight line L is not changed, only the straight line equation coefficients representing the straight line L are changed.
  • the coefficients in the floating-point format can be scaled. Scales coefficients in floating-point format to the range of values that can be represented in fixed-point format. The scaled line coefficients are then recorded in fixed-point number format.
  • the first format conversion circuit 6112 may determine the scaling factor S according to the coefficients A, B, and C of the floating-point number format and the maximum value N in the numerical range (-N, N) that the fixed-point number format can represent.
  • S is the largest value in the coefficients of the straight line equation in floating point format, that is,
  • the numerical value N may be determined according to the number of digits in the fixed-point number format, and the numerical value N may be the maximum numerical value that can be represented by the fixed-point number format.
  • the first format conversion circuit 6112 performs scaling processing on the coefficients A, B, and C in the floating point format of the straight line equation according to the determined scaling coefficient S.
  • the scaled coefficients are The scaled coefficients are within the range of values that the fixed-point number format can represent.
  • the first format conversion circuit 6112 records the scaled coefficients A', B', C' of the equation of the straight line in a fixed-point number format.
  • the first format conversion circuit 6112 may determine the coefficients in the fixed-point format of the straight-line equation by right-shifting the mantissa of the coefficients in the floating-point format of the straight-line equation.
  • the coefficients A, B, C of the floating-point number format of the straight line equation, the corresponding exponents in the floating-point number format can be recorded as E A , E B , and E C respectively, and the mantissas in the floating-point number format corresponding to the coefficients A, B, and C can be They are denoted as MA , MB , and MC respectively.
  • the first format conversion unit 6112 may implement scaling of the coefficients of the straight line equation by shifting the mantissa part of the coefficients to the right.
  • E max max(EA , EB , EC ).
  • the primitive processing pipeline 61 may be the second primitive processing pipeline 6120 .
  • the second primitive processing pipeline 6120 may include a second format conversion circuit 6121 and a second coefficient determination circuit 6122 connected in sequence.
  • the input terminal of the second format conversion circuit 6121 can be connected to the output terminal of the vertex detection circuit 60, and receives the vertex coordinates of the primitives provided by the vertex detection circuit 60, wherein the vertex coordinates are in floating point format.
  • the output terminal of the second coefficient determination circuit 6122 may be connected to the input terminal of the rasterization circuit 62 , and the coefficients in the fixed-point format of the line equation corresponding to the primitive are input into the rasterization circuit 62 .
  • the second format conversion circuit 6121 may also be referred to as a floating-point number to fixed-point number circuit.
  • the second format conversion circuit 6121 is configured to convert the floating point format coordinates of the vertices of the primitive into fixed point format coordinates, wherein the coordinates of the primitive vertices are within the numerical range that can be represented by the fixed point format.
  • the vertex detection circuit 60 inputs the floating point format coordinates (m j , n j ) of any vertex Pj of the primitive into the second format conversion circuit 6121, and the second format conversion circuit 6121 converts the floating point format coordinates (m j ) of any vertex Pj. , n j ) into fixed-point format coordinates (m j ', n j ').
  • m j and m j ' are both the same numerical value, but the form of the numerical value is different.
  • the second coefficient determination circuit 6122 may also be referred to as a fixed-point number-based straight-line equation calculation circuit.
  • the second coefficient determination circuit 6122 is used to determine the straight line equation of the straight line where any two adjacent vertices of the primitive are located, wherein the coordinates of the vertices are the coordinates of the fixed point format output by the second format conversion circuit 6121 .
  • the following formula can be used to determine the coefficient of the straight line equation with the adjacent vertices Pi(m i ', n i ') and Pi+1(m i+1 ', n i+1 ') in the primitive:
  • the adjacent vertices Pi and Pi+1 in the primitive are sorted in a certain order.
  • the number of all vertices of the primitive is 3, which are P0, P1, and P2 respectively.
  • the specified direction is x.
  • the included angles of the ray OP0, the ray OP1, the ray OP2 and the predetermined direction x are respectively determined, and the order of all the vertices of the pattern is determined according to the included angle of each ray.
  • the angle between the ray OP0 and the prescribed direction is ⁇ 0
  • the angle between the ray OP1 and the prescribed direction is ⁇ 1
  • the angle between the ray OP2 and the prescribed direction is ⁇ 2 .
  • the vertex ordering can be the same as that of the included angles, and the vertex ordering can be P0, P1, and P2. In other words, take point O as the reference point, and sort the vertices in a counterclockwise direction.
  • the adjacent vertices Pi and Pi+1 may be P0 and P1, respectively, or P1 and P2, respectively, and may also be P0 and P2, respectively.
  • the adjacent vertices Pi(m i , n i ) and Pi+1(m i+1 , n i+1 ) can use the following formula to determine the coefficient of the straight line equation:
  • the vertex ordering can also be opposite to that of the included angles, and the vertex ordering can be P2, P1, and P0.
  • the vertex ordering can be P2, P1, and P0.
  • the vertices are sorted clockwise.
  • the adjacent vertices Pi and Pi+1 may be P2 and P1, respectively, or P1 and P0, respectively, and may also be P2 and P0, respectively.
  • the primitive processing pipeline 61 in the graphics processing apparatus is the first primitive processing pipeline 6110 .
  • the first primitive processing pipeline 6110 is based on the coordinates of the vertices of the primitives in the floating-point format, calculates the coefficients in the floating-point format of the line equation of the outline of the primitives, and then converts the coefficients in the floating-point format of the line equation into Coefficients in fixed-point format.
  • the floating-point number format can represent a wide range of values, and can determine the coefficients of the straight line equation of the outline of primitives of any size, so that the image processing device can directly process the super-large primitives, and does not need to cut the super-large primitives and determine the attributes.
  • the process of data processing can speed up the processing of very large primitives.
  • the primitive processing pipeline 61 in the graphics processing device is the second primitive processing pipeline 6120 .
  • the second primitive processing pipeline 6120 converts the coordinates of the vertices of the primitive in the floating point format into the coordinates in the fixed point format, and then calculates the coefficients in the fixed point format of the straight line equation of the outline of the primitive.
  • the coordinates in the fixed-point format are used, and the data operation speed in the fixed-point format is faster, which can improve the processing speed of primitives.
  • the primitive processing pipeline 61 in the graphics processing apparatus includes at least one first primitive processing pipeline 6110 and at least one second primitive processing pipeline 6120 .
  • the vertex detection circuit 60 may filter the input primitives. If the vertex detection circuit 60 determines that the input primitive is a primitive in the display range, it can also classify the primitives in the display range, and divide the primitives in the display range into normal primitives and super large primitives. types.
  • the vertex detection circuit 60 can determine that the input primitive is a normal primitive if all the vertices of the primitive are within the pre-determined range. If at least one vertex among all the vertices of the primitive is not in the determination range, the rasterizer 30 may determine that the input primitive is a very large primitive. As shown in Figure 10, all the vertices of primitive 5 and primitive 6 are not within the judgment range. There is one vertex in primitive 5 that is outside the determination range, and primitive 5 is a super-large primitive. All vertices of the primitive 6 are outside the determination range, and the primitive 6 is a super-large primitive.
  • the determination range may be determined according to the representation range of the floating point number format. Any numerical value in the judgment range is within the representation range of the floating-point number format.
  • the determination range may be determined according to a simulation experiment result or set according to an empirical value, and the determination range is larger than the guard band range in the second prior art.
  • the vertex detection circuit 60 determines whether the primitive is a super large primitive.
  • the vertex detection circuit 60 may determine whether all the vertices of the primitive are within the determination range by comparing the coordinates of all the vertices of the primitive with the second coordinate threshold.
  • the second coordinate threshold may be determined according to the vertex coordinates of the determination range.
  • the second coordinate threshold may include a second abscissa threshold and a second ordinate threshold.
  • the vertex coordinates of the determination range are (r1, t1), (r1, t2), (r2, t1), (r2, t2), where r2>r1, t2>t1.
  • the second abscissa thresholds are r1, r2, and the second ordinate thresholds are t1, t2.
  • the coordinates of the i-th vertex Pi among all the vertices of the primitive can be recorded as (m i , n i ).
  • the vertex detection circuit 60 can compare the abscissas mi of the vertices of the primitives with r1 and r2 respectively, and compare the ordinates ni of the vertices of the primitives with t1 and t2 respectively.
  • the vertex detection circuit 60 may also determine that the primitive is a primitive outside the determination range and is also a super large primitive.
  • the vertex detection circuit 60 determines that the primitive is a normal primitive if it is determined that the primitive is not an extra-large primitive.
  • the vertex detection circuit 60 can input the vertex coordinates of the input primitive determined as the super primitive to the first primitive processing pipeline 6110, and the first primitive processing pipeline 6110 determines the coefficients of the edge equation fixed-point number format of the input primitive.
  • the rasterizer 30 may also input the vertex coordinates of the input primitive determined as a normal primitive to the second primitive processing pipeline 6120, and the second primitive processing pipeline 6120 determines the coefficients of the edge equation of the input primitive in fixed-point number format .
  • the graphics processing device processes the graphics primitives of the super-large primitive type and the normal primitive type through the first primitive processing pipeline 6110 and the second primitive processing pipeline 6120 respectively, which can improve the processing speed and processing speed of the primitives. performance.
  • the graphics processing apparatus provided by the embodiments of the present application has a faster processing speed.
  • the graphics processing apparatus provided by the embodiment of the present application processes the polygonal primitives without splitting the polygonal primitives into multiple triangular primitives, thereby improving the processing speed and reducing the computing load.
  • the rasterization circuit 62 may determine the fragments covered by the primitives according to the coefficients in the fixed-point format of the edge equations of the primitives. Because of the simple mathematical operations in the fixed-point format, the precision is high.
  • the rasterization circuit 62 provides the coefficients in the fixed-point format of the edge equation according to the primitive processing pipeline 61, which can improve the accuracy of determining the fragments covered by the primitives, avoid calculation errors, and improve the display effect or rendering effect of the primitives.
  • the fixed-point format of the edge equations of the primitives may be either 6-bit or 8-bit fixed-point format.
  • the outline of the primitive 7 corresponds to three straight lines, which are L1, L2, and L3 respectively.
  • the dashed arrows in FIG. 11 show the side of each straight line close to the interior of the primitive.
  • the rasterization circuit 62 can determine whether any fragment PYj satisfies the orientation of the ith straight line. The side inside the element.
  • the rasterization circuit 62 can traverse all the fragments in the display range, and determine the fragments that satisfy the preset positional relationship with all the straight lines as the target fragments, so as to determine all the fragments (also the target fragments) covered by the primitives. .
  • the rasterization circuit 62 can more accurately determine any slice in the display range based on the fragment covered by the coefficient primitive in the fixed-point format based on the edge equation of the primitive. Whether the element is in the element.
  • the rasterization circuit 62 After the rasterization circuit 62 determines the target fragment, it can send the coordinates of the target fragment to the fragment shader 31 .
  • the fragment shader 31 can perform shading processing on the target fragment.
  • the fragment shader 31 can also perform rendering processing on the target fragment.
  • the drawing layer unit 33 may fill in pixels in the layer to be drawn within the display range according to the result of coloring the target fragment.
  • the layer drawing unit 33 may also generate a layer, and the layer includes the target fragment after rendering processing or rendering processing.
  • a display controller and a display screen assembly may also be included in the graphics processing device. The display controller can display the target fragment output to the display screen component.
  • FIG. 12 shows the process of processing primitives by the graphics processing apparatus provided by the present application.
  • the graphics processing device includes two processes of rasterization and fragment coloring when processing primitives.
  • the prior art graphics processing apparatus needs to determine the vertices at which the primitive intersects with the guard band, and clip the primitive into one or more new primitives composed of these intersection point groups according to these vertices.
  • the primitives are not clipped before the rasterization processing, and no new primitive vertices are generated.
  • the graphics processing apparatus can use the first primitive processing pipeline 6110 and/or the second primitive processing pipeline 6120 to determine the coefficients of the edge equation of the primitive in the fixed-point format. Then, the rasterization circuit 62 determines the fragments covered by the primitives according to the coefficients in the fixed-point number format of each line equation, and completes the rasterization process.
  • the graphics processing apparatus can directly process the original primitives. If the graphics processing apparatus has a vertex transformation function, the original primitives are the primitives after the vertex transformation process.
  • the coordinate range of the original primitive vertex of the graphics processing device is not limited by the range of the screen or the protective band, and it does not need to re-determine the primitive by cutting, which can improve the processing speed of the primitive and has better graphics processing performance. .
  • the graphics processing device provided by the embodiment of the present application processes millions of primitives, compared with the existing graphics processing device (such as a GPU), it has a faster processing speed and a significant performance improvement, less power consumption.
  • the graphics processing apparatus provided by the embodiments of the present application can quickly process complex graphic elements, and the processing effect on complex graphic elements is also better than that of existing graphic processing apparatuses.
  • the embodiments of the present application provide a graphics processing method, and the graphics processing method can be executed by an electronic device.
  • FIG. 13 it is a schematic flowchart of a graphics processing method provided by an embodiment of the present application, and the method may be executed by the graphics processing apparatus shown in FIG. 3 . As shown in Figure 13, the flow of the method includes:
  • the electronic device can receive graphics processing instructions, and the graphics processing instructions include all vertex coordinates of the original primitives.
  • the graphics processing instruction may also include attribute data such as the color, normal vector, and texture coordinates of the primitive.
  • the graphics processing instruction received by the electronic device may be sent by an external device.
  • Input primitives can be lines, triangles, or polygons.
  • the vertex coordinates of the original primitives in this embodiment of the present application may be expressed in a floating-point number format.
  • the lines have a certain width.
  • the electronic device can decompose the primitive belonging to the line into two sides or four sides.
  • step S1303 it is judged whether to discard the primitive, if yes, step S1303 is executed next, if not, step S1304 is executed next.
  • the electronic device may adopt the process of the rasterizer 30 in the above-mentioned embodiment to determine whether the primitive is outside the display range. If it is determined that the graphic element is outside the display range, the graphic element can be determined to be discarded, and the next step is to perform step S1303;
  • step S1305 determines whether the graphic element is a normal graphic element, if yes, step S1305 is performed next, if not, step S1307 is performed next.
  • the electronic device may adopt the process of classifying the primitives within the display range by the rasterizer 30 in the above embodiment. If it is determined that the graphic element is a normal graphic element, the next step is to perform step S1305, and if it is determined that the graphic element is a super large graphic element, the next step is to perform step S1307.
  • S1305 Convert the coordinates of the primitive in the floating point format to the coordinates in the fixed point format.
  • the electronic device may convert the coordinates of the vertices of the primitives into fixed-point coordinates, wherein the coordinates of the vertices of the primitives are within the range of values that can be represented by the fixed-point format.
  • S1306 Determine the fixed-point format coefficients of the line equation corresponding to each edge of the primitive according to the coordinates of the primitive in the fixed-point format.
  • the electronic device may use the processing procedure of the second coefficient determination circuit 6122 in the above-mentioned embodiment to determine the fixed-point number format coefficients of the line equation to determine the fixed-point number format coefficients of the line equation corresponding to each edge of the primitive.
  • the electronic device may use the processing procedure of the first coefficient determination circuit 6111 in the above embodiment to determine the floating point format coefficients of the straight line equation to determine the floating point format coefficients of the straight line equation corresponding to each edge of the primitive.
  • the electronic device may determine the fixed-point format coefficients of the straight-line equation by using the first format conversion circuit 6112 in the above embodiment to convert the floating-point format coefficients of the straight-line equation into fixed-point format coefficients.
  • the electronic device may also determine the target fragment covered by the primitive according to the fixed-point number format coefficients of the straight line equation corresponding to each edge of the primitive, and then perform shading processing or rendering processing on the target fragment covered by the primitive.
  • the electronic device may also generate a layer, and the layer includes the target fragment after shading or rendering.
  • the electronic device may include a display controller and a display screen assembly. The display controller can display the target fragment output to the display screen component.
  • the embodiment of the present application also provides a graphics processing method, and the graphics processing method can be executed by an electronic device.
  • the graphics processing method may include the following steps:
  • S1401 Acquire a primitive to be processed, wherein the vertex coordinates of the primitive are in a floating-point format.
  • the equation coefficients may include an abscissa coefficient, an ordinate coefficient, and a constant term, wherein the abscissa coefficient is determined according to the difference between the ordinate value of the first vertex of the two vertices and the ordinate value of the second vertex of the two vertices ;
  • the longitudinal variable coefficient is determined according to the difference between the abscissa value of the second vertex and the abscissa value of the first vertex;
  • the constant term is determined according to the difference between the first value and the second value.
  • the first value is the product of the abscissa value of the first vertex and the ordinate value of the second vertex
  • the second value is the abscissa value of the second vertex.
  • the vertices of the primitives are sorted in a preset order, and the first vertex is in front of the second vertex.
  • the value of the abscissa or the value of the ordinate of at least one vertex of the primitive is greater than the preset value, and the value of the abscissa or the value of the ordinate of at least one vertex of the rectangular outline of the primitive is within the coordinate range of the screen. middle.
  • the electronic device determines the equation coefficients in the fixed-point format corresponding to the straight line where the two vertices are located according to the coordinates of the two vertices, it can determine the equation coefficients in the floating-point format corresponding to the straight line where the two vertices are located according to the coordinates of the two vertices.
  • the electronic device determines the scaling factor according to the equation coefficient in the floating-point number format and the target threshold value, where the target threshold value is the maximum value that can be represented in the fixed-point number format. Then, the equation coefficients in the fixed-point format are determined from the equation coefficients in the floating-point format and the scaling factor.
  • the abscissa value and the ordinate value of all vertices of the primitive are smaller than the preset value.
  • the electronic device determines, according to the coordinates of the two vertices, the equation coefficients in the fixed-point number format corresponding to the straight line where the two vertices are located, the coordinates of the two vertices can be converted into the fixed-point number format. Then, the electronic device determines the equation coefficients in the fixed-point format based on the coordinates of the two vertices converted into the fixed-point format.
  • S1403 Determine a target fragment on the screen according to equation coefficients corresponding to a plurality of straight lines, where the plurality of straight lines include a straight line where every two adjacent vertices in the primitive are located.
  • the electronic device determines, based on the equation corresponding to the ith straight line, whether the fragment satisfies the preset positional relationship corresponding to the ith straight line, wherein the preset positional relationship of the ith straight line is that the fragment is in the ith straight line.
  • the preset direction side of i straight lines, i ⁇ 1, 2, 3...N ⁇ , where N is the number of multiple straight lines. If the fragment satisfies the preset positional relationship corresponding to the plurality of straight lines, the electronic device determines the fragment as the target fragment.
  • the electronic device renders the target fragment.
  • the graphics processing methods shown in FIG. 13 and FIG. 14 are specific examples of processing primitives by the graphics processing apparatus shown in FIG. 3 .
  • Embodiments of the present application also provide a GPU 1500.
  • the GPU 1500 may include a rasterizer 1501 and a shader 1502 .
  • the rasterizer 1501 of the GPU 1500 may correspond to the rasterizer 30 of the image processing apparatus in FIG. 3 .
  • the shader 1502 may correspond to the fragment shader 31 of the image processing apparatus in FIG. 3 .
  • the rasterizer 1501 and the shader 1502 are similar to the components in the image processing apparatus corresponding to FIG. 3 , but are not limited thereto.
  • the GPU 1500 may include components other than similar components in the image processing apparatus corresponding to FIG. 3 , or may include additional similar components of the image processing apparatus corresponding to FIG. 3 .
  • the rasterizer 1501 may acquire the primitive to be processed, for any two adjacent vertices of the primitive. And according to the coordinates of the two vertices, the equation coefficients of the fixed-point number format corresponding to the straight lines where the two vertices are located are determined. Then, the target fragment in the screen is determined according to the equation coefficients corresponding to a plurality of straight lines, and the plurality of straight lines include a straight line where every two adjacent vertices of the primitives are located, wherein the vertex coordinates of the primitives are floating Point format.
  • Shader 1502 may shade the target fragment.
  • the value of the abscissa or the value of the ordinate of at least one vertex of the primitive is greater than a preset value, and the value of the maximum ordinate among all the vertices of the rectangular outline of the primitive is greater than the coordinate range of the screen. and the smallest vertical coordinate value in all vertices is less than the largest vertical coordinate value in the coordinate range, and the largest horizontal coordinate value in all the vertices is greater than the smallest horizontal coordinate value in the coordinate range, and all The smallest abscissa value in all the vertices is smaller than the largest abscissa value in the coordinate range.
  • the rasterizer 1501 determines the equation coefficient operation of the fixed-point number format corresponding to the straight line where the two vertices are located according to the coordinates of the two vertices, it can specifically determine the location where the two vertices are located according to the coordinates of the two vertices.
  • a scaling factor is determined according to the equation coefficients in the floating point number format and a target threshold value, wherein the target threshold value is the maximum value that can be represented by the fixed point number format.
  • the equation coefficients in the fixed-point format are determined according to the equation coefficients in the floating-point format and the scaling factor.
  • the abscissa value and the ordinate value of all vertices of the primitive are smaller than preset values, and the maximum ordinate value among all the vertices of the rectangular outline of the primitive is greater than the coordinates of the screen
  • the smallest ordinate value in the range, and the smallest ordinate value in all the vertices is less than the largest ordinate value in the coordinate range, and the largest abscissa value in all the vertices is greater than the smallest abscissa value in the coordinate range, and The smallest abscissa value in all the vertices is smaller than the largest abscissa value in the coordinate range.
  • the rasterizer 1501 may specifically convert the coordinates of the two vertices into a fixed-point number format when determining the equation coefficients in the fixed-point number format corresponding to the straight line where the two vertices are located according to the coordinates of the two vertices. The equation coefficients in the fixed-point format are then determined based on the coordinates of the two vertices converted to the fixed-point format.
  • the equation coefficients in the embodiments of the present application may include abscissa coefficients, ordinate coefficients, and constant terms, wherein the abscissa coefficients are based on the coefficient of the first vertex of the two vertices. It is determined by the difference between the ordinate value and the ordinate value of the second vertex of the two vertices.
  • the longitudinal variable coefficient is determined according to the difference between the abscissa value of the second vertex and the abscissa value of the first vertex.
  • the constant term is determined according to the difference between the first value and the second value, where the first value is the product of the abscissa value of the first vertex and the ordinate value of the second vertex, and the first value is the product of the abscissa value of the first vertex and the ordinate value of the second vertex.
  • the two values are the product of the abscissa value of the second vertex and the ordinate value of the first vertex.
  • the fixed points of the primitives are sorted according to a preset order, and the first vertex is in front of the second vertex.
  • the GPU 1500 may further include a memory 1503 .
  • the memory 1503 can store data required in the process of primitive processing, such as attribute data of the vertices of the primitive, and display range information.
  • the memory 1503 can also store data generated in the process of primitive processing, such as coefficients of edge equations of primitives, target fragment information, and the like.
  • the memory in the embodiments of the present application may be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory.
  • the non-volatile memory may be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically programmable Erase programmable read-only memory (electrically EPROM, EEPROM) or flash memory.
  • Volatile memory may be random access memory (RAM), which acts as an external cache.
  • RAM random access memory
  • SRAM static random access memory
  • DRAM dynamic random access memory
  • SDRAM synchronous DRAM
  • SDRAM double data rate synchronous dynamic random access memory
  • double data rate SDRAM, DDR SDRAM double data rate SDRAM, DDR SDRAM
  • enhanced synchronous dynamic random access memory enhanced synchronous dynamic random access memory (enhanced SDRAM, ESDRAM) and synchronous link dynamic random access memory (sync link DRAM, SLDRAM).
  • SRAM static random access memory
  • DRAM dynamic random access memory
  • SDRAM synchronous DRAM
  • SDRAM double data rate synchronous dynamic random access memory
  • double data rate SDRAM double data rate SDRAM
  • the GPU 1500 in this embodiment of the present application may be an integrated circuit chip, which has the capability of processing primitives.
  • GPU 1500 can include at least one first primitive processing pipeline that can determine fixed-point number format coefficients for edge equations of very large primitives.
  • GPU 1500 can include at least one second primitive processing pipeline that can determine fixed-point number format coefficients for edge equations of normal primitives.
  • GPU 1500 may also include at least one first primitive processing pipeline and at least one second primitive processing pipeline.
  • an embodiment of the present application further provides a chip.
  • the chip may include a GPU 1600 , an input/output circuit 1601 .
  • the input/output circuit 1601 and the GPU 1600 may be connected through a bus 1602 .
  • the input/output circuit 1601 in the chip can receive primitive processing instructions, or receive vertex coordinates and attribute data of primitives.
  • the GPU 1600 may be the image processing apparatus as shown in FIG. 3 , or may be the GPU 1500 as shown in FIG. 15 .
  • the GPU 1600 may perform the method described in the embodiments described in FIG. 13 and FIG. 14 on the primitive according to the vertex coordinates of the primitive.
  • the chip further includes a memory 1603, and the memory 1603 may be the memory 1503 in FIG. 15 .
  • the memory 1603 may store data required by the graphics processing process, or data generated during the graphics processing process. Memory 1603 may also store instructions. GPU 1600 can request required data from memory 1603 .
  • Electronic devices may be implemented as computers, laptops, handheld devices (eg cell phones, tablets), servers, virtual reality devices, augmented reality devices, mixed reality, wearable electronic devices with display screens, projection devices, holographic devices, etc. with display functional device.
  • the electronic device may include a GPU 1700 , a processor 1701 , and a display screen assembly 1702 .
  • the GPU 1700 may be any one of the graphics processing apparatuses provided in the foregoing embodiments or any one of the GPUs provided in the foregoing embodiments.
  • the GPU 1700, the processor 1701, and the display screen assembly 1702 can be connected through the bus 1703, so that the hardware in the electronic device can send and receive data.
  • the bus is represented by only a thick line in Figure 17, but it does not mean that there is only one bus or one type of bus.
  • the bus can be divided into an address bus, a data bus, a control bus, and the like.
  • the processor 1701 may be hardware for controlling the overall operation and function of the electronic device.
  • the processor 1701 may be a central processing unit (central processing unit, CPU) or a display controller.
  • the processor 1701 can control the display screen component 1702 to display the target fragment or layer provided by the GPU 1700 .
  • the display screen assembly 1702 may include various types of display screens, such as liquid crystal display (LCD), cathode ray tube (CRT) display, light-emitting diode (LED) display, organic light-emitting diode (OLED) display (organic LED, OLED) display, combined LCD-LED display, plasma display panel (PDP), digital light processing (digital light processing, DLP) display, or other types of devices that can display fragments or device.
  • LCD liquid crystal display
  • CRT cathode ray tube
  • LED light-emitting diode
  • OLED organic light-emitting diode
  • LCD-LED organic LED
  • PDP plasma display panel
  • DLP digital light processing
  • the electronic device may also include a memory 1704 that is connected to other hardware in the electronic device through a bus 1703 .
  • Memory 1704 may store various types of data that are processed within the electronic device.
  • the memory 1704 stores programs that the processor 1701 needs to execute.
  • Embodiments of the present application further provide a computer-readable storage medium for storing computer software instructions that need to be executed to execute the above-mentioned processor, which includes a program to be executed to execute the above-mentioned processor.
  • the embodiments of the present application may be provided as a method, a system, or a computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) having computer-usable program code embodied therein.
  • computer-usable storage media including, but not limited to, disk storage, CD-ROM, optical storage, etc.

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Abstract

本申请公开了一种图形处理方法、装置、设备及介质，提升处理图元速度，并且不需要对图元裁剪。所述方法包括：获取待处理的图元，其中，所述图元的顶点坐标为浮点数格式；针对所述图元任意相邻的两个顶点，根据所述两个顶点的坐标确定所述两个顶点所在直线对应的定点数格式的方程系数；根据多条直线对应的方程系数，确定屏幕中的目标片元，所述多条直线包括所述图元中每两个相邻的顶点所在的直线；对所述目标片元着色。

Description

一种图形处理方法、装置、设备及介质 技术领域
本申请涉及图形处理领域，尤其涉及一种图形处理方法、装置、设备及介质。
背景技术
图形处理器(graphics processing unit，GPU)广泛应用于游戏、视频以及建模等图形学相关领域，是专用的图像渲染硬件加速处理器。GPU固定硬件管道对图元进行光栅化的过程中，需要利用图元的坐标，确定图元轮廓中包括的片元。但由于GPU固定硬件管道出于设计复杂度、硬件成本以及计算精度等因素，现有GPU中的光栅化固定渲染管道所能直接计算处理的图元的坐标范围有限，例如超出10 9坐标范围的图元(便于描述，将此类图元称为超大图元)无法直接计算。针对超大图元，现有技术一提供一种3D裁剪器，用于对超大图元进行处理。
如图1所示，如果图元完全在屏幕外面(例如第一图元)，表明第一图元对屏幕所展示的渲染结果没有任何影响，不需要对第一图元进行处理，也即GPU对图元进行处理过程中，直接丢弃第一图元。如果图元完全在屏幕内部(例如第二图元)，因第二图元的坐标范围在屏幕范围内，GPU固定硬件管道可以利用图元的坐标，确定图元轮廓中包括的片元。如果图元的一部分在屏幕内部，另一部分在屏幕外部(例如第三图元)，此类图元为现有技术一GPU中的光栅化固定渲染管道无法直接计算的超大图元。通常由中央处理器(central processing unit，CPU)或者由GPU内部的着色器对第三图元进行剪裁处理。将第三图元△V0V1V2与屏幕有交集的部分(四边形V3V4V5V6)裁剪为两个三角形图元△V3V4V6和△V3V5V6，并作为两个新的图元。然后分别对这两个新的图元进行光栅化或片元着色处理。为了保障渲染效果，CPU还需要根据第三图元顶点的颜色、法向量以及纹理坐标等属性数据，采用插值的方法，计算出新的图元与屏幕的交点对应的属性数据。
现有技术一中若由CPU对超大图元进行处理，在将图元输入GPU之前，还需CPU对图元进行裁剪处理，加剧了CPU负载，使得CPU成为系统的性能瓶颈。另外，CPU对图元进行裁剪处理后，还需要重新计算第三图元与屏幕的交点的属性数据。若属性数据中的属性类型数量较多时，处理速度会大幅下降。并且因第三图元对应的新图元为多个图元，在对第三图元渲染时，GPU实际是对多个图元进行处理，增加了GPU的负载，造成GPU性能与功耗的损失。因此，现有技术一对超大图元的处理流程复杂，并且增大了计算资源的负载，效率低下。
发明内容
本申请提供一种图形处理方法、装置、设备及介质，用于提升处理图元速度，并且不需要对图元裁剪。
第一方面，本申请提供一种图形处理方法，可以由电子设备执行。其中，该方法具体包括以下步骤：电子设备获取待处理的图元，其中，所述图元的顶点坐标为浮点数格式；然后针对所述图元任意相邻的两个顶点，电子设备根据所述两个顶点的坐标确定所述两个顶点所在直线对应的定点数格式的方程系数。电子设备根据多条直线对应的方程系数确定 屏幕中的目标片元，所述多条直线包括所述图元中每两个相邻的顶点所在的直线，并对所述目标片元着色。
本申请实施例中，电子设备可以根据图元的浮点数格式的顶点坐标，确定图元任意相邻的两个顶点所在直线的定点数格式的方程系数。电子设备可以处理任意大小的图元，不需对图元进行裁剪处理。电子设备可以根据图元对应的多个直线的定点数格式的方程系数，确定在屏幕中图元所覆盖的目标片元，减少了图元在屏幕中所覆盖的片元的计算量，可以提高处理图元速度。并且定点数计算的精度高，电子设备利用定点数格式的直线系数确定目标片元，还可以提升确定图元在屏幕中所覆盖的片元的准确性，有助于提升图形处理质量。
一种可能的设计中，所述图元的至少一个顶点的横坐标数值或者纵坐标数值大于预设数值，所述图元的矩形轮廓全部顶点中最大纵坐标数值大于所述屏幕的坐标范围中最小纵坐标数值，且所述全部顶点中最小纵坐标数值小于所述坐标范围中最大纵坐标数值，且所述全部顶点中最大横坐标数值大于所述坐标范围中最小横坐标数值，且所述全部顶点中最小横坐标数值小于所述坐标范围中最大横坐标数值；电子设备在根据所述两个顶点的坐标确定所述两个顶点所在直线对应的定点数格式的方程系数操作时，可以根据所述两个顶点的坐标，确定所述两个顶点所在直线对应的浮点数格式的方程系数。并根据所述浮点数格式的方程系数以及目标阈值，确定缩放系数，其中，所述目标阈值为所述定点数格式能够表示的最大数值。然后根据所述浮点数格式的方程系数与所述缩放系数确定所述定点数格式的方程系数。
本申请实施例中，电子设备也可以确定超出预设范围的图元，也即超大图元进行处理。电子设备可以先通过浮点数计算确定图元的相邻两个顶点所在直线的浮点数格式的方程系数，由于浮点数格式可以表示的数值范围较大，电子设备也可以确定超大图元各边对应的直线浮点数格式的方程系数。然后电子设备根据各直线对应的缩放系数对各直线的浮点数格式系数进行缩放，获得各直线的定点数格式的方程系数。电子设备确定超大图元各边对应直线的定点数格式的系数的计算量少于对超大图元裁剪的计算量，并且可以缩短对超大图元处理时长，提升对超大图元的处理速度。
一种可能的设计中，所述图元的全部顶点的横坐标数值以及纵坐标数值均小于预设数值，所述图元的矩形轮廓全部顶点中最大纵坐标数值大于所述屏幕的坐标范围中最小纵坐标数值，且所述全部顶点中最小纵坐标数值小于所述坐标范围中最大纵坐标数值，且所述全部顶点中最大横坐标数值大于所述坐标范围中最小横坐标数值，且所述全部顶点中最小横坐标数值小于所述坐标范围中最大横坐标数值。电子设备在根据所述两个顶点的坐标确定所述两个顶点所在直线对应的定点数格式的方程系数操作时，可以将所述两个顶点的坐标转化为定点数格式。然后基于转化为定点数格式的所述两个顶点的坐标，确定所述定点数格式的方程系数。
本申请实施例中，因定点数计算的精度较高，电子设备对正常图元的处理时，可以先将图元的相邻两个顶点坐标转化为定点数格式。然后通过定点数计算确定所述两个顶点所在直线的方程系数，能够提升确定图元的各边所在直线的准确性，从而提高确定图元在屏幕中所覆盖片元的准确性，有助于提升图元处理的质量。
一种可能的设计中，所述方程系数包括横坐标系数、纵坐标系数和常数项，其中，所述横坐标系数为根据所述两个顶点中第一顶点的纵坐标数值与所述两个顶点中第二顶点 的纵坐标数值的差值确定的。所述纵向变量系数为根据所述第二顶点的横坐标数值与所述第一顶点的横坐标数值的差值确定的。所述常数项为根据第一数值与第二数值的差值确定的，所述第一数值为所述第一顶点的横坐标数值与所述第二顶点的纵坐标数值的乘积，所述第二数值为所述第二顶点的横坐标数值与所述第一顶点的纵坐标数值的乘积。其中，将所述图元的定点按照预设顺序进行排序，所述第一顶点在所述第二顶点前面。
本申请实施例中，对于超大图元和正常图元，图元相邻两个顶点的坐标与所述两个顶点所在直线的方程系数关系是相同的，简化图元处理过程，有利于实现。电子设备利用相邻的两个顶点的浮点数格式坐标，通过浮点数计算确定直线的方程系数。电子设备也可以利用相邻的两个顶点的定点数格式的坐标，通过定点数计算确定直线的方程系数。
一种可能的设计中，电子设备所述根据全部直线对应的方程系数，确定屏幕中的目标片元，针对所述屏幕中的任一片元，可以基于所述第i条直线对应的方程系数确定所述片元是否满足所述第i条直线对应的预设位置关系，其中，所述第i条直线的预设位置关系为所述片元在所述第i条直线的预设方向侧，所述i＝{1,2,3……N}，所述N为所述多条直线的数量。若所述片元满足所述多条直线分别对应的预设位置关系，则电子设备确定所述片元为所述目标片元。
本申请实施例中，电子设备可以根据直线的定点数格式的方程系数和屏幕中每个片元的坐标，通过定点数计算确定每个片元与图元各边所在直线的位置关系。因定点数计算的精度较高，电子设备可以准确地确定出每个片元与图元各边所在直线的位置关系，从而电子设备可以根据各直线对应的预设位置关系，准确地确定出图元在屏幕中所覆盖的片元。
一种可能的设计中，电子设备在根据所述两个顶点的坐标确定所述两个顶点所在直线对应的定点数格式的方程系数之前，若确定所述待处理图元的矩形轮廓全部坐标顶点中最小纵坐标数值大于所述屏幕的坐标范围中最大纵坐标数值，或者所述全部顶点中最大纵坐标数值小于所述坐标范围中最小纵坐标数值，或者所述全部顶点中最小横坐标数值大于所述坐标范围中最大横坐标数值，或者所述全部顶点中最大横坐标数值小于所述坐标范围中最小横坐标数值，则确定丢弃所述待处理的图元。
本申请实施例中，电子设备在确定图元的各边所在直线的定点数格式的方程系数之前，对图元进行过滤处理。电子设备若确定图元的任意一部分均不在屏幕的坐标范围中，则丢弃该图元，不对该图元进行处理。因图元不在屏幕的坐标范围中，图元不会在屏幕上显示，所以电子设备丢弃该图元，不影响屏幕上的显示效果。
一种可能的设计中，电子设备在根据所述两个顶点的坐标确定所述两个顶点所在直线对应的定点数格式的方程系数之前，可以根据预设数值、图元的全部顶点、图元的矩形轮廓全部顶点的坐标以及屏幕的坐标范围对所述图元分类。电子设备若确定所述图元的至少一个顶点的横坐标数值或者纵坐标数值大于预设数值，所述图元的矩形轮廓全部顶点中最大纵坐标数值大于所述屏幕的坐标范围中最小纵坐标数值，且所述全部顶点中最小纵坐标数值小于所述坐标范围中最大纵坐标数值，且所述全部顶点中最大横坐标数值大于所述坐标范围中最小横坐标数值，且所述全部顶点中最小横坐标数值小于所述坐标范围中最大横坐标数值，则确定所述图元为超大图元。电子设备若确定所述图元的全部顶点的横坐标数值以及纵坐标数值均小于预设数值，所述图元的矩形轮廓全部顶点中最大纵坐标数值大于所述屏幕的坐标范围中最小纵坐标数值，且所述全部顶点中最小纵坐标数值小于所述坐标范围中最大纵坐标数值，且所述全部顶点中最大横坐标数值大于所述坐标范围中最小横坐 标数值，且所述全部顶点中最小横坐标数值小于所述坐标范围中最大横坐标数值，则确定所述图元为正常图元。
本申请实施例中，电子设备可以对待处理的图元进行分类。电子设备若确定所述图元的矩形轮廓全部顶点中最大纵坐标数值大于所述屏幕的坐标范围中最小纵坐标数值，且所述全部顶点中最小纵坐标数值小于所述坐标范围中最大纵坐标数值，且所述全部顶点中最大横坐标数值大于所述坐标范围中最小横坐标数值，且所述全部顶点中最小横坐标数值小于所述坐标范围中最大横坐标数值，可以确定图元与屏幕有交集。电子设备可以根据图元全部顶点的坐标数值均小于预设阈值，确定该与屏幕有交集的图元是正常图元。反之，可以确定与屏幕有交集的图元是超大图元。电子设备可以对不同的类型的图元，采用不同的方式确定图元多条直线对应的定点数格式方程系数。
第二方面，本申请提供一种图形处理装置，包括光栅化器和着色器。光栅化器，用于获取待处理的图元，其中，所述图元的顶点坐标为浮点数格式；并针对所述图元任意相邻的两个顶点，根据所述两个顶点的坐标确定所述两个顶点所在直线对应的定点数格式的方程系数；以及根据多条直线对应的方程系数确定屏幕中的目标片元，所述多条直线包括所述图元中每两个相邻的顶点所在的直线。着色器，用于对所述目标片元着色。
一种可能的设计中，所述图元的至少一个顶点的横坐标数值或者纵坐标数值大于预设数值，所述图元的矩形轮廓全部顶点中最大纵坐标数值大于所述屏幕的坐标范围中最小纵坐标数值，且所述全部顶点中最小纵坐标数值小于所述坐标范围中最大纵坐标数值，且所述全部顶点中最大横坐标数值大于所述坐标范围中最小横坐标数值，且所述全部顶点中最小横坐标数值小于所述坐标范围中最大横坐标数值。所述光栅化器在根据所述两个顶点的坐标确定所述两个顶点所在直线对应的定点数格式的方程系数时，具体用于：根据所述两个顶点的坐标，确定所述两个顶点所在直线对应的浮点数格式的方程系数。并根据所述浮点数格式的方程系数以及目标阈值，确定缩放系数，其中，所述目标阈值为所述定点数格式能够表示的最大数值。然后根据所述浮点数格式的方程系数与所述缩放系数确定所述定点数格式的方程系数。
一种可能的设计中，所述图元的全部顶点的横坐标数值以及纵坐标数值均小于预设数值，所述图元的矩形轮廓全部顶点中最大纵坐标数值大于所述屏幕的坐标范围中最小纵坐标数值，且所述全部顶点中最小纵坐标数值小于所述坐标范围中最大纵坐标数值，且所述全部顶点中最大横坐标数值大于所述坐标范围中最小横坐标数值，且所述全部顶点中最小横坐标数值小于所述坐标范围中最大横坐标数值。所述光栅化器在根据所述两个顶点的坐标确定所述两个顶点所在直线对应的定点数格式的方程系数时，具体用于：将所述两个顶点的坐标转化为定点数格式。并基于转化为定点数格式的所述两个顶点的坐标，确定所述定点数格式的方程系数。
一种可能的设计中，所述方程系数包括横坐标系数、纵坐标系数和常数项，其中，所述横坐标系数为根据所述两个顶点中第一顶点的纵坐标数值与所述两个顶点中第二顶点的纵坐标数值的差值确定的。所述纵向变量系数为根据所述第二顶点的横坐标数值与所述第一顶点的横坐标数值的差值确定的。所述常数项为根据第一数值与第二数值的差值确定的，所述第一数值为所述第一顶点的横坐标数值与所述第二顶点的纵坐标数值的乘积，所述第二数值为所述第二顶点的横坐标数值与所述第一顶点的纵坐标数值的乘积。其中，将所述图元的定点按照预设顺序进行排序，所述第一顶点在所述第二顶点前面。
一种可能的实施方式中，所述光栅化器在根据多条直线对应的方程系数确定屏幕中的目标片元时，具体用于：针对所述屏幕中的任一片元，基于所述第i条直线对应的方程确定所述片元是否满足所述第i条直线对应的预设位置关系，其中，所述第i条直线的预设位置关系为所述片元在所述第i条直线的预设方向侧，所述i＝{1,2,3……N}，所述N为所述多条直线的数量。若所述片元满足所述多条直线分别对应的预设位置关系，则确定所述片元为所述目标片元。
一种可能的实施方式中，图形处理装置还包括存储器，用于图形处理所需的数据，或者图形处理过程中产生的数据。例如，存储器存储屏幕的坐标范围，图元的顶点坐标等数据。
第三方面，本申请实施例提供一种电子设备，包括处理器、显示屏幕组件以及如第二方面中任一项所述的图形处理装置。所述处理器用于将所述图形处装置得到的片元输出显示到所述显示屏幕组件上。
第四方面，本申请实施例提供一种芯片，芯片可以与电子设备中的显示屏幕组件耦合，用于执行本申请实施例第一方面及其第一方面任一可能设计的技术方案。本申请实施例中“耦合”是指两个部件彼此直接或间接地结合。具体的，该芯片可以获取待处理的图元，其中，所述图元的顶点坐标为浮点数格式；针对所述图元任意相邻的两个顶点，根据所述两个顶点的坐标确定所述两个顶点所在直线对应的定点数格式的方程系数；根据多条直线对应的方程系数，确定屏幕中的目标片元，所述多条直线包括所述图元中每两个相邻的顶点所在的直线；对所述目标片元着色。该芯片可以指示显示屏幕组件显示所述目标片元。
第五方面，本申请实施例提供一种电路系统。该电路系统可以是一个或多个芯片，比如片上系统。该电路系统包括：至少一个处理电路；所述至少一个处理电路用于获取待处理的图元，其中，所述图元的顶点坐标为浮点数格式。针对所述图元任意相邻的两个顶点，根据所述两个顶点的坐标确定所述两个顶点所在直线对应的定点数格式的方程系数。根据多条直线对应的方程系数，确定屏幕中的目标片元，所述多条直线包括所述图元中每两个相邻的顶点所在的直线。对所述目标片元着色。
第六方面，本申请实施例提供一种计算机可读存储介质，所述计算机可读存储介质包括计算机程序，当计算机程序在处理器上运行时，使得所述处理器执行本申请实施例第一方面及其第一方面任一可能设计的技术方案。
第七方面，本申请实施例的中一种计算机程序产品，当所述计算机程序产品在电子设备上运行时，使得所述电子设备执行本申请实施例第一方面及其第一方面任一可能设计的技术方案。
另外，第二方面至第七方面中任一种可能设计方式所带来的技术效果可参见方法部分相关中不同设计方式所带来的技术效果，此处不再赘述。
附图说明
图1为现有技术一中图形处理过程示意图；
图2为现有技术二中图形处理过程示意图；
图3为本申请实施例提供的一种图形处理装置；
图4为图元与显示范围的关系示意图；
图5为图元的矩形轮廓与显示范围的关系示意图；
图6为本申请实施例提供的一种光栅化器的结构示意图；
图7为本申请实施例提供的一种图元处理管道的结构示意图；
图8为本申请实施例提供的另一种图元处理管道的结构示意图；
图9为本申请实施例提供的图元顶点示意图；
图10为图元与判定范围的关系示意图；
图11为图元的轮廓所在直线的预设方向侧的示意图；
图12为本申请实施例提供的图形处理过程的示意图；
图13为本申请实施例提供的一种图形处理方法的示意流程图；
图14为本申请实施例提供的另一种图形处理方法的示意流程图；
图15为本申请实施例提供的一种图形处理器的结构示意图；
图16为本申请实施例提供的一种芯片；
图17为本申请实施例提供的一种电子设备。
具体实施方式
GPU广泛应用于游戏、视频以及建模等图形学相关领域，是专用的图像渲染硬件加速处理器。GPU通常可以对各种二维(2D)或三维(3D)模型进行处理。模型一般是由点、线或三角形等简单几何图元组成。对于其它复杂图元，GPU可以先将其转换成简单的几何图元，然后通过固定硬件管道对几何图元进行光栅化、片元着色等处理。由于GPU固定硬件管道出于设计复杂度、硬件成本以及计算精度等因素，难以直接处理超大图元。
现有技术一提供的3D裁剪方法将屏幕范围配置为处理图元的坐标范围，以屏幕范围为基准，确定输入图元与屏幕的位置关系。现有技术一提供的GPU中固定硬件管道可以直接处理完全处于屏幕范围内的图元。对于固定硬件管道无法直接处理的超大图元，也即图元的一部分在屏幕范围之内，且另一部分在屏幕范围之外的图元，现有技术一对超大图元进行裁剪。
例如，图1中的第三图元为图元的一部分在屏幕内部，且另一部分在屏幕外部，为超大图元。现有技术一对第三图元进行裁剪处理时，首先，通常由CPU将第三图元△V0V1V2的边与屏幕的四条边界进行检测。CPU基于直线方程计算，确定第三图元△V0V1V2与屏幕的交点分别为点V3、点V4、点V5以及点V6。
然后，CPU基于第三图元△V0V1V2与屏幕的交点构建新的图元，例如将△V3V4V6以及△V3V5V6确定为第三图元对应的新图元。CPU将第三图元对应的新图元输入至GPU中，因此GPU不对第三图元处理，而是对CPU确定出的第三图元对应的新图元△V3V4V6以及△V3V5V6进行光栅化或者片元着色处理。为了保障渲染效果，CPU还需要通过第三图元顶点的颜色、法向量以及纹理坐标等属性数据，采用插值的方法，计算出第三图元与屏幕的交点对应的属性数据。
由于现有技术一中，针对超大图元，在将超大图元输入GPU之前，还需CPU对超大图元进行裁剪处理。加剧了CPU负载，使得CPU成为系统的性能瓶颈。另外，CPU对超大图元进行裁剪处理后，还需要重新计算超大图元与屏幕的交点的属性数据。若属性数据中的属性类型数量较多时，处理速度会大幅下降。并且因超大图元对应的新图元可能为多个图元，在对超大图元渲染时，GPU实际是对多个图元进行处理，增加了GPU的负载，造成GPU性能与功耗的损失。
在实际应用场景中，输入GPU的图元中，超出屏幕范围的图元比例较高，也即超大图元的比例较高。现有技术一中对超大图元进行裁剪的频次增加，导致图元处理效率低下。为缓解该问题，现有技术二提供一种保护带裁剪法(guard band clipping，GBC)，用于对超大图元进行处理。现有技术二所提供的GPU中固定硬件管道可以直接对保护带内的图元进行直接处理，其中，保护带范围远大于屏幕范围。因而，现有技术二中提供的GPU可以直接处理更大坐标范围的图元。
现有技术二中首先以保护带范围为基准，确定输入图元与保护带的位置关系。如图2所示，如果图元完全在屏幕外面(例如第四图元)，表明第四图元对屏幕所展示的渲染结果没有任何影响，不需要对第四图元进行处理，也即GPU对图元进行处理过程中，直接丢弃第四图元。如果图元完全在保护带内部(例如第五图元)，因第五图元的坐标范围在保护带范围内，GPU固定硬件管道可以利用图元的坐标，确定图元轮廓中包括的片元。
现有技术二对于GPU固定硬件管道无法直接处理的超大图元，也即图元的一部分在保护带之内，且另一部分在保护带之外的图元，例如第六图元进行裁剪处理。
首先，GPU将第六图元△M0M1M2的边与保护带的四条边界进行检测。GPU确定第六图元△M0M1M2与屏幕的交点分别为点M3、点M4、点M5以及点M6。然后，GPU基于第六图元△M0M1M2与屏幕的交点构建新的图元，例如将△M3M4M6以及△M3M5M6确定为第六图元对应的新图元。GPU将第六图元对应的新图元输入至GPU中。
由此可见，现有技术二中GPU不对第六图元直接处理，而是对通过裁剪第六图元后生成的新图元△M3M4M6以及△M3M5M6进行光栅化或者片元着色处理。
相比于现有技术一，在现有技术二中由于保护带的范围远大于屏幕范围，固定硬件管道可以直接处理的图元的数量增多，从而减少了需要进行裁剪处理的超大图元的数量。但是现有技术二在对第六图元裁剪后的过程与现有技术一类似，GPU还需要通过第六图元顶点的颜色、法向量以及纹理坐标等属性数据，采用插值的方法，计算出第六图元与屏幕的交点对应的属性数据。因需要确定图元裁剪后产生的新的顶点的属性数据，会使GPU对图元处理的速度大幅下降。
现有技术二中引入上述保护带机制后，通常会使用GPU实现上述裁剪功能。若由GPU中的着色器实现裁剪功能，会使得GPU硬件管道与编程模型更加复杂。若由GPU中的专用的硬件电路实现，那裁剪与属性插值会引入较大的硬件开销。另外，类似第六图元的图元被GPU裁剪后，可能会生成多个图元，也增大了GPU后续光栅化等管道负载，造成GPU性能下降，功耗剧增。
可见，现有技术一和现有技术二中提供的GPU以及裁剪方法在对超大图元处理时，会造成GPU对图元处理速度下降。并且处理超大图元会导致GPU性能下降，增大功耗。
有鉴于此，本申请提供一种图形处理方法、装置、设备及介质，能够提升处理图元速度，提升处理超大图元的性能，也不需要对图元进行裁剪处理。图形处理装置中具有光栅化固定渲染管道功能的电路，能够处理任一图元，并且不对图元的坐标范围有任何限制。其中，方法和装置是基于同一技术构思的，由于方法及设备解决问题的原理相似，因此装置与方法的实施可以相互参见，重复之处不再赘述。以下，对本申请中的部分用语进行解释说明，以便于本领域技术人员理解。
1)数据的表达
通常，计算机中的数据可以用浮点数格式和定点数格式进行表达。例如，一个数值可 以由浮点数格式表达，也可以由定点数格式表达，这两种表达方式均不会影响数值。
2)浮点数格式
数值N的数学形式可记为M×R E，其中，M为尾数，R为底数，E为阶码。在计算机中可用尾数，底数以及阶码的组合来表示数值N。在一个计算机中，底数一般是固定的数值。
浮点数格式可以表示的数值范围较大，例如，IEEE FP32浮点数可以表示10 38量级的范围。但浮点数格式的数据的数学运算(如加法、减法、乘法、除法等运算)复杂。相比于定点数运算，浮点数运算的精度较低，并且是非线性的。
3)定点数格式
定点数格式中小数点的位置是固定的。小数点的位置可以设置在任一位置。通常定点数格式可以表示纯小数或纯整数。在一个计算机中存储数值时不存储小数点，存储定点数格式的数据时，小数点的位置是固定的。
定点数格式可以表示的数值范围较小，例如，32位的定点数格式，只能表示10 9量级的范围，远小于相同位宽的浮点数。但定点数格式的数学运算(如加法、减法、乘法、除法等运算)简单，精度高，在整个表示范围内精度是线性的。
4)直线的表达
一条直线可以采用多种方式进行描述。例如，利用直线方程来描述直线。从数学角度，直线方程有多种形式，如参数方程、点斜式方程、一般式方程。计算机中通常用一般式方程来描述直线，直线方程记为Ax+By+C＝0。其中，A，B，C为直线方程中的系数，其中A为横坐标系数，B为纵坐标系数，C为常数项。
计算机中通过记录直线方程中的系数，来记录直线。在图形处理领域中，图元的轮廓所在直线的直线方程也称为边方程，也是图元的任一两个相邻顶点所在直线的直线方程。
需要说明的是，本申请中所涉及的“和/或”，用于描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。字符“/”一般表示前后关联对象是一种“或”的关系。本申请中所涉及的多个，是指两个或两个以上。
另外，需要理解的是，在本申请的描述中，“第一”、“第二”等词汇，仅用于区分描述的目的，而不能理解为指示或暗示相对重要性，也不能理解为指示或暗示顺序。
下面将结合附图，对本申请实施例进行详细描述。本申请实施例提供一种图形处理装置，可以处理任意以浮点数格式表示顶点坐标的图元。例如，以FP32浮点数格式表示顶点坐标的图元。如图3所示，图形处理装置可以包括光栅化器30、片元着色器31。
图形处理装置还可以包括顶点着色器32。顶点着色器32可以在图元输入光栅化器30之前对图元进行顶点变换。顶点变换过程，通常是指根据图形处理配置参数，对图元进行平移、旋转、缩放等处理。其中，图形处理配置参数可以由用户触发的图形处理指令携带的。例如，图元处理配置参数中平移距离为x，图形处理装置根据平移距离和图元的坐标，确定平移后图元的坐标。图形处理装置还可以包括绘制图层单元33，绘制图层单元33可以生成包括着色后的片元的图层。
顶点着色器32可以将图元的顶点变换后的坐标输入光栅化器30。然后，光栅化器30可以对图元进行过滤。例如，光栅化器30可以对图元的全部顶点进行检测，确定各顶点是否在显示范围内。显示范围可以是与图形处理装置连接的显示装置的展示范围。例如，屏幕范围，或者投影范围。
本申请实施例中输入光栅化器30的图元可以是线、三角形。并且，输入光栅化器30的图元的顶点坐标为浮点数格式。
在实际应用场景中，依据输入的图元与显示范围的位置关系，光栅化器30可以将图元分为在显示范围之外的图元(如图4中示出的图元1)以及在显示范围之内的图元(如图4中示出的图元2、图元3、图元4)两种类型。其中，在显示范围之内的图元可以理解为图元的全部或部分在显示范围之内，如图4中示出的图元2的全部均在显示范围之内的，图元2属于在显示范围之内的图元类型。如图4中示出的图元3为部分在显示范围之内，图元3属于在显示范围之内的图元类型。
光栅化器30可以根据图元的全部顶点坐标，确定该图元的矩形轮廓的顶点坐标。光栅化器30将图元的矩形轮廓全部顶点的坐标与第一坐标阈值进行比较。第一坐标阈值可以是根据显示范围的顶点坐标确定的。第一坐标阈值可以包括第一横坐标阈值和第一纵坐标阈值。如图5所示，显示范围的顶点坐标分别为(x1，y1)、(x1，y2)、(x2，y1)、(x2，y2)，其中，x2>x1，y2>y1。第一横坐标阈值为x1，x2，第一纵坐标阈值为y1，y2。如图5中示出的图元以及该图元的矩形轮廓，将矩形轮廓的顶点坐标分别为(v1，w1)、(v1，w2)、(v2，w1)、(v2，w2)，其中，v2>v1，w2>w1。矩形轮廓的全部顶点中第i个顶点Pi的坐标可记为(mi，ni)。
光栅化器30可以将矩形轮廓的顶点的横坐标m i分别与x1，x2比较，将矩形轮廓的顶点的纵坐标n i分别与y1，y2比较。
光栅化器30将图元的矩形轮廓的坐标与第一坐标阈值进行比较。第一坐标阈值可以是根据显示范围的顶点坐标确定的。显示范围的顶点坐标分别为(x1，y1)、(x1，y2)、(x2，y1)、(x2，y2)，其中，x2>x1，y2>y1。若矩形轮廓的全部顶点中任一个顶点Pj(m j，n j)的横坐标mj≤x1，或者mj≥x2，或者任一个顶点Pj的纵坐标n j≤y1，或者n j≥y2，光栅化器30可以确定该图元为在显示范围之外的图元。例如，图5中示出的图元1，图元1的矩形轮廓任一个顶点Pj的纵坐标均满足n j≥y2，图元1为在显示范围之外的图元。因图元完全位于显示范围之外，对于显示范围内的显示情况没有任何影响，因而光栅化器30可以丢弃该图元。
光栅化器30若确定该图元不是在显示范围之外的图元，则可以确定该图元在显示范围之内。
为缩短图元的矩形轮廓的坐标与第一坐标阈值进行比较的过程，光栅化器30也可以通过确定图元的矩形轮廓的全部顶点中最大横坐标v2≤x1，或者最小横坐标v1≥x2，或者最大纵坐标v2≤y1，或者最小纵坐标v1≥y2，则光栅化器30可确定该图元为在显示范围之外的图元。反之，光栅化器30若确定图元的矩形轮廓的全部顶点中最大横坐标v2>x1、且最小横坐标v1<x2、且最大纵坐标v2>y1，且最小纵坐标v1<y2，可以确定该图元为在显示范围之内的图元。
本申请实施例中，图元的矩形轮廓包括了该图元的全部覆盖区域，因而该图元实际的覆盖区域是该图元矩形轮廓的子集。如果该图元的矩形轮廓与显示范围没有交集，则该图元的实际覆盖区域与显示范围也没有交集，可以确定该图元完全位于显示范围之外。光栅化器30不对该图元处理，对于显示范围的显示情况不会产生影响。因而光栅化器30可以丢弃在显示范围之外的图元。
一种可能的实施方式中，如图6光栅化器30可以包括依次连接的顶点检测电路60， 图元处理管道61，光栅化电路62。其中，顶点检测电路60的输入端也是光栅化器30的输入端。光栅化电路62的输出端也是光栅化器30的输出端。应理解的是，顶点检测电路60所实现的功能或能力，图元处理管道61所实现的功能或能力以及光栅化电路62所实现的功能或能力，也是光栅化器30可以实现的功能或能力。下面对顶点检测电路60，图元处理管道61，光栅化电路62可以实现的功能或能力进行介绍。
本申请实施例中的顶点检测电路60可以执行前述对图元进行过滤的过程，然后将位于显示范围之内的图元的浮点数格式的顶点坐标输入图元处理管道61。图元处理管道61可以对位于显示范围之内的任一图元进行图形处理，例如，确定图元的边方程。
本申请实施例提供的图元处理管道61可以为第一图元处理管道6110。如图7所示，第一图元处理管道6110可以包括依次连接的第一系数确定电路6111和第一格式转换电路6112。第一系数确定电路6111的输入端可以与顶点检测电路60的输出端连接，接收顶点检测电路60提供的图元的顶点坐标，其中，顶点坐标为浮点数格式。第一格式转换电路6112的输出端可以与光栅化电路62的输入端连接，将图元对应的直线方程(边方程)的定点数格式的系数输入至光栅化电路62中。
其中，第一系数确定电路6111也可以称作基于浮点数的直线方程计算电路。第一系数确定电路6111用于确定图元的任意两个相邻顶点所在直线的直线方程，也即用于确定组成图元轮廓的各直线的直线方程，其中，顶点坐标为浮点数格式。通常用一般式直线方程Ax+By+C＝0来描述各直线。以图元中相邻顶点Pi(m i，n i)和Pi+1(m i+1，n i+1)确定直线方程的系数可以采用如下公式：
A＝n i-n i+1
B＝m i+1-m i
C＝m in i+1-m i+1n i
由于图元的坐标任一个顶点Pj(m j，n j)为浮点数格式，确定出的直线方程的系数也为浮点数格式。浮点数格式可以表示数值的范围较大，因此本申请实施例可以直接处理任一图元，并且不需要对图元进行裁剪处理，也不需要设置保护带。换句话说本申请实施例提供的图元处理管道61对图元的坐标范围不作限制，能够处理顶点坐标数值很大的图元。
第一系数确定电路6111在确定直线方程的系数的过程中使用浮点数格式，可以防止计算结果溢出。并且在确定直线方程的系数过程中的数学运算(如加法、减法、乘法、除法等)运算过程中可以保持精度不受损。
一种可能的实施方式中，第一系数确定电路6111将图元的顶点浮点数格式FP32的坐标的乘法运算结果可以用浮点数格式FP64进行表示。
第一格式转换电路6112也可以称作归一化(Normalizer)电路。第一格式转换电路6112用于将第一系数确定电路6111输出的浮点数格式的直线方程系数转化为定点数格式。
由于定点数格式的位宽有限，定点数格式能够表示的数值范围较小。而第一系数确定电路6111输出的浮点数格式对应的数值可能会超出定点数格式能够表示的最大数值范围。本申请实施例提供一种浮点数格式转化为定点数格式的方法，应用于转化直线方程的系数的场景中。
首先介绍一下直线方程的一种特性。直线L可以用直线方程A 1x+B 1y+C 1＝0进行表示。同时，直线L也可以用直线方程
Figure PCTCN2020135755-appb-000001
对于一个方程等式，方程左侧各项均除以数值q，方程右侧各项也除以数值q，不改变方程两边的等于关系。由 于直线方程中等号的右侧为0，在除以数值q后仍为0。因此直线L可以用不同的直线方程进行表示。若方程系数同时除以数值q或者同时乘以数值q，不会改变直线L，仅改变了表示直线L的直线方程系数。
基于前述直线方程的特性，第一格式转换电路6112将第一系数确定电路6111输出的浮点数格式的系数转化为定点数格式时，可以对浮点数格式的系数进行缩放。将浮点数格式的系数缩放至定点数格式能够表示的数值范围内。然后用定点数格式记录缩放后的直线系数。
一个示例中，第一系数确定电路6111输出的直线方程Ax+By+C＝0的浮点数格式的系数A、B、C。第一格式转换电路6112可以根据浮点数格式的系数A、B、C以及定点数格式可以能够表示的数值范围(-N，N)中的最大数值N，确定缩放系数S。例如，S为直线方程浮点数格式的系数中的最大数值，也即
Figure PCTCN2020135755-appb-000002
在实际应用场景中，数值N可以根据定点数格式的位数确定，数值N可以是定点数格式能够表示的最大数值。
第一格式转换电路6112根据确定的缩放系数S对直线方程的浮点数格式的系数A、B、C进行缩放处理。缩放后的系数分别为
Figure PCTCN2020135755-appb-000003
缩放后的系数在定点数格式能够表示的数值范围内。第一格式转换电路6112用定点数格式记录直线方程缩放后的系数A′、B′、C′。
一个示例中，第一格式转换电路6112可以通过对直线方程的浮点数格式的系数的尾数，进行右移位的方式，确定直线方程的定点数格式的系数。
直线方程的浮点数格式的系数A、B、C，所对应的浮点数格式的指数可以分别记为E A、E B、E C，系数A、B、C所对应的浮点数格式的尾数可以分别记为M A、M B、M C。
由于浮点数格式的尾数部分可以用定点数格式表示。第一格式转换单元6112可以通过系数的尾数部分右移位的方式，实现对直线方程的系数进行缩放。定点数格式的系数A′＝M A＞＞(E max-E A)，B′＝M B＞＞(E max-E B)，C′＝M C＞＞(E max-E C)。其中，E max＝max(E A,E B,E C)。
本申请实施例中，图元处理管道61可以为第二图元处理管道6120。如图8所示，第二图元处理管道6120可以包括依次连接的第二格式转换电路6121和第二系数确定电路6122。第二格式转换电路6121的输入端可以与顶点检测电路60的输出端连接，接收顶点检测电路60提供的图元的顶点坐标，其中，顶点坐标为浮点数格式。第二系数确定电路6122的输出端可以与光栅化电路62的输入端连接，将图元对应的直线方程的定点数格式的系数输入至光栅化电路62中。
其中，第二格式转换电路6121也可以称作浮点数转定点数电路。第二格式转换电路6121用于将图元顶点的浮点数格式坐标转化为定点数格式坐标，其中图元顶点的坐标在定点数格式能够表示的数值范围内。
顶点检测电路60将图元任一个顶点Pj的浮点数格式坐标(m j，n j)输入第二格式转换电路6121，第二格式转换电路6121将任一个顶点Pj的浮点数格式坐标(m j，n j)转化为定点数格式坐标(m j’，n j’)。其中，m j和m j’均为同一个数值，仅是表示数值的形式不同。
第二系数确定电路6122也可以称作基于定点数的直线方程计算电路。第二系数确定电路6122用于确定图元的任意两个相邻顶点所在直线的直线方程，其中，顶点的坐标为第二格式转换电路6121输出的定点数格式坐标。以图元中相邻顶点Pi(m i’，n i’)和Pi+1(m i+1’，n i+1’)确定直线方程的系数可以采用如下公式：
A’＝n i’-n i+1’
B’＝m i+1’-m i’
C’＝m i’n i+1’-m’ i+1n i’
由于利用定点数格式的坐标确定直线方程的系数，确定直线方程系数的计算过程中，能够保持计算精度，并且计算速度更快。
另外，本申请实施例中确定图元的任一两个相邻顶点所在直线的直线方程过程中，图元中相邻顶点Pi和Pi+1是按照一定次序排序的。如图9所示，假设图元全部顶点数量为3，分别为P0、P1、P2。以点O为参考点，规定方向为x。以参考点O为射线的顶点，分别确定射线OP0、射线OP1、射线OP2与规定方向x的夹角，根据各射线的夹角确定图案的全部顶点的排序。射线OP0与规定方向的夹角为θ 0，射线OP1与规定方向的夹角为θ 1，射线OP2与规定方向的夹角为θ 2。
若各夹角的大小关系为θ 0<θ 1<θ 2，顶点排序可以与夹角的排序相同，顶点排序可为P0、P1、P2。或者说，以点O为参考点，按照逆时针方向对顶点进行排序。相邻顶点Pi和Pi+1可分别为P0和P1，也可以分别为P1和P2，还可以分别为P0和P2。那么确定直线方程的系数时，相邻顶点Pi(m i，n i)和Pi+1(m i+1，n i+1)确定直线方程的系数可以采用如下公式：
A＝n i-n i+1
B＝m i+1-m i
C＝m in i+1-m i+1n i
若夹角的大小关系为θ 0<θ 1<θ 2，顶点排序也可以与夹角的排序相反，顶点排序可为P2、P1、P0。换句话说，以点O为参考点，按照顺时针方向对顶点进行排序。相邻顶点Pi和Pi+1可分别为P2和P1，也可以分别为P1和P0，还可以分别为P2和P0。确定直线方程的系数时，也可以通过前述公式确定直线方程的系数。
一种可能的实施方式中，图形处理装置中的图元处理管道61为第一图元处理管道6110。第一图元处理管道6110是基于图元顶点的浮点数格式坐标，计算图元的轮廓的直线方程的浮点数格式的系数，然后通过缩放的方式，将直线方程的浮点数格式的系数转化为定点数格式的系数。浮点数格式可以表示的数值范围较大，能够确定任意大小的图元的轮廓的直线方程的系数，使得图像处理装置可以直接处理超大图元，并且不需要对超大图元进行裁剪操作以及确定属性数据的过程，从而可以加快对超大图元处理的速度。
另一种可能的实施方式中，图形处理装置中的图元处理管道61为第二图元处理管道6120。第二图元处理管道6120是将图元顶点的浮点数格式的坐标转化为定点数格式的坐标，然后计算图元的轮廓的直线方程的定点数格式的系数。由于本申请实施例中图形处理装置确定直线方程的定点数格式的系数过程中，使用定点数格式的坐标，定点数格式的数据运算速度较快，可以提升图元处理速度。
又一种可能的实施方式中，图形处理装置中的图元处理管道61包括至少一个第一图元处理管道6110和至少一个第二图元处理管道6120。
顶点检测电路60可以对输入的图元进行过滤。顶点检测电路60若确定输入的图元为在显示范围内的图元，还可以对在显示范围内的图元进行分类，将在显示范围内的图元分为正常图元和超大图元两种类型。
顶点检测电路60可以根据预先设置的判定范围，若图元的全部顶点全部在判定范围中，可以确定输入的图元为正常图元。若图元的全部顶点中至少一个顶点不在判定范围中，可光栅化器30可以确定输入的图元为超大图元。如图10所示，图元5和图元6的全部顶 点均不在判定范围内。图元5中有一个顶点在判定范围之外，图元5为超大图元。图元6的全部顶点均在判定范围之外，图元6为超大图元。
一个示例中，判定范围可以是根据浮点数格式的表示范围确定的。判定范围中的任意数值均在浮点数格式的表示范围内。
另一个示例中，判定范围可以是根据仿真实验结果确定的，或者根据经验值设定的，并且判定范围大于现有技术二中的保护带范围。
顶点检测电路60确定图元为显示范围之内的图元后，判断图元是否为超大图元。顶点检测电路60可以通过图元的全部顶点坐标与第二坐标阈值进行比较方式，确定图元的全部顶点是否在判定范围。其中，第二坐标阈值可以是根据判定范围的顶点坐标确定的。第二坐标阈值可以包括第二横坐标阈值和第二纵坐标阈值。例如，如图10所示，判定范围的顶点坐标分别为(r1，t1)、(r1，t2)、(r2，t1)、(r2，t2)，其中，r2>r1，t2>t1。第二横坐标阈值为r1、r2，第二纵坐标阈值为t1、t2。图元的全部顶点中第i个顶点Pi的坐标可记为(m i，n i)。顶点检测电路60可以将图元顶点的横坐标m i分别与r1、r2比较，将图元顶点的纵坐标n i分别与t1、t2比较。
若图元中的全部顶点中存在一个顶点的横坐标值小于r1，或者大于r2，可以确定该图元为在判定范围之外的图元，也是确定输入的图元为超大图元。或者，若图元中的全部顶点中存在一个顶点的纵坐标值小于t1，或者大于t2，顶点检测电路60也可以确定该图元为在判定范围之外的图元，也是超大图元。
顶点检测电路60在判断图元是否为超大图元时，若确定图元不是超大图元，则确定该图元为正常图元。
顶点检测电路60可以将确定为超大图元的输入图元的顶点坐标输入至第一图元处理管道6110，由第一图元处理管道6110确定该输入图元的边方程定点数格式的系数。光栅化器30也可以将确定为正常图元的输入图元的顶点坐标输入至第二图元处理管道6120，由第二图元处理管道6120确定该输入图元的边方程定点数格式的系数。
本申请实施例中，图形处理装置通过第一图元处理管道6110和第二图元处理管道6120分别对超大图元类型和正常图元类型的图元进行处理，可以提升图元处理速度和处理性能。尤其在处理大量图元的场景中，相比于现有技术，本申请实施例提供的图形处理装置具有较快的处理速度。并且，本申请实施例提供的图形处理装置对多边形状的图元进行处理，不需要将多边形图元拆分为多个三角形图元，从而可以提升处理速度，降低计算负载。
上述实施例提供的图形处理装置中，光栅化电路62可以根据图元的边方程的定点数格式的系数，确定图元覆盖的片元。由于定点数格式的数学运算简单，精度高。光栅化电路62根据图元处理管道61提供边方程的定点数格式的系数，可以提升确定图元覆盖的片元的准确率，避免计算误差，从而提升图元的显示效果或渲染效果。通常，图元的边方程的定点数格式可以是6比特或者8比特小数位的定点数格式。
一种可能的实施方式中，针对所述屏幕中的任一片元，光栅化电路62基于所述第i条直线对应的方程确定所述片元是否满足所述第i条直线对应的预设位置关系，其中，所述第i条直线的预设位置关系为所述片元在所述第i条直线的预设方向侧，所述i＝{1,2,3……N}，所述N为所述多条直线的数量。
光栅化电路62可以确定显示范围中的任一片元PYj(j＝{1,2,3……M})是否在每一直线靠近图元内部的一侧。如图11所示，图元7的轮廓对应3条直线，分别为L1、L2、L3。 图11中虚线箭头示出了各直线靠近图元内部的一侧。
光栅化电路62基于所述第i条直线对应的方程确定所述片元是否满足所述第i条直线对应的预设位置关系时，可以确定任一片元PYj是否满足在第i条直线的指向图元内部的一侧。
一个示例中，光栅化电路62可以根据第i条直线对应的方程Ai’x+Bi’y+Ci’＝0(Ai’、Bi’、Ci’为定点数格式)，片元PYj坐标(xj’，yj’)可以计算数值num＝A’xj’+B’yj’+C’，若num>0，可以确定片元PYj在第i条直线指向图元内部一侧，也是满足第i条直线对应的预设位置关系。
若片元PYj与全部直线均满足预设位置关系，则可以确定片元PYj在图元的内部。光栅化电路62可以通过遍历显示范围中的全部片元，将与全部直线均满足预设位置关系的片元确定为目标片元，可以实现确定图元覆盖的全部片元(也是目标片元)。
本申请实施例中，光栅化电路62基于图元的边方程定点数格式的系数图元覆盖的片元，因定点数格式的计算精度更高，可以更准确地确定显示范围中的任一个片元是否在图元中。
光栅化电路62确定目标片元后，可以将目标片元的坐标发送给片元着色器31。片元着色器31可以对目标片元进行着色处理。片元着色器31也可以对目标片元进行渲染处理。
绘制图层单元33可以根据目标片元着色后的结果，在显示范围内的待绘制图层中进行像素填充。绘制图层单元33还可以生成图层，图层中包括着色处理后或者渲染处理后的目标片元。图形处理装置中还可以包括显示控制器和显示屏幕组件。显示控制器可以将目标片元输出显示到显示屏幕组件上。
图12中示出了本申请提供的图形处理装置对图元的处理过程。图形处理装置对图元处理时包括光栅化、片元着色两个过程。现有技术图形处理装置在光栅化过程之前，需要确定图元与保护带相交的顶点，并根据这些顶点将图元裁剪为由这些相交点组构成的一个或多个新的图元。而本申请提供的图形处理装置对图元处理过程中，在光栅化处理之前不对图元进行裁剪处理，也不会产生新的图元顶点。区别于现有技术，本申请实施例提供的图形处理装置可以利用第一图元处理管道6110和/或第二图元处理管道6120，确定图元的边方程的定点数格式的系数。然后由光栅化电路62根据各直线方程的定点数格式的系数，确定图元所覆盖的片元，完成光栅化处理过程。
由此可见，本申请实施例提供的图形处理装置能够直接处理原始的图元，若图形处理装置具有顶点变换功能，则原始的图元为顶点变换过程后的图元。图形处理装置对原始的图元顶点的坐标范围不受屏幕或者保护带等范围的限制，也不需要通过裁剪的方式重新确定图元，可以提高图元的处理速度，具有较好的图形处理性能。
在测试环境下，本申请实施例提供的图形处理装置处理上百万图元的测试条件下，与现有图形处理装置(如GPU)相比，具有更快的处理速度，显著的性能提升，更少的功耗。并且，本申请实施例提供的图形处理装置能够快速的处理复杂图元，对复杂图元的处理效果也优于现有的图形处理装置。
基于上述实施例，本申请实施例提供一种图形处理方法，该图形处理方法可以由电子设备执行。参见图13为本申请实施例提供的图形处理方法的流程示意图，该方法可以由图3所示的图形处理装置执行。如图13所示，该方法的流程包括：
S1301，接收原始图元全部顶点坐标。
电子设备可以接收图形处理指令，图形处理指令中包含原始图元全部顶点坐标。图形处理指令中也可以包括图元的颜色、法向量、纹理坐标等属性数据。电子设备接收的图形处理指令可以是外部设备发送的。输入的图元可以是线、三角形或者多边形。本申请实施例中原始图元的顶点坐标可以为浮点数格式表示。
图形显示时，线具有一定宽度。在图元处理过程中，电子设备可以将属于线的图元，分解为两条边，或者四条边。
S1302，判断是否丢弃图元，若是，则下一步执行步骤S1303，若否，下一步执行步骤S1304。
电子设备可以采用上述实施例中光栅化器30确定图元是否在显示范围之外的过程。若确定图元在显示范围之外，可确定丢弃该图元，则下一步执行步骤S1303，若确定图元在显示范围之内，可确定不丢弃该图元，则下一步执行S1304。
S1303，丢弃图元。
S1304，判断图元是否为正常图元，若是，下一步执行步骤S1305，若否，下一步执行步骤S1307。
电子设备可以采用上述实施例中光栅化器30对在显示范围之内的图元分类的过程。若确定图元为正常图元，下一步执行步骤S1305，若确定图元为超大图元，下一步执行步骤S1307。
S1305，将图元的浮点数格式的坐标转化为定点数格式的坐标。
电子设备可以将图元顶点的浮点数格式坐标转化为定点数格式坐标，其中，图元顶点的坐标在定点数格式能够表示的数值范围内。
S1306，根据图元定点数格式的坐标，确定图元各边对应的直线方程的定点数格式系数。
电子设备可以采用上述实施例中第二系数确定电路6122确定直线方程的定点数格式系数的处理过程，确定图元各边对应的直线方程的定点数格式系数。
S1307，根据图元的浮点数格式的坐标，确定图元各边对应的直线方程的浮点数格式系数。
电子设备可以采用上述实施例中第一系数确定电路6111确定直线方程的浮点数格式系数的处理过程，确定图元各边对应的直线方程的浮点数格式系数。
S1308，针对每个边对应的直线方程，将直线方程的浮点数格式系数转化为定点数格式系数。
电子设备可以采用上述实施例中第一格式转换电路6112将直线方程的浮点数格式系数转化为定点数格式系数的处理过程，确定直线方程的定点数格式系数。
电子设备还可以根据图元的各边对应的直线方程的定点数格式系数，确定图元覆盖的目标片元，然后对图元覆盖的目标片元进行着色处理，或者渲染处理。
电子设备还可以生成图层，图层中包括着色处理后或者渲染处理后的目标片元。电子设备中可以包括显示控制器和显示屏幕组件。显示控制器可以将目标片元输出显示到显示屏幕组件上。
本申请实施例还提供一种图形处理方法，该图形处理方法可以由电子设备执行。如图14所示，图形处理方法可以包括如下步骤：
S1401，获取待处理的图元，其中，图元的顶点坐标为浮点数格式。
S1402，针对图元任意相邻的两个顶点，根据两个顶点的坐标确定两个顶点所在直线对应的定点数格式的方程系数。
方程系数可以包括横坐标系数、纵坐标系数和常数项，其中，横坐标系数为根据两个顶点中第一顶点的纵坐标数值与两个顶点中第二顶点的纵坐标数值的差值确定的；
纵向变量系数为根据第二顶点的横坐标数值与第一顶点的横坐标数值的差值确定的；
常数项为根据第一数值与第二数值的差值确定的，第一数值为第一顶点的横坐标数值与第二顶点的纵坐标数值的乘积，第二数值为第二顶点的横坐标数值与第一顶点的纵坐标数值的乘积；
其中，将图元的顶点照预设顺序进行排序，第一顶点在第二顶点前面。
一种可能的实施方式中，图元的至少一个顶点的横坐标数值或者纵坐标数值大于预设数值，且图元的矩形轮廓的至少一个顶点的横坐标数值或者纵坐标数值在屏幕的坐标范围中。电子设备根据两个顶点的坐标确定两个顶点所在直线对应的定点数格式的方程系数时，可以根据两个顶点的坐标，确定两个顶点所在直线对应的浮点数格式的方程系数。电子设备根据浮点数格式的方程系数以及目标阈值，确定缩放系数，其中，目标阈值为定点数格式能够表示的最大数值。然后，根据浮点数格式的方程系数与缩放系数确定定点数格式的方程系数。
一种可能的实施方式中，图元的全部顶点的横坐标数值以及纵坐标数值均小于预设数值。电子设备根据两个顶点的坐标确定两个顶点所在直线对应的定点数格式的方程系数时，可以将两个顶点的坐标转化为定点数格式。然后，电子设备基于转化为定点数格式的两个顶点的坐标，确定定点数格式的方程系数。
S1403，根据多条直线对应的方程系数确定屏幕中的目标片元，多条直线包括图元中每两个相邻的顶点所在的直线。
针对屏幕中的任一片元，电子设备基于第i条直线对应的方程确定片元是否满足第i条直线对应的预设位置关系，其中，第i条直线的预设位置关系为片元在第i条直线的预设方向侧，i＝{1,2,3……N}，N为多条直线的数量。若片元满足多条直线分别对应的预设位置关系，电子设备确定片元为目标片元。
S1404，对目标片元着色。
电子设备对目标片元进行着色处理。
图13和图14所示的图形处理方法为图3所示的图形处理装置对图元处理的具体示例。图13和图14所示的图形处理方法中未详尽描述的实现方式及其技术效果可以参见图3所示的图形处理装置中的相关描述。
本申请实施例还提供一种GPU1500。如图15所示，GPU1500可以包括光栅化器1501和着色器1502。
一个示例中，GPU1500的光栅化器1501可以与图3中图像处理装置的光栅化器30对应。着色器1502可以与图3中图像处理装置的片元着色器31对应。
另一个示例中，光栅化器1501和着色器1502与图3对应的图像处理装置中的组件类似，但不限于此。GPU1500可以包括除了图3对应的图像处理装置中的类似的组件之外的组件，或者可包括图3对应的图像处理装置的额外类似的组件。
本申请实施例中，光栅化器1501可以获取待处理的图元，针对所述图元任意相邻的两个顶点。并根据所述两个顶点的坐标确定所述两个顶点所在直线对应的定点数格式的方 程系数。然后根据多条直线对应的方程系数确定屏幕中的目标片元，所述多条直线包括所述图元中每两个相邻的顶点所在的直线，其中，所述图元的顶点坐标为浮点数格式。
着色器1502可以对所述目标片元着色。
一种可能的实施方式中，所述图元的至少一个顶点的横坐标数值或者纵坐标数值大于预设数值，所述图元的矩形轮廓全部顶点中最大纵坐标数值大于所述屏幕的坐标范围中最小纵坐标数值，且所述全部顶点中最小纵坐标数值小于所述坐标范围中最大纵坐标数值，且所述全部顶点中最大横坐标数值大于所述坐标范围中最小横坐标数值，且所述全部顶点中最小横坐标数值小于所述坐标范围中最大横坐标数值。
光栅化器1501在根据所述两个顶点的坐标确定所述两个顶点所在直线对应的定点数格式的方程系数操作时，具体可以根据所述两个顶点的坐标，确定所述两个顶点所在直线对应的浮点数格式的方程系数。根据所述浮点数格式的方程系数以及目标阈值，确定缩放系数，其中，所述目标阈值为所述定点数格式能够表示的最大数值。根据所述浮点数格式的方程系数与所述缩放系数确定所述定点数格式的方程系数。
另一种可能的实施方式中，所述图元的全部顶点的横坐标数值以及纵坐标数值均小于预设数值，所述图元的矩形轮廓全部顶点中最大纵坐标数值大于所述屏幕的坐标范围中最小纵坐标数值，且所述全部顶点中最小纵坐标数值小于所述坐标范围中最大纵坐标数值，且所述全部顶点中最大横坐标数值大于所述坐标范围中最小横坐标数值，且所述全部顶点中最小横坐标数值小于所述坐标范围中最大横坐标数值。
光栅化器1501在根据所述两个顶点的坐标确定所述两个顶点所在直线对应的定点数格式的方程系数操作时，具体可以将所述两个顶点的坐标转化为定点数格式。然后基于转化为定点数格式的所述两个顶点的坐标，确定所述定点数格式的方程系数。
一种可能的实施方式中，本申请实施例中的所述方程系数可以包括横坐标系数、纵坐标系数和常数项，其中，所述横坐标系数为根据所述两个顶点中第一顶点的纵坐标数值与所述两个顶点中第二顶点的纵坐标数值的差值确定的。所述纵向变量系数为根据所述第二顶点的横坐标数值与所述第一顶点的横坐标数值的差值确定的。所述常数项为根据第一数值与第二数值的差值确定的，所述第一数值为所述第一顶点的横坐标数值与所述第二顶点的纵坐标数值的乘积，所述第二数值为所述第二顶点的横坐标数值与所述第一顶点的纵坐标数值的乘积。其中，将所述图元的定点按照预设顺序进行排序，所述第一顶点在所述第二顶点前面。
光栅化器1501在根据多条直线对应的方程系数确定屏幕中的目标片元操作时，具体可以针对所述屏幕中的任一片元，基于所述第i条直线对应的方程系数确定所述片元是否满足所述第i条直线对应的预设位置关系，其中，所述第i条直线的预设位置关系为所述片元在所述第i条直线的预设方向侧，所述i＝{1,2,3……N}，所述N为所述多条直线的数量。若所述片元满足所述多条直线分别对应的预设位置关系，则确定所述片元为所述目标片元。
一种可能的实施方式中，GPU1500还可以包括存储器1503。存储器1503可以存储图元处理过程中所需数据，如图元的顶点的属性数据，显示范围信息。存储器1503也可以存储图元处理过程中产生的数据，如图元的边方程的系数，目标片元信息等。本申请实施例中的存储器可以是易失性存储器或非易失性存储器，或可包括易失性和非易失性存储器两者。其中，非易失性存储器可以是只读存储器(read-only memory，ROM)、可编程只读 存储器(programmable ROM，PROM)、可擦除可编程只读存储器(erasable PROM，EPROM)、电可擦除可编程只读存储器(electrically EPROM，EEPROM)或闪存。易失性存储器可以是随机存取存储器(random access memory，RAM)，其用作外部高速缓存。通过示例性但不是限制性说明，许多形式的RAM可用，例如静态随机存取存储器(static RAM，SRAM)、动态随机存取存储器(dynamic RAM，DRAM)、同步动态随机存取存储器(synchronous DRAM，SDRAM)、双倍数据速率同步动态随机存取存储器(double data rate SDRAM，DDR SDRAM)、增强型同步动态随机存取存储器(enhanced SDRAM，ESDRAM)和同步连接动态随机存取存储器(sync link DRAM，SLDRAM)。应注意，本文描述的存储器旨在包括但不限于这些和任意其它适合类型的存储器。
一种可能的实施方式中，本申请实施例中GPU1500可以是一种集成电路芯片，具有图元处理能力。GPU1500可以包括至少一个第一图元处理管道，第一图元处理管道可以确定超大图元的边方程的定点数格式系数。GPU1500可以包括至少一个第二图元处理管道，第二图元处理管道可以确定正常图元的边方程的定点数格式系数。GPU1500也可以包括至少一个第一图元处理管道和至少一个第二图元处理管道。
相应地，本申请实施例还提供一种芯片。如图16所示，芯片可以包括GPU1600，输入/输出电路1601。输入/输出电路1601与GPU1600可以通过总线1602连接。芯片中的输入/输出电路1601可以接收图元处理指令，或者接收图元的顶点坐标和属性数据。GPU1600可以是如图3中的图像处理装置，也可以是如图15中的GPU1500。GPU1600可以根据图元的顶点坐标对图元进行如图13、图14所述的实施例描述的方法。
一种可能的实施方式中，芯片还包括存储器1603，存储器1603可以是如图15中的存储器1503。存储器1603可以存储图形处理过程所需要的数据，或者图形处理过程中产生的数据。存储器1603也可以存储指令。GPU1600可以从存储器1603请求所需的数据。
本申请实施例还提供一种电子设备。电子设备可以实施为计算机、便携式电脑、手持设备(例如手机，平板电脑)、服务器、虚拟现实设备、增强现实设备、混合现实、具有显示屏幕的可穿戴电子设备、投影设备、全息设备等具有显示功能的设备。
如图17所示，电子设备可以包括GPU1700，处理器1701，显示屏幕组件1702。其中，GPU1700可以是上述实施例中提供的任意一种图形处理装置或者上述实施例中提供的任意一种GPU。GPU1700，处理器1701，显示屏幕组件1702之间可以通过总线1703连接，使得电子设备内的硬件之间发送和接收数据。总线在图17中仅用一条粗线表示，但并不表示仅有一根总线或一种类型的总线。所述总线可以分为地址总线、数据总线、控制总线等。
处理器1701可以是用于控制电子设备的整体操作和功能的硬件。例如，处理器1701可以是中央处理器(central processing unit，CPU)，也可以是显示控制器。处理器1701可以控制显示屏幕组件1702对GPU1700提供的目标片元或者图层进行显示。
显示屏幕组件1702可以包括各类型的显示屏幕，如液晶显示器(liquid crystal display，LCD)、阴极射线管(cathode ray tube，CRT)显示器、发光二极管(light-emitting diode，LED)显示器、有机发光二极管(organic LED，OLED)显示器、组合式LCD-LED显示器、等离子体显示面板(plasma display panel，PDP)、数字光处理(digital light processing，DLP)显示器、或者可以显示片元的其他类型的设备或装置。
电子设备还可以包括存储器1704，与电子设备中的其它硬件通过总线1703连接。存 储器1704可以存储电子设备内被处理的各种类型的数据。例如，存储器1704存储处理器1701所需执行的程序。
本申请实施例还提供了一种计算机可读存储介质，用于存储为执行上述处理器所需执行的计算机软件指令，其包含用于执行上述处理器所需执行的程序。
本领域内的技术人员应明白，本申请的实施例可提供为方法、系统、或计算机程序产品。因此，本申请可采用完全硬件实施例、完全软件实施例、或结合软件和硬件方面的实施例的形式。而且，本申请可采用在一个或多个其中包含有计算机可用程序代码的计算机可用存储介质(包括但不限于磁盘存储器、CD-ROM、光学存储器等)上实施的计算机程序产品的形式。

Claims (13)

  1. 一种图形处理方法，其特征在于，所述方法包括：
    获取待处理的图元，其中，所述图元的顶点坐标为浮点数格式；
    针对所述图元任意相邻的两个顶点，根据所述两个顶点的坐标确定所述两个顶点所在直线对应的定点数格式的方程系数；
    根据多条直线对应的方程系数，确定屏幕中的目标片元，所述多条直线包括所述图元中每两个相邻的顶点所在的直线；
    对所述目标片元着色。
  2. 如权利要求1所述的方法，其特征在于，所述图元的至少一个顶点的横坐标数值或者纵坐标数值大于预设数值，所述图元的矩形轮廓全部顶点中最大纵坐标数值大于所述屏幕的坐标范围中最小纵坐标数值，且所述全部顶点中最小纵坐标数值小于所述坐标范围中最大纵坐标数值，且所述全部顶点中最大横坐标数值大于所述坐标范围中最小横坐标数值，且所述全部顶点中最小横坐标数值小于所述坐标范围中最大横坐标数值；
    所述根据所述两个顶点的坐标确定所述两个顶点所在直线对应的定点数格式的方程系数，包括：
    根据所述两个顶点的坐标，确定所述两个顶点所在直线对应的浮点数格式的方程系数；
    根据所述浮点数格式的方程系数以及目标阈值，确定缩放系数，其中，所述目标阈值为所述定点数格式能够表示的最大数值；
    根据所述浮点数格式的方程系数与所述缩放系数确定所述定点数格式的方程系数。
  3. 如权利要求1所述的方法，其特征在于，所述图元的全部顶点的横坐标数值以及纵坐标数值均小于预设数值，所述图元的矩形轮廓全部顶点中最大纵坐标数值大于所述屏幕的坐标范围中最小纵坐标数值，且所述全部顶点中最小纵坐标数值小于所述坐标范围中最大纵坐标数值，且所述全部顶点中最大横坐标数值大于所述坐标范围中最小横坐标数值，且所述全部顶点中最小横坐标数值小于所述坐标范围中最大横坐标数值；
    所述根据所述两个顶点的坐标确定所述两个顶点所在直线对应的定点数格式的方程系数，包括：
    将所述两个顶点的坐标转化为定点数格式；
    基于转化为定点数格式的所述两个顶点的坐标，确定所述定点数格式的方程系数。
  4. 如权利要求1-3中任一所述的方法，其特征在于，所述方程系数包括横坐标系数、纵坐标系数和常数项，其中，所述横坐标系数为根据所述两个顶点中第一顶点的纵坐标数值与所述两个顶点中第二顶点的纵坐标数值的差值确定的；
    所述纵向变量系数为根据所述第二顶点的横坐标数值与所述第一顶点的横坐标数值的差值确定的；
    所述常数项为根据第一数值与第二数值的差值确定的，所述第一数值为所述第一顶点的横坐标数值与所述第二顶点的纵坐标数值的乘积，所述第二数值为所述第二顶点的横坐标数值与所述第一顶点的纵坐标数值的乘积；
    其中，将所述图元的定点按照预设顺序进行排序，所述第一顶点在所述第二顶点前面。
  5. 如权利要求1-4中任一所述的方法，其特征在于，所述根据全部直线对应的方程系数，确定屏幕中的目标片元，包括：
    针对所述屏幕中的任一片元，基于所述第i条直线对应的方程系数确定所述片元是否满足所述第i条直线对应的预设位置关系，其中，所述第i条直线的预设位置关系为所述片元在所述第i条直线的预设方向侧，所述i＝{1,2,3……N}，所述N为所述多条直线的数量；
    若所述片元满足所述多条直线分别对应的预设位置关系，则确定所述片元为所述目标片元。
  6. 一种图形处理装置，其特征在于，所述装置包括：
    光栅化器，用于获取待处理的图元，其中，所述图元的顶点坐标为浮点数格式；并针对所述图元任意相邻的两个顶点，根据所述两个顶点的坐标确定所述两个顶点所在直线对应的定点数格式的方程系数；以及根据多条直线对应的方程系数确定屏幕中的目标片元，所述多条直线包括所述图元中每两个相邻的顶点所在的直线；
    着色器，用于对所述目标片元着色。
  7. 如权利要求6所述的装置，其特征在于，所述图元的至少一个顶点的横坐标数值或者纵坐标数值大于预设数值，所述图元的矩形轮廓全部顶点中最大纵坐标数值大于所述屏幕的坐标范围中最小纵坐标数值，且所述全部顶点中最小纵坐标数值小于所述坐标范围中最大纵坐标数值，且所述全部顶点中最大横坐标数值大于所述坐标范围中最小横坐标数值，且所述全部顶点中最小横坐标数值小于所述坐标范围中最大横坐标数值；
    所述光栅化器在根据所述两个顶点的坐标确定所述两个顶点所在直线对应的定点数格式的方程系数时，具体用于：
    根据所述两个顶点的坐标，确定所述两个顶点所在直线对应的浮点数格式的方程系数；
    根据所述浮点数格式的方程系数以及目标阈值，确定缩放系数，其中，所述目标阈值为所述定点数格式能够表示的最大数值；
    根据所述浮点数格式的方程系数与所述缩放系数确定所述定点数格式的方程系数。
  8. 如权利要求6所述的装置，其特征在于，所述图元的全部顶点的横坐标数值以及纵坐标数值均小于预设数值，所述图元的矩形轮廓全部顶点中最大纵坐标数值大于所述屏幕的坐标范围中最小纵坐标数值，且所述全部顶点中最小纵坐标数值小于所述坐标范围中最大纵坐标数值，且所述全部顶点中最大横坐标数值大于所述坐标范围中最小横坐标数值，且所述全部顶点中最小横坐标数值小于所述坐标范围中最大横坐标数值；
    所述光栅化器在根据所述两个顶点的坐标确定所述两个顶点所在直线对应的定点数格式的方程系数时，具体用于：
    将所述两个顶点的坐标转化为定点数格式；
    基于转化为定点数格式的所述两个顶点的坐标，确定所述定点数格式的方程系数。
  9. 如权利要求6-8中任一项所述的装置，其特征在于，所述方程系数包括横坐标系数、纵坐标系数和常数项，其中，所述横坐标系数为根据所述两个顶点中第一顶点的纵坐标数值与所述两个顶点中第二顶点的纵坐标数值的差值确定的；
    所述纵向变量系数为根据所述第二顶点的横坐标数值与所述第一顶点的横坐标数值的差值确定的；
    所述常数项为根据第一数值与第二数值的差值确定的，所述第一数值为所述第一顶点的横坐标数值与所述第二顶点的纵坐标数值的乘积，所述第二数值为所述第二顶点的横坐标数值与所述第一顶点的纵坐标数值的乘积；
    其中，将所述图元的定点按照预设顺序进行排序，所述第一顶点在所述第二顶点前面。
  10. 如权利要求6-9中任一项所述的装置，其特征在于，所述光栅化器在根据多条直线对应的方程系数确定屏幕中的目标片元时，具体用于：
    针对所述屏幕中的任一片元，基于所述第i条直线对应的方程确定所述片元是否满足所述第i条直线对应的预设位置关系，其中，所述第i条直线的预设位置关系为所述片元在所述第i条直线的预设方向侧，所述i＝{1,2,3……N}，所述N为所述多条直线的数量；
    若所述片元满足所述多条直线分别对应的预设位置关系，则确定所述片元为所述目标片元。
  11. 一种电子设备，其特征在于，包括处理器、显示屏幕组件以及如权利要求6-10中任一项所述的图形处理装置；
    所述处理器用于将所述图形处装置得到的所述目标片元输出显示到所述显示屏幕组件上。
  12. 一种计算机可读存储介质，其特征在于，所述计算机可读存储介质包括计算机指令，当所述计算机指令在计算机上运行时，使得计算机执行如权利要求1至5任一项所述的方法。
  13. 一种芯片，其特征在于，包括图形处理器，当所述图形处理器执行指令时，所述图形处理器执行如权利要求1至5任一项所述的方法。
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Citations (3)

* Cited by examiner, † Cited by third party
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US20030076331A1 (en) * 2001-10-23 2003-04-24 Deering Michael F. Relative coordinates for triangle rendering
CN101292271A (zh) * 2005-08-24 2008-10-22 高通股份有限公司 具有重要内插的图形引擎
CN110544290A (zh) * 2019-09-06 2019-12-06 广东省城乡规划设计研究院 数据渲染方法及装置

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030076331A1 (en) * 2001-10-23 2003-04-24 Deering Michael F. Relative coordinates for triangle rendering
CN101292271A (zh) * 2005-08-24 2008-10-22 高通股份有限公司 具有重要内插的图形引擎
CN110544290A (zh) * 2019-09-06 2019-12-06 广东省城乡规划设计研究院 数据渲染方法及装置

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