WO2022120722A1

WO2022120722A1 - Resource scheduling apparatus, digital signal processor and movable platform

Info

Publication number: WO2022120722A1
Application number: PCT/CN2020/135284
Authority: WO
Inventors: 韩志; 张英; 吴穹蔗
Original assignee: 深圳市大疆创新科技有限公司
Priority date: 2020-12-10
Filing date: 2020-12-10
Publication date: 2022-06-16

Abstract

Embodiments of the present invention provide a resource scheduling apparatus, a digital signal processor, and a movable platform. The apparatus comprises: a target read-write request receiving unit, configured to receive a target read-write request sent by a target vector calculating unit; a scheduling unit, configured to determine, according to addressing unit information corresponding to the target read-write request, an addressing unit corresponding to the target vector calculating unit; and a target read-write request sending unit, configured to send the target read-write request to the addressing unit corresponding to the target vector calculating unit. By using the present invention, in the case that the target read-write request sent by the target vector calculating unit is received, an available addressing unit can be automatically allocated to the target vector calculating unit according to the addressing unit information corresponding to the target read-write request, such that the operation difficulty of a technician can be reduced, and the operation efficiency can be improved.

Description

Resource scheduling device, digital signal processor and movable platform

technical field

The present invention relates to the technical field of data processing, and in particular, to a resource scheduling device, a digital signal processor and a movable platform.

Background technique

In the related art, a digital signal processor (Digital Signal Processing, DSP) can be used to process the digital signal. The DSP includes multiple vector calculation units, multiple addressing units and vector memory. During the calculation process of the vector computing unit, the vector memory needs to be read and written to store the data to be stored in the specified storage location of the vector memory, or to read the data to be used in the calculation process from the specified storage location of the vector memory. The vector calculation unit needs to find the specified storage location of the vector memory through the target addressing unit.

In practical applications, programmers need to be very clear about the underlying technology that the vector computing unit reads and writes the vector memory through the addressing unit, so that when the vector memory needs to be read and written, they can manually write codes to implement vector computing. The process in which the unit allocates the target addressing unit among multiple addressing units, so that the vector computing unit can successfully complete the read and write operations to the vector memory through the target addressing unit.

Since the programmer in the related art needs to use the programming knowledge to manually implement the process of allocating the target addressing unit by the vector calculation unit, the operation difficulty is increased and the operation efficiency is reduced.

SUMMARY OF THE INVENTION

Embodiments of the present invention provide a resource scheduling device, a digital signal processor, and a movable platform, which are used to automatically assign an addressing unit to a failure vector calculation unit, thereby reducing operation difficulty and improving operation efficiency.

In a first aspect, an embodiment of the present invention provides a resource scheduling apparatus, and the method includes:

a target read/write request receiving unit, configured to receive the target read/write request sent by the target vector computing unit;

a scheduling unit, configured to determine the addressing unit corresponding to the target vector computing unit according to the addressing unit information corresponding to the target read/write request; and

A target read/write request sending unit, configured to send the target read/write request to an addressing unit corresponding to the target vector calculation unit.

Optionally, the resource scheduling apparatus further includes:

A configuration information sending unit, configured to send configuration information corresponding to the target read/write request to a target configuration information receiving unit corresponding to the target vector calculation unit.

Optionally, the scheduling unit is used for:

According to the addressing unit information corresponding to the target read/write request, determine the number of first addressing units that need to be used to execute the target read/write request;

determining a second addressing unit whose working state is idle among the plurality of addressing units;

If the number of the second addressing units is greater than or equal to the number of the first addressing units, determining the first addressing for executing the target read/write request in the second addressing unit unit, so as to perform read and write operations of the vector memory through the first addressing unit and the configuration information.

Optionally, the target read/write request includes a read interface and/or a write interface indicating that the target vector computing unit needs to be used,

The read interface corresponds to a third addressing unit, and the write interface corresponds to a fourth addressing unit.

Optionally, the target read/write request includes indication information of preset digits corresponding to all read interfaces and/or all write interfaces of the target vector computing unit;

When the highest 1-bit data of the indication information is 1, the indication information is used to instruct to enable the corresponding read interface or write interface; when the highest 1 of the indication information is 0, the indication information is used for Indicates that the corresponding read interface or write interface is not enabled.

Optionally, the scheduling unit is used for:

The number of first addressing units to be used for executing the target read/write request is determined according to the read interface and/or write interface to be used indicated in the target read/write request.

Optionally, the scheduling unit includes a plurality of indication registers, and the indication register is connected to a read interface and/or a write interface of a vector calculation unit of the plurality of vector calculation units and one of the plurality of addressing units. The addressing unit is associated, and when the first value is stored in any indication register, the any indication register indicates that the addressing unit associated with the any indication register is assigned to the address unit associated with the any indication register read interface and/or write interface.

Optionally, the scheduling unit is used for:

determining, in the second addressing unit, a first addressing unit corresponding to the read interface and/or the write interface indicated in the target read/write request to be used;

determining, among the plurality of indication registers, a target indication register that is simultaneously associated with the read interface and/or write interface indicated in the target read/write request and/or the write interface and the corresponding first addressing unit;

The first value is stored in the target indication register.

Optionally, the resource scheduling apparatus further includes:

a virtual addressing unit, used for allocating the virtual addressing unit to the The read interface and/or write interface to be used as indicated in the target read and write request.

Optionally, the target read/write request also carries a target vector computing unit identifier and a target configuration information receiving unit identifier; the scheduling unit includes a plurality of indication registers, the indication register and one of the plurality of configuration information receiving units. The configuration information receiving unit is associated with one addressing unit in the plurality of addressing units, and when the second value is stored in any indication register, the any indication register indicates the address associated with the any indication register. The configuration information receiving unit is assigned to the addressing unit associated with any of the indication registers.

Optionally, the scheduling unit is used for:

According to the target configuration information receiving unit identifier to be used indicated in the target read/write request, determine the target configuration information receiving unit among the plurality of configuration information receiving units;

determining, among the plurality of indication registers, a target indication register associated with the first addressing unit and the target configuration information receiving unit at the same time;

The second value is stored in the target indication register.

Optionally, the resource scheduling apparatus further includes:

a read-write request receiving unit, used for receiving read-write requests sent by multiple vector computing units respectively;

an arbitration unit, configured to determine the target vector calculation unit among the plurality of vector calculation units according to the respective priorities of the vector calculation units, and the respective priorities of the vector calculation units are different; The target read and write request sent by the target vector calculation unit.

Optionally, the arbitration unit is configured to:

When the read/write request response period arrives, the target vector calculation unit with the highest priority is determined among the plurality of vector calculation units.

Optionally, the arbitration unit is further configured to:

When the next read/write request response cycle of the read/write request response cycle arrives, a vector calculation unit to be adjusted whose priority is lower than the target vector calculation unit is determined in the plurality of vector calculation units, and the to-be-adjusted vector calculation unit is determined in the plurality of vector calculation units. Adjust the priority of the vector calculation unit to increase the preset level;

The priority corresponding to the target vector calculation unit is adjusted to the lowest value.

Optionally, the resource scheduling apparatus further includes:

a timestamp unit, configured to record the reception time of receiving the read/write request sent by any vector calculation unit when the read/write request receiving unit receives the read/write request sent by any vector calculation unit;

The arbitration unit is used to determine the candidate read/write request with the earliest corresponding reception time among the multiple read/write requests when the read/write request response period arrives; if the number of the candidate read/write requests is 1, then The candidate read/write request is determined as the target read/write request; if the number of the candidate read/write requests is greater than 1, the target vector computation unit with the highest priority is determined in the vector computation unit that sends the candidate read/write request, Determine the target read/write request sent by the target vector calculation unit.

In a second aspect, an embodiment of the present invention provides a digital signal processor, where the digital signal processor includes a target vector calculation unit, a plurality of addressing units, a vector memory, and the resource scheduling apparatus provided in the first aspect of the embodiment of the present invention, in:

the target vector calculation unit, configured to send a target read and write request to the resource scheduling device;

The resource scheduling device is configured to select an addressing unit corresponding to the target vector computing unit from the multiple addressing units according to the target read/write request;

The addressing unit corresponding to the target vector calculation unit is configured to perform read/write operations on the vector memory according to the target read/write request.

Optionally, the target vector calculation unit includes a vector arithmetic logic operation unit, a floating point operation unit, an accelerator unit or a peripheral interface.

In a third aspect, an embodiment of the present invention provides a movable platform, which includes the digital signal processor provided in the second aspect of the embodiment of the present invention.

By adopting the present invention, the resource scheduling device can automatically allocate available addressing to the target vector computing unit according to the addressing unit information corresponding to the target reading and writing request in the case of receiving the target reading and writing request sent by the target vector computing unit. unit, so that the target vector calculation unit can read and write operations to the vector memory through the allocated addressing unit to complete the calculation task. By adopting the present invention, it is no longer necessary to manually assign addressing units to the target vector calculation unit, and these processes can be completed automatically, thereby reducing the operation difficulty of technicians and improving the operation efficiency.

Description of drawings

In order to illustrate the technical solutions in the embodiments of the present invention more clearly, the following briefly introduces the accompanying drawings used in the description of the embodiments. Obviously, the drawings in the following description are some embodiments of the present invention. For those of ordinary skill in the art, other drawings can also be obtained from these drawings without creative effort.

1 is a schematic structural diagram of a digital signal processor according to an embodiment of the present invention;

FIG. 2 is a schematic structural diagram of a resource scheduling apparatus according to an embodiment of the present invention;

3 is a schematic diagram of a read-write request provided by an embodiment of the present invention;

FIG. 4 is a schematic structural diagram of a scheduling unit according to an embodiment of the present invention;

5 is a schematic diagram of a read interface bridge provided by an embodiment of the present invention;

6 is a schematic diagram of a write interface bridge according to an embodiment of the present invention;

7 is a schematic diagram of an indication register for connecting a vector computing unit and an addressing unit according to an embodiment of the present invention;

8 is a schematic diagram of an indication register for connecting a configuration information receiving unit and an addressing unit according to an embodiment of the present invention;

9 is a schematic structural diagram of another digital signal processor provided by an embodiment of the present invention;

FIG. 10 is a schematic structural diagram of another resource scheduling apparatus provided by an embodiment of the present invention;

FIG. 11 is a schematic flowchart of a flow sequence of a resource scheduling method according to an embodiment of the present invention;

FIG. 12 is a schematic structural diagram of another resource scheduling apparatus provided by an embodiment of the present invention;

13 is a schematic diagram of determining the sequential processing order of read and write requests in a fixed priority mode according to an embodiment of the present invention;

14 is a schematic diagram of determining the sequential processing order of read and write requests in a polling mode provided by an embodiment of the present invention;

15 is a schematic diagram of determining the sequential processing order of read and write requests in a time priority mode according to an embodiment of the present invention;

FIG. 16 is a schematic structural diagram of a movable platform according to an embodiment of the present invention.

Detailed ways

In order to make the purposes, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments These are some embodiments of the present invention, but not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

The terms used in the embodiments of the present invention are only for the purpose of describing specific embodiments, and are not intended to limit the present invention. The singular forms "a," "the," and "the" as used in the embodiments of the present invention and the appended claims are intended to include the plural forms as well, unless the context clearly dictates otherwise, "a plurality" Generally at least two are included.

Depending on the context, the words "if", "if" as used herein may be interpreted as "at" or "when" or "in response to determining" or "in response to detecting". Similarly, the phrases "if determined" or "if detected (the stated condition or event)" can be interpreted as "when determined" or "in response to determining" or "when detected (the stated condition or event)," depending on the context )" or "in response to detection (a stated condition or event)".

In addition, the sequence of steps in the following method embodiments is only an example, and is not strictly limited.

FIG. 1 is a digital signal processor provided by an embodiment of the present invention. As shown in FIG. 1, the digital signal processor 10 may include a target vector calculation unit 11, a plurality of addressing units 12, a vector memory 13, and an implementation of the present invention. The resource scheduling device 14 provided by the example. in:

The target vector calculation unit 11 is configured to send a target read/write request to the resource scheduling apparatus 14 .

The resource scheduling device 14 is configured to select the addressing unit 12 corresponding to the target vector computing unit 11 from the multiple addressing units 12 according to the target read/write request.

The addressing unit 12 corresponding to the target vector calculation unit 11 is configured to perform read and write operations on the vector memory 13 according to the target read and write request.

In practical applications, the digital signal processor 10 (Digital Signal Process, DSP) may also include a scalar processor (Reduced Instruction Set Computing, RISC). The scalar processor may send instructions to any of a plurality of vector computing units included in the digital signal processor 10 . After the any vector computing unit receives the instruction, in order to execute the instruction to realize the required function of the instruction, it is often necessary to perform read and write operations on the data in the vector memory 13, so that any vector computing unit can parse the instruction into a read and write request. , the read and write operations to the vector memory 13 are completed based on the read and write requests. The target vector calculation unit 11 in this embodiment of the present invention may be any vector calculation unit with read and write requirements among the multiple vector calculation units included in the digital signal processor 10 .

Optionally, the above-mentioned target vector calculation unit 11 may include a vector arithmetic logic operation unit, a floating point operation unit (VFPU), an accelerator unit or a peripheral interface (MCL). The vector arithmetic logic unit may be a vector arithmetic logic unit (Vector Arithmetic Logic Unit, VALU) or a VEU. The accelerator unit can be Multi Media Extensions (MMX) or ACC.

The target vector calculation unit 11 may generate a target read/write request based on the instruction sent by the scalar processor, and then send the target read/write request to the resource scheduling apparatus 14 . The resource scheduling device 14 can select the addressing unit 12 corresponding to the target vector calculation unit 11 from the multiple addressing units 12 (AGU) according to the target read and write request and assign it to the target vector calculation unit 11, so that the target vector calculation unit 11 can pass through the target vector calculation unit 11. The assigned addressing unit 12 performs read and write operations on the vector memory 13 .

FIG. 2 is a schematic structural diagram of a resource scheduling device 14 provided by an embodiment of the present invention. As shown in FIG. 2 , the device includes a target read/write request receiving unit 21, a scheduling unit 22, and a target read/write request sending unit 23. in:

The target read/write request receiving unit 21 is configured to receive the target read/write request sent by the target vector calculation unit 11 .

The scheduling unit 22 is configured to determine the addressing unit 12 corresponding to the target vector calculation unit 11 according to the addressing unit 12 information corresponding to the target read/write request.

The target read/write request sending unit 23 is configured to send the target read/write request to the addressing unit 12 corresponding to the target vector calculation unit 11 .

In practical application, the target read/write request unit in the resource scheduling device 14 (Slave Resource Scheduler, SRS) can receive the target read/write request sent by the target vector calculation unit 11, and the target read/write request carries a target vector calculation unit 11 for indicating the target read/write request. The addressing unit 12 information of the number of addressing units 12 to be used, the scheduling unit 22 can determine the addressing unit 12 that can be used by the target vector calculation unit 11 among the multiple addressing units 12 according to the addressing unit 12 information carried in the target read and write request Addressing unit 12. After determining the addressing unit 12 corresponding to the target vector calculation unit 11, the target read/write request sending unit 23 may send the target read/write request to the addressing unit 12 corresponding to the target vector calculation unit 11, so that the target vector calculation unit 11 can The vector memory 13 is read and written through the addressing unit 12 corresponding to the target vector calculation unit 11 .

Optionally, the resource scheduling apparatus 14 may further include: a configuration information sending unit 24 configured to send configuration information corresponding to the target read/write request to the target configuration information receiving unit 25 corresponding to the target vector calculation unit 11 .

It should be noted that the resource scheduling apparatus 14 may further include multiple configuration information receiving units 25 (config), and the target configuration information receiving unit 25 may be selected from the multiple configuration information receiving units 25 and assigned to the target vector calculating unit 11 . If the vector memory 13 needs to be read and written correctly, in addition to the relevant information carried in the target read and write requests, configuration information corresponding to the target read and write requests is also required to jointly control and complete the read and write operations to the vector memory 13 . Therefore, after the scalar processor sends the configuration information corresponding to the target read/write request, the configuration information corresponding to the target read/write request may be stored in the target configuration information receiving unit 25 through the configuration information sending unit 24 .

Optionally, the above-mentioned scheduling unit 22 can be used to determine the number of first addressing units that need to be used to execute the target read/write request according to the addressing unit 12 information corresponding to the target read/write request; among the multiple addressing units 12 Determine the second addressing unit whose working state is idle; if the number of the second addressing units is greater than or equal to the number of the first addressing units, determine the first addressing unit for executing the target read/write request in the second addressing unit The addressing unit is used to perform read and write operations of the vector memory 13 through the first addressing unit and configuration information.

In practical applications, the working state of each addressing unit 12 can be recorded. When any addressing unit 12 is assigned to any vector computing unit and the any vector computing unit has not finished using the any addressing unit 12, Any addressing unit 12 is marked as busy. When any addressing unit 12 is not assigned to any vector computing unit, or any addressing unit 12 is assigned to any vector computing unit and any vector computing unit has used up any addressing unit 12 , any addressing unit 12 is marked as free. Based on this, a second addressing unit whose working state is idle may be determined among the plurality of addressing units 12 .

In addition, the number of first addressing units to be used to execute the target read/write request can be determined according to the addressing unit 12 information corresponding to the target read/write request, if the number of the second addressing units is greater than or equal to the number of the first addressing units number, the first addressing unit for executing the target read/write request may be determined in the second addressing unit.

The resource scheduling device 14 may also include a virtual addressing unit (Virtual AGU). If the number of the second addressing units is smaller than the number of the first addressing units, the virtual addressing unit may be temporarily determined as the addressing unit 12 for executing the target read/write request.

The following will introduce the process of determining the number of first addressing units to be used for executing the target read/write request according to the target read/write request.

The target vector calculation unit 11 may include multiple read interfaces and multiple write interfaces, and can configure whether to use these interfaces, and then add the configuration information to the target read/write request. Optionally, the target read/write request may include a read interface and/or a write interface indicating that the target vector calculation unit 11 needs to be used, and each read interface uses one addressing unit 12 and each write interface uses one addressing unit 12 . It can be understood that, if an interface in the target vector calculation unit 11 is used in the configuration, a corresponding addressing unit 12 needs to be allocated to serve the interface in the process of using the interface.

Based on this, the scheduling unit 22 may be configured to: determine the number of first addressing units to be used to execute the target read/write request according to the read interface and/or write interface to be used indicated in the target read/write request.

Optionally, the target read/write request may include indication information of preset bits corresponding to all read interfaces and/or all write interfaces of the target vector computing unit 11 respectively. When the highest 1-bit data of the indication information is 1, the indication information is used to indicate to enable the corresponding read interface or write interface; when the highest 1 of the indication information is the data is 0, the indication information is used to indicate that the corresponding read interface is not enabled or write interface.

As shown in Figure 3, it is a schematic diagram of the structure of the target read and write request. Bits 0-3 in the target read and write request are time stamps, which are used to indicate the receiving time when the target read and write request is received. Bits 4-7 in the target read/write request are the master id, and a corresponding identifier can be assigned to each vector computing unit in advance, and the identifier of the target vector unit that sends the target read/write request is recorded in the master id.

Bits 8-12 and 13-17 in the target read and write request are write ID0 and write ID1 in turn. The upper 1 bit in write ID0 and write ID1 indicates whether the corresponding write interface is enabled, for example, when the upper 1 bit data is 1 , indicating that the corresponding write interface is enabled. When the highest 1 is the data of 0, it indicates that the corresponding write interface is not enabled. The lower 4 bits in write ID0 and write ID1 indicate the identity of the target configuration information receiving unit 25 that needs to be used.

Bits 18-22, 23-27, and 28-32 in the target read and write request are read ID0, read ID1, and read ID2 in turn. The high 1 in read ID0, read ID1 and read ID2 indicates whether the corresponding read interface is enabled. For example, when the high 1-bit data is 1, it indicates that the corresponding read interface is enabled, and when the highest 1 is the data 0, it indicates that the corresponding read interface is not enabled. Enable the corresponding read interface. The lower 4 bits in read ID0, read ID1 and read ID2 indicate the identification of the target configuration information receiving unit 25 that needs to be used.

In the example of FIG. 3 , it is assumed that the maximum number of read interfaces supported at the same time is 3, and the maximum number of write interfaces is 2. Of course, the structure of the target read/write request is not limited to the example in FIG. 3, and the structure of the target read/write request can be changed according to actual needs to meet the actual needs.

Based on the above description, it can be known that the number of first addressing units to be used to execute the target read/write request may be determined based on the target read/write request.

As shown in FIG. 4 , it is a schematic structural diagram of a scheduling unit 22 provided by an embodiment of the present invention. For the scheduling unit 22, each unit is arranged around the resource pool. In the process of allocating the addressing unit 12, as shown in Figures 5 and 6, the agu allocation unit can complete the actual allocation process through the read interface bridge and the write interface bridge. The read interface bridge is used to connect the read interface and the search interface of the vector calculation unit. The read interface of the addressing unit 12, correspondingly, the write interface bridge is used to connect the write interface of the vector calculation unit and the write interface of the addressing unit 12.

For example, it is assumed that the target read and write request needs to use two read interfaces and one write interface, the two read interfaces are read1 and read2, and the one write interface is write0. The second square in a column of squares corresponding to read2 on the left side of Figure 5 is filled, and the second square in a column of squares corresponding to agu1 on the right side of Figure 5 is filled, indicating that read2 is connected to RB1 of the read interface bridge, And agu1 is also connected to the RB1 of the read interface bridge, and the connection to the same RB is represented as an assignment relationship, that is, agu1 is assigned to the read2. The first square in a column of squares corresponding to read1 on the left side of Figure 5 is filled, and the first square in the medical square corresponding to agu0 on the right side of Figure 5 is filled, indicating that read1 is connected to RB0 of the read interface bridge, And agu0 is also connected to RB0 of the read interface bridge, that is to say, agu0 is assigned to the read1. The allocation process of the write interface is similar to the allocation process of the read interface. For the allocation process of the write interface, reference may be made to the process of the read interface in conjunction with FIG. 6 , which will not be repeated here.

It should be noted that, in the process of allocating the read interface, the free agu can be searched in the order of agu0 to agu5. In the process of allocating the write interface, the free agu can be searched in the order of agu5 to agu0, which can ensure that the same agu will not be assigned to the read interface and the write interface at the same time. When the agu allocation unit completes the allocation of the agu, it will adjust the working state of the agu currently allocated in the resource pool to the occupied state, until the vector computing unit occupying the agu updates the working state of the agu to idle after the use of the agu until.

After the agu allocation unit completes the allocation of the agu, the allocation result can be written into the indication register in the connection state. Optionally, the indication register is associated with a read interface and/or a write interface of a vector computation unit in a plurality of vector computation units and an addressing unit 12 in a plurality of addressing units 12, when any indication register in the When storing the first value, any indication register indicates that the addressing unit 12 associated with any indication register is assigned to the read interface and/or the write interface associated with any indication register.

As shown in Figure 7, it is a schematic diagram of the structure of the indicating register. In FIG. 7 , there are multiple rows of horizontal lines and multiple columns of vertical lines, and the intersection between the horizontal lines and the vertical lines is represented by a black dot, and the black dot is a register. m0-m5 represents the vector computing unit 0-5, r0-r2 represents the read interface 0-2 of a certain vector computing unit, and w0-w1 represents the writing interface 0-1 of a certain vector computing unit. Taking the intersection of the horizontal line in the first row and the vertical line in the first column as an example, the horizontal line in the first row is represented as m0r0, which means the read interface 0 of the vector computing unit 0, and the vertical line in the first column represents agu0. If If the first value is stored in the register represented by their intersection, it means that the agu0 is allocated to the read interface 0 of the vector calculation unit 0 . The first numerical value may be 1, for example.

Optionally, after the agu allocation unit completes the allocation of the agu, the first address corresponding to the read interface and/or the write interface indicated in the target read-write request and/or the write interface can be determined in the second addressing unit according to the allocation result. Addressing unit; determine a target indication register that is simultaneously associated with the read interface and/or write interface indicated in the target read and write request and the corresponding first addressing unit; in the target indication register The first value is stored.

Through the above operations, the actually allocated agu can be connected to the read interface or the write interface of a certain vector computing unit.

Optionally, the resource scheduling apparatus 14 provided in this embodiment of the present invention may further include: a virtual addressing unit, configured to allocate a corresponding first read interface and/or a write interface indicated in the target read/write request to be used. Before addressing the unit, the virtual addressing unit is allocated to the read interface and/or the write interface to be used indicated in the target read and write request.

In practical applications, after the resource scheduling device 14 receives the read/write request, it can immediately connect the read interface and the write interface of the vector computing unit that sends the read/write request to the virtual addressing unit, until the vector computing unit that sends the read/write request is the virtual addressing unit. When the actual addressing unit 12 is allocated by the read interface or the write interface, the actually allocated addressing unit 12 is then connected to the read interface or the write interface of the vector computing unit that sends the read and write request.

The scheduling unit 22 can allocate the target configuration information receiving unit 25 (config) in addition to the addressing unit 12 . Optionally, the target read and write request also carries the target vector calculation unit 11 identification and the target configuration information receiving unit 25 identification; the scheduling unit 22 includes a plurality of indication registers, and a configuration information in the indication register and a plurality of configuration information receiving units 25 is included. The receiving unit 25 is associated with one addressing unit 12 in the plurality of addressing units 12. When any indication register stores the second value, any indication register indicates the configuration information receiving unit 25 associated with any indication register. is assigned to the addressing unit 12 associated with any of the indication registers.

As shown in Figure 8, it is assumed that there are config0-9 and agu0-5, which is similar to the way of assigning addressing unit 12. Taking config0 represented by the horizontal line in the first row and agu0 represented by the vertical line in the first column as an example, if they are If the second value is stored in the register represented by the intersection, it means that the config0 is assigned to the agu0. The second numerical value may be 1, for example.

It should be noted that the number of configs in practical applications can be set according to actual requirements. In an optional implementation manner, the number of configs can be set to be consistent with the number of vector memories 13 . When a certain config is allocated to a certain agu, in the process of reading and writing the vector memory 13 by the agu, the reading and writing operations can be completed in combination with the configuration information corresponding to the target read and write requests stored in the allocated config.

Optionally, after completing the allocation of the target configuration information receiving unit 25, it can be determined in multiple configuration information receiving units 25 according to the target configuration information receiving unit 25 identifier that needs to be used indicated in the target read and write request based on the allocation result. The target configuration information receiving unit 25; determining a target indicating register simultaneously associated with the first addressing unit and the target configuration information receiving unit 25 among the plurality of indicating registers; storing the second value in the target indicating register.

Based on the above content, a possible implementation structure of the digital signal processor 10 described in the embodiment of the present invention is provided below. As shown in FIG. 9, the digital signal processor 10 may include a scalar processor 901, various vector computing units, a bus 902, a resource scheduling device 14, a configuration information receiving unit 25 (config0-i), and addressing units 0-n , a virtual addressing unit 908 , and a plurality of vector memories 903 . The various vector computing units may include a vector arithmetic logic operation unit 904 , a floating point operation unit 905 , an accelerator unit 906 , and a peripheral interface 907 . It should be noted that data transmission can be performed between the units through connecting lines with arrows.

A possible implementation structure of the above resource scheduling apparatus 14 is provided below. As shown in FIG. 10 , the resource scheduling apparatus 14 may include a timestamp register 101, a plurality of FIFO registers 102 with a depth of 2 (represented as 2 depth fifo in the figure), an arbitration unit 103, and a FIFO with a depth of 1 A first-out register 104 (represented as 1 depth fifo in the figure), a scheduling unit 22, a configuration information receiving unit 25 (config0-9), and a connecting unit 105. The scheduling unit 22 may include an addressing unit working state management module 221 , a decoding module 222 , an allocation decision module 223 , an addressing unit allocation module 224 , a connection state module 225 , a timer 226 , and a virtual addressing unit 227 . A bus 106 and addressing units (eg, addressing units 0 to 5) may also be provided outside the resource scheduling device 14 .

In the above structure, the time stamp register 101 is used to time stamp each received read and write request.

Each FIFO register 102 with a depth of 2 corresponds to a vector computing unit, and is used for buffering read and write requests sent by the corresponding vector computing unit. Therefore, the number of deployments of FIFO registers 102 with a depth of 2 is greater than or equal to the number of vector computation units. In addition, if the current vector calculation unit will send read and write requests at the same time, you can configure a FIFO register for the current vector calculation unit. If the current vector calculation unit may send read and write requests in time-sharing, you can The number of write requests configures the FIFO register.

Since different vector computing units may send multiple read and write requests in a short period of time, the order of processing these read and write requests can be decided by the arbitration unit 103, and the read and write requests processed first are output to the FIFO register 104 with a depth of 1 for processing. cache. It should be noted that the arbitration mode and the priority of each vector calculation unit can be configured, and then the order of processing different read and write requests is decided according to the arbitration mode and the priority of the vector calculation unit. Specifically, the method for determining the sequential processing order of read and write requests will be described in detail later in this article.

The connection unit 105 can complete the interconnection between the vector calculation unit and the addressing unit, and the interconnection between the configuration information receiving unit 25 and the addressing unit according to the connection state output by the scheduling unit 22 .

In addition, the other units in FIG. 10 have been explained in detail above, and will not be repeated here.

The working sequence relationship among the scalar processor, the vector computing unit, the resource scheduling device and the addressing unit is described below. As shown in Figure 11, first, the scalar processor can configure the vector computing unit and the resource scheduling device, and then the vector computing unit sends read and write requests to the resource scheduling device according to the configuration, and then after the resource scheduling device receives the read and write requests, it can immediately The vector computing unit is connected to the virtual addressing unit, and at the same time, the resource scheduling device can perform arbitration, decoding, decision-making, allocation, etc. on read and write requests, during which the vector computing unit is in a waiting state. After the allocation is completed, the vector computing unit is connected to the allocated addressing unit, and the vector computing unit can complete read and write operations through the connected addressing unit. Finally, after the vector computing unit completes the read and write operations, a read and write task end flag can be sent to the resource scheduling device to inform the resource scheduling device that the read and write operations are over, and the resource scheduling device can release the occupied addressing unit, so that the search The address unit re-enters the resource pool, and then processes the next new read and write request.

The method of determining the sequential processing order of read and write requests will be described below.

Optionally, as shown in FIG. 12 , on the basis of the structure shown in FIG. 2 , the resource scheduling apparatus 14 provided by the embodiment of the present invention may further include: a read/write request receiving unit 121 configured to receive the data sent by multiple vector computing units respectively. The arbitration unit 122 is used to determine the target vector calculation unit 11 in the plurality of vector calculation units according to the respective priorities of the vector calculation units, and the priorities corresponding to the vector calculation units are different; determine The target read and write request sent by the target vector calculation unit 11 .

It can be understood that the target read/write request is the read/write request processed first after arbitration.

In the embodiment of the present invention, a total of three different arbitration modes are provided. Of course, in addition to the three arbitration modes provided by the embodiment of the present invention, the mechanism of the arbitration mode can also be set according to actual needs, which is not implemented in the present invention. limited.

(1) Fixed priority mode

Optionally, the arbitration unit 122 may be configured to: when the read/write request response period arrives, determine the target vector calculation unit 11 with the highest priority among the multiple vector calculation units.

For ease of understanding, a method for determining the sequential processing order of read and write requests in the fixed priority mode will be described below with reference to FIG. 13 . In Figure 13, master represents the vector computing unit, assuming that there are 6 masters, including master0-5, the priority from high to low is expressed as from level 5 to level 0, and the priority of master0-5 is 5, 4, 3. , 2, 1, 0. Figure 13 shows the situation in which different masters send read and write requests at 5 times. It is assumed that the one column of squares corresponding to any time is filled with the master identifier for the master that currently has read and write requests, and the one that does not fill in the master identifier is currently unregistered. The master that sends read and write requests.

As can be seen from Figure 13, at time 0, master0, 3, and 5 all sent read and write requests, and each read and write request can be processed. Therefore, the request sent by master0 according to the priority is the first to be responded, and at time 1, there are remaining The read and write requests of the

next master

3 and 5 need to be responded, and the request sent by the priority master 3 is responded at this moment. Suppose that at time 2, master0 and 1 send read and write requests again, and now there are read and write requests from

masters

0, 1, and 5 that need to be responded to. The request sent by master0 according to the priority is responded at this time. By analogy, at time 3, the request sent by master1 is responded, and at time 4, the request sent by master5 is responded.

(2) Polling mode

Optionally, the arbitration unit 122 can be used to: when the read/write request response cycle arrives, determine the target vector computation unit 11 with the highest priority among the multiple vector computation units; when the next read/write request of the read/write request response cycle arrives When the response period arrives, a vector calculation unit to be adjusted whose priority is lower than the target vector calculation unit 11 is determined among the plurality of vector calculation units, and the priority of the vector calculation unit to be adjusted is raised to a preset level; the target vector calculation unit 11 corresponds to The priority is adjusted to the lowest value.

The above-mentioned preset level may be level 1.

For ease of understanding, the following describes the manner of determining the sequential processing order of read and write requests in the polling mode with reference to FIG. 14 . In Figure 14, master represents the vector computing unit, assuming that there are 6 masters, including master0-5, the priority from high to low is expressed as from level 5 to level 0, and the priority of master0-5 is 5, 4, 3. , 2, 1, 0. Figure 14 shows the situation in which different masters send read and write requests at 5 times. It is assumed that the one column of squares corresponding to any time is filled with the master identifier for the master that currently has read and write requests, and the one that does not fill in the master identifier is currently unregistered. The master that sends read and write requests.

At time 0, master0 has the highest priority and is responded first. At time 1, because master0 has been responded, the priority of master0 is adjusted to the lowest 0, and the priority of masters lower than the priority of master0 before adjustment is increased by 1, so master1 is adjusted to 5, master2 is adjusted to 4, master3 is adjusted to 3, master4 is adjusted to 2, and master5 is adjusted to 1. At time 1, the read and write requests of

masters

3 and 5 in the adjusted master need to be responded, and master 3 has the highest priority, so master 3 is responded. At time 2, master0 and 1 send new read and write requests, and because master3 has already responded, the priority of master3 is adjusted to 0, and the priority of master1 and 2, which is higher than that of master3 before adjustment, remains unchanged. The priorities of master0, 4, and 5, which are lower than the priority of master3 before adjustment, are all increased by 1. Therefore, master0 is adjusted to 1, master4 is adjusted to 3, and master5 is adjusted to 2. At time 2, the read and write requests of

masters

0, 1, and 5 in the adjusted master need to be responded, and master1 has the highest priority, so master1 is responded. And so on, at time 3, master5 is responded, and at time 4, master0 is responded.

(3) Time priority mode

Optionally, the resource scheduling apparatus 14 may further include: a time stamp unit, configured to record the read/write request sent by any vector calculation unit when the read/write request receiving unit 121 receives the read/write request sent by any vector calculation unit. The reception time of the write request; the arbitration unit 122 is used to determine the candidate read/write request with the earliest reception time among multiple read/write requests when the read/write request response period arrives, and assign the candidate read/write request with the earliest reception time The priority is set to the highest priority. If the number of candidate read/write requests is 1, the candidate read/write request will be determined as the target read/write request; if the number of candidate read/write requests is greater than 1, the one with the highest priority will be determined in the vector computing unit that sends the candidate read/write request. The target vector calculation unit 11 determines the target read/write request sent by the target vector calculation unit 11 .

For ease of understanding, the following describes the manner of determining the sequential processing order of read and write requests in the polling mode with reference to FIG. 15 . In Figure 15, master represents the vector computing unit, assuming that there are 6 masters, including master0-5, the priority from high to low is expressed as from level 5 to level 0, and the priority of master0-5 is 5, 4, 3. , 2, 1, 0. Figure 15 shows the situation in which different masters send read and write requests at 5 times. It is assumed that the one column of squares corresponding to any time is filled with the master identifier for the master that currently has read and write requests, and the one that does not fill in the master identifier is currently unregistered. The master that sends read and write requests.

At time 0, master0, 3, and 5 all send read and write requests. Since the read and write requests are received at the same time, master0 has the highest priority according to the priority, so master0 is responded first. At time 1, the read and write requests of

masters

3 and 5 need to be responded. Since the read and write requests of

masters

3 and 5 have the same reception time, master 3 is responded according to the priority. At time 2, master0 and 1 sent new read and write requests, and now there are read and write requests from

masters

0, 1, and 5 that need to be responded to. Since master5's read and write requests are received earlier than

masters

0 and 1, master5 is responded. At time 3, the read and write requests of master0 and 1 need to be responded. Since the read and write requests of master0 and 1 are received at the same time, master0 is responded according to the priority. At time 4, master1 is responded.

It should be noted that, in the above three arbitration modes, the priority of the vector calculation unit is used, and the priority of the vector calculation unit can be configured.

Yet another exemplary embodiment of the present invention provides a movable platform, as shown in FIG. 16 , the movable platform 160 may include the digital signal processor 10 in the embodiment shown in FIG. 1 .

The technical solutions and technical features in each of the above embodiments can be used alone or in combination without conflict. As long as they do not exceed the cognitive scope of those skilled in the art, they all belong to equivalent embodiments within the protection scope of the present invention.

The above descriptions are only the embodiments of the present invention, and are not intended to limit the scope of the present invention. Any equivalent structure or equivalent process transformation made by using the contents of the description and drawings of the present invention, or directly or indirectly applied to other related technologies Fields are similarly included in the scope of patent protection of the present invention.

Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, but not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: The technical solutions described in the foregoing embodiments can still be modified, or some or all of the technical features thereof can be equivalently replaced; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the technical solutions of the embodiments of the present invention. scope.

Claims

A resource scheduling device, comprising:

a target read/write request receiving unit, configured to receive the target read/write request sent by the target vector computing unit;

a scheduling unit, configured to determine the addressing unit corresponding to the target vector computing unit according to the addressing unit information corresponding to the target read/write request; and

A target read/write request sending unit, configured to send the target read/write request to an addressing unit corresponding to the target vector calculation unit.
The resource scheduling apparatus according to claim 1, wherein the resource scheduling apparatus further comprises:

A configuration information sending unit, configured to send configuration information corresponding to the target read/write request to a target configuration information receiving unit corresponding to the target vector calculation unit.
The resource scheduling apparatus according to claim 2, wherein the scheduling unit is configured to:

According to the addressing unit information corresponding to the target read/write request, determine the number of first addressing units that need to be used to execute the target read/write request;

determining a second addressing unit whose working state is idle among the plurality of addressing units;

If the number of the second addressing units is greater than or equal to the number of the first addressing units, determining the first addressing for executing the target read/write request in the second addressing unit unit, so as to perform read and write operations of the vector memory through the first addressing unit and the configuration information.
The resource scheduling apparatus according to claim 2, wherein the target read/write request includes a read interface and/or a write interface indicating that the target vector computing unit needs to be used,

The read interface corresponds to a third addressing unit, and the write interface corresponds to a fourth addressing unit.
The resource scheduling apparatus according to claim 4, wherein the target read/write request includes indication information of preset number of bits corresponding to all read interfaces and/or all write interfaces of the target vector computing unit;

When the highest 1-bit data of the indication information is 1, the indication information is used to instruct to enable the corresponding read interface or write interface; when the highest 1 of the indication information is 0, the indication information is used for Indicates that the corresponding read interface or write interface is not enabled.
The resource scheduling apparatus according to claim 4, wherein the scheduling unit is configured to:

The number of first addressing units to be used for executing the target read/write request is determined according to the read interface and/or write interface to be used indicated in the target read/write request.
The resource scheduling apparatus according to claim 4, wherein the scheduling unit comprises a plurality of indication registers, and the indication registers are connected to a read interface and/or a write interface of a vector calculation unit among the plurality of vector calculation units Associated with one addressing unit in the plurality of addressing units, when the first value is stored in any indication register, the any indication register indicates that the addressing unit associated with the any indication register is to be Assigned to the read interface and/or write interface associated with any of the indication registers.
The resource scheduling apparatus according to claim 7, wherein the scheduling unit is configured to:

determining, in the second addressing unit, a first addressing unit corresponding to the read interface and/or the write interface indicated in the target read/write request to be used;

determining, among the plurality of indication registers, a target indication register that is simultaneously associated with the read interface and/or write interface indicated in the target read/write request and/or the write interface and the corresponding first addressing unit;

The first value is stored in the target indication register.
The resource scheduling apparatus according to claim 7, wherein the resource scheduling apparatus further comprises:

a virtual addressing unit, used for allocating the virtual addressing unit to the The read interface and/or write interface to be used as indicated in the target read and write request.
The resource scheduling apparatus according to claim 4, wherein the target read/write request further carries a target vector calculation unit identifier and a target configuration information receiving unit identifier; the scheduling unit includes a plurality of indication registers, the indication The register is associated with one configuration information receiving unit in the plurality of configuration information receiving units and one addressing unit in the plurality of addressing units, and when the second value is stored in any indication register, the any indication register Indicates that the configuration information receiving unit associated with the any of the indication registers is assigned to the addressing unit associated with the any of the indication registers.
The resource scheduling apparatus according to claim 10, wherein the scheduling unit is configured to:

According to the target configuration information receiving unit identifier to be used indicated in the target read/write request, determine the target configuration information receiving unit among the plurality of configuration information receiving units;

determining, among the plurality of indication registers, a target indication register associated with the first addressing unit and the target configuration information receiving unit at the same time;

The second value is stored in the target indication register.
The resource scheduling apparatus according to claim 1, wherein the resource scheduling apparatus further comprises:

a read-write request receiving unit, used for receiving read-write requests sent by multiple vector computing units respectively;

an arbitration unit, configured to determine the target vector calculation unit among the plurality of vector calculation units according to the respective priorities of the vector calculation units, and the respective priorities of the vector calculation units are different; The target read and write request sent by the target vector calculation unit.
The resource scheduling apparatus according to claim 12, wherein the arbitration unit is configured to:

When the read/write request response period arrives, the target vector calculation unit with the highest priority is determined among the plurality of vector calculation units.
The resource scheduling apparatus according to claim 13, wherein the arbitration unit is further configured to:

When the next read/write request response cycle of the read/write request response cycle arrives, a vector calculation unit to be adjusted whose priority is lower than the target vector calculation unit is determined in the plurality of vector calculation units, and the to-be-adjusted vector calculation unit is determined in the plurality of vector calculation units. Adjust the priority of the vector calculation unit to increase the preset level;

The priority corresponding to the target vector calculation unit is adjusted to the lowest value.
The resource scheduling device according to claim 12, wherein the resource scheduling device further comprises:

a timestamp unit, configured to record the reception time of receiving the read/write request sent by any vector calculation unit when the read/write request receiving unit receives the read/write request sent by any vector calculation unit;

The arbitration unit is used to determine the candidate read/write request with the earliest corresponding reception time among the multiple read/write requests when the read/write request response period arrives; if the number of the candidate read/write requests is 1, then The candidate read/write request is determined as the target read/write request; if the number of the candidate read/write requests is greater than 1, the target vector computation unit with the highest priority is determined in the vector computation unit that sends the candidate read/write request, Determine the target read/write request sent by the target vector calculation unit.
A digital signal processor, characterized in that the digital signal processor comprises a target vector calculation unit, a plurality of addressing units, a vector memory, and the resource scheduling device according to any one of claims 1-15, wherein:

the target vector calculation unit, configured to send a target read and write request to the resource scheduling device;

The resource scheduling device is configured to select an addressing unit corresponding to the target vector computing unit from the multiple addressing units according to the target read/write request;

The addressing unit corresponding to the target vector calculation unit is configured to perform read/write operations on the vector memory according to the target read/write request.
The digital signal processor according to claim 16, wherein the target vector calculation unit comprises a vector arithmetic logic operation unit, a floating point operation unit, an accelerator unit or a peripheral interface.
A movable platform, characterized in that, the movable platform comprises the digital signal processor of any one of claims 16-17.