WO2022120586A1 - 一种存储装置、存储控制装置及片上系统 - Google Patents

一种存储装置、存储控制装置及片上系统 Download PDF

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Publication number
WO2022120586A1
WO2022120586A1 PCT/CN2020/134604 CN2020134604W WO2022120586A1 WO 2022120586 A1 WO2022120586 A1 WO 2022120586A1 CN 2020134604 W CN2020134604 W CN 2020134604W WO 2022120586 A1 WO2022120586 A1 WO 2022120586A1
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Prior art keywords
data
memory
storage
address
error correction
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PCT/CN2020/134604
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English (en)
French (fr)
Inventor
沈国明
王正波
伊学文
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华为技术有限公司
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Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to CN202080107263.6A priority Critical patent/CN116457761A/zh
Priority to EP20964531.6A priority patent/EP4246328A4/en
Priority to PCT/CN2020/134604 priority patent/WO2022120586A1/zh
Publication of WO2022120586A1 publication Critical patent/WO2022120586A1/zh
Priority to US18/331,635 priority patent/US20230315566A1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1048—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using arrangements adapted for a specific error detection or correction feature
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1044—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices with specific ECC/EDC distribution

Definitions

  • the present application relates to the field of storage, and in particular, to a storage device, a storage control device and a system-on-chip.
  • DRAM dynamic random access memory
  • DRAM data protection technology generally configures an independent error correcting code (ECC) storage partition in the DRAM chip, and the ECC storage partition is generally evenly deployed near the DRAM storage partition.
  • ECC error correcting code
  • the present application provides a storage device, a storage control device and a system-on-chip, so as to prevent the error correction code from occupying the storage space in the first memory and increase the capacity of the available data in the first memory.
  • the present application provides a storage device, comprising: a first memory, configured to store data; a second memory, configured to store an error correction code corresponding to the data, and the error correction code is used for data protection of the data;
  • the memory controller is configured to: write data to the first memory; and read data from the first memory; wherein the first memory and the second memory belong to different dies.
  • the storage controller and the first memory are coupled through address lines and data lines (including write data lines and read data lines), and the storage controller can be configured to write the first data to the first memory through the address lines and the write data lines Alternatively, the second data is read from the first memory through the address line and the read data line.
  • the first memory may be a DRAM.
  • the first memory may include one or more DRAM dies, such as multiple DRAM dies stacked in 3D (3 dimension).
  • the first memory may also be a 3D stack-based static random-access memory (static random-access memory, SRAM), non-volatile memory (non-volatile memory, NVM) and other memories.
  • SRAM static random-access memory
  • NVM non-volatile memory
  • the second memory may be SRAM.
  • the second memory may include one or more SRAM dies.
  • the error correction code is stored in the second memory, that is, the storage area of the error correction code is concentrated outside the first memory In the second memory, in this way, the error correction code is prevented from occupying the storage space in the first memory, and the capacity of the available data in the first memory is increased.
  • the error correction code is stored in the second memory (such as SRAM), and the second memory and the first memory (such as DRAM) belong to a different die, then there is no need to allocate storage for the error correction code in the DRAM die area to avoid error correction codes occupying storage space in the DRAM die, thereby increasing the capacity of available data on the DRAM die.
  • the error correction code storage partition and the data storage partition are set on the same die, and the error correction code can only perform data protection on data on the same die.
  • the error correction code storage partition is set in the second memory, and the second memory and the first memory belong to different die, so the error correction code in the second memory is Data protection can be performed for the data in one or more first memories, so as to realize that multiple first memories share one second memory, which can also be understood as realizing global sharing of error correction codes.
  • the error correction code storage partition is set in the second memory, and the second memory and the first memory belong to different die, so that the storage partition of the second memory can be flexibly allocated Error correction code storage partitions are allocated to the storage partitions of the first memory that actually require data protection, not all data storage partitions.
  • the storage resources of error correction codes can be saved, thereby realizing flexible adjustment and use according to actual needs and working conditions. Data protection area, thereby improving the utilization of error correction code storage resources.
  • the data includes first data and second data
  • the storage device further includes: an error checking and correction (error checking and correction, ECC) circuit configured to: generate a corresponding a first error correction code; and performing error correction on the second data according to the second error correction code in the second memory; the second error correction code is an error correction code corresponding to the second data; the storage controller is specifically configured to: The first data is written to the first memory, and the second data is read from the first memory.
  • ECC error checking and correction
  • the ECC circuit is further configured to: when it is determined that the first data is the data that needs to be protected, generate a first error correction code; and when it is determined that the second data is the data that needs to be protected, according to the first The second error correction code performs error correction on the second data.
  • the ECC circuit is further configured to: when it is determined that the first data is data that does not require protection, write the first data into the first storage partition according to the first address.
  • the ECC circuit is further configured to: when it is determined that the second data is data that does not require protection, output the second data to the memory controller according to the second address.
  • the ECC circuit determines that the first data and the second data are data that need to be protected
  • the ECC operation (such as generating an error correction code) is performed on the first data and the second data.
  • the ECC operation is performed to improve the utilization rate of error correction code storage resources while ensuring effective data protection.
  • the ECC circuit is configured to determine whether the first data is data to be protected according to a first address corresponding to the first data and preset protection configuration information; and according to the first address corresponding to the second data Two addresses and protection configuration information to determine whether the second data is data that needs to be protected; wherein, the protection configuration information includes the mapping relationship between the storage partition in the first memory and the storage partition in the second memory, and the storage partition in the second memory is the same as the one in the second memory. Correspondence to the data to be protected.
  • configurable protection configuration information can be set, and by configuring the protection configuration information, the mapping relationship between the storage partition in the first memory and the storage partition in the second storage can be changed, so that the storage partition of the second storage can be flexibly
  • the storage partitions of the first memory that need to be protected need not be fixedly assigned to all data storage partitions. In this way, for data storage partitions with less access, the corresponding error correction code storage resources may not be configured, so as to save error correction code storage resources, so as to adjust the area for data protection according to actual needs and working conditions, thereby improving error correction. utilization of code storage resources.
  • the memory controller is configured to output the first address and the first data to the ECC circuit; the ECC circuit is further configured to: write the first error correction code into the second memory; according to the first address to write the first data into the first storage partition of the first memory.
  • the ECC circuit is further configured to: when it is determined that the first data is data that does not require protection, obtain a third address corresponding to the first address; The second storage partition in the second memory is written, so as to realize the protection of the first data.
  • the ECC circuit is further configured to: when it is determined that the second data is data to be protected, obtain a fourth address corresponding to the second address; according to the fourth address, obtain the fourth address from the second memory
  • the storage partition reads the second error correction code, thereby realizing the protection of the second data.
  • the storage controller is further configured to output the second address to the ECC circuit; the ECC circuit is further configured to: read the first address from the third storage partition of the first memory according to the second address Second data; output the second data to the storage controller.
  • the ECC circuit is configured to: check the second data according to the second error correction code; if an error is detected, perform error correction on the second data, and output the error correction to the memory controller second data after; if no error is detected, output the second data to the storage controller.
  • the ECC circuit determines that the first data and the second data are data that need to be protected, the ECC operation is performed on the first data and the second data (for example, error correction is performed according to an error correction code), so as to achieve selective The ECC operation is performed on the data, which improves the utilization rate of error correction code storage resources while ensuring effective data protection.
  • the ECC circuit is configured to output the second data to the memory controller when it is determined that the second data is data that does not require protection.
  • the ECC circuit and the second memory belong to the same die; alternatively, the ECC circuit and the second memory belong to different dies.
  • the ECC circuit and the memory controller belong to different dies; alternatively, the ECC circuit and the memory controller belong to the same die.
  • the lower address of each storage partition in the first memory is the same as the storage address of each storage partition in the second memory.
  • the present application provides a storage control device, which may include: a storage controller and an ECC circuit; wherein the storage controller is configured to write first data to a first memory, and read first data from the first memory two data; the ECC circuit is configured to: when it is determined that the first data is the data that needs to be protected, generate a first error correction code; and when it is determined that the second data is the data that needs to be protected, according to the second error correction code Two data for error correction.
  • the ECC circuit determines that the first data and the second data are data to be protected, the ECC operation is performed on the first data and the second data (such as generating an error correction code, performing error correction according to the error correction code, etc.) , in this way, the ECC operation can be selectively performed on the data, and the utilization rate of error correction code storage resources can be improved while ensuring effective data protection.
  • the ECC circuit is configured to determine whether the first data is data to be protected according to a first address corresponding to the first data and preset protection configuration information; and according to the first address corresponding to the second data Two addresses and protection configuration information to determine whether the second data is data that needs to be protected; wherein, the protection configuration information includes the mapping relationship between the addresses of the storage partitions in the first memory and the addresses of the storage partitions in the second storage, and the second storage corresponding to the data that needs to be protected.
  • the memory controller is configured to output the first address and the first data to the ECC circuit; the ECC circuit is further configured to: write the first error correction code into the second memory; according to the first address to write the first data into the first storage partition of the first memory.
  • the ECC circuit is further configured to: when it is determined that the first data is the data to be protected, obtain a third address corresponding to the first address; and write the first error correction code according to the third address into the second storage partition in the second memory.
  • the ECC circuit is further configured to: when it is determined that the first data is data that does not require protection, write the first data into the first storage partition according to the first address.
  • the storage controller is further configured to output the second address to the ECC circuit; the ECC circuit is further configured to: read the first address from the third storage partition of the first memory according to the second address Second data; output the second data to the storage controller.
  • the ECC circuit is configured to: check the second data according to the second error correction code; if an error is detected, perform error correction on the second data, and output the error correction to the memory controller second data after; if no error is detected, output the second data to the storage controller.
  • the ECC circuit is further configured to: when it is determined that the second data is data to be protected, obtain a fourth address corresponding to the second address; according to the fourth address, obtain the fourth address from the second memory
  • the bucket reads the second error correction code.
  • the ECC circuit is configured to output the second data to the memory controller when it is determined that the second data is data that does not require protection.
  • the ECC circuit and the second memory belong to the same die; alternatively, the ECC circuit and the second memory belong to different dies.
  • the ECC circuit and the memory controller belong to different dies; alternatively, the ECC circuit and the memory controller belong to the same die.
  • the present application provides a system on a chip, including: a processor, a bus, and the storage device according to any one of the first aspect and its possible implementations;
  • the processor is configured to: output the write instruction and the first data to the storage device through the bus, or output the read instruction to the storage device through the bus, and receive the second data output from the storage device through the bus; the write instruction is used to instruct the first data to be sent to the storage device
  • the storage area writes the first data
  • the read instruction is used to instruct to read the second data from the second storage area.
  • the present application provides a data storage method, which can be applied to the storage device described in any one of the above-mentioned first aspect and its possible implementation manners. Then, the method may include: the storage controller writes data to the first memory, and reads data from the first memory, wherein the first memory and the second memory belong to different dies, and the second memory is used for storing data corresponding to The error correction code is used for data protection of data.
  • the data includes first data and second data; the foregoing storage controller writing data to the first memory includes: the storage controller writing the first data to the first memory;
  • the above-mentioned memory controller reading data from the first memory includes: the memory controller reading the second data from the first memory.
  • the above method further includes: the ECC circuit generates a first error correction code corresponding to the first data; or, the ECC circuit performs error correction on the second data according to the second error correction code in the second memory, and the second error correction code is the error correction code corresponding to the second data.
  • the above-mentioned ECC circuit generates a first error correction code corresponding to the first data, including: when it is determined that the first data is data that needs to be protected, the ECC circuit generates a first error correction code;
  • the above-mentioned ECC circuit performs error correction on the second data according to the second error correction code in the second memory, including: when it is determined that the second data is data that needs to be protected, the ECC circuit corrects the second data according to the second error correction code. wrong.
  • the above method further includes: the ECC circuit determines whether the first data is data that needs to be protected according to the first address corresponding to the first data and preset protection configuration information; The second address corresponding to the data and the protection configuration information, to determine whether the second data is data that needs to be protected; wherein, the protection configuration information includes the mapping relationship between the address of the storage partition in the first memory and the address of the storage partition in the second memory , and the storage partition of the second memory corresponds to the data to be protected.
  • the above-mentioned storage controller writing the first data to the first memory includes: the storage controller outputs the first address and the first data to the ECC circuit; the ECC circuit converts the first data to the ECC circuit according to the first address Write to the first storage partition of the first memory.
  • the above method further includes: the ECC circuit obtains a third address corresponding to the first address; according to the third address, writing the first error correction code into the third address The second storage partition in the second memory.
  • the above method further includes: when it is determined that the first data is data that does not require protection, the ECC circuit writes the first data into the first memory.
  • the above-mentioned storage controller reads the second data from the first memory, including: the storage controller outputs the second address to the ECC circuit; the ECC circuit stores the third data from the first memory according to the second address The second data is read in the partition; the ECC circuit outputs the second data to the memory controller.
  • the above-mentioned ECC circuit outputs the second data to the memory controller, including: the ECC circuit checks the second data according to the second error correction code; if an error is detected, error correction is performed on the second data , and output the error-corrected second data to the storage controller; if no error is detected, output the second data to the storage controller.
  • the above method when it is determined that the second data is data that needs to be protected, the above method further includes: the ECC circuit obtains a fourth address corresponding to the second address; Four memory partitions read the second error correction code.
  • the above method further includes: when it is determined that the second data is data that does not require protection, the ECC circuit outputs the second data to the memory controller.
  • the present application provides a data storage method, which can be applied to the storage control device according to any one of the second aspect and its possible implementation manners. Then, the method can include:
  • the storage control device writes the first data to the first memory, and reads the second data from the first memory;
  • the storage control device When it is determined that the first data is data requiring protection, the storage control device generates a first error correction code; and,
  • the storage control device When it is determined that the second data is data that needs to be protected, the storage control device performs error correction on the second data according to the second error correction code.
  • the above method further includes: the storage control device determines whether the first data is data that needs to be protected according to the first address corresponding to the first data and preset protection configuration information; and,
  • the storage control device determines whether the second data is data to be protected according to the second address corresponding to the second data and the protection configuration information;
  • the protection configuration information includes the mapping relationship between the addresses of the storage partitions in the first memory and the addresses of the storage partitions in the second memory, and the storage partitions of the second memory correspond to the data to be protected.
  • the above-mentioned storage control apparatus writing the first data to the first memory includes: the storage control apparatus writes the first data into the first storage partition of the first memory according to the first address.
  • the above method further includes: the storage control apparatus obtains a third address corresponding to the first address; and writes the first error correction code according to the third address into the second storage partition in the second memory.
  • the above method further includes: when it is determined that the first data is data that does not require protection, the storage control apparatus writes the first data into the first memory.
  • the above-mentioned storage control apparatus reads the second data from the first memory, including: the storage controller reads the second data from the third storage partition of the first memory according to the second address.
  • the above-mentioned storage control device reads the second data from the first memory, including: the storage control device checks the second data according to the second error correction code; if an error is detected, the storage control device checks the second data. The second data is subjected to error correction, and the error-corrected second data is obtained; if no error is detected, the storage control device obtains the second data.
  • the above method before the storage control apparatus performs error correction on the second data, the above method further includes: when it is determined that the second data is data to be protected, the storage control apparatus obtains a fourth address corresponding to the second address ; The storage control device reads the second error correction code from the fourth storage partition in the second memory according to the fourth address.
  • the above method further includes: when it is determined that the second data is data that does not require protection, the storage control apparatus reads the second data.
  • the present application provides an electronic device, the electronic device comprising: a processor, a bus, and the storage device according to the first aspect and any possible implementation manner thereof, the processor communicates with the storage device through the bus coupling.
  • the above-mentioned processor may include the system-on-chip as described in the third aspect.
  • the above-mentioned storage device is further used to store program instructions.
  • the above-mentioned processor is configured to: when the electronic device is running, the processor executes the program instructions stored in the storage device, so that the electronic device realizes corresponding functions.
  • the above electronic device further includes: an input device and an output device.
  • the input device is used to input commands and information to the electronic device, and the input device is connected to the processor through a bus.
  • the output device is used for the electronic device to output information, and the output device can also be connected to the processor through the bus.
  • the above electronic device further includes: an antenna system, which, under the control of the processor, sends and receives wireless communication signals to implement wireless communication with the mobile communication network.
  • FIG. 1 is a schematic diagram of a DRAM chip in an embodiment of the application
  • FIG. 2 is a schematic diagram of protection configuration information in an embodiment of the present application.
  • FIG. 3 is a schematic structural diagram of a storage device according to an embodiment of the present application.
  • FIG. 4 is a schematic diagram of a data writing process of a storage device in an embodiment of the present application.
  • FIG. 5 is a schematic diagram of a data read process of a storage device in an embodiment of the present application.
  • FIG. 6 is a schematic structural diagram of an ECC circuit in an embodiment of the present application.
  • FIG. 7 is a schematic diagram of the workflow of the ECC circuit in the data writing process in the embodiment of the application.
  • FIG. 8 is a schematic diagram of the workflow of the ECC circuit in the process of reading data in an embodiment of the present application.
  • FIG. 9 is another schematic structural diagram of a storage device in an embodiment of the present application.
  • FIG. 10 is a schematic diagram of the first packaging of the storage device in the embodiment of the present application.
  • FIG. 11 is a schematic diagram of a second package of the storage device in the embodiment of the present application.
  • FIG. 12 is a schematic diagram of a third packaging of the storage device in the embodiment of the present application.
  • FIG. 13 is a schematic diagram of a fourth packaging of the storage device in the embodiment of the present application.
  • FIG. 14 is a schematic diagram of a fifth packaging of the storage device in the embodiment of the application.
  • FIG. 15 is a schematic diagram of hardware of an electronic device in an embodiment of the present application.
  • Dynamic random access memory is a large-capacity and high-density semiconductor memory. As the scale of DRAM chips becomes larger and larger, the operating frequency becomes higher and higher. In the working state of the DRAM chip, the unit (cell) in the DRAM chip will spontaneously change to the opposite state due to electromagnetic interference inside the electronic device (the data soft fails at this time). This unit error may be recessive, that is, it will not have a serious impact on the data; however, the individual memory partitions (banks) in a DRAM chip are interrelated, so a unit error will cause data read and write errors , which in turn may affect the entire electronic device. Then, in order to avoid data read and write errors caused by unit errors, DRAM chips usually use error checking and correction (error checking and correction, ECC) techniques to correct soft failure data.
  • ECC error checking and correction
  • ECC technology is a means of data protection, and its main function is to detect and correct errors.
  • ECC technology requires an additional storage partition to store the error correction code, but the number of bits occupied by the error correction code is not linear with the length of the data.
  • the ECC technology is based on 8-bit data and 5-bit error correction code, and each additional 8-bit data only needs to add another bit of error correction code.
  • the error correction code generated by an 8-bit data needs to occupy 5 bits of space, and the error correction code corresponding to a 16-bit data only needs to add one more bit to the space occupied by the error correction code corresponding to the 8-bit data.
  • an independent ECC storage partition is generally configured in the DRAM chip, and the address of the ECC storage partition is the same as that of the DRAM storage partition.
  • FIG. 1 is a schematic structural diagram of an example of a DRAM chip in an embodiment of the present application.
  • a DRAM chip 100 may include a DRAM controller 101 , an ECC circuit 102 , a DRAM storage partition 103 and an ECC storage partition 104 .
  • the DRAM controller 101 is coupled with the DRAM storage partition 103 through the address line A, the DRAM controller 101 is coupled with the ECC circuit 102 through the data line (including the write data line W and the read data line R), and the ECC circuit 102 is coupled with the ECC circuit 102 through the data line (including the write data line W and the read data line R) are coupled to the DRAM storage area 103 and the ECC storage area 104 .
  • the above-mentioned ECC circuit 102 may include an ECC generation module 1021 and an ECC check module 1022 .
  • the ECC generation module 1021 is configured to generate an error correction code corresponding to the data
  • the ECC check module 1022 is configured to check the to-be-error-corrected code, and when a 1-bit error is detected, correct the to-be-error-corrected code according to the error correction code.
  • the DRAM chip 100 may include: a logic die (logic die/basic die) 111 and at least one DRAM die 112, the above-mentioned DRAM controller 101 and the ECC circuit 102 may be integrated in the logic die 111, and the above-mentioned DRAM storage partition 103 And the ECC memory partition 104 can be integrated into one DRAM die 112.
  • the logic die 111 and each DRAM die 112 are individually packaged, or the logic die 111 and the DRAM die 112 may be 2.5D (2.5 dimension) stacked or 3D (3 dimension) stacked in a package.
  • the logic die and the DRAM die may also have other implementation forms, which are not specifically limited in the embodiments of the present application.
  • the data reading and writing process of the DRAM chip 100 may be as follows:
  • the writing data process can include the following steps:
  • Step 1 the DRAM controller 101 receives the write instruction from the user side, and outputs the write operation instruction and the write address to the DRAM die 112 through the address line A;
  • Step 2 the DRAM controller 101 outputs the write data to the ECC circuit 102 through the write data line W;
  • Step 3 the ECC circuit 102 generates a corresponding error correction code for the write data
  • Step 4 the ECC circuit 102 outputs the write data and the corresponding error correction code to the DRAM die 112 through the write data line W;
  • the write data is output to the DRAM storage partition 103 , and the error correction code is output to the ECC storage partition 104 .
  • DRAM chips can generate 8-bit error correction codes using 64-bit data.
  • Step 5 the DRAM die 112 responds to the write operation instruction, writes the write data into the DRAM storage partition 103 according to the write address, and writes the error correction code into the ECC storage partition 104 according to the write address.
  • the process of reading data can include the following steps:
  • Step 1 the DRAM controller 101 receives the read instruction from the user side, and outputs the read operation instruction and the read address to the DRAM die 112 through the address line A;
  • Step 2 the DRAM die 112 responds to the read operation instruction, and reads the read data and the corresponding error correction code from the DRAM storage partition 103 and the ECC storage partition 104 respectively according to the read address;
  • Step 3 the DRAM die 112 outputs the read data and the corresponding error correction code to the ECC circuit 102 through the read data line R;
  • Step 4 The ECC circuit 102 checks the read data
  • Step 5 If the ECC circuit 102 detects a 1-bit error, the ECC circuit 102 performs error correction on the read data according to the error correction code, and outputs the error-corrected read data to the DRAM controller 101 through the read data line R; 102 If no error is detected, the ECC circuit 102 outputs the read data to the DRAM controller 101 through the read data line R;
  • Step 6 The DRAM controller 101 outputs the read data from the ECC circuit 102 to the user side.
  • some DRAM chips can support the use of the ECC storage partition in the above-mentioned DRAM die as a common data storage partition (that is, use the ECC storage partition to expand the DRAM storage partition) to increase the usable capacity of the DRAM chip.
  • the ECC storage partition in the above-mentioned DRAM die as a common data storage partition (that is, use the ECC storage partition to expand the DRAM storage partition) to increase the usable capacity of the DRAM chip.
  • an embodiment of the present application provides a storage device, and the storage device may include: a first memory, a second memory, and a storage controller; wherein the first memory and the second memory belong to different dies, that is, , the first memory and the second memory are physically independent.
  • the first memory may be configured to store data; the second memory may be configured to store error correction codes corresponding to the data in the first memory.
  • the memory controller and the first memory are coupled through address lines and data lines (including write data lines and read data lines), and the memory controller may be configured to write the first data to the first memory through the address lines and the write data lines or to write the first data through the address lines and the write data lines.
  • the address line and the read data line read the second data from the first memory.
  • the first memory may be implemented in the form of a DRAM die.
  • the first memory may be one or more DRAM dies.
  • the first memory may also be a 3D stack-based static random-access memory (static random-access memory, SRAM), non-volatile memory (non-volatile memory, NVM) and other memories.
  • SRAM static random-access memory
  • NVM non-volatile memory
  • the second memory may be implemented in the form of an SRAM die.
  • the second memory can be one or more SRAM dies.
  • first memory and the second memory may also be implemented in other forms, which are not specifically limited in this embodiment of the present application.
  • the first memory does not need to allocate a storage partition for the error correction code, thus, the error correction code is prevented from occupying the storage space of the first memory, and the capacity of the available data in the first memory is increased.
  • the difference from the embodiment in FIG. 1 is that the first memory (such as DRAM) and the second memory (such as SRAM) are integrated in different dies, and data and corresponding error correction codes are stored in the first memory respectively.
  • a memory and a second memory in this way, there is no need to allocate corresponding storage space for the error correction code in the DRAM, thereby reducing the fixedly configured storage space of the error correction code in the DRAM, thereby increasing the available data capacity of the DRAM.
  • the error correction code does not need to be as described in the embodiment of FIG. 1 , It can only protect the data in the data storage partition of the same die as the error correction code storage partition, but can perform data protection on the data in one or more first memories, thereby realizing that multiple first memories share one second. memory.
  • the error correction code storage partition is set in the second memory, and the second memory and the first memory belong to different die, so that the storage partition of the second memory can be It is flexibly allocated to the storage partition of the first memory that actually needs data protection, instead of all the data storage partitions are allocated the error correction code storage partition, so that the storage resources of the error correction code can be saved, so as to realize the actual demand and working status Flexibly adjust the area where data protection is used, thereby improving the utilization of error correction code storage resources.
  • the first memory and the second memory may be deployed in a certain proportion.
  • the ratio of the data to the error correction code may also be other ratios, as long as the storage space of the error correction code is far smaller than the storage space of the data, which is not specifically limited in this embodiment of the present application.
  • the storage space of the error correction code is much smaller than the storage space of the data, which can be understood as using the error correction code of the smaller address range to protect the data of the larger address range, thus saving the storage resources of the error correction code , and improve the utilization of error correction code storage resources.
  • the first memory is DRAM and the second memory is SRAM as an example for description.
  • the first memory can be divided into multiple DRAM partitions
  • the second memory can also be divided into multiple SRAM partitions.
  • the number of DRAM partitions and SRAM partitions can be configured with reference to the ratio of the above data to error correction codes.
  • configurable protection configuration information may be set, and the protection configuration information may include a mapping relationship between the addresses of the storage partitions in the first memory and the addresses of the storage partitions in the second memory.
  • the protection configuration information may include a mapping relationship between the addresses of the storage partitions in the first memory and the addresses of the storage partitions in the second memory.
  • the protection configuration information may include a mapping relationship between the addresses of the DRAM partitions requiring data protection and the addresses of the SRAM partitions allocated for the DRAM partitions. Then, as long as there is a DRAM partition with a mapping relationship between addresses in the protection configuration information, it means that the data corresponding to the DRAM partition is the data that needs to be protected, and the protection configuration information does not have a DRAM partition between addresses. It means that the DRAM partition has no mapping relationship between addresses. The data corresponding to the partition is the data that does not need to be protected.
  • the protection configuration information may further include the mapping relationship between the addresses of all DRAM partitions and the addresses of the SRAM partitions, wherein the addresses of the DRAM partitions requiring data protection correspond to the addresses of the SRAM partitions allocated for the DRAM partitions, and The address of the SRAM partition corresponding to the address of the DRAM partition that does not require data protection can be set to "0", "null", "empty” and so on. Then, as long as there is a DRAM partition with a corresponding SRAM partition address, it means that the data corresponding to the DRAM partition is the data that needs to be protected, and the DRAM partition whose mapping address is "0", "null", "empty”, etc. The data corresponding to the DRAM partition is data that does not need to be protected.
  • FIG. 2 is a schematic diagram of the protection configuration information in the embodiment of the application.
  • the above protection configuration information is implemented in the form of a table.
  • the DRAM partitions requiring data protection represented by the high-order addresses of each storage partition
  • the DRAM partitions requiring data protection such as channel0+bank1 (that is, partition 1 in channel 0), channel0+bank63, channel1+bank62, ..., channel7+bank63
  • SRAM partition represented by the storage address of each storage partition
  • zone0 to zone7 mapped address of a DRAM partition that does not require data protection is "0".
  • the above-mentioned high-order address refers to the address of the previous part of the storage address of the DRAM partition (may include the Channel identifier + the Bank address).
  • the latter part of the storage address is the low-order address of the DRAM partition.
  • the storage address of the DRAM partition can be 16 bits, then, the first 8 bits are the high-order address of the DRAM partition, and correspondingly, the last 8 bits are the low-order address of the DRAM partition.
  • the storage address of the DRAM partition is channel0+bank1+00010110, the high-order address is channel0+bank1, and the low-order address is 00010110.
  • the protection configuration information may also include an identifier of "whether ECC", and this identifier can be used to indicate whether the DRAM partition needs data protection, It can also be understood that this identifier can be used to indicate whether the data corresponding to the DRAM partition is data that needs to be protected, whether the DRAM partition has a corresponding error correction code, whether the DRAM partition is configured with a corresponding SRAM partition, and the like.
  • the lower address of each storage partition in the first memory is the same as the storage address of each storage partition in the second memory.
  • the storage address of the DRAM partition that needs data protection is channel0+bank1+00010110
  • the address of the SRAM partition corresponding to the DRAM partition may be the lower address 00010110 of the DRAM partition.
  • FIG. 3 is a schematic structural diagram of a storage device according to an embodiment of the present application.
  • the storage device 300 may include: a first memory 301 , a second memory 302 , and a storage controller 303 and the ECC circuit 304; wherein, the first memory 301 and the second memory 302 belong to different dies.
  • the storage controller 303 is coupled to the first memory 301 through the address line A
  • the storage controller 303 is coupled to the ECC circuit 304 through the data line (including the write data line W and the read data line R) and the address line A
  • the ECC circuit 304 passes through the data line Coupled with the first memory 301 and the second memory 302 .
  • the first memory 301, the second memory 302, and the storage controller 303 are the same as the first memory, the second memory, and the storage controller in the above-mentioned embodiment.
  • the ECC circuit is further configured to: when it is determined that the first data is the data that needs to be protected, generate a first error correction code corresponding to the first data; when it is determined that the second data is the data that needs to be protected When , the second data is subjected to error correction according to the second error correction code corresponding to the second data.
  • the ECC circuit determines that the first data and the second data are data that need to be protected, the ECC operation is performed on the first data and the second data (for example, generating an error correction code, performing correction according to the error correction code) Errors, etc.), in this way, the selective ECC operation is implemented on the data, and the utilization rate of error correction code storage resources is improved while ensuring effective data protection.
  • the ECC circuit 304 is further configured to monitor the address line between the storage controller 303 and the first memory 301 to obtain the write address (ie the first address) or the read address (the second address) of the data.
  • the ECC circuit 304 can be configured to: according to the write address and the above protection configuration information, determine whether the first data is the data that needs to be protected; and according to the read address and the above protection configuration information, determine whether the second data is the data that needs to be protected data.
  • the ECC circuit can determine that data protection is required for the DRAM partition whose high-order address is "channel0+bank1" by querying the protection configuration information shown in Figure 2. Then, the ECC circuit can generate the first error correction code corresponding to the first data. Similarly, if the read address is channel0+bank63+0100101, the ECC circuit can determine that data protection is required for the DRAM partition whose high-order address is "channel0+bank63" by querying the protection configuration information shown in Figure 2. Then, the ECC circuit performs error correction on the second data according to the second error correction code.
  • the storage controller is further configured to output the first data to the ECC circuit; then, the ECC circuit is further configured to: when it is determined that the first data is data that needs to be protected, generate a first error correction code, and use The first error correction code is written into the second memory; according to the write address, the first data is written into the first storage partition of the first memory.
  • the ECC circuit is further configured to: read the second data from the third storage partition of the second memory according to the read address; when it is determined that the second data is data that needs to be protected, read the second ECC from the second memory error code, and perform error correction on the second data according to the second error correction code; output the error-corrected second data to the storage controller.
  • the ECC circuit may belong to the same die as the second memory; alternatively, the ECC circuit may belong to a different die than the second memory.
  • the ECC circuit may belong to a different die from the memory controller; alternatively, the ECC circuit may belong to a different die from the memory controller.
  • the ECC circuit, the second memory, and the memory controller can be integrated into the same die, or can be integrated into different dies respectively.
  • the ECC circuit and the memory controller are integrated into one die, and the second memory is integrated into another die. die.
  • the following describes the data reading and writing process of the storage device with reference to the structure of the storage device.
  • FIG. 4 is a schematic diagram of a data writing process of a storage device in an embodiment of the present application. Then, referring to FIG. 4 , the data writing process may include the following steps:
  • S401 The storage controller receives a write instruction from a user side
  • the storage controller outputs a write operation instruction and a write address (that is, the first address of the first storage partition) to the first memory through the address line;
  • S403 the storage controller outputs the write address to the ECC circuit
  • S404 the storage controller outputs the first data (ie, the write data) to the ECC circuit through the write data line;
  • S405 The ECC circuit determines whether the first data is data to be protected according to the write address; if so, obtains the second address of the second storage partition in the second memory, and executes S406; if not, executes S408.
  • the ECC circuit can take the high-order address of the write address (such as Channel ID+Bank address), and then use the high-order address to query the protection configuration information (as shown in FIG. 2 ), To determine whether the first data is data that needs to be protected, that is, to determine whether the first storage partition needs data protection. For example, if the write address is channel0+bank1, the ECC circuit queries the protection configuration information shown in Figure 2, and determines that the data corresponding to channel0+bank1 is the data that needs to be protected through the "ECC" flag, that is, it is determined that the first storage partition needs data. protection, and then the ECC circuit can obtain the SRAM partition address (third address) corresponding to channel0+bank1 through the protection configuration information, that is, zone0.
  • the write address is channel0+bank1
  • the ECC circuit queries the protection configuration information shown in Figure 2, and determines that the data corresponding to channel0+bank1 is the data that needs to be protected through the "ECC" flag, that is, it is determined that the first storage partition needs
  • the ECC circuit generates an error correction code corresponding to the first data (ie, the first error correction code);
  • the ECC circuit writes the error correction code corresponding to the first data into the second storage partition according to the third address;
  • the ECC circuit outputs the first data to the first memory through the write data line;
  • the storage controller may transparently output the first data to the first data through the ECC circuit memory.
  • the process of writing the first data by the storage controller to the first storage partition and the execution timing of the ECC circuit generating and storing the error correction code corresponding to the first data are not specifically limited.
  • FIG. 5 is a schematic diagram of a data reading process of a storage device in an embodiment of the present application. Then, referring to FIG. 5 , the data reading process may include the following steps:
  • S501 the storage controller receives a read instruction from a user side
  • the storage controller outputs a read operation instruction and a read address (that is, the second address of the second storage partition) to the first memory through the address line;
  • the first memory responds to the read operation instruction, and reads the second data (that is, the read data) from the second storage partition according to the read address;
  • S506 The ECC circuit determines whether the second data is data to be protected according to the read address; if so, obtains the fourth address of the fourth storage partition in the second memory, and executes S507; if not, executes S510.
  • the ECC circuit can take the high-order address of the write address (such as Channel ID+Bank address), and then use the high-order address to query the protection configuration information (as shown in FIG. 2 ), to determine whether the second data is data that needs to be protected.
  • the process of the ECC circuit determining whether the second data is data that needs to be protected is similar to the above-mentioned process of determining whether the first data is the data that needs to be protected, and will not be repeated here.
  • the ECC circuit reads the error correction code (ie, the second error correction code) corresponding to the second data from the fourth storage partition according to the fourth address;
  • S508 the ECC circuit checks the second data according to the error correction code; if the ECC circuit detects an error, execute S509; if the ECC circuit does not detect an error, execute S510;
  • the first data and the second data may include multiple bits.
  • the ECC circuit detects a unit (ie, 1 bit) error, execute S509.
  • the ECC circuit may output the second data or the error-corrected second data to the memory controller.
  • the first memory may transparently output the second data to the storage control via the ECC circuit device.
  • S511 The storage controller outputs the second data from the ECC circuit to the user side.
  • the error correction code storage partition is set in the second memory, and the second memory and the first memory belong to different die, so that the storage partition of the second memory can be flexibly allocated to the needs.
  • the storage partition of the first memory for data protection rather than all data storage partitions, is allocated an error correction code storage partition. In this way, the storage resources of the error correction code can be saved, thereby realizing flexible adjustment of the use of data protection according to actual needs and working conditions. area, thereby improving the utilization rate of error correction code storage resources.
  • the error correction code storage partition is set in the second memory, and the second memory and the first memory belong to different dies, so that the ECC circuit can determine that the first data and the second data are When the data needs to be protected, perform an ECC operation on the first data and the second data (such as generating an error correction code, performing error correction according to the error correction code, etc.), and when determining that the first data and the second data are data that do not require protection Data is transparently transmitted from time to time. In this way, the ECC operation can be selectively performed on the data, and the utilization rate of error correction code storage resources can be improved while ensuring effective data protection.
  • FIG. 6 is a schematic structural diagram of an ECC circuit in an embodiment of the present application.
  • the ECC circuit 304 may include: Analysis sub-module 3041 and generation sub-module 3042;
  • the above analysis submodule is configured to: obtain a write address from the storage controller; determine that the first data is the data to be protected according to the write address and the protection configuration information; output a first instruction to the generation submodule to instruct the generation of the first correction.
  • An error code; the generating sub-module is configured to: generate a first error correction code in response to the first instruction.
  • FIG. 7 is a schematic diagram of the work flow of the ECC circuit in the embodiment of the application in the data writing process.
  • the work process of the ECC circuit may include the following steps:
  • the analysis sub-module determines whether the first data is data that needs to be protected according to the write address and the protection configuration information; if so, execute S703, if not, do not respond;
  • the analysis submodule may query the write address in the preset protection configuration information; when the query result indicates that the write address needs data protection, it may determine that the first data is the data that needs to be protected.
  • the generating submodule responds to the first instruction and generates an error correction code corresponding to the first data
  • the generation submodule writes the error correction code corresponding to the first data into the second storage module.
  • the analysis sub-module may also obtain the corresponding write address through the protection configuration information 's third address. Then, the analyzing sub-module outputs the third address to the generating sub-module through the first instruction. Next, when the generation sub-module executes S706, the error correction code corresponding to the first data is written into the third storage partition in the second memory according to the third address.
  • the ECC circuit 304 may further include: a check sub-module 3043;
  • the above-mentioned analysis sub-module is also configured to: obtain a read address; according to the read address, determine that the second data is the data to be protected; output a second instruction to the inspection sub-module to instruct to read the second error correction code; check the sub-module , which is configured to read the second error correction code from the second memory in response to the second instruction.
  • FIG. 8 is a schematic diagram of the work flow of the ECC circuit in the embodiment of the application in the data read process.
  • the work process of the ECC circuit may include the following steps:
  • S802 The analysis sub-module determines whether the second data is data to be protected according to the read address; if so, execute S803; if not, execute S808;
  • the analysis submodule may query the read address in the preset protection configuration information; when the query result indicates that data protection is required for the read address, it may determine that the second data is the data to be protected.
  • the check sub-module responds to the second instruction and reads the error correction code corresponding to the second data from the second memory;
  • the checking sub-module checks the second data according to the error correction code; if a 1-bit error is detected, execute S807; if no error is detected, execute S808;
  • S808 The checking sub-module outputs the error-corrected second data to the storage controller.
  • the analysis sub-module may also obtain the corresponding read address through the protection configuration information 's fourth address. Then, the analyzing sub-module outputs the fourth address to the checking sub-module through the second instruction. Next, when the checking sub-module executes S805, the error correction code corresponding to the second data is read from the fourth storage partition in the second memory according to the fourth address.
  • the analysis sub-module is further configured to control whether the ECC circuit works when the storage device is in a working state, thereby enabling or disabling the data protection function of the storage device.
  • FIG. 9 is another schematic structural diagram of a storage device in an embodiment of the present application.
  • a process of reading and writing data of the storage device may be as follows.
  • the first step the storage controller 303 receives the write instruction from the user side
  • the storage controller 303 outputs the write operation instruction and the write address (eg, channel0+bank1) to the first memory 301 through the address line;
  • the storage controller 303 outputs the write address to the analysis sub-module 2021;
  • the DRAM controller that is, the storage controller 303
  • the DRAM controller receives the user's write instruction
  • it issues a corresponding operation instruction according to the DRAM timing requirements, and at the same time sends the DRAM write address to the ECC address analysis module (that is, the analysis sub-module 2021). ).
  • the storage controller 303 outputs the write data to the generation sub-module 2022 through the write data line;
  • the fifth step, the analysis submodule 2021 queries the write address in the table of FIG. 2, determines that the storage partition whose address is channel0+bank1 needs data protection, and obtains the corresponding SRAM partition address, namely zone0;
  • the analysis sub-module 2021 sends the first command and the SRAM partition address zone0 to the generation sub-module 2022; here, the first command is used to instruct the generation of the ECC code.
  • the ECC address analysis module when the ECC address analysis module receives the write command from the DRAM controller, it can analyze the access address in the write command. Use the high-order address of this write operation (such as 3-bit channel ID + 6-bit Bank address BA5 ⁇ BA0) to find an ECC configuration table (that is, protection configuration information). If the corresponding table entry indicates that the address segment needs ECC, the write operation belongs to the segment that needs ECC protection, and an ECC SRAM partition number can be obtained. If it is identified that the write operation belongs to a section that needs ECC protection, the ECC address analysis module will send an ECC instruction to the ECC generation module (ie, the generation sub-module) and the used ECC SRAM area number (ie, the SRAM partition address).
  • the ECC generation module ie, the generation sub-module
  • the used ECC SRAM area number ie, the SRAM partition address
  • the generating submodule 2022 responds to the first instruction and generates an error correction code corresponding to the first data
  • the eighth step, the generation submodule 2022 writes the error correction code corresponding to the first data into zone0;
  • the ninth step the storage controller 303 outputs the first data to the first memory 301 through the write data line;
  • the ECC generation module performs ECC calculation according to the ECC instruction of the ECC address analysis module, and generates a corresponding ECC check bit (ie, the first error correction code) in units of certain data bits.
  • the generated ECC check bits are sent to the ECC storage resource pool module (ie, the second memory) for processing.
  • the write data is sent to the DRAM die (that is, the first memory) and stored in the corresponding DRAM storage unit (that is, the first storage partition).
  • the first memory 301 responds to the write operation command and writes the first data into channel0+bank1.
  • the ECC storage resource pool module receives the ECC indication from the ECC address analysis module, it can write the ECC check bit sent by the ECC generation module into the corresponding SRAM ECC storage address (SRAM storage address). The address is the same as the DRAM lower address). If the ECC storage resource pool module does not receive the ECC indication from the ECC address analysis module, it means that the address of this write operation does not belong to the segment that needs ECC protection, and no operation is performed.
  • the first step the storage controller 303 receives the read instruction from the user side
  • the storage controller 303 outputs the read operation instruction and the read address (such as channel0+bank63) to the first memory 301 through the address line;
  • the storage controller 303 outputs the read address to the analysis sub-module 2021;
  • the DRAM die receives a read command to read data from the data storage area.
  • the address of the read operation is sent to the ECC address analysis module.
  • the fourth step, the analysis submodule 2021 queries the read address in the table of FIG. 2, determines that the DRAM partition whose address is channel0+bank63 needs data protection, and obtains the corresponding SRAM storage partition address, namely zone1;
  • the analysis sub-module 2021 sends the second instruction and the SRAM partition address zone1 to the checking sub-module 2023; here, the second instruction is used to instruct to read the ECC code.
  • the ECC address analysis module when the ECC address analysis module receives the read operation address controlled by the DRAM, it will analyze the high-order address in it, and use the high-order address of the read operation (such as 3-bit channel ID+6-bit Bank address BA5 ⁇ BA0) Find an ECC configuration table. If the corresponding table entry indicates that the address segment needs ECC, the read operation belongs to the segment that requires ECC protection, and an ECC SRAM partition number can be obtained. The ECC address analysis module will issue the ECC instruction that needs ECC inspection and the used ECC SRAM area number to the ECC inspection module and the ECC storage resource pool module. If an address identified for a read operation does not belong to a sector requiring ECC protection, no ECC indication will be issued.
  • the high-order address of the read operation such as 3-bit channel ID+6-bit Bank address BA5 ⁇ BA0
  • the inspection sub-module 2023 responds to the second instruction and reads the error correction code corresponding to the second data from zone1;
  • the ECC storage resource pool module when the ECC storage resource pool module receives the read operation ECC instruction sent by the ECC address analysis module, it will send the corresponding ECC data read from the SRAM that stores the ECC data to the ECC check module.
  • the first memory 301 reads the second data from channel0+bank63 and outputs it to the checking sub-module 2023;
  • the read data of the DRAM sends the DRAM data of the read operation to the ECC check module according to the chip working sequence.
  • the eighth step, the checking submodule 2023 checks the second data according to the error correction code
  • the ninth step if the error of 1 bit is checked, the checking sub-module 2023 performs error correction on the second data;
  • the tenth step the checking sub-module 2023 outputs the error-corrected second data to the storage controller 201;
  • the ECC check module receives the data bits read from the DRAM, and also receives the ECC check bit from the ECC storage resource pool module and the ECC indication from the ECC address analysis module, the ECC calculation check will be performed. . If a single-bit ECC error is detected, the data can be corrected and sent to the DRAM controller. If the ECC check module does not receive the ECC instruction sent by the ECC address analysis module when it receives the data bits read from the DRAM, it does not need to perform the ECC calculation check and directly sends the data to the DRAM controller.
  • the storage controller 201 outputs the second data to the user side.
  • the DRAM controller returns the read data that has undergone ECC check/error correction to the user side.
  • the above storage device may be packaged in but not limited to the following manners.
  • FIG. 10 is a schematic diagram of the first packaging of the storage device in the embodiment of the present application.
  • the first memory 301 , the second memory 302 , the storage controller 303 and the ECC circuit 304 are installed in the same The packaging substrate 11, wherein the memory controller 303, the ECC circuit 304 and the second memory 302 are integrated into the same bare chip a (eg logic die or basic die).
  • the first memory 301 is integrated into another bare chip b (eg, a DRAM die) and mounted on the package substrate 12 .
  • the ECC circuit 304 can communicate with the second memory 302 through an on-chip high-speed bus interface.
  • FIG. 11 is a schematic diagram of the second packaging of the storage device in the embodiment of the application.
  • the first memory 301 , the second memory 302 , the storage controller 303 and the ECC circuit 304 are installed in the same The package substrate 21, wherein the storage controller 303 and the ECC circuit 304 are integrated into a bare die c (eg logic die or basic die), and the second memory 302 is integrated into a bare die d (eg SRAM die).
  • the first memory 301 is integrated into another die e (eg, a DRAM die).
  • the ECC circuit 304 can communicate with the second memory 302 through a high-speed interconnect interface such as die-to-die phy.
  • FIG. 12 is a schematic diagram of the third packaging of the storage device in the embodiment of the present application.
  • the storage controller 303 , the ECC circuit 304 and the second memory 302 are mounted on the packaging substrate 31 , and the storage controller 303, the ECC circuit 304 and the second memory 302 are integrated in the same bare chip f (eg logic die or basic die).
  • the first memory 301 is integrated into another bare chip g (eg, a DRAM die) and mounted on the package substrate 32 .
  • the ECC circuit 304 can communicate with the second memory 302 through an on-chip high-speed bus interface.
  • FIG. 13 is a schematic diagram of the fourth packaging of the storage device in the embodiment of the present application.
  • the storage controller 303 and the ECC circuit 304 are integrated in the same bare chip h (such as a logic die or a basic die). ) and mounted on the package substrate 41 .
  • the second memory 302 is integrated on a bare chip i (eg, an SRAM die) and mounted on the package substrate 42 .
  • the first memory 301 is integrated into a bare chip j (eg, a DRAM die) and mounted on the package substrate 43 .
  • the ECC circuit 304 can communicate with the second memory 302 through a high-speed interconnect interface such as serdes phy.
  • FIG. 14 is a schematic diagram of the fifth packaging of the storage device in the embodiment of the application.
  • the storage controller 303 is integrated into a bare chip k (such as a logic die or a basic die), and is installed on the Package substrate 51 .
  • the ECC circuit 304 and the second memory 302 are integrated on the die 1 and the die m, and are mounted on the package substrate 52.
  • the first memory 301 is integrated into a bare die n (eg, a DRAM die) and mounted on the package substrate 53 .
  • the ECC circuit 304 can communicate with the second memory 302 through a high-speed interconnect interface such as die-to-die phy.
  • the above storage device may also have other packaging manners, which are not specifically limited in this embodiment of the present application.
  • an embodiment of the present application further provides an error correction apparatus, including: the ECC circuit shown in FIG. 2 to FIG. 9 and the second memory.
  • the ECC circuit and the second memory may be packaged in the packaging manner shown in FIG. 14 .
  • an embodiment of the present application further provides a storage control device, including: the storage controller and the ECC circuit shown in FIG. 2 to FIG. 9 above.
  • the storage controller and the ECC circuit may be packaged in the packaging manner shown in FIG. 11 or 13 .
  • embodiments of the present application further provide a system on chip (SOC), which may include a processor, a bus, and the storage device shown in FIG. 2 to FIG. 9 above. Therein, a processor and a storage device are coupled to the bus.
  • SOC system on chip
  • the processor is configured to: output a write command and first data to the storage device through the bus, or output a read command to the storage device through the bus, and receive second data output from the storage device through the bus.
  • the processor may be a general-purpose central processing unit (CPU), a microprocessor, an application-specific integrated circuit (ASIC), or the like.
  • CPU central processing unit
  • ASIC application-specific integrated circuit
  • an electronic device which can be a computing device, such as a server; the electronic device can also be a storage device, such as a storage array; the electronic device can also be a network device, such as switches, etc.
  • FIG. 15 is a hardware schematic diagram of an electronic device in an embodiment of the application.
  • the electronic device 1500 may include a processor 1501 , a storage device 1502 , a bus 1503 , an input device 1504 , an output device 1505 , and an antenna system 1506 .
  • the storage device 1502 is consistent with the storage device described in one or more of the above embodiments. Further, the above-mentioned processor 1501 may be consistent with the system-on-chip described in the above-mentioned embodiment.
  • Storage 1502 may store program instructions, such as operating systems, application programs, other program modules, executable code, program data, user data, and the like.
  • Input device 1504 may be used to input commands and information to electronic device 1500, such as a keyboard or pointing device such as a mouse, trackball, touchpad, microphone, joystick, game pad, satellite dish, scanner, or similar device . These input devices may be connected to processor 1501 through bus 1503 .
  • the output device 1505 can be used for the electronic device 1500 to output information.
  • the output device 1505 can also be other peripheral output devices, such as speakers and/or printing devices. These output devices can also be connected to the processor 1501 through the bus 1503. .
  • the electronic device may also have other functional devices, which are not specifically limited in the embodiments of the present application.
  • an embodiment of the present application further provides a data storage method, which can be applied to the storage device described in one or more of the foregoing embodiments.
  • the method may include: the storage controller writes data to the first memory, and reads data from the first memory, wherein the first memory and the second memory belong to different dies, and the second memory is used for storing data corresponding to The error correction code is used for data protection of data.
  • the data includes first data and second data; the foregoing storage controller writing data to the first memory includes: the storage controller writing the first data to the first memory;
  • the above-mentioned memory controller reading data from the first memory includes: the memory controller reading the second data from the first memory.
  • the above method further includes: the ECC circuit generates a first error correction code corresponding to the first data; or, the ECC circuit performs error correction on the second data according to the second error correction code in the second memory, and the second error correction code is the error correction code corresponding to the second data.
  • the above-mentioned ECC circuit generates a first error correction code corresponding to the first data, including: when it is determined that the first data is data that needs to be protected, the ECC circuit generates a first error correction code;
  • the above-mentioned ECC circuit performs error correction on the second data according to the second error correction code in the second memory, including: when it is determined that the second data is data that needs to be protected, the ECC circuit corrects the second data according to the second error correction code. wrong.
  • the above method further includes: the ECC circuit determines whether the first data is data that needs to be protected according to the first address corresponding to the first data and preset protection configuration information; The second address corresponding to the data and the protection configuration information, to determine whether the second data is the data that needs to be protected; wherein, the protection configuration information includes the mapping relationship between the address of the storage partition in the first memory and the address of the storage partition in the second memory , and the storage partition of the second memory corresponds to the data to be protected.
  • the above-mentioned storage controller writing the first data to the first memory includes: the storage controller outputs the first address and the first data to the ECC circuit; the ECC circuit converts the first data to the ECC circuit according to the first address Write to the first storage partition of the first memory.
  • the above method further includes: the ECC circuit obtains a third address corresponding to the first address; according to the third address, writing the first error correction code into the third address The second storage partition in the second memory.
  • the above method further includes: when it is determined that the first data is data that does not require protection, the ECC circuit writes the first data into the first memory.
  • the above-mentioned storage controller reads the second data from the first memory, including: the storage controller outputs the second address to the ECC circuit; the ECC circuit stores the third data from the first memory according to the second address The second data is read in the partition; the ECC circuit outputs the second data to the memory controller.
  • the above-mentioned ECC circuit outputs the second data to the memory controller, including: the ECC circuit checks the second data according to the second error correction code; if an error is detected, error correction is performed on the second data , and output the error-corrected second data to the storage controller; if no error is detected, output the second data to the storage controller.
  • the above method when it is determined that the second data is data that needs to be protected, the above method further includes: the ECC circuit obtains a fourth address corresponding to the second address; Four memory partitions read the second error correction code.
  • the above method further includes: when it is determined that the second data is data that does not require protection, the ECC circuit outputs the second data to the memory controller.
  • an embodiment of the present application further provides a data storage method, which can be applied to the storage control apparatus described in one or more of the foregoing embodiments.
  • the method can include:
  • the storage control device writes the first data to the first memory, and reads the second data from the first memory; when it is determined that the first data is data that needs to be protected, the storage control device generates a first error correction code; and, when it is determined When the second data is data that needs to be protected, the storage control device performs error correction on the second data according to the second error correction code.
  • the above method further includes: the storage control device determines whether the first data is data that needs to be protected according to the first address corresponding to the first data and preset protection configuration information; The second address corresponding to the second data and the protection configuration information are used to determine whether the second data is data that needs to be protected; wherein, the protection configuration information includes an address between the address of the storage partition in the first memory and the address of the storage partition in the second memory.
  • the mapping relationship, the storage partition of the second memory corresponds to the data to be protected.
  • the above-mentioned storage control apparatus writing the first data to the first memory includes: the storage control apparatus writes the first data into the first storage partition of the first memory according to the first address.
  • the above method further includes: the storage control apparatus obtains a third address corresponding to the first address; and writes the first error correction code according to the third address into the second storage partition in the second memory.
  • the above method further includes: when it is determined that the first data is data that does not require protection, the storage control apparatus writes the first data into the first memory.
  • the above-mentioned storage control apparatus reads the second data from the first memory, including: the storage controller reads the second data from the third storage partition of the first memory according to the second address.
  • the above-mentioned storage control device reads the second data from the first memory, including: the storage control device checks the second data according to the second error correction code; if an error is detected, the storage control device checks the second data. The second data is subjected to error correction, and the error-corrected second data is obtained; if no error is detected, the storage control device obtains the second data.
  • the above method before the storage control apparatus performs error correction on the second data, the above method further includes: when it is determined that the second data is data to be protected, the storage control apparatus obtains a fourth address corresponding to the second address ; The storage control device reads the second error correction code from the fourth storage partition in the second memory according to the fourth address.
  • the above method further includes: when it is determined that the second data is data that does not require protection, the storage control apparatus reads the second data.
  • the above-described embodiments may be implemented in whole or in part by software, hardware, firmware or any other combination.
  • the above-described embodiments may be implemented in whole or in part in the form of a computer program product.
  • the computer program product includes one or more computer instructions. When the computer program instructions are loaded or executed on a computer, all or part of the processes or functions described in the embodiments of the present application are generated.
  • the computer may be a general purpose computer, special purpose computer, computer network, or other programmable device.
  • the computer instructions may be stored in or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be downloaded from a website site, computer, server, or data center Transmission to another website site, computer, server, or data center is by wire (eg, coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (eg, infrared, wireless, microwave, etc.).
  • the computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server, a data center, or the like that contains one or more sets of available media.
  • the usable media may be magnetic media (eg, floppy disks, hard disks, magnetic tapes), optical media (eg, DVDs), or semiconductor media.
  • the semiconductor medium may be a solid state drive (SSD).

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Abstract

本申请提供一种存储装置、存储控制装置及片上系统。该存储装置包括：第一存储器，被配置为存储数据；第二存储器，被配置为存储所述数据对应的纠错码，所述纠错码用于对所述数据进行数据保护；存储控制器，被配置为：向所述第一存储器写入所述数据；以及从所述第一存储器读取所述数据；其中，所述第一存储器与所述第二存储器属于不同裸片。在本申请中，由于第一存储器和第二存储器属于不同的裸片(die)，避免纠错码占用第一存储器中的存储空间，提高第一存储器中可用数据的容量。

Description

一种存储装置、存储控制装置及片上系统 技术领域
本申请涉及存储领域，特别涉及一种存储装置、存储控制装置及片上系统。
背景技术
随着科技的发展，动态随机存取存储器(dynamic random access memory，DRAM)芯片规模越来越大，工作频率越来越高。DRAM芯片在工作状态下，可能存在不同程度的局部软失效概率。为了避免软失效带来的数据读写错误，DRAM芯片中采用错误检查和纠正技术对软失效的数据进行数据保护。
目前，DRAM的数据保护技术一般会在DRAM芯片中配置独立的纠错码(error correcting code，ECC)存储分区，ECC存储分区一般均匀部署在DRAM存储分区附近。但是，由于ECC存储分区会占用DRAM芯片的存储空间，使得DRAM芯片中可用数据的容量较少。
发明内容
本申请提供了一种存储装置、存储控制装置及片上系统，以避免纠错码占用第一存储器中的存储空间，提高第一存储器中可用数据的容量。
第一方面，本申请提供一种存储装置，包括：第一存储器，被配置为存储数据；第二存储器，被配置为存储数据对应的纠错码，纠错码用于对数据进行数据保护；存储控制器，被配置为：向第一存储器写入数据；以及从第一存储器读取数据；其中，第一存储器与第二存储器属于不同裸片。
其中，存储控制器和第一存储器通过地址线和数据线(包括写数据线和读数据线)耦合，存储控制器可以被配置为通过地址线和写数据线向第一存储器写入第一数据或者通过地址线和读数据线从第一存储器读取第二数据。
示例性的，第一存储器可以为DRAM。第一存储器可以包括一个或者多个DRAM die，例如可以为于3D(3 dimension)堆叠的多个DRAM die。可选的，第一存储器还可以为基于3D堆叠的静态随机存取存储器(static random-access memory，SRAM)、非易失性存储器(non-volatile memory，NVM)等存储器。
示例性的，第二存储器可以为SRAM。第二存储器可以包括一个或者多个SRAM die。
在本申请中，通过将第一存储器和第二存储器集成于不同的裸片(die)，将纠错码存储在第二存储器中，即纠错码的存储区域集中在第一存储器之外的第二存储器 中，如此，避免纠错码占用第一存储器中的存储空间，提高第一存储器中可用数据的容量。例如，在DRAM场景下，纠错码存储于第二存储器(如SRAM)，第二存储器与第一存储器(如DRAM)属于不同的die，那么，在DRAM die中不需要为纠错码分配存储区域，避免纠错码占用DRAM die中的存储空间，进而提高DRAM die上可用数据的容量。
进一步地，在现有技术中，纠错码存储分区与数据存储分区设置于同一个die，纠错码只能够对同一个die上的数据进行数据保护。而在本申请中，由于数据存储分区设置于第一存储器，纠错码存储分区设置于第二存储器，第二存储器与第一存储器属于不同的die，这样，第二存储器中的纠错码就可以为一个或者多个第一存储器中的数据进行数据保护，进而实现多个第一存储器共享一个第二存储器，也可以理解为实现纠错码全局共享。
另外，在现有技术中，由于第一存储器的软失效与实际应用场景相关，是无法预期哪些数据存储分区出现软失效的概率大，所以，只能给所有数据存储分区都配置纠错码存储分区。但是，这样的话，对于不会出现软失效的数据存储分区，或者对数据软失效不敏感(容错强)的应用场景来说，为所有数据存储分区配置的纠错码存储分区是浪费的。而在本申请中，由于数据存储分区设置于第一存储器，纠错码存储分区设置于第二存储器，第二存储器与第一存储器属于不同的die，使得第二存储器的存储分区能够灵活地分配给实际需要数据保护的第一存储器的存储分区，而不是所有的数据存储分区都会分配纠错码存储分区，这样，可以节省纠错码的存储资源，从而实现根据实际需求和工作状态灵活调整使用数据保护的区域，进而提高纠错码存储资源的利用率。
在一些可能的实施方式中，上述数据包括第一数据和第二数据，上述存储装置，还包括：错误检查和纠正(error checking and correction，ECC)电路，被配置为：生成第一数据对应的第一纠错码；以及根据第二存储器中的第二纠错码对第二数据进行纠错；第二纠错码为第二数据对应的纠错码；存储控制器，具体被配置：为向第一存储器写入第一数据，以及从第一存储器读取第二数据。
在一些可能的实施方式中，ECC电路，还被配置为：当确定第一数据为需要保护的数据时，生成第一纠错码；以及当确定第二数据为需要保护的数据时，根据第二纠错码对第二数据进行纠错。
在一些可能的实施方式中，ECC电路，还被配置为：当确定第一数据为不需要保护的数据时，根据第一地址，将第一数据写入第一存储分区。
在一些可能的实施方式中，ECC电路，还被配置为：当确定第二数据为不需要保护的数据时，根据第二地址，向存储控制器输出第二数据。
在本申请中，ECC电路在确定第一数据和第二数据为需要保护的数据时，对第一数据和第二数据进行ECC操作(如生成纠错码)，如此，实现选择性的对数据进行ECC操作，在保证有效的数据保护的同时提高纠错码存储资源的利用率。
在一些可能的实施方式中，ECC电路，被配置为根据第一数据对应的第一地址和预设的保护配置信息，确定第一数据是否为需要保护的数据；以及根据第二数据对应的第二地址和保护配置信息，确定第二数据是否为需要保护的数据；其中，保护配置信息包括第一存储器中存储分区与第二存储器中存储分区之间的映射关系，第二存储器的存储分区与需要保护的数据对应。
在本申请中，可以设置可配置的保护配置信息，通过配置该保护配置信息，改变第一存储器中存储分区与第二存储器中存储分区之间的映射关系，使得第二存储器的存储分区能够灵活地分配给需要保护的第一存储器的存储分区，而不需要固定的与所有数据存储分区对应。这样，对于访问量较少的数据存储分区，可以不配置相应的纠错码存储资源，以节省纠错码存储资源，从而实现根据实际需求和工作状态调整使用数据保护的区域，进而提高纠错码存储资源的利用率。
在一些可能的实施方式中，存储控制器，被配置为向ECC电路输出第一地址和第一数据；ECC电路，还被配置为：将第一纠错码写入第二存储器；根据第一地址，将第一数据写入第一存储器的第一存储分区。
在一些可能的实施方式中，ECC电路，还被配置为：当确定第一数据为不需要保护的数据时，获取第一地址对应的第三地址；根据第三地址，将第一纠错码写入第二存储器中的第二存储分区，以此实现对第一数据的保护。
在一些可能的实施方式中，ECC电路，还被配置为：当确定第二数据为需要保护的数据时，获取第二地址对应的第四地址；根据第四地址，从第二存储器中第四存储分区读取第二纠错码，以此实现对第二数据的保护。
在一些可能的实施方式中，存储控制器，还被配置为向ECC电路输出第二地址；ECC电路，还被配置为：根据第二地址，从第一存储器的第三存储分区中读取第二数据；向存储控制器输出第二数据。
在一些可能的实施方式中，ECC电路，被配置为：根据第二纠错码对第二数据进行检查；若检查出错误，则对第二数据进行纠错，并向存储控制器输出纠错后的第二数据；若未检查出错误，则向存储控制器输出第二数据。
在本申请中，ECC电路在确定第一数据和第二数据为需要保护的数据时，对第一数据和第二数据进行ECC操作(如根据纠错码进行纠错)，如此，实现选择性的对数据进行ECC操作，在保证有效的数据保护的同时提高纠错码存储资源的利用率。
在一些可能的实施方式中，ECC电路，被配置为：当确定第二数据为不需要保护的 数据时，向存储控制器输出第二数据。
在一些可能的实施方式中，ECC电路与第二存储器属于同一裸片；或者，ECC电路与第二存储器属于不同裸片。
在一些可能的实施方式中，ECC电路与存储控制器属于不同裸片；或者，ECC电路与存储控制器属于同一裸片。
在一些可能的实施方式中，第一存储器中各个存储分区的低位地址与第二存储器中各个存储分区的存储地址相同。
第二方面，本申请提供一种存储控制装置，可以包括：存储控制器和ECC电路；其中，存储控制器，被配置为向第一存储器写入第一数据，以及从第一存储器读取第二数据；ECC电路，被配置为：当确定第一数据为需要保护的数据时，生成第一纠错码；以及当确定第二数据为需要保护的数据时，根据第二纠错码对第二数据进行纠错。
在本申请中，ECC电路在确定第一数据和第二数据为需要保护的数据时，对第一数据和第二数据进行ECC操作(如生成纠错码、根据纠错码进行纠错等)，如此，实现选择性的对数据进行ECC操作，在保证有效的数据保护的同时提高纠错码存储资源的利用率。
在一些可能的实施方式中，ECC电路，被配置为根据第一数据对应的第一地址和预设的保护配置信息，确定第一数据是否为需要保护的数据；以及根据第二数据对应的第二地址和保护配置信息，确定第二数据是否为需要保护的数据；其中，保护配置信息包括第一存储器中存储分区的地址与第二存储器中存储分区的地址之间的映射关系，第二存储器的存储分区与需要保护的数据对应。
在一些可能的实施方式中，存储控制器，被配置为向ECC电路输出第一地址和第一数据；ECC电路，还被配置为：将第一纠错码写入第二存储器；根据第一地址，将第一数据写入第一存储器的第一存储分区。
在一些可能的实施方式中，ECC电路，还被配置为：当确定第一数据为需要保护的数据时，获取第一地址对应的第三地址；根据第三地址，将第一纠错码写入第二存储器中的第二存储分区。
在一些可能的实施方式中，ECC电路，还被配置为：当确定第一数据为不需要保护的数据时，根据第一地址，将第一数据写入第一存储分区。
在一些可能的实施方式中，存储控制器，还被配置为向ECC电路输出第二地址；ECC电路，还被配置为：根据第二地址，从第一存储器的第三存储分区中读取第二数据；向存储控制器输出第二数据。
在一些可能的实施方式中，ECC电路，被配置为：根据第二纠错码对第二数据进行检查；若检查出错误，则对第二数据进行纠错，并向存储控制器输出纠错后的第二数 据；若未检查出错误，则向存储控制器输出第二数据。
在一些可能的实施方式中，ECC电路，还被配置为：当确定第二数据为需要保护的数据时，获取第二地址对应的第四地址；根据第四地址，从第二存储器中第四存储分区读取第二纠错码。
在一些可能的实施方式中，ECC电路，被配置为：当确定第二数据为不需要保护的数据时，向存储控制器输出第二数据。
在一些可能的实施方式中，ECC电路与第二存储器属于同一裸片；或者，ECC电路与第二存储器属于不同裸片。
在一些可能的实施方式中，ECC电路与存储控制器属于不同裸片；或者，ECC电路与存储控制器属于同一裸片。
第三方面，本申请提供一种片上系统，包括：处理器、总线以及第一方面及其可能的实施方式中任一项的存储装置；
处理器，被配置为：通过总线向存储装置输出写指令及第一数据，或者通过总线向存储装置输出读指令，并通过总线接收存储装置输出的第二数据；写指令用于指示向第一存储区域写入第一数据，读指令用于指示从第二存储区域读取第二数据。
第四方面，本申请提供一种数据存储方法，可以应用于上述第一方面及其可能的实施方式中任一项所述的存储装置。那么，该方法可以包括：存储控制器向第一存储器写入数据，以及从第一存储器读取数据，其中，第一存储器与第二存储器属于不同的裸片，第二存储器用于存储数据对应的纠错码，纠错码用于对数据进行数据保护。
在一些可能的实施方式中，数据包括第一数据和第二数据；上述存储控制器向第一存储器写入数据，包括：存储控制器向第一存储器写入第一数据；
上述存储器控制器从第一存储器读取数据，包括：存储控制器从第一存储器读取第二数据。
相应地，上述方法还包括：ECC电路生成第一数据对应的第一纠错码；或者，ECC电路根据第二存储器中的第二纠错码对第二数据进行纠错，第二纠错码为第二数据对应的纠错码。
在一些可能的实施方式中，上述ECC电路生成第一数据对应的第一纠错码，包括：当确定第一数据为需要保护的数据时，ECC电路生成第一纠错码；
上述ECC电路根据第二存储器中的第二纠错码对第二数据进行纠错，包括：当确定第二数据为需要保护的数据时，ECC电路根据第二纠错码对第二数据进行纠错。
在一些可能的实施方式中，上述方法还包括：ECC电路根据第一数据对应的第一地址和预设的保护配置信息，确定第一数据是否为需要保护的数据；或者，ECC电路根据第二数据对应的第二地址和保护配置信息，确定第二数据是否为需要保护的数 据；其中，保护配置信息包括第一存储器中存储分区的地址与第二存储器中存储分区的地址之间的映射关系，第二存储器的存储分区与需要保护的数据对应。
在一些可能的实施方式中，上述存储控制器向第一存储器写入第一数据，包括：存储控制器向ECC电路输出第一地址和第一数据；ECC电路根据第一地址，将第一数据写入第一存储器的第一存储分区。
在一些可能的实施方式中，在ECC电路生成第一纠错码之后，上述方法还包括：ECC电路获取第一地址对应的第三地址；根据第三地址，将第一纠错码写入第二存储器中的第二存储分区。
在一些可能的实施方式中，上述方法还包括：当确定第一数据为不需要保护的数据时，ECC电路将第一数据写入第一存储器。
在一些可能的实施方式中，上述存储控制器从第一存储器读取第二数据，包括：存储控制器向ECC电路输出第二地址；ECC电路根据第二地址，从第一存储器的第三存储分区中读取第二数据；ECC电路向存储控制器输出第二数据。
在一些可能的实施方式中，上述ECC电路向存储控制器输出第二数据，包括：ECC电路根据第二纠错码对第二数据进行检查；若检查出错误，则对第二数据进行纠错，并向存储控制器输出纠错后的第二数据；若未检查出错误，则向存储控制器输出第二数据。
在一些可能的实施方式中，当确定所述第二数据为需要保护的数据时，上述方法还包括：ECC电路获取第二地址对应的第四地址；根据第四地址，从第二存储器中第四存储分区读取第二纠错码。
在一些可能的实施方式中，上述方法还包括：当确定第二数据为不需要保护的数据时，ECC电路向存储控制器输出第二数据。
第五方面，本申请提供一种数据存储方法，可以应用于上述第二方面及其可能的实施方式中任一项所述的存储控制装置。那么，该方法可以包括：
存储控制装置向第一存储器写入第一数据，以及从第一存储器读取第二数据；
当确定第一数据为需要保护的数据时，存储控制装置生成第一纠错码；以及，
当确定第二数据为需要保护的数据时，存储控制装置根据第二纠错码对第二数据进行纠错。
在一些可能的实施方式中，上述方法还包括：存储控制装置根据第一数据对应的第一地址和预设的保护配置信息，确定第一数据是否为需要保护的数据；以及，
存储控制装置根据第二数据对应的第二地址和保护配置信息，确定第二数据是否为需要保护的数据；
其中，保护配置信息包括第一存储器中存储分区的地址与第二存储器中存储分 区的地址之间的映射关系，第二存储器的存储分区与进行保护的数据对应。
在一些可能的实施方式中，上述存储控制装置向第一存储器写入第一数据，包括：存储控制装置根据第一地址，将第一数据写入第一存储器的第一存储分区。
在一些可能的实施方式中，在存储控制装置生成第一纠错码之后，上述方法还包括：存储控制装置获取第一地址对应的第三地址；根据第三地址，将第一纠错码写入第二存储器中的第二存储分区。
在一些可能的实施方式中，上述方法还包括：当确定第一数据为不需要保护的数据时，存储控制装置将第一数据写入第一存储器。
在一些可能的实施方式中，上述存储控制装置从第一存储器读取第二数据，包括：存储控制器根据第二地址，从第一存储器的第三存储分区中读取第二数据。
在一些可能的实施方式中，上述存储控制装置从第一存储器读取第二数据，包括：存储控制装置根据第二纠错码对第二数据进行检查；若检查出错误，则存储控制装置对第二数据进行纠错，并获取纠错后的第二数据；若未检查出错误，则存储控制装置获取第二数据。
在一些可能的实施方式中，在存储控制装置对第二数据进行纠错之前，上述方法还包括：当确定第二数据为需要保护的数据时，存储控制装置获取第二地址对应的第四地址；存储控制装置根据第四地址，从第二存储器中第四存储分区读取第二纠错码。
在一些可能的实施方式中，上述方法还包括：当确定第二数据为不需要保护的数据时，存储控制装置读取第二数据。
第六方面，本申请提供一种电子设备，该电子设备包括：处理器、总线以及如第一方面及其任一项可能的实施方式所述的存储装置，处理器通过总线与所述存储装置耦合。
在一些可能的实施方式中，上述处理器可以包括如第三方面所述的片上系统。
在一些可能的实施方式中，上述存储装置还用于存储程序指令。上述处理器，被配置为：当电子设备运行时，处理器执行存储装置中存储的程序指令，以使电子设备实现相应的功能。
在一些可能的实施方式中，上述电子设备还包括：输入设备以及输出设备。其中，输入设备用于向电子设备输入命令和信息，输入设备通过总线连接至处理器。输出设备用于电子设备输出信息，输出设备也可以通过总线连接到处理器。
在一些可能的实施方式中，上述电子设备还包括：天线系统，该天线系统在处理器的控制下，收发无线通信信号实现与移动通信网络的无线通信。
应当理解的是，本申请的第二至六方面与本申请的第一方面的技术方案一致，各方 面及对应的可行实施方式所取得的有益效果相似，不再赘述。
附图说明
图1为本申请实施例中的DRAM芯片的示意图；
图2为本申请实施例中的保护配置信息的示意图；
图3为本申请实施例的存储装置的一种结构示意图；
图4为本申请实施例中的存储装置的写数据流程的示意图；
图5为本申请实施例中的存储装置的读数据流程的示意图；
图6为本申请实施例中的ECC电路的结构示意图；
图7为本申请实施例中的ECC电路在写数据过程中的工作流程示意图；
图8为本申请实施例中的ECC电路在读数据过程中的工作流程示意图；
图9为本申请实施例中的存储装置的另一种结构示意图；
图10为本申请实施例中的存储装置的第一种封装示意图；
图11为本申请实施例中的存储装置的第二种封装示意图
图12为本申请实施例中的存储装置的第三种封装示意图；
图13为本申请实施例中的存储装置的第四种封装示意图；
图14为本申请实施例中的存储装置的第五种封装示意图；
图15为本申请实施例中的电子设备的硬件示意图。
具体实施方式
下面结合本申请实施例中的附图对本申请实施例进行描述。以下描述中，参考形成本申请一部分并以说明之方式示出本申请实施例的具体方面或可使用本申请实施例的具体方面的附图。
动态随机存取存储器(dynamic random access memory，DRAM)是一种大容量高密度的半导体存储器。随着DRAM芯片规模越来越大，工作频率越来越高。DRAM芯片在工作状态下，因为电子设备内部的电磁干扰等会导致DRAM芯片中单位(cell)自发地变成相反的状态(此时数据软失效)。这种单位错误可能是隐性的，也就是说，不会对数据造成严重影响；但是，DRAM芯片中的各个存储分区(bank)是相互关联的，因此，单位错误会带来数据读写错误，进而可能会影响整个电子设备。那么，为了避免单位错误带来的数据读写错误，DRAM芯片中通常采用如错误检查和纠正(error checking and correction，ECC)技术对软失效的数据进行纠错。
ECC技术是一种数据保护手段，主要的功能是发现并纠正错误。ECC技术需要额外的存储分区来储存纠错码，但纠错码所占用的位数跟数据的长度并非成线性关系。具体来 说，ECC技术是以8位数据、5位纠错码为基准，随后每增加一个8位数据只需另增加一位纠错码即可。举例来说，一个8bit的数据产生的纠错码要占用5bit的空间，而一个16bit数据对应的纠错码只需在8bit数据对应的纠错码占用的空间的基础上再增加一位，也就是6bit；而32bit的数据则只需再在16bit数据对应的纠错码占用的空间的基础上增加1bit，即7bit的纠错码即可，如此类推。一个K＝2n bit的数据产生的纠错码要占用(n+2)bit空间。当K＝64时，n＝6，则n+2＝8。因此，一般会在DRAM芯片中配置独立的ECC存储分区，ECC存储分区的地址与DRAM存储分区的地址相同。
图1为本申请实施例中的DRAM芯片的一种示例结构示意图，参见图1所示，DRAM芯片100可以包括：DRAM控制器101、ECC电路102、DRAM存储分区103以及ECC存储分区104。DRAM存储分区103与ECC存储分区104可以按照如数据:纠错码(可以理解为数据长度与纠错码位数之比)＝8:1的比例进行部署。
具体来说，DRAM控制器101通过地址线A与DRAM存储分区103耦合，DRAM控制器101通过数据线(包括写数据线W和读数据线R)与ECC电路102耦合，ECC电路102通过数据线(包括写数据线W和读数据线R)与DRAM存储分区103和ECC存储分区104耦合。
上述ECC电路102可以包括ECC生成模块1021和ECC检查模块1022。ECC生成模块1021被配置为生成数据对应的纠错码，ECC检查模块1022被配置为对待纠错码进行检查，并在检查出1bit的错误时按照纠错码对待纠错码进行纠错。
在实际封装中，DRAM芯片100可以包括：逻辑裸片(logic die/basic die)111和至少一个DRAM die 112，上述DRAM控制器101和ECC电路102可以集成于logic die 111，上述DRAM存储分区103以及ECC存储分区104可以集成于一个DRAM die 112。logic die 111和每一个DRAM die 112均为单独封装，或者，logic die 111和DRAM die 112可以是2.5D(2.5 dimension)堆叠或3D(3 dimension)堆叠后的合封。当然，logic die和DRAM die还可以存在其他的实现形式，本申请实施例对此不做具体限定。
仍参考图1所示，上述DRAM芯片100的数据读写过程可以如下所示：
首先，写数据过程可以包括以下步骤：
步骤1、DRAM控制器101接收来自用户侧的写指令，并通过地址线A向DRAM die 112输出写操作指令和写地址；
步骤2、DRAM控制器101通过写数据线W将写数据输出至ECC电路102；
步骤3、ECC电路102为写数据生成对应的纠错码；
步骤4、ECC电路102通过写数据线W将写数据和对应的纠错码输出至DRAM die 112；
其中，写数据输出至DRAM存储分区103，纠错码输出至ECC存储分区104。
在实际应用中，DRAM芯片可以使用64bit的数据生成8bit的纠错码。
步骤5、DRAM die 112响应写操作指令，将写数据按照写地址写入DRAM存储分区103，并且将纠错码按照写地址写入ECC存储分区104。
其次，读数据过程可以包括以下步骤：
步骤1、DRAM控制器101接收来自用户侧的读指令，并通过地址线A向DRAM die 112输出读操作指令及读地址；
步骤2、DRAM die 112响应读操作指令，按照读地址从DRAM存储分区103和ECC存储分区104分别读取读数据和对应的纠错码；
步骤3、DRAM die 112通过读数据线R将读数据和对应的纠错码输出至ECC电路102；
步骤4、ECC电路102对读数据进行检查；
步骤5、如果ECC电路102检查出1bit的错误，ECC电路102根据纠错码对读数据进行纠错，并将纠错后的读数据通过读数据线R输出至DRAM控制器101；如果ECC电路102未检查出错误，ECC电路102将读数据通过读数据线R输出至DRAM控制器101；
步骤6、DRAM控制器101将来自ECC电路102的读数据输出给用户侧。
由上述可以看出，由于DRAM芯片的软失效与实际应用场景相关，是无法预期哪些DRAM分区出现软失效的概率大，只能给所有分区都配置ECC存储分区。这样的话，对于不会出现软失效的分区，或者对数据软失效不敏感(容错强)的应用场景，为所有分区配置的ECC存储分区实际上是浪费的，整体上提高了DRAM芯片的成本。
另外，有一些DRAM芯片可以支持将上述DRAM die中的ECC存储分区作为普通数据存储分区使用(也就是说使用ECC存储分区对DRAM存储分区扩容)，以提高DRAM芯片的可用容量。但是，在这样的应用场景中，DRAM die中可能不存在ECC存储分区，那么，针对于DRAM芯片的实际工作情况(如高温导致偶发软失效等)，DRAM存储分区中的数据无法得到有效的保护。
为了解决上述问题，本申请实施例提供一种存储装置，该存储装置可以包括：第一存储器、第二存储器以及存储控制器；其中，第一存储器与第二存储器属于不同的die，也就是说，第一存储器与第二存储器在物理上独立设置。
其中，第一存储器可以被配置为存储数据；第二存储器可以被配置为存储第一存储器中的数据对应的纠错码。存储控制器和第一存储器通过地址线和数据线(包括写数据线和读数据线)耦合，存储控制器可以被配置为通过地址线和写数据线向第一存储器写入第一数据或者通过地址线和读数据线从第一存储器读取第二数据。
示例性的，第一存储器可以以DRAM die的形式实现。第一存储器可以为一个或者多个DRAM die。
在一些可能的实施方式中，第一存储器还可以为基于3D堆叠的静态随机存取存储器(static random-access memory，SRAM)、非易失性存储器(non-volatile  memory，NVM)等存储器。
示例性的，第二存储器可以以SRAM die的形式实现。第二存储器可以为一个或者多个SRAM die。
当然，在实际应用中，第一存储器和第二存储器还可以采用其他形式实现，本申请实施例不做具体限定。
在本申请实施例中，通过将第一存储器和第二存储器集成于不同的die，使得数据和纠错码存储在不同的存储器中，那么，第一存储器中无需为纠错码分配存储分区，进而避免纠错码占用第一存储器的存储空间，提高第一存储器中可用数据的容量。示例性的，在DRAM场景下，与图1实施例不同的是，第一存储器(如DRAM)和第二存储器(如SRAM)集成于不同的die，数据和对应的纠错码分别存储于第一存储器和第二存储器，这样，在DRAM中就无需为纠错码分配相应的存储空间，以此减少DRAM中固定配置的纠错码存储空间，进而提高DRAM可用数据容量。
进一步地，由于数据和纠错码分别存储于第一存储器和第二存储器，第二存储器与第一存储器属于不同的die，这样，纠错码就无需像图1的实施例中所说的，只能够保护与纠错码存储分区在同一个die的数据存储分区中的数据，而是可以对一个或者多个第一存储器中的数据进行数据保护，进而实现多个第一存储器共享一个第二存储器。
另外，如图1实施例所述，由于DRAM的软失效与实际应用场景相关，是无法预期哪些数据存储分区出现软失效的概率大，所以，无论是否需要使用数据保护，所有数据存储分区都会配置纠错码存储分区。但是，这样的话，对于不会出现软失效的数据存储分区，或者对数据软失效不敏感(容错强)的应用场景来说，为所有数据存储分区配置的纠错码存储分区是浪费的。那么，在本申请实施例中，由于数据存储分区设置于第一存储器，纠错码存储分区设置于第二存储器，第二存储器与第一存储器属于不同的die，使得第二存储器的存储分区能够灵活地分配给实际需要数据保护的第一存储器的存储分区，而不是所有的数据存储分区都分配纠错码存储分区，这样，可以节省纠错码的存储资源，从而实现根据实际需求和工作状态灵活调整使用数据保护的区域，进而提高纠错码存储资源的利用率。
可选的，第一存储器和第二存储器可以按照一定比例进行部署。例如，第一存储器和第二存储器可以按照数据:纠错码(可以理解为数据长度与纠错码位数之比)＝512:1、256:1、128:1、64:1等比例来布置。当然，数据与纠错码的比例还可以为其他比例，只要纠错码的存储空间远远小于数据的存储空间即可，本申请实施例不做具体限定。
在本申请实施例中，纠错码的存储空间远远小于数据的存储空间，可以理解为使用较小地址范围的纠错码来保护较大地址范围的数据，如此，节省纠错码存储资源，并提高纠错码存储资源的利用率。
进一步地，举例来说，在图1的实施例中，一个8Gbit DRAM上的所有存储区域无论是否需要使用ECC，都需要固定配置1Gbit的纠错码存储区域，对于不需要保护的数据来说，付出了额外的功耗和面积，造成浪费。而在本申请实施例中，一个8Gbit的第一存储器仅需要部署128Mbit的第二存储器，大大节省了纠错码存储资源，提高了DRAM上可用数据的容量。
需要说明的是，在本申请实施例中，以第一存储器为DRAM以及第二存储器为SRAM为例进行说明。
进一步地，第一存储器可以被划分为多个DRAM分区，第二存储器也可以被划分为多个SRAM分区。DRAM分区和SRAM分区的数量可以参考上述数据与纠错码的比例进行配置。另外，第一存储器与第二存储器之间可以存在可配置的存储分区地址的映射关系，通过配置这个映射关系将不同的SRAM分区分配给不同的DRAM分区作为相应的纠错码的存储空间，以支持第二存储器被第一存储器灵活共享。具体来说，如果某一个DRAM分区需要数据保护，则为该DRAM分区配置对应的SRAM分区；反之，如果某一个DRAM分区不需要数据保护，则不为该DRAM分区配置对应的SRAM分区。
在本申请实施例中，可以设置可配置的保护配置信息，该保护配置信息可以包括第一存储器中存储分区的地址与第二存储器中存储分区的地址之间的映射关系。通过配置该保护配置信息，改变上述映射关系，使得第二存储器的存储分区可以灵活地分配给需要数据保护的第一存储器的存储分区，而不需要固定的与所有DRAM分区对应。这样，对于访问量较少的数据存储分区，可以不配置相应的纠错码存储资源，以节省纠错码存储资源，从而实现根据实际需求和工作状态调整使用数据保护的区域，进而提高纠错码存储资源的利用率。
在实际应用中，保护配置信息中可以包括需要数据保护的DRAM分区的地址与为该DRAM分区分配的SRAM分区的地址之间的映射关系。那么，只要是保护配置信息中存在有地址间映射关系的DRAM分区，就说明该DRAM分区对应的数据是需要保护的数据，而保护配置信息不存在地址间映射关系的DRAM分区，就说明该DRAM分区对应的数据是不需要保护的数据。
或者，保护配置信息中可以还包括所有的DRAM分区的地址与SRAM分区的地址之间的映射关系，其中，需要数据保护的DRAM分区的地址与为该DRAM分区分配的SRAM分区的地址对应，而不需要数据保护的DRAM分区的地址对应的SRAM 分区地址可以设置为“0”、“null”、“空”等。那么，只要是存在对应的SRAM分区地址的DRAM分区就说明该DRAM分区对应的数据是需要保护的数据，而映射地址为“0”、“null”、“空”等的DRAM分区，就说明该DRAM分区对应的数据是不需要保护的数据。
举例来说，假设第一存储器被划分成512个DRAM分区，第二存储器被划分为8个分区。图2为本申请实施例中的保护配置信息的示意图，上述保护配置信息以表的形式实现，那么，参见图2所示，需要数据保护的DRAM分区(以各个存储分区的高位地址来表示)，如channel0+bank1(即通道0中的分区1)、channel0+bank63、channel1+bank62、……、channel7+bank63，分别分配一个SRAM分区(以各个存储分区的存储地址表示)，如zone0至zone7。不需要数据保护的DRAM分区的映射地址为“0”。
需要说明的是，上述高位地址是指DRAM分区的存储地址的前一部分地址(可以包括Channel标识+Bank地址)。相应的，存储地址的后一部分就是DRAM分区的低位地址。例如，DRAM分区的存储地址可以为16bit，那么，前8bit即为DRAM分区的高位地址，相应的，后8bit即为DRAM分区的低位地址。示例性的，DRAM分区的存储地址为channel0+bank1+00010110，高位地址为channel0+bank1，低位地址为00010110。
在一些可能的实施方式中，上述保护配置信息中除了DRAM分区与SRAM分区这两个表项外，还可以包括“是否ECC”的标识，这个标识可以用于表示该DRAM分区是否需要数据保护，也可以理解为这个标识可以用于表示该DRAM分区对应的数据是否为需要保护的数据、该DRAM分区是否存在对应的纠错码、该DRAM分区是否配置有对应的SRAM分区等。
在一些可能的实施方式中，第一存储器中各个存储分区的低位地址与第二存储器中各个存储分区的存储地址相同。例如，需要数据保护的DRAM分区的存储地址为channel0+bank1+00010110，该DRAM分区对应的SRAM分区的地址可以为该DRAM分区的低位地址00010110。
在一些可能的实施方式中，图3为本申请实施例的存储装置的一种结构示意图，参见图3所示，存储装置300可以包括：第一存储器301、第二存储器302、存储控制器303以及ECC电路304；其中，第一存储器301与第二存储器302属于不同的die。存储控制器303通过地址线A与第一存储器301耦合，存储控制器303通过数据线(包括写数据线W和读数据线R)和地址线A与ECC电路304耦合，ECC电路304通过数据线与第一存储器301和第二存储器302耦合。
这里，第一存储器301、第二存储器302、存储控制器303与上述实施例中的第 一存储器、第二存储器、存储控制器一致。
在一些可能的实施方式中，ECC电路，还被配置为：当确定第一数据为需要保护的数据时，生成第一数据对应的第一纠错码；当确定第二数据为需要保护的数据时，根据第二数据对应的第二纠错码，对第二数据进行纠错。
在本申请实施例中，ECC电路在确定对第一数据和第二数据为需要保护的数据时，对第一数据和第二数据进行ECC操作(如生成纠错码、根据纠错码进行纠错等)，如此，实现选择性的对数据进行ECC操作，在保证有效的数据保护的同时提高纠错码存储资源的利用率。
可选的，ECC电路304，还被配置为：监听存储控制器303和第一存储器301之间的地址线，以获取数据的写地址(即第一地址)或者读地址(第二地址)。
那么，ECC电路304，可以被配置为：根据写地址和上述保护配置信息，确定第一数据是否为需要保护的数据；以及根据读地址和上述保护配置信息，确定第二数据是否为需要保护的数据。
举例来说，如果写地址为channel0+bank1+00010110，ECC电路通过查询如图2所示的保护配置信息，可以确定对高位地址为“channel0+bank1”的DRAM分区需要数据保护。那么，ECC电路就可以生成第一数据对应的第一纠错码。同样的，如果读地址为channel0+bank63+0100101，ECC电路通过查询如图2所示的保护配置信息，可以确定对高位地址为“channel0+bank63”的DRAM分区需要数据保护。那么，ECC电路根据第二纠错码对第二数据进行纠错。
进一步地，存储控制器，还被配置为向ECC电路输出第一数据；那么，ECC电路，还被配置为：当确定第一数据为需要保护的数据时，生成第一纠错码，并将第一纠错码写入第二存储器；根据写地址，将第一数据写入第一存储器的第一存储分区。
以及，ECC电路，还被配置为：根据读地址，从第二存储器的第三存储分区读取第二数据；当确定第二数据为需要保护的数据时，从第二存储器读取第二纠错码，并根据第二纠错码对第二数据进行纠错；将纠错后的第二数据输出至存储控制器。
在一些可能的实施例中，ECC电路可以与第二存储器属于同一die；或者，ECC电路可以与第二存储器属于不同die。
进一步地，ECC电路可以与存储控制器属于不同的die；或者，ECC电路可以与存储控制器属于不同die。
可以理解的，ECC电路、第二存储器以及存储控制器可以集成于同一个die，也可以分别集成于不同的die，例如，ECC电路与存储控制器集成于一个die，第二存储器集成于另一个die。当然，还可以存在不同的实现形式，本申请实施例不做具体限定。
下面结合上述存储装置的结构，对存储装置的数据读写过程进行说明。
图4为本申请实施例中的存储装置的写数据流程的示意图，那么，参见图4所示，该写数据流程可以包括以下步骤：
S401：存储控制器接收来自用户侧的写指令；
S402：存储控制器通过地址线向第一存储器输出写操作指令和写地址(即第一存储分区的第一地址)；
S403：存储控制器向ECC电路输出写地址；
S404：存储控制器通过写数据线将第一数据(即写数据)输出至ECC电路；
S405：ECC电路根据写地址，确定第一数据是否为需要保护的数据；若是，则获得第二存储器中第二存储分区的第二地址，并执行S406，若否，则执行S408。
在一些可能的实施例中，ECC电路在获得写地址之后，可以取写地址的高位地址(如Channel ID+Bank地址)，然后，以该高位地址查询保护配置信息(如图2所示)，以确定第一数据是否为需要保护的数据，也就是确定第一存储分区是否需要数据保护。例如，写地址为channel0+bank1，ECC电路查询图2所示的保护配置信息，通过“是否ECC”标识确定对channel0+bank1对应的数据为需要保护的数据，也就是确定第一存储分区需要数据保护，进而ECC电路可以通过保护配置信息获得channel0+bank1对应的SRAM分区地址(第三地址)，即zone0。
S406：ECC电路生成第一数据对应的纠错码(即第一纠错码)；
S407：ECC电路按照第三地址将第一数据对应的纠错码写入第二存储分区；
S408：ECC电路通过写数据线将第一数据输出至第一存储器；
在一些可能的实施方式中，如果ECC电路根据写地址确定第一数据为不需要保护的数据，则在S408中，存储控制器可以经由ECC电路将第一数据以透传的方式输出至第一存储器。
S409：第一存储器响应写操作指令，将第一数据按照写地址写入第一存储分区。
在上述S401至S409中，对存储控制器向第一存储分区写入第一数据的过程与ECC电路生成并存储第一数据对应的纠错码的执行时序不具体限定。
在一些可能的实施方式中，图5为本申请实施例中的存储装置的读数据流程的示意图，那么，参见图5所示，该读数据流程可以包括以下步骤：
S501：存储控制器接收来自用户侧的读指令；
S502：存储控制器通过地址线向第一存储器输出读操作指令和读地址(即第二存储分区的第二地址)；
S503：第一存储器响应读操作指令，按照读地址从第二存储分区读取第二数据(即读数据)；
S504：第一存储器通过读数据线将第二数据输出至ECC电路；
S505：存储控制器向ECC电路输出读地址；
S506：ECC电路根据读地址，确定第二数据是否为需要保护的数据；若是，则获得第二存储器中的第四存储分区的第四地址，并执行S507，若否，则执行S510。
在一些可能的实施例中，ECC电路在获得写地址之后，可以取写地址的高位地址(如Channel ID+Bank地址)，然后，以该高位地址查询保护配置信息(如图2所示)，以确定第二数据是否为需要保护的数据。这里，ECC电路确定第二数据是否为需要保护的数据的过程与上述确定第一数据是否为需要保护的数据的过程类似，在此不再赘述。
S507：ECC电路按照第四地址从第四存储分区中读取第二数据对应的纠错码(即第二纠错码)；
S508：ECC电路根据纠错码对第二数据进行检查；如果ECC电路检查出错误，则执行S509；如果ECC电路未检查出错误，则执行S510；
在实际应用中，第一数据和第二数据可以包括多个bit。当ECC电路在检查出单位(即1bit)错误，则执行S509。
S509：ECC电路对第二数据进行纠错；
S510：ECC电路通过读数据线将第二数据输出至存储控制器；
这里，在S510中，ECC电路可以将第二数据或者纠错后的第二数据输出至存储控制器。
在一些可能的实施方式中，如果ECC电路根据写地址确定第二数据为不需要保护的数据，则在S510中，第一存储器可以经由ECC电路将第二数据以透传的方式输出至存储控制器。
S511：存储控制器将来自ECC电路的第二数据输出给用户侧。
由上述可知，由于数据存储分区设置于第一存储器，纠错码存储分区设置于第二存储器，第二存储器与第一存储器属于不同的die，使得第二存储器的存储分区能够灵活地分配给需要数据保护的第一存储器的存储分区，而不是所有的数据存储分区都分配纠错码存储分区，这样，可以节省纠错码的存储资源，从而实现根据实际需求和工作状态灵活调整使用数据保护的区域，进而提高纠错码存储资源的利用率。
进一步地，由于数据存储分区设置于第一存储器，纠错码存储分区设置于第二存储器，第二存储器与第一存储器属于不同的die，使得ECC电路可以在确定第一数据和第二数据为需要保护的数据时，对第一数据和第二数据进行ECC操作(如生成纠错码、根据纠错码进行纠错等)，而在确定第一数据和第二数据为不需要保护的数据 时透传数据，如此，实现选择性的对数据进行ECC操作，在保证有效的数据保护的同时提高纠错码存储资源的利用率。
在一些可能的实施方式中，为了提高纠错码存储资源的利用率，图6为本申请实施例中的ECC电路的结构示意图，参见图6中的实线所示，ECC电路304可以包括：分析子模块3041和生成子模块3042；
上述分析子模块，被配置为：从存储控制器获取写地址；根据写地址和保护配置信息，确定第一数据为需要保护的数据；向生成子模块输出第一指令，以指示生成第一纠错码；生成子模块，被配置为：响应第一指令，生成第一纠错码。
结合上述图4中存储装置的写数据过程，图7为本申请实施例中的ECC电路在写数据过程中的工作流程示意图，参见图7所示，ECC电路的工作过程可以包括以下步骤：
S701：分析子模块获取来自存储控制器的写地址；
S702：分析子模块根据写地址和保护配置信息，确定第一数据是否为需要保护的数据；若是，则执行S703，若否，不作响应；
具体来说，在执行S702时，分析子模块可以在预设的保护配置信息中查询写地址；当查询结果表示写地址需要数据保护时，可以确定第一数据为需要保护的数据。
S703：分析子模块向生成子模块输出第一指令；
S704：生成子模块通过写数据线获取第一数据；
S705：生成子模块响应第一指令，生成第一数据对应的纠错码；
S706：生成子模块将第一数据对应的纠错码写入第二存储模块。
在一些可能的实施例中，分析子模块在通过S702查询保护配置信息(如图2所示)确定第一数据为需要保护的数据之后，分析子模块还可以通过该保护配置信息获得写地址对应的第三地址。然后，分析子模块通过第一指令将第三地址输出至生成子模块。接下来，生成子模块在执行S706时，将第一数据对应的纠错码按照第三地址写入第二存储器中的第三存储分区。
需要说明的是，在上述S701至S706中，S701至S703与S704的执行顺序不做具体限定。
在一些可能的实施方式中，参见图6中的虚线所示，ECC电路304，还可以包括：检验子模块3043；
上述分析子模块，还被配置为：获取读地址；根据读地址，确定第二数据为需要保护的数据；向检查子模块输出第二指令，以指示读取第二纠错码；检查子模块，被配置为：响应第二指令，从第二存储器读取第二纠错码。
结合上述图5中存储装置的读数据过程，图8为本申请实施例中的ECC电路在读数据过程中的工作流程示意图，参见图8所示，ECC电路的工作过程可以包括以下步骤：
S801：分析子模块获取来自存储控制器的读地址；
S802：分析子模块根据读地址，确定第二数据是否为需要保护的数据；若是，则执行S803；若否，则执行S808；
具体来说，在执行S802时，分析子模块可以在预设的保护配置信息中查询读地址；当查询结果表示对读地址需要数据保护时，可以确定第二数据为需要保护的数据。
S803：分析子模块向检查子模块输出第二指令；
S804：检查子模块通过读数据线获取第二数据；
S805：检查子模块响应第二指令，从第二存储器读取第二数据对应的纠错码；
S806：检查子模块根据纠错码对第二数据进行检查；如果检查出1bit的错误，则执行S807；如果未检查出错误，则执行S808；
S807：检查子模块对第二数据进行纠错；
S808：检查子模块向存储控制器输出纠错后的第二数据。
在一些可能的实施例中，分析子模块在通过S802查询保护配置信息(如图2所示)确定第二数据为需要保护的数据之后，分析子模块还可以通过该保护配置信息获得读地址对应的第四地址。然后，分析子模块通过第二指令将第四地址输出至检查子模块。接下来，检查子模块在执行S805时，按照第四地址从第二存储器中的第四存储分区读取第二数据对应的纠错码。
需要说明的是，在上述S801至S808中，S801至S803与S804的执行顺序不做具体限定。
在本申请实施例中，上述分析子模块，还被配置为：在存储装置处于工作状态时，控制ECC电路是否工作，进而实现开启或关闭存储装置的数据保护功能。
下面以具体实例来对上述存储装置的读写数据过程进行说明。
图9为本申请实施例中的存储装置的另一种结构示意图，结合图9所示，存储装置的读写数据过程可以如下所示。
写过程：
第一步、存储控制器303接收来自用户侧的写指令；
第二步、存储控制器303通过地址线向第一存储器301输出写操作指令和写地址(如channel0+bank1)；
第三步、存储控制器303向分析子模块2021输出写地址；
示例性的，DRAM控制器(即存储控制器303)接收到用户的写指令后，按DRAM时序要求发出相应的操作指令，同时将DRAM写指地址送到ECC地址分析模块(即分析子模块2021)。
第四步、存储控制器303通过写数据线将写数据输出至生成子模块2022；
第五步、分析子模块2021在图2的表中查询写地址，确定地址为channel0+bank1的存储分区需要数据保护，并获得对应的SRAM分区地址，即zone0；
第六步、分析子模块2021向生成子模块2022发送第一指令以及SRAM分区地址zone0；这里，第一指令用于指示生成ECC码。
示例性的，ECC地址分析模块接收到DRAM控器的写指令时，可以对写指令中的访问地址进行分析。使用此次写操作的高位地址(如3bit的channel ID+6bit的Bank地址BA5～BA0)查找一个ECC配置表(即保护配置信息)。如果对应表项中表示该地址段需要进行ECC，则此次写操作属于需要ECC保护的区段，并可以得到一个ECC SRAM分区号。如果识别出此次写操作属于需要ECC保护的区段，ECC地址分析模块将给ECC生成模块(即生成子模块)发出ECC指示以及所使用的ECC SRAM区号(即SRAM分区地址)。
第七步、生成子模块2022响应第一指令，生成第一数据对应的纠错码；
第八步、生成子模块2022将第一数据对应的纠错码写入zone0；
第九步、存储控制器303通过写数据线将第一数据输出至第一存储器301；
示例性的，对于DRAM写操作，ECC生成模块根据ECC地址分析模块的ECC指示进行ECC计算，以一定的数据位为单元生成对应的ECC校验位(即第一纠错码)。生成的ECC校验位送至ECC存储资源池模块(即第二存储器)处理。写数据则送到DRAM die(即第一存储器)上存储在对应的DRAM存储单元(即第一存储分区)中。
第十步、第一存储器301响应写操作指令，将第一数据写入channel0+bank1。
在另一实施例中，示例性的，如果ECC存储资源池模块接收到ECC地址分析模块的ECC指示，则可以将ECC生成模块送来的ECC检验位写入相应的SRAM ECC存储地址(SRAM存储地址与DRAM低位地址相同)。如果ECC存储资源池模块未接收到ECC地址分析模块的ECC指示，则说明此次写操作的地址不属于需要ECC保护的区段，不做任何操作。
读过程：
第一步、存储控制器303接收来自用户侧的读指令；
第二步、存储控制器303通过地址线向第一存储器301输出读操作指令和读地址 (如channel0+bank63)；
第三步、存储控制器303向分析子模块2021输出读地址；
示例性的，对于DRAM读操作，DRAM die收到读指令，从数据存储区读取数据。同时，将读操作的地址送至ECC地址分析模块。
第四步、分析子模块2021在图2的表中查询读地址，确定地址为channel0+bank63的DRAM分区需要数据保护，并获得对应的SRAM存储分区地址，即zone1；
第五步、分析子模块2021向检查子模块2023发送第二指令以及SRAM分区地址zone1；这里，第二指令用于指示读取ECC码。
示例性的，ECC地址分析模块接收到DRAM控制的读操作地址时，会对其中的高位地址进行分析，使用此次读操作的高位地址(如3bit的channel ID+6bit的Bank地址BA5～BA0)查找一个ECC配置表。如果对应表项中表示该地址段需要进行ECC，则此次读操作属于需要ECC保护的区段，并可以得到一个ECC SRAM分区号。ECC地址分析模块会给ECC检查模块及ECC存储资源池模块发出需要ECC检验的ECC指示以及所使用的ECC SRAM区号。如果识别到读操作的地址不属于需要ECC保护的区段，则不会发出ECC指示。
第六步、检查子模块2023响应第二指令，从zone1读取第二数据对应的纠错码；
示例性的，当ECC存储资源池模块接收到ECC地址分析模块送来的读操作ECC指示，会送存储ECC数据的SRAM中读出相应的ECC数据送给ECC检查模块。
第七步、第一存储器301从channel0+bank63中读取第二数据，并输出至检查子模块2023；
示例性的，DRAM的读数据按照芯片工作时序将此次读操作的DRAM数据送给ECC检查模块。
第八步、检查子模块2023根据纠错码对第二数据进行检查；
第九步、如果检查出1bit的错误，检查子模块2023对第二数据进行纠错；
第十步、检查子模块2023将纠错后的第二数据输出至存储控制器201；
示例性的，如果ECC检查模块收到DRAM读出的数据位时，同时也接收到ECC存储资源池模块送来ECC校验位及ECC地址分析模块送来的ECC指示，则会进行ECC计算检查。如果检出单bit的ECC错，可以将数据纠错并送给DRAM控制器。如果ECC检查模块收到DRAM读出的数据位时没有接收到ECC地址分析模块送来的ECC指示，则不需要进行ECC计算检查，直接将数据送给DRAM控制器。
第十一步、存储控制器201将第二数据输出至用户侧。
示例性的，DRAM控制器将经过ECC检查/纠错的读数据返回给用户侧。
在具体实施过程中，上述存储装置可以采用且不限于以下几种方式进行封装。
第一种，图10为本申请实施例中的存储装置的第一种封装示意图，参见图10所示，第一存储器301、第二存储器302、存储控制器303和ECC电路304安装于同一个封装基板11，其中，存储控制器303、ECC电路304和第二存储器302集成于同一个裸片a(如logic die或者basic die)。第一存储器301集成于另一个裸片b(如DRAM die)，并安装于封装基板12。
在实际应用中，ECC电路304可以通过片内高速总线接口与第二存储器302通信。
第二种，图11为本申请实施例中的存储装置的第二种封装示意图，参见图11所示，第一存储器301、第二存储器302、存储控制器303和ECC电路304安装于同一个封装基板21，其中，存储控制器303和ECC电路304集成于一个裸片c(如logic die或者basic die)，第二存储器302集成于一个裸片d(如SRAM die)。第一存储器301集成于另一个裸片e(如DRAM die)。
在实际应用中，ECC电路304可以通过如die-to-die phy的高速互联接口与第二存储器302通信。
第三种，图12为本申请实施例中的存储装置的第三种封装示意图，参见图12所示，存储控制器303、ECC电路304和第二存储器302安装于封装基板31，存储控制器303、ECC电路304和第二存储器302集成于同一个裸片f(如logic die或者basic die)。第一存储器301集成于另一个裸片g(如DRAM die)，并安装于封装基板32。
在实际应用中，ECC电路304可以通过片内高速总线接口与第二存储器302通信。
第四种，图13为本申请实施例中的存储装置的第四种封装示意图，参见图13所示，存储控制器303和ECC电路304集成于同一个裸片h(如logic die或者basic die)，并安装于封装基板41。第二存储器302集成于一个裸片i(如SRAM die)，并安装于封装基板42。第一存储器301集成于一个裸片j(如DRAM die)，并安装于封装基板43。
在实际应用中，ECC电路304可以通过如serdes phy的高速互联接口与第二存储器302通信。
第五种，图14为本申请实施例中的存储装置的第五种封装示意图，参见图14所示，存储控制器303集成于一个裸片k(如logic die或者basic die)，并安装于封装基板51。ECC电路304和第二存储器302集成于裸片l和裸片m，并安装于封装基板 52。第一存储器301集成于一个裸片n(如DRAM die)，并安装于封装基板53。
在实际应用中，ECC电路304可以通过如die-to-die phy的高速互联接口与第二存储器302通信。
当然，上述存储装置还可以存在其他的封装方式，本申请实施例不做具体限定。
基于相同的发明构思，本申请实施例还提供一种纠错装置，包括：上述图2至图9所示的ECC电路和第二存储器。
可以理解的，在纠错装置中，ECC电路与第二存储器可以采用如图14所示的封装方式进行封装。
基于相同的发明构思，本申请实施例还提供一种存储控制装置，包括：上述图2至图9所示的存储控制器和ECC电路。
可以理解的，在存储控制装置中，存储控制器与ECC电路可以采用如图11或13所示的封装方式进行封装。
基于相同的发明构思，本申请实施例还提供一种片上系统(system on chip，SOC)，该片上系统可以包括处理器、总线以及上述图2至图9所示的存储装置。其中，处理器和存储装置耦合至总线。
处理器，被配置为：通过总线向存储装置输出写指令及第一数据，或者通过总线向存储装置输出读指令，并通过总线接收存储装置输出的第二数据。
处理器可以是通用中央处理器(CPU)、微处理器、特定应用集成电路(ASIC)等。
基于相同的发明构思，本申请实施例还提供一种电子设备，该电子设备可以为计算设备，如服务器；电子设备还可以为存储设备，如存储阵列等；电子设备还可以为网络设备，如交换机等。
图15为本申请实施例中的电子设备的硬件示意图，参见图15所示，电子设备1500可以包括处理器1501、存储装置1502、总线1503、输入设备1504、输出设备1505以及天线系统1506。
在一些可能的实施方式中，存储装置1502与上述一个或者多个实施例中所述的存储装置一致。进一步地，上述处理器1501可以与上述实施例中所述的片上系统一致。
存储装置1502可以存储程序指令，如操作系统、应用程序、其他程序模块、可执行代码、程序数据、用户数据等。
输入设备1504可以用于向电子设备1500输入命令和信息，输入设备1504如键盘或指向设备，如鼠标、轨迹球、触摸板、麦克风、操纵杆、游戏垫、卫星电视天线、扫描仪或类似设备。这些输入设备可以通过总线1503连接至处理器1501。
输出设备1505可以用于电子设备1500输出信息，除了监视器之外，输出设备1505还可以为其他外围输出设备，如扬声器和/或打印设备，这些输出设备也可以通过总线1503连接到处理器1501。
天线系统1506，该天线系统1506在处理器1501的控制下，收发无线通信信号实现与移动通信网络的无线通信。
当然，电子设备还可以存在其他的功能器件，本申请实施例不做具体限定。
基于相同的发明构思，本申请实施例还提供一种数据存储方法，可以应用于上述一个或者多个实施例所述的存储装置。
那么，该方法可以包括：存储控制器向第一存储器写入数据，以及从第一存储器读取数据，其中，第一存储器与第二存储器属于不同的裸片，第二存储器用于存储数据对应的纠错码，纠错码用于对数据进行数据保护。
在一些可能的实施方式中，数据包括第一数据和第二数据；上述存储控制器向第一存储器写入数据，包括：存储控制器向第一存储器写入第一数据；
上述存储器控制器从第一存储器读取数据，包括：存储控制器从第一存储器读取第二数据。
相应地，上述方法还包括：ECC电路生成第一数据对应的第一纠错码；或者，ECC电路根据第二存储器中的第二纠错码对第二数据进行纠错，第二纠错码为第二数据对应的纠错码。
在一些可能的实施方式中，上述ECC电路生成第一数据对应的第一纠错码，包括：当确定第一数据为需要保护的数据时，ECC电路生成第一纠错码；
上述ECC电路根据第二存储器中的第二纠错码对第二数据进行纠错，包括：当确定第二数据为需要保护的数据时，ECC电路根据第二纠错码对第二数据进行纠错。
在一些可能的实施方式中，上述方法还包括：ECC电路根据第一数据对应的第一地址和预设的保护配置信息，确定第一数据是否为需要保护的数据；或者，ECC电路根据第二数据对应的第二地址和保护配置信息，确定第二数据是否为需要保护的数据；其中，保护配置信息包括第一存储器中存储分区的地址与第二存储器中存储分区的地址之间的映射关系，第二存储器的存储分区与需要保护的数据对应。
在一些可能的实施方式中，上述存储控制器向第一存储器写入第一数据，包括：存储控制器向ECC电路输出第一地址和第一数据；ECC电路根据第一地址，将第一数据写入第一存储器的第一存储分区。
在一些可能的实施方式中，在ECC电路生成第一纠错码之后，上述方法还包括：ECC电路获取第一地址对应的第三地址；根据第三地址，将第一纠错码写入第二存储器中的第二存储分区。
在一些可能的实施方式中，上述方法还包括：当确定第一数据为不需要保护的数据时，ECC电路将第一数据写入第一存储器。
在一些可能的实施方式中，上述存储控制器从第一存储器读取第二数据，包括：存储控制器向ECC电路输出第二地址；ECC电路根据第二地址，从第一存储器的第三存储分区中读取第二数据；ECC电路向存储控制器输出第二数据。
在一些可能的实施方式中，上述ECC电路向存储控制器输出第二数据，包括：ECC电路根据第二纠错码对第二数据进行检查；若检查出错误，则对第二数据进行纠错，并向存储控制器输出纠错后的第二数据；若未检查出错误，则向存储控制器输出第二数据。
在一些可能的实施方式中，当确定所述第二数据为需要保护的数据时，上述方法还包括：ECC电路获取第二地址对应的第四地址；根据第四地址，从第二存储器中第四存储分区读取第二纠错码。
在一些可能的实施方式中，上述方法还包括：当确定第二数据为不需要保护的数据时，ECC电路向存储控制器输出第二数据。
基于相同的发明构思，本申请实施例还提供一种数据存储方法，可以应用于上述一个或者多个实施例所述的存储控制装置。
那么，该方法可以包括：
存储控制装置向第一存储器写入第一数据，以及从第一存储器读取第二数据；当确定第一数据为需要保护的数据时，存储控制装置生成第一纠错码；以及，当确定第二数据为需要保护的数据时，存储控制装置根据第二纠错码对第二数据进行纠错。
在一些可能的实施方式中，上述方法还包括：存储控制装置根据第一数据对应的第一地址和预设的保护配置信息，确定第一数据是否为需要保护的数据；以及，存储控制装置根据第二数据对应的第二地址和保护配置信息，确定第二数据是否为需要保护的数据；其中，保护配置信息包括第一存储器中存储分区的地址与第二存储器中存储分区的地址之间的映射关系，第二存储器的存储分区与进行保护的数据对应。
在一些可能的实施方式中，上述存储控制装置向第一存储器写入第一数据，包括：存储控制装置根据第一地址，将第一数据写入第一存储器的第一存储分区。
在一些可能的实施方式中，在存储控制装置生成第一纠错码之后，上述方法还包括：存储控制装置获取第一地址对应的第三地址；根据第三地址，将第一纠错码写入第二存储器中的第二存储分区。
在一些可能的实施方式中，上述方法还包括：当确定第一数据为不需要保护的数据时，存储控制装置将第一数据写入第一存储器。
在一些可能的实施方式中，上述存储控制装置从第一存储器读取第二数据，包 括：存储控制器根据第二地址，从第一存储器的第三存储分区中读取第二数据。
在一些可能的实施方式中，上述存储控制装置从第一存储器读取第二数据，包括：存储控制装置根据第二纠错码对第二数据进行检查；若检查出错误，则存储控制装置对第二数据进行纠错，并获取纠错后的第二数据；若未检查出错误，则存储控制装置获取第二数据。
在一些可能的实施方式中，在存储控制装置对第二数据进行纠错之前，上述方法还包括：当确定第二数据为需要保护的数据时，存储控制装置获取第二地址对应的第四地址；存储控制装置根据第四地址，从第二存储器中第四存储分区读取第二纠错码。
在一些可能的实施方式中，上述方法还包括：当确定第二数据为不需要保护的数据时，存储控制装置读取第二数据。
上述实施例可以全部或部分地通过软件、硬件、固件或其他任意组合来实现。当使用软件实现时，上述实施例可以全部或部分地以计算机程序产品的形式实现。所述计算机程序产品包括一个或多个计算机指令。在计算机上加载或执行所述计算机程序指令时，全部或部分地产生按照本申请实施例所述的流程或功能。所述计算机可以为通用计算机、专用计算机、计算机网络、或者其他可编程装置。所述计算机指令可以存储在计算机可读存储介质中，或者从一个计算机可读存储介质向另一个计算机可读存储介质传输，例如，所述计算机指令可以从一个网站站点、计算机、服务器或数据中心通过有线(例如同轴电缆、光纤、数字用户线(DSL))或无线(例如红外、无线、微波等)方式向另一个网站站点、计算机、服务器或数据中心进行传输。所述计算机可读存储介质可以是计算机能够存取的任何可用介质或者是包含一个或多个可用介质集合的服务器、数据中心等数据存储设备。所述可用介质可以是磁性介质(例如，软盘、硬盘、磁带)、光介质(例如，DVD)、或者半导体介质。半导体介质可以是固态硬盘(solid state drive，SSD)。
以上所述，仅为本申请示例性的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到的变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应该以权利要求的保护范围为准。

Claims (28)

  1. 一种存储装置，其特征在于，包括：
    第一存储器，被配置为存储数据；
    第二存储器，被配置为存储所述数据对应的纠错码，所述纠错码用于对所述数据进行数据保护；
    存储控制器，被配置为：向所述第一存储器写入所述数据；以及从所述第一存储器读取所述数据；
    其中，所述第一存储器与所述第二存储器属于不同裸片。
  2. 根据权利要求1所述的存储装置，其特征在于，所述数据包括第一数据和第二数据，所述存储装置，还包括：
    错误检查和纠正ECC电路，被配置为：生成所述第一数据对应的第一纠错码；以及根据所述第二存储器中的第二纠错码对所述第二数据进行纠错；所述第二纠错码为所述第二数据对应的纠错码；
    所述存储控制器，具体被配置为向所述第一存储器写入所述第一数据，以及从所述第一存储器读取所述第二数据。
  3. 根据权利要求2所述的存储装置，其特征在于，所述ECC电路，还被配置为：当确定所述第一数据为需要保护的数据时，生成所述第一纠错码；以及当确定所述第二数据为需要保护的数据时，根据所述第二纠错码对所述第二数据进行纠错。
  4. 根据权利要求3所述的存储装置，其特征在于，所述ECC电路，被配置为根据所述第一数据对应的第一地址和预设的保护配置信息，确定所述第一数据是否为需要保护的数据；以及根据所述第二数据对应的第二地址和所述保护配置信息，确定所述第二数据是否为需要保护的数据；
    其中，所述保护配置信息包括所述第一存储器中存储分区的地址与所述第二存储器中存储分区的地址之间的映射关系，所述第二存储器的存储分区与需要保护的数据对应。
  5. 根据权利要求2至4任一项所述的存储装置，其特征在于，所述存储控制器，被配置为向所述ECC电路输出第一地址和第一数据；
    所述ECC电路，还被配置为：根据所述第一地址，将所述第一数据写入所述第一存储器的第一存储分区。
  6. 根据权利要求4或5所述的存储装置，其特征在于，所述ECC电路，还被配置为：当确定所述第一数据为需要保护的数据时，获取所述第一地址对应的第三地址；根据所述第三地址，将所述第一纠错码写入所述第二存储器中的第二存储分区。
  7. 根据权利要求3至6任一项所述的存储装置，其特征在于，所述ECC电 路，还被配置为：当确定所述第一数据为不需要保护的数据时，将所述第一数据写入所述第一存储器。
  8. 根据权利要求3至7任一项所述的存储装置，其特征在于，所述存储控制器，还被配置为向所述ECC电路输出第二地址；
    所述ECC电路，还被配置为：根据所述第二地址，从所述第一存储器的第三存储分区中读取所述第二数据；向所述存储控制器输出所述第二数据。
  9. 根据权利要求8所述的存储装置，其特征在于，所述ECC电路，被配置为：根据所述第二纠错码对所述第二数据进行检查；若检查出错误，则对所述第二数据进行纠错，并向所述存储控制器输出纠错后的第二数据；若未检查出错误，则向所述存储控制器输出所述第二数据。
  10. 根据权利要求8或9所述的存储装置，其特征在于，所述ECC电路，还被配置为：当确定所述第二数据为需要保护的数据时，获取所述第二地址对应的第四地址；根据所述第四地址，从所述第二存储器中第四存储分区读取所述第二纠错码。
  11. 根据权利要求3至10任一项所述的存储装置，其特征在于，所述ECC电路，被配置为：当确定所述第二数据为不需要保护的数据时，向所述存储控制器输出所述第二数据。
  12. 根据权利要求2至11任一项所述的存储装置，其特征在于，所述ECC电路与所述第二存储器属于同一裸片；或者，所述ECC电路与所述第二存储器属于不同裸片。
  13. 根据权利要求2至12任一项所述的存储装置，其特征在于，所述ECC电路与所述存储控制器属于不同裸片；或者，所述ECC电路与所述存储控制器属于同一裸片。
  14. 根据权利要求1至13任一项所述的存储装置，其特征在于，所述第一存储器中各个存储分区的低位地址与所述第二存储器中各个存储分区的存储地址相同。
  15. 根据权利要求1至14任一项所述的存储装置，其特征在于，所述第一存储器为动态随机存取存储器DRAM、静态随机存取存储器SRAM或非易失存储器NVM。
  16. 根据权利要求1至15任一项所述的存储装置，其特征在于，所述第二存储器为静态随机存取存储器SRAM。
  17. 一种存储控制装置，其特征在于，包括：存储控制器和错误检查和纠正ECC电路；
    所述存储控制器，被配置为向第一存储器写入第一数据，以及从所述第一存储器读取第二数据；
    所述ECC电路，被配置为：当确定所述第一数据为需要保护的数据时，生成第一纠错码；以及当确定所述第二数据为需要保护的数据时，根据第二纠错码对所述第二数据进行纠错。
  18. 根据权利要求17所述的存储控制装置，其特征在于，所述ECC电路，被配置为根据所述第一数据对应的第一地址和预设的保护配置信息，确定所述第一数据是否为需要保护的数据；以及根据所述第二数据对应的第二地址和所述保护配置信息，确定所述第二数据是否为需要保护的数据；
    其中，所述保护配置信息包括所述第一存储器中存储分区的地址与所述第二存储器中存储分区的地址之间的映射关系，所述第二存储器的存储分区与进行保护的数据对应。
  19. 根据权利要求17或18所述的存储控制装置，其特征在于，所述存储控制器，被配置为向所述ECC电路输出第一地址和第一数据；
    所述ECC电路，还被配置为：根据第一地址，将所述第一数据写入所述第一存储器的第一存储分区。
  20. 根据权利要求19所述的存储控制装置，其特征在于，所述ECC电路，还被配置为：当确定所述第一数据为需要保护的数据时，获取所述第一地址对应的第三地址；根据所述第三地址，将所述第一纠错码写入所述第二存储器中的第二存储分区。
  21. 根据权利要求17至20任一项所述的存储控制装置，其特征在于，所述ECC电路，还被配置为：当确定所述第一数据为不需要保护的数据时，将所述第一数据写入所述第一存储器。
  22. 根据权利要求17至21任一项所述的存储控制装置，其特征在于，所述存储控制器，还被配置为向所述ECC电路输出第二地址；
    所述ECC电路，还被配置为：根据所述第二地址，从所述第一存储器的第三存储分区中读取所述第二数据；向所述存储控制器输出所述第二数据。
  23. 根据权利要求22所述的存储控制装置，其特征在于，所述ECC电路，被配置为：根据所述第二纠错码对所述第二数据进行检查；若检查出错误，则对所述第二数据进行纠错，并向所述存储控制器输出纠错后的第二数据；若未检查出错误，则向所述存储控制器输出所述第二数据。
  24. 根据权利要求22或23所述的存储控制装置，其特征在于，所述ECC电路，还被配置为：当确定所述第二数据为需要保护的数据时，获取所述第二地址对应的第四地址；根据所述第四地址，从所述第二存储器中第四存储分区读取所述第二纠错码。
  25. 根据权利要求17至24任一项所述的存储控制装置，其特征在于，所述ECC电路，被配置为：当确定所述第二数据为不需要保护的数据时，向所述存储控制器输出所述第二数据。
  26. 根据权利要求22至25任一项所述的存储控制装置，其特征在于，所述ECC电路与所述第二存储器属于同一裸片；或者，所述ECC电路与所述第二存储器属于不同裸片。
  27. 根据权利要求17至26任一项所述的存储控制装置，其特征在于，所述ECC电路与所述存储控制器属于不同裸片；或者，所述ECC电路与所述存储控制器属于同一裸片。
  28. 一种片上系统，其特征在于，包括：处理器、总线以及权利要求1至16任一项所述的存储装置；
    所述处理器，被配置为：通过所述总线向所述存储装置输出写指令及第一数据，或者通过所述总线向所述存储装置输出读指令，并通过所述总线接收所述存储装置输出的第二数据；所述写指令用于指示向所述第一存储器写入所述第一数据，所述读指令用于指示从所述第二存储器读取所述第二数据。
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