WO2022119690A1 - Mémoire non-et de détection capacitive - Google Patents

Mémoire non-et de détection capacitive Download PDF

Info

Publication number
WO2022119690A1
WO2022119690A1 PCT/US2021/058717 US2021058717W WO2022119690A1 WO 2022119690 A1 WO2022119690 A1 WO 2022119690A1 US 2021058717 W US2021058717 W US 2021058717W WO 2022119690 A1 WO2022119690 A1 WO 2022119690A1
Authority
WO
WIPO (PCT)
Prior art keywords
series
memory cells
unit column
field
data line
Prior art date
Application number
PCT/US2021/058717
Other languages
English (en)
Inventor
Yoshiaki Fukuzumi
Jun Fujiki
Shuji Tanaka
Masashi Yoshida
Masanobu Saito
Yoshihiko Kamata
Original Assignee
Micron Technology, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US17/111,751 external-priority patent/US11670379B2/en
Priority claimed from US17/111,746 external-priority patent/US11227869B1/en
Priority claimed from US17/111,770 external-priority patent/US11386966B2/en
Priority claimed from US17/111,729 external-priority patent/US11437106B2/en
Application filed by Micron Technology, Inc. filed Critical Micron Technology, Inc.
Priority to CN202180081026.1A priority Critical patent/CN116636324A/zh
Publication of WO2022119690A1 publication Critical patent/WO2022119690A1/fr

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/08—Address circuits; Decoders; Word-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/24—Bit-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/10—EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/32—Timing circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels

Definitions

  • the present disclosure relates generally to integrated circuits, and, in particular, in one or more embodiments, the present disclosure relates to apparatus including strings of series-connected memory cells, and to methods of their formation and operation.
  • RAM random-access memory
  • ROM read only memory
  • DRAM dynamic random access memory
  • SDRAM synchronous dynamic random access memory
  • Flash memory has developed into a popular source of non-volatile memory for a wide range of electronic applications. Flash memory typically use a one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption. Changes in threshold voltage (Vt) of the memory cells, through programming (which is often referred to as writing) of charge storage structures (e.g., floating gates or charge traps) or other physical phenomena (e.g., phase change or polarization), determine the data state (e.g., data value) of each memory cell.
  • Vt threshold voltage
  • flash memory and other non-volatile memory include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, appliances, vehicles, wireless devices, mobile telephones, and removable memory modules, and the uses for non-volatile memory continue to expand.
  • PDAs personal digital assistants
  • flash memory and other non-volatile memory include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, appliances, vehicles, wireless devices, mobile telephones, and removable memory modules, and the uses for non-volatile memory continue to expand.
  • a NAND flash memory is a common type of flash memory device, so called for the logical form in which the basic memory cell configuration is arranged.
  • the array of memory cells for NAND flash memory is arranged such that the control gate of each memory cell of a row of the array is connected together to form an access line, such as a word line.
  • Columns of the array include strings (often termed NAND strings) of memory cells connected together in series between a pair of select gates, e.g., a source select transistor and a drain select transistor.
  • Each source select transistor might be connected to a source, while each drain select transistor might be connected to a data line, such as column bit line.
  • Variations using more than one select gate between a string of memory cells and the source, and/or between the string of memory cells and the data line, are known.
  • Figure 1 is a simplified block diagram of a memory in communication with a processor as part of an electronic system, according to an embodiment.
  • Figures 2A-2B are schematics of portions of an array of memory cells as could be used in a memory of the type described with reference to Figure 1, according to embodiments.
  • Figure 2C is a perspective conceptualization of a portion of an array of memory cells over peripheral circuitry as could be used in a memory of the type described with reference to Figure 1, according to a further embodiment.
  • Figures 3A-3E are conceptual depictions of portions of a block of memory cells using array structures such as depicted in Figure 2A and demonstrating layouts of backside gate lines, sense select lines, sense lines, common source, and lower data lines, according to embodiments.
  • Figures 3F-3G are conceptual depictions of a portion of a block of memory cells using an array structure such as depicted in Figure 2B and demonstrating a layout of backside gate lines, sense select lines, sense lines, common source, and lower data lines, according to additional embodiments.
  • Figure 4A is a conceptual depiction of a portion of a block of memory cells using an array structure such as depicted in Figures 3A and 3B, and demonstrating a layout of upper data line connectivity, according to an embodiment.
  • Figure 4B is a conceptual depiction of a portion of a block of memory cells using an array structure such as depicted in Figures 3C and 3D, and demonstrating a layout of upper data line connectivity, according to another embodiment.
  • Figure 4C is a conceptual depiction of a portion of a block of memory cells using an array structure such as depicted in Figures 3C and 3E, and demonstrating a layout of upper data line connectivity, according to a further embodiment.
  • Figure 4D is a conceptual depiction of a portion of a block of memory cells using an array structure such as depicted in Figures 3F and 3G, and demonstrating a layout of upper data line connectivity, according to a still further embodiment.
  • Figures 5A-5N depict an integrated circuit structure during various stages of fabrication in accordance with embodiments.
  • Figures 6A-6F depict an integrated circuit structure during various stages of fabrication in accordance with additional embodiments.
  • Figures 7A-7J depict orthogonal views of various structures for sense lines in accordance with embodiments.
  • Figures 8A-8C depict an integrated circuit structure during various stages of fabrication in accordance with an embodiment.
  • Figures 9A-9E depict an integrated circuit structure during various stages of fabrication in accordance with another embodiment.
  • Figures 10A-10B depict integrated circuit structures in accordance with further embodiments.
  • Figure 11 is a timing diagram of a method of operating a memory in accordance with an embodiment.
  • Figure 12 is a timing diagram of a method of operating a memory in accordance with a different embodiment.
  • Figure 13 is a timing diagram of a method of operating a memory in accordance with another embodiment.
  • Figure 14 is a timing diagram of a method of operating a memory in accordance with a further embodiment.
  • semiconductor used herein can refer to, for example, a layer of material, a wafer, or a substrate, and includes any base semiconductor structure.
  • semiconductor is to be understood as including silicon-on-sapphire (SOS) technology, silicon-on-insulator (SOI) technology, thin film transistor (TFT) technology, doped and undoped semiconductors, epitaxial layers of a silicon supported by a base semiconductor structure, as well as other semiconductor structures well known to one skilled in the art. Furthermore, when reference is made to a semiconductor in the following description, previous process steps might have been utilized to form regions/j unctions in the base semiconductor structure, and the term semiconductor can include the underlying layers containing such regions/j unctions.
  • conductive as used herein, as well as its various related forms, e.g., conduct, conductively, conducting, conduction, conductivity, etc., refers to electrically conductive unless otherwise apparent from the context.
  • connecting refers to electrically connecting unless otherwise apparent from the context.
  • FIG. 1 is a simplified block diagram of a first apparatus, in the form of a memory (e.g., memory device) 100, in communication with a second apparatus, in the form of a processor 130, as part of a third apparatus, in the form of an electronic system, according to an embodiment.
  • a memory e.g., memory device
  • PDAs personal digital assistants
  • the processor 130 e.g., a controller external to the memory device 100, might be a memory controller or other external host device.
  • Memory device 100 includes an array of memory cells 104 logically arranged in rows and columns. Memory cells of a logical row are typically connected to the same access line (commonly referred to as a word line) while memory cells of a logical column are typically selectively connected to the same data line (commonly referred to as a bit line). A single access line might be associated with more than one logical row of memory cells and a single data line might be associated with more than one logical column. Memory cells (not shown in Figure 1) of at least a portion of array of memory cells 104 are capable of being programmed to one of at least two target data states.
  • the array of memory cells 104 includes an array structure in accordance with one or more embodiments described herein.
  • a row decode circuitry 108 and a column decode circuitry 110 are provided to decode address signals. Address signals are received and decoded to access the array of memory cells 104.
  • Memory device 100 also includes input/output (I/O) control circuitry 112 to manage input of commands, addresses and data to the memory device 100 as well as output of data and status information from the memory device 100.
  • An address register 114 is in communication with I/O control circuitry 112 and row decode circuitry 108 and column decode circuitry 110 to latch the address signals prior to decoding.
  • a command register 124 is in communication with I/O control circuitry 112 and control logic 116 to latch incoming commands.
  • a controller controls access to the array of memory cells 104 in response to the commands and generates status information for the external processor 130, i.e., control logic 116 is configured to perform access operations (e.g., sensing operations [which might include read operations and verify operations], programming operations and/or erase operations) on the array of memory cells 104.
  • the control logic 116 is in communication with row decode circuitry 108 and column decode circuitry 110 to control the row decode circuitry 108 and column decode circuitry 110 in response to the addresses.
  • the control logic 116 might include instruction registers 128 which might represent computer-usable memory for storing computer-readable instructions.
  • the instruction registers 128 might represent firmware.
  • the instruction registers 128 might represent a grouping of memory cells, e.g., reserved block(s) of memory cells, of the array of memory cells 104.
  • Control logic 116 is also in communication with a cache register 118.
  • Cache register 118 latches data, either incoming or outgoing, as directed by control logic 116 to temporarily store data while the array of memory cells 104 is busy writing or reading, respectively, other data.
  • data might be passed from the cache register 118 to the data register 120 for transfer to the array of memory cells 104; then new data might be latched in the cache register 118 from the I/O control circuitry 112.
  • a read operation data might be passed from the cache register 118 to the I/O control circuitry 112 for output to the external processor 130; then new data might be passed from the data register 120 to the cache register 118.
  • the cache register 118 and/or the data register 120 might form (e.g., might form a portion of) a page buffer of the memory device 100.
  • a page buffer might further include sensing devices (not shown in Figure 1) to sense a data state of a memory cell of the array of memory cells 104, e.g., by sensing a state of a data line connected to that memory cell.
  • a status register 122 might be in communication with I/O control circuitry 112 and control logic 116 to latch the status information for output to the processor 130.
  • Memory device 100 is depicted to receive control signals at control logic 116 from processor 130 over a control link 132.
  • the control signals might include a chip enable CE#, a command latch enable CLE, an address latch enable ALE, a write enable WE#, a read enable RE#, and a write protect WP#. Additional or alternative control signals (not shown) might be further received over control link 132 depending upon the nature of the memory device 100.
  • Memory device 100 receives command signals (which represent commands), address signals (which represent addresses), and data signals (which represent data) from processor 130 over a multiplexed input/output (I/O) bus 134 and outputs data to processor 130 over I/O bus 134.
  • I/O input/output
  • the commands might be received over input/output (I/O) pins [7:0] of I/O bus 134 at I/O control circuitry 112 and might then be written into command register 124.
  • the addresses might be received over input/output (I/O) pins [7:0] of I/O bus 134 at I/O control circuitry 112 and might then be written into address register 114.
  • the data might be received over input/output (I/O) pins [7:0] for an 8-bit device or input/output (I/O) pins [15:0] for a 16-bit device at I/O control circuitry 112 and then might be written into cache register 118.
  • the data might be subsequently written into data register 120 for programming the array of memory cells 104.
  • cache register 118 might be omitted, and the data might be written directly into data register 120.
  • Data might also be output over input/output (I/O) pins [7:0] for an 8-bit device or input/output (I/O) pins [15:0] for a 16-bit device.
  • I/O pins they might include any conductive node providing for electrical connection to the memory device 100 by an external device (e.g., processor 130), such as conductive pads or conductive bumps as are commonly used.
  • FIG. 2A is a schematic of a portion of an array of memory cells 200A, such as a NAND memory array, as could be used in a memory of the type described with reference to Figure 1, e.g., as a portion of array of memory cells 104.
  • Memory array 200A includes access lines, such as word lines 2O2o to 202N, and data lines, such as first, or upper, data lines (e.g., upper bit lines) 2O4o to 204M and second, or lower, data line (e.g., lower bit line) 254.
  • the word lines 202 might be connected to global access lines (e.g., global word lines), not shown in Figure 2A, in a many-to-one relationship.
  • memory array 200A might be formed over a semiconductor that, for example, might be conductively doped to have a conductivity type, such as a p-type conductivity, e.g., to form a p-well, or an n-type conductivity, e.g., to form an n-well.
  • the memory array 200A might be formed over other circuitry, e.g., peripheral circuitry under the memory array 200A and used for controlling access to the memory cells of the memory array 200A.
  • directional descriptors used herein, e.g., lower, upper, over, under, etc. are relative and do not require any particular orientation in physical space.
  • Memory array 200A might be arranged in rows (each corresponding to a word line 202 and a lower data line 254) and columns (each corresponding to a upper data line 204). Each column might include a string of series-connected memory cells (e.g., nonvolatile memory cells), such as one of NAND strings 2O6o to 206M.
  • the memory cells 208 might represent non-volatile memory cells for storage of data.
  • each NAND string 206 might be connected in series between a select gate 210 (e.g., a field-effect transistor), such as one of the select gates 21Oo to 210M (e.g., lower select gates), and a select gate 212 (e.g., a field-effect transistor), such as one of the select gates 212o to 212M (e.g., upper select gates).
  • a select gate 210 e.g., a field-effect transistor
  • select gate 212 e.g., a field-effect transistor
  • Lower select gates 21Oo to 210M might be commonly connected to a select line 214, such as a lower select line LSG
  • upper select gates 212o to 212M might be commonly connected to a select line 215, such as an upper select line USG.
  • the lower select gates 210 and upper select gates 212 might utilize a structure similar to (e.g., the same as) the memory cells 208.
  • the lower select gates 210 and upper select gates 212 might each represent a plurality of select gates connected in series, with each select gate in series configured to receive a same or independent control signal.
  • Typical construction of memory cells 208 includes a data-storage structure 234 (e.g., a floating gate, charge trap, or other structure configured to store charge) that can determine a data state of the memory cell (e.g., through changes in threshold voltage), and a control gate 236, as shown in Figure 2A.
  • the data-storage structure 234 might include both conductive and dielectric structures while the control gate 236 is generally formed of one or more conductive materials.
  • memory cells 208 might further have a defined source/drain (e.g., source) 230 and a defined source/drain (e.g., drain) 232.
  • Memory cells 208 have their control gates 236 connected to (and in some cases form) a word line 202.
  • each NAND string 206 might be connected in series between its memory cells 208 and a respective capacitance 226, e.g., one of capacitances 226o to 226M.
  • Each lower select gate 210 might be connected (e.g., directly connected) to its respective capacitance 226.
  • Each lower select gate 210 might further be connected (e.g., directly connected) to the memory cell 2O8o of its corresponding NAND string 206.
  • the lower select gate 21Oo might be connected to the capacitance 226o
  • the lower select gate 21Oo might be connected to memory cell 2O8o of the corresponding NAND string 2O6o. Therefore, each lower select gate 210 might be configured to selectively connect a corresponding NAND string 206 to a respective capacitance 226.
  • a control gate of each lower select gate 210 might be connected to select line 214.
  • the upper select gates 212 of each NAND string 206 might be connected in series between its memory cells 208 and a GIDL (gate-induced drain leakage) generator gate 220 (e.g., a field-effect transistor), such as one of the GIDL generator (GG) gates 22Oo to 220M.
  • the GG gates 22Oo to 220M might be connected (e.g., directly connected) to their respective upper data lines 2O4o to 204M, and selectively connected to their respective NAND strings 2O6o to 206M, e.g., through respective upper select gates 212o to 212M.
  • GG gates 22Oo to 220M might be commonly connected to a control line 224, such as a GG control line. Although depicted as traditional field-effect transistors, the GG gates 220 may utilize a structure similar to (e.g., the same as) the memory cells 208.
  • the GG gates 220 might represent a plurality of GG gates connected in series, with each GG gate in series configured to receive a same or independent control signal. In general, the GG gates 220 may have threshold voltages different than (e.g., lower than) the threshold voltages of the upper select gates 212.
  • Threshold voltages of the GG gates 220 may be of an opposite polarity than, and/or may be lower than, threshold voltages of the upper select gates 212.
  • the upper select gates 212 might have positive threshold voltages (e.g., 2V to 4V)
  • the GG gates 220 might have negative threshold voltages (e.g., -IV to -4V).
  • the GG gates 220 might be provided to assist in the generation of GIDL current into a channel region of their corresponding NAND string 206 during a read operation or an erase operation, for example.
  • Each GG gate 220 might be connected (e.g., directly connected) to the upper data line 204 for the corresponding NAND string 206.
  • the GG gate 22Oo might be connected to the upper data line 2O4o for its corresponding NAND string 2O6o.
  • Each GG gate 220 might be connected (e.g., directly connected) to the upper select gate 212 of its corresponding NAND string 206.
  • GG gate 22Oo might be connected to the upper select gate 212o of the corresponding NAND string 2O6o.
  • Each upper select gate 212 might further be connected (e.g., directly connected) to the memory cell 208N of its corresponding NAND string 206.
  • each upper select gate 212o might be connected to memory cell 208N of the corresponding NAND string 2O6o. Therefore, in cooperation, each upper select gate 212 and GG gate 220 for a corresponding NAND string 206 might be configured to selectively connect that NAND string 206 to the corresponding upper data line 204.
  • a control gate of each GG gate 220 might be connected to control line 224.
  • a control gate of each upper select gate 212 might be connected to select line 215.
  • each capacitance 226 might be connected to control line 228, e.g., control line CAP.
  • a different electrode of each capacitance 226 might be capacitively coupled to a respective pass gate 238, e.g., pass gates 238o to 238M.
  • the capacitance 226o might be capacitively coupled to, or electrically connected to, a first control gate 240 of the pass gate 238o, and thus capacitively coupled to a channel of the pass gate 238o.
  • a second control gate 242 of each pass gate 238 might be connected (e.g., directly connected) to a respective backside gate line 244, e.g., backside gate lines 244o to 244M.
  • the second control gate 242 of pass gate 238o might be connected to the backside gate line 244o.
  • the pass gates 238 might be connected in series between the a source 216 (e.g., common source SRC) as one voltage node, and the lower data line 254 as another voltage node, and their resulting current path might be referred to as a sense line 258.
  • One pass gate 238, e.g., pass gate 238o might be selectively connected to the lower data line 254 through a first sense select gate (e.g., field-effect transistor) 246.
  • a control gate of the first sense select gate 246 might be connected to a first sense select line 248.
  • Another pass gate 238, e.g., pass gate 238M, might be selectively connected to the common source 216 through a second sense select gate (e.g., field-effect transistor) 250.
  • a control gate of the second sense select gate 250 might be connected to a second sense select line 252.
  • Pass gates 238 might be deemed to be two field-effect transistors connected in parallel that are responsive to two control gates, e.g., the first control gate 240 and the second control gate 242.
  • the two field-effect transistors of a pass gate 238 might have discrete channels, e.g., one channel capacitively coupled to the first control gate 240 and another channel capacitively coupled to the second control gate 242.
  • a first channel of a pass gate 238 capacitively coupled to the first control gate 240 and a second channel of the pass gate 238 capacitively coupled to the second control gate 242 might be a same channel of that pass gate 238.
  • a sensing device 268 might be connected to the lower data line 254 for use in sensing a data state of a memory cell 208, e.g., by sensing a state of the lower data line 254.
  • the sensing device 268 might be used to detect whether the lower data line 254 is experiencing current flow, or experiencing a change in voltage level, to determine whether a unit column structure 256 containing a memory cell 208 selected for sensing stores a sufficient level of electrical charge to activate the first control gate 240 of its corresponding pass gate 238 while the second control gate 242 of that pass gate 238 is deactivated.
  • the remaining pass gates in the sense line 258 might have their second control gates 242 activated.
  • electrically connecting the lower data line to the common source 216 through the sense line 258 could indicate that the selected memory cell has one data state, while electrically isolating the lower data line from the common source 216 could indicate that the selected memory cell has a different data state.
  • each capacitance 226 is depicted as a single capacitance for each NAND string 206, each capacitance 226 might represent a number of field-effect transistors connected in series, and each such transistor might utilize a structure similar to (e.g., the same as) the memory cells 208.
  • An example of this configuration is depicted in further detail in Figure 2B.
  • a unit column structure 256 refers to the elements between its memory cells 208 and an upper data line 204, its memory cells 208, and the elements between its memory cells 208 and a pass gate 238, that are connected (e.g., selectively connected) to one another.
  • a unit column structure 256 for a given NAND string 206 might include its GG gate 220, upper select gate 212, memory cells 208, lower select gate 210 and capacitance 226, connected in series between an upper data line 204 and a pass gate 238.
  • the memory array in Figure 2A might be a quasi-two-dimensional memory array and might have a generally planar structure, e.g., where the common source 216, NAND strings 206 and upper data lines 204 extend in substantially parallel planes.
  • the memory array in Figure 2A might be a three-dimensional memory array, e.g., where upper data lines 204 are selectively connected to more than one NAND string 206 and where backside gate lines 244 are connected to more than one pass gate 238.
  • a column of the memory cells 208 might be a NAND string 206 or a plurality of NAND strings 206 selectively connected to a given upper data line 204.
  • a row of the memory cells 208 might be memory cells 208 commonly connected to a given word line 202.
  • a row of memory cells 208 can, but need not, include all memory cells 208 commonly connected to a given word line 202.
  • the memory cells 208 might be programmed as what are often termed single-level cells (SLC).
  • SLC may use a single memory cell to represent one digit (e.g., one bit) of data.
  • a Vt of 2.5V or higher might indicate a programmed memory cell (e.g., representing a logical 0) while a Vt of -0.5V or lower might indicate an erased memory cell (e.g., representing a logical 1).
  • Memory might achieve higher levels of storage capacity by including multi-level cells (MLC), triple-level cells (TLC), quad-level cells (QLC), etc., or combinations thereof in which the memory cell has multiple levels that enable more digits of data to be stored in each memory cell.
  • MLC multi-level cells
  • TLC triple-level cells
  • QLC quad-level cells
  • MLC might be configured to store two digits of data per memory cell represented by four Vt ranges
  • TLC might be configured to store three digits of data per memory cell represented by eight Vt ranges
  • QLC might be configured to store four digits of data per memory cell represented by sixteen Vt ranges
  • a number of binary digits of data stored in a memory cell is typically an integer value to represent a binary number of data states per memory cell
  • a memory cell may be operated to store non-integer digits of data. For example, where the memory cell is operated using three Vt ranges, each memory cell might store 1.5 digits of data, with two memory cells collectively capable of representing one of eight data states.
  • the memory cells 208 of a given NAND string 206 might be configured to store data at a variety of storage densities.
  • a NAND string 206 might contain some memory cells (e.g., dummy memory cells) 208 configured to store data at a first storage density, e.g., 0 bits per memory cell.
  • Dummy memory cells 208 are typically incorporated into a NAND string 206 for operational advantages, are generally inaccessible to a user of the memory, and are generally not intended to store user data.
  • memory cells 208 formed in certain locations of a NAND string 206 might have different operating characteristics than memory cells formed in other locations. By operating these memory cells as dummy memory cells, such differences in operating characteristics might generally be mitigated.
  • dummy memory cells can be used to buffer select gates from high voltage levels that might be applied to principal memory cells (e.g., those memory cells intended to store user data) during certain operations.
  • a NAND string 206 might further contain other memory cells 208 configured to store data at one or more additional (e.g., higher) storage densities.
  • Figure 2B is another schematic of a portion of an array of memory cells 200B as could be used in a memory of the type described with reference to Figure 1, e.g., as a portion of array of memory cells 104, according to another embodiment.
  • Like numbered elements in Figure 2B correspond to the description as provided with respect to Figure 2A. For clarity, certain elements are not numbered, although their identity would be apparent with reference to depictions in Figure 2A.
  • Figure 2B provides additional detail of one example of the structure of the capacitances 226 as well as the incorporation of a dummy unit column structure 257 in addition to unit column structures, e.g., principal unit column structures, 256.
  • the unit column structures 256o to 256s might be part of a first sub-block of memory cells 262o of the block of memory cells corresponding to backside gate lines 244o to 244s.
  • the unit column structures 2564 to 256? might be part of a second sub-block of memory cells 262i of the block of memory cells corresponding to backside gate lines 2444 to 244?.
  • the dummy unit column structure 257 might have the same association to a pass gate 238 as the unit column structures 256o to 256?, and might have a second control gate 242 of its associated pass gate 238 connected to a dummy backside gate line 260. Where the dummy unit column structure 257 lack a connection to an upper data line 204, the first control gate 240 of its associated pass gate 238 might be electrically floating, e.g., permanently electrically floating.
  • the unit column structures 256o to 256? and the dummy unit column structure 257 might each include memory cells 2O8o to 208N connected to (e.g., having control gates connected to) the access lines 2O2o to 202N, respectively.
  • the unit column structures 256o to 256? and the dummy unit column structure 257 might each include select gates (e.g., lower select gates) 21Oo to 2102, which might have the same structure as the memory cells 208.
  • the select gates 21Oo to 2IO2 might be connected to (e.g., have control gates connected to) the select lines 214o to 2142, respectively.
  • the unit column structures 256o to 256? and the dummy unit column structure 257 might each include an optional compensation gate 211 between the select gates 210 and the memory cells 208, and might have the same structure as the memory cells 208.
  • the compensation gate 211 might be connected to (e.g., have its control gate connected to) the control line 213.
  • the unit column structures 256o to 256? and the dummy unit column structure 257 might each include capacitances 226o to 226K, which might have the same structure as the memory cells 208.
  • the capacitances 226o to 226K might be connected to (e.g., have control gates connected to) the control lines 228o to 228K, respectively.
  • the control gate of the field-effect transistor forming a capacitance 226 of Figure 2B might correspond to a first electrode of that capacitance 226, and the channel, e.g., body, of the field-effect transistor forming that capacitance 226 might correspond to a second electrode of that capacitance 226.
  • the field-effect transistors of the capacitances 226 might be operated to apply a same voltage level to each control line 228o to 228K of each unit column structure 256o to 256?, which might be 2-3V, for example.
  • the unit column structures 256o to 256? and the dummy unit column structure 257 might each include a GIDL generator gate 220, which might have the same structure as the memory cells 208.
  • the GIDL generator gates 220 might be connected to (e.g., have control gates connected to) the control line 224.
  • the GIDL generator gates 220 of the unit column structures 256o to 256s might be connected to (e.g., have source/drain regions connected to) the upper data lines 2O4o to 204s. respectively.
  • the GIDL generator gates 220 of the unit column structures 2564 to 256? might be connected to (e.g., have source/drain regions connected to) the upper data lines 204s to 2O4o, respectively.
  • the unit column structures 256o to 256? and the dummy unit column structure 257 might each include select gates (e.g., upper select gates) 212o to 2122, which might have the same structure as the memory cells 208.
  • the select gates 212o to 2122 of the unit column structures 256o to 256s might be connected to (e.g., have control gates connected to) the select lines 215oo to 215o2, respectively.
  • the select gates 212o to 2122 of the dummy unit column structure 257 might be connected to (e.g., have control gates connected to) the dummy select lines 217o to 2172, respectively. Because the dummy unit column structure 257 is not intended to store data, the dummy select lines 217o to 2172 may each be electrically floating.
  • a contiguous conductive structure could be formed, from which a first select line 215 (e.g., select line 215oo), a second select line 215 (e.g., select line 215io), and a dummy select line 217 (e.g., dummy select line 217o) subsequently might be formed.
  • isolation regions could be formed in such a contiguous conductive structure to define the first select line 215, the second select line 215 and the dummy select line 217, with each select line electrically isolated from one another.
  • a single isolation region could be formed in the contiguous conductive structure such that the dummy select line 217 would remain connected to either the first select line 215 or the second select line 215, but the first select line 215 would be isolated from the second select line 215.
  • Figure 2C is a perspective conceptualization of a portion of an array of memory cells 200C over peripheral circuitry 266 as could be used in a memory of the type described with reference to Figure 1, according to a further embodiment.
  • sense lines 258o to 258L e.g., sense lines 258L.
  • the peripheral circuitry 266 might represent a variety of circuitry for accessing the memory array 200C.
  • the peripheral circuitry 266 might include complementary circuit elements.
  • the peripheral circuitry 266 might include both n-channel and p-channel transistors formed on a same semiconductor substrate, a process commonly referred to as CMOS, or complementary metal-oxide-semiconductors.
  • CMOS complementary metal-oxide-semiconductors.
  • Figures 3A-3E are conceptual depictions of portions of a block of memory cells using array structures such as depicted in Figure 2A and demonstrating layouts of backside gate lines 244, sense select lines 248 and 252, sense lines 258, common source 216 and lower data lines 254, according to embodiments.
  • Figure 3B depicts a top-down view of a memory array 300B, which might include the same memory array structure as the memory array 300A.
  • the memory array 300B further depicts sense lines 258o to 2582 in diagonal orientations, which each might individually correspond to the sense line 258 of Figure 2A. It is recognized that fewer or more sense lines 258 could be utilized, and that fewer or more unit column structures could be associated with each sense line 258.
  • the memory array 300B further depicts a common source 216 in a horizontal orientation connected to each of the sense lines 258 through a respective contact 366, and lower data lines 254o to 2542 in vertical orientations each connected to a respective sense line 258o to 2582, respectively, through a respective contact 367. It is noted that the lower data lines 254 and the common source 216 might be connected to sense lines 258 of additional blocks of memory cells (not depicted in Figure 3B). [0065]
  • Figure 3C depicts a top-down view of a memory array 300C having a number of unit column structures 256, including unit column structures 256o to 256s.
  • Figure 3D depicts a top-down view of a memory array 300D, which might include the same memory array structure as the memory array 300C.
  • the memory array 300D further depicts sense lines 258o to 2584 in diagonal orientations, which each might individually correspond to the sense line 258 of Figure 2A. It is recognized that fewer or more sense lines 258 could be utilized, and that fewer or more unit column structures could be associated with each sense line 258.
  • the memory array 300D further depicts a common source 216 in a horizontal orientation connected to each of the sense lines 258 through a respective contact 366, and lower data lines 254o to 2544 in vertical orientations each connected to a respective sense line 258o to 2584, respectively, through a respective contact 367. It is noted that the lower data lines 254 and the common source 216 might be connected to sense lines 258 of additional blocks of memory cells (not depicted in Figure 3D).
  • Figure 3E depicts a top-down view of a memory array 300E, which might include the same memory array structure as the memory array 300C.
  • the memory array 300E further depicts sense lines 258o to 258n in vertical orientations, which each might individually correspond to the sense line 258 of Figure 2A. It is recognized that fewer or more sense lines 258 could be utilized, and that fewer or more unit column structures could be associated with each sense line 258.
  • the memory array 300E might further include a common source 216 (not depicted in Figure 3E) in a horizontal orientation connected to each of the sense lines 258 through a respective contact 366 such as depicted in Figure 3D, and lower data lines 254 (not depicted in Figure 3E) in vertical orientations each connected to a respective sense line 258 through a respective contact 367 such as depicted in Figure 3D.
  • a common source 216 (not depicted in Figure 3E) in a horizontal orientation connected to each of the sense lines 258 through a respective contact 366 such as depicted in Figure 3D
  • lower data lines 254 not depicted in Figure 3E
  • Figures 3F-3G are conceptual depictions of a portion of a block of memory cells using an array structure such as depicted in Figure 2B and demonstrating a layout of backside gate lines 244, dummy backside gate line 260, sense select lines 248 and 252, common source 216 and lower data lines 254, according to an additional embodiment.
  • Figure 3F depicts a top-down view of a memory array 300F having a number of unit column structures 256, including unit column structures 256o to 256?, which might correspond to the unit column structures 256o to 256? of Figure 2B, respectively.
  • the memory array 300F further has a number of dummy unit column structures 257, including the dummy unit column structure 257', which might correspond to the dummy unit column structure 257 of Figure 2B.
  • the memory array 300F further depicts a first sense select line 248, backside gate lines 244o to 244s.
  • dummy backside gate line 260, backside gate lines 244r to 2447, and a second sense select line 252 in horizontal orientations which might correspond to the first sense select line 248, the backside gate lines 244o to 244s, the dummy backside gate line 260, the backside gate lines 2444 to 244?, and the second sense select line 252 of Figure 2B, respectively.
  • fewer or more backside gate lines 244 and dummy backside gate lines 260 could be utilized between the sense select lines 248 and 252, and that fewer or more unit column structures 256 could be associated with each backside gate line 244 and fewer or more dummy unit column structures 257 could be associated with each dummy backside gate line 260.
  • Figure 3G depicts a top-down view of a memory array 300G, which might include the same memory array structure as the memory array 300F.
  • the memory array 300G further has a number of dummy unit column structures 257, including the dummy unit column structure 257', which might correspond to the dummy unit column structure 257 of Figure 2B.
  • the memory array 300G further depicts sense lines 258o to 258s in folded orientations, which each might individually correspond to the sense line 258 of Figure 2B.
  • the memory array 300G further depicts a common source 216 in a horizontal orientation connected to each of the sense lines 258 through a respective contact 366, and lower data lines 254o to 254s in vertical orientations each connected to a respective sense line 258o to 258s, respectively, through a respective contact 367. It is noted that the lower data lines 254 and the common source 216 might be connected to sense lines 258 of additional blocks of memory cells (not depicted in Figure 3D).
  • Figure 4A is a conceptual depiction of a portion of a block of memory cells using an array structure such as depicted in Figures 3A and 3B, and demonstrating a layout of upper data line 204 connectivity, according to an embodiment.
  • Figure 4A depicts a top-down view of a memory array 400A having a number of unit column structures 256, which might correspond to the unit column structures 256 of Figures 3A and 3B.
  • the memory array 400 A further depicts sense lines 258o to 2582 in diagonal orientations, which each might individually correspond to the sense line 258 of Figure 2A. It is recognized that fewer or more sense lines 258 could be utilized, and that fewer or more unit column structures could be associated with each sense line 258.
  • the sense lines 258 might be non-orthogonal to, e.g., angled in relation to, the backside gate lines 244.
  • the memory array 400A further depicts a number of upper data lines 204 in vertical orientations, including upper data lines 2O4o to 20421.
  • the upper data lines 204 might be orthogonal to the backside gate lines 244.
  • the upper data line 204s of Figure 4A might correspond to the upper data line 2O4o of Figure 2A
  • the upper data line 2O4io of Figure 4A might correspond to the upper data line 204i of Figure 2A
  • the upper data line 204n of Figure 4A might correspond to the upper data line 2042 of Figure 2A
  • the upper data line 204B of Figure 4A might correspond to the upper data line 204s of Figure 2A
  • the upper data line 20416 of Figure 4A might correspond to the upper data line 2044 of Figure 2A
  • the upper data line 20418 of Figure 4A might correspond to the upper data line 204s of Figure 2A
  • the upper data line 20419 of Figure 4A might correspond to the upper data line 204e of Figure 2A
  • the upper data line 20421 of Figure 4A might correspond to the upper data line 204?
  • upper data lines 204s to 204e are not explicitly depicted in Figure 2A, it is apparent from the figure that the upper data lines 204 of the array of memory cells 200A may be numbered consecutively from upper data line 2O4o to upper data line 204M.
  • Each of the upper data lines 204 might be connected to one or more respective unit column structures 256 through respective contacts 464. It is noted that the upper data lines 204 might be connected to unit column structures 256 of additional blocks of memory cells (not depicted in Figure 4A).
  • a set of upper data lines 204 e.g., upper data lines 2044, 2046, 204?, 2049, 20412, 20414, 204B, and 20417, connected to unit column structures 256 that are capacitively coupled to one sense line 258, e.g., sense line 258i
  • a set of upper data lines 204 may be mutually exclusive from a set of upper data lines 204, e.g., upper data lines 204s, 2O4io, 204n, 204B, 20416, 204B, 20419, and 20421, connected to unit column structures 256 that are capacitively coupled to a different sense line 258, e.g., adjacent (e.g., immediately adjacent) sense line 2582.
  • one or more of the upper data lines 204 connected to unit column structures 256 that are capacitively coupled to sense line 2581 may be interleaved with one or more upper data lines 204 connected to unit column structures 256 that are capacitively coupled to sense line 2582.
  • a set of upper data lines 204 e.g., upper data lines 2O4o, 2042, 204s, 204s, 204s, 2O4io, 204n, and 204B, connected to unit column structures 256 that are capacitively coupled to one sense line 258, e.g., sense line 258o
  • a set of upper data lines 204 e.g., upper data lines 204s, 2O4io, 204n, 204B, 20416, 20418, 20419, and 20421, connected to unit column structures 256 that are capacitively coupled to a different sense line 258, e.g., sense line 2582.
  • Figure 4B is a conceptual depiction of a portion of a block of memory cells using an array structure such as depicted in Figures 3C and 3D, and demonstrating a layout of upper data line 204 connectivity, according to another embodiment.
  • Figure 4B depicts a top-down view of a memory array 400B having a number of unit column structures 256, which might correspond to the unit column structures 256 of Figures 3C and 3D.
  • the memory array 400B further depicts sense lines 258o to 2584 in diagonal orientations, which each might individually correspond to the sense line 258 of Figure 2A.
  • sense lines 258 could be utilized, and that fewer or more unit column structures could be associated with each sense line 258.
  • the sense lines 258 might be non-orthogonal to, e.g., angled in relation to, the backside gate lines 244.
  • the memory array 400B further depicts a number of upper data lines 204 in vertical orientations, including upper data lines 2O4o to 20423.
  • the upper data lines 204 might be orthogonal to the backside gate lines 244.
  • the upper data line 20416 of Figure 4B might correspond to the upper data line 2O4o of Figure 2A
  • the upper data line 204xs of Figure 4B might correspond to the upper data line 204i of Figure 2A
  • the upper data line 20421 of Figure 4B might correspond to the upper data line 2042 of Figure 2A
  • the upper data lines 204 might be connected to unit column structures 256 of additional blocks of memory cells (not depicted in Figure 4B).
  • a set of upper data lines 204 e.g., upper data lines 2O4o, 2042, 204s, and 204?, connected to unit column structures 256 that are capacitively coupled to one sense line 258, e.g., sense line 258o
  • a set of upper data lines 204 may be mutually exclusive from a set of upper data lines 204, e.g., upper data lines 2044, 204e, 2049, and 204n, connected to unit column structures 256 that are capacitively coupled to a different sense line 258, e.g., adjacent sense line 258i.
  • one or more of the upper data lines 204 connected to unit column structures 256 that are capacitively coupled to sense line 258o may be interleaved with one or more upper data lines 204 connected to unit column structures 256 that are capacitively coupled to sense line 258i. This relationship may be true for sets of upper data lines 204 connected to unit column structures 256 that are capacitively coupled to each remaining sense line 258.
  • Figure 4C is a conceptual depiction of a portion of a block of memory cells using an array structure such as depicted in Figures 3C and 3E, and demonstrating a layout of upper data line 204 connectivity, according to a further embodiment.
  • Figure 4C depicts a top-down view of a memory array 400C having a number of unit column structures 256, which might correspond to the unit column structures 256 of Figures 3C and 3E.
  • the memory array 400C further depicts sense lines 258o to 258n in vertical orientations, which each might individually correspond to the sense line 258 of Figure 2A. It is recognized that fewer or more sense lines 258 could be utilized, and that fewer or more unit column structures could be associated with each sense line 258.
  • the sense lines 258 might be orthogonal to the backside gate lines 244.
  • the memory array 400C further depicts a number of upper data lines 204 in vertical orientations, including upper data lines 2O4o to 20423.
  • the upper data lines 204 might be orthogonal to the backside gate lines 244.
  • the upper data line 2O4o of Figure 4C might correspond to the upper data line 2O4o of Figure 2A
  • the upper data lines 204 might be connected to unit column structures 256 of additional blocks of memory cells (not depicted in Figure 4C).
  • a set of upper data lines 204 e.g., upper data lines 2O4o and 204i, connected to unit column structures 256 that are capacitively coupled to one sense line 258, e.g., sense line 258o
  • a set of upper data lines 204 e.g., upper data lines 2042 and 2043.
  • a different sense line 258, e.g., adjacent (e.g., immediately adjacent) sense line 258i there may be no interleaving of sets of upper data lines 204. This relationship may be true for sets of upper data lines 204 connected to unit column structures 256 that are capacitively coupled to each remaining sense line 258.
  • Figure 4D is a conceptual depiction of a portion of a block of memory cells using an array structure such as depicted in Figures 3F and 3G, and demonstrating a layout of upper data line 204 connectivity, according to a further embodiment.
  • Figure 4D depicts a top-down view of a memory array 400D having a number of unit column structures 256 and dummy unit column structures 257, which might correspond to the unit column structures 256 and dummy unit column structures 257, respectively, of Figures 3F and 3G.
  • the memory array 400D further depicts a first sense select line 248, backside gate lines 244o to 244s, dummy backside gate line 260, backside gate lines 2444 to 244?, and a second sense select line 252 in horizontal orientations, which might correspond to the first sense select line 248, the backside gate lines 244o to 244s, the dummy backside gate line 260, the backside gate lines 2444 to 244?, and the second sense select line 252 of Figure 2B, respectively.
  • the memory array 400D further depicts sense lines 258o to 258s in folded orientations, which each might individually correspond to the sense line 258 of Figure 2B. It is recognized that fewer or more sense lines 258 could be utilized, and that fewer or more unit column structures 256 and dummy unit column structures 257 could be associated with each sense line 258.
  • the sense lines 258 might be non-orthogonal to, e.g., angled in relation to, the backside gate lines 244.
  • the memory array 400D further depicts a number of upper data lines 204 in vertical orientations, including upper data lines 2O4o to 2049.
  • the upper data lines 204 might be orthogonal to the backside gate lines 244.
  • the upper data line 20420 of Figure 4D might correspond to the upper data line 2O4o of Figure 2B
  • the upper data line 204xs of Figure 4D might correspond to the upper data line 204i of Figure 2B
  • the upper data line 20417 of Figure 4D might correspond to the upper data line 2042 of Figure 2B
  • the upper data line 20415 of Figure 4D might correspond to the upper data line 204s of Figure 2B.
  • Each of the upper data lines 204 might be connected to one or more respective unit column structures 256 through respective contacts 464.
  • a set of upper data lines 204 e.g., upper data lines 204s, 204s, 204e, and 204s, connected to unit column structures 256 that are capacitively coupled to one sense line 258, e.g., sense line 258o
  • a set of upper data lines 204 e.g., upper data lines 204?, 2049, 204 io, and 20412, connected to unit column structures 256 that are capacitively coupled to a different sense line 258, e.g., adjacent (e.g., immediately adjacent) sense line 2581.
  • one or more of the upper data lines 204 connected to unit column structures 256 that are capacitively coupled to sense line 258o may be interleaved with one or more upper data lines 204 connected to unit column structures 256 that are capacitively coupled to sense line 258i. This relationship may be true for each pair of adjacent sense lines 258.
  • Figures 5A-5N depict an integrated circuit structure, such as a portion of a sense line (e.g., sense line 258 of Figure 2A or 2B) and associated elements, during various stages of fabrication in accordance with embodiments.
  • a conductor 562 might be formed overlying (e.g., on) a dielectric 560.
  • the conductor 562 might be formed of one or more conductive materials.
  • the conductor 562 might comprise, consist of, or consist essentially of conductively doped polysilicon and/or might comprise, consist of, or consist essentially of metal, such as a refractory metal, or a metal-containing material, such as a refractory metal silicide or a metal nitride, e.g., a refractory metal nitride, as well as any other conductive material.
  • the conductor 562 might include tungsten (W) formed overlying the dielectric 560 and titanium nitride (TiN) formed overlying the tungsten.
  • the dielectric 560 might comprise, consist of, or consist essentially of an oxide, e.g., silicon dioxide (SiCh), and/or may comprise, consist of, or consist essentially of a high-K dielectric material, such as aluminum oxides (AlOx), hafnium oxides (HfOx), hafnium aluminum oxides (HfAlOx), hafnium silicon oxides (HfSiOx), lanthanum oxides (LaOx), tantalum oxides (TaOx), zirconium oxides (ZrOx), zirconium aluminum oxides (ZrAlOx), or yttrium oxide (Y2O3), as well as any other dielectric material.
  • AlOx aluminum oxides
  • HfOx hafnium oxides
  • HfAlOx hafnium aluminum oxides
  • HfSiOx hafnium silicon oxides
  • LaOx tantalum oxides
  • ZrOx zirconium oxides
  • High-K dielectrics as used herein means a material having a dielectric constant greater than that of silicon dioxide.
  • the dielectric 560 might further comprise, consist of, or consist essentially of a spin-on dielectric material, e.g., hydrogen silsesquioxane (HSQ), hexamethyldisiloxane, octamethyltrisiloxane, etc., or a high- density-plasma (HDP) oxide.
  • the dielectric 560 might contain silicon dioxide.
  • the dielectric 560 might be formed overlying other circuitry, such as the peripheral circuitry 266 of Figure 2C.
  • the conductor 562 might be patterned to define a lower data line 254. Patterning might include forming a photolithographic mask (not depicted) overlying (e.g., on) the conductor 562 to define areas for removal, followed by a removal process, such as anisotropic etching, for example. The mask might subsequently be removed, such as by an ashing process, for example.
  • a photolithographic mask not depicted
  • anisotropic etching for example.
  • the mask might subsequently be removed, such as by an ashing process, for example.
  • a dielectric 564 might be formed overlying (e.g., on) the dielectric 560 and the lower data line 254.
  • the dielectric 564 might contain one or more dielectric materials, e.g., dielectric materials such as described with reference to the dielectric 560.
  • the dielectric 564 might contain silicon dioxide.
  • a conductor 566 might be formed overlying (e.g., on) the dielectric 564.
  • the conductor 566 might contain one or more conductive materials, e.g., conductive materials such as described with reference to the conductor 562.
  • the conductor 566 might contain tungsten.
  • a dielectric 568 might be formed overlying (e.g., on) the conductor 566.
  • the dielectric 568 might contain one or more dielectric materials, e.g., dielectric materials such as described with reference to the dielectric 560.
  • the dielectric 568 might contain silicon dioxide.
  • the dielectric 568 might include a structure of SiCh/SiN/SiCh, commonly referred to as ONO.
  • a sacrificial material 570 might be formed overlying (e.g., on) the dielectric 568.
  • the sacrificial material 570 might contain a material that can be subjected to removal without significantly affecting the material(s) of the dielectric 568.
  • the sacrificial material 570 might contain silicon nitride (SiN).
  • the conductor 566, dielectric 568 and sacrificial material 570 might be patterned to define backside gate lines 244oo to 244o2, first sense select line 248oo, and first select line 248io, along with instances of the dielectric 568 and sacrificial material 570 overlying each one.
  • a patterned mask might be formed overlying the sacrificial material 570 defining areas for removal, and an anisotropic removal process, e.g., reactive ion etching (RIE), might be used to define the various instances. Spaces or voids between these instances might be filled with a dielectric 572.
  • RIE reactive ion etching
  • the dielectric 572 might contain one or more dielectric materials, e.g., dielectric materials such as described with reference to the dielectric 560.
  • dielectric materials e.g., dielectric materials such as described with reference to the dielectric 560.
  • silicon dioxide could be formed overlying the resulting structure after patterning, and chemical-mechanical polishing (CMP) could be used to remove any excess silicon dioxide overlying the instances of the sacrificial material 570 to produce the structure depicted in Figure 5D.
  • CMP chemical-mechanical polishing
  • the backside gate lines 244oo to 244o2 of Figure 5D might correspond to the backside gate lines 244o to 2442 of Figure 2A or 2B for a first block of memory cells.
  • the first sense select line 248oo of Figure 5D might correspond to the first sense select line 248 of Figure 2A or 2B for the first block of memory cells.
  • the first sense select line 248 io of Figure 5D might correspond to the first sense select line 248 of Figure 2A or 2B for a second block of memory cells sharing a connection to the same lower data line 254.
  • a via might be formed, e.g., using RIE, in one of the instances of the dielectric 572 and filled with conductive material to form a contact 574 to the lower data line 254.
  • the contact 574 might contain one or more conductive materials, e.g., conductive materials such as described with reference to the conductor 562.
  • the contact 574 might include conduct! vely -doped polysilicon (e.g., an N+ type conductivity) formed overlying the lower data line 254 and titanium nitride (TiN) formed overlying the conductively-doped poly silicon.
  • the instances of the sacrificial material 570 might be removed, e.g., using an isotropic removal process, such as chemical or plasma etching, to define voids 576.
  • a semiconductor 578 might be formed overlying (e.g., on), the instances of the dielectric 568, the instances of the dielectric 572, and the contact 574.
  • the semiconductor 578 might comprise, consist of, or consist essentially of polysilicon, singlecrystal silicon or amorphous silicon, as well as any other semiconductive material, such as germanium, silicon-germanium, or silicon-germanium-carbon semiconductors.
  • the semiconductor 578 might be formed, for example, using chemical vapor deposition (CVD), low-pressure CVD (LPCVD), physical vapor deposition (PVD) or atomic layer deposition (ALD).
  • the semiconductor might have a conductivity type, e.g., a first conductivity type.
  • the semiconductor 578 might contain amorphous silicon.
  • the semiconductor 578 might be doped during or following formation.
  • the semiconductor 578 might be a p-type semiconductor.
  • diborane (B2H6) might be added to the reaction gases of a CVD process to form the amorphous silicon in order to incorporate sufficient boron into the semiconductor 578 to achieve a desired threshold voltage of a future pass gate 238, e.g., a dopant concentration of lE18/cm 3 .
  • the semiconductor 578 might be an n-type semiconductor.
  • phosphine might be added to the reaction gases of a CVD process to form the amorphous silicon in order to incorporate sufficient phosphorus into the semiconductor 578 to achieve a desired threshold voltage of a future pass gate 238, e.g., a dopant concentration of 5E18/cm 3 .
  • the semiconductor 578 might be patterned to define a future sense line 258.
  • instances of a dielectric 580 might be formed overlying (e.g., on) the semiconductor 578 and filling the voids 576.
  • the dielectric 580 might contain one or more dielectric materials, e.g., dielectric materials such as described with reference to the dielectric 560.
  • silicon dioxide could be formed overlying the semiconductor 578, and chemical-mechanical polishing (CMP) could be used to remove any excess silicon dioxide overlying the semiconductor 578 to produce the structure depicted in Figure 5H.
  • portions of the semiconductor 578 might be conductively doped using a dopant impurity of a second conductivity type, which might be the same or different than the first conductivity type, e.g., to form source/drain regions.
  • a dopant impurity is an ion, element or molecule, or some combination of ions, elements and/or molecules, added to the semiconductor 578 to impart bulk conductivity to affected portions. Such doping might involve the acceleration of the dopant impurity, as depicted conceptually by arrows 582.
  • the dopant impurity might be an n-type impurity, such as ions of arsenic (As), antimony (Sb), phosphorus (P) or another n-type impurity.
  • Examples of such doping processes might include plasma doping (PLAD) and/or beam-line implantation.
  • An anneal process might be used to diffuse the implanted dopant impurity within portions of the semiconductor 578 not covered by the dielectric 580, thereby defining instances of semiconductor (e.g., channels) 584 having the first conductivity type and instances of conductively-doped semiconductor 586 having the second conductivity type.
  • an instance of semiconductor 584 overlying a backside gate line 244 or sense select line 248 might form one channel region for a future pass gate 238 or first sense select gate 246, respectively, having the backside gate line 244 or sense select line 248, respectively, as its control gate and a corresponding instance of the dielectric 568 as its gate dielectric.
  • instances of the conductively-doped semiconductor 586 on either side of that backside gate line 244 or sense select line 248 might form source/drain regions for that pass gate 238 or first sense select gate 246, respectively.
  • the doping level of the instances of conductively-doped semiconductor 586 might be one or more orders of magnitude higher than the doping level of the instances of semiconductor 584.
  • the doping level of the instances of conductively-doped semiconductor 586 might be 3E19/cm A 3 compared to a doping level of the instances of semiconductor 584 of lE18/cm 3 .
  • a dielectric 568 having an ONO or similar charge trap structure might allow for programming to adjust a threshold voltage of the pass gate 238.
  • a semiconductor 588 might be formed overlying (e.g., on) the instances of dielectric 580 and the exposed portions of the instances of conductively-doped semiconductor 586.
  • the semiconductor 588 might comprise, consist of, or consist essentially of poly silicon, single-crystal silicon or amorphous silicon, as well as any other semiconductive material, such as germanium, silicon-germanium, or silicon-germanium- carbon semiconductors.
  • the semiconductor 588 might be formed such as described with reference to the semiconductor 578, and might have the same conductivity type, e.g., the first conductivity type, or a different conductivity type, e.g., the second conductivity type.
  • the semiconductor 588 might be an p-type amorphous silicon.
  • the semiconductor 588 might be an n-type amorphous silicon.
  • the semiconductor 588 might have a doping level of 5E18/cm 3 .
  • the resulting transistor might be a depletion mode or normally-on transistor.
  • the semiconductor 588 and the conductively-doped semiconductor 586 have different conductivity types, the resulting transistor might be an enhancement mode or normally-off transistor, or a depletion mode or normally-on transistor.
  • the semiconductor 588 might be formed prior to the doping described with reference to Figure 51, and may receive doping concurrently with the conductively-doped semiconductor 586.
  • a first act and a second act occur concurrently when the first act occurs simultaneously with the second act for at least a portion of a duration of the second act.
  • a dielectric 590 might be formed overlying (e.g., on) the semiconductor 588.
  • the dielectric 590 might contain one or more dielectric materials, e.g., dielectric materials such as described with reference to the dielectric 560.
  • the dielectric 590 might contain silicon dioxide.
  • the dielectric 590 might contain a high- K dielectric.
  • a sacrificial material 592 might be formed overlying (e.g., on) the dielectric 590.
  • the sacrificial material 592 might contain a material that can be subjected to removal without significantly affecting the material(s) of the dielectric 590.
  • the sacrificial material 592 might contain silicon nitride (SiN).
  • the semiconductor 588, dielectric 590 and sacrificial material 592 might be patterned to define instances of semiconductor (e.g., channels) 589, along with instances of the dielectric 590 and sacrificial material 592 overlying each one.
  • a patterned mask might be formed overlying the sacrificial material 592 defining areas for removal, and an anisotropic removal process, e.g., reactive ion etching (REI), might be used to define the various instances. Spaces or voids between these instances might be filled with a dielectric 594.
  • the dielectric 594 might contain one or more dielectric materials, e.g., dielectric materials such as described with reference to the dielectric 560.
  • silicon dioxide could be formed overlying the resulting structure, and chemical-mechanical polishing (CMP) could be used to remove any excess silicon dioxide overlying the instances of the sacrificial material 592 to produce the structure depicted in Figure 5K.
  • CMP chemical-mechanical polishing
  • exposed portions of the conduct! vely-doped semiconductor 586 may receive additional doping of a same conductivity type prior to forming the dielectric 594.
  • the instances of the sacrificial material 592 might be removed, e.g., using an isotropic removal process, such as chemical or plasma etching, to define voids 596.
  • plugs 598oo to 598o2 might be formed in the voids 596.
  • conductive material e.g., titanium nitride over tungsten
  • CMP CMP
  • the plugs 598 might be formed of a material selected to act as a stop layer during subsequent processing as described with reference to Figure 6B, and may be sacrificial and removed during subsequent processing, such as described with reference to Figure 6C.
  • the bracket 600 identifies a portion of the integrated circuit structure of Figure 5M that might be depicted in Figures 6A- 6F.
  • Figures 5A-5M depicted an integrated circuit structure that might correspond to a portion of a sense line (e.g., sense line 258 of Figure 2A or 2B) and associated elements at an end adjacent a lower data line 254,
  • Figure 5N might depict another portion of that sense line (e.g., sense line 258 of Figure 2A or 2B) and associated elements at an opposing end, e.g., an end adjacent a common source 216.
  • Figure 5N might be formed concurrently with the structure of Figure 5M, and depicts backside gate lines 244o(M-i) and 244OM and corresponding plugs 598o(M-i) and 598OM, respectively, a second select line 252, and a common source 216 and its connection to an instance of conductively- doped semiconductor 586 through a conductive contact 574.
  • the common source 216 and second sense select line 252 might be formed from the conductor 566 (e.g., as in Figures 5C- 5D) concurrently with the first sense select line 248 and the backside gate lines 244.
  • Figures 6A-6F depict an integrated circuit structure, which might correspond to a portion of a unit column structure 256 of Figure 2A or 2B during various stages of fabrication in accordance with additional embodiments. Figures 6A-6F might be used to depict further processing following formation of the structure of Figure 5M, for example. It will be understood that Figures 6A-6F could equally apply to the formation of a dummy unit column structure 257, where the backside gate line 244x of Figures 6A-6F is instead a dummy backside gate line 260.
  • the backside gate line 244x might correspond to a second control gate 242 of a pass gate 238x , where X might be any integer value from zero to M, with a number of unit column structures 256 associated with a sense line 258 being equal to M + 1.
  • the pass gate 238x might further include channels formed of the semiconductors 584 and 589, gate dielectrics formed of the dielectrics 568 and 590, and source/drain regions formed of the conductively-doped semiconductors 586.
  • a first control gate 240 of the pass gate 238x might not yet be formed, but its future location might correspond to the location of the plug 598x.
  • instances of a dielectric 602 e.g., 6O2o to 6024
  • instances of a sacrificial material 604 e.g., 6O4o to 604s
  • the instances of the dielectric 602 might each contain one or more dielectric materials, e.g., dielectric materials such as described with reference to the dielectric 560.
  • the instances of the dielectric 602 might contain silicon dioxide.
  • the instances of the sacrificial material 604 might contain a material that can be subjected to removal without significantly affecting the material(s) of the dielectric 602.
  • the instances of the sacrificial material 604 might contain silicon nitride. Additional instances of the dielectric 602 and instances of the sacrificial material 604 might be formed, depending upon the number of transistors intended to be formed, e.g., memory cells, GIDL generator gates, select gates and capacitances, for a future unit column structure. While all intended instances of the dielectric 602 and instances of the sacrificial material 604 might be formed before proceeding to the processing of Figure 6B, typical processing of such stacked structures might be performed in stages as the aspect ratio of the via 606 might become too large to form the entire structure reliably as a contiguous entity.
  • a via 606 might be formed through the instances of the dielectric 602 and the instances of the sacrificial material 604, using the plug 598x as a stop.
  • an anisotropic removal process e.g., RIE
  • the plug 598x acting as an etch stop.
  • the via 606 might extend to the surface of the plug 598x or below.
  • the plug 598x might be removed following formation of the via 606 to complete a void 607.
  • a channel material structure 610 might be formed to line the sidewalls of the void 607, e.g., formed along the sidewalls of the instances of the dielectric 602 and the instances of the sacrificial material 604, as well as along sidewalls of the dielectric 594 and a surface (e.g., upper surface) of the dielectric 590.
  • the dielectric 590 might also be removed prior to forming the channel material structure 610, and portions of the channel material structure 610 could function as a gate dielectric to the resulting pass gate 238.
  • the channel material structure 610 might include a charge-blocking material 612 formed to line the void 607, a charge-storage material 614 might be formed on the charge-blocking material 612, a dielectric (e.g., gate dielectric) 616 might be formed on the charge-storage material 614, and a channel material (e.g., a semiconductor) 618 might be formed on the dielectric 616.
  • the charge-storage material 614 might contain a dielectric or conductive charge-storage material.
  • the charge-storage material 614 might further contain both dielectric and conductive materials, e.g., conductive nano- particles in a dielectric bulk material.
  • resulting memory cells might typically be referred to as floating-gate memory cells.
  • charge-storage material 614 containing a dielectric material as its bulk, or contiguous, structure resulting memory cells might typically be referred to as charge-trap memory cells.
  • the chargeblocking material 612, charge-storage material 614 and dielectric 616 might form an ONO structure.
  • the channel material 618 might be a portion of a contiguous semiconductor structure for each transistor of the future unit column structure, or might otherwise be electrically connected, which might include selectively electrically connected, to channels of each transistor of the future unit column structure.
  • the charge-blocking material 612 might function as a charge-blocking node for future memory cells and other transistors of the unit column structure having a same structure, and might include one or more dielectric materials, such as described with reference to the dielectric 560.
  • the charge-blocking material 612 might include a high-K dielectric material.
  • the charge-storage material 614 might function as a chargestorage node for future memory cells and other transistors of the unit column structure having a same structure, and might include one or more conductive or dielectric materials capable of storing a charge.
  • the charge-storage material 614 might include poly silicon, which might be conductively doped.
  • the dielectric 616 might function as a gate dielectric for future memory cells and other transistors of the unit column structure having a same structure, and might include one or more dielectric materials such as described with reference to the dielectric 568.
  • the dielectric 568 might include silicon dioxide.
  • the channel material 618 might function as a channel for future memory cells and other transistors of the unit column structure having a same structure, and might include one or more semiconductors such as described with reference to the semiconductor 578.
  • the instances of sacrificial material 604 might be removed to define voids 620, e.g., voids 62Oo to 620s.
  • the removal might include an isotropic removal process, e.g., a plasma etching process.
  • instances of an optional charge-blocking material 622 e.g., instances of charge-blocking material 622o-622s, might be formed to line the voids 620, e.g., voids 62Oo to 620s, respectively.
  • the instances of charge-blocking material 622 might include one or more dielectric materials, such as described with reference to the dielectric 560, and might include a high-K dielectric material.
  • the instances of charge-blocking material 622 might function as an additional charge-blocking material of a charge-blocking node for future memory cells and other transistors of the unit column structure having a same structure.
  • the instances of charge-blocking material 622 might function individually as a charge-blocking node for future memory cells and other transistors of the unit column structure having a same structure.
  • the charge-blocking material 612 and without the instances of charge-blocking material 622, the charge-blocking material 612 might function individually as a charge-blocking node for future memory cells and other transistors of the unit column structure having a same structure.
  • Instances of a conductor 624 e.g., instances of a conductor 624o to 624s, might be formed to fill the voids 620, e.g., voids 62Oo to 620s, respectively.
  • the instances of the conductor 624 might contain one or more conductive materials, e.g., conductive materials such as described with reference to the conductor 562.
  • a transistor might be formed at each intersection of an instance of the conductor 624 and the channel material 618, where an instance of the conductor 624 might function as a control gate of the transistor, adjacent channel material 618 might function as a channel of the transistor, and an instance of charge-blocking material 622 and/or charge-blocking material 612, charge-storage material 614, and dielectric 616 between the instance of the conductor 624 and the adjacent channel material 618 might function as a charge-blocking node, chargestorage node and gate dielectric, respectively, of that transistor.
  • Such transistors could include memory cells 208, GIDL generator gates 220, upper select gates 212, lower select gates 210, and/or capacitances 226 for a future unit column structure, for example.
  • the channel material 618 adjacent the dielectric 590 might function as the first control gate 240 of a pass gate 238 having the semiconductor 589 as its channel and the dielectric 590 as its gate dielectric, for example.
  • Figure 6F might depict an opposing end of the portion of a unit column structure depicted in Figure 6E.
  • Figure 6E might depict an end of a unit column structure nearest an associated pass gate 238,
  • Figure 6F might depict an end of that unit column structure nearest an associated upper data line 204.
  • Figure 6F might depict further alternating instances of the dielectric 602, e.g., instances of dielectric 602K-5 to 602K+I, instances of charge-blocking material 622, e.g., instances of charge-blocking material 622K-5 to 622K, and instances of conductor 624, e.g., instances of conductor 624K-5 to 624K., where K might equal a total number of memory cells 208 (including any dummy memory cells), GIDL generator gates 220, upper select gates 212, lower select gates 210, and capacitances 226 in a unit column structure, minus 1.
  • the channel material structure 610 depicted in Figure 6F might be contiguous with the channel material structure 610 depicted in Figure 6E.
  • the upper data line 204 might be connected to the channel material 618 of the channel material structure 610 through a contact 464.
  • the contact 464 might contain one or more conductive materials, e.g., conductive materials such as described with reference to the conductor 562.
  • the contact 464 might contain an n + -type conductively-doped polysilicon.
  • the contact 464 might include an n + -type conductively- doped poly silicon formed overlying the channel material structure 610, titanium nitride (TiN) formed overlying the n + -type conductively-doped polysilicon, and tungsten (W) formed overlying the titanium nitride.
  • the upper portion of the channel material 618 of the channel material structure 610 might be doped to an n + -type conductivity
  • the contact 464 might include titanium nitride (TiN) formed overlying the channel material structure 610, and tungsten (W) formed overlying the titanium nitride.
  • TiN titanium nitride
  • W tungsten
  • the channel material 618 of a unit column structure is dead-headed at the bottom of the void 607.
  • the channels of the various transistors of the unit column structure might be selectively connected to only one voltage node, e.g., an upper data line 204, for sourcing or sinking a current to those channels, and would be electrically floating (e.g., permanently electrically floating) but for its connection (e.g., selective connection) to an upper data line 204.
  • Figures 7A-7J depict orthogonal views of various structures for sense lines in accordance with embodiments.
  • Figure 7B depicts a view of the structure of Figure 7A taken along line B-B'.
  • Figure 7D depicts a view of the structure of Figure 7C taken along line D- D'.
  • Figure 7F depicts a view of the structure of Figure 7E taken along line F-F'.
  • Figure 7H depicts a view of the structure of Figure 7G taken along line H-H'.
  • Figure 7J depicts a view of the structure of Figure 71 taken along line J-J'.
  • FIG. 7A and 7B depict an example where the semiconductor 588 first might be patterned concurrently with the semiconductor 578, and then patterned again concurrently with the dielectric 590 and sacrificial material 592.
  • the physical width of the semiconductor 589 e.g., a distance left to right in Figure 7B
  • the semiconductor 584 and conductively-doped semiconductor 586 for a given pass gate 238 might be the same as the semiconductor 584 and conductively-doped semiconductor 586 for a given pass gate 238.
  • the physical length of the semiconductor 589 (e.g., a distance left to right in Figure 7A) might be different than the physical length of the semiconductor 584, but may provide a similar electrical channel length as the semiconductor 584 due to the conductivity level of the conductively-doped semiconductor 586.
  • the semiconductor 578 might be formed as a flat layer instead of a serpentine layer as depicted in Figure 5G.
  • the conductively-doped semiconductor 586 could be formed overlying the semiconductor 578 as an additional layer of semiconductor material, e.g., conductively-doped polysilicon, and subsequently patterned to define blocks of conductively-doped semiconductor 586 as depicted in Figures 7C and 7D. These blocks of conductively-doped semiconductor 586 might act as source/drain regions of a pass gate 238, and may extend to a next pass gate 238 or to a first sense select gate 246 or a second sense select gate 250.
  • Patterning of a semiconductor 588 to define an instance of semiconductor 589 might be performed as described with reference to Figures 7A and 7B to produce the structure depicted in Figures 7C and 7D.
  • the added bulk of the conductively- doped semiconductor 586 in Figures 7C-7D might mitigate the risk of damage to the conductively-doped semiconductor 586 during patterning of the semiconductor 588 to form the semiconductor 589 relative to the embodiment of Figures 7A-7B.
  • the semiconductor 578 might be formed as a flat layer instead of a serpentine layer as depicted in Figure 5G, and selectively conductively doped to define the instances of the semiconductor 584 and conductively-doped semiconductor 586.
  • An instance of the semiconductor 584 might serve as a channel for both control gates of a resulting pass gate 238, e.g., without formation of a semiconductor 589.
  • the semiconductor 578 might be formed around raised portions of the backside gate line 244X, and selectively conductively doped to define the instances of the semiconductor 584 and conductively-doped semiconductor 586.
  • An instance of the semiconductor 584 might serve as a channel for both control gates of a resulting pass gate 238, e.g., without formation of a semiconductor 589.
  • the two channels of a pass gate 238 might be formed of separate contiguous semiconductor materials.
  • the processing of Figures 5C and 5D might proceed without forming the sacrificial material 570, and an instance of semiconductor 578 might be formed after patterning the conductor 566 and the dielectric 568, and forming the dielectric 572, to be overlying the instances of the dielectric 568 and the dielectric 572.
  • This instance of semiconductor 578 might be selectively conductively doped to define the instances of the semiconductor 584i OW er and conductively-doped semiconductor 586iower.
  • a dielectric might then be formed overlying the instances of the semiconductor 584iower and conductively-doped semiconductor 586i OW er, and patterned to define an instance of dielectric 726 for each pass gate 238.
  • Another instance of semiconductor 578 might then be formed overlying the dielectric 726 and the exposed instances of conductively-doped semiconductor 586.
  • This instance of semiconductor 578 might be selectively conductively doped to define the instances of the semiconductor 584 upP er and conductively-doped semiconductor 586 upP er.
  • Figures 8A-8C depict an integrated circuit structure during various stages of fabrication in accordance with an embodiment.
  • Figure 8A might depict a structure similar to that shown in Figure 6A, and might be formed in a similar manner.
  • a conductively-doped polysilicon 830, and an optional barrier layer 832 might be formed between the dielectric 590 and the plug 598.
  • the conductively-doped polysilicon 830 might be formed to line the voids 596 in Figure 5L, and then the plug 598 might be formed to fill a remaining portion of a void 596.
  • the barrier layer 832 might be formed between the conductively-doped polysilicon and the plug 598.
  • the void 607 might be formed in a manner similar to that described with reference to Figures 6B and 6C, including removal of the plug 598 and the barrier layer 832.
  • the channel material structure might then be formed as described with reference to Figure 6C, including the charge-blocking material 612, charge-storage material 614, dielectric 616, and channel material 618.
  • the first control gate 240 of a pass gate 238 might be a discrete conductive element (e.g., conductively-doped polysilicon 830) between the electrode of a capacitance 226 (e.g., a channel of a field-effect transistor or channel material 618) and a channel (e.g., semiconductor 589) of that pass gate 238.
  • Figures 8A-8C utilizes conductively-doped polysilicon, other conductive materials could also be utilized, such as conductive materials described with reference to the conductor 562.
  • conductive materials described with reference to the conductor 562.
  • the example of Figures 8A-8C depicts an embodiment utilizing two discrete channels of a pass gate 238, e.g., forming a separate semiconductor 589, such structures could also be used in embodiments utilizing a single channel.
  • the conductively-doped polysilicon 830 was formed to be below, and adjacent sidewalls of, the channel material 618, it might be formed without extending to a point adjacent the sidewalls of the channel material 618.
  • Figures 9A-9E depict an integrated circuit structure during various stages of fabrication in accordance with another embodiment.
  • Figure 9A might depict a structure similar to that shown in Figure 6A, and might be formed in a similar manner.
  • the dielectric 594 might be formed as a first dielectric 94Oo, a second dielectric 942, and a third dielectric 940i.
  • the dielectrics 94Oo and 940i might be a same dielectric material, while the dielectric 942 might be a different dielectric material.
  • the dielectrics 94Oo and 940i might contain silicon carbon nitride (SiCN), while the dielectric 942 might contain silicon dioxide.
  • a conductively-doped polysilicon 944 might be formed between the dielectric 590 and the plug 598.
  • the conductively-doped polysilicon 944 might be formed to fill a bottom of a void 596 in Figure 5L, and then the plug 598 might be formed to fill a remaining portion of the void 596.
  • a barrier layer (not shown) might be formed between the conductively-doped poly silicon 944 and the plug 598.
  • the void 607 might be formed in a manner similar to that described with reference to Figures 6B and 6C, including removal of the plug 598 and any barrier layer.
  • the channel material structure might then be formed as described with reference to Figure 6C, including the charge-blocking material 612, charge-storage material 614, dielectric 616, and channel material 618.
  • the dielectric 942 might be removed, along with exposed portions of the charge-blocking material 612, charge-storage material 614, and dielectric 616 sufficient to remove the thickness of these materials, e.g., which might leave a recessed portion between the channel material 618 and the conductively- doped poly silicon 944.
  • an isotropic etch process could be used with a chemistry selective to the materials for removal over materials of the channel material 618, conductively-doped polysilicon 944 and the dielectrics 94Oo and 940i.
  • a conductively-doped poly silicon 946 might be selectively grown on exposed surfaces of the channel material 618 and the conductively-doped polysilicon 944 to bridge the gap, and form an electrical connection, between the channel material 618 and the conductively-doped polysilicon 944.
  • the first control gate 240 of a pass gate 238 might be a discrete conductive element (e.g., conductively-doped polysilicon 944 and 946) between the electrode of a capacitance 226 (e.g., a channel of a field-effect transistor or channel material 618) and a channel (e.g., semiconductor 589) of that pass gate 238.
  • a capacitance 226 e.g., a channel of a field-effect transistor or channel material 6108
  • a channel e.g., semiconductor 589
  • Figures 9A-9E depicts an embodiment utilizing two discrete channels of a pass gate 238, e.g., forming a separate semiconductor 589, such structures could also be used in embodiments utilizing a single channel.
  • the conductively-doped poly silicon 946 was formed to be below, and adjacent sidewalls of, the channel material 618, it might be formed without extending to a point adjacent the sidewalls of the channel material 618.
  • forming the dielectric 9401 to be thicker could restrict formation of the conductively-doped poly silicon 946 to be solely below the channel material 618.
  • Figures 10A and 10B depict an integrated circuit structures at a particular stage of fabrication in accordance with further embodiments.
  • the embodiment of Figure 10A might depict a structure similar to that shown in Figure 6C, and might be formed in a similar manner.
  • a high-K dielectric 1050 might be formed between the semiconductor 589 and the plug 598.
  • the high-K dielectric 1050 might be formed to line a lower portion (e.g., a bottom) of a void 596 in Figure 5L, and then the plug 598 might be formed to fill a remaining portion of that void 596.
  • the dielectric 590 might be omitted, with the high-K dielectric 1050 serving as the gate dielectric of the first control gate 240 of a pass gate 238.
  • the void 607 might be formed in a manner similar to that described with reference to Figures 6B and 6C, including removal of the plug 598.
  • the channel material structure 610 might then be formed as described with reference to Figure 6C.
  • the embodiment of Figure 10B might also depict a structure similar to that shown in Figure 6C, and might be formed in a similar manner.
  • a high-K dielectric 1050 might be formed between the semiconductor 589 and the plug 598.
  • the high-K dielectric 1050 might be formed to line a void 596 in Figure 5L e.g., the bottom and sidewalls of the void 596, and then the plug 598 might be formed to fill a remaining portion of that void 596.
  • the dielectric 590 might be omitted, with the high-K dielectric 1050 serving as the gate dielectric of the first control gate 240 of a pass gate 238.
  • the dielectric 590 might be de minimis, e.g., on the order of Inm in thickness.
  • the void 607 might be formed in a manner similar to that described with reference to Figures 6B and 6C, including removal of the plug 598.
  • channel material structure 610 might then be formed as described with reference to Figure 6C.
  • Use of a high-K dielectric in the embodiments of Figures 10A and 10B might facilitate suppression of electron back-tunneling from the sense line 258.
  • Erasing memory cells in the unit column structures of embodiments might proceed similar to a typical string of series-connected memory cells.
  • an erase voltage level might be applied to both ends of the string while the select gates and GG gates are operated to induce GIDL current into the string.
  • an erase voltage level might be applied to the upper data line 204, while the GG gates 220 and upper select gates 212 are operated to induce GIDL current into the unit column structures.
  • the GG gates 220 might receive a voltage level on control line 224, e.g., 1 IV less than the erase voltage level, while the upper select gates 212 might receive a voltage level on select line 215, e.g., 4V less than the erase voltage level.
  • the access lines 202 might receive a nominal voltage level configured to remove charge from the charge storage nodes, e.g., 0.5V.
  • the lower select gates 210 and the capacitances 226 might receive a control gate voltage level configured to inhibit erasure, e.g., 4V less than the erase voltage level.
  • Figure 11 is a timing diagram of a method of operating a memory in accordance with an embodiment.
  • Figure 11 might represent a method of programming one or more memory cells, e.g., a logical page of memory cells.
  • the method might be in the form of computer-readable instructions, e.g., stored to the instruction registers 128.
  • Such computer-readable instructions might be executed by a controller, e.g., the control logic 116, to cause the memory (e.g., relevant components of the memory) to perform the method.
  • the trace 1101 might depict voltage levels of an upper data line 204, e.g., a selected upper data line 204, selectively connected to a memory cell selected for programming during the programming operation, e.g., a selected memory cell to be enabled for programming.
  • the trace 1103 might depict voltage levels of an upper data line 204, e.g., an unselected upper data line 204, selectively connected to a memory cell not selected for programming during the programming operation, e.g., an unselected memory cell to be inhibited from programming.
  • the trace 1105 might depict voltage levels of a select line 215.
  • the trace 1107 might depict voltage levels of an access line 202 connected to a selected memory cell
  • the trace 1109 might depict voltage levels of an access line 202 connected to an unselected memory cell.
  • traces 1101, e.g., selected upper data lines, and 1103, e.g., unselected upper data lines might be increased from an initial voltage level, e.g., a ground potential or 0V, to an inhibit voltage level, e.g., 2.3V.
  • Trace 1105 might be increased from an initial voltage level, e.g., a ground potential or 0V, to a voltage level sufficient to activate the upper select gates, e.g., 4V.
  • control line 224 might also receive a voltage level sufficient to activate the GG gates.
  • Trace 1107 e.g., the selected access line
  • trace 1109 e.g., unselected access lines
  • an initial voltage level e.g., a ground potential or 0V
  • traces 1107 and 1109 might be increased to 4V.
  • trace 1101 might be returned to its initial voltage level.
  • trace 1101 might be decreased to some intermediate voltage level between the inhibit voltage level and its initial voltage level.
  • SSPC selective slow programming convergence
  • memory cells nearer to their respective intended data states are programmed more slowly (e.g., partially enabled for programming) compared to memory cells farther from their respective intended data states (e.g., fully enabled for programming) while receiving a same voltage level at their respective control gates.
  • Different target data states might utilize different intermediate voltage levels.
  • Trace 1105 might be decreased to some voltage level configured to activate upper select gates selectively connected to selected upper data lines, and configured to deactivate upper select gates selectively connected to unselected upper data lines. Remaining traces 1103, 1107 and 1109 might remain at their present voltage levels.
  • traces 1107 and 1109 might be increased to the pass voltage level of the programming operation.
  • the pass voltage level is some voltage level higher than the expected threshold voltage level of each memory cell connected to the selected and unselected access lines, e.g., configured to activate each memory cell regardless of its data state.
  • traces 1107 and 1109 might be increased to 9V.
  • trace 1107 might be increased to a programming voltage level, e.g., 15V or higher.
  • the application of the programming voltage level from time t3 to time t4 might be referred to as a programming pulse.
  • traces 1101 and 1103 might each be transitioned to 0.5V
  • traces 1105, 1107 and 1109 might each be transitioned to 4V.
  • control gate voltage levels to compensation gates, lower select gates and capacitances might remain at an initial voltage level, e.g., a ground potential or 0V.
  • a verify operation might be performed after each programming pulse to determine whether any memory cells have reached their respective intended data states, and/or their respective intermediate data states in the case of SSPC programming. Any memory cells failing to reach their respective intended data states might be enabled for a subsequent programming pulse of a higher programming voltage level. In the case of SSPC programming, memory cells not reaching their respective intermediate data states might be fully enabled for programming during the subsequent memory pulse, and memory cells reaching their respective intermediate data states, but not reaching their respective intended data states, might be partially enabled for programming during the subsequent memory pulse.
  • Figure 12 is a timing diagram of a method of operating a memory in accordance with an embodiment.
  • Figure 12 might represent a method of sensing, e.g., reading or verifying, one or more memory cells, e.g., a logical page of memory cells.
  • the method might be in the form of computer-readable instructions, e.g., stored to the instruction registers 128.
  • Such computer-readable instructions might be executed by a controller, e.g., the control logic 116, to cause the memory (e.g., relevant components of the memory) to perform the method.
  • Figure 12 will refer specifically to elements of Figure 2B, but it is to be understood that this description can be used with other memory array structures disclosed herein.
  • the trace 1211 might depict voltage levels of an upper data line 204, e.g., an upper data line 204 selectively connected to a memory cell selected for sensing during a sense operation, e.g., a selected memory cell.
  • the trace 1211 might correspond to upper data lines 2O4o-2O43.
  • the trace 1213 might depict voltage levels of an access line 202, e.g., a selected access line 202, connected to a selected memory cell
  • the trace 1215 might depict voltage levels of an access line 202, e.g., an unselected access line 202, not connected to a selected memory cell.
  • trace 1213 might correspond to access line 202i
  • trace 1215 might correspond to access lines 2O2O-2O2N other than access line 202i.
  • the trace 1217 might depict voltage levels of a control line 213 connected to compensation gates 211.
  • the trace 1219 might depict voltage levels of lower select lines 214 connected to lower select gates 210.
  • the trace 1221 might depict voltage levels on control lines 228 connected to capacitances 226.
  • the traces 1223o and 12231 might depict voltage levels of the channels of the capacitances 226, e.g., a sense node, capacitively coupled to, or connected to, a first control gate 240 of a pass gate 238 for a unit column structure 256 whose selected memory cell is deactivated in response to a read voltage level, and for a unit column structure 256 whose selected memory cell is activated in response to a read voltage level, respectively.
  • the traces 1225o to 1225s might depict voltage levels of backside gate lines 244, e.g., backside gate lines 244o to 2443 of the sub-block of memory cells 262o when the selected memory cells are contained in the unit column structures 256o to 2563.
  • trace 1211 might be increased from an initial voltage level, e.g., a ground potential or 0V, to a precharge voltage level.
  • the precharge voltage level might be some voltage level configured to activate a first control gate 240 of a pass gate 238, e.g., for an enhancement type device, or deactivate a first control gate 240 of a pass gate 238, e.g., for a depletion type device.
  • the precharge voltage level might be 4V.
  • the traces 1213 and 1215 might be increased from an initial voltage level, e.g., a ground potential or 0V, to a pass voltage level of the sense operation.
  • the pass voltage level is some voltage level higher than the expected threshold voltage level of each memory cell connected to the selected and unselected access lines, e.g., configured to activate each memory cell regardless of its data state. For example, traces 1213 and 1215 might be increased to 9V.
  • traces 1217, 1219 and 1221 might be increased from an initial voltage level, e.g., a ground potential or 0V, to some voltage levels configured to activate their corresponding compensation gates 211, lower select gates 210, and capacitances 226, respectively.
  • an initial voltage level e.g., a ground potential or 0V
  • upper select lines 215 and control line 224 might also receive voltage levels configured to activate their upper select gates 212 and GG gates 220, respectively. Because these transistors are generally not programmed to the same threshold voltage levels as the memory cells, this voltage level might be lower, e.g., 2-3V.
  • traces 1223o and 12231 might increase toward a voltage level of trace 1211 at time tO.
  • the traces 1225o to 1225s might be increased to a voltage level configured to activate a second select gate 242 of each corresponding pass gate 238.
  • voltage levels applied to the backside gate lines 2444 to 244?, and the dummy backside gate line 260 might also be configured to activate their corresponding pass gates 238.
  • the trace 1213 might be decreased to a read voltage level for the sense operation.
  • the read voltage level might be some voltage level configured to distinguish between adjacent data states. As such, depending upon the data state programmed to memory cells receiving the read voltage at its control gate, that memory cells may or may not remain activated.
  • trace 1211 might be decreased from the precharge voltage level to some lower voltage level.
  • the lower voltage level might be some voltage level configured to deactivate a first control gate 240 of a pass gate 238, e.g., for an enhancement type device, or activate a first control gate 240 of a pass gate 238, e.g., for a depletion type device.
  • the lower voltage level might be its initial voltage level. If the selected memory cell of a unit column structure 256 is deactivated at time t2, its sense node might be represented by the trace 1223o. If the selected memory cell of a unit column structure 256 is activated at time t2, its sense node might be represented by the trace 12231.
  • trace 1219 might be decreased to some voltage level configured to deactivate its corresponding lower select gates 210, e.g., its initial voltage level. This might serve to isolate, e.g., trap, the charge of its corresponding sense node from its corresponding upper data line.
  • the trace 1217 might be increased such that the compensation gates 211 might absorb displacement charge from the lower select gates 210. Note that this discussion of trace 1217 might be moot for embodiments not utilizing compensation gates 211.
  • the sense nodes trapping charge configured to either activate or deactivate the first control gates 240 of their respective pass gates 238, selective activation of the second control gates 242 of their respective pass gates 238 can be used to determine whether their respective selected memory cells were activated or deactivated at time t2, such that the respective data states of those memory cells might be determined.
  • the second control gates 242 for each of the pass gates 238 could be deactivated sequentially while the second control gates 242 for remaining pass gates 238 remain activated.
  • the trace 1225o might be transitioned to a voltage level configured to deactivate the second control gate 242 of its corresponding pass gate 238 while traces 12251 to 1225 s (and backside gate lines 2444 to 244? and dummy backside gate line 260) might be maintained at a voltage level configured to activate the second control gates 242 of their respective pass gates 238.
  • the presence or absence of an electrical path between the lower data line 254 and the common source 216 might then be detected in manners well understood, such as sensing a current flow through, or a voltage change of, the lower data line 254.
  • the trace 1225o might then be returned to a voltage level configured to activate the second control gate 242 of is corresponding pass gate 238, and this process might be repeated for each remaining trace 12251 to 1225s.
  • the trace 12251 might be transitioned to a voltage level configured to deactivate the second control gate 242 of its corresponding pass gate 238 at time t5
  • the trace 12252 might be transitioned to a voltage level configured to deactivate the second control gate 242 of its corresponding pass gate 238 at time t6
  • the trace 1225 s might be transitioned to a voltage level configured to deactivate the second control gate 242 of its corresponding pass gate 238 at time t7
  • the remaining traces 1225 (and backside gate lines 2444 to 244? and dummy backside gate line 260) might be maintained at a voltage level configured to activate the second control gates 242 of their respective pass gates 238 at times when they are not transitioned low.
  • Figure 13 is a timing diagram of a method of operating a memory in accordance with another embodiment.
  • Figure 13 might represent a method of sensing, e.g., reading or verifying, one or more memory cells, e.g., a logical page of memory cells.
  • the method might be in the form of computer-readable instructions, e.g., stored to the instruction registers 128.
  • Such computer-readable instructions might be executed by a controller, e.g., the control logic 116, to cause the memory (e.g., relevant components of the memory) to perform the method.
  • Figure 13 will refer specifically to elements of Figure 2B, but it is to be understood that this description can be used with other memory array structures disclosed herein.
  • the trace 1331 might depict voltage levels of an upper data line 204, e.g., an upper data line 204 selectively connected to a memory cell selected for sensing during a sense operation, e.g., a selected memory cell.
  • the trace 1331 might correspond to upper data lines 2O4o-2O43.
  • the trace 1333 might depict voltage levels of an access line 202, e.g., a selected access line 202, connected to a selected memory cell
  • the trace 1335 might depict voltage levels of an access line 202, e.g., an unselected access line 202, not connected to a selected memory cell.
  • trace 1333 might correspond to access line 202i
  • trace 1335 might correspond to access lines 2O2O-2O2N other than access line 202i.
  • the trace 1337 might depict voltage levels of a control line 213 connected to compensation gates 211.
  • the trace 1339 might depict voltage levels of lower select lines 214 connected to lower select gates 210.
  • the trace 1341 might depict voltage levels on control lines 228 connected to capacitances 226.
  • the traces 1343o and 13431 might depict voltage levels of the channels of the capacitances 226, e.g., a sense node, capacitively coupled to, or connected to, a first control gate 240 of a pass gate 238 for a unit column structure 256 whose selected memory cell is deactivated in response to a read voltage level, and for a unit column structure 256 whose selected memory cell is activated in response to a read voltage level, respectively.
  • the traces 1345o to 1345s might depict voltage levels of backside gate lines 244, e.g., backside gate lines 244o to 244s of the sub-block of memory cells 262o when the selected memory cells are contained in the unit column structures 256o to 256s.
  • trace 1331 might be increased from an initial voltage level, e.g., a ground potential or 0V to some voltage level that might be selected to mitigate drain induced barrier lowering (DIBL) and to mitigate read disturb.
  • the trace 1331 might be increased to IV.
  • the traces 1343o and 13431 might increase due to the increase of the trace 1331.
  • the traces 1333 and 1335 might be increased from an initial voltage level, e.g., IV, to a pass voltage level of the sense operation.
  • the pass voltage level is some voltage level higher than the expected threshold voltage level of each memory cell connected to the selected and unselected access lines, e.g., configured to activate each memory cell regardless of its data state.
  • traces 1333 and 1335 might be increased to 9V.
  • traces 1337, 1339 and 1341 might be increased from an initial voltage level, e.g., a ground potential or 0V, to some voltage levels configured to activate their corresponding compensation gates 211, lower select gates 210, and capacitances 226, respectively.
  • an initial voltage level e.g., a ground potential or 0V
  • upper select lines 215 and control line 224 might also receive voltage levels configured to activate their upper select gates 212 and GG gates 220, respectively. Because these transistors are generally not programmed to the same threshold voltage levels as the memory cells, this voltage level might be lower, e.g., 2-3V.
  • the trace 1339 might be decreased to some voltage level configured to deactivate its corresponding lower select gates 210, e.g., its initial voltage level. This might serve to isolate the capacitances 226 from their corresponding upper data line 204. At this time, the trace 1337 might be increased. Note that this discussion of trace 1337 might be moot for embodiments not utilizing compensation gates 211.
  • the control lines 228 might be biased to boost the channels of the capacitances 226 such the traces 1343o and 13431 might further increase.
  • the increase in voltage level of trace 1341 might be sufficient to boost the traces 1343o and 13431 to some precharge voltage level configured to activate a first control gate 240 of a pass gate 238, e.g., for an enhancement type device, or deactivate a first control gate 240 of a pass gate 238, e.g., for a depletion type device.
  • the precharge voltage level might be 4V.
  • the trace 1333 might be decreased to a read voltage level for the sense operation.
  • the read voltage level might be some voltage level configured to distinguish between adjacent data states. As such, depending upon the data state programmed to memory cells receiving the read voltage at its control gate, that memory cells may or may not remain activated.
  • the trace 1339 might be increased to a voltage level sufficient to activate the corresponding lower select gates 210.
  • the voltage level of trace 1339 between times t5 and t6 might be selected to limit a voltage level of the channel of a selected memory cell to a value near the voltage level of the trace 1331 at time t5. If the selected memory cell of a unit column structure 256 is deactivated at time t5, its sense node might be represented by the trace 1343o. If the selected memory cell of a unit column structure 256 is activated at time t5, its sense node might be represented by the trace 13431.
  • the trace 1331 might be decreased to some lower voltage level.
  • the lower voltage level might be some voltage level configured to deactivate a first control gate 240 of a pass gate 238, e.g., for an enhancement type device, or activate a first control gate 240 of a pass gate 238, e.g., for a depletion type device.
  • the lower voltage level might be its initial voltage level. This might result in a further decrease in the voltage level of the trace 13431.
  • the trace 1339 might be decreased to some voltage level configured to deactivate its corresponding lower select gates 210, e.g., its initial voltage level. This might serve to isolate, e.g., trap, the charge of its corresponding sense node from its corresponding upper data line.
  • sense nodes trapping charge configured to either activate or deactivate the first control gates 240 of their respective pass gates 238, selective activation of the second control gates 242 of their respective pass gates 238 can be used to determine whether their respective selected memory cells were activated or deactivated at time t6, such that the respective data states of those memory cells might be determined.
  • the trace 1345o might be transitioned to a voltage level configured to deactivate the second control gate 242 of its corresponding pass gate 238 while traces 13451 to 1345s (and backside gate lines 2444 to 244? and dummy backside gate line 260) might be maintained at a voltage level configured to activate the second control gates 242 of their respective pass gates 238.
  • the presence or absence of an electrical path between the lower data line 254 and the common source 216 might then be detected in manners well understood, such as sensing a current flow through, or a voltage change of, the lower data line 254.
  • the trace 1345o might then be returned to a voltage level configured to activate the second control gate 242 of is corresponding pass gate 238, and this process might be repeated for each remaining trace 13451 to 1345s.
  • the trace 13451 might be transitioned to a voltage level configured to deactivate the second control gate 242 of its corresponding pass gate 238 at time t9
  • the trace 13452 might be transitioned to a voltage level configured to deactivate the second control gate 242 of its corresponding pass gate 238 at time tlO
  • the trace 1345s might be transitioned to a voltage level configured to deactivate the second control gate 242 of its corresponding pass gate 238 at time til
  • the remaining traces 1345 (and backside gate lines 2444 to 244? and dummy backside gate line 260) might be maintained at a voltage level configured to activate the second control gates 242 of their respective pass gates 238 at times when they are not transitioned low.
  • Figure 14 is a timing diagram of a method of operating a memory in accordance with a further embodiment.
  • Figure 14 might represent a method of sensing, e.g., reading or verifying, one or more memory cells, e.g., a logical page of memory cells.
  • the method might be in the form of computer-readable instructions, e.g., stored to the instruction registers 128.
  • Such computer-readable instructions might be executed by a controller, e.g., the control logic 116, to cause the memory (e.g., relevant components of the memory) to perform the method.
  • Figure 14 will refer specifically to elements of Figure 2B, but it is to be understood that this description can be used with other memory array structures disclosed herein.
  • the trace 1451 might depict voltage levels of an upper data line 204, e.g., an upper data line 204 selectively connected to a memory cell selected for sensing during a sense operation, e.g., a selected memory cell.
  • the trace 1451 might correspond to upper data lines 2O4o-2O43.
  • the trace 1453 might depict voltage levels of an access line 202, e.g., a selected access line 202, connected to a selected memory cell
  • the trace 1455 might depict voltage levels of an access line 202, e.g., an unselected access line 202, not connected to a selected memory cell.
  • trace 1453 might correspond to access line 202i
  • trace 1455 might correspond to access lines 2O2O-2O2N other than access line 202i.
  • the trace 1459 might depict voltage levels of lower select lines 214 connected to lower select gates 210.
  • the trace 1461 might depict voltage levels on control lines 228 connected to capacitances 226.
  • the traces 1463o and 14631 might depict voltage levels of the channels of the capacitances 226, e.g., a sense node, capacitively coupled to, or connected to, a first control gate 240 of a pass gate 238 for a unit column structure 256 whose selected memory cell is deactivated in response to a read voltage level, and for a unit column structure 256 whose selected memory cell is activated in response to a read voltage level, respectively.
  • the traces 1465o to 1465s might depict voltage levels of backside gate lines 244, e.g., backside gate lines 244o to 244s of the sub-block of memory cells 262o when the selected memory cells are contained in the unit column structures 256o to 256s.
  • trace 1451 might be increased from an initial voltage level, e.g., a ground potential or 0V, to a precharge voltage level.
  • the precharge voltage level might be some voltage level configured to activate a first control gate 240 of a pass gate 238, e.g., for an enhancement type device, or deactivate a first control gate 240 of a pass gate 238, e.g., for a depletion type device.
  • the precharge voltage level might be 4V.
  • the traces 1453 and 1455 might be increased from an initial voltage level, e.g., a ground potential or 0V, to a pass voltage level of the sense operation.
  • the pass voltage level is some voltage level higher than the expected threshold voltage level of each memory cell connected to the selected and unselected access lines, e.g., configured to activate each memory cell regardless of its data state. For example, traces 1453 and 1455 might be increased to 9V.
  • traces 1459 and 1461 might be increased from an initial voltage level, e.g., a ground potential or 0V, to some voltage levels configured to activate their corresponding lower select gates 210 and capacitances 226, respectively.
  • an initial voltage level e.g., a ground potential or 0V
  • upper select lines 215 and control line 224 might also receive voltage levels configured to activate their upper select gates 212 and GG gates 220, respectively. Because these transistors are generally not programmed to the same threshold voltage levels as the memory cells, this voltage level might be lower, e.g., 2-3V.
  • traces 1463o and 14631 might increase toward a voltage level of trace 1451 at time tO.
  • the traces 1465o to 1465s might be increased to a voltage level configured to activate a second select gate 242 of each corresponding pass gate 238.
  • voltage levels applied to the backside gate lines 2444 to 244?, and the dummy backside gate line 260 might also be configured to activate their corresponding pass gates 238.
  • the trace 1453 might be decreased to a read voltage level for the sense operation.
  • the read voltage level might be some voltage level configured to distinguish between adjacent data states. As such, depending upon the data state programmed to memory cells receiving the read voltage at its control gate, that memory cells may or may not remain activated.
  • trace 1451 might be decreased from the precharge voltage level to some lower voltage level.
  • the lower voltage level might be some voltage level configured to deactivate a first control gate 240 of a pass gate 238, e.g., for an enhancement type device, or activate a first control gate 240 of a pass gate 238, e.g., for a depletion type device.
  • the lower voltage level might be its initial voltage level. If the selected memory cell of a unit column structure 256 is deactivated at time t2, its sense node might be represented by the trace 1463o. If the selected memory cell of a unit column structure 256 is activated at time t2, its sense node might be represented by the trace 14631.
  • trace 1459 might be decreased to some voltage level configured to deactivate its corresponding lower select gates 210, e.g., its initial voltage level. This might serve to isolate, e.g., trap, the charge of its corresponding sense node from its corresponding upper data line. With the sense nodes isolated from their corresponding upper data lines, the traces 1453 and 1455 optionally might be discharged at time t4, e.g., to their initial voltage levels/
  • the sense nodes trapping charge configured to either activate or deactivate the first control gates 240 of their respective pass gates 238, selective activation of the second control gates 242 of their respective pass gates 238 can be used to determine whether their respective selected memory cells were activated or deactivated at time t2, such that the respective data states of those memory cells might be determined.
  • the trace 1465o might be transitioned to a voltage level configured to deactivate the second control gate 242 of its corresponding pass gate 238 while traces 14651 to 1465 s (and backside gate lines 2444 to 244? and dummy backside gate line 260) might be maintained at a voltage level configured to activate the second control gates 242 of their respective pass gates 238.
  • the presence or absence of an electrical path between the lower data line 254 and the common source 216 might then be detected in manners well understood, such as sensing a current flow through, or a voltage change of, the lower data line 254. This in turn can indicate whether the corresponding selected memory cell was activated or deactivated in response to the read voltage, which can thus indicate its data state in a manner similar to typical NAND memory.
  • the trace 1465o might then be returned to a voltage level configured to activate the second control gate 242 of is corresponding pass gate 238, and this process might be repeated for each remaining trace 14651 to 1465s.
  • the trace 14651 might be transitioned to a voltage level configured to deactivate the second control gate 242 of its corresponding pass gate 238 at time t5
  • the trace 14652 might be transitioned to a voltage level configured to deactivate the second control gate 242 of its corresponding pass gate 238 at time t6
  • the trace 1465 s might be transitioned to a voltage level configured to deactivate the second control gate 242 of its corresponding pass gate 238 at time t7
  • the remaining traces 1465 (and backside gate lines 2444 to 244? and dummy backside gate line 260) might be maintained at a voltage level configured to activate the second control gates 242 of their respective pass gates 238 at times when they are not transitioned low.
  • a first example includes a memory, comprising a non-volatile memory cell; a capacitance selectively connected to the non-volatile memory cell; a field-effect transistor, wherein the field-effect transistor comprises a control gate and a channel, and wherein the channel of the field-effect transistor is capacitively coupled to an electrode of the capacitance; and a controller for access of the non-volatile memory cell.
  • the controller during a sense operation of the memory, is configured to cause the memory to increase a voltage level of the electrode of the capacitance; selectively discharge the voltage level of the electrode of the capacitance through the non-volatile memory cell responsive to a data state stored in the nonvolatile memory cell; and determine whether the field-effect transistor is activated in response to a remaining voltage level of the electrode of the capacitance.
  • a second example includes the memory of the first example, wherein the controller being configured to cause the memory to increase the voltage level of the electrode of the capacitance comprises the controller being configured to cause the memory to increase the voltage level of the electrode of the capacitance to a voltage level configured to activate the field-effect transistor.
  • a third example includes the memory of the first example, wherein the controller being configured to cause the memory to increase the voltage level of the electrode of the capacitance comprises the controller being configured to cause the memory to increase the voltage level of the electrode of the capacitance through the non-volatile memory cell.
  • a fourth example includes the memory of the first example, wherein the electrode of the capacitance is a first electrode of the capacitance, and wherein the controller being configured to cause the memory to increase the voltage level of the electrode of the capacitance comprises the controller being configured to cause the memory to bias a second electrode of the capacitance while the first electrode of the capacitance is isolated from the non-volatile memory cell.
  • a fifth example includes the memory of the first example, wherein the field-effect transistor is a first field-effect transistor of a pass gate comprising the first field-effect transistor and a second field-effect transistor connected in parallel.
  • a sixth example includes the memory of the first example, wherein the capacitance comprises a plurality of series-connected field-effect transistors, and wherein the electrode of the capacitance comprises a channel of each field-effect transistor of the plurality of series-connected field-effect transistors.
  • a seventh example includes a memory, comprising a plurality of non-volatile memory cells comprising a plurality of strings of series-connected non-volatile memory cells; a plurality of first data lines; a second data line; a source; a plurality of pass gates connected in series between the second data line and the source, wherein each pass gate of the plurality of pass gates comprises a first channel, a second channel, a first control gate capacitively coupled to its first channel, and a second control gate capacitively coupled to its second channel; a plurality of capacitances, wherein, for each capacitance of the plurality of capacitances, an electrode of that capacitance is selectively connected to a respective string of series-connected non-volatile memory cells of the plurality of strings of series-connected non-volatile memory cells, and the electrode of that capacitance is capacitively coupled to the first channel of a respective pass gate of the plurality of pass gates; and a controller for access of the non-volatile memory cell
  • the controller during a sense operation of the memory, is configured to cause the memory to, for each capacitance of the plurality of capacitances, increase a voltage level of the electrode of that capacitance; for each capacitance of the plurality of capacitances, selectively discharge the voltage level of the electrode of that capacitance through its respective string of series-connected non-volatile memory cells responsive to a data state stored in a particular non-volatile memory cell of its respective string of series-connected non-volatile memory cells; and for each capacitance of the plurality of capacitances, determine whether the first control gate of the respective pass gate of that capacitance is activated in response to a remaining voltage level of the electrode of that capacitance.
  • An eighth example includes the memory of the seventh example, wherein the controller is further configured to determine the data state stored in the particular non-volatile memory cell of the respective string of series-connected non-volatile memory cells for a particular capacitance in response to determining whether the first control gate of the respective pass gate of the particular capacitance is activated.
  • a ninth example includes the memory of the seventh example, wherein the controller being configured to determine whether the first control gate of a particular pass gate of the plurality of pass gates is activated comprises the controller being configured to determine whether the first control gate of the particular pass gate is activated while the second control gate of each pass gate of the plurality of pass gates other than the particular pass gate is activated.
  • a tenth example includes the memory of the seventh example, wherein the controller being configured to cause the memory to increase the voltage level of the electrode of a particular capacitance comprises the controller being configured to cause the memory to increase the voltage level of the electrode of the particular capacitance to a first voltage level, and wherein the controller being configured to cause the memory to selectively discharge the voltage level of the electrode of the particular capacitance comprises the controller being configured to cause the memory to selectively discharge the voltage level of the electrode of the particular capacitance to a second voltage level lower than the first voltage level.
  • An eleventh example includes the memory of the tenth example, wherein the first voltage level is configured to activate the first control gate of the respective pass gate capacitively coupled to the electrode of the particular capacitance, and wherein the second voltage level is configured to deactivate the first control gate of the respective pass gate capacitively coupled to the electrode of the particular capacitance.
  • a twelfth example includes the memory of the seventh example, wherein the controller being configured to cause the memory to determine, for each capacitance of the plurality of capacitances, whether the first control gate of the respective pass gate of that capacitance is activated in response to a remaining voltage level of the electrode of that capacitance comprises the controller being configured to cause the memory to determine, for each capacitance of the plurality of capacitances in sequence, whether the first control gate of the respective pass gate of that capacitance is activated in response to a remaining voltage level of the electrode of that capacitance.
  • a thirteenth example includes the memory of the twelfth example, wherein the controller being configured to cause the memory to determine whether the first control gate of the respective pass gate of a particular capacitance is activated in response to a remaining voltage level of the electrode of that capacitance comprises the controller being configured to cause the memory to determine whether the first control gate of the respective pass gate of the particular capacitance is activated while the second control gate of the respective pass gate of the particular capacitance is deactivated and while the second control gate of each pass gate of the plurality of pass gates other than the respective pass gate of the particular capacitance is activated.
  • a fourteenth example includes a memory, comprising a plurality of first data lines; a second data line; a source; a plurality of pass gates connected in series between the second data line and the source, wherein each pass gate of the plurality of pass gates comprises a first channel, a second channel, a first control gate capacitively coupled to its first channel, and a second control gate capacitively coupled to its second channel; a plurality of unit column structures, wherein each unit column structure of the plurality of unit column structures comprises a respective string of series-connected non-volatile memory cells, and wherein each unit column structure of the plurality of unit column structures is capacitively coupled to the first channel of a respective pass gate of the plurality of pass gates; a plurality of access lines, wherein each access line of the plurality of access lines is connected to a control gate of a respective non-volatile memory cell of the respective string of series- connected non-volatile memory cells for each unit column structure of the plurality of unit column structures; and a controller for
  • the controller during a programming operation of the memory, is configured to cause the memory to apply a first voltage level to each first data line of a first subset of first data lines of the plurality of first data lines, and apply a second voltage level, different than the first voltage level, to each first data line of a second subset of first data lines of the plurality of first data lines; connect the respective string of series-connected non-volatile memory cells for each unit column structure of the plurality of unit column structures that is selectively connected to a respective first data line of the first subset of data lines to its respective first data line of the first subset of data lines; isolate the respective string of series-connected non-volatile memory cells for each unit column structure of the plurality of unit column structures that is selectively connected to a respective first data line of the second subset of data lines from its respective first data line of the second subset of data lines; increase a voltage level applied to each access line of the plurality of access line to a pass voltage level; and increase the voltage level applied to a particular access line of the plurality of
  • a fifteenth example includes the memory of the fourteenth example, wherein the pass voltage level is higher than an expected threshold voltage level of each memory cell of the respective string of series-connected non-volatile memory cells for each unit column structure of the plurality of unit column structures.
  • a sixteenth example includes the memory of the fourteenth example, wherein the second voltage level is higher than the first voltage level.
  • a seventeenth example includes the memory of the fourteenth example, wherein the programming voltage level is a first programming voltage level, and wherein the controller is further configured to cause the memory to apply the first voltage level to each first data line of a third subset of first data lines of the plurality of first data lines, and apply the second voltage level to each first data line of a fourth subset of first data lines of the plurality of first data lines; connect the respective string of series -connected non-volatile memory cells for each unit column structure of the plurality of unit column structures that is selectively connected to a respective first data line of the third subset of data lines to its respective first data line of the third subset of data lines; isolate the respective string of series- connected non-volatile memory cells for each unit column structure of the plurality of unit column structures that is selectively connected to a respective first data line of the fourth subset of data lines from its respective first data line of the fourth subset of data lines; increase a voltage level applied to each access line of the plurality of access line to the pass voltage level; and increase
  • An eighteenth example includes the memory of the seventeenth example, wherein a number of first access lines of the fourth subset of first access lines is greater than or equal to a number of first access lines of the second subset of first access lines, and wherein a number of first access lines of the third subset of first access lines is less than or equal to a number of first access lines of the first subset of first access lines.
  • a nineteenth example includes the memory of the eighteenth example, wherein the fourth subset of first access lines includes each first access line of the second subset of first access lines.
  • a twentieth example includes the memory of the nineteenth example, wherein the third subset of first access lines includes less than all first access lines of the first subset of first access lines.
  • a twenty -first example includes an array of memory cells, comprising a data line; a source; a plurality of pass gates connected in series between the data line and the source, wherein each pass gate of the plurality of pass gates comprises a first channel, a second channel, a first control gate capacitively coupled to its first channel, a second control gate capacitively coupled to its second channel, a first source/drain region connected to its first channel and to its second channel, and a second source/drain region connected to its first channel and to its second channel; a plurality of unit column structures, wherein each unit column structure of the plurality of unit column structures comprises a respective plurality of series-connected non-volatile memory cells connected in series with a respective plurality of series-connected field-effect transistors, wherein a channel of each non-volatile memory cell of the plurality of series-connected non-volatile memory cells and a channel of each fieldeffect transistor of the plurality of series-connected field-effect transistors are selectively connected to one another; and
  • a twenty-second example includes the array of memory cells of the twenty -first example, wherein, for each unit column structure of the plurality of unit column structures, a material forming the channel of the particular field-effect transistor of its respective plurality of field-effect transistors is electrically connected to the first control gate of its respective pass gate.
  • a twenty -third example includes the array of memory cells of the twenty -first example, wherein, for each unit column structure of the plurality of unit column structures, a material forming the channel of the particular field-effect transistor of its respective plurality of field-effect transistors is capacitively coupled to the first control gate of its respective pass gate.
  • a twenty -fourth example includes the array of memory cells of the twenty-third example, further comprising a high-K dielectric between the material forming the channel of the particular field-effect transistor of the respective plurality of field-effect transistors of a particular unit column structure and the first channel of the respective pass gate of the particular unit column structure, wherein the high-K dielectric is formed below the material forming the channel of the particular field-effect transistor of the respective plurality of fieldeffect transistors of the particular unit column structure.
  • a twenty -fifth example includes the array of memory cells of the twenty-fourth example, wherein the high-K dielectric is further formed adjacent sidewalls of the material forming the channel of the particular field-effect transistor of the respective plurality of fieldeffect transistors of a particular unit column structure.
  • a twenty-sixth example includes the array of memory cells of the twenty-first example, wherein the first control gate of a particular pass gate of the plurality of pass gates is permanently electrically floating.
  • a twenty -seventh example includes the array of memory cells of the twenty-first example, wherein the first source/drain region and the second source/drain region of a particular pass gate of the plurality of pass gates each comprise a respective conductively- doped portion of an instance of a semiconductor.
  • a twenty-eighth example includes the array of memory cells of the twentyseventh example, wherein the instance of the semiconductor has a serpentine shape.
  • a twenty -ninth example includes the array of memory cells of the twenty -seventh example, wherein the first channel of the particular pass gate and the second channel of the particular pass gate are a same channel of the particular pass gate.
  • a thirtieth example includes the array of memory cells of the twenty-seventh example, wherein the instance of the semiconductor contains the second channel of the particular pass gate.
  • a thirty -first example includes the array of memory cells of the twenty-seventh example, wherein the instance of the semiconductor is a first instance of the semiconductor, and wherein the first source/drain region and the second source/drain region of the particular pass gate each further comprise a respective conductively-doped portion of a second instance of a semiconductor.
  • a thirty-second example includes the array of memory cells of the thirty -first example, wherein the first instance of the semiconductor contains the second channel of the particular pass gate, and wherein the second instance of the semiconductor contains the first channel of the particular pass gate.
  • a thirty -third example includes the array of memory cells of the twenty -first example, wherein the first channel of a particular pass gate of the plurality of pass gates comprises a first semiconductor, wherein the second channel of the particular pass gate comprises a second semiconductor, wherein the first source/drain region of the particular pass gate comprises a first instance of conductively-doped semiconductor formed between the first semiconductor and the second semiconductor, and wherein the second source/drain region the particular pass gate comprises a second instance of the conductively-doped semiconductor formed between the first semiconductor and the second semiconductor.
  • a thirty -fourth example includes an array of memory cells, comprising a data line; a source; a plurality of pass gates connected in series between the data line and the source, wherein each pass gate of the plurality of pass gates comprises a first channel, a second channel, a first control gate capacitively coupled to its first channel, a second control gate capacitively coupled to its second channel, a first source/drain region connected to its first channel and to its second channel, and a second source/drain region connected to its first channel and to its second channel; a plurality of unit column structures, wherein each unit column structure of the plurality of unit column structures comprises a respective plurality of series-connected non-volatile memory cells connected in series with a respective plurality of series-connected field-effect transistors, wherein a channel of each non-volatile memory cell of the plurality of series-connected non-volatile memory cells and a channel of each fieldeffect transistor of the plurality of series-connected field-effect transistors are selectively connected to one another;
  • a thirty-fifth example includes the array of memory cells of the thirty -fourth example, wherein the conductive element of the first control gate of the respective pass gate for a particular unit column structure of the plurality of unit column structures is formed below a material forming the channel of the particular field-effect transistor of the respective plurality of field-effect transistors of the particular unit column structure.
  • a thirty-sixth example includes the array of memory cells of the thirty-fifth example, wherein the conductive element of the first control gate of the respective pass gate for a particular unit column structure of the plurality of unit column structures is further formed adjacent sidewalls of the material forming the channel of the particular field-effect transistor of the respective plurality of field-effect transistors of the particular unit column structure.
  • a thirty -seventh example includes the array of memory cells of the thirty -fourth example, wherein the conductive element of the first control gate of the respective pass gate for a particular unit column structure of the plurality of unit column structures comprises a conductively-doped polysilicon.
  • a thirty-eighth example includes an array of memory cells, comprising a data line; a source; a plurality of pass gates connected in series between the data line and the source, wherein each pass gate of the plurality of pass gates comprises a first channel, a second channel, a first control gate capacitively coupled to its first channel, a second control gate capacitively coupled to its second channel, a first source/drain region connected to its first channel and to its second channel, and a second source/drain region connected to its first channel and to its second channel; a plurality of unit column structures, wherein each unit column structure of the plurality of unit column structures comprises a respective plurality of series-connected non-volatile memory cells connected in series with a respective plurality of series-connected field-effect transistors, wherein a channel of each non-volatile memory cell of the plurality of series-connected non-volatile memory cells and a channel of each fieldeffect transistor of the plurality of series-connected field-effect transistors are selectively connected to one another;
  • a thirty -ninth example includes the array of memory cells of the thirty-eighth example, wherein, for each unit column structure of the plurality of unit column structures, the conductive element of the first control gate of the respective pass gate for that unit column structure is formed below the material forming the channel of the particular fieldeffect transistor of the respective plurality of field-effect transistors of that unit column structure.
  • a fortieth example includes the array of memory cells of the thirty -ninth example, wherein, for each unit column structure of the plurality of unit column structures, the conductive element of the first control gate of the respective pass gate for that unit column structure is further formed adjacent sidewalls of the material forming the channel of the particular field-effect transistor of the respective plurality of field-effect transistors of that unit column structure.
  • a forty-first example includes the array of memory cells of the thirty-eighth example, wherein, for each unit column structure of the plurality of unit column structures, the conductive element of the first control gate of the respective pass gate for that unit column structure comprises a first conductively-doped polysilicon, and a second conductively-doped polysilicon formed between the first conductively-doped polysilicon and the material forming the channel of the particular field-effect transistor of the respective plurality of field-effect transistors of that unit column structure.
  • a forty-second example includes an array of memory cells, comprising a plurality of first data lines; a second data line; a source; a plurality of unit column structures, wherein each unit column structure of the plurality of unit column structures comprises a respective plurality of series-connected non-volatile memory cells; a plurality of sense lines, wherein each sense line of the plurality of sense lines comprises a respective plurality of pass gates connected in series between the second data line and the source, wherein each pass gate of its respective plurality of pass gates comprises a first channel, a second channel, a first control gate capacitively coupled to its first channel, and a second control gate capacitively coupled to its second channel, and wherein each unit column structure of a respective subset of unit column structures of the plurality of unit column structures for that sense line of the plurality of sense lines is capacitively coupled to the first channel of a respective pass gate of its respective plurality of pass gates; and a plurality of backside gate lines, wherein each backside gate line is connected to the second
  • a forty -third example includes the array of memory cells of the forty-second example, wherein the respective subset of first data lines of the plurality of first data lines for a first sense line of the plurality of sense lines is mutually exclusive from the respective subset of first data lines of the plurality of first data lines for a second sense line.
  • a forty-fourth example includes the array of memory cells of the forty -third example, wherein the respective subset of first data lines of the plurality of first data lines for a third sense line of the plurality of sense lines is not mutually exclusive from the respective subset of first data lines of the plurality of first data lines for the first sense line.
  • a forty-fifth example includes the array of memory cells of the forty-fourth example, wherein the first sense line is immediately adjacent the second sense line, and wherein the second sense line is between the third sense line and the first sense line.
  • a forty-sixth example includes the array of memory cells of the forty-fourth example, wherein at least one first data line of the respective subset of first data lines of the plurality of first data lines for the third sense line of the plurality of sense lines is mutually exclusive from the respective subset of first data lines of the plurality of first data lines for the first sense line.
  • a forty-seventh example includes the array of memory cells of the forty-second example, wherein the respective subset of first data lines of the plurality of first data lines for each sense line of the plurality of sense lines is mutually exclusive from the respective subset of first data lines of the plurality of first data lines for each remaining sense line of the plurality of sense lines.
  • a forty-eighth example includes the array of memory cells of the forty-seventh example, wherein each backside gate line of the plurality of backside gate lines is orthogonal to each sense line of the plurality of sense lines.
  • a forty -ninth example includes an array of memory cells, comprising a plurality of first data lines; a second data line; a source; a plurality of unit column structures, wherein each unit column structure of the plurality of unit column structures comprises a respective plurality of series-connected non-volatile memory cells; a plurality of sense lines, wherein each sense line of the plurality of sense lines comprises a respective plurality of pass gates connected in series between the second data line and the source, wherein each pass gate of its respective plurality of pass gates comprises a first channel, a second channel, a first control gate capacitively coupled to its first channel, and a second control gate capacitively coupled to its second channel, and wherein each unit column structure of a respective subset of unit column structures of the plurality of unit column structures for that sense line of the plurality of sense lines is capacitively coupled to the first channel of a respective pass gate of its respective plurality of pass gates; and a plurality of backside gate lines, wherein each backside gate line is connected
  • a fiftieth example includes the array of memory cells of the forty -ninth example, wherein each backside gate line of the plurality of backside gate lines is non-orthogonal to each sense line of the plurality of sense lines.
  • a fifty-first example includes the array of memory cells of the fiftieth example, wherein the respective subset of first data lines of the plurality of first data lines for a first sense line of the plurality of sense lines is mutually exclusive from the respective subset of first data lines of the plurality of first data lines for a second sense line.
  • a fifty-second example includes the array of memory cells of the fifty-first example, wherein, for each sense line of the plurality of sense lines, the respective subset of first data lines of the plurality of first data lines for that sense line of the plurality of sense lines is mutually exclusive from the respective subset of first data lines of the plurality of first data lines for each remaining sense line of the plurality of sense lines.
  • a fifty-third example includes the array of memory cells of the fiftieth example, wherein the respective subset of first data lines of the plurality of first data lines for a third sense line of the plurality of sense lines is not mutually exclusive from the respective subset of first data lines of the plurality of first data lines for the first sense line, wherein the first sense line is immediately adjacent the second sense line, wherein the second sense line is immediately adjacent the third sense line, and wherein the second sense line is between the third sense line and the first sense line.
  • a fifty-fourth example includes the array of memory cells of the forty -ninth example, wherein each sense line of the plurality of sense lines is angled in relation to each backside gate line of the plurality of backside gate lines.
  • a fifty-fifth example includes an array of memory cells, comprising a plurality of first data lines; a second data line; a source; a plurality of unit column structures, wherein each unit column structure of the plurality of unit column structures comprises a respective plurality of series-connected non-volatile memory cells; a plurality of dummy unit column structures; a plurality of sense lines, wherein each sense line of the plurality of sense lines comprises a respective plurality of pass gates connected in series between the second data line and the source, wherein each pass gate of its respective plurality of pass gates comprises a first channel, a second channel, a first control gate capacitively coupled to its first channel, and a second control gate capacitively coupled to its second channel, wherein each unit column structure of a respective subset of unit column structures of the plurality of unit column structure for that sense line of the plurality of sense lines is capacitively coupled to the first channel of a respective pass gate of its respective plurality of pass gates, and wherein a respective dummy unit
  • a fifty-sixth example includes the array of memory cells of the fifty -fifth example, wherein, for each sense line of the plurality of sense lines, its respective dummy unit column is not connected to any first data line of the plurality of first data lines.
  • a fifty-seventh example includes the array of memory cells of the fifty-fifth example, wherein each sense line of the plurality of sense lines is arranged in a folded orientation.
  • a fifty-eighth example includes the array of memory cells of the fifty -fifth example, wherein, for a particular sense line of the plurality of sense lines, a particular first data line of its respective subset of first data lines is connected to a first unit column structure of its respective subset of unit column structures that is immediately adjacent its respective dummy unit column structure in a first direction, and is connected to a second unit column structure of its respective subset of unit column structures that is immediately adjacent its respective dummy unit column structure in a second direction.
  • a fifty-ninth example includes the array of memory cells of the fifty-eighth example, wherein, for the particular sense line of the plurality of sense lines, a different first data line of its respective subset of first data lines is connected to a third unit column structure of its respective subset of unit column structures that is immediately adjacent its first unit column structure in the first direction, and is connected to a fourth unit column structure of its respective subset of unit column structures that is immediately adjacent its second unit column structure in the second direction.
  • a sixtieth example includes the array of memory cells of the fifty -ninth example, wherein, for the particular sense line of the plurality of sense lines, a different first data line of its respective subset of first data lines is connected to a third unit column structure of its respective subset of unit column structures that is immediately adjacent its first unit column structure in the first direction, and is connected to a fourth unit column structure of its respective subset of unit column structures that is immediately adjacent its second unit column structure in the second direction.
  • a sixty-first example includes the array of memory cells of the fifty-fifth example, wherein, for a particular sense line of the plurality of sense lines, each first data line of its respective subset of first data lines is connected to two unit column structures of its respective subset of unit column structures.
  • a sixty-second example includes the array of memory cells of the sixty -first example, wherein, for the particular sense line of the plurality of sense lines, each first data line of its respective subset of first data lines is connected to two unit column structures of its respective subset of unit column structures that are on opposing sides of its respective dummy unit column structure.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Non-Volatile Memory (AREA)
  • Read Only Memory (AREA)
  • Semiconductor Memories (AREA)

Abstract

Un réseau de cellules de mémoire peut comprendre une première ligne de données, une seconde ligne de données, une source, une capacité connectée sélectivement à la première ligne de données, une chaîne de cellules de mémoire non volatile connectées en série entre la première ligne de données et la capacité, et une grille de passage connectée sélectivement entre la seconde ligne de données et la source, une électrode de la capacité étant couplée de manière capacitive à un canal de la grille de passage.
PCT/US2021/058717 2020-12-04 2021-11-10 Mémoire non-et de détection capacitive WO2022119690A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202180081026.1A CN116636324A (zh) 2020-12-04 2021-11-10 电容式感测nand存储器

Applications Claiming Priority (8)

Application Number Priority Date Filing Date Title
US17/111,751 US11670379B2 (en) 2020-12-04 2020-12-04 Sense line structures in capacitive sense NAND memory
US17/111,751 2020-12-04
US17/111,746 2020-12-04
US17/111,746 US11227869B1 (en) 2020-12-04 2020-12-04 Memory array structures for capacitive sense NAND memory
US17/111,770 2020-12-04
US17/111,729 2020-12-04
US17/111,770 US11386966B2 (en) 2020-12-04 2020-12-04 Access operations in capacitive sense NAND memory
US17/111,729 US11437106B2 (en) 2020-12-04 2020-12-04 Capacitive sense NAND memory

Publications (1)

Publication Number Publication Date
WO2022119690A1 true WO2022119690A1 (fr) 2022-06-09

Family

ID=81853516

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2021/058717 WO2022119690A1 (fr) 2020-12-04 2021-11-10 Mémoire non-et de détection capacitive

Country Status (2)

Country Link
TW (1) TW202236640A (fr)
WO (1) WO2022119690A1 (fr)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110310670A1 (en) * 2010-02-05 2011-12-22 Samsung Electronics Co., Ltd. Vertically-integrated nonvolatile memory devices having laterally-integrated ground select transistors
US20160005753A1 (en) * 2014-07-02 2016-01-07 Etienne Nowak Three Dimensional Semiconductor Memory Devices
US20160042791A1 (en) * 2014-08-11 2016-02-11 Micron Technology, Inc. Methods and apparatuses including a string of memory cells having a first select transistor coupled to a second select transistor
US20160093391A1 (en) * 2014-09-29 2016-03-31 SK Hynix Inc. Semiconductor device
US20200211649A1 (en) * 2018-12-31 2020-07-02 Samsung Electronics Co., Ltd. Nonvolatile memory device and method of processing in memory (pim) using the same

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110310670A1 (en) * 2010-02-05 2011-12-22 Samsung Electronics Co., Ltd. Vertically-integrated nonvolatile memory devices having laterally-integrated ground select transistors
US20160005753A1 (en) * 2014-07-02 2016-01-07 Etienne Nowak Three Dimensional Semiconductor Memory Devices
US20160042791A1 (en) * 2014-08-11 2016-02-11 Micron Technology, Inc. Methods and apparatuses including a string of memory cells having a first select transistor coupled to a second select transistor
US20160093391A1 (en) * 2014-09-29 2016-03-31 SK Hynix Inc. Semiconductor device
US20200211649A1 (en) * 2018-12-31 2020-07-02 Samsung Electronics Co., Ltd. Nonvolatile memory device and method of processing in memory (pim) using the same

Also Published As

Publication number Publication date
TW202236640A (zh) 2022-09-16

Similar Documents

Publication Publication Date Title
JP7117406B2 (ja) ３次元垂直ｎｏｒフラッシュ薄膜トランジスタストリング
US11749344B2 (en) Three-dimensional vertical nor flash thin-film transistor strings
WO2019152226A1 (fr) Chaînes de transistors en couches minces flash non-ou verticales tridimensionnelles
US11678482B2 (en) Memory array structures for capacitive sense NAND memory
US11657880B2 (en) Access operations in capacitive sense NAND memory
US12080356B2 (en) Methods of forming integrated circuit structures for capacitive sense NAND memory
EP4022617A1 (fr) Effacement de mémoire
US11935883B2 (en) Capacitor structures and apparatus containing such capacitor structures
US12112805B2 (en) Apparatus containing memory array structures having multiple sub-blocks
WO2022119690A1 (fr) Mémoire non-et de détection capacitive
US11670379B2 (en) Sense line structures in capacitive sense NAND memory

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21901250

Country of ref document: EP

Kind code of ref document: A1

WWE Wipo information: entry into national phase

Ref document number: 202180081026.1

Country of ref document: CN

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 21901250

Country of ref document: EP

Kind code of ref document: A1