WO2022111155A1 - 同时钟域下寄存器的逻辑解耦方法 - Google Patents

同时钟域下寄存器的逻辑解耦方法 Download PDF

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WO2022111155A1
WO2022111155A1 PCT/CN2021/125322 CN2021125322W WO2022111155A1 WO 2022111155 A1 WO2022111155 A1 WO 2022111155A1 CN 2021125322 W CN2021125322 W CN 2021125322W WO 2022111155 A1 WO2022111155 A1 WO 2022111155A1
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registers
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WO2022111155A9 (zh
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赵少峰
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东科半导体(安徽)股份有限公司
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/225—Clock input buffers

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  • the invention relates to the technical field of digital circuit design, in particular to a logic decoupling method for registers in a simultaneous clock domain.
  • the system data rate and clock rate are constantly increasing, and the operating frequency of the corresponding processor is also getting higher and higher; data, voice, image transmission
  • the speed has been much higher than 500Mbps, and the backplane of hundreds of megabytes or even several gigabytes is becoming more and more common.
  • the increase in the speed of digital systems means that the rise and fall times of signals are as short as possible, and a series of high-speed design problems arising from the increase in the frequency and edge rate of digital signals have become more and more prominent.
  • Buffers in digital circuits generally have two functions: one is to improve the driving capability, and the other is to ensure the correct timing of signals, such as when there is a hold violation on a trace (which means that the data arrives too fast and needs to be delayed to arrive) ), a buffer can be inserted and the delay of the buffer can be used to correct this hold violation. This approach is very effective to solve the clock synchronization requirements.
  • the purpose of the present invention is to provide a method for logical decoupling of registers in the simultaneous clock domain, by decoupling the registers in the simultaneous clock domain according to a logical relationship, dividing them into multiple clusters, and using a sub-root buffer (sub-root buffer) for each cluster.
  • the root buffer is connected to the clock tree, and the registers in each cluster are synchronized under the sub-clock domain, that is to say, by constructing the sub-clock domain, the delay deviation between the sub-clock domains that are logically decoupled is allowed to exist.
  • the amount of buffers (buffer) in the entire clock domain can be reduced, the power consumption can be reduced, the chip area can be saved, and the clock tree structure can be simplified.
  • an embodiment of the present invention provides a method for logical decoupling of registers in a simultaneous clock domain, including:
  • the registers with the same cluster identification mark are divided into one cluster, and the registers that are not in the same cluster are logically decoupled from each other;
  • the pre-layout is adjusted according to the cluster identification mark, and the physical positions of multiple registers in the same cluster are adjusted within a certain area according to the design rules, and a sub-clock domain is constructed;
  • Sub-root buffers Insert one or more sub-root buffers (sub-root buffers) into each sub-clock domain to independently access each sub-clock domain to the clock tree, and drive the sub-clock through the inserted one or more sub-root buffers registers in the domain.
  • the method further includes:
  • Clock synchronization is performed on a plurality of registers in each sub-clock domain under the sub-clock domain.
  • the method for clock synchronization specifically includes:
  • One or more buffers are inserted into multiple registers in each sub-clock domain according to clock synchronization requirements.
  • the adjusting the physical positions of the multiple registers of the same cluster within a certain area according to the design rule is specifically:
  • the physical positions of the multiple registers of the same cluster are adjusted within a certain area not larger than the area constraint area according to the design rule.
  • the preset coefficient is 0.5.
  • the physical location of the sub-root buffer is also set in a certain area corresponding to the connected sub-clock domain.
  • the method for logical decoupling of registers in the simultaneous clock domain provided by the embodiment of the present invention, by decoupling the registers in the simultaneous clock domain according to a logical relationship, dividing them into multiple clusters, and using a sub-root buffer for each cluster. ) is connected to the clock tree, and the registers in each cluster are synchronized under the sub-clock domain, that is to say, by constructing the sub-clock domain, the delay deviation between the sub-clock domains that are logically decoupled is allowed to exist.
  • the amount of buffers (buffer) in the entire clock domain can be reduced, the power consumption can be reduced, the chip area can be saved, and the clock tree structure can be simplified.
  • FIG. 1 is a flowchart of a method for logical decoupling of registers in a simultaneous clock domain according to an embodiment of the present invention.
  • the embodiment of the present invention provides a logic decoupling method for registers in a simultaneous clock domain, which is used in the design process of the back end of a digital circuit.
  • the main method steps are shown in Figure 1, including:
  • Step 110 acquiring all register information of the access clock tree under the simultaneous clock domain
  • each register group includes multiple registers, and the data between different register groups may or may not have a logical relationship.
  • each data signal is stored in a bistable register, when the clock signal of the register arrives, the data signal will leave the register and enter the next register.
  • the clock tree is used to generate a specific clock signal that is synchronized to each register. Synchronization events occur on all registers at the same time, and the timing of the synchronization clock signal to each register is defined based on a global time base.
  • Step 120 assigning a different cluster identification mark to each register
  • the generation rules of the cluster identification marks may be preset, and then the cluster identification marks are generated based on the rules. Or randomly generate cluster identification markers. In the initial state, the cluster identification flag assigned to each register is different.
  • Step 130 look up the connected register from the output of each register to the subsequent stage, when it is determined that there is a timing path (Timing path) between the second register of the subsequent stage and the first register of the previous stage, the second register of the subsequent stage is determined.
  • the cluster identification mark of the register is modified to the cluster identification mark of the first register;
  • Timing path refers to the logic path traversed in the process of data signal propagation in the design.
  • Each timing path has an origination point and a termination point corresponding to it.
  • Step 140 After traversing all the registers, the registers with the same cluster identification mark are divided into one cluster, and the registers that are not in the same cluster are logically decoupled from each other;
  • Step 150 adjusting the pre-layout according to the cluster identification mark, adjusting the physical positions of multiple registers of the same cluster within a certain area according to the design rules, and constructing a sub-clock domain;
  • the area constraint area of each cluster can be calculated according to the ratio of the sum of the areas of each single register in the multiple registers under the same cluster to the preset coefficient, and the certain area described in the step is determined according to the calculated area constraint area. area; and then adjust the physical placement positions of multiple registers of the same cluster within the certain area not larger than the area constraint area according to the design rules.
  • the preset coefficient is preferably 0.5.
  • Step 160 Insert one or more sub-root buffers (sub-root buffers) into each sub-clock domain, so as to connect each sub-clock domain to the clock tree independently, and drive the sub-clock domain through the inserted one or more sub-root buffers. of each register.
  • the sub-root buffer (sub-root buffer) is also the aforementioned buffer (buffer), which is used to drive each register in the sub-clock domain.
  • the sub-root buffer is referred to here only to emphasize that its role is to access each sub-clock domain independently into the clock tree.
  • the physical location of the sub-root buffer is also set in a certain area corresponding to the connected sub-clock domain.
  • Step 170 Perform clock synchronization on multiple registers in each sub-clock domain under the sub-clock domain.
  • the method for clock synchronization in the sub-clock domain specifically includes: inserting one or more buffers into multiple registers in each sub-clock domain according to clock synchronization requirements.
  • each register is connected to the clock tree through one or more buffers connected to its CP terminal, i.e. the clocks of the five registers are all synchronized.
  • the area of this area is less than or equal to twice the sum of the areas of registers S4 and S5, and is constructed as a second sub-clock domain. Insert sub-root buffers into these two sub-clock domains respectively to make them independently connected to the clock tree, and then synchronize the clocks of registers S1, S2, and S3 in the first sub-clock domain, and synchronize the registers in the second sub-clock domain. Registers S4 and S5 perform clock synchronization.
  • the method for logical decoupling of registers in the simultaneous clock domain provided by the embodiment of the present invention, by decoupling the registers in the simultaneous clock domain according to a logical relationship, dividing them into multiple clusters, and using a sub-root buffer for each cluster. ) is connected to the clock tree, and the registers in each cluster are synchronized under the sub-clock domain, that is to say, by constructing the sub-clock domain, the delay deviation between the sub-clock domains that are logically decoupled is allowed to exist.
  • the number of sub-root buffers that drive each sub-clock domain is much smaller than the number of buffers that need to drive and timing adjustments (eg, delay) for each register separately. Therefore, on the premise that the logic function can be satisfied, the amount of buffers in the entire clock domain can be reduced, the power consumption can be reduced, the chip area can be saved, and the clock tree structure can be simplified.
  • a software module can be placed in random access memory (RAM), internal memory, read only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other in the technical field. in any other known form of storage medium.
  • RAM random access memory
  • ROM read only memory
  • electrically programmable ROM electrically erasable programmable ROM
  • registers hard disk, removable disk, CD-ROM, or any other in the technical field. in any other known form of storage medium.

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Abstract

本发明实施例涉及一种同时钟域下寄存器的逻辑解耦方法，包括：获取同时钟域下的接入时钟树的全部寄存器信息；对每个寄存器赋予一个不同的簇识别标记；当确定后级的第二寄存器与前级的第一寄存器之间存在时序路径时，将后级的第二寄存器的簇识别标记修改为第一寄存器的簇识别标记；遍历全部寄存器后，将具有相同簇识别标记的寄存器分为一簇，不在同一簇的寄存器之间互为逻辑解耦；根据簇识别标记对预布局进行调整，将同一簇的多个寄存器的物理位置按照设计规则调整在一定区域内，构建成一个子时钟域；对每个子时钟域插入一个或多个子根缓冲器，以将每个子时钟域独立接入时钟树，并通过插入的一个或多个子根缓冲器驱动子时钟域内的各寄存器。

Description

同时钟域下寄存器的逻辑解耦方法
本申请要求于2020年11月26日提交中国专利局、申请号为202011348726.6，发明名称为“同时钟域下寄存器的逻辑解耦方法”的中国专利申请的优先权。
技术领域
本发明涉及数字电路设计技术领域，尤其涉及同时钟域下寄存器的逻辑解耦方法。
背景技术
在网络通讯领域，ATM交换机、核心路由器、千兆以太网以及各种网关设备中，系统数据速率、时钟速率不断提高，相应处理器的工作频率也越来越高；数据、语音、图像的传输速度已经远远高于500Mbps，数百兆乃至数吉的背板也越来越普遍。数字系统速度的提高意味着信号的升降时间尽可能短，由数字信号频率和边沿速率提高而产生的一系列高速设计问题也变得越来越突出。当信号的互连延迟大于边沿信号翻转时间的20％时，板上的信号导线就会呈现出传输线效应，这样的设计就成为高速设计。高速问题的出现给硬件设计带来了更大的挑战，有许多从逻辑角度看来正确的设计，如果在实际PCB设计中处理不当就会导致整个设计失败，这种情形在日益追求高速的网络通信领域更加明显。因高速问题产生的信号过冲、下冲、反射、振铃、串扰等将严重影响系统的正常时序，系统时序余量的减少迫使人们关注影响数字波形时序和质量的各种现象。由于速度的提高使时序变得苛刻时，无论事先对系统原理理解得多么透彻，任何忽略和简化都可能给系统带来严重的后果。在高速设计中，时序问题的影响更为关 键。
目前，业内普遍采用在芯片设计过程中在时序路径上每个寄存器的CP端插入缓冲器(buffer)来保证在同一时钟域下全部寄存器的时钟同步。数字电路中的缓冲器一般有两个作用：一是提高驱动能力，二是确保信号时序正确，比如当一条走线上有保持时间违规(hold violation)(表现为数据到达过快，需要滞后到达)，则可插入缓冲器，利用缓冲器的延时来修正这个保持时间违规(hold violation)。这一做法非常有效的解决了时钟同步的要求。
但是随着芯片规模越来越大，在一个时钟域内往往需要插入大量的缓冲器以满足时钟同步的需求，这样导致了大量缓冲器对芯片面积的占用，使得设计结构复杂，也带来了芯片功耗大等问题。
发明内容
本发明的目的是提供一种同时钟域下寄存器的逻辑解耦方法，通过将同时钟域下的寄存器按照逻辑关系进行解耦，划分为多簇，对于每簇使用子根缓冲器(sub-root buffer)接入时钟树，并使每簇中的寄存器在子时钟域下进行同步，也就是说通过构建子时钟域，允许逻辑解耦的各子时钟域之间存在时延偏差。这样在能够满足逻辑功能的前提下，既可以减少整个时钟域内的缓冲器(buffer)用量，降低功耗，又可节省芯片面积，使时钟树结构简化。
为此，第一方面，本发明实施例提供了一种同时钟域下寄存器的逻辑解耦方法，包括：
获取同时钟域下的接入时钟树的全部寄存器信息；
对每个寄存器赋予一个不同的簇识别标记；
从每个寄存器的输出向后级查找所连接的寄存器，当确定后级的第二寄存器与前级的第一寄存器之间存在时序路径(Timing path)时，将后级的第 二寄存器的簇识别标记修改为第一寄存器的簇识别标记；
遍历全部寄存器后，将具有相同簇识别标记的寄存器分为一簇，不在同一簇的寄存器之间互为逻辑解耦；
根据簇识别标记对预布局进行调整，将同一簇的多个寄存器的物理位置按照设计规则调整在一定区域内，构建成一个子时钟域；
对每个子时钟域插入一个或多个子根缓冲器(sub-root buffer)，以将每个子时钟域独立接入所述时钟树，并通过插入的一个或多个子根缓冲器驱动所述子时钟域内的各寄存器。
优选的，所述方法还包括：
在所述在子时钟域下对每个子时钟域内的多个寄存器进行时钟同步。
进一步优选的，所述时钟同步的方法具体包括：
对每个子时钟域内的多个寄存器根据时钟同步要求插入一个或多个缓冲器。
优选的，所述将同一簇的多个寄存器的物理位置按照设计规则调整在一定区域内具体为：
按照同一簇下的多个寄存器中各个单个寄存器的面积之和与预设系数之比计算每一簇的区域约束面积，并根据计算得到的区域约束面积确定所述一定区域；
将同一簇的多个寄存器的物理位置按照设计规则调整在不大于所述区域约束面积的一定区域内。
进一步优选的，所述预设系数为0.5。
优选的，所述子根缓冲器的物理位置也设置在所连接的子时钟域对应的一定区域内。
本发明实施例提供的同时钟域下寄存器的逻辑解耦方法，通过将同时钟域下的寄存器按照逻辑关系进行解耦，划分为多簇，对于每簇使用子根缓冲器(sub-root buffer)接入时钟树，并使每簇中的寄存器在子时钟域下 进行同步，也就是说通过构建子时钟域，允许逻辑解耦的各子时钟域之间存在时延偏差。这样在能够满足逻辑功能的前提下，既可以减少整个时钟域内的缓冲器(buffer)用量，降低功耗，又可节省芯片面积，使时钟树结构简化。
附图说明
下面通过附图和实施例，对本发明实施例的技术方案做进一步详细描述。
图1为本发明实施例提供的同时钟域下寄存器的逻辑解耦方法流程图。
具体实施方式
下面通过附图和实施例，对本发明的技术方案做进一步的详细描述。
本发明实施例提供了一种同时钟域下寄存器的逻辑解耦方法，用于数字电路后端设计过程中。其主要方法步骤如图1所示，包括：
步骤110，获取同时钟域下的接入时钟树的全部寄存器信息；
具体的，大部分的同步数字系统由级联的时序寄存器组及它们之间的组合电路组成，每个寄存器组包括多个寄存器，不同寄存器组之间的数据可能存在逻辑关系或不存在逻辑关系，每个数据信号都所存在一个双稳态下的寄存器中，当寄存器的时能时钟信号一到达，数据信号就离开寄存器，进入到下一个寄存器。理论上讲，在系统中，时钟树用以产生同步于每一个寄存器的特定时钟信号。同步事件在同一时刻发生在所有寄存器上，同步时钟信号到每一个寄存器的时间都基于一个全局时间基准来定义。
步骤120，对每个寄存器赋予一个不同的簇识别标记；
具体的，可以预先设定簇识别标记的生成规则，然后基于规则来生成簇识别标记。或者随机生成簇识别标记。在初始状态下，对每个寄存器赋予的簇识别标记都是不同的。
步骤130，从每个寄存器的输出向后级查找所连接的寄存器，当确定后级的第二寄存器与前级的第一寄存器之间存在时序路径(Timing path)时，将后级的第二寄存器的簇识别标记修改为第一寄存器的簇识别标记；
具体的，对每个寄存器按照输出向后级查找的过程，即是时序路径的追溯过程。时序路径是指设计中数据信号传播过程中所经过的逻辑路径。每一条时序路径都存在与之对应的一个始发点和一个终止点。通过本步骤的实施，最终可以实现同一个时序路径上的全部寄存器被赋成同样的簇识别标记，即作为其始发点的寄存器的簇识别标记。而对于不存在逻辑关系的两条时序路径，最终获得的簇识别标记是不同的。
步骤140，遍历全部寄存器后，将具有相同簇识别标记的寄存器分为一簇，不在同一簇的寄存器之间互为逻辑解耦；
步骤150，根据簇识别标记对预布局进行调整，将同一簇的多个寄存器的物理位置按照设计规则调整在一定区域内，构建成一个子时钟域；
具体的，可按照同一簇下的多个寄存器中各个单个寄存器的面积之和与预设系数之比计算每一簇的区域约束面积，并根据计算得到的区域约束面积确定步骤中所述的一定区域；然后将同一簇的多个寄存器的物理摆放位置按照设计规则调整在不大于区域约束面积的该一定区域内。
在本发明的具体实现中，预设系数优选为0.5。
步骤160，对每个子时钟域插入一个或多个子根缓冲器(sub-root buffer)，以将每个子时钟域独立接入时钟树，并通过插入的一个或多个子根缓冲器驱动子时钟域内的各寄存器。
具体的，子根缓冲器(sub-root buffer)也是前面所述的缓冲器(buffer)，用于驱动子时钟域内的各寄存器。在这里称为子根缓冲器仅为强调其作用是将每个子时钟域独立接入时钟树。优选的，子根缓冲器的物理位置也设置在所连接的子时钟域对应的一定区域内。
通过构建子时钟域，允许逻辑解耦的各子时钟域之间存在时延偏差，即 对各子根缓冲器(sub-root buffer)带来的时延偏差不需要进行纠正。
步骤170，在子时钟域下对每个子时钟域内的多个寄存器进行时钟同步。
子时钟域下时钟同步的方法具体包括：对每个子时钟域内的多个寄存器根据时钟同步要求插入一个或多个缓冲器。
为了更好的理解，以一个具体例子进行说明。
在一个同时钟域下，具有五个寄存器，分别为S1、S2、S3、S4和S5。其中S1、S2、S3相互级联，S4和S5级联。每个寄存器都通过其CP端连接的一个或多个缓冲器连接到时钟树，即五个寄存器的时钟都同步。
通过采用本发明的逻辑解耦方法，首先对S1、S2、S3、S4和S5分别赋予一个不同的簇识别标记，然后根据时序路径的关系，将S2、S3的簇识别标记修改为与S1的相同，将S5的簇识别标记修改为与S4的相同。即将S1、S2、S3分为一簇，S4和S5分为一簇。将S1、S2、S3的物理位置按照设计规则调整在一定区域内，这个区域面积小于等于寄存器S1、S2、S3的面积和的两倍，构建成第一个子时钟域；将S4、S5的物理位置按照设计规则调整在一定区域内，这个区域面积小于等于寄存器S4、S5的面积和的两倍，构建成第二个子时钟域。对这两个子时钟域分别插入子根缓冲器以使其独立接入时钟树，然后再在第一子时钟域下对寄存器S1、S2、S3进行时钟同步，以及在第二子时钟域下对寄存器S4、S5进行时钟同步。
本发明实施例提供的同时钟域下寄存器的逻辑解耦方法，通过将同时钟域下的寄存器按照逻辑关系进行解耦，划分为多簇，对于每簇使用子根缓冲器(sub-root buffer)接入时钟树，并使每簇中的寄存器在子时钟域下进行同步，也就是说通过构建子时钟域，允许逻辑解耦的各子时钟域之间存在时延偏差。为各子时钟域提供驱动的子根缓冲器的数量远远小于要对每个寄存器分别进行驱动和时序调整(如时延)的缓冲器的数量。因此这样在能够满足逻辑功能的前提下，既可以减少整个时钟域内的缓冲器 (buffer)用量，降低功耗，又可节省芯片面积，使时钟树结构简化。
专业人员应该还可以进一步意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，能够以电子硬件、计算机软件或者二者的结合来实现，为了清楚地说明硬件和软件的可互换性，在上述说明中已经按照功能一般性地描述了各示例的组成及步骤。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本发明的范围。
结合本文中所公开的实施例描述的方法或算法的步骤可以用硬件、处理器执行的软件模块，或者二者的结合来实施。软件模块可以置于随机存储器(RAM)、内存、只读存储器(ROM)、电可编程ROM、电可擦除可编程ROM、寄存器、硬盘、可移动磁盘、CD-ROM、或技术领域内所公知的任意其它形式的存储介质中。
以上所述的具体实施方式，对本发明的目的、技术方案和有益效果进行了进一步详细说明，所应理解的是，以上所述仅为本发明的具体实施方式而已，并不用于限定本发明的保护范围，凡在本发明的精神和原则之内，所做的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (6)

  1. 一种同时钟域下寄存器的逻辑解耦方法，其特征在于，所述逻辑解耦方法包括：
    获取同时钟域下的接入时钟树的全部寄存器信息；
    对每个寄存器赋予一个不同的簇识别标记；
    从每个寄存器的输出向后级查找所连接的寄存器，当确定后级的第二寄存器与前级的第一寄存器之间存在时序路径(Timing path)时，将后级的第二寄存器的簇识别标记修改为第一寄存器的簇识别标记；
    遍历全部寄存器后，将具有相同簇识别标记的寄存器分为一簇，不在同一簇的寄存器之间互为逻辑解耦；
    根据簇识别标记对预布局进行调整，将同一簇的多个寄存器的物理位置按照设计规则调整在一定区域内，构建成一个子时钟域；
    对每个子时钟域插入一个或多个子根缓冲器(sub-root buffer)，以将每个子时钟域独立接入所述时钟树，并通过插入的一个或多个子根缓冲器驱动所述子时钟域内的各寄存器。
  2. 根据权利要求1所述的逻辑解耦方法，其特征在于，所述方法还包括：
    在所述在子时钟域下对每个子时钟域内的多个寄存器进行时钟同步。
  3. 根据权利要求2所述的逻辑解耦方法，其特征在于，所述时钟同步的方法具体包括：
    对每个子时钟域内的多个寄存器根据时钟同步要求插入一个或多个缓冲器。
  4. 根据权利要求1所述的逻辑解耦方法，其特征在于，所述将同一簇的多个寄存器的物理位置按照设计规则调整在一定区域内具体为：
    按照同一簇下的多个寄存器中各个单个寄存器的面积之和与预设系数之比计算每一簇的区域约束面积，并根据计算得到的区域约束面积确定所 述一定区域；
    将同一簇的多个寄存器的物理位置按照设计规则调整在不大于所述区域约束面积的一定区域内。
  5. 根据权利要求4所述的逻辑解耦方法，其特征在于，所述预设系数为0.5。
  6. 根据权利要求1所述的逻辑解耦方法，其特征在于，所述子根缓冲器的物理位置也设置在所连接的子时钟域对应的一定区域内。
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