WO2022110387A1 - 路由装置及片上网络的路由设备 - Google Patents

路由装置及片上网络的路由设备 Download PDF

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Publication number
WO2022110387A1
WO2022110387A1 PCT/CN2020/137465 CN2020137465W WO2022110387A1 WO 2022110387 A1 WO2022110387 A1 WO 2022110387A1 CN 2020137465 W CN2020137465 W CN 2020137465W WO 2022110387 A1 WO2022110387 A1 WO 2022110387A1
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Prior art keywords
packet
routing
module
data
routing packet
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PCT/CN2020/137465
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English (en)
French (fr)
Inventor
马骋
裴京
宋晨航
鲁明胜
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清华大学
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Publication of WO2022110387A1 publication Critical patent/WO2022110387A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L45/00—Routing or path finding of packets in data switching networks
    • H04L45/12—Shortest path evaluation
    • H04L45/121—Shortest path evaluation by minimising delays
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L45/00—Routing or path finding of packets in data switching networks
    • H04L45/14—Routing performance; Theoretical aspects
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present disclosure relates to the technical field of system-on-chip, and in particular, to a routing device and a routing device of a network-on-chip.
  • NoC Network on Chip
  • the network-on-chip can have various topologies.
  • the two-dimensional network (2-Dimension mesh, 2D Mesh) is a more commonly used structure, as shown in Figure 1, mainly has the advantages of simple structure, good scalability, easy implementation and analysis.
  • the routing device in the network-on-chip processes the multiple routing packets according to the receiving order of the multiple routing packets.
  • some routing packets may have strict requirements on delay, and some routing packets have lower requirements on delay.
  • a routing device which includes:
  • the unpacking module is configured to acquire transmission request information of the received second routing packet during the process of transmitting the first routing packet through the first output channel, where the transmission request information includes the output channel and priority of the second routing packet class;
  • an arbitration module electrically connected to the unpacking module, and configured to determine, according to the transmission request information, that the output channel requested by the second routing packet is the first output channel and the priority of the second routing packet When the priority is greater than the priority of the first routing packet, interrupt the transmission of the first routing packet, and output a first switch control signal;
  • a transmission module electrically connected to the arbitration module, for connecting the input channel of the second routing packet and the first output channel according to the first switch control signal, so as to transmit the first output channel through the first output channel Two routing packets.
  • the device further includes:
  • a storage module electrically connected to the unpacking module and the arbitration module, and used for storing header information of the first routing packet and header information of the second routing packet, the header information including a priority and routing information.
  • the device further includes:
  • a counting module electrically connected to the unpacking module and the transmission module
  • the unpacking module is further configured to write the first data packet sequence number of the second routing packet into the counting module as a count value, and the first data packet sequence number is the total number of data packets of the second routing packet. number;
  • the counting module is configured to decrement the count value of the counting module by one each time the transmission module completes data forwarding of the second routing packet through the first output channel.
  • the arbitration module is further configured to output a first packing instruction when the transmission of the first routing packet is interrupted, and the apparatus further includes:
  • the packing module is electrically connected to the arbitration module and the counting module, and is used for obtaining the count value corresponding to the first routing packet in the counting module as the second data when receiving the first packing instruction packet sequence number, and generate a pseudo-tail packet of the first routing packet, wherein the second packet sequence number in the pseudo-tail packet is the first packet sequence number and the number of transmitted packets in the first routing packet.
  • the difference between the numbers, the sequence number of the first data packet is the total number of data packets of the second routing packet, and the pseudo-tail packet is used to indicate that the transmission of the first routing packet is interrupted;
  • the transmission module is further configured to send a pseudo-tail packet of the first routing packet through the first output channel to interrupt transmission of the first routing packet;
  • the storage module is electrically connected to the packaging module, and is further configured to store a pseudo-tail packet of the first routing packet.
  • the arbitration module is further configured to output a second packing instruction when the transmission of the first routing packet is interrupted, wherein,
  • the packaging module is further configured to, in the case of receiving the second packaging instruction, obtain the header packet information of the first routing packet in the storage module to generate a pseudo-header packet of the first routing packet , wherein the sequence number of the first data packet in the pseudo-header packet is the sequence number of the second data packet in the pseudo-tail packet of the first routing packet;
  • the storage module is further configured to store the pseudo-header packet of the first routing packet.
  • the arbitration module is further configured to, in the case of determining that the data transmission of the second routing packet ends, control the transmission module to disconnect the input channel of the second routing packet from the the connection of the first output channel;
  • the unpacking module is further configured to acquire, from the storage module, the transmission request information of the pseudo-header packet of the first routing packet;
  • the arbitration module is further configured to, according to the transmission request information of the pseudo-header packet of the first routing packet, control the transmission module to connect the input channel of the first routing packet and the first output channel, so as to continue to pass through the first routing packet.
  • the first output channel transmits data that has not been transmitted in the first routing packet.
  • the transmitting the data of the second routing packet through the first output channel includes:
  • the data packet and the tail packet of the second routing packet are transmitted through the first output channel
  • the data packet includes data of the second routing packet
  • the tail packet is used to indicate the end of the transmission of the second routing packet
  • the tail packet includes the routing packet type and a second data packet sequence number, and the second data packet sequence number is used to indicate the number of data packets that have not been transmitted in the second routing packet.
  • the device further includes:
  • a statistics module configured to determine whether there is packet loss in the second routing packet according to the magnitude of the difference between the number of the received data packets in the second routing packet and the sequence number
  • the sequence number difference is the difference between the first data packet sequence number and the second data packet sequence number, and the first data packet sequence number is the total number of data packets in the second routing packet.
  • the transmission module includes a switch unit, and the switch unit is configured to connect the input channel and the output channel according to the switch control signal, so as to transmit the routing packet;
  • the storage module includes a register unit and a cache unit, the register unit is used to store header packet information of the routing packet, and the cache unit is used to cache the routing packet on the input channel, the pseudo-tail packet and the pseudo-head packet of the routing packet;
  • the counting module includes a plurality of counters, and the plurality of counters are in one-to-one correspondence with the plurality of output channels.
  • the unpacking module is further configured to receive a header packet of the second routing packet, and obtain the header packet including the priority and routing information of the second routing packet,
  • the routing information includes at least one of routing packet type, destination address, first data packet sequence number, starting storage address, data packet address storage mode, and parity bit;
  • the routing packet type is used to indicate the type of the second routing packet
  • the destination address is the absolute address or relative address of the receiving end of the second routing packet
  • the first data packet sequence number is used to indicate The total number of data packets to be transmitted in the second routing packet
  • the starting storage address is the starting address of the data packets in the second routing packet stored in the memory of the receiving end
  • the data packet The address storage mode is used to indicate the storage mode of the data packet in the second routing packet in the memory of the receiving end
  • the check bit is used to indicate whether the data in the header packet is correct.
  • a routing device for a network-on-chip includes the routing device,
  • the routing device is a routing device in any node of the network-on-chip, and the node includes a processor core.
  • Embodiments of the present disclosure provide a routing device that, during the process of transmitting data of a first routing packet through a first output channel, receives transmission request information of a second routing packet; when the output channel requested by the second routing packet is the first routing packet The output channel and the priority of the second routing packet is greater than the priority of the first routing packet; the data of the second routing packet is transmitted through the first output channel; by constructing a routing protocol with a priority order, the higher priority is guaranteed. Routing packets can obtain lower routing delay. For example, when a group of routing packets is about to be blocked because the path is busy, if the priority of the routing packet is higher than the priority of the routing packet being transmitted on the output channel, the interrupt takes precedence. The routing packet with a lower priority is transmitted, and then the routing packet with a higher priority is transmitted, which ensures the rationality of routing control and routing transmission efficiency by the routing device of the network-on-chip.
  • FIG. 1 shows a structural diagram of a two-dimensional network in the related art.
  • FIG. 2 shows a block diagram of a routing apparatus according to an embodiment of the present disclosure.
  • FIG. 3 shows a schematic diagram of a routing device according to an embodiment of the present disclosure.
  • FIG. 4 shows a schematic diagram of a routing apparatus according to an embodiment of the present disclosure.
  • FIG. 5 , FIG. 6 , and FIG. 7 show schematic diagrams of routing packets transmitted by a routing device according to an embodiment of the present disclosure.
  • the routing device in the network-on-chip processes the multiple routing packets according to the receiving order of the multiple routing packets.
  • the current routing protocol does not differentiate the priority of routing packets, and all routing packets have the same priority.
  • some routing packets may have stricter requirements on delay, and some routing packets may have lower requirements on delay. Therefore, it is very necessary to establish an efficient routing protocol with priority order.
  • An embodiment of the present disclosure provides a routing device, which ensures that routing packets with higher priorities can obtain lower routing delays. If the priority of the routing packet being transmitted on the output channel is high, the transmission of the routing packet with the lower priority will be interrupted, and the routing packet with the high priority will be transmitted instead, which ensures the rationality of routing control by the routing device of the on-chip network. and routing efficiency.
  • FIG. 2 shows a block diagram of a routing apparatus according to an embodiment of the present disclosure.
  • the device includes:
  • the unpacking module 10 is configured to obtain transmission request information of the received second routing packet during the process of transmitting the first routing packet through the first output channel, where the transmission request information includes the output channel of the second routing packet and the priority;
  • the arbitration module 20 is electrically connected to the unpacking module 10, and is used for determining, according to the transmission request information, that the output channel requested by the second routing packet is the first output channel, and the second routing packet When the priority is greater than the priority of the first routing packet, interrupt the transmission of the first routing packet, and output a first switch control signal;
  • the transmission module 30 is electrically connected to the arbitration module 20, and is configured to connect the input channel of the second routing packet and the first output channel according to the first switch control signal, so as to transmit all data through the first output channel. Describe the second routing packet.
  • the transmission request information of the second routing packet is received; when the output channel requested by the second routing packet is the first output channel and The priority of the second routing packet is greater than that of the first routing packet; the data of the second routing packet is transmitted through the first output channel; by constructing a routing protocol with priority order, it is ensured that the routing packet with higher priority can be Obtain lower routing delay, such as when a group of routing packets is about to be blocked because the path is busy, if the priority of the routing packet is higher than the priority of the routing packet being transmitted on the output channel, the interrupt priority is lower The transmission of the routing packet, and then start to transmit the routing packet with the high priority, which ensures the rationality of routing control and routing transmission efficiency by the routing device of the network-on-chip.
  • the unpacking module and the arbitration module in the embodiment of the present disclosure may be implemented by a dedicated hardware circuit, or may be implemented by a general-purpose hardware circuit combined with executable logic.
  • the unpacking module and the arbitration module may be implemented by a central The implementation of the processor CPU, the microprocessor MCU, the graphics processor GPU, the digital signal processor DSP, the programmable gate array FPGA, etc., is not limited in this embodiment of the present disclosure.
  • the routing apparatus may be a routing device in a network-on-chip, and the routing device is a routing device in any node of the network-on-chip, and the node includes a processor core.
  • the network-on-chip includes a plurality of nodes (as shown in FIG. 1 ), and each node includes a routing device.
  • the network-on-chip can have various topologies. The embodiments of the present disclosure are only described by taking the topology structure of the network-on-chip as 2D Mesh as an example.
  • a routing device also known as a router, is a hardware device that connects two or more networks, acts as a gateway between the networks, and is a dedicated intelligent network device that reads the address in each data packet and transmits it.
  • FIG. 3 shows a schematic diagram of a routing device according to an embodiment of the present disclosure.
  • a routing device may include multiple input channels (eg, input channel W, input channel N, input channel E, input channel S, local input channel, ), multiple output channels (eg, output channel channel W, output channel N, output channel E, output channel S, local output channel), the routing device can establish the connection between the input channel and the output channel to transmit the routing packet.
  • multiple input channels eg, input channel W, input channel N, input channel E, input channel S, local input channel
  • multiple output channels eg, output channel channel W, output channel N, output channel E, output channel S, local output channel
  • the format of the routing packet is exemplarily introduced below.
  • packet header information including routing address information and data are generally packaged and sent, and the packet header information is included in each transmitted data packet, resulting in low routing transmission efficiency.
  • each data packet in the current routing transmission consists of a packet header and data.
  • the one-time routing process includes the transmission of header packets, data packets and tail packets, that is, a header packet is sent first, and the header packet includes routing address information; then a data packet is sent, and the data packet no longer includes routing address information. , that is, reducing the routing address information in the data packet; finally, a tail packet is transmitted, and the tail packet is used to indicate that all data packets in the routing process have been sent, and the data transmission of this routing is completed.
  • the header packet of each group of routing packets also needs to indicate the priority of the routing packet, so that routing packets of different priorities can be processed separately.
  • a complete routing process is a process of transmitting a group of routing packets, where the group of routing packets includes a header packet, a data packet and a tail packet, wherein the data packet is one or more data packets.
  • the header packet information of the header packet includes the priority of the routing packet, the type of the routing packet, the destination address, the sequence number of the first data packet, the starting storage address, the storage method of the data packet address, and the check digit at least one of the information.
  • the information contained in the header packet is shown in Table 1.
  • P is the priority of the routing packet.
  • the priority of the routing packet is used to indicate the transmission order of the routing packet.
  • the priority is positively correlated with the transmission order, that is, the higher the priority, the higher the transmission order.
  • T is the routing packet type, for example, the routing packet type includes one of a data configuration packet, a common data packet, and a query packet. This embodiment of the present disclosure does not limit the way of dividing the routing packet types.
  • Dst is the destination address, that is, the absolute address or relative address of the receiving end of the routing packet.
  • the destination address is a multi-dimensional structure.
  • Rank is the sequence number of the first data packet, and is used to indicate the total number of data packets to be transmitted in the routing packet.
  • Addr is the starting storage address, that is, the starting address where the data packet in the routing packet is stored in the memory of the receiving end.
  • R is the storage mode of the data packet address, which is used to indicate the storage mode of the data packet in the routing packet in the memory of the receiver.
  • the data packet address storage method is used to indicate that each time a preset number of data packets are stored in the memory of the receiving end, the routing address is jumped to a preset amount and then continues to be stored.
  • the preset number is 5, that is, each time 5 data packets are received and stored, the routing address will continue to be stored after jumping a certain amount, and this information can retain flexibility for actual routing applications.
  • C is the check digit, which is used to indicate whether the data in the header packet is correct.
  • the check digit is a first value, it is used to indicate that the data in the header packet is correct, and when the check digit is a value other than the first value, it is used to indicate that the data in the header packet is incorrect.
  • the embodiment of the present disclosure does not limit the specific value of the first numerical value.
  • none of the multiple data packets in the routing packet includes routing address information.
  • Each data packet includes data and may also include check digits.
  • the information contained in the data packet is shown in Table 2.
  • Data is the data
  • C is the check digit, which is used to indicate whether the data in the data packet is correct.
  • the tail packet is used to indicate the end of the transmission of the routing packet.
  • the tail packet includes the routing packet type and the second data packet sequence number, and the second data packet sequence number is used to indicate the number of data packets that have not been transmitted in the routing packet, which is convenient for the receiving end to perform data integrity verification.
  • a check digit may also be included in the tail packet to indicate whether the data in the tail packet is correct.
  • the check digit when the check digit is the second value, it is used to indicate that the data in the data packet is correct, and when the check digit is a value other than the second value, it is used to indicate that the data in the data packet is incorrect.
  • the specific value of the second numerical value is not limited in the embodiment of the present disclosure.
  • the information contained in the tail packet is shown in Table 3.
  • T is the routing packet type, and the routing packet types of the head packet and the tail packet in a group of routing packets are the same.
  • Rank is the second data packet sequence number, and is used to indicate the number of data packets that have not been transmitted in the routing packet.
  • sequence number of the second data packet is zero.
  • C is the check digit, which is used to indicate whether the data in the tail packet is correct.
  • the check digit is a third value, it is used to indicate that the data in the tail packet is correct, and when the check digit is a value other than the third value, it is used to indicate that the data in the tail packet is incorrect.
  • the embodiment of the present disclosure does not limit the specific value of the third numerical value.
  • the routing packet transmitted by the routing device in the embodiment of the present disclosure includes a header packet, a data packet, and a tail packet.
  • the routing address information in the data packets is reduced, and the transmission efficiency is improved; meanwhile, the routing device of the embodiment of the present disclosure transmits routing packets based on the above methods, and can also support interruption and resumption of routing data transmission, further ensuring the routing transmission effect.
  • a routing process should be sent by the sender in turn to send the header packet, data packet, and tail packet, and then end the data transmission of the group of routing packets.
  • the receiving end judges by checking whether the number of received data packets is equal to the difference between the sequence number of the first data packet in the header packet and the sequence number of the second data packet in the end packet.
  • the sending end is the abbreviation of the routing device at the sending end
  • the receiving end is the abbreviation of the routing device at the receiving end.
  • FIG. 4 shows a schematic diagram of a routing apparatus according to an embodiment of the present disclosure.
  • the apparatus may further include:
  • the storage module 40 is electrically connected to the unpacking module 10 and the arbitration module 20, and is used for storing the header packet information of the first routing packet and the header packet information of the second routing packet, the header packet information Including priority and routing information.
  • the memory module 40 may be implemented by any type of volatile or non-volatile memory device or combination thereof, such as Static Random Access Memory (SRAM), electrically erasable programmable Read-Only Memory (Electrically Erasable Programmable Read-Only Memory, EEPROM), Erasable Programmable Read-Only Memory (EPROM), Programmable Read-Only Memory (PROM), Read-Only Memory (Read Only Memory, ROM), magnetic memory, flash memory, magnetic disk or optical disk.
  • SRAM Static Random Access Memory
  • EEPROM Electrically erasable programmable Read-Only Memory
  • EPROM Erasable Programmable Read-Only Memory
  • PROM Programmable Read-Only Memory
  • Read Only Memory ROM
  • magnetic memory flash memory
  • flash memory magnetic disk or optical disk.
  • memory 20 may also include a memory controller to provide processor 10 access to memory 20 .
  • the storage module 40 may include a register unit 410 and a cache unit 420 .
  • the register unit 410 may include multiple sets of registers, and the register unit 410 may be configured to store header packet information of the routing packet, and the header packet may include the priority and routing information of the routing packet.
  • the routing information may include at least one of a routing packet type, a destination address, a first data packet sequence number, a starting storage address, a data packet address storage mode, and a check bit.
  • the routing packet type is used to indicate the type of the second routing packet
  • the destination address is an absolute address or a relative address of a receiving end of the second routing packet
  • the sequence number of the first data packet is It is used to indicate the total number of data packets to be transmitted in the second routing packet
  • the starting storage address is the starting address stored in the memory of the receiving end for the data packets in the second routing packet.
  • the storage mode of the data packet address is used to indicate the storage mode of the data packet in the second routing packet in the memory of the receiving end
  • the check bit is used to indicate whether the data in the header packet is correct.
  • the unpacking module 10 can perform unpacking processing on the routing packet, and obtain the header packet information of the routing packet (for example, the second routing packet).
  • the unpacking module 10 can use routing algorithms such as XY dimension order routing. Unpack the routing packet.
  • the depacketizing module 10 may store the header packet information of the routing packet in the register unit 410 .
  • the buffering unit 420 can be used as a buffer for the routing packets received by the input channel, and the buffering unit 420 can be set to a first-in, first-out FIFO mode (of course, it can also be set to a last-in, first-out LIFO mode.
  • the disclosed embodiment is not limited) to buffer the routing packets on each input channel.
  • an input buffer FIFO is set for each input channel. It is assumed that the routing device has five input FIFOs in total.
  • the buffer size can be set as an integer multiple of the length of the routing packet.
  • each FIFO of the router can be set to 3 routing packet size to take into account the performance and cost of the router.
  • the unpacking module can query whether there is a routing packet in each input channel FIFO of the buffer unit by polling, and if there is a routing packet, extract the flag bit in the routing packet to determine whether the routing packet belongs to the header Packet, data packet or tail packet. If the routing packet belongs to the head packet or the tail packet, the unpacking module makes a copy of the routing packet and unpacks it. If it is a header packet, the unpacking module determines the output direction (output channel) of the routing packet according to the routing algorithm (such as XY-dimensional order routing, etc.), and then sends the output direction and priority information of the routing packet to the arbitration module. If it is a tail packet, the register value corresponding to the routing output channel is cleared, and the corresponding output channel is sent to the arbitration module at the same time, so as to close the routing process.
  • the routing algorithm such as XY-dimensional order routing, etc.
  • the arbitration module receives information from the unpacking module. If the arbitration module receives information about the routing output direction and routing priority, it means that a header packet of a routing packet applies for a certain output channel and its priority is corresponding value. At this time, the arbitration module firstly judges whether the requested output channel is occupied, and if not, it controls the transmission module to establish a connection between the input channel of the routing packet and the output channel of the application, so as to directly transmit the routing packet. Whenever the arbitration module sends information to the transmission module and determines to connect the corresponding input channel and output channel, the unpacking module will also get this information, and the unpacking module can write all the information of the routing header packet into the output channel in the corresponding register.
  • the apparatus may further include:
  • the counting module 50 is electrically connected to the unpacking module 10 and the transmission module 30 .
  • the unpacking module 10 can also be used to write the first data packet sequence number of the second routing packet into the counting module as a count value, and the first data packet sequence number is the data of the second routing packet.
  • the counting module may be configured to decrement the count value of the counting module by one each time the transmission module 30 completes data forwarding of the second routing packet through the first output channel.
  • the embodiment of the present disclosure can realize the transmission count of the routing packet.
  • the counting module 50 may include a plurality of counters (for example, 5), and each counter corresponds to the output channel one-to-one.
  • the unpacking module 30 may The total number of data packets to be transmitted by the routing packet is written into the corresponding counter, so that the counter counts the data packets that have not been transmitted by the current routing packet.
  • the packet is the total number of data packets to be transmitted by the routing packet; after that, the counter is decremented from the current count value by one each time a data packet of the routing packet is transmitted; if the current processing is the tail packet of the routing packet, all data of the routing packet are identified. After all packets are transmitted, the counter counts to 0.
  • the arbitration module 20 may be further configured to output a first packing instruction when the transmission of the first routing packet is interrupted.
  • the apparatus may further include:
  • the packing module 60 is electrically connected to the arbitration module 20 and the counting module 50 (and the storage module 40 ), and is used for obtaining the same relationship between the counting module 50 and the first packing instruction when the first packing instruction is received.
  • the count value corresponding to the routing packet is used as the sequence number of the second data packet, and a pseudo-tail packet of the first routing packet is generated, wherein the sequence number of the second data packet in the pseudo-tail packet is the sequence number of the first data packet and the sequence number of the first data packet.
  • the difference between the number of transmitted data packets in a routing packet, the first data packet sequence number is the total number of data packets in the second routing packet, and the pseudo-tail packet is used to indicate interruption to the the transmission of the first routing packet;
  • the transmission module 30 may be further configured to send a pseudo-tail packet of the first routing packet through the first output channel, so as to interrupt the transmission of the first routing packet;
  • the storage module 40 may also be configured to store the pseudo-tail packet of the first routing packet.
  • the transmission module 30 may include a switch unit 310, and the switch unit 310 may be configured to connect the input channel and the output channel according to the switch control signal, so as to transmit the routing packet.
  • the switch unit 310 may include a crossbar switch, a single-pole-multi-throw switch, a multi-pole-multi-throw switch, or the like.
  • the arbitration module 20 can control the transmission module 30 to cut off the connection between the input channel of the first routing packet and the first output channel, and the depacketizing module 10 can control to stop receiving the first routing packet.
  • the arbitration module 20 of each routing device can control the transmission module 30 to cut off the input channel of the first routing packet Connection to the first output channel.
  • the arbitration module 20 may be further configured to output a second packing instruction when the transmission of the first routing packet is interrupted.
  • the packing module 60 is further configured to, in the case of receiving the second packing instruction, obtain the header of the first routing packet in the storage module 40 (register unit) packet information to generate a pseudo-header packet of the first routing packet, wherein the first data packet sequence number in the pseudo-header packet is the second data packet sequence number in the pseudo-tail packet of the first routing packet;
  • the storage module 40 is further configured to store the pseudo-header packet of the first routing packet.
  • the packaging module 60 may replace the sequence number of the first data packet in the header packet information of the first routing packet obtained in the storage module 40 with the count value in the counting module 50, that is, the pseudo-tail of the first data packet The second packet sequence number of the packet, and the rest of the information remains unchanged.
  • the packing module of the embodiment of the present disclosure may be implemented by a dedicated hardware circuit, or may be implemented by a general-purpose hardware circuit combined with executable logic, for example, the unpacking module and the arbitration module may be implemented by the central processing unit (CPU),
  • CPU central processing unit
  • the implementation of the microprocessor MCU, the graphics processor GPU, the digital signal processor DSP, the programmable gate array FPGA, etc., is not limited in this embodiment of the present disclosure.
  • the pseudo-header packet of the first routing packet may be stored in the foremost row of the buffer FIFO corresponding to the first routing packet, so that when the transmission of the second routing packet is completed, the unpacking module 10 can obtain the pseudo-header packet of the first routing packet.
  • the header packet triggers continued transmission of the first routing packet.
  • Interrupting the transmission of the first routing packet includes dividing the routing process of the first routing packet into two routing processes, which are: the routing process of the first routing packet header packet + the pseudo-tail packet, the routing process of the first routing packet The routing process of the pseudo-header packet + the first routing packet header packet is described.
  • the arbitration module 20 may be further configured to, in the case of determining that the data transmission of the second routing packet ends, control the transmission module to disconnect the input of the second routing packet A channel is connected to the first output channel.
  • the transmitting the data of the second routing packet through the first output channel may include:
  • the data packet and the tail packet of the second routing packet are transmitted through the first output channel
  • the data packet includes data of the second routing packet
  • the tail packet is used to indicate the end of the transmission of the second routing packet
  • the tail packet includes the routing packet type and a second data packet sequence number, and the second data packet sequence number is used to indicate the number of data packets that have not been transmitted in the second routing packet.
  • the input channel of the second routing packet is connected to the first output channel, and the data packet and the tail packet of the second routing packet can be transmitted through the first output channel to the next hop routing node.
  • the apparatus may further include:
  • a statistics module 70 configured to determine whether there is packet loss in the second routing packet according to the magnitude relationship between the number of the received data packets in the second routing packet and the sequence number difference,
  • the sequence number difference is the difference between the first data packet sequence number and the second data packet sequence number, and the first data packet sequence number is the total number of data packets in the second routing packet.
  • the routing transmission process of the second routing packet may be ended.
  • the statistics module 70 may determine whether the second routing packet has packet loss according to the relationship between the number of data packets in the received second routing packet and the sequence number difference, The sequence number difference is the difference between the sequence number of the first data packet and the sequence number of the second data packet.
  • the sequence number difference provided to the routing device or the controller is the difference between the sequence number of the first data packet and the sequence number of the second data packet.
  • the statistics module in this embodiment of the present disclosure may be implemented by a dedicated hardware circuit, or may be implemented by a general-purpose hardware circuit combined with executable logic, for example, the unpacking module and the arbitration module may be implemented by a central processing unit (CPU,
  • CPU central processing unit
  • the depacketizing module 10 may be further configured to acquire, from the storage module, the transmission request information of the pseudo-header packet of the first routing packet;
  • the arbitration module 20 may be further configured to control the transmission module to connect the input channel of the first routing packet with the transmission request information of the pseudo-header packet of the first routing packet the first output channel, so as to continue to transmit the data that has not been transmitted in the first routing packet through the first output channel.
  • the routing apparatus continues to transmit the data that has not been transmitted in the first routing packet.
  • the routing device continues to transmit the untransmitted data packets and tail packets in the first routing packet according to the cached pseudo-header packet of the first routing packet.
  • the routing device is exemplarily introduced below with reference to specific examples.
  • FIG. 5 , FIG. 6 , and FIG. 7 show schematic diagrams of routing packets transmitted by a routing device according to an embodiment of the present disclosure.
  • the transmission path of the first routing packet K1 includes routing device A, routing device B, and routing device C.
  • routing device B if routing device B in the routing path There is a situation where the high-priority routing packet (the second routing packet K2 from the routing device D) will interrupt the low-priority routing packet, and the routing device B is transmitting the priority of "1" through the output channel E (the first output channel). ” of the first routing packet K1.
  • the routing device of the routing device B receives the second routing packet K2 input in the S direction, and the unpacking module extracts the flag bit in the second routing packet K2, and judges that the second routing packet K2 is a header packet (header packet, The data packet and the tail packet have different identification information), copy the second routing packet K2, unpack the copied second routing packet K2, and determine the output direction (output channel E) and priority of the second routing packet K2 , and send the output direction and priority information of the second routing packet K2 to the arbitration module.
  • the arbitration module obtains the priority in the header packet information of the first routing packet K1 from the storage module.
  • the arbitration module determines the second routing Packet K2 is about to apply for output channel E and the priority of the second routing packet K2 (assumed to be 2) is higher than the priority of routing packet K1 (assumed to be 1), then the interrupt operation is started, an interrupt command is issued, and the routing packet K1 is input into the FIFO Stop receiving new input routing packets, and after all routing packets in the FIFO corresponding to the routing packet K1 are transmitted, the routing device B can determine the number of data packets that have been transmitted by the first routing packet K1 according to the count value in the counting module, and generate a The pseudo-tail packet is sent, and the data transmission of the first routing packet K1 is ended in advance.
  • the arbitration module outputs a control instruction to control the switch unit in the transmission module to disconnect the first route including the input channel W of K1 and the output channel E, and interrupt the first route with low priority.
  • the input channel (S) of the routing packet K2 is connected with the output channel, and the data of the second routing packet K2 with a higher priority starts to be transmitted.
  • the unpacking module determines that the tail packet of the second routing packet is to be transmitted according to the identification of the flag bit
  • the value of the corresponding register can be cleared (the header packet information of the second routing packet is cleared), and the count of the counter at this time The value is 0, indicating that all the data packets of the second routing packet K2 have been transmitted.
  • the output channel is sent to the arbitration module. In this case, because the arbitration module Only the channel information of the second routing packet K2 is received, and the arbitration module determines that the current transmission is the tail packet of the first routing packet K2, and the data packet is transmitted, and a switch control instruction is generated to control the transmission module to input the second routing packet K2.
  • the connection between the channel S and the output channel E is disconnected, as shown in FIG. 7 , that is, after the data transmission of the second routing packet K2 with higher priority is completed, the routing of the interrupted first routing packet K1 is continued.
  • the process is to transmit the remaining data of the first routing packet K1 that has not been transmitted yet.
  • the embodiments of the present disclosure provide a routing device.
  • a priority order of routing packets is added to ensure that routing packets with higher priorities pass through blocking nodes more preferentially.
  • a protocol for interrupting and resuming routing packets is proposed, which theoretically ensures that routing packets with high priority can interrupt routing packets with low priority.
  • a routing protocol of header packet + data packet + tail packet is proposed, which supports the above-mentioned routing protocols with priority order and the characteristics of interruption and resume transmission, which improves the efficiency of routing transmission.
  • the routing device in the embodiment of the present disclosure can implement priority transmission of routing packets, improve configuration flexibility, and ensure priority transmission of high-priority routes. It can significantly improve the routing efficiency in the NoC network and reduce unnecessary packet header information.
  • the present disclosure may be a system, method and/or computer program product.
  • the computer program product may include a computer-readable storage medium having computer-readable program instructions loaded thereon for causing a processor to implement various aspects of the present disclosure.
  • a computer-readable storage medium may be a tangible device that can hold and store instructions for use by the instruction execution device.
  • the computer-readable storage medium may be, for example, but not limited to, an electrical storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing.
  • Non-exhaustive list of computer readable storage media include: portable computer disks, hard disks, random access memory (RAM), read only memory (ROM), erasable programmable read only memory (EPROM) or flash memory), static random access memory (SRAM), portable compact disk read only memory (CD-ROM), digital versatile disk (DVD), memory sticks, floppy disks, mechanically coded devices, such as printers with instructions stored thereon Hole cards or raised structures in grooves, and any suitable combination of the above.
  • RAM random access memory
  • ROM read only memory
  • EPROM erasable programmable read only memory
  • flash memory static random access memory
  • SRAM static random access memory
  • CD-ROM compact disk read only memory
  • DVD digital versatile disk
  • memory sticks floppy disks
  • mechanically coded devices such as printers with instructions stored thereon Hole cards or raised structures in grooves, and any suitable combination of the above.
  • Computer-readable storage media are not to be construed as transient signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (eg, light pulses through fiber optic cables), or through electrical wires transmitted electrical signals.
  • the computer readable program instructions described herein may be downloaded to various computing/processing devices from a computer readable storage medium, or to an external computer or external storage device over a network such as the Internet, a local area network, a wide area network and/or a wireless network.
  • the network may include copper transmission cables, fiber optic transmission, wireless transmission, routers, firewalls, switches, gateway computers, and/or edge servers.
  • a network adapter card or network interface in each computing/processing device receives computer-readable program instructions from a network and forwards the computer-readable program instructions for storage in a computer-readable storage medium in each computing/processing device .
  • Computer program instructions for carrying out operations of the present disclosure may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, or instructions in one or more programming languages.
  • Source or object code written in any combination, including object-oriented programming languages, such as Smalltalk, C++, etc., and conventional procedural programming languages, such as the "C" language or similar programming languages.
  • the computer readable program instructions may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer, or entirely on the remote computer or server implement.
  • the remote computer may be connected to the user's computer through any kind of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (eg, using an Internet service provider through the Internet connect).
  • LAN local area network
  • WAN wide area network
  • custom electronic circuits such as programmable logic circuits, field programmable gate arrays (FPGAs), or programmable logic arrays (PLAs) can be personalized by utilizing state information of computer readable program instructions.
  • Computer readable program instructions are executed to implement various aspects of the present disclosure.
  • These computer readable program instructions may be provided to a processor of a general purpose computer, special purpose computer or other programmable data processing apparatus to produce a machine that causes the instructions when executed by the processor of the computer or other programmable data processing apparatus , resulting in means for implementing the functions/acts specified in one or more blocks of the flowchart and/or block diagrams.
  • These computer readable program instructions can also be stored in a computer readable storage medium, these instructions cause a computer, programmable data processing apparatus and/or other equipment to operate in a specific manner, so that the computer readable medium on which the instructions are stored includes An article of manufacture comprising instructions for implementing various aspects of the functions/acts specified in one or more blocks of the flowchart and/or block diagrams.
  • Computer readable program instructions can also be loaded onto a computer, other programmable data processing apparatus, or other equipment to cause a series of operational steps to be performed on the computer, other programmable data processing apparatus, or other equipment to produce a computer-implemented process , thereby causing instructions executing on a computer, other programmable data processing apparatus, or other device to implement the functions/acts specified in one or more blocks of the flowcharts and/or block diagrams.
  • each block in the flowchart or block diagrams may represent a module, segment, or portion of instructions, which comprises one or more functions for implementing the specified logical function(s) executable instructions.
  • the functions noted in the blocks may occur out of the order noted in the figures. For example, two blocks in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved.
  • each block of the block diagrams and/or flowchart illustrations, and combinations of blocks in the block diagrams and/or flowchart illustrations can be implemented in dedicated hardware-based systems that perform the specified functions or actions , or can be implemented in a combination of dedicated hardware and computer instructions.

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Abstract

本公开涉及路由装置及片上网络的路由设备，所述装置包括：解包模块，用于在通过第一输出通道传输第一路由包的过程中，获取接收的第二路由包的传输请求信息；仲裁模块，用于当根据传输请求信息确定第二路由包请求的输出通道为第一输出通道、且第二路由包的优先级大于第一路由包的优先级时，中断所述第一路由包的传输，并输出第一开关控制信号；传输模块，用于根据所述第一开关控制信号连接所述第二路由包的输入通道及所述第一输出通道，以通过所述第一输出通道传输所述第二路由包。本公开实施例的装置通过中断优先级较低的路由包的传输，转而开始传输该优先级高的路由包，保证了片上网络的路由设备进行路由控制的合理性和路由传输效率。

Description

路由装置及片上网络的路由设备 技术领域
本公开涉及片上系统技术领域，尤其涉及一种路由装置及片上网络的路由设备。
背景技术
随着集成电路的发展，单个芯片上的计算单元不断增加，基于传统式总线的结构已经成为了芯片速度的瓶颈。因此借鉴计算机网络的思想，提出了片上网络(Network on Chip，NoC)的概念。对于多核系统，片上网络可以显著提高通信的性能。
根据物理链路的不同组成方式，片上网络可以有多种拓扑结构。在二维结构中，二维网络(2-Dimension mesh，2D Mesh)是一种较为常用的结构，如图1所示，主要有结构简单、可扩展性好、实现和分析较容易等优点。
相关技术中，片上网络中的路由设备按照多个路由包的接收顺序对多个路由包进行处理。然而实际使用中部分路由包可能对延时要求交严格，部分路由包则对延时要求较低。
发明内容
有鉴于此，本公开提出了一种路由装置，所述装置包括：
解包模块，用于在通过第一输出通道传输第一路由包的过程中，获取接收的第二路由包的传输请求信息，所述传输请求信息包括所述第二路由包的输出通道及优先级；
仲裁模块，电连接于所述解包模块，用于当根据所述传输请求信息确定所述第二路由包请求的输出通道为所述第一输出通道、且所述第二路由包的优先级大于所述第一路由包的优先级时，中断所述第一路由包的传输，并输出第一开关控制信号；
传输模块，电连接所述仲裁模块，用于根据所述第一开关控制信号连接所述第二路由包的输入通道及所述第一输出通道，以通过所述第一输出通道传输所述第二路由包。
在一种可能的实施方式中，所述装置还包括：
存储模块，电连接于所述解包模块、所述仲裁模块，用于存储所述第一路由包的头包信息及所述 第二路由包的头包信息，所述头包信息包括优先级及路由信息。
在一种可能的实施方式中，所述装置还包括：
计数模块，电连接于所述解包模块、所述传输模块；
所述解包模块还用于，将所述第二路由包的第一数据包序号写入所述计数模块作为计数值，所述第一数据包序号为所述第二路由包的数据包总个数；
所述计数模块用于，当所述传输模块通过所述第一输出通道每完成一次所述第二路由包的数据转发时，将所述计数模块的计数值减一。
在一种可能的实施方式中，所述仲裁模块还用于在中断所述第一路由包的传输时，输出第一打包指令，所述装置还包括：
打包模块，电连接于所述仲裁模块及所述计数模块，用于在接收到所述第一打包指令的情况下，获取计数模块中与所述第一路由包对应的计数值作为第二数据包序号，并生成所述第一路由包的伪尾包，其中，所述伪尾包中的第二数据包序号为第一数据包序号与所述第一路由包中已传输的数据包个数之间的差值，所述第一数据包序号为所述第二路由包的数据包总个数，所述伪尾包用于指示中断对所述第一路由包的传输；
所述传输模块还用于通过所述第一输出通道发送所述第一路由包的伪尾包，以中断所述第一路由包的传输；
所述存储模块电连接于所述打包模块，还用于存储所述第一路由包的伪尾包。
在一种可能的实施方式中，所述仲裁模块还用于在中断所述第一路由包的传输时，输出第二打包指令，其中，
所述打包模块还用于，在接收到所述第二打包指令的情况下，获取所述存储模块中所述第一路由包的头包信息，以生成所述第一路由包的伪头包，其中，所述伪头包中的第一数据包序号为所述第一路由包的伪尾包中的第二数据包序号；
所述存储模块还用于存储所述第一路由包的伪头包。
在一种可能的实施方式中，所述仲裁模块还用于，在确定所述第二路由包的数据传输结束的情况下，控制所述传输模块断开所述第二路由包的输入通道与所述第一输出通道的连接；
所述解包模块还用于，从所述存储模块获取所述第一路由包的伪头包的传输请求信息；
所述仲裁模块还用于，根据所述第一路由包的伪头包的传输请求信息控制所述传输模块连接所述第一路由包的输入通道与所述第一输出通道，以继续通过所述第一输出通道传输所述第一路由包中尚未传输的数据。
在一种可能的实施方式中，所述通过所述第一输出通道传输所述第二路由包的数据，包括：
通过所述第一输出通道传输所述第二路由包的数据包和尾包，
其中，所述数据包包括所述第二路由包的数据，所述尾包用于指示结束对所述第二路由包的传输，
其中，所述尾包包括所述路由包类型和第二数据包序号，所述第二数据包序号用于指示所述第二路由包中尚未传输的数据包个数。
在一种可能的实施方式中，所述装置还包括：
统计模块，用于根据接收到的所述第二路由包中的数据包的个数与序号差值的大小关系，确定所述第二路由包是否存在丢包情况，
其中，所述序号差值为第一数据包序号与所述第二数据包序号之间的差值，所述第一数据包序号为所述第二路由包的数据包总个数。
在一种可能的实施方式中，所述传输模块包括开关单元，所述开关单元用于根据开关控制信号连接输入通道及输出通道，以传输路由包；
所述存储模块包括寄存器单元及缓存单元，所述寄存器单元用于存储路由包的头包信息，所述缓存单元用于缓存输入通道上的路由包、路由包的伪尾包、伪头包；
所述计数模块包括多个计数器，多个计数器与多个输出通道一一对应。
在一种可能的实施方式中，所述解包模块还用于接收所述第二路由包的头包，获取所述头包包括所述第二路由包的优先级和路由信息，
其中，所述路由信息包括路由包类型、目的端地址、第一数据包序号、起始存储地址、数据包地址存储方式和校验位中的至少一种；
其中，所述路由包类型用于指示所述第二路由包的类型，所述目的端地址为所述第二路由包的接收端的绝对地址或者相对地址，所述第一数据包序号用于指示所述第二路由包中待传输的数据包总个 数，所述起始存储地址为所述第二路由包中的数据包在所述接收端内存中存储的起始地址，所述数据包地址存储方式用于指示所述第二路由包中的数据包在所述接收端内存中的存储方式，所述校验位用于指示所述头包中的数据是否正确。
根据本公开的另一方面，提供了一种片上网络的路由设备，所述路由设备包括所述的路由装置，
其中，所述路由设备为所述片上网络的任意一个节点中的路由设备，所述节点包括处理器核。
本公开实施例通过提供一种路由装置，在通过第一输出通道传输第一路由包的数据的过程中，接收第二路由包的传输请求信息；当第二路由包请求的输出通道为第一输出通道且第二路由包的优先级大于第一路由包的优先级；通过第一输出通道传输第二路由包的数据；通过构建一种具有优先级顺序的路由协议，保证优先级较高的路由包可以获得较低的路由延时，比如当一组路由包因为路径繁忙而将要被阻塞时，如果该路由包的优先级比输出通道上正在传输的路由包的优先级高，则中断优先级较低的路由包的传输，转而开始传输该优先级高的路由包，保证了片上网络的路由设备进行路由控制的合理性和路由传输效率。
根据下面参考附图对示例性实施例的详细说明，本公开的其它特征及方面将变得清楚。
附图说明
包含在说明书中并且构成说明书的一部分的附图与说明书一起示出了本公开的示例性实施例、特征和方面，并且用于解释本公开的原理。
图1示出了相关技术中的二维网络的结构图。
图2示出了根据本公开一实施方式的路由装置的框图。
图3示出了根据本公开一实施方式的路由装置的示意图。
图4示出了根据本公开一实施例的路由装置的示意图。
图5、图6、图7示出了根据本公开一实施例的路由装置传输路由包的示意图。
具体实施方式
以下将参考附图详细说明本公开的各种示例性实施例、特征和方面。附图中相同的附图标记表示 功能相同或相似的元件。尽管在附图中示出了实施例的各种方面，但是除非特别指出，不必按比例绘制附图。
在这里专用的词“示例性”意为“用作例子、实施例或说明性”。这里作为“示例性”所说明的任何实施例不必解释为优于或好于其它实施例。
另外，为了更好的说明本公开，在下文的具体实施方式中给出了众多的具体细节。本领域技术人员应当理解，没有某些具体细节，本公开同样可以实施。在一些实例中，对于本领域技术人员熟知的方法、手段、元件和电路未作详细描述，以便于凸显本公开的主旨。
相关技术中，片上网络中的路由设备按照多个路由包的接收顺序对多个路由包进行处理。目前的路由协议对路由包不做优先级上的区分，所有路由包优先级相同。然而实际使用中部分路由包可能对延时要求较严格，部分路由包则对延时要求较低。因此建立一种带有优先级顺序的高效路由协议就是非常必要的。
本公开实施例提供一种路由装置，保证优先级较高的路由包可以获得较低的路由延时，比如当一组路由包因为路径繁忙而将要被阻塞时，如果该路由包的优先级比输出通道上正在传输的路由包的优先级高，则中断优先级较低的路由包的传输，转而开始传输该优先级高的路由包，保证了片上网络的路由设备进行路由控制的合理性和路由传输效率。
请参阅图2，图2示出了根据本公开一实施方式的路由装置的框图。
如图2所示，所述装置包括：
解包模块10，用于在通过第一输出通道传输第一路由包的过程中，获取接收的第二路由包的传输请求信息，所述传输请求信息包括所述第二路由包的输出通道及优先级；
仲裁模块20，电连接于所述解包模块10，用于当根据所述传输请求信息确定所述第二路由包请求的输出通道为所述第一输出通道、且所述第二路由包的优先级大于所述第一路由包的优先级时，中断所述第一路由包的传输，并输出第一开关控制信号；
传输模块30，电连接所述仲裁模块20，用于根据所述第一开关控制信号连接所述第二路由包的输入通道及所述第一输出通道，以通过所述第一输出通道传输所述第二路由包。
本公开实施例的路由装置，在通过第一输出通道传输第一路由包的数据的过程中，接收第二路由包的传输请求信息；当第二路由包请求的输出通道为第一输出通道且第二路由包的优先级大于第一路 由包的优先级；通过第一输出通道传输第二路由包的数据；通过构建一种具有优先级顺序的路由协议，保证优先级较高的路由包可以获得较低的路由延时，比如当一组路由包因为路径繁忙而将要被阻塞时，如果该路由包的优先级比输出通道上正在传输的路由包的优先级高，则中断优先级较低的路由包的传输，转而开始传输该优先级高的路由包，保证了片上网络的路由设备进行路由控制的合理性和路由传输效率。
在一种可能的实施方式中，本公开实施例的解包模块、仲裁模块可以通过专用硬件电路实现，也可以通过通用硬件电路结合可执行逻辑实现，例如，解包模块、仲裁模块可以通过中央处理器CPU、微处理器MCU、图形处理器GPU、数字信号处理器DSP、可编程门阵列FPGA等实现，对此本公开实施例不做限定。
在一个示例中，所述路由装置可以为片上网络中的路由设备，路由设备为片上网络的任意一个节点中的路由设备，节点包括处理器核。
其中，片上网络包括多个节点(如图1所示)，每个节点中包括路由设备。根据物理链路的不同组成方式，片上网络可以有多种拓扑结构。本公开实施例仅以片上网络的拓扑结构为2D Mesh为例进行说明。
路由设备也称为路由器，是连接两个或多个网络的硬件设备，在网络间起网关的作用，是读取每一个数据包中的地址并进行传送的专用智能性的网络设备。
请参阅图3，图3示出了根据本公开一实施方式的路由装置的示意图。
在一个示例中，路由装置(路由器、路由设备)可以包括多个输入通道(如输入通道W、输入通道N、输入通道E、输入通道S、本地输入通道、)、多个输出通道(例如输出通道W、输出通道N、输出通道E、输出通道S、本地输出通道)，路由装置可以建立输入通道与输出通道的连接，以将路由包进行传输。
下面对路由包的格式进行示例性介绍。
相关技术中，一般是将包含路由地址信息的包头信息与数据进行打包后发送，每次发送的数据包中都包含包头信息，导致路由传输效率较低。
即目前的路由传输中每个数据包都由包头和数据两部分组成，然而一般情况下，同一个路由器发 出的数据包中大部分的路由信息都是一样的，因此可以将路由信息的传输减少到一次。本公开实施例提供的一次路由过程包括头包、数据包和尾包的传输，即先发送一个头包，该头包包括路由地址信息；然后发送数据包，数据包中不再包含路由地址信息，即减少数据包中的路由地址信息；最后传输一个尾包，尾包用于指示该路由过程的所有数据包已经发送完成，完成本次路由的数据传输。
每组路由包的头包中还需要标明该路由包的优先级，以便对不同优先级的路由包分别处理。
一个完整的路由过程为传输一组路由包的过程，该组路由包包含头包、数据包和尾包，其中数据包为一个或者多个数据包。
在一种可能的实现方式中，头包的头包信息包括路由包的优先级、路由包类型、目的端地址、第一数据包序号、起始存储地址、数据包地址存储方式和校验位中的至少一种信息。
示意性的，头包所包含的信息如表一所示。
表一
P T Dst Rank Addr R C
其中，P为路由包的优先级。路由包的优先级用于指示该路由包的传输顺序。优先级与传输顺序呈正相关关系，即优先级越高，传输顺序也靠前。
T为路由包类型，比如，路由包类型包括数据配置包、普通数据包、查询包中的一种。本公开实施例对路由包类型的划分方式不加以限定。
Dst为目的端地址，即为该路由包的接收端的绝对地址或者相对地址。针对多维结构，比如包含一个芯片阵列，每个芯片又包含若干个核的阵列，则目的端地址为多维结构。
Rank为第一数据包序号，用于指示路由包中待传输的数据包总个数。
Addr为起始存储地址，即为路由包中的数据包在接收端内存中存储的起始地址。
R为数据包地址存储方式，用于指示路由包中的数据包在接收端内存中的存储方式。通常一个路由过程中不同数据包在接收端内存中按地址连续存储，但也可能有一定规律。示意性的，数据包地址存储方式用于指示在接收端内存中每存储预设数量的数据包，将路由地址跳转预设量后继续存储。比如，预设数量为5，即每接收并存储5个数据包，路由地址跳转一定量后继续存储，该信息可为实际的路由应用保留灵活性。
C为校验位，用于指示头包中的数据是否正确。可选地，校验位为第一数值时用于指示头包中的数据正确，校验位为除第一数值外的其他数值时用于指示头包中的数据错误。本公开实施例对第一数值的具体取值不加以限定。
在一种可能的实现方式中，路由包中的多个数据包均不包含路由地址信息。每个数据包包括数据，还可以包括校验位。
示意性的，数据包所包含的信息如表二所示。
表二
Data C
其中，Data为数据，C为校验位，用于指示数据包中的数据是否正确。
在一种可能的实现方式中，尾包用于指示结束对路由包的传输。尾包中包括路由包类型和第二数据包序号，第二数据包序号用于指示路由包中尚未传输的数据包个数，方便接收端进行数据完整性校验。尾包中还可以包括校验位，用于指示尾包中的数据是否正确。
可选地，校验位为第二数值时用于指示数据包中的数据正确，校验位为除第二数值外的其他数值时用于指示数据包中的数据错误。本公开实施例对第二数值的具体取值不加以限定。
示意性的，尾包所包含的信息如表三所示。
表三
T Rank C
其中，T为路由包类型，一组路由包中的头包和尾包的路由包类型是相同的。
Rank为第二数据包序号，用于指示路由包中尚未传输的数据包个数。一般情况下第二数据包序号为零。
C为校验位，用于指尾包中的数据是否正确。可选地，校验位为第三数值时用于指示尾包中的数据正确，校验位为除第三数值外的其他数值时用于指示尾包中的数据错误。本公开实施例对第三数值的具体取值不加以限定。
综上所述，本公开实施例的路由装置传输的路由包包括头包、数据包、尾包，通过将头包、数据包、尾包分开传输，使得数据包中不再包含路由地址信息，减少了数据包中的路由地址信息，提高传 递提高效率；同时，本公开实施例的路由装置基于以上方式传输路由包，还可以支持路由数据传输的中断和续传，进一步保证了路由传输效果。
即基于上述的头包+数据包+尾包的路由协议，在一般情况下，一个路由过程应该是由发送端依次发送头包、数据包、尾包，然后结束该组路由包的数据传输，接收端通过校验接收到的数据包的个数是否等于头包中的第一数据包序号与尾包中的第二数据包序号的差值来判断。
需要说明的是，本公开实施例中的发送端为发送端路由设备的简称，接收端为接收端路由设备的简称。
请参阅图4，图4示出了根据本公开一实施例的路由装置的示意图。
在一种可能的实施方式中，如图4所示，所述装置还可以包括：
存储模块40，电连接于所述解包模块10、所述仲裁模块20，用于存储所述第一路由包的头包信息及所述第二路由包的头包信息，所述头包信息包括优先级及路由信息。
在一个示例中，存储器模块40可以由任何类型的易失性或非易失性存储设备或者它们的组合实现，如静态随机存取存储器(Static Random Access Memory，SRAM)，电可擦除可编程只读存储器(Electrically Erasable Programmable Read-Only Memory，EEPROM)，可擦除可编程只读存储器(Erasable Programmable Read Only Memory，EPROM)，可编程只读存储器(Programmable Read-Only Memory，PROM)，只读存储器(Read Only Memory，ROM)，磁存储器，快闪存储器，磁盘或光盘。相应地，存储器20还可以包括存储器控制器，以提供处理器10对存储器20的访问。
在一个示例中，如图4所示，存储模块40可以包括寄存器单元410及缓存单元420。
在一个示例中，寄存器单元410可以包括多组寄存器，寄存器单元410可以用于存储路由包的头包信息，所述头包可以包括路由包的优先级和路由信息。
在一个示例中，所述路由信息可以包括路由包类型、目的端地址、第一数据包序号、起始存储地址、数据包地址存储方式和校验位中的至少一种。
在一个示例中，所述路由包类型用于指示所述第二路由包的类型，所述目的端地址为所述第二路由包的接收端的绝对地址或者相对地址，所述第一数据包序号用于指示所述第二路由包中待传输的数 据包总个数，所述起始存储地址为所述第二路由包中的数据包在所述接收端内存中存储的起始地址，所述数据包地址存储方式用于指示所述第二路由包中的数据包在所述接收端内存中的存储方式，所述校验位用于指示所述头包中的数据是否正确。
在一个示例中，解包模块10可以对路由包进行解包处理，获取路由包(例如第二路由包)的头包信息，示例性的，解包模块10可以通过XY维序路由等路由算法对路由包进行解包。在获得路由包的头包信息的情况下，解包模块10可以将该路由包的头包信息存储在寄存器单元410中。
在一个示例中，缓存单元420可以作为输入通道接收的路由包的缓冲带，缓存单元420可以被设置为先入先出FIFO模式(当然，也可以设置为后入先出LIFO模式，对此，本公开实施例不做限定)，以缓冲各个输入通道上的路由包，本公开实施例对于每个输入通道，都设置有一个输入缓冲FIFO，假设路由装置共有五个输入FIFO，每个输入通道的缓存大小可以设置为路由包长度的整倍数，在一个示例中，可以将路由器每个FIFO设置为3个路由包大小，以兼顾路由器的性能和代价。
在一个示例中，解包模块可以通过轮询的方式查询缓存单元的每个输入通道FIFO中是否有路由包，如果有路由包，则提取路由包中的标志位，判断该路由包是属于头包、数据包还是尾包。如果该路由包属于头包或尾包，则解包模块将该路由包复制一份，进行解包。如果是头包，则解包模块根据路由算法(如XY维序路由等)确定该路由包的输出方向(输出通道)，然后将路由包的输出方向以及优先级信息发送给仲裁模块。如果是尾包，则将该路由输出通道对应的寄存器值清空，同时发送对应的输出通道给仲裁模块，便于关闭该路由过程。
在一个示例中，仲裁模块接收到解包模块的信息，如果仲裁模块接收到的是路由输出方向和路由优先级信息，则表示有一个路由包的头包申请某个输出通道且其优先级为对应值。此时，仲裁模块首先判断申请的输出通道是否占用，如果没有占用，则控制传输模块建立该路由包的输入通道及申请的输出通道的连接，以直接传输该路由包。每当仲裁模块向传输模块发送信息，确定将对应的输入通道和输出通道连接起来的时候，解包模块也会得到此信息，解包模块可以将该路由头包的全部信息写入该输出通道对应的寄存器中。
在一种可能的实施方式中，如图4所示，所述装置还可以包括：
计数模块50，电连接于所述解包模块10、所述传输模块30。
所述解包模块10还可以用于，将所述第二路由包的第一数据包序号写入所述计数模块作为计数值，所述第一数据包序号为所述第二路由包的数据包总个数；
所述计数模块可以用于，当所述传输模块30通过所述第一输出通道每完成一次所述第二路由包的数据转发时，将所述计数模块的计数值减一。
通过以上装置，本公开实施例可以实现对路由包的传输计数。
在一个示例中，计数模块50可以包括多个计数器(例如5个)，每个计数器与输出通道一一对应，当仲裁模块20发送指令控制传输模块30传输路由包时，解包模块30可以将路由包要传输的数据包的总数写入对应的计数器中，以使得计数器对当前路由包还未传输的数据包进行计数，例如，若当前处理的是路由包的头包，则未传输的数据包为路由包待传输的数据包的总数；此后，每传输一个路由包的数据包，计数器即从当前计数值减一；若当前处理的是路由包的尾包，则标识路由包的所有数据包均传输完毕，计数器的计数值为0。
在一种可能的实施方式中，所述仲裁模块20还可以用于在中断所述第一路由包的传输时，输出第一打包指令。
在一种可能的实施方式中，如图4所示，所述装置还可以包括：
打包模块60，电连接于所述仲裁模块20及所述计数模块50(及存储模块40)，用于在接收到所述第一打包指令的情况下，获取计数模块50中与所述第一路由包对应的计数值作为第二数据包序号，并生成所述第一路由包的伪尾包，其中，所述伪尾包中的第二数据包序号为第一数据包序号与所述第一路由包中已传输的数据包个数之间的差值，所述第一数据包序号为所述第二路由包的数据包总个数，所述伪尾包用于指示中断对所述第一路由包的传输；
在一种可能的实施方式中，所述传输模块30还可以用于通过所述第一输出通道发送所述第一路由包的伪尾包，以中断所述第一路由包的传输；
在一种可能的实施方式中，所述存储模块40还可以用于存储所述第一路由包的伪尾包。
在一种可能的实施方式中，所述传输模块30可以包括开关单元310，所述开关单元310可以用于根据开关控制信号连接输入通道及输出通道，以传输路由包。
在一个示例中，开关单元310可以包括交叉开关、单刀多掷开关、多刀多掷开关等。
在一个示例中，当发送该伪尾包时，仲裁模块20可以控制传输模块30切断所述第一路由包的输入通道与第一输出通道的连接，并且，解包模块10可以控制停止接收第一路由包的数据包。
在一个示例中，当原路径上的各个路由装置接收到第一路由包的伪尾包的情况下，各个路由装置的仲裁模块20均可以控制传输模块30切断所述第一路由包的输入通道与第一输出通道的连接。
在一种可能的实施方式中，所述仲裁模块20还可以用于在中断所述第一路由包的传输时，输出第二打包指令。
在一种可能的实施方式中，所述打包模块60还用于，在接收到所述第二打包指令的情况下，获取所述存储模块40(寄存器单元)中所述第一路由包的头包信息，以生成所述第一路由包的伪头包，其中，所述伪头包中的第一数据包序号为所述第一路由包的伪尾包中的第二数据包序号；
在一种可能的实施方式中，所述存储模块40还用于存储所述第一路由包的伪头包。
在一个示例中，打包模块60可以将存储模块40中获取的第一路由包的头包信息中的第一数据包序号替换为计数模块50中的计数值，也即第一数据包的伪尾包的第二数据包序号，其余信息保持不变。
在一种可能的实施方式中，本公开实施例的打包模块可以通过专用硬件电路实现，也可以通过通用硬件电路结合可执行逻辑实现，例如，解包模块、仲裁模块可以通过中央处理器CPU、微处理器MCU、图形处理器GPU、数字信号处理器DSP、可编程门阵列FPGA等实现，对此本公开实施例不做限定。
在一个示例中，第一路由包的伪头包可以存储在第一路由包对应的缓存FIFO的最前列，以在第二路由包完成传输时，使得解包模块10获取第一路由包的伪头包触发第一路由包的继续传输。
本公开实施例所述的中断第一路由包的传输，包括将第一路由包的路由过程分为两个路由过程，分别为：第一路由包头包+所述伪尾包的路由过程、所述伪头包+第一路由包头包的路由过程。
在一种可能的实施方式中，所述仲裁模块20还可以用于，在确定所述第二路由包的数据传输结束的情况下，控制所述传输模块断开所述第二路由包的输入通道与所述第一输出通道的连接。
在一种可能的实施方式中，所述通过所述第一输出通道传输所述第二路由包的数据，可以包括：
通过所述第一输出通道传输所述第二路由包的数据包和尾包，
其中，所述数据包包括所述第二路由包的数据，所述尾包用于指示结束对所述第二路由包的传输，
其中，所述尾包包括所述路由包类型和第二数据包序号，所述第二数据包序号用于指示所述第二路由包中尚未传输的数据包个数。
在一个示例中，当传输第二路由包的路径建立完成时，第二路由包的输入通道与第一输出通道建立了连接，第二路由包的数据包及尾包可以通过第一输出通道传输到下一跳路由节点。
在一种可能的实施方式中，如图4所示，所述装置还可以包括：
统计模块70，用于根据接收到的所述第二路由包中的数据包的个数与序号差值的大小关系，确定所述第二路由包是否存在丢包情况，
其中，所述序号差值为第一数据包序号与所述第二数据包序号之间的差值，所述第一数据包序号为所述第二路由包的数据包总个数。
在一个示例中，当路由装置接收到第二路由包的尾包时，可以结束第二路由包的路由传输过程。路由装置结束对第二路由包的传输后，统计模块70可以根据接收到的第二路由包中的数据包的个数与序号差值的大小关系，确定第二路由包是否存在丢包情况，序号差值为第一数据包序号与第二数据包序号之间的差值。
即若接收到的第二路由包中的数据包的个数等于序号差值，表示第二路由包不存在丢包情况；若接收到的第二路由包中的数据包的个数不等于序号差值时，表示第二路由包存在丢包情况，则产生可供控制器处理的错误信号。其中，提供给路由设备或控制器的序号差值为第一数据包序号与第二数据包序号之间的差值。
在一种可能的实施方式中，本公开实施例的统计模块可以通过专用硬件电路实现，也可以通过通用硬件电路结合可执行逻辑实现，例如，解包模块、仲裁模块可以通过中央处理器CPU、微处理器MCU、图形处理器GPU、数字信号处理器DSP、可编程门阵列FPGA等实现，对此本公开实施例不做限定。
在一种可能的实施方式中，所述解包模块10还可以用于，从所述存储模块获取所述第一路由包的伪头包的传输请求信息；
在一种可能的实施方式中，所述仲裁模块20还可以用于，根据所述第一路由包的伪头包的传输请求信息控制所述传输模块连接所述第一路由包的输入通道与所述第一输出通道，以继续通过所述 第一输出通道传输所述第一路由包中尚未传输的数据。
在一个示例中，在第二路由包的数据传输结束后，路由装置继续传输第一路由包中尚未传输的数据。在第二路由包的数据传输结束后，路由装置根据缓存的第一路由包的伪头包，继续传输第一路由包中尚未传输的数据包和尾包。
下面结合具体的示例对所述路由装置进行示例性介绍。
请参阅图5、图6、图7，图5、图6、图7示出了根据本公开一实施例的路由装置传输路由包的示意图。
在一个示例中，如图5所示，假设在第一路由包K1的传输路径中包括路由装置A、路由装置B、路由装置C，以路由装置B为例，假如在路由路径的路由装置B出现了高优先级路由包(来自路由装置D的第二路由包K2)将要打断低优先级路由包的情况，路由装置B正在通过输出通道E(第一输出通道)传输优先级为“1”的第一路由包K1。
假设，某一时刻路由装置B的路由设备收到了S方向输入的第二路由包K2，解包模块提取第二路由包K2中的标志位，判断第二路由包K2为头包(头包、数据包、尾包具有不同的标识信息)，对第二路由包K2进行复制，对复制的第二路由包K2进行解包，确定第二路由包K2的输出方向(输出通道E)及优先级，并将第二路由包K2的输出方向以及优先级信息发送给仲裁模块，此时，仲裁模块从存储模块中获取第一路由包K1的头包信息中优先级，当仲裁模块确定第二路由包K2将要申请输出通道E且第二路由包K2的优先级(假设为2)高于路由包K1的优先级(假设为1)，此时开始中断操作，发出中断指令，路由包K1输入FIFO停止接收新的输入路由包，待路由包K1对应的FIFO中的路由包全部传输结束之后，路由装置B可以根据计数模块中计数值确定第一路由包K1已经传输的数据包个数，生成一个伪尾包，并发送该伪尾包，提前结束该第一路由包K1的数据传输。同时根据之前保存的第一路由包K1的头包，从存储模块中获取第一路由包K1的头包信息，重新为该优先级较低的第一路由包K1生成一个伪头包，并存放在路由包K1的缓存队列的队首首，然后仲裁模块输出控制指令控制传输模块中的开关单元断开第一路由包括K1的输入通道W与输出通道E的连接，中断低优先级的第一路由包K1的数据的传输(如图6所示)，将路由包K2的输入通道(S)与该输出通道连接起来，开始传输优先级较高 的第二路由包K2的数据。
在一个示例中，当解包模块根据标志位的标识判断要传输第二路由包的尾包时，可以清空对应的寄存器的值(清除第二路由包的头包信息)，此时计数器的计数值为0，表示第二路由包K2的数据包全部传输完毕，解包模块对第二路由包K2的尾包解包后，将输出通道发送到仲裁模块，在这种情况下，由于仲裁模块仅收到了第二路由包K2的通道信息，仲裁模块判断当前传输的是第一路由包K2的尾包，其数据包完成传输，生成开关控制指令，控制传输模块将第二路由包K2的输入通道S与输出通道E之间的连接断开，如图7所示，即，当优先级较高的第二路由包K2的数据传输结束后，继续刚才被中断的第一路由包K1的路由过程，即对剩余的尚未传输的第一路由包K1的数据进行传输。
综上所述，本公开实施例提供了一种路由装置，在一方面，添加了路由包的优先级顺序，保证高优先级的路由包更优先通过阻塞节点。在另一方面，提出了路由包中断和续传的协议，理论上保证高优先级的路由包可以打断低优先级的路由包。在另一方面，提出头包+数据包+尾包的路由协议，支持上述具有优先级顺序的路由协议和中断、续传的特点，提高了路由传输的效率。
本公开实施例的路由装置可以实现对路由包按优先级传输，提高配置灵活性，保证高优先级路由优先传输。可以显著提高NoC网络中的路由效率，减少不必要的包头信息。
本公开可以是系统、方法和/或计算机程序产品。计算机程序产品可以包括计算机可读存储介质，其上载有用于使处理器实现本公开的各个方面的计算机可读程序指令。
计算机可读存储介质可以是可以保持和存储由指令执行设备使用的指令的有形设备。计算机可读存储介质例如可以是――但不限于――电存储设备、磁存储设备、光存储设备、电磁存储设备、半导体存储设备或者上述的任意合适的组合。计算机可读存储介质的更具体的例子(非穷举的列表)包括：便携式计算机盘、硬盘、随机存取存储器(RAM)、只读存储器(ROM)、可擦式可编程只读存储器(EPROM或闪存)、静态随机存取存储器(SRAM)、便携式压缩盘只读存储器(CD-ROM)、数字多功能盘(DVD)、记忆棒、软盘、机械编码设备、例如其上存储有指令的打孔卡或凹槽内凸起结构、以及上述的任意合适的组合。这里所使用的计算机可读存储介质不被解释为瞬时信号本身，诸如无线电波或者其他自由传播的电磁波、通过波导或其他传输媒介传播的电磁波(例如，通过光纤电缆的光脉冲)、或者通过电线传输的电信号。
这里所描述的计算机可读程序指令可以从计算机可读存储介质下载到各个计算/处理设备，或者 通过网络、例如因特网、局域网、广域网和/或无线网下载到外部计算机或外部存储设备。网络可以包括铜传输电缆、光纤传输、无线传输、路由器、防火墙、交换机、网关计算机和/或边缘服务器。每个计算/处理设备中的网络适配卡或者网络接口从网络接收计算机可读程序指令，并转发该计算机可读程序指令，以供存储在各个计算/处理设备中的计算机可读存储介质中。
用于执行本公开操作的计算机程序指令可以是汇编指令、指令集架构(ISA)指令、机器指令、机器相关指令、微代码、固件指令、状态设置数据、或者以一种或多种编程语言的任意组合编写的源代码或目标代码，所述编程语言包括面向对象的编程语言—诸如Smalltalk、C++等，以及常规的过程式编程语言—诸如“C”语言或类似的编程语言。计算机可读程序指令可以完全地在用户计算机上执行、部分地在用户计算机上执行、作为一个独立的软件包执行、部分在用户计算机上部分在远程计算机上执行、或者完全在远程计算机或服务器上执行。在涉及远程计算机的情形中，远程计算机可以通过任意种类的网络—包括局域网(LAN)或广域网(WAN)—连接到用户计算机，或者，可以连接到外部计算机(例如利用因特网服务提供商来通过因特网连接)。在一些实施例中，通过利用计算机可读程序指令的状态信息来个性化定制电子电路，例如可编程逻辑电路、现场可编程门阵列(FPGA)或可编程逻辑阵列(PLA)，该电子电路可以执行计算机可读程序指令，从而实现本公开的各个方面。
这里参照根据本公开实施例的方法、装置(系统)和计算机程序产品的流程图和/或框图描述了本公开的各个方面。应当理解，流程图和/或框图的每个方框以及流程图和/或框图中各方框的组合，都可以由计算机可读程序指令实现。
这些计算机可读程序指令可以提供给通用计算机、专用计算机或其它可编程数据处理装置的处理器，从而生产出一种机器，使得这些指令在通过计算机或其它可编程数据处理装置的处理器执行时，产生了实现流程图和/或框图中的一个或多个方框中规定的功能/动作的装置。也可以把这些计算机可读程序指令存储在计算机可读存储介质中，这些指令使得计算机、可编程数据处理装置和/或其他设备以特定方式工作，从而，存储有指令的计算机可读介质则包括一个制造品，其包括实现流程图和/或框图中的一个或多个方框中规定的功能/动作的各个方面的指令。
也可以把计算机可读程序指令加载到计算机、其它可编程数据处理装置、或其它设备上，使得在计算机、其它可编程数据处理装置或其它设备上执行一系列操作步骤，以产生计算机实现的过程，从而使得在计算机、其它可编程数据处理装置、或其它设备上执行的指令实现流程图和/或框图中的一个或多个方框中规定的功能/动作。
附图中的流程图和框图显示了根据本公开的多个实施例的系统、方法和计算机程序产品的可能实现的体系架构、功能和操作。在这点上，流程图或框图中的每个方框可以代表一个模块、程序段或指令的一部分，所述模块、程序段或指令的一部分包含一个或多个用于实现规定的逻辑功能的可执行指令。在有些作为替换的实现中，方框中所标注的功能也可以以不同于附图中所标注的顺序发生。例如，两个连续的方框实际上可以基本并行地执行，它们有时也可以按相反的顺序执行，这依所涉及的功能而定。也要注意的是，框图和/或流程图中的每个方框、以及框图和/或流程图中的方框的组合，可以用执行规定的功能或动作的专用的基于硬件的系统来实现，或者可以用专用硬件与计算机指令的组合来实现。
以上已经描述了本公开的各实施例，上述说明是示例性的，并非穷尽性的，并且也不限于所披露的各实施例。在不偏离所说明的各实施例的范围和精神的情况下，对于本技术领域的普通技术人员来说许多修改和变更都是显而易见的。本文中所用术语的选择，旨在最好地解释各实施例的原理、实际应用或对市场中的技术的改进，或者使本技术领域的其它普通技术人员能理解本文披露的各实施例。

Claims (11)

  1. 一种路由装置，其特征在于，所述装置包括：
    解包模块，用于在通过第一输出通道传输第一路由包的过程中，获取接收的第二路由包的传输请求信息，所述传输请求信息包括所述第二路由包的输出通道及优先级；
    仲裁模块，电连接于所述解包模块，用于当根据所述传输请求信息确定所述第二路由包请求的输出通道为所述第一输出通道、且所述第二路由包的优先级大于所述第一路由包的优先级时，中断所述第一路由包的传输，并输出第一开关控制信号；
    传输模块，电连接所述仲裁模块，用于根据所述第一开关控制信号连接所述第二路由包的输入通道及所述第一输出通道，以通过所述第一输出通道传输所述第二路由包。
  2. 根据权利要求1所述的装置，其特征在于，所述装置还包括：
    存储模块，电连接于所述解包模块、所述仲裁模块，用于存储所述第一路由包的头包信息及所述第二路由包的头包信息，所述头包信息包括优先级及路由信息。
  3. 根据权利要求2所述的装置，其特征在于，所述装置还包括：
    计数模块，电连接于所述解包模块、所述传输模块；
    所述解包模块还用于，将所述第二路由包的第一数据包序号写入所述计数模块作为计数值，所述第一数据包序号为所述第二路由包的数据包总个数；
    所述计数模块用于，当所述传输模块通过所述第一输出通道每完成一次所述第二路由包的数据转发时，将所述计数模块的计数值减一。
  4. 根据权利要求2或3所述的装置，其特征在于，所述仲裁模块还用于在中断所述第一路由包的传输时，输出第一打包指令，所述装置还包括：
    打包模块，电连接于所述仲裁模块及所述计数模块，用于在接收到所述第一打包指令的情况下，获取计数模块中与所述第一路由包对应的计数值作为第二数据包序号，并生成所述第一路由包的伪尾包，其中，所述伪尾包中的第二数据包序号为第一数据包序号与所述第一路由包中已传输的数据包个数之间的差值，所述第一数据包序号为所述第二路由包的数据包总个数，所述伪尾包用于指示中断对所述第一路由包的传输；
    所述传输模块还用于通过所述第一输出通道发送所述第一路由包的伪尾包，以中断所述第一路由 包的传输；
    所述存储模块电连接于所述打包模块，还用于存储所述第一路由包的伪尾包。
  5. 根据权利要求4所述的装置，其特征在于，所述仲裁模块还用于在中断所述第一路由包的传输时，输出第二打包指令，其中，
    所述打包模块还用于，在接收到所述第二打包指令的情况下，获取所述存储模块中所述第一路由包的头包信息，以生成所述第一路由包的伪头包，其中，所述伪头包中的第一数据包序号为所述第一路由包的伪尾包中的第二数据包序号；
    所述存储模块还用于存储所述第一路由包的伪头包。
  6. 根据权利要求5所述的装置，其特征在于，
    所述仲裁模块还用于，在确定所述第二路由包的数据传输结束的情况下，控制所述传输模块断开所述第二路由包的输入通道与所述第一输出通道的连接；
    所述解包模块还用于，从所述存储模块获取所述第一路由包的伪头包的传输请求信息；
    所述仲裁模块还用于，根据所述第一路由包的伪头包的传输请求信息控制所述传输模块连接所述第一路由包的输入通道与所述第一输出通道，以继续通过所述第一输出通道传输所述第一路由包中尚未传输的数据。
  7. 根据权利要求1所述的装置，其特征在于，所述通过所述第一输出通道传输所述第二路由包的数据，包括：
    通过所述第一输出通道传输所述第二路由包的数据包和尾包，
    其中，所述数据包包括所述第二路由包的数据，所述尾包用于指示结束对所述第二路由包的传输，
    其中，所述尾包包括所述路由包类型和第二数据包序号，所述第二数据包序号用于指示所述第二路由包中尚未传输的数据包个数。
  8. 根据权利要求7所述的装置，其特征在于，所述装置还包括：
    统计模块，用于根据接收到的所述第二路由包中的数据包的个数与序号差值的大小关系，确定所述第二路由包是否存在丢包情况，
    其中，所述序号差值为第一数据包序号与所述第二数据包序号之间的差值，所述第一数据包序号 为所述第二路由包的数据包总个数。
  9. 根据权利要求3所述的装置，其特征在于，
    所述传输模块包括开关单元，所述开关单元用于根据开关控制信号连接输入通道及输出通道，以传输路由包；
    所述存储模块包括寄存器单元及缓存单元，所述寄存器单元用于存储路由包的头包信息，所述缓存单元用于缓存输入通道上的路由包、路由包的伪尾包、伪头包；
    所述计数模块包括多个计数器，多个计数器与多个输出通道一一对应。
  10. 根据权利要求1所述的装置，其特征在于，所述解包模块还用于接收所述第二路由包的头包，获取所述头包包括所述第二路由包的优先级和路由信息，
    其中，所述路由信息包括路由包类型、目的端地址、第一数据包序号、起始存储地址、数据包地址存储方式和校验位中的至少一种；
    其中，所述路由包类型用于指示所述第二路由包的类型，所述目的端地址为所述第二路由包的接收端的绝对地址或者相对地址，所述第一数据包序号用于指示所述第二路由包中待传输的数据包总个数，所述起始存储地址为所述第二路由包中的数据包在所述接收端内存中存储的起始地址，所述数据包地址存储方式用于指示所述第二路由包中的数据包在所述接收端内存中的存储方式，所述校验位用于指示所述头包中的数据是否正确。
  11. 一种片上网络的路由设备，其特征在于，所述路由设备包括如权利要求1-10任一项所述的路由装置，
    其中，所述路由设备为所述片上网络的任意一个节点中的路由设备，所述节点包括处理器核。
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