WO2022109975A1 - 存储芯片、存储设备及其访问方法 - Google Patents

存储芯片、存储设备及其访问方法 Download PDF

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Publication number
WO2022109975A1
WO2022109975A1 PCT/CN2020/132076 CN2020132076W WO2022109975A1 WO 2022109975 A1 WO2022109975 A1 WO 2022109975A1 CN 2020132076 W CN2020132076 W CN 2020132076W WO 2022109975 A1 WO2022109975 A1 WO 2022109975A1
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storage
data
channel
controller
channels
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PCT/CN2020/132076
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English (en)
French (fr)
Inventor
王祥林
鲁傚禹
刘光辉
金颀
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华为技术有限公司
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Priority to PCT/CN2020/132076 priority Critical patent/WO2022109975A1/zh
Priority to CN202080104318.8A priority patent/CN116097233A/zh
Publication of WO2022109975A1 publication Critical patent/WO2022109975A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus

Definitions

  • the present application relates to the technical field of mobile storage, and in particular, to a storage chip, a storage device and an access method thereof.
  • NAND flash is used as the main information cache space.
  • process evolution and the development of three-dimensional (3-dimensions, 3D) stacking technology the density of a single dielectric particle (die) in NAND flash memory continues to increase to increase the capacity of a single dielectric particle.
  • the data line width of a single storage channel (channel) on the current NAND flash memory interface is 8 bits (bit).
  • the number of storage channels coupled with the controller is fixed, for example, 8 storage channels; under the condition of a certain total capacity, when the capacity of a single medium particle increases, the single medium particle is relatively smaller than the smaller capacity.
  • the relative proportion of the data line bit width of the storage channel that can be used by the single media particle is reduced. For example, when the capacity of a single media particle is increased from 64 gigabytes (GB) to 128 GB, the The data line bit width of the memory channel is still 8 bits. Therefore, when the capacity of a single medium particle increases, the performance of direct memory access (DMA) in the NAND flash memory interface may be degraded, thereby reducing the access rate of the memory.
  • DMA direct memory access
  • the embodiments of the present application provide a memory chip, a storage device and an access method thereof, which can solve the problem that the access performance of the memory decreases when the capacity of a single medium particle increases when the total capacity of the storage device remains unchanged, thereby improving the performance of the memory. access rate.
  • an embodiment of the present application provides a memory chip.
  • the memory chip includes a controller and a plurality of memory channels coupled with the controller.
  • a controller for determining an access mode for accessing the flash media based on the number of the plurality of storage channels and the number of flash media coupled to the controller through the plurality of storage channels.
  • the controller is further configured to combine multiple storage channels into a first channel if the access mode is the wide-port mode, and access the flash memory medium through the first channel.
  • the first channel includes at least one associated storage channel, and the bit width of one associated storage channel is N times that of a single storage channel; N is a positive integer greater than or equal to 2.
  • the controller can combine all memory channels into one or more associated memory channels.
  • a memory chip includes 8 memory channels with a bit width of 8 bits, and the 8 memory channels can be combined in pairs, that is, Combined into 4 associative storage channels with a bit width of 16 bits; some storage channels can also be combined into one or more associative storage channels.
  • a memory chip includes 8 storage channels with a bit width of 8 bits. Merge 4 of the 8 storage channels into a 32-bit associative storage channel, and the rest are not merged; or merge 4 of the 8 storage channels in pairs, that is, merge into 2 bit widths of 16-bit associative memory channels, the rest are not merged.
  • the controller of the memory chip may determine an access mode for accessing the flash memory medium based on the relationship between the number of memory channels and the flash memory medium. If the access mode is the wide-port mode, that is, the conditions of the wide-port mode are satisfied. For example, when the number of storage channels is greater than the number of flash media, the controller can combine some or all of the multiple storage channels to make the combined first channel It includes at least one associated storage channel, and accesses the flash memory medium through the merged first channel, and the data line bit width of the storage channel usable by the corresponding flash memory medium can be increased through the combination of the storage channels, thereby improving the read and write of the memory chip. performance, thereby improving the memory access efficiency.
  • the controller is further configured to access the flash memory medium through multiple storage channels if the access mode is the normal mode. That is, if the conditions for wide-port mode are not met, such as when the number of storage channels is equal to the number of flash media, the storage channels will not be combined, and the controller will access the flash media through the original multiple storage channels, so that the storage chip can be compatible with more memory, thereby reducing costs.
  • the number of multiple storage channels coupled to the controller is X; the number of flash memory media coupled to the controller through the multiple storage channels is Y; wherein X and Y are both positive integers. If X>Y, the access mode for accessing the flash medium can be the wide-port mode. In this solution, if X is greater than Y, it means that there is an idle storage channel in the memory chip, and the data line bit width of the storage channel corresponding to the flash memory medium can be increased by multiplexing the part of the idle storage channel. Thus, the memory access efficiency is improved.
  • the controller may also be configured to access the first flash medium through the first associated storage channel.
  • the first associated storage channel may be an associated storage channel in the first channel; the first flash medium may be a flash medium in the flash media.
  • the number of storage channels included in the first associated storage channel of the device determines the number of multiple storage channels coupled to the controller, the media capacity of the first flash medium, and the number of flash media coupled to the controller through the multiple storage channels.
  • the total media capacity can determine the number of storage channels contained in the first associated storage channel.
  • the controller may include a cache unit and an alignment control unit.
  • the cache unit may include multiple cache spaces, and the multiple cache spaces are in one-to-one correspondence with multiple storage channels in the memory chip.
  • the controller may be configured to write data to the first flash memory medium through the first associated memory channel.
  • the cache unit can be used to split the first data into multiple data segments, and store the multiple data segments of the first data cyclically in sequence according to a preset sequence, and the M storage channels in the first associated storage channel are respectively in the corresponding M cache spaces.
  • the alignment control unit can be configured to cyclically obtain the data segments in the M cache spaces corresponding to the M storage channels in the first associated storage channel in a preset order, and send them to the M buffer spaces in the first associated storage channel respectively in the storage channel, so that the first data is written into the first flash memory medium.
  • one encoded block (CW data) is stored in the first flash medium, and data can be transmitted through multiple storage channels in the first associated storage channel. Therefore, in order to ensure correct and orderly storage of data, it is necessary to align the data storage.
  • the cache unit splits one CW data (ie, the first data) into multiple data segments, and stores them in the cache spaces corresponding to the M storage channels in the first associative storage channel respectively, and through the The alignment control unit sequentially retrieves each data segment of the first data from a plurality of storage channels in the first associative storage channel and the corresponding cache spaces, and sends them to the corresponding storage channel in the first associative storage channel, so as to realize the data aligned storage.
  • the orderly storage of data can be ensured, and the reliability of the storage chip can be improved while the data writing efficiency in the storage chip is improved.
  • the controller may include a cache unit and an alignment control unit.
  • the cache unit may include multiple cache spaces, and the multiple cache spaces are in one-to-one correspondence with multiple storage channels in the memory chip.
  • the controller may be configured to read data from the first flash memory medium through the first associated memory channel.
  • the cache unit can be used to obtain the second data from the M storage channels in the first associative storage channel respectively, and respectively cache the second data in the M cache spaces corresponding to the M storage channels in the first associative storage channel, and store the second data in the M cache spaces respectively corresponding to the M storage channels in the first associative storage channel.
  • the decoded data is sent when the first information sent by the alignment control unit is received.
  • the second data is the data stored in the first flash memory medium
  • the decoded data is the second data obtained by the cache unit.
  • the alignment control unit may be configured to record the total length of the second data acquired from the first associated storage channel, and send the first information to the cache unit when the total length of the acquired second data reaches a preset length.
  • the first information is used to indicate that the acquired second data can be decoded.
  • the second data is buffered in the buffer space corresponding to the storage channel CH0; If the second data is returned from the storage channel CH1 to the buffer unit, the second data is buffered in the buffer space corresponding to the storage channel CH1. In this way, when the second data reaches the size of one CW data, it can be decoded smoothly to complete the data read operation, thereby improving the reliability of the memory chip.
  • the controller may further include a decoding unit.
  • the cache unit can also be used to obtain second data of a fixed length from the M cache spaces respectively corresponding to the M storage channels in the first associated storage channel in a circular sequence according to a preset sequence; and send the fixed length to the decoding unit the second data.
  • the decoding unit is used to decode the second data read from the first flash memory medium, and when the data is decoded, the cache unit is sequentially corresponding to the M storage channels in the first associated storage channel. In the M buffer spaces, the data to be decoded is obtained and sent to the decoding unit for decoding, thereby ensuring the correct sequence of the read data for correct decoding, thereby improving the reliability of the memory chip.
  • an embodiment of the present application provides a storage device.
  • the storage device includes a plurality of flash memory media, and any possible memory chip as in the first aspect above; the plurality of flash memory media are coupled to the controller through a plurality of storage channels in the memory chip.
  • an embodiment of the present application provides an access method for a storage device.
  • the storage device includes a storage chip and a plurality of flash media, wherein the storage chip includes a controller and a plurality of storage channels coupled to the controller, and the plurality of flash media are coupled to the controller through the plurality of storage channels.
  • the method includes the controller determining an access mode for accessing the flash memory medium based on the number of the plurality of memory channels and the number of the flash memory medium coupled to the controller through the plurality of memory channels. If the access mode is the wide-port mode, the controller combines the multiple storage channels into a first channel, and accesses the flash memory medium through the first channel.
  • the first channel includes at least one associated storage channel, and the bit width of one associated storage channel is N times that of a single storage channel; N is a positive integer greater than or equal to 2.
  • the controller accesses the flash memory medium through multiple storage channels.
  • the number of multiple storage channels coupled to the controller is X; the number of flash media coupled to the controller through the multiple storage channels is Y; both X and Y are positive integers. If X>Y, the access mode for accessing the flash medium is wide port mode.
  • the controller accessing the flash memory medium through the first channel may include: the controller accessing the first flash memory medium through a first associated storage channel.
  • the first associated storage channel is an associated storage channel in the first channels.
  • the first flash medium is one of the flash mediums.
  • the controller may include a cache unit and an alignment control unit; the cache unit may include multiple cache spaces, and the multiple cache spaces are in one-to-one correspondence with multiple storage channels in the memory chip.
  • the controller accessing the first flash memory medium through the first associated storage channel may include: the controller writing data to the first flash memory medium through the first associated storage channel.
  • the cache unit splits the first data into a plurality of data segments. The cache unit sequentially and cyclically stores the plurality of data segments of the first data in the M cache spaces corresponding to the M memory channels in the first associated memory channel according to a preset sequence.
  • the alignment control unit cyclically acquires the data segments in the M cache spaces corresponding to the M storage channels in the first associated storage channel in a preset order, and sends them to the M storage channels in the first associated storage channel, respectively, to write the first data to the first flash medium of the memory.
  • the controller may include a cache unit and an alignment control unit, the cache unit may include X cache spaces, and the X cache spaces respectively correspond to the X memory channels in the memory chip one-to-one.
  • the controller accessing the first flash memory medium through the first associated storage channel may include: the controller reading data from the first flash memory medium through the first associated storage channel.
  • the cache unit obtains the second data from the M storage channels in the first associative storage channel respectively, and caches the second data in the M storage channels in the first associative storage channel, respectively, in the corresponding M cache spaces; the second data is the storage data in the first flash medium.
  • the alignment control unit records the total length of the second data acquired from the first associated storage channel, and sends the first information to the cache unit when the total length of the acquired second data reaches a preset length.
  • the first information is used to indicate that the acquired second data can be decoded.
  • the buffer unit After receiving the first information of the alignment control unit, the buffer unit sends the decoded data.
  • the decoded data is the second data obtained by the cache unit.
  • the controller may further include a decoding unit.
  • Sending the decoded data by the buffer unit may include: the buffer unit sequentially and circularly obtains second data of a fixed length from the M storage channels in the first associated storage channel in the corresponding M buffer spaces according to a preset sequence.
  • the buffer unit sends the fixed-length second data to the decoding unit.
  • any storage device provided above and an access method for the storage device, etc. can be implemented by the storage chip provided in the first aspect above or associated with the storage chip provided in the first aspect above. Therefore, , the beneficial effects that can be achieved can be referred to the beneficial effects of the memory chips provided above, which will not be repeated here.
  • FIG. 1 is a schematic diagram 1 of a system architecture of a memory chip according to an embodiment of the present application
  • FIG. 2 is a second schematic diagram of a system architecture of a memory chip according to an embodiment of the present application
  • FIG. 3 is a structural block diagram of a storage device provided by an embodiment of the present application.
  • FIG. 4 is a schematic diagram of a data storage format of a cache unit in a memory chip provided by an embodiment of the present application
  • FIG. 5 is a flowchart of a method for accessing a storage device provided by an embodiment of the present application.
  • FIG. 6 is an interactive flowchart when writing data to a storage device according to an embodiment of the present application.
  • FIG. 7 is an interaction flowchart when the storage device according to the embodiment of the present application reads data.
  • At least one means one or more
  • plural means two or more.
  • And/or which describes the association relationship of the associated objects, indicates that there can be three kinds of relationships, for example, A and/or B, which can indicate: the existence of A alone, the existence of A and B at the same time, and the existence of B alone, where A, B can be singular or plural.
  • At least one item(s) below or similar expressions thereof refer to any combination of these items, including any combination of single item(s) or plural items(s).
  • At least one (a) of a, b or c may represent: a, b, c, a-b, a-c, b-c or a-b-c, where a, b and c may be single or multiple.
  • the character "/" generally indicates that the associated objects are an "or” relationship.
  • words such as "first” and “second” do not limit the quantity and execution order.
  • FIG. 1 is a schematic diagram 1 of a system architecture of a memory chip according to an embodiment of the present application.
  • a memory chip of universal flash storage generally includes a flash controller and a plurality of storage channels (channels) coupled to the flash controller.
  • the storage channel can be a flash input/output (flash input/output, flash IO) pin.
  • the flash memory controller in UFS is generally coupled with 4 or more storage channels, and each storage channel is coupled with a flash die (ie, medium particle) for data transmission of the flash medium.
  • the storage capacity of a single flash medium increases, the storage capacity of the flash medium that can be used by the flash medium relative to a flash medium with a smaller capacity remains unchanged.
  • the relative proportion of the data line bit width of the channel is reduced. For example, when the capacity of the flash memory medium is increased from 64 gigabytes (GB) to 128 GB, the data line bit width of the storage channel that can be used is still 8 bits. Therefore, when the capacity of the flash memory medium increases, the access performance of direct memory access (DMA) of the memory chip may be degraded, which in turn leads to a decrease in the access rate of the memory.
  • DMA direct memory access
  • the total capacity of the memory (or storage device) remains unchanged, if the capacity of a single flash memory medium increases, the number of flash memory media in the memory will decrease accordingly, resulting in redundant storage channels in the memory chip. cause a waste of resources.
  • FIG. 2 is a second schematic diagram of a system architecture of a memory chip according to an embodiment of the present application. Since the number of storage channels coupled to the flash memory controller is fixed and the total memory capacity remains unchanged, if the storage capacity of a single flash memory medium increases, the number of flash memory media in the memory decreases, resulting in remaining storage channels. Please refer to FIG. 2 , in the memory chip shown in FIG. 2 , compared with the memory chip shown in FIG. 1 , the number of flash media coupled to the memory chip has changed from 4 to 2. Therefore, between the storage channel and the flash media In the case of one-to-one correspondence, there are idle memory channels in the memory chip.
  • At least two storage channels can be combined into one associated storage channel, that is, the wide-port mode, which can increase the data line bit width of the storage channels available to the flash medium and improve the readability of the storage chip. Write performance, thereby improving the direct memory access (DMA) bandwidth and improving the memory access rate.
  • DMA direct memory access
  • the wide-port mode described in the embodiments of the present application is a usage scenario in which at least two memory channels are combined into one associated memory channel in one memory chip.
  • the normal mode described in the embodiments of the present application is a usage scenario in which memory channels are not combined in one memory chip. Whether the wide port mode is used in a memory chip (or memory device) is determined by the number of memory channels in the memory chip and the number of flash media coupled to the controller through the plurality of memory channels.
  • each flash memory medium it can be determined as follows (taking the memory chip shown in FIG. 1 as an example):
  • the wide-port mode can be used, and two adjacent storage channels can be combined into one storage channel.
  • CH0 and CH1 in Figure 1 can be combined into an associated storage channel, and CH2 and CH3 can be merged into an associated storage channel.
  • the associated storage The bit width of the data line of the channel can be expanded to 2 times that of a single storage channel, that is, from the original 8 bits to 16 bits.
  • the wide-port mode can be used to combine the four storage channels into one storage channel. For example, assuming that the number of flash media in Figure 1 is changed from 4 to 1, CH0, CH1, CH2, and CH3 in Figure 1 can be combined into one associated storage channel, and the associated storage channel can be expanded to a single
  • the data line bit width of the storage channel is 4 times, that is, the original 8 bits are expanded to 32 bits.
  • the wide-port mode can be used only if the number of storage channels is greater than the number of flash media.
  • the number of memory channels is X
  • the number of flash media coupled to the controller through a plurality of memory channels is Y. If the number of storage channels is greater than the number of flash media, that is, X>Y, the access mode for accessing the flash media in the memory can adopt the wide-port mode, that is, the idle storage channels can be multiplexed, so that at least two storage channels can be combined into An associative memory channel.
  • a memory or storage device
  • the original memory chip including the controller and multiple devices coupled to the controller
  • the medium capacity of a single flash memory medium increases under the condition that the medium capacity remains unchanged. storage channels
  • the read and write performance of the original memory can still be maintained, thereby reducing costs.
  • FIG. 3 is a structural block diagram of a storage device provided by an embodiment of the present application.
  • a storage device provided by an embodiment of the present application includes a plurality of flash memory media, and a memory chip as shown in FIG. 1 or FIG. 2 ; wherein the plurality of flash memory media are coupled to a controller through a plurality of storage channels in the memory chip device.
  • an embodiment of the present application provides a memory chip, the memory chip includes a controller and a plurality of storage channels coupled to the controller; wherein the controller may be a flash memory controller as shown in FIG. 1 or FIG. 2
  • the storage channel can be CH0, CH1, CH2 and CH3 as shown in Figure 1 or Figure 2.
  • the controller is configured to determine an access pattern for accessing the flash memory medium based on the number of the plurality of storage channels and the number of flash memory media coupled to the controller through the plurality of memory channels. If the number of storage channels is greater than the number of flash media, the access mode for accessing the flash media may be determined as a wide-port mode.
  • the controller is configured to combine multiple storage channels into a first channel, and access the above-mentioned flash memory medium through the first channel.
  • the first channel includes at least one associated storage channel, the bit width of one associated storage channel is N times that of a single storage channel, and N is a positive integer greater than or equal to 2.
  • the controller is used to access the flash memory medium through the original multiple storage channels.
  • controller is configured to determine the access mode for accessing the flash medium based on the number of multiple storage channels and the number of flash media coupled to the controller through the multiple storage channels, and may use the following methods:
  • the number of flash media, the type and capacity of each flash media can be known, and according to the number of flash media and the number of storage channels, it can be known whether the memory can be accessed in wide-port mode; therefore, when the chip is packaged , GPIO pins can be reserved on the top layer of the UFS chip to select and control the access mode for accessing the flash memory medium; for example, the value of the GPIO pins can be directly configured on the substrate, for example, when the GPIO is 1, it means the memory chip
  • the wide port mode can be used, the idle storage channels can be reused, at least two storage channels can be combined into one storage channel for use, and the data line bit width of the storage channel can be increased.
  • the initial state of the flash media after power-on can be normal mode.
  • the ID of the flash media manufacturer can be scanned to obtain the model of the flash media. information, calculate the total media capacity of the flash media, and then identify whether to switch to the wide-port mode according to the relationship between the number of flash media and the number of storage channels. If you need to switch to wide-port mode, you can send a set feature command to the flash medium to modify the access mode of accessing the flash medium to wide-port mode; and combine some or all of multiple storage channels into One or more associated storage channels to expand the bit width of the data lines of the storage channel.
  • the controller When the controller is used to combine multiple storage channels into the first channel, it should determine the number of associated storage channels in the first channel and the number of storage channels in each associated storage channel.
  • the specific determination methods are as follows:
  • the total storage capacity in one memory is 1 terabyte (TB), and the number of memory channels to which the flash memory controller in the memory is coupled is 8.
  • the memory uses flash media with the same capacity, for example, if the memory uses a flash die with a capacity of 128GB, the memory requires 8 flash media, so one storage channel and flash media just meet the requirements One-to-one correspondence.
  • the flash memory medium with a capacity of 256GB is used in the memory, 4 flash memory media are required in the memory.
  • 4 storage channels in the memory may be in an idle state, so it is possible to Combines every two memory channels into an associative memory channel.
  • a flash memory medium with a capacity of 512 GB is used in the memory, 2 flash memory mediums are required in the memory, so every four storage channels can be combined into one associated storage channel.
  • the memory uses flash media of different capacities, for example, if the memory uses four 128GB flash media and one 512GB flash media, the four storage channels can be combined into one association
  • the storage channel is for 512GB of flash media.
  • the storage uses two 128GB flash media, one 256GB flash media, and one 512GB flash media, the two storage channels can be combined into one associated storage channel for the 256GB flash media.
  • Four of the storage channels are combined into one associated storage channel for 512GB of flash media.
  • the first associated storage channel can be used to access the first flash media among the flash media coupled to the controller through the plurality of storage channels, that is, the controller can use the for accessing the first flash medium through the first associated storage channel.
  • the controller When the access mode for accessing the flash medium is the wide-port mode, and the controller is used to combine multiple storage channels into the first channel, take the first channel including the first associated storage channel as an example, that is, the controller can combine multiple storage channels
  • the M storage channels in the M storage channel are merged into the first associated storage channel, which can be merged in the following ways:
  • a memory channel it can include DQ, DQS, CE, ALE, CLE, WEN and RE input and output pins;
  • CE is a chip enable (chip enable, CE) pin, and can also be used as a chip select pin ;
  • ALE is the address latch enable pin;
  • CLE is the command latch enable (command latch enable, CLE) pin;
  • DQ is the data input/output pin;
  • DQS is bidirectional Data control (bi-directional data strobe, DQS) pin;
  • WEN is a write enable (write enable, WEN) pin;
  • RE is a read enable (read enable, RE) pin.
  • Each storage channel includes a programmable timing generator (PTG) and a physical layer, where , the programmable timing generator PTG is used to generate the timing of data transmission, and the physical layer is used for data transmission, that is, input and output pins such as DQ, DQS, CE, ALE, CLE, WEN and RE are coupled to the physical layer of the storage channel .
  • PTG programmable timing generator
  • the controller merges the storage channel CH0 and the storage channel CH1 into the first associated storage channel (taking the data bit width in CH0 and CH1 as an example), the controller controls CH1 to turn off CLE, ALE, WEN and CE.
  • the enabling of the four signal input and output pins only enables the DQS and DQ signal input and output pins on CH1, so that CH1 is only used to transmit the data of the upper 8 bits or the lower 8 bits, so that the CH0 and CH1 is merged into an associated storage channel, that is, the first associated storage channel.
  • a memory chip includes at least 4 memory channels including a memory channel CH0, a memory channel CH1, a memory channel CH2, and a memory channel CH3.
  • the controller merges the four storage channels CH0, CH1, CH2 and CH3 into the first associated storage channel (taking the data bit width of CH0, CH1, CH2 and CH3 as an example)
  • the controller controls CH1, CH2 , CH3 all turn off the enable of the four signal input and output pins of CLE, ALE, WEN and CE, and only enable the DQS and DQ signal input and output pins on CH1, CH2 and CH3, so that CH1 is only used for transmitting high
  • the data of the 8th-15th bits, CH2 is only used to transmit the data of the 16th-23rd bits, and CH3 is only used to transmit the data of the 24th-31st bits.
  • the above is a specific manner for the controller to combine M storage channels among the multiple storage channels into the first associated storage channel. It should be understood that at least one associative storage channel is included in the first channel, so the manner of combining other associative storage channels is similar to that of the first associative storage channel, and details are not described herein again.
  • the controller accessing the flash medium through the first channel may include the controller accessing the first flash medium through the first associated storage channel. That is, after the controller merges at least two storage channels among the multiple storage channels into the first associated storage channel, the controller can access the first flash medium through the first associated storage channel. The following describes how to access the first flash memory medium through the first associated storage channel in the wide-port mode.
  • one encoded code word data corresponds to only one storage channel; however, in wide-port mode, one encoded CW data needs to correspond to two or more storage channels; Therefore, in order to facilitate decoding with a low density parity check code (LDPC), the data needs to be stored in alignment.
  • LDPC low density parity check code
  • an alignment control unit is arranged in the controller.
  • the controller may include an encoding unit (encoder), a decoding unit (decoder), a code word data buffer unit (code word buffer), and an alignment control unit (align controller).
  • the encoding unit is used to encode the data to be stored into a CW data
  • the decoding unit is used to decode the CW data read from the flash memory medium to restore the data
  • the codeword data buffer unit (hereinafter referred to as the buffer unit) It is used to cache CW data
  • the alignment control unit is used to realize the alignment and order preservation of CW data in wide port mode.
  • the controller determines the access mode for accessing the flash memory medium, and the related operations of the controller combining at least two storage channels among the plurality of storage channels into the first associated storage channel can be performed by the alignment control unit in the controller. accomplish.
  • the cache unit includes a plurality of cache spaces, and the plurality of cache spaces on the cache unit respectively correspond to the plurality of memory channels in the memory chip one-to-one. That is to say, a plurality of cache areas (ie, cache spaces) are provided on the cache unit, and each cache area is used to cache the transmission data of one memory channel in the memory chip.
  • a plurality of cache areas ie, cache spaces
  • each cache area is used to cache the transmission data of one memory channel in the memory chip.
  • the wide-port mode since two or more storage channels in the memory chip are combined into one first associated storage channel, which is used to access the first flash memory medium; therefore, one encoded CW data needs to correspond to two or more storage channels. More than two storage channels, that is, one CW data needs to be buffered in two or more buffer spaces on the buffer unit, and the two or more buffer spaces are respectively the same as the two in the first associated storage channel. corresponding to one or more storage channels.
  • the controller accesses the first flash memory medium through the first associated memory channel, which may include a write operation and a read operation. That is, the controller can be used to write data to the first flash memory medium through the first associated storage channel; the controller can also be used to read data from the first flash memory medium through the first associated storage channel.
  • controller for writing data to the first flash medium through the first associated storage channel.
  • the cache unit is configured to split the first data (ie, one CW data) into a plurality of data segments, and according to a preset sequence, The multiple data segments of the data are sequentially and cyclically stored in the M buffer spaces corresponding to the M storage channels in the first associated storage channel respectively.
  • FIG. 4 is a schematic diagram of a data storage format of a cache unit in a memory chip according to an embodiment of the present application.
  • FIG. 4 shows two buffer spaces in a buffer unit corresponding to the storage channels CH0 and CH1 respectively. If the storage channels CH0 and CH1 are combined into the first associated storage channel, the buffer unit divides one CW data into multiple 16-bit (bit) data segments (taking the bit width of the data lines of the storage channels CH0 and CH1 as 8 bits as Example), namely D0, D1, D2, D3, D4, D5... etc. 16-bit data segments in Fig. 4 .
  • bit 16-bit
  • the buffer unit will still split a CW data into multiple 16-bit data segments (taking the data line width of each storage channel as 8 bits as an example), such as D0, D1, D2, D3, D4, D5...etc.
  • the preset sequence of data is D0, D1, D2, D3, D4, D5..., so when CW data is stored, according to the preset sequence, data segments D0, D4, D8...
  • the cache unit can be stored in the cache unit for storage In the buffer space corresponding to the channel CH0; store the data segments D1, D5, D9... in the buffer space corresponding to the storage channel CH1 in the cache unit; store the data segments D2, D6, D10... In the corresponding buffer space; store the data segments D3, D7, D11... in the buffer space corresponding to the storage channel CH1 in the buffer unit.
  • the length of each data segment after one CW data is split is related to the data line bit width of each memory channel in the first associated memory channel.
  • the storage channel transmits data, it can transmit different data on the rising edge and falling edge of the clock cycle in one clock cycle, that is, in one clock cycle, the data length that the storage channel can transmit is the data line bit of the storage channel. 2 times the width. Therefore, when the CW data is divided into multiple data segments, the length of each data segment can be twice the data line bit width of the corresponding storage channel. Assuming that the data line bit width of the storage channel is 8 bits, then pass One data segment of the CW data transmitted by the storage channel may be 16 bits.
  • the CW data when a CW data is split, the CW data can be split into multiple data segments with inconsistent lengths, and each data segment can be split into multiple data segments with inconsistent lengths.
  • the length is determined by the data line bit width of the storage channel that transmits the data segment.
  • the alignment control unit is configured to cyclically obtain the M cache spaces corresponding to the M storage channels in the first associated storage channel according to a preset sequence.
  • the data segments are respectively sent to the M storage channels in the first associated storage channel, so that the first data is written into the first flash memory medium.
  • the alignment control unit alternates between the memory channels CH0 and CH0.
  • a 16-bit data segment is read from the cache space corresponding to the storage channel CH1, and sent to the storage channel CH0 and the storage channel CH1 respectively, so that the corresponding data is written into the first flash memory medium. That is to say, the alignment control unit sequentially reads the data segments D0, D2, D4, etc. from the cache space corresponding to the storage channel CH0, and sends them to the storage channel CH0; the alignment control unit sequentially reads the data segments from the cache space corresponding to the storage channel CH1. Data segments such as D1, D3, D5, etc. read from within, and sent to the storage channel CH1.
  • the first associated memory channel includes a memory channel CH0, a memory channel CH1, a memory channel CH2, and a memory channel CH3.
  • the alignment control unit may sequentially start from the storage channel CH0, the storage channel CH1, the storage channel CH2, and the storage channel CH3 corresponding to the storage channel CH0.
  • Corresponding data segments are acquired in the cache space and sent to the storage channel CH0, the storage channel CH1, the storage channel CH2 and the storage channel CH3 respectively, so that the corresponding data is written into the first flash memory medium. That is to say, the alignment control unit sequentially reads the data segments D0, D4, D8, etc.
  • the alignment control unit sequentially reads the data segments from the cache space corresponding to the storage channel CH1. Data segments such as D1, D5, D9, etc., read from the internal storage channel, and sent to the storage channel CH1; the alignment control unit sequentially reads the data segments such as D2, D6, D10, etc. from the buffer space corresponding to the storage channel CH2, and Send to the storage channel CH2; the alignment control unit sequentially reads the data segments D3, D7, D11, etc. from the buffer space corresponding to the storage channel CH3, and sends them to the storage channel CH3.
  • the following is an illustration of how the controller reads data from the first flash medium through the first associated storage channel.
  • the cache unit is configured to obtain the second data from M storage channels in the first associated storage channel respectively, and respectively cache the second data in the first associated storage channel
  • the M storage channels in are respectively in the corresponding M cache spaces; the second data is the data stored in the first flash memory medium.
  • the first associated storage channel includes a storage channel CH0 and a storage channel CH1, and the data acquired by the cache unit through the storage channel CH0 is stored in the storage channel CH0.
  • the data acquired by the buffer unit through the storage channel CH1 is stored in the buffer space corresponding to the storage channel CH1.
  • the first associated storage channel includes storage channel CH0, storage channel CH1, storage channel CH2 and storage channel CH3.
  • the data obtained by the cache unit through the storage channel CH0 is stored in the cache space corresponding to the storage channel CH0, and the cache unit passes through the storage channel CH0.
  • the data obtained by the storage channel CH1 is stored in the buffer space corresponding to the storage channel CH1
  • the data obtained by the buffer unit through the storage channel CH2 is stored in the buffer space corresponding to the storage channel CH2
  • the data obtained by the buffer unit through the storage channel CH3 is stored in the storage channel.
  • the buffer space corresponding to CH3 is stored in the buffer space corresponding to CH3.
  • the alignment control unit is configured to record the total length of the second data that has been acquired from the first associated storage channel, and is When the total length reaches the preset length, the first information is sent to the buffer unit.
  • the first information is used to indicate that the acquired second data can be decoded.
  • the buffer unit is also used to send decoded data. Wherein, the decoded data is the second data obtained by the cache unit.
  • the alignment control unit will record the total length of the second data acquired from the first associated storage channel;
  • the total length of the data reaches the preset length, for example, the length of one CW data (4KB)
  • the acquired CW data ie, the second data
  • the alignment control unit notifies the buffer unit to send the decoded data.
  • the second data reaches the size of one CW data, it can be decoded smoothly, so as to complete the data reading operation, so that the data transmission is correct, thereby improving the reliability of the memory chip.
  • the buffer unit when the buffer unit sends the decoded data, the buffer unit is further configured to, in a preset order, sequentially and cyclically obtain second data of a fixed length from the M buffer spaces respectively corresponding to the M storage channels in the first associated storage channel. ; and send the second data of fixed length to the decoding unit.
  • the sequence of the decoded data sent to the decoding unit can be correct, so that accurate data can be obtained, thereby improving the read and write performance of the memory chip. reliability of memory chips.
  • the cache unit sequentially circulates from the two memory channels (CH0 and CH1) in the first associated memory channel according to the preset order, respectively corresponding to the two memory channels (CH0 and CH1).
  • second data of a fixed length is obtained.
  • the fixed-length second data is the length of the data that can be transmitted in a single clock cycle of each storage channel (here, 16bit is taken as an example).
  • the cache unit first reads the data D0 from the cache space corresponding to the storage channel CH0, and then from the storage channel CH1
  • the data D1 is read from the corresponding buffer space
  • the data D2 is read from the buffer space corresponding to the storage channel CH0
  • the data D3 is read from the buffer space corresponding to the storage channel CH1, and the cycle is repeated in turn.
  • the decoding unit may read in the following order: sequentially cycle from the buffer space corresponding to the storage channel CH0, the buffer space corresponding to the storage channel CH1 The data D0, D1, D2, D3, etc. are read from the buffer space, the buffer space corresponding to the storage channel CH2, and the buffer space corresponding to the storage channel CH3.
  • the decoding unit may decode the received second data to complete data recovery.
  • each storage channel is in an independent state, and the input and output pins of each storage channel are enabled, namely DQ, DQS, RE, CE, ALE , CLE and WEN pins are enabled. If the normal mode is used to read and write data in the memory chip, the first flash memory medium can be accessed through the storage channel CH0, and the second flash memory medium can be accessed through the storage channel CH1.
  • the alignment control unit in the controller in the memory chip may only be used for instruction distribution, for example, distribute instructions to corresponding storage channels, such as storage channels CH0 and CH1.
  • an embodiment of the present application further provides a method for accessing a storage device, where the storage device includes a storage chip and multiple flash memory media, wherein the storage chip includes a controller and multiple storage channels coupled to the controller, Multiple flash media are coupled to the controller through multiple storage channels.
  • the method includes the following steps:
  • the controller determines an access mode for accessing the flash memory medium based on the number of the multiple storage channels and the number of the flash memory medium coupled to the controller through the multiple storage channels.
  • the number of multiple storage channels coupled to the controller is X; the number of flash media coupled to the controller through the multiple storage channels is Y; both X and Y are positive integers. If X>Y, the access mode for accessing the flash medium is wide-port mode.
  • controller determines the access mode for accessing the flash memory medium is described in the memory chip shown in FIG. 3, and will not be repeated here.
  • the controller if the access mode for accessing the flash memory medium is the wide-port mode, the controller combines multiple storage channels into a first channel.
  • the first channel includes at least one associated storage channel, and the data line bit width of one associated storage channel is N times that of a single storage channel; N is a positive integer greater than or equal to 2.
  • the controller can combine all memory channels into one or more associated memory channels.
  • a memory chip includes 8 memory channels with a bit width of 8 bits, and the 8 memory channels can be combined in pairs, that is, Combined into 4 associative storage channels with a bit width of 16 bits; some storage channels can also be combined into one or more associative storage channels.
  • a memory chip includes 8 storage channels with a bit width of 8 bits. Merge 4 of the 8 storage channels into a 32-bit associative storage channel, and the rest are not merged; or merge 4 of the 8 storage channels in pairs, that is, merge into 2 bit widths of 16-bit associative memory channels, the rest are not merged.
  • the controller accesses the flash memory medium through the first channel.
  • the controller accessing the flash memory medium through the first channel may include: the controller accessing the first flash memory medium through the first associated storage channel.
  • the first associated storage channel is an associated storage channel in the first channels.
  • the first flash medium is one of the flash mediums coupled to the controller through a plurality of storage channels.
  • the total media capacity of the flash media; X is the number of multiple storage channels coupled to the controller.
  • the controller accessing the first flash memory medium through the first associated storage channel may include: the controller writes data to the first flash memory medium through the first associated storage channel; and/or, the controller writes data from the first associated storage channel from The first flash medium reads data.
  • the controller includes an encoding unit (encoder), a decoding unit (decoder), a buffer unit (code word buffer), and an alignment control unit (align controller).
  • the encoding unit is used to encode the data to be stored into a CW data
  • the decoding unit is used to decode the CW data read from the flash memory medium to restore the data
  • the buffer unit is used to buffer the CW data
  • the alignment control unit is used to Alignment and order preservation of CW data is achieved in wide-port mode.
  • FIG. 6 shows an interaction flow chart for the controller in the embodiment of the present application to write data to the first flash memory medium through the first associated storage channel.
  • the controller for the controller to write data to the first flash memory medium through the first associated storage channel, the following operations may be included:
  • the encoding unit sends the first data to the buffer unit.
  • the encoding unit may send the CW data (ie, the first data) to the buffer unit.
  • the cache unit splits the first data into a plurality of data segments and caches them in M cache spaces respectively corresponding to the M memory channels in the first associative memory channel.
  • the cache unit may split the received first data (ie, one CW data) into multiple data segments, and store the multiple data segments of the first data cyclically in sequence in a preset sequence in the first data segment.
  • the M storage channels in the associative storage channels are respectively in the M buffer spaces corresponding to the M storage channels.
  • the preset sequence may be determined according to the number of the storage channel. For a specific storage method, reference may be made to the above description of the memory chip shown in FIG. 3 about how the cache unit stores data, which will not be repeated here.
  • the cache unit notifies the alignment control unit to write the first data to the first flash medium.
  • the alignment control unit reads the first data from the cache unit.
  • the alignment control unit sends a CLE/ALE instruction to the first associated memory channel.
  • the alignment control unit sends the CLE/ALE command to the storage channel whose CLE and ALE signal input and output pins are enabled That's it.
  • the CLE/ALE instruction is used to indicate the type of the first data written into the first flash memory medium, that is, to determine whether the first data is an address, a command or data.
  • the first associated storage channel returns a CLE/ALE command response.
  • the programmable timing generator (program timing generator, PTG) of one of the storage channels in the first associated storage channel may return an acknowledgement (acknowledgment, ACK) indication to the alignment control unit.
  • the first associated storage channel outputs the CLE/ALE timing sequence to the first flash medium.
  • the programmable timing generator PTG in one of the first associated storage channels outputs the CLE/ALE timing to the first flash medium, so as to determine when the transmitted first data is Address, command or data.
  • the alignment control unit outputs a direct memory access write operation (write DMA) instruction to the first associative storage channel, and transmits the first data to the first associative storage channel.
  • write DMA direct memory access write operation
  • step S604 the alignment control unit reads data
  • the alignment control unit cyclically obtains M in the first associated storage channel according to a preset sequence.
  • the data segments in the M cache spaces corresponding to the storage channels are respectively sent to the M storage channels in the first associated storage channel, so that the first data is written into the first flash medium of the memory.
  • the alignment control unit reads the first data from the buffer space corresponding to CH0 and CH1, and converts the 16-bit data to alternately output to CH0 and CH1 to write the first data into the first flash medium.
  • CH0 and CH1 the alignment control unit
  • the first associated storage channel outputs the DMA write operation sequence to the first flash memory medium, and transmits the first data.
  • the PTG in the first associative memory channel outputs the sequence of the direct memory access write operation to the first flash medium, and transmits the first data.
  • the PTG of each storage channel in the first associated storage channel first outputs the timing of the DMA write operation to the first flash memory medium, so as to transmit the first data .
  • each storage channel in the first associated storage channel can transmit the first data to the first flash memory medium, so that the first data is written into the first flash memory medium.
  • FIG. 7 shows an interaction flow chart for the controller in the embodiment of the present application to write data to the first flash memory medium through the first associated storage channel.
  • the controller for the controller to write data to the first flash memory medium through the first associated storage channel, the following operations may be performed:
  • the alignment control unit sends a CLE/ALE instruction to the first associated memory channel.
  • the alignment control unit sends the CLE/ALE command to the storage channel whose CLE and ALE signal input and output pins are enabled That's it.
  • the CLE/ALE instruction is used to indicate the type of the second data read from the first flash medium, that is, to determine whether the second data is an address, a command or data.
  • the first associated storage channel returns a response to the CLE/ALE instruction.
  • a programmable timing generator (program timing generator, PTG) of one of the storage channels in the first associated storage channel returns an acknowledgement (ACK) to the alignment control unit.
  • the first associated storage channel outputs the CLE/ALE timing sequence to the first flash medium.
  • the programmable timing generator PTG in one of the first associated storage channels outputs the CLE/ALE timing to the first flash medium, so as to determine when the second data is transmitted Address, command or data.
  • the alignment control unit sends a direct memory access read operation (read DMA) instruction to the first associated memory channel.
  • read DMA direct memory access read operation
  • the first associated storage channel outputs the DMA read operation timing sequence to the first flash memory medium.
  • the first flash medium returns the second data to the cache unit.
  • the first flash medium when the first flash medium returns the second data, it returns through M storage channels in the first associated storage channels.
  • the cache unit obtains the second data from the M storage channels in the first associative storage channel, respectively, and buffers the second data in the M storage channels in the first associative storage channel, respectively, in the corresponding M cache spaces.
  • the alignment control unit records the total length of the returned second data, and when the total length of the acquired second data reaches a preset length, sends the first information to the cache unit.
  • the first information is used to indicate that the acquired second data can be decoded.
  • the alignment control unit records the total length of the second data acquired from the first associative storage channel; if the total length of the acquired second data
  • the preset length is reached, such as the length of one CW data (4KB)
  • the acquired CW data ie, the second data
  • the alignment control unit notifies the buffer unit to send the decoded data (ie, send the first data). information).
  • the second data reaches the size of one CW data, it can be decoded smoothly, so as to complete the data reading operation, so that the data transmission is correct, thereby improving the reliability of the memory chip.
  • the buffer unit sends the decoded data to the decoding unit.
  • the decoded data is the second data obtained by the cache unit.
  • Sending decoded data to the decoding unit by the buffering unit includes: the buffering unit, in a preset order, sequentially circulates from the M storage channels in the first associated storage channel, respectively, in the corresponding M buffer spaces, and obtains a second fixed-length storage channel. data.
  • the buffer unit sends the fixed-length second data to the decoding unit.
  • the cache unit acquires the second data of the fixed length from the cache space, reference may be made to the memory chip shown in FIG. 3 . The description about the acquisition of the second data of the fixed length by the cache unit will not be repeated here.
  • the decoding unit decodes the received second data to complete data recovery.
  • the bit width of the data line can be increased by multiplexing the idle storage channels, so that the DMA read and write performance is increased.
  • Table 1 shows that in a storage device, under the condition that the total storage capacity remains unchanged, after the storage capacity of a single flash medium is increased, the number of flash media is reduced, and each flash medium is reused Free storage channel. When transferring data with a page size of 18 kilobytes (kilobyte, KB), the read performance is significantly improved after the data line bit width of the storage channel is extended from 8 bits to 16 bits.
  • the size of the sequence numbers of the above-mentioned processes does not mean the sequence of execution, and the execution sequence of each process should be determined by its functions and internal logic, and should not be dealt with in the embodiments of the present application. implementation constitutes any limitation.
  • the disclosed system, apparatus and method may be implemented in other manners.
  • the apparatus embodiments described above are only illustrative.
  • the division of the units is only a logical function division. In actual implementation, there may be other division methods.
  • multiple units or components may be combined or Can be integrated into another system, or some features can be ignored, or not implemented.
  • the shown or discussed mutual coupling or direct coupling or communication connection may be through some interfaces, indirect coupling or communication connection of devices or units, and may be in electrical, mechanical or other forms.
  • the units described as separate components may or may not be physically separated, and components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution in this embodiment.
  • each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically alone, or two or more units may be integrated into one unit.

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Abstract

本申请提供一种存储芯片、存储设备及其访问方法，能够解决存储设备在总容量不变的情况下，单介质颗粒的容量增加时，存储器的访问性能下降的问题，从而提高存储器的访问速率。该存储芯片的控制器可以基于存储通道和闪存介质的数量关系，确定访问闪存介质的访问模式。若访问闪存介质的访问模式为宽口模式，如存储通道的数量大于闪存介质的数量时，控制器可以将多个存储通道中的部分或全部合并，使合并后的第一通道中包括至少一个关联存储通道，并通过合并后的第一通道访问闪存介质，经过存储通道的合并可以增加相应的闪存介质可使用的存储通道的数据线位宽，从而提升该存储芯片的读写性能，进而提升存储器的访问效率。

Description

存储芯片、存储设备及其访问方法 技术领域
本申请涉及移动存储技术领域，尤其涉及一种存储芯片、存储设备及其访问方法。
背景技术
目前在消费级固态硬盘(solid state drive，SSD)中，采用与非电路式闪存(NAND flash)作为最主要的信息缓存空间。随着工艺演进和三维(3 dimensions，3D)堆叠技术的发展，NAND闪存中单个介质颗粒(die)的密度不断上升，以增加单介质颗粒的容量。
根据开放式NAND闪存接口协议(open nand flash interface，ONFI)和Toggle协议，目前NAND闪存接口上单个存储通道(channel)的数据线位宽为8位(bit)。对于一个存储设备来说，与控制器耦合的存储通道数量是一定的，例如8个存储通道；在总容量一定的情况下，单介质颗粒容量增加时，该单介质颗粒相对于更小容量的单介质颗粒而言，该单介质颗粒能够使用的存储通道的数据线位宽的相对比例减少，如单介质颗粒的容量由64吉字节(gigabyte，GB)增加到128GB时，其能够使用的存储通道的数据线位宽仍然为8位。因此，在单介质颗粒的容量增加的情况下，可能造成NAND闪存接口中的直接存储器访问(direct memory access，DMA)性能下降，进而导致存储器的访问速率降低。
发明内容
本申请实施例提供一种存储芯片、存储设备及其访问方法，能够解决存储设备在总容量不变的情况下，单介质颗粒的容量增加时，存储器的访问性能下降的问题，从而提高存储器的访问速率。
为达到上述目的，本申请采用如下技术方案：
第一方面，本申请实施例提供一种存储芯片。该存储芯片包括控制器以及与控制器耦合的多个存储通道。控制器，用于基于多个存储通道的数量以及通过多个存储通道耦合至控制器的闪存介质的数量，确定访问闪存介质的访问模式。控制器，还用于若访问模式为宽口模式，则将多个存储通道合并为第一通道，并通过第一通道访问闪存介质。其中，第一通道中包括至少一个关联存储通道，一个关联存储通道位宽为单个存储通道的N倍；N为大于或等于2的正整数。
也就是说，控制器可以将全部的存储通道合并为一个或多个关联存储通道，如一个存储芯片中包括8个位宽为8位的存储通道，可以将8个存储通道两两合并，即合并为4个位宽均为16位的关联存储通道；也可以将部分的存储通道合并为一个或多个关联存储通道，如一个存储芯片中包括8个位宽为8位的存储通道，可以将8个存储通道的其中4个存储通道合并为一个32位的关联存储通道，其余不合并；或者将8个存储通道的其中4个存储通道两两合并，即合并为2个位宽均为16位的关联存储通道，其余不合并。
基于第一方面提供的存储芯片，该存储芯片的控制器可以基于存储通道和闪存介质的数量关系，确定访问闪存介质的访问模式。若访问模式为宽口模式，即满足宽口模式的条件，如存储通道的数量大于闪存介质的数量时，控制器可以将多个存储通道中的部分或全部合并，使合并后的第一通道中包括至少一个关联存储通道，并通过合并后的第一通道访问闪存介质，经过存储通道的合并可以增加相应的闪存介质可使用的存储通道的数据线位宽，从而提升该存储芯片的读写性能，进而提升存储器的访问效率。
可选地，控制器还用于若访问模式为正常模式，则通过多个存储通道访问闪存介质。即若不满足宽口模式的条件，如存储通道的数量等于闪存介质的数量时，则不合并存储通道，控制器通过原有的多个存储通道访问闪存介质，以便该存储芯片可以兼容更多的存储器，从而降低成本。
可选地，与控制器耦合的多个存储通道的数量为X；通过多个存储通道耦合至控制器的闪存介质的数量为Y；其中，X和Y均为正整数。若X>Y，则访问闪存介质的访问模式可以为宽口模式。在该方案中，若X大于Y，则表示在该存储芯片中，存在空闲的存储通道，可通过复用该部分空闲的存储通道，来提升闪存介质所对应的存储通道的数据线位宽，从而提升存储器的访问效率。
进一步地，控制器还可以用于通过第一关联存储通道访问第一闪存介质。其中，第一关联存储通道可以为第一通道中的一个关联存储通道；第一闪存介质可以为闪存介质中的一个闪存介质。第一关联存储通道中的存储通道的数量M满足如下关系：M＝(P/Q)*X。其中，P为第一闪存介质的介质容量；Q为通过多个存储通道耦合至控制器的闪存介质的总介质容量；X为与控制器耦合的多个存储通道的数量。在该方案中，控制器将多个存储通道中的M个存储通道合并为第一关联存储通道时，可以通过关系式M＝(P/Q)*X直接确定，用于访问第一闪存介质的第一关联存储通道中包含的存储通道的数量，即确定了与控制器耦合的多个存储通道的数量、第一闪存介质的介质容量以及通过多个存储通道耦合至控制器的闪存介质的总介质容量，便可以确定第一关联存储通道中包含的存储通道的数量。
一种可能的设计方案中，控制器可以包括缓存单元和对齐控制单元。其中，缓存单元可以包括多个缓存空间，多个缓存空间分别与存储芯片中的多个存储通道一一对应。在该存储芯片中，控制器可以用于通过第一关联存储通道向第一闪存介质写入数据。缓存单元，可以用于将第一数据拆分为多个数据段，且按照预设顺序，将第一数据的多个数据段依次循环存储在，第一关联存储通道中的M个存储通道分别对应的M个缓存空间内。对齐控制单元，可以用于按照预设顺序，循环获取第一关联存储通道中的M个存储通道分别对应的M个缓存空间内的数据段，并分别发送至第一关联存储通道中的M个存储通道中，以使第一数据写入第一闪存介质。在该方案中，一个编码块(CW数据)存储至第一闪存介质，可以通过第一关联存储通道中的多个存储通道传输数据，因此为保证数据存储正确且有序存储，需要将数据对齐存储。在对齐存储时，缓存单元将一个CW数据(即第一数据)拆分为多个数据段，并分别存储在与第一关联存储通道中的M个存储通道分别对应的缓存空间内，以及通过对齐控制单元分别从第一关联存储通道中的多个存储通道，分别对应的缓存空间内依次取出第一数 据的各数据段，并发送至第一关联存储通道中相应的存储通道，从而实现数据的对齐存储。如此，可实现在通过多个存储通道向一个闪存介质存储数据时，保证数据的有序存储，在提高该存储芯片中的数据写入效率的情况下，提高该存储芯片的可靠性。
另一种可能的设计方案中，控制器可以包括缓存单元和对齐控制单元。其中，缓存单元可以包括多个缓存空间，多个缓存空间分别与存储芯片中的多个存储通道一一对应。在该存储芯片中，控制器可以用于通过第一关联存储通道从第一闪存介质读取数据。缓存单元，可以用于分别从第一关联存储通道中的M个存储通道获取第二数据，并分别缓存于第一关联存储通道中的M个存储通道分别对应的M个缓存空间内，并在接收到对齐控制单元发送的第一信息时发送解码数据。其中，第二数据为存储于第一闪存介质中的数据，解码数据为缓存单元已获取的第二数据。对齐控制单元，可以用于记录从第一关联存储通道已获取的第二数据的总长度，且当已获取的第二数据的总长度达到预设长度时，向缓存单元发送第一信息。其中，第一信息用于指示可对已获取的第二数据解码。在该方案中，从第一闪存介质中读取数据时，通过第一关联存储通道中的M个存储通道传输，且分别存储于第一关联存储通道中的M个存储通道对应的缓存空间内。具体地，以第一关联存储通道中包括存储通道CH0和存储通道CH1为例，若第二数据从存储通道CH0返回至缓存单元，则该第二数据缓存于存储通道CH0对应的缓存空间内；若第二数据从存储通道CH1返回至缓存单元，则该第二数据缓存于存储通道CH1对应的缓存空间内。如此，可使第二数据达到一个CW数据的大小时，能够顺利被解码，以完成数据的读取操作，从而提高该存储芯片的可靠性。
可选地，控制器还可以包括解码单元。缓存单元，还可以用于按照预设顺序，依次循环从第一关联存储通道中的M个存储通道分别对应的M个缓存空间内，获取固定长度的第二数据；并向解码单元发送固定长度的第二数据。在该可选方案中，解码单元用于对从第一闪存介质中读取的第二数据解码，在数据解码时，缓存单元有序从第一关联存储通道中的M个存储通道分别对应的M个缓存空间内，获取需解码的数据，并发送给解码单元解码，从而保证读取的数据的顺序正确，以便正确解码，从而提高该存储芯片的可靠性。
第二方面，本申请实施例提供一种存储设备。该存储设备包括多个闪存介质，以及如上第一方面中任一种可能的存储芯片；多个闪存介质通过存储芯片中的多个存储通道耦合至控制器。
第三方面，本申请实施例提供一种存储设备的访问方法。该存储设备包括存储芯片和多个闪存介质，其中存储芯片包括控制器以及与控制器耦合的多个存储通道，多个闪存介质通过多个存储通道耦合至控制器。该方法包括：控制器基于多个存储通道的数量以及通过多个存储通道耦合至控制器的闪存介质的数量，确定访问闪存介质的访问模式。若访问模式为宽口模式，则控制器将多个存储通道合并为第一通道，并通过第一通道访问闪存介质。其中，第一通道中包括至少一个关联存储通道，一个关联存储通道位宽为单个存储通道的N倍；N为大于或等于2的正整数。
可选地，若访问模式为正常模式，则控制器通过多个存储通道访问闪存介质。
可选地，与控制器耦合的多个存储通道的数量为X；通过多个存储通道耦合至控制器的闪存介质的数量为Y；X和Y均为正整数。若X>Y，则访问闪存介质的访问 模式为宽口模式。
进一步地，控制器通过所述第一通道访问所述闪存介质，可以包括：控制器通过第一关联存储通道访问第一闪存介质。其中，第一关联存储通道为第一通道中的一个关联存储通道。第一闪存介质为闪存介质中的一个闪存介质。第一关联存储通道中的存储通道的数量M满足如下关系：M＝(P/Q)*X；其中，P为第一闪存介质的介质容量；Q为通过多个存储通道耦合至控制器的闪存介质的总介质容量；X为与所述控制器耦合的多个存储通道的数量。
一种可能的设计方案中，控制器可以包括缓存单元和对齐控制单元；缓存单元可以包括多个缓存空间，多个缓存空间分别与存储芯片中的多个存储通道一一对应。控制器通过第一关联存储通道访问第一闪存介质，可以包括：控制器通过第一关联存储通道向第一闪存介质写入数据。缓存单元将第一数据拆分为多个数据段。缓存单元按照预设顺序，将第一数据的多个数据段依次循环存储在，第一关联存储通道中的M个存储通道分别对应的M个缓存空间内。对齐控制单元按照预设顺序，循环获取第一关联存储通道中的M个存储通道分别对应的M个缓存空间内的数据段，并分别发送至第一关联存储通道中的M个存储通道中，以使第一数据写入存储器的第一闪存介质。
另一种可能的设计方案中，控制器可以包括缓存单元和对齐控制单元，缓存单元可以包括X个缓存空间，X个缓存空间分别与存储芯片中的X个存储通道一一对应。控制器通过第一关联存储通道访问第一闪存介质，可以包括：控制器通过第一关联存储通道从第一闪存介质读取数据。缓存单元分别从第一关联存储通道中的M个存储通道获取第二数据，并分别缓存于第一关联存储通道中的M个存储通道，分别对应的M个缓存空间内；第二数据为存储于第一闪存介质中的数据。对齐控制单元记录从第一关联存储通道已获取的第二数据的总长度，且当已获取的第二数据的总长度达到预设长度时，向缓存单元发送第一信息。其中，第一信息用于指示可对已获取的所述第二数据解码。缓存单元接收到对齐控制单元的第一信息后，发送解码数据。其中，解码数据为所述缓存单元已获取的第二数据。
可选地，控制器还可以包括解码单元。缓存单元发送解码数据，可以包括：所述缓存单元按照预设顺序，依次循环从第一关联存储通道中的M个存储通道，分别对应的M个缓存空间内，获取固定长度的第二数据。缓存单元向解码单元发送固定长度的第二数据。
可以理解地，上述提供的任一种存储设备以及存储设备的访问方法等，均可以由上文第一方面所提供的存储芯片来实现或与上文第一方面提供的存储芯片相关联，因此，其所能达到的有益效果可参考上文所提供的存储芯片中的有益效果，此处不再赘述。
附图说明
图1为本申请实施例提供的一种存储芯片的系统架构示意图一；
图2为本申请实施例提供的一种存储芯片的系统架构示意图二；
图3为本申请实施例提供的存储设备的结构框图；
图4为本申请实施例提供的存储芯片中的缓存单元的数据存储格式示意图；
图5为本申请实施例提供的存储设备的访问方法的流程图；
图6为本申请实施例提供的存储设备写入数据时的交互流程图；
图7为本申请实施例提供的存储设备读取数据时的交互流程图。
具体实施方式
下面将结合附图，对本申请中的技术方案进行描述。
本申请中，“至少一个”是指一个或者多个，“多个”是指两个或两个以上。“和/或”，描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B的情况，其中A，B可以是单数或者复数。“以下至少一项(个)”或其类似表达，是指的这些项中的任意组合，包括单项(个)或复数项(个)的任意组合。例如，a，b或c中的至少一项(个)，可以表示：a，b，c，a-b，a-c，b-c或a-b-c，其中a、b和c可以是单个，也可以是多个。字符“/”一般表示前后关联对象是一种“或”的关系。另外，在本申请的实施例中，“第一”、“第二”等字样并不对数量和执行次序进行限定。
需要说明的是，本申请中，“示例性的”或者“例如”等词用于表示作例子、例证或说明。本申请中被描述为“示例性的”或者“例如”的任何实施例或设计方案不应被解释为比其他实施例或设计方案更优选或更具优势。确切而言，使用“示例性的”或者“例如”等词旨在以具体方式呈现相关概念。
图1为本申请实施例提供的一种存储芯片的系统架构示意图一。如图1所示，通用闪存存储(universal flash storage，UFS)的存储芯片，一般包括闪存(flash)控制器以及与闪存控制器相耦合的多个存储通道(channel)。其中，存储通道可以为闪存输入输出(flash input/output，flash IO)管脚。通常情况下，UFS中的闪存控制器一般会耦合4个及以上的存储通道，每个存储通道耦合一个闪存介质(flash die)(即介质颗粒)，用于该闪存介质的数据传输。在闪存控制器耦合的存储通道数量固定，且在存储器总容量不变的情况下，若单个闪存介质的存储容量增加，该闪存介质相对于更小容量的闪存介质而言，其能够使用的存储通道的数据线位宽的相对比例减小，如闪存介质的容量由64吉字节(gigabyte，GB)增加到128GB时，其能够使用的存储通道的数据线位宽仍然为8位。因此，在闪存介质的容量增加的情况下，可能造成该存储芯片的直接存储器访问(direct memory access，DMA)的访问性能下降，进而导致存储器的访问速率降低。此外，在存储器(或存储设备)总容量不变的情况下，若单个闪存介质的容量增加，则该存储器中的闪存介质的个数会相应减少，从而导致存储芯片内存在多余的存储通道，造成资源的浪费。
图2为本申请实施例提供的一种存储芯片的系统架构示意图二。由于在闪存控制器耦合的存储通道数量固定，且在存储器总容量不变的情况下，若单个闪存介质的存储容量增加，存储器中闪存介质个数减少而导致存储通道有剩余。请参考图2，在图2所示的存储芯片中，相比于图1所示的存储芯片，该存储芯片耦合的闪存介质的数量由4个变为了2个，因此在存储通道和闪存介质一一对应的情况下，该存储芯片中存在空闲的存储通道。在存储通道有空闲的情况下，可以将其中的至少两个存储通道合并为一个关联存储通道使用，即宽口模式，可以增加闪存介质可用的存储通道的数据 线位宽，提升存储芯片的读写性能，进而提升直接存储器访问(direct memory Access，DMA)带宽，提升存储器的访问速率。
应理解，本申请实施例中所述的宽口模式为在一个存储芯片中将至少两个存储通道合并为一个关联存储通道的使用场景。本申请实施例中所述的正常模式为在一个存储芯片中不合并存储通道的使用场景。在一个存储芯片(或存储设备)中是否使用宽口模式，是由使用该存储芯片中的存储通道的数量以及通过多个存储通道耦合至控制器的闪存介质的数量决定的。
具体地，若每个闪存介质的介质容量均相同，则可以按照如下方式确定(以图1所示的存储芯片为例)：
若闪存介质的数量≤存储通道的数量/2，则可以采用宽口模式，可将相邻的两个存储通道合并为一个存储通道。例如，假设图1中的闪存介质的数量由4个变为2个，则可将图1中的CH0和CH1合并为一个关联存储通道，CH2和CH3合并为一个关联存储通道，此时关联存储通道的数据线位宽可扩展为单个存储通道的2倍，即由原来的8位扩展至16位。
若闪存介质的数量≤存储通道的数量/4，则可以采用宽口模式，将4个存储通道合并为一个存储通道。例如，假设图1中的闪存介质的数量由4个变为1个，则可将图1中的CH0、CH1、CH2和CH3合并为一个关联存储通道，此时关联存储通道的可扩展为单个存储通道的数据线位宽的4倍，即由原来的8位扩展至32位。
应理解，若闪存介质的数量≥存储通道的数量，则不采用宽口模式，每个存储通道的数据线位宽保持8位不变。
此外，当每个闪存介质的介质容量不相同时，只需要存储通道的数量大于闪存介质的数量即可使用宽口模式。综合而言，在一个存储芯片中，假设存储通道的数量为X，通过多个存储通道耦合至控制器的闪存介质的数量为Y。若存储通道的数量大于闪存介质的数量，即X＞Y，则该存储器中访问闪存介质的访问模式可采用宽口模式，即可以对空闲的存储通道复用，使至少两个存储通道合并为一个关联存储通道。
需要说明的是，在存储通道合并时并不限于将相邻的存储通道合并，即也可以将不相邻的存储通道合并。通过宽口模式的应用，可以使一个存储器(或存储设备)在介质容量不变的情况下，若单个闪存介质的介质容量增加，使用原来的存储芯片(包括控制器以及与控制器耦合的多个存储通道)，依然能够保持原存储器的读写性能，从而降低成本。
图3为本申请实施例提供的存储设备的结构框图。请参考图3，本申请的实施例提供的存储设备包括多个闪存介质，以及如图1或图2所示的存储芯片；其中多个闪存介质通过存储芯片中的多个存储通道耦合至控制器。
根据图1和图2，本申请的实施例提供一种存储芯片，该存储芯片包括控制器以及与控制器耦合的多个存储通道；其中控制器可以为如图1或图2中的闪存控制器；存储通道可以为如图1或图2所示的CH0、CH1、CH2和CH3。控制器用于基于多个存储通道的数量以及通过多个存储通道耦合至控制器的闪存介质的数量，确定访问闪存介质的访问模式。若存储通道的数量大于闪存介质的数量，则访问闪存介质的访问模式可确定为宽口模式。
若访问闪存介质的访问模式为宽口模式，则控制器用于将多个存储通道合并为第一通道，并通过第一通道访问上述闪存介质。其中，第一通道中包括至少一个关联存储通道，一个关联存储通道位宽为单个存储通道的N倍，N为大于或等于2的正整数。
相应地，若访问闪存介质的访问模式为正常模式，即与控制器耦合的多个存储通道单独使用，不合并，则控制器用于通过原有的多个存储通道访问闪存介质。
需要说明的是，控制器用于基于多个存储通道的数量以及通过多个存储通道耦合至控制器的闪存介质的数量，确定访问闪存介质的访问模式，可以采用如下方式：
(1)根据存储芯片上配置的通用输入/输出(general purpose input/output，GPIO)管脚值确定。
在芯片封装时，可以知晓闪存介质的数量、每个闪存介质的型号以及介质容量，根据闪存介质的数量以及存储通道的数量，可以知晓是否可采用宽口模式访问该存储器；因此在芯片封装时，可以在UFS芯片的顶层预留GPIO管脚，用于对访问闪存介质的访问模式的选择与控制；如在基板上直接配置GPIO管脚的值，例如当GPIO为1时，表示该存储芯片可以使用宽口模式，可复用空闲的存储通道，将至少两个存储通道合并为一个存储通道使用，而提升存储通道的数据线位宽。
(2)根据识别得到的存储通道的数量和闪存介质的数量确定。
对于一些闪存介质的厂家可以支持宽口模式/正常模式的切换，闪存介质上电后的初始状态可以为正常模式，在初始化(如romcode)阶段可以扫描闪存介质厂家的ID，获取闪存介质的型号信息，推算出闪存介质的总介质容量，然后根据闪存介质的数量和存储通道的数量关系识别出是否需要切换为宽口模式。如果需要切换为宽口模式，则可以向闪存介质发送设置特性(set feature)指令，以修改访问闪存介质的访问模式为宽口模式；以及通过控制器将多个存储通道的部分或全部合并为一个或多个关联存储通道，实现存储通道数据线位宽的扩展。
控制器用于将多个存储通道合并为第一通道时，应确定第一通道中关联存储通道的数量、以及每个关联存储通道中的存储通道的数量，具体的确定方式如下：
示例性地，假设一个存储器中的存储总容量为1太字节(terabyte，TB)，存储器中的闪存控制器耦合的存储通道的数量为8个。在存储器使用相同容量的闪存介质的情况下，例如：若该存储器中采用的是容量为128GB的闪存介质(flash die)，则该存储器需要8个闪存介质，因此一个存储通道与闪存介质正好满足一一对应的关系。若该存储器中采用的是容量为256GB的闪存介质，则该存储器中需要4个闪存介质，按照一个存储通道服务一个闪存介质的规则，该存储器中有4个存储通道可能处于空闲状态，因此可将每两个存储通道合并为一个关联存储通道。相应地，若该存储器中采用的是容量为512GB的闪存介质，则该存储器中需要2个闪存介质，因此可将每四个存储通道合并为一个关联存储通道。
类似地，在存储器使用不同容量的闪存介质的情况下，例如：若该存储器采用的是4个128GB的闪存介质和1个512GB的闪存介质，则可以将其中的4个存储通道合并为一个关联存储通道供512GB的闪存介质使用。若该存储器采用的是2个128GB的闪存介质、1个256GB的闪存介质和1个512GB的闪存介质，则可以将其中的2个存储通道合并为一个关联存储通道供256GB的闪存介质使用，将其中的4个存储通道 合并为一个关联存储通道供512GB的闪存介质使用。
综上所述，若第一通道中包括第一关联存储通道，该第一关联存储通道可用于访问通过多个存储通道耦合至控制器的闪存介质中的第一闪存介质，即控制器可以用于通过第一关联存储通道访问第一闪存介质。第一关联存储通道中的存储通道的数量M可以按照如下关系确定：M＝(P/Q)*X；其中，P为第一闪存介质的介质容量；Q为通过多个存储通道耦合至控制器的闪存介质的总介质容量；X为与控制器耦合的多个存储通道的数量。
当访问闪存介质的访问模式为宽口模式，控制器用于将多个存储通道合并为第一通道时，以第一通道中包括第一关联存储通道为例，即控制器可以将多个存储通道中的M个存储通道合并为第一关联存储通道，具体可通过如下方式合并：
首先，在一个存储通道中，可以包括DQ、DQS、CE、ALE、CLE、WEN和RE输入输出管脚；其中CE为芯片使能(chip enable，CE)管脚，也可作片选管脚；ALE为地址锁存使能(address latch enable)管脚；CLE为命令锁存使能(command latch enable，CLE)管脚；DQ为数据输入输出(data input/output)管脚；DQS为双向数据控制(bi-directional data strobe，DQS)管脚；WEN为写使能(write enable，WEN)管脚；RE为读使能(read enable，RE)管脚。需要说明的是，ALE管脚为高电平时，可传输地址数据；CLE管脚为高电平时，可传输命令数据；当ALE、CLE均为低电平时，可传输数据。
在宽口模式下，即控制器确定访问闪存介质的访问模式为宽口模式时，请参考图3，每个存储通道均包括可编程时序生成器(program timing generate，PTG)和物理层，其中，可编程时序生成器PTG用于生成数据传输的时序，物理层用于数据传输，即DQ、DQS、CE、ALE、CLE、WEN和RE等输入输出管脚均耦合在存储通道的物理层上。假设控制器将存储通道CH0和存储通道CH1合并为第一关联存储通道(以CH0和CH1中的数据位宽均为8位为例)，则控制器控制CH1关闭CLE、ALE、WEN和CE这四个信号输入输出管脚的使能，仅使CH1上的DQS、DQ信号输入输出管脚使能，以便使CH1仅用于传输高8位或低8位的数据，如此便完成将CH0和CH1合并为关联存储通道，即第一关联存储通道。
示例性地，假设一个存储芯片中包括存储通道CH0、存储通道CH1、存储通道CH2、存储通道CH3至少4个存储通道。控制器将存储通道CH0、CH1、CH2和CH3四个通道合并为第一关联存储通道(以CH0、CH1、CH2和CH3的数据位宽均为8位为例)时，控制器控制CH1、CH2、CH3均关闭CLE、ALE、WEN和CE四个信号输入输出管脚的使能，仅使CH1、CH2和CH3上的DQS、DQ信号输入输出管脚使能，以便使CH1仅用于传输高第8-15位的数据，CH2仅用于传输第16-23位的数据，CH3仅用于传输第24-31位的数据，此时可认为完成了将CH0、CH1、CH2和CH3合并为第一关联存储通道的操作。
以上为控制器将多个存储通道中的M个存储通道合并为第一关联存储通道的具体方式。应理解，在第一通道中包括至少一个关联存储通道，因此其他关联存储通道的合并方式与第一关联存储通道的合并方式类似，此处不再赘述。
相应地，控制器通过第一通道访问闪存介质，可以包括控制器通过第一关联存储 通道访问第一闪存介质。也就是说，控制器将多个存储通道中的至少两个存储通道合并为第一关联存储通道后，即可通过第一关联存储通道访问第一闪存介质。下面，针对在宽口模式下，如何通过第一关联存储通道访问第一闪存介质进行说明。
在正常模式下，一个编码后的码字数据(code word，CW)只对应一个存储通道；然而在宽口模式下，一个编码后的CW数据则需要对应两个或两个以上的存储通道；因此，为了便于利用低密度奇偶校验码(low density parity check code，LDPC)解码，需要对数据对齐存储。为实现数据的对齐存储，控制器内设置有对齐控制单元。
根据图3，控制器可以包括编码单元(encoder)、解码单元(decoder)、码字数据缓存单元(code word buffer)、对齐控制单元(align controller)。其中，编码单元用于将待存储的数据编码为一个CW数据；解码单元用于对从闪存介质中读取的CW数据解码，以恢复数据；码字数据缓存单元(后文简称：缓存单元)用于缓存CW数据；对齐控制单元用于在宽口模式下实现CW数据的对齐和顺序的保持。
应理解，控制器确定访问闪存介质的访问模式，以及控制器将多个存储通道中的至少两个存储通道合并为第一关联存储通道的相关操作，均可以由控制器中的对齐控制单元来实现。
在该存储芯片的控制器中，缓存单元包括多个缓存空间，该缓存单元上的多个缓存空间分别与存储芯片中的多个存储通道一一对应。也就是说，在缓存单元上设置有多个缓存区域(即缓存空间)，每个缓存区域用于缓存存储芯片中的一个存储通道的传输数据。在宽口模式下，由于存储芯片中的两个或两个以上的存储通道合并为一个第一关联存储通道，用于访问第一闪存介质；因此一个编码后的CW数据则需要对应两个或两个以上的存储通道，即一个CW数据需要缓存在缓存单元上的两个或两个以上的缓存空间内，该两个或两个以上的缓存空间，分别与第一关联存储通道中的两个或两个以上的存储通道对应。
在一个存储芯片中，控制器通过第一关联存储通道访问第一闪存介质，可以包括写入操作和读取操作。即控制器可以用于通过第一关联存储通道向第一闪存介质写入数据；控制器也可以用于通过第一关联存储通道从第一闪存介质读取数据。
以下为控制器用于通过第一关联存储通道向第一闪存介质写入数据的说明。
控制器用于通过第一关联存储通道向第一闪存介质写入数据时，缓存单元用于将第一数据(即一个CW数据)拆分为多个数据段，且按照预设顺序，将第一数据的多个数据段依次循环存储在，第一关联存储通道中的M个存储通道分别对应的M个缓存空间内。
示例性地，图4为本申请实施例提供的存储芯片中的缓存单元的数据存储格式示意图。图4中示出了一个缓存单元中，分别对应存储通道CH0和CH1的两个缓存空间。若存储通道CH0和CH1合并为第一关联存储通道，则缓存单元将一个CW数据拆分为多个16位(bit)的数据段(以存储通道CH0和CH1的数据线位宽为8位为例)，即图4中的D0、D1、D2、D3、D4、D5……等16位的数据段。假设数据段的预设顺序为D0、D1、D2、D3、D4、D5……，因此在CW数据存储时，按照预设顺序，可以将数据段D0、D2、D4、D6、D8……存储于缓存单元中存储通道CH0对应的缓存空间内；将数据段D1、D3、D5、D7、D9……存储于缓存单元中存储通道CH1对应的 缓存空间内。
类似地，假设一个存储芯片中合并了CH0、CH1、CH2和CH3这四个存储通道，因此一个CW数据需对应存储通道CH0、CH1、CH2和CH3。在将CW数据缓存至缓存单元时，缓存单元依然会将一个CW数据拆分为多个16位的数据段(以每个存储通道的数据线位宽均为8位为例)，如D0、D1、D2、D3、D4、D5……等。假设数据的预设顺序为D0、D1、D2、D3、D4、D5……，因此在CW数据存储时，按照预设顺序，可以将数据段D0、D4、D8……存储于缓存单元中存储通道CH0对应的缓存空间内；将数据段D1、D5、D9……存储于缓存单元中存储通道CH1对应的缓存空间内；将数据段D2、D6、D10……存储于缓存单元中存储通道CH1对应的缓存空间内；将数据段D3、D7、D11……存储于缓存单元中存储通道CH1对应的缓存空间内。
应理解，一个CW数据被拆分后的各个数据段的长度与第一关联存储通道中的各个存储通道的数据线位宽有关。存储通道在传输数据时，在一个时钟周期内可在时钟周期的上升沿和下降沿分别传输不同的数据，即在一个时钟周期内，存储通道可传输的数据长度为该存储通道的数据线位宽的2倍。因此，在CW数据被拆分为多个数据段时，每个数据段的长度可以为对应的存储通道的数据线位宽的2倍，假设存储通道的数据线位宽为8位，则通过该存储通道传输的CW数据的一个数据段可以为16位。
相应地，假设第一关联存储通道的各个存储通道的数据线位宽不一致时，在一个CW数据被拆分时，可以将该CW数据拆分为长度不一致的多个数据段，每个数据段的长度由传输该数据段的存储通道的数据线位宽来决定。
控制器用于通过第一关联存储通道向第一闪存介质写入数据时，对齐控制单元用于按照预设顺序，循环获取第一关联存储通道中的M个存储通道分别对应的M个缓存空间内的数据段，并分别发送至第一关联存储通道中的M个存储通道中，以使第一数据写入第一闪存介质。
以图4示出的存储芯片中的缓存单元的数据存储格式为例，存储芯片中的控制器通过第一关联存储通道向第一闪存介质写入数据时，对齐控制单元交替从存储通道CH0和存储通道CH1对应的缓存空间内读取16位的数据段，并分别发送至存储通道CH0和存储通道CH1中，使相应的数据写入第一闪存介质中。也就是说，对齐控制单元依次从存储通道CH0对应的缓存空间内读取的D0、D2、D4……等数据段，并发送至存储通道CH0；对齐控制单元依次从存储通道CH1对应的缓存空间内读取的D1、D3、D5……等数据段，并发送至存储通道CH1。
类似地，假设第一关联存储通道中包括存储通道CH0、存储通道CH1、存储通道CH2以及存储通道CH3。存储芯片中的控制器通过第一关联存储通道向第一闪存介质写入数据时，按照预设顺序，对齐控制单元可以依次从存储通道CH0、存储通道CH1、存储通道CH2以及存储通道CH3对应的缓存空间内获取相应的数据段，并分别发送至存储通道CH0、存储通道CH1、存储通道CH2和存储通道CH3中，从而使相应的数据写入第一闪存介质中。也就是说，对齐控制单元依次从存储通道CH0对应的缓存空间内读取的D0、D4、D8……等数据段，并发送至存储通道CH0；对齐控制单元依次从存储通道CH1对应的缓存空间内读取的D1、D5、D9……等数据段，并发送至存储通道CH1；对齐控制单元依次从存储通道CH2对应的缓存空间内读取的D2、D6、 D10……等数据段，并发送至存储通道CH2；对齐控制单元依次从存储通道CH3对应的缓存空间内读取的D3、D7、D11……等数据段，并发送至存储通道CH3。
以下为控制器用于通过第一关联存储通道从第一闪存介质读取数据的说明。
控制器用于通过第一关联存储通道从第一闪存介质读取数据时，缓存单元用于分别从第一关联存储通道中的M个存储通道获取第二数据，并分别缓存于第一关联存储通道中的M个存储通道，分别对应的M个缓存空间内；第二数据为存储于第一闪存介质中的数据。
与控制器用于通过第一关联存储通道向第一闪存介质写入数据类似，假设第一关联存储通道中包括存储通道CH0和存储通道CH1，缓存单元通过存储通道CH0获取的数据存储于存储通道CH0对应的缓存空间内，缓存单元通过存储通道CH1获取的数据存储于存储通道CH1对应的缓存空间内。假设第一关联存储通道中包括存储通道CH0、存储通道CH1、存储通道CH2以及存储通道CH3，同理，缓存单元通过存储通道CH0获取的数据存储于存储通道CH0对应的缓存空间内，缓存单元通过存储通道CH1获取的数据存储于存储通道CH1对应的缓存空间内，缓存单元通过存储通道CH2获取的数据存储于存储通道CH2对应的缓存空间内，缓存单元通过存储通道CH3获取的数据存储于存储通道CH3对应的缓存空间内。
控制器用于通过第一关联存储通道从第一闪存介质读取数据时，对齐控制单元用于记录从第一关联存储通道已获取的第二数据的总长度，且在已获取的第二数据的总长度达到预设长度，向缓存单元发送第一信息。其中，第一信息用于指示可对已获取的第二数据解码。缓存单元还用于发送解码数据。其中，解码数据为缓存单元已获取的第二数据。也就是说，在缓存单元通过第一关联存储通道从第一闪存介质中获取数据时，对齐控制单元会记录从第一关联存储通道已获取的第二数据的总长度；若已获取的第二数据的总长度达到预设长度，例如达到一个CW数据的长度(4KB)，此时可通过解码单元对已获取的CW数据(即第二数据)解码，对齐控制单元通知缓存单元发送解码数据。如此，可使得第二数据达到一个CW数据的大小时，能够顺利被解码，以完成数据的读取操作，使得数据传输正确，从而提高该存储芯片的可靠性。
此外，缓存单元发送解码数据时，缓存单元还用于，按照预设顺序，依次循环从第一关联存储通道中的M个存储通道分别对应的M个缓存空间内，获取固定长度的第二数据；并发送固定长度的第二数据至解码单元。通过此种方式，可使得发送至解码单元的解码数据顺序正确，以便得到准确的数据，从而提高存储芯片的读写性能，在提高读写效率的情况下，保证数据传输的准确性，提高该存储芯片的可靠性。
以图4示出的存储芯片中的缓存单元的数据存储格式为例，缓存单元按照预设顺序，依次循环从第一关联存储通道中的两个存储通道(CH0和CH1)，分别对应的两个缓存空间内，获取固定长度的第二数据。固定长度的第二数据即每个存储通道单个时钟周期可传输的数据的长度(这里以16bit为例)，缓存单元先从存储通道CH0对应的缓存空间中读取数据D0、再从存储通道CH1对应的缓存空间中读取数据D1，又从存储通道CH0对应的缓存空间中读取数据D2，再从存储通道CH1对应的缓存空间中读取数据D3，依次循环。
类似地，若第一关联存储通道中包括四个存储通道(CH0、CH1、CH2和CH3)， 解码单元可以按照如下顺序读取：依次循环从存储通道CH0对应的缓存空间、存储通道CH1对应的缓存空间、存储通道CH2对应的缓存空间和存储通道CH3对应的缓存空间中读取数据D0、D1、D2、D3……等。
当读取完一个编码块的数据(即一个CW数据的长度)时，解码单元可以对接收到的第二数据解码，以完成数据的恢复。
以上为在宽口模式下，如何通过第一关联存储通道访问第一闪存介质的说明。区别于宽口模式，在正常模式下，请参考图3，每个存储通道均为独立状态，每个存储通道的输入输出管脚均为使能状态，即DQ、DQS、RE、CE、ALE、CLE、WEN管脚均使能。若在该存储芯片中采用正常模式读写数据时，第一闪存介质可通过存储通道CH0访问，第二闪存介质可通过存储通道CH1访问。该存储芯片中的控制器中的对齐控制单元可以仅用于指令分发，例如分发指令到对应的各存储通道，如存储通道CH0和CH1。
应理解，本申请实施例中仅说明了如何通过第一关联存储通道访问第一闪存介质，对于第一通道中的其他关联存储通道访问相对应的闪存介质与之类似，此处不再赘述。
请参考图5，本申请的实施例还提供一种存储设备的访问方法，，该存储设备包括存储芯片和多个闪存介质，其中存储芯片包括控制器以及与控制器耦合的多个存储通道，多个闪存介质通过多个存储通道耦合至控制器。
该方法包括如下步骤：
S501，控制器基于多个存储通道的数量以及通过多个存储通道耦合至控制器的闪存介质的数量，确定访问闪存介质的访问模式。
与控制器耦合的多个存储通道的数量为X；通过多个存储通道耦合至控制器的闪存介质的数量为Y；X和Y均为正整数。若X>Y，则访问闪存介质的访问模式为宽口模式。
在上述图3所示的存储芯片中说明了控制器如何确定访问闪存介质的访问模式，此处不再赘述。
S502，若访问闪存介质的访问模式为宽口模式，则控制器将多个存储通道合并为第一通道。
其中，第一通道中包括至少一个关联存储通道，一个关联存储通道的数据线位宽为单个存储通道的N倍；N为大于或等于2的正整数。
也就是说，控制器可以将全部的存储通道合并为一个或多个关联存储通道，如一个存储芯片中包括8个位宽为8位的存储通道，可以将8个存储通道两两合并，即合并为4个位宽均为16位的关联存储通道；也可以将部分的存储通道合并为一个或多个关联存储通道，如一个存储芯片中包括8个位宽为8位的存储通道，可以将8个存储通道的其中4个存储通道合并为一个32位的关联存储通道，其余不合并；或者将8个存储通道的其中4个存储通道两两合并，即合并为2个位宽均为16位的关联存储通道，其余不合并。
在上述图3所示的存储芯片中说明了如何将多个存储通道中的M个存储通道合并为第一关联存储通道，第一通道中包含的其他关联存储通道的合并方式与第一关联存储通道的合并方式类似，因此此处不再赘述。
S503，控制器通过第一通道访问闪存介质。
具体地，控制器通过第一通道访问闪存介质，可以包括：控制器通过第一关联存储通道访问第一闪存介质。其中，第一关联存储通道为第一通道中的一个关联存储通道。第一闪存介质为通过多个存储通道耦合至控制器的闪存介质中的其中一个闪存介质。第一关联存储通道中的存储通道的数量M满足如下关系：M＝(P/Q)*X；其中，P为第一闪存介质的介质容量；Q为通过多个存储通道耦合至控制器的闪存介质的总介质容量；X为与所述控制器耦合的多个存储通道的数量。
进一步地，控制器通过第一关联存储通道访问第一闪存介质，可以包括：控制器通过第一关联存储通道向第一闪存介质写入数据；和/或，控制器通过第一关联存储通道从第一闪存介质读取数据。
控制器包括编码单元(encoder)、解码单元(decoder)、缓存单元(code word buffer)、对齐控制单元(align controller)。其中，编码单元用于将待存储的数据编码为一个CW数据；解码单元用于对从闪存介质中读取的CW数据解码，以恢复数据；缓存单元用于缓存CW数据；对齐控制单元用于在宽口模式下实现CW数据的对齐和顺序保持。
图6示出了本申请实施例中的控制器通过第一关联存储通道向第一闪存介质写入数据的交互流程图。请参考图6，对于控制器通过第一关联存储通道向第一闪存介质写入数据，可以包括如下操作：
S601，编码单元向缓存单元发送第一数据。
具体地，编码单元完成CW数据编码后，可以向缓存单元发送CW数据(即第一数据)。
S602，缓存单元将第一数据拆分为多个数据段缓存于第一关联存储通道中的M个存储通道分别对应的M个缓存空间内。
具体地，缓存单元可以将接收到的第一数据(即一个CW数据)拆分为多个数据段后，并按照预设顺序，将第一数据的多个数据段依次循环存储在，第一关联存储通道中的M个存储通道分别对应的M个缓存空间内。其中，预设顺序可以按照存储通道的编号来确定。具体存储方式可参考上述图3所示的存储芯片关于缓存单元如何存储数据的相关描述，此处不再赘述。
S603，缓存单元通知对齐控制单元向第一闪存介质写入第一数据。
S604，对齐控制单元从缓存单元读取第一数据。
S605，对齐控制单元向第一关联存储通道发送CLE/ALE指令。
具体地，由于第一关联存储通道中仅有其中一个存储通道CLE、ALE信号输入输出管脚使能，因此对齐控制单元向CLE、ALE信号输入输出管脚使能的存储通道发送CLE/ALE指令即可。其中，该CLE/ALE指令用于指示写入第一闪存介质的第一数据的类型，即确定第一数据是地址、命令还是数据。
S606，第一关联存储通道返回CLE/ALE指令响应。
具体地，第一关联存储通道中的其中一个存储通道的可编程时序生成器(program timing generate，PTG)接收到CLE/ALE指令后，可以向对齐控制单元返回确认(acknowledgement，ACK)指示。
S607，第一关联存储通道向第一闪存介质输出CLE/ALE时序。
具体地，待对齐控制单元返回ACK后，第一关联存储通道中的其中一个存储通道中的可编程时序生成器PTG，向第一闪存介质输出CLE/ALE时序，以便确定传输的第一数据时地址、命令还是数据。
S608，对齐控制单元向第一关联存储通道输出直接存储器访问写操作(write DMA)指令，并向第一关联存储通道传输第一数据。
具体地，步骤S604中对齐控制单元读取数据，以及S608中对齐控制单元向第一存储通道传输数据可以采用如下方式，对齐控制单元按照预设顺序，循环获取第一关联存储通道中的M个存储通道分别对应的M个缓存空间内的数据段，并分别发送至第一关联存储通道中的M个存储通道中，以使第一数据写入存储器的第一闪存介质。以第一关联存储通道包括两个存储通道(CH0和CH1)为例，对齐控制单元将从CH0和CH1对应的缓存空间内读取的第一数据，转串为16位的数据交替输出至CH0和CH1，使该第一数据写入第一闪存介质。具体方式可参考图3所示的存储芯片中，关于对齐控制单元通过第一关联存储通道向第一闪存介质写入第一数据的相关内容，此处不再赘述。
S609，第一关联存储通道向第一闪存介质输出DMA写操作时序，并传输第一数据。
第一关联存储通道中的PTG向第一闪存介质输出直接存储器访问写操作的时序，并传输第一数据。
具体地，第一关联存储通道向第一闪存介质写入第一数据时，先通过第一关联存储通道中各存储通道的PTG向第一闪存介质输出DMA写操作的时序，以便传输第一数据。在生成DMA写操作的时序后，第一关联存储通道中的各存储通道即可向第一闪存介质传输第一数据，以使第一数据写入第一闪存介质。
图7示出了本申请实施例中的控制器通过第一关联存储通道向第一闪存介质写入数据的交互流程图。请参考图7，对于控制器通过第一关联存储通道向第一闪存介质写入数据，可以具有如下操作：
S701，对齐控制单元向第一关联存储通道发送CLE/ALE指令。
具体地，由于第一关联存储通道中仅有其中一个存储通道CLE、ALE信号输入输出管脚使能，因此对齐控制单元向CLE、ALE信号输入输出管脚使能的存储通道发送CLE/ALE指令即可。该CLE/ALE指令用于指示从第一闪存介质读取的第二数据的类型，即确定第二数据是地址、命令还是数据。
S702，第一关联存储通道返回CLE/ALE指令的响应。
具体地，第一关联存储通道中的其中一个存储通道的可编程时序生成器(program timing generate，PTG)接收到CLE/ALE指令后，会向对齐控制单元返回确认(acknowledgement，ACK)。
S703，第一关联存储通道向第一闪存介质输出CLE/ALE时序。
具体地，待对齐控制单元返回ACK后，第一关联存储通道中的其中一个存储通道中的可编程时序生成器PTG，向第一闪存介质输出CLE/ALE时序，以便确定传输的第二数据时地址、命令还是数据。
S704，对齐控制单元向第一关联存储通道发送直接存储器访问读操作(read DMA) 指令。
S705，第一关联存储通道向第一闪存介质输出DMA读操作时序。
S706，第一闪存介质向缓存单元返回第二数据。
具体地，第一闪存介质返回第二数据时，通过第一关联存储通道中的M个存储通道返回。缓存单元分别从第一关联存储通道中的M个存储通道获取第二数据，并分别缓存于第一关联存储通道中的M个存储通道，分别对应的M个缓存空间内。
S707，对齐控制单元记录已返回的第二数据的总长度，且当已获取的第二数据的总长度达到预设长度时，向缓存单元发送第一信息。
其中，第一信息用于指示可对已获取的第二数据解码。在缓存单元通过第一关联存储通道从第一闪存介质中获取数据时，对齐控制单元会记录从第一关联存储通道已获取的第二数据的总长度；若已获取的第二数据的总长度达到预设长度，例如达到一个CW数据的长度(4KB)，此时可通过解码单元对已获取的CW数据(即第二数据)解码，对齐控制单元通知缓存单元发送解码数据(即发送第一信息)。如此，可使得第二数据达到一个CW数据的大小时，能够顺利被解码，以完成数据的读取操作，使得数据传输正确，从而提高该存储芯片的可靠性。
S708，缓存单元向解码单元发送解码数据。
其中解码数据为缓存单元已获取的第二数据。缓存单元向解码单元发送解码数据，包括：所述缓存单元按照预设顺序，依次循环从第一关联存储通道中的M个存储通道，分别对应的M个缓存空间内，获取固定长度的第二数据。缓存单元发送固定长度的第二数据至解码单元。缓存单元如何从缓存空间内获取固定长度的第二数据可参考图3所示的存储芯片中，关于缓存单元获取固定长度的第二数据的相关描述，此处不再赘述。当读取完一个编码块的数据(即一个CW数据的长度)时，解码单元对接收到的第二数据解码，完成数据的恢复。
应理解，本申请实施例中仅说明了如何通过第一关联存储通道访问第一闪存介质，对于第一通道中的其他关联存储通道访问相对应的闪存介质与之类似，此处不再赘述。
表1
Figure PCTCN2020132076-appb-000001
针对一个存储设备，其DMA读写性能与接口频率和数据线位宽有关，即DMA读写性能＝频率*位宽，因此在接口频率不变的情况下，提升数据线位宽可以提高DMA的读写性能。在本申请提供的实施例中，可通过复用空闲的存储通道来提高数据线位宽，使得DMA读写性能增加。具体可参考表1，在表1中示出了一个存储设备中，在总存储容量不变的情况下，单个闪存介质的存储容量增加后，减少闪存介质的数量，使每个闪存介质复用空闲的存储通道。在传输页面大小为18千字节(kilobyte，KB)的数 据时，将存储通道数据线位宽由8位扩展为16位后的读取性能有明显的提高。
应理解，在本申请的各种实施例中，上述各过程的序号的大小并不意味着执行顺序的先后，各过程的执行顺序应以其功能和内在逻辑确定，而不应对本申请实施例的实施过程构成任何限定。
本领域普通技术人员可以意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，能够以电子硬件、或者计算机软件和电子硬件的结合来实现。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本申请的范围。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的系统、装置和单元的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
在本申请所提供的几个实施例中，应该理解到，所揭露的系统、装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本申请各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (15)

  1. 一种存储芯片，其特征在于，包括：控制器以及与所述控制器耦合的多个存储通道；
    所述控制器，用于基于所述多个存储通道的数量以及通过所述多个存储通道耦合至所述控制器的闪存介质的数量，确定访问所述闪存介质的访问模式；
    所述控制器，还用于若所述访问模式为宽口模式，则将所述多个存储通道合并为第一通道；其中，所述第一通道中包括至少一个关联存储通道，所述关联存储通道的数据线位宽为单个存储通道的N倍，N为大于或等于2的正整数；
    所述控制器，还用于通过所述第一通道访问所述闪存介质。
  2. 根据权利要求1所述的存储芯片，其特征在于，与所述控制器耦合的多个存储通道的数量为X；通过所述多个存储通道耦合至所述控制器的闪存介质的数量为Y；X和Y均为正整数；
    若X>Y，则所述访问模式为宽口模式。
  3. 根据权利要求1或2所述的存储芯片，其特征在于，所述控制器，还用于若所述访问模式为正常模式，则通过所述多个存储通道访问所述闪存介质。
  4. 根据权利要求1至3任一项所述的存储芯片，其特征在于，所述控制器，还用于通过第一关联存储通道访问第一闪存介质；其中，所述第一关联存储通道为所述第一通道中的一个关联存储通道；所述第一闪存介质为所述闪存介质中的一个闪存介质；
    所述第一关联存储通道中的存储通道的数量M满足如下关系：
    M＝(P/Q)*X；
    其中，P为所述第一闪存介质的介质容量；Q为通过所述多个存储通道耦合至所述控制器的闪存介质的总介质容量；X为与所述控制器耦合的多个存储通道的数量。
  5. 根据权利要求4所述的存储芯片，其特征在于，所述控制器包括缓存单元和对齐控制单元；所述缓存单元包括多个缓存空间，所述多个缓存空间分别与所述存储芯片中的多个存储通道一一对应；
    所述控制器，用于通过所述第一关联存储通道向所述第一闪存介质写入数据；
    所述缓存单元，用于将第一数据拆分为多个数据段，且按照预设顺序，将所述第一数据的多个数据段依次循环存储在，所述第一关联存储通道中的M个存储通道分别对应的M个所述缓存空间内；
    所述对齐控制单元，用于按照预设顺序，循环获取所述第一关联存储通道中的M个存储通道分别对应的M个所述缓存空间内的数据段，并分别发送至所述第一关联存储通道中的M个存储通道中，以使所述第一数据写入所述第一闪存介质。
  6. 根据权利要求4所述的存储芯片，其特征在于，所述控制器包括缓存单元和对齐控制单元，所述缓存单元包括多个缓存空间，所述多个缓存空间分别与所述存储芯片中的多个存储通道一一对应；
    所述控制器，用于通过所述第一关联存储通道从所述第一闪存介质读取数据；
    所述缓存单元，用于分别从所述第一关联存储通道中的M个存储通道获取第二数据，并分别缓存于所述第一关联存储通道中的M个存储通道，分别对应的M个所述 缓存空间内；其中，所述第二数据为存储于所述第一闪存介质中的数据；
    所述对齐控制单元，用于记录从所述第一关联存储通道已获取的所述第二数据的总长度，且当已获取的所述第二数据的总长度达到预设长度时，向所述缓存单元发送第一信息；其中，所述第一信息用于指示可对已获取的所述第二数据解码；
    所述缓存单元，还用于发送解码数据；所述解码数据为所述缓存单元已获取的第二数据。
  7. 根据权利要求6所述的存储芯片，其特征在于，所述控制器还包括解码单元；
    所述缓存单元还用于，按照预设顺序，依次循环从所述第一关联存储通道中的M个存储通道分别对应的M个缓存空间内，获取固定长度的所述第二数据；并向所述解码单元发送固定长度的所述第二数据。
  8. 一种存储设备，其特征在于，包括多个闪存介质，以及如权利要求1至6任一项所述的存储芯片；所述多个闪存介质通过所述存储芯片中的多个存储通道耦合至所述控制器。
  9. 一种存储设备的访问方法，其特征在于，所述存储设备包括存储芯片和多个闪存介质，所述存储芯片包括控制器以及与控制器耦合的多个存储通道，所述多个闪存介质通过所述多个存储通道耦合至所述控制器；
    所述方法包括：
    所述控制器基于所述多个存储通道的数量以及通过所述多个存储通道耦合至所述控制器的闪存介质的数量，确定访问所述闪存介质的访问模式；
    若所述访问模式为宽口模式，则所述控制器将所述多个存储通道合并为第一通道；其中，所述第一通道中包括至少一个关联存储通道，一个所述关联存储通道的数据线位宽为单个存储通道的N倍；N为大于或等于2的正整数；
    所述控制器通过所述第一通道访问所述闪存介质。
  10. 根据权利要求9所述的方法，其特征在于，与所述控制器耦合的多个存储通道的数量为X；通过所述多个存储通道耦合至所述控制器的闪存介质的数量为Y；X和Y均为正整数；
    若X>Y，则所述访问模式为宽口模式。
  11. 根据权利要求9或10所述的方法，其特征在于，若所述访问模式为正常模式，则所述控制器通过所述多个存储通道访问所述闪存介质。
  12. 根据权利要求9至11任一项所述的方法，其特征在于，所述控制器通过所述第一通道访问所述闪存介质，包括：
    所述控制器通过第一关联存储通道访问第一闪存介质；其中，所述第一关联存储通道为所述第一通道中的一个关联存储通道；所述第一闪存介质为所述闪存介质中的一个闪存介质；
    所述第一关联存储通道中的存储通道的数量M满足如下关系：
    M＝(P/Q)*X；其中，P为所述第一闪存介质的介质容量；Q为通过所述多个存储通道耦合至所述控制器的闪存介质的总介质容量；X为与所述控制器耦合的多个存储通道的数量。
  13. 根据权利要求12所述的方法，其特征在于，所述控制器包括缓存单元和对齐 控制单元；所述缓存单元包括多个缓存空间，所述多个缓存空间分别与所述存储芯片中的多个存储通道一一对应；
    所述控制器通过第一关联存储通道访问第一闪存介质，包括：
    所述控制器通过所述第一关联存储通道向所述第一闪存介质写入数据；
    所述缓存单元将第一数据拆分为多个数据段；
    所述缓存单元按照预设顺序，将第一数据的多个数据段依次循环存储在，所述第一关联存储通道中的M个存储通道分别对应的M个所述缓存空间内；
    所述对齐控制单元按照预设顺序，循环获取所述第一关联存储通道中的M个存储通道分别对应的M个所述缓存空间内的数据段，并分别发送至所述第一关联存储通道中的M个存储通道中，以使所述第一数据写入所述第一闪存介质。
  14. 根据权利要求12所述的方法，其特征在于，所述控制器包括缓存单元、对齐控制单元，所述缓存单元包括多个缓存空间，所述多个缓存空间分别与所述存储芯片中的多个存储通道一一对应；
    所述控制器通过第一关联存储通道访问第一闪存介质，包括：
    所述控制器通过所述第一关联存储通道从所述第一闪存介质读取数据；
    所述缓存单元分别从所述第一关联存储通道中的M个存储通道获取第二数据，并分别缓存于所述第一关联存储通道中的M个存储通道，分别对应的M个所述缓存空间内；所述第二数据为存储于所述第一闪存介质中的数据；
    所述对齐控制单元记录从所述第一关联存储通道已获取的所述第二数据的总长度，且当已获取的所述第二数据的总长度达到预设长度时，向所述缓存单元发送第一信息；所述第一信息用于指示可对已获取的所述第二数据解码；
    所述缓存单元发送解码数据；所述解码数据为所述缓存单元已获取的第二数据。
  15. 根据权利要求14所述的方法，其特征在于，所述控制器还包括解码单元；所述缓存单元发送解码数据，包括：
    所述缓存单元按照预设顺序，依次循环从所述第一关联存储通道中的M个存储通道分别对应的M个缓存空间内，获取固定长度的所述第二数据；
    所述缓存单元向解码单元发送固定长度的所述第二数据。
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