WO2022109973A1

WO2022109973A1 - Manufacturing method for phase change memory, and phase change memory

Info

Publication number: WO2022109973A1
Application number: PCT/CN2020/132064
Authority: WO
Inventors: 廖昱程
Original assignee: 江苏时代全芯存储科技股份有限公司; 江苏时代芯存半导体有限公司
Priority date: 2020-11-27
Filing date: 2020-11-27
Publication date: 2022-06-02
Also published as: CN115443537A

Abstract

Provided are a manufacturing method for a phase change memory, and a phase change memory. The phase change memory comprises: a substrate having an N-type semiconductor surface; a stacked structure, wherein the stacked structure is columnar, and comprises a patterned N-type semiconductor layer, a P-type semiconductor layer, a heater, and a columnar thermal insulation layer enclosing the heater; a phase change material layer located above the stacked structure; a dielectric layer covering the stacked structure and the phase change material layer; an interlayer dielectric layer filled in gaps between the above structures to cover the substrate, the dielectric layer, the stacked structure, and the phase change material layer; and an electrical connection structure. In the present invention, the phase change memory structure combining a diode has the advantages of a low current, good heating efficiency, a low operating voltage, high density, simple manufacturing process and operations and the like, thereby exhibiting improved performance over conventional memories.

Description

Phase change memory preparation method and phase change memory

technical field

The invention relates to the field of semiconductors, and in particular, to a preparation method of a phase change memory and a phase change memory.

Background technique

The traditional 1T1R structure fabricated using transistors has the disadvantages of low density, complicated operation, complicated fabrication process, and high operating voltage. The use of diodes to prepare 1D1R structures has the advantages of lower reset current, good heating efficiency, and low operating voltage. The three-dimensional structural design of diodes with phase-change memory structures can improve the density of 1D1R structures and solve the above problems.

SUMMARY OF THE INVENTION

The technical problem to be solved by the present invention is to provide a preparation method of a phase change memory and a phase change memory, which solve the shortcomings of traditional memory such as low density, complicated operation, complicated preparation process, and high operating voltage.

In order to solve the above problems, the present invention provides a preparation method of a phase change memory, which is characterized by comprising: providing a substrate with a surface of an N-type semiconductor layer; forming a P-type semiconductor layer, wherein the P-type semiconductor layer is located in the above the substrate; forming a patterned thermal insulation layer, the thermal insulation layer is located above the P-type semiconductor layer and is distributed with column-shaped through holes to expose the P-type semiconductor layer; in the column-shaped through holes depositing a heater; patterning the heat insulating layer, the P-type semiconductor layer, and part of the N-type semiconductor layer to form a stacked structure; and forming a phase-change material layer over the stacked structure.

In order to solve the above problems, the present invention also provides a phase change memory. The phase change memory includes: a substrate with an N-type semiconductor surface; a stacked structure, the stacked structure is columnar, including a patterned N-type semiconductor layer, a P-type semiconductor layer, a heater and a wrapping heater a columnar thermal insulation layer; a phase change material layer, the phase change material layer is located above the laminated structure; a dielectric layer, the dielectric layer covers the laminated structure and the phase change material layer; The interlayer dielectric layer is filled in the void of the above structure to cover the substrate, the dielectric layer, the laminated structure, and the phase change material layer; and the electrical connection structure.

The invention adopts a diode with a phase-change memory structure, and has the advantages of low current, good heating efficiency, low working voltage, high density, simple preparation process and operation, etc., and improves the performance of traditional memory.

Description of drawings

FIG. 1 is a schematic diagram of the steps described in a specific embodiment of the present invention.

2A-2F are schematic diagrams of the processes of steps S10-S15 in FIG. 1 .

FIG. 3 is a schematic diagram showing the steps of forming the structure shown in FIG. 2A according to an embodiment of the present invention.

4A-4E are schematic diagrams of the processes in steps S30-S33 of FIG. 3 .

FIG. 5 is a schematic diagram showing the steps after the formation of the phase change material layer according to an embodiment of the present invention.

6A-6C are schematic diagrams of the processes of steps S51-S53 in FIG. 5 .

FIG. 7 shows two views of the word line direction and the bit line direction according to an embodiment of the present invention.

Detailed ways

The method for preparing a change memory and the specific implementation of the phase change memory provided by the present invention will be described in detail below with reference to the accompanying drawings.

1 is a schematic diagram of the steps described in a specific embodiment of the present invention, including:

Step S10, providing a substrate with an N-type semiconductor layer surface; Step S11, forming a P-type semiconductor layer, the P-type semiconductor layer is located above the substrate; Step S12, forming a patterned thermal insulation layer, so The heat insulating layer is located above the P-type semiconductor layer and is distributed with column-shaped through holes to expose the P-type semiconductor layer; step S13 , depositing a heater in the column-shaped through holes; step S14 , patterning the spacer The thermal layer, the P-type semiconductor layer, and part of the N-type semiconductor layer form a stacked structure; in step S15, a phase change material layer is formed on the stacked structure.

As shown in FIG. 2A , referring to step S10 , a substrate 20 having a surface of an N-type semiconductor layer 201 is provided.

In a specific embodiment of the present invention, the formation of the above structure can be carried out by the following methods, and referring to FIG. 3 is a schematic diagram of the implementation of the following steps: Step S30, providing an SOI wafer, the SOI wafer includes N Step S31, forming a P-type isolation layer in the N-type top silicon layer; Step S32, forming a dielectric isolation structure; Step S33, forming an N-type semiconductor layer in the P-type isolation layer .

As shown in FIG. 4A , referring to step S30 , an SOI wafer is provided, the SOI wafer includes an N-type top layer silicon 43 and a buried oxide layer 42 , and the supporting substrate 41 is located under the buried oxide layer 42 . In a specific embodiment, the material of the supporting substrate 41 is single crystal silicon; the N-type top layer silicon 43 is formed by ion implantation.

As shown in FIG. 4B , referring to step S31 , a P-type isolation layer 44 is formed over the N-type top layer silicon 43 . In a specific embodiment, the P-type isolation layer 44 is formed by ion implantation.

As shown in FIG. 4C , referring to step S32 , a dielectric isolation structure 45 is formed. In a specific embodiment, the dielectric isolation structure 45 is a shallow trench structure (STI), using SiO ₂ material to form the isolation region and the active region.

As shown in FIG. 4D , referring to step S33 , an N-type semiconductor layer 201 is formed in the P-type isolation layer 44 . In a specific embodiment, the N-type semiconductor layer 201 is formed by ion implantation.

As shown in FIG. 4E , in a specific embodiment, an N-type heavily doped layer 202 is provided on the surface of the N-type semiconductor layer 201 , and this step is an optional step. The N-type heavily doped layer 202 can improve the conductivity of the interface.

After the above steps are completed, the structure shown in FIG. 2A is obtained. On this basis, the following steps are continued.

As shown in FIG. 2B , referring to step S11 , a P-type semiconductor layer 203 is formed, and the P-type semiconductor layer 203 is located above the substrate 20 . The threshold voltage of the PN diode can be adjusted by the P ion concentration or the thickness of the P-type semiconductor layer 203 . In a specific embodiment, there is a P-type heavily doped layer 204 on the surface of the P-type semiconductor layer 203, and this step is an optional step. The P-type heavily doped layer 204 can improve the conductivity of the interface.

As shown in FIG. 2C , referring to step S12 , a patterned heat insulating layer 205 is formed. The heat insulating layer 205 is located above the P-type semiconductor layer 203 and is distributed with columnar vias to expose the P-type semiconductor layer. 203. In a specific embodiment, the thermal insulation layer 205 is made of TaN material, which can reduce thermal conductivity and improve thermal efficiency.

As shown in FIG. 2D, referring to step S13, a heater 206 is deposited in the columnar through hole. In a specific embodiment, the heater 206 is made of TiN material.

As shown in FIG. 2E , referring to step S14 , the heat insulating layer 205 , the P-type semiconductor layer 203 , and part of the N-type semiconductor layer 201 are patterned to form a stacked structure 21 , and the stacked structure 21 is columnar and includes a pattern The doped N-type semiconductor layer 201, the P-type semiconductor layer 203, the heater 206, and the columnar heat insulating layer 205 wrapping the heater.

As shown in FIG. 2F , referring to step S15 , a phase change material layer 207 is formed above the stacked structure 21 . In a specific embodiment, the phase change material layer adopts GST material.

FIG. 5 is a schematic diagram of the steps after the formation of the phase change material layer according to an embodiment of the present invention, including:

Step S51, forming a dielectric layer, the dielectric layer covering the laminated structure and the phase change material layer; Step S52, depositing an interlayer dielectric layer to cover the dielectric layer, the laminated structure, and the phase change material layer; step S53, forming an electrical connection structure.

As shown in FIG. 6A , referring to step S51 , a dielectric layer is formed, and the dielectric layer covers the laminated structure and the phase change material layer. In a specific embodiment, the dielectric layer is made of SiN material, which can reduce thermal conductivity and improve heating efficiency.

As shown in FIG. 6B , referring to step S52 , an interlayer dielectric layer is deposited to cover the dielectric layer, the laminated structure, and the phase change material layer. In a specific embodiment, the interlayer dielectric layer is made of SiO ₂ material.

As shown in FIG. 6C , referring to step S53 , an electrical connection structure is formed. The electrical connection structure is connected by conductive materials, including: a first connection structure 210 for connecting bit lines, a second connection structure 211 for connecting the phase change material layer 207 and the first connection structure 210, and a second connection structure for connecting word lines. Three connection structures 212 and a fourth connection structure 213 connecting the N-type semiconductor layer 201 and the third connection structure 212 . In a specific embodiment, the first connection structure 210 and the third connection structure 212 are made of low-resistance materials such as Cu and Al, and the second connection structure 211 and the fourth connection structure 213 are prepared by filling with W.

FIG. 6C is a schematic structural diagram of a specific implementation of the phase change memory obtained after the above steps are completed, including:

A substrate 20 having a surface of an N-type semiconductor layer 201; a stacked structure 21, the stacked structure 21 is columnar, including a patterned N-type semiconductor layer 201, a P-type semiconductor layer 203, a heater 206, and a package heating a columnar thermal insulation layer 205 of the device; a phase change material layer 207, the phase change material layer 207 is located above the laminated structure 21; a dielectric layer 208, the dielectric layer covers the laminated structure 21 and the phase change material layer 207; an interlayer dielectric layer 209, the interlayer dielectric layer 209 is filled in the voids of the above structure to cover the substrate 20, the dielectric layer 208, the laminated structure 21, and the phase change material layer 207; and Electrical connection structure 210 . The electrical connection structure is connected by conductive materials, including: a first connection structure 210 for connecting bit lines, a second connection structure 211 for connecting the phase change material layer 207 and the first connection structure 210, and a second connection structure for connecting word lines. Three connection structures 212 and a fourth connection structure 213 connecting the N-type semiconductor layer 201 and the third connection structure 212 . In a specific embodiment, the first connection structure 210 and the third connection structure 212 are made of low-resistance materials such as Cu and Al, and the second connection structure 211 and the fourth connection structure 213 are prepared by filling with W.

The above technical solution adopts a diode with a phase-change memory structure, and has the advantages of low current, good heating efficiency, low operating voltage, high density, simple preparation process and operation, etc., and improves the performance of traditional memory.

The above are only the preferred embodiments of the present invention. It should be pointed out that for those skilled in the art, without departing from the principles of the present invention, several improvements and modifications can also be made, and these improvements and modifications should also be regarded as It is the protection scope of the present invention.

Claims

A method for preparing a phase change memory, comprising:

providing a substrate with an N-type semiconductor layer surface;

forming a P-type semiconductor layer, the P-type semiconductor layer is located above the substrate;

forming a patterned thermal insulation layer, the thermal insulation layer is located above the P-type semiconductor layer and is distributed with columnar through holes to expose the P-type semiconductor layer;

depositing a heater in the columnar via;

patterning the heat insulating layer, the P-type semiconductor layer, and part of the N-type semiconductor layer to form a stacked structure;

A phase change material layer is formed over the stacked structure.
The method according to claim 1, wherein the preparation method of the substrate is further:

providing an SOI wafer, the SOI wafer includes an N-type top layer silicon and a buried oxide layer;

forming a P-type isolation layer within the N-type top layer silicon;

form a dielectric isolation structure;

An N-type semiconductor layer is formed within the P-type isolation layer.
The method of claim 1, wherein the surface of the N-type semiconductor layer has an N-type heavily doped layer.
The method according to claim 1, wherein the surface of the P-type semiconductor layer has a P-type heavily doped layer.
The method of claim 1, wherein the heat insulating layer is made of TaN material, the heater is made of TiN material, the dielectric layer is made of SiN material, and the phase change material layer is made of GST material.
The method according to claim 1, wherein the stacked structure is columnar, comprising a patterned N-type semiconductor layer, a P-type semiconductor layer, a heater, and a columnar thermal insulation layer wrapping the heater.
The method of claim 1, wherein the step after the phase change material layer is formed comprises:

forming a dielectric layer covering the laminated structure and the phase change material layer;

depositing an interlayer dielectric layer to encapsulate the dielectric layer, the stack structure, and the phase change material layer;

An electrical connection structure is formed.
A phase change memory, characterized in that, comprising:

a substrate having an N-type semiconductor surface;

a stacked structure, the stacked structure is columnar, comprising a patterned N-type semiconductor layer, a P-type semiconductor layer, a heater, and a columnar thermal insulation layer wrapping the heater;

a phase change material layer, the phase change material layer is located above the laminated structure;

a dielectric layer covering the laminated structure and the phase change material layer;

an interlayer dielectric layer, the interlayer dielectric layer is filled in the void of the above-mentioned structure to cover the substrate, the dielectric layer, the laminated structure, and the phase change material layer; and

Electrical connection structure.
The structure according to claim 8, wherein the substrate is prepared by using an SOI wafer.
The structure of claim 8, wherein an N-type heavily doped layer exists on the surface of the N-type semiconductor layer, and a P-type heavily doped layer exists on the surface of the P-type semiconductor layer.