WO2022109873A1 - 时序裕量确定方法、装置、测试电路系统及可读存储介质 - Google Patents

时序裕量确定方法、装置、测试电路系统及可读存储介质 Download PDF

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WO2022109873A1
WO2022109873A1 PCT/CN2020/131484 CN2020131484W WO2022109873A1 WO 2022109873 A1 WO2022109873 A1 WO 2022109873A1 CN 2020131484 W CN2020131484 W CN 2020131484W WO 2022109873 A1 WO2022109873 A1 WO 2022109873A1
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link
timing
circuit
tested
test
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PCT/CN2020/131484
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English (en)
French (fr)
Inventor
冯鲲鹏
欧宇
刘其龙
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深圳市大疆创新科技有限公司
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Priority to PCT/CN2020/131484 priority Critical patent/WO2022109873A1/zh
Publication of WO2022109873A1 publication Critical patent/WO2022109873A1/zh

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer

Definitions

  • the present invention belongs to the field of network technology, and in particular, relates to a timing margin determination method, device, test circuit system and readable storage medium.
  • timing margin is often directly set higher. In this way, the accuracy of the timing slack will be lower, and the resulting chip will have a larger area and higher power consumption.
  • the present invention provides a timing margin determination method, device, test circuit system and readable storage medium, so as to solve the problem of low accuracy of timing margin, which leads to larger area and higher power consumption of the finally generated chip .
  • an embodiment of the present invention provides a timing margin determination method, which is applied to a test circuit system, where the test circuit system includes a first analog circuit and a delay introduction circuit, and the first analog circuit is used to simulate The circuit in the first chip to be tested, the delay introduction circuit is used to introduce a timing delay for the first analog circuit, and the method includes:
  • a target timing margin of the current link under test is determined.
  • an embodiment of the present invention provides an apparatus for determining a timing margin, which is applied to a test circuit system, where the test circuit system includes a first analog circuit and a delay introduction circuit, and the first analog circuit is used to simulate A circuit in the first chip to be tested, the delay introduction circuit is used to introduce a timing delay for the first analog circuit, and the device includes a memory and a processor;
  • the memory for storing program codes
  • the processor calls the program code, and when the program code is executed, is configured to perform the following operations:
  • the current link under test is adjusted, and/or, based on the delay introduction circuit, a timing delay is introduced for the current link under test, so that timing violation occurs in the first analog circuit;
  • a target timing margin of the current link under test is determined.
  • an embodiment of the present invention provides a test circuit system, the test circuit system includes a control circuit, a first simulation circuit and a delay introduction circuit; the first simulation circuit is used to simulate a first chip to be tested The circuit in , the delay introduction circuit is used to introduce a timing delay for the first analog circuit; the control circuit is used to implement the steps in the method of the first aspect above.
  • an embodiment of the present invention provides a computer-readable storage medium for testing a circuit system, where the testing circuit system includes a first analog circuit and a delay introduction circuit, and the first analog circuit is used to simulate A circuit in the first chip to be tested, the delay introduction circuit is used to introduce a timing delay for the first analog circuit, and a computer program is stored on the computer-readable storage medium, and when the computer program is executed by the processor Do the following:
  • a target timing margin of the current link under test is determined.
  • the current link to be tested is determined from the first analog circuit of the test circuit system, and then the current link to be tested is adjusted and/or introduced based on delay The circuit introduces a timing delay for the current link under test, so that a timing violation occurs in the first analog circuit. Finally, when a timing violation occurs on the current link to be tested, the target timing margin of the current link to be tested is determined. In this way, by pre-designing the test circuit system and measuring the target timing margin when the link under test actually occurs timing violation in the actual circuit, the determined target timing margin can be closer to the real situation to a certain extent, and then the target timing can be improved. The accuracy of the margin avoids the problem of large area and high power consumption of the resulting chip due to directly setting a higher timing margin.
  • FIG. 1 is a flowchart of steps of a method for determining a timing margin provided by an embodiment of the present invention
  • FIG. 2 is a schematic diagram of a partial circuit structure provided by an embodiment of the present invention.
  • FIG. 3 is a schematic diagram of a waveform provided by an embodiment of the present invention.
  • FIG. 4 is a schematic diagram of a module design of a test circuit system provided by an embodiment of the present invention.
  • FIG. 5 is a block diagram of an apparatus for determining a timing margin provided by an embodiment of the present invention.
  • FIG. 6 is a block diagram of a computing processing device according to an embodiment of the present invention.
  • FIG. 7 is a block diagram of a portable or fixed storage unit according to an embodiment of the present invention.
  • the test verification (sign off) strategy of chip timing analysis has become more and more complicated.
  • the sign off strategy is a collection of a series of constraints and processes in the process of integrated circuit design and implementation, and the sign off strategy can be given by the chip manufacturer.
  • some timing slack is often added to various processes and links.
  • how to determine the timing margin of the circuits in the chip has become a widely concerned issue.
  • a static timing analysis (STA) method is used to divide the entire circuit design under test into multiple timing paths, calculate the transmission time of the electronic signal along each path, and then determine the final Whether the circuit under test can work normally.
  • STA static timing analysis
  • the STA tool calculates the delays of the basic units and connections on the clock path and data path respectively.
  • the SETUP timing check requires that the data signal input by the sequential device arrives before the clock edge arrives for a period of time
  • the HDLD timing check requires that the input data signal of the sequential device remains unchanged for a period of time after the clock edge arrives.
  • the STA tool assumes that it takes one clock cycle to transmit a signal through a set of timing paths. Therefore, the STA tool will consider the largest possible data delay and the smallest clock delay when checking in SETUP. When checking HDLD, the STA tool considers the minimum data delay and the maximum clock delay.
  • an embodiment of the present invention proposes a timing margin determination method.
  • the timing margin determination method will be described in detail below.
  • the method can be applied to a test circuit system.
  • the test circuit system includes a first analog circuit and a delay introduction circuit.
  • An analog circuit is used to simulate the circuit in the first chip to be tested, and the delay introduction circuit is used to introduce a timing delay for the first analog circuit.
  • the method may include:
  • Step 101 Receive test configuration information.
  • the specific structure of the first analog circuit and the specific structure of the delay introduction circuit may be set according to actual requirements.
  • the first analog circuit may be generated according to the circuit structure included in the chip to be tested.
  • the number of chips to be tested may be one or more, the chips to be tested may include the first chip to be tested that currently needs to be tested, and the circuit structures of the chips to be tested may be different. In this way, the testing of multiple chips to be tested can be implemented through the first analog circuit, thereby improving the covered test scenarios.
  • components that can increase the delay can be selected to construct a delay introduction circuit, so that when the delay introduction circuit is connected to the first analog circuit, the delay of the first analog circuit can be increased, thereby introducing a timing delay. effect.
  • the specific content of the test configuration information may be set according to current actual test requirements.
  • the test configuration information may be used to indicate which link is currently to be tested.
  • the link refers to the circuit in the chip to be tested, and the link can be composed of multiple connected components.
  • the test configuration information may be entered by the user. For example, when a link needs to be tested, the user may input corresponding test configuration information.
  • the test circuit system can confirm that the test timing margin is currently required, and accordingly, can perform subsequent steps according to the test configuration information.
  • a test start signal can also be given separately based on the input bus. After receiving the test start signal, the test circuit system performs subsequent steps according to the test configuration information, thereby reducing the probability of misoperation.
  • Step 102 Determine the current link to be tested in the first analog circuit according to the test configuration information.
  • the link in the first analog circuit indicated by the test configuration information may be used as the current link to be tested, to ensure that the link to be tested subsequently is the link that the user currently needs to test.
  • Step 103 Adjust the current link under test, and/or introduce a timing delay for the current link under test based on the delay introduction circuit, so that a timing violation occurs in the first analog circuit.
  • the adjustment operation performed on the current link under test may be an operation capable of changing the timing delay of the current link under test. For example, it may be to adjust the relevant parameters of the current link to be tested.
  • the time sequence delay is introduced into the current link under test based on the delay introduction circuit, which may be adding a delay introduction circuit for the current link under test.
  • the delay introduction circuit which may be adding a delay introduction circuit for the current link under test.
  • Step 104 When a timing violation occurs on the current link under test, determine a target timing margin of the current link under test.
  • the target timing margin of the current link to be tested may be determined when a timing violation of the current link to be tested just occurs.
  • the determined target timing slack may be a minimum timing slack capable of correcting timing violations, that is, a minimum timing slack that makes timing satisfaction just occur. In this way, to a certain extent, while making the determined target timing margin closer to the real situation, it can be ensured that the circuit is configured with the target timing margin subsequently, so that there is enough safety space in the circuit in actual use to ensure the circuit timing convergence.
  • the method for determining the timing margin determines, based on the test configuration information, the current link to be tested from the first analog circuit of the test circuit system, and then determines the current link to be tested by Adjusting and/or introducing a timing delay for the current link under test based on the delay introduction circuit, so that a timing violation occurs in the first analog circuit. Finally, when a timing violation occurs on the current link to be tested, the target timing margin of the current link to be tested is determined. In this way, by pre-designing the test circuit system and measuring the target timing margin when the link under test actually occurs timing violation in the actual circuit, the determined target timing margin can be closer to the real situation to a certain extent, and then the target timing can be improved.
  • the accuracy of the margin avoids the problem of large area and high power consumption of the resulting chip due to directly setting a higher timing margin. At the same time, by avoiding the large area and high power consumption of the finally generated chip, the production cost can be reduced and the chip performance can be improved.
  • the test circuit system in the embodiment of the present invention may be provided on a circuit board.
  • the test process can take into account the outside world to a certain extent. Therefore, to a certain extent, the final target timing slack can be closer to the real situation of subsequent use, thereby improving the accuracy of the target timing slack.
  • test circuit system in the embodiment of the present invention may be provided on the same circuit board as the circuit in the first chip to be tested, that is, the circuit of the first chip to be tested may also be provided on the aforementioned circuit board.
  • chip re-chipping may be performed, that is, part of the test chip for testing may be produced first, wherein the test chip may include a test circuit system, that is, the test circuit may be The system is put into the corresponding chip design, thereby realizing that the test circuit system and the circuit in the first chip to be tested are arranged on the same circuit board.
  • the process and design margin can be fully analyzed to set the working conditions of the existing chips and the design of subsequent chips. Provide guidance. Further, it is also possible to test the circuits of the chips to be tested on multiple circuit boards at the same time, thereby realizing mass production testing, which facilitates circuit adjustment based on the test results in the later stage.
  • the testing process can take into account the overall situation of the first chip to be tested during operation, and to a certain extent The closeness to the real situation in subsequent use can be improved, thereby further improving the accuracy of the target timing margin.
  • the first analog circuit in this embodiment of the present invention may include m link groups, one link group may include n available links, and the available links may be used to simulate the first link in the first chip to be tested.
  • a link the test configuration information may include group selection information.
  • the test configuration information may be input by a central processing unit (Central Processing Unit/Processor, CPU) or external control software through a control peripheral bus (Advanced Peripheral Bus, APB).
  • CPU Central Processing Unit/Processor
  • APB Advanced Peripheral Bus
  • n and n may be positive integers, and specific values of m and n may be set according to actual requirements, which are not limited in this embodiment of the present invention.
  • n may be 128, that is, 128 available links (Chains) may be used as a link group internally. Since the number of available links and link groups can be configured and the structure can be adjusted, the impact of various factors of the actual timing analysis process on the timing margin can be comprehensively considered when constructing the first analog circuit, with high flexibility .
  • the components included in the first analog circuit and the connection manner between the components in the embodiment of the present invention may be set according to the components included in the first chip to be tested and the connection relationship between the components. In this way, it can be ensured that the first simulation circuit can accurately simulate the circuit in the first chip to be tested, thereby ensuring the accuracy of the timing margin obtained by the test.
  • the type of the combinational logic unit in the first analog circuit can be further determined in combination with the process analysis result of the chip, the sign off strategy and other dimensions.
  • the first link may be a link whose usage frequency is greater than a preset frequency threshold and/or whose structural complexity is less than a preset complexity threshold among the links included in the first chip under test.
  • the preset frequency threshold and the preset complexity threshold may be set according to actual requirements.
  • the usage frequency of the link included in the first chip under test may be estimated according to the actual function to be implemented by the link. For example, when the actual implemented function is a more commonly used function, the usage frequency of the link may be higher. high.
  • the structural complexity can be determined according to the number and type of components included in the link and the connection relationship between the components. For example, in the case that the number and types are more, and the connection relationship between the components is more complicated, the structural complexity of the link is higher.
  • the first link may be determined first according to a preset frequency threshold and/or a preset complexity threshold.
  • a first analog circuit is constructed based on the components included in the first link and the connection manner between the components. For example, a first analog circuit including the same components and the same connection mode can be constructed to evaluate the timing margin of the actual circuit in an actual scenario.
  • the first analog circuit by only using the first analog circuit to simulate a link in the first chip under test whose usage frequency is greater than the preset frequency threshold and/or whose structural complexity is less than the preset complexity threshold, it is possible to achieve a certain level of When the first chip to be tested performs the timing test, the reusability of the test results is increased, and the realization difficulty and the realization cost are reduced. At the same time, the coverage of as many sequential circuit scenarios as possible can be achieved while ensuring low relative complexity.
  • the above step of determining the current link to be tested in the first analog circuit according to the test configuration information may include the following steps:
  • the group selection information may be information that can uniquely indicate the link group.
  • the group selection information may be group name, group number, and the like.
  • the test configuration information can be parsed first, and then the group selection information can be read therefrom.
  • the group information of each link group may be matched with the group selection information, and the link group whose group information is matched with the group selection information is the link group indicated by the group selection information.
  • the group number of each link group may be matched with the group number represented by the group selection information, and the link group whose group number matches is determined as the current link group to be tested.
  • the user by setting the first analog circuit in the form of a link group, the user only needs to set the group selection information for indicating the link group to be tested in the test configuration information to realize the specific link The test of the road group, thereby improving the convenience of operation to a certain extent.
  • the group selection information when determining the current link to be tested, only the group selection information needs to be read, and the current link to be tested can be determined directly according to the group selection information, thereby improving the determination efficiency of determining the current link to be tested to a certain extent.
  • the above-mentioned operation of introducing a timing delay for the current link under test based on the delay introduction circuit may include the following steps:
  • adjusting the length of the connected link it may be to adjust the number of components connected to the current link to be tested in the delay introduction circuit.
  • a multiplexer may be set between the first analog circuit and the delay introduction circuit, and the multiplexer is controlled in real time based on the control signal, thereby realizing real-time control of the length of the link accessing the current link to be tested.
  • different control signals may indicate different lengths. In this way, since the control signal of the multiplexer is adjusted in real time in the actual circuit, the purpose of adjusting the delay of the current link to be tested can be achieved.
  • the introduction of different timing delays can be implemented, thereby ensuring the efficiency of introducing timing delays to a certain extent.
  • the method of adjusting the access length can change the circuit delay relatively smoothly to a certain extent, so that the circuit transitions smoothly from the timing satisfaction to the timing violation state.
  • the components in the delay introduction circuit may include buffers and/or inverters.
  • the use of buffers and inverters to form a delay introduction circuit can realize the introduction of delay, and at the same time avoid the problems that the structure of the delay introduction circuit is too complicated and the cost is high, thereby reducing the difficulty of implementation.
  • the total number of components in the delay introduction circuit may be positively correlated with the maximum operating frequency that the first analog circuit needs to support.
  • test configuration information in this embodiment of the present invention may further include initial link length information.
  • the initial link length information may characterize the initial link length.
  • the operation of adjusting the link length of the delay introduction circuit to access the current link under test may include:
  • the initial link length indicated by the initial link length information may be determined first, and then the length of the link accessing the current link to be measured is set as the initial link length, so that the current The link to be tested is tested. For example, assuming that the initial link length is 3, the connection relationship between the current link under test and the delay introduction circuit can be changed, so that the three components in the delay introduction circuit can be connected to the current link under test. . Accordingly, it can be detected whether a timing violation occurs in the current situation.
  • the accessed link length can be further set as the target link length. Further, if the target link length set this time is not enough to cause a timing violation on the current link to be tested, a new target link length can be re-determined, and adjustment is continued until a timing violation occurs.
  • the link length can be controlled to be adjusted to different values for testing, so that the convenience of the testing operation can be improved to a certain extent, thereby improving the testing efficiency.
  • the type of the target timing margin to be measured can be first determined, and if the type of the target timing margin is the establishment timing margin, the initial link length is incremented, Get at least one target link length. If the type of the target timing slack is maintaining the timing slack, the initial link length is decremented to obtain at least one target link length. Specifically, when performing incremental processing, a fixed value may be added to the initial link length to obtain a target link length. Correspondingly, if the length of the target link generated this time is not enough to cause a timing violation on the current link to be tested, a fixed value is added to the initial link length to continue generating the target link length.
  • the target link length 4 can be generated. If the target link length 4 generated this time is not enough to cause a timing violation of the current link to be tested, you can add a fixed value of 1 to the initial link length after the previous round of updates to generate the target link The length is 5, and so on, until the current link under test has a timing violation.
  • a fixed value can be subtracted from the initial link length to obtain a target link length.
  • a fixed value is subtracted from the initial link length to continue generating the target link length.
  • the control module may scan the length selection signal in an increment or decrement according to a predefined order, thereby realizing increment processing or decrement processing.
  • the length information in the length selection signal may be set according to a preset sign off policy.
  • the target link length is generated by first determining the type of the target timing margin, and performing corresponding increment processing or decrement processing for different types. In this way, it can be ensured that the length of the generated target link can match the current test scenario, thereby ensuring that the length of the continuously generated target link can increase/reduce the circuit delay, so that the current link to be tested eventually has a timing violation in the SETUP mode. Timing violation in /HOLD mode to ensure test results.
  • the above-mentioned operation of adjusting the current link to be tested may include the following steps:
  • the current working frequency of the link to be tested is the working clock frequency of the current link to be tested.
  • the timing delay requirement will be affected by the working clock frequency.
  • the timing delay of the current link to be tested has different requirements. For example, when the operating clock frequency is higher, the timing delay of the current link to be tested can be shorter.
  • the working clock cycle of the circuit is related to the working clock frequency, and the higher the working clock frequency is, the smaller the working clock cycle can be.
  • the operating frequency of the current link to be measured can be set to a preset fixed frequency to Ensure that the delay value caused by the current working clock cycle of the link under test occupies a large proportion of the total delay in the timing path, thereby ensuring the test effect.
  • the timing delay of the current link to be tested can meet different requirements, thereby ensuring the introduction efficiency to a certain extent.
  • the test configuration information may further include working frequency information. Accordingly, the above-mentioned operation of adjusting the working frequency of the current link to be tested may include:
  • the preset fixed value may be set according to actual requirements.
  • the preset fixed value may be a value configured by a preset sign off, which is not limited in this embodiment of the present invention.
  • the frequency indicated by the working frequency information is first determined, and then the working frequency of the current link to be tested is set to the indicated frequency, so as to test the current link to be tested at the working frequency.
  • a phase-locked loop (Phase-Locked Loop, PLL) frequency modulation can be used externally to perform frequency ergodic scanning, and after the current link to be tested is tested at the previous operating frequency, the operating clock frequency is updated externally, The next scan is restarted to enter new test configuration information with the updated operating clock frequency.
  • PLL Phase-locked Loop
  • the HOLD mode is often not affected by the frequency, that is, it is not affected in the frequency modulation mode. Therefore, this step can be performed in the SETUP mode. Change the circuit delay so that the circuit has a timing violation in SETUP mode.
  • the operating frequency can be adjusted based on the operating frequency specified in the test configuration information. In this way, the convenience of the test operation can be improved to a certain extent, thereby improving the test efficiency.
  • the test circuit system in this embodiment of the present invention may further include a standard device link.
  • a standard device link may be set in the first analog circuit.
  • a standard device link may be set in the first analog circuit.
  • a link is a link group of available links.
  • a standard device link can correspond to one standard device, that is, according to the different dimensions of the standard device, it can be strung into multiple single-type combinational logic unit chains as standard device links, which are used to analyze the timing margins of different standard devices respectively. quantity.
  • the standard components may be components included in each of the second links in the first chip under test.
  • the second link may be a link other than the first link in the first chip under test.
  • the second link may be a link with a relatively low frequency of use and high structural complexity.
  • the operation of determining the target timing margin of the current link under test may include the following steps:
  • the operating frequency of the standard device link can be adjusted to change the timing delay in the standard device link until the standard device link A timing violation occurred.
  • the length of the access delay introduction circuit can also be changed to cause a timing violation on the standard device link.
  • the currently used operating frequency can be recorded when the standard device link just has a timing violation.
  • the clock skew skew
  • the period corresponding to the operating frequency currently used by the standard device link may be determined first, and then calculated The ratio of the cycle duration to the number of standard components in the standard device link, to obtain a single delay value corresponding to the standard components. That is, the link delay is approximately scaled in duty cycles.
  • the inverse of the currently used operating frequency can be used as the corresponding cycle duration, and then the number of standard components in the standard device link can be obtained. For example, the number of standard components can be directly read from the configuration information of the standard device link. .
  • the value of dividing the cycle duration by the number of standard components can be calculated to obtain a single delay value corresponding to the standard components.
  • a single delay value corresponding to the standard components can be obtained, which can improve the test efficiency to a certain extent.
  • a more objective and accurate reduction standard can be provided for the timing margin adjustment in the later stage.
  • the single delay value corresponding to each standard component is determined when the standard device link just has a timing violation, the single delay value corresponding to the standard component can be used to avoid the standard device link to a certain extent.
  • the target timing margin of the second link can be determined according to the single delay value corresponding to the standard component.
  • a standard device link is constructed with the components included in the second link, a single delay value corresponding to the standard component is determined based on the standard device link, and then, according to the single delay value corresponding to each standard component value to determine the target timing margin of the second link, which can expand the test scenarios that can be covered by the test circuit system.
  • the single delay value corresponding to the standard component is tested first, and the method of determining the target timing margin of the second link based on the single delay value corresponding to the standard component can be omitted according to the connection relationship of the components in the second link.
  • the operation of the link group for simulating the second link is pre-built in the first analog circuit, thereby reducing the difficulty of implementation and saving the implementation cost to a certain extent.
  • the operation of determining the target timing margin of the second link according to a single delay value corresponding to each of the standard components may include:
  • the preset timing simulation algorithm may be an existing algorithm selected according to actual requirements, which is not limited in this embodiment of the present invention.
  • the preset timing simulation algorithm may be an STA algorithm, and accordingly, timing analysis may be performed on the second link based on the STA tool, so as to obtain the timing margin to be corrected.
  • S42B Determine a single delay value corresponding to a component included in the second link according to a single delay value corresponding to each of the standard components.
  • any second link specific components included in the second link may be determined first. Then, from the single delay values corresponding to all standard components, the single delay value corresponding to each component included in the second link is searched for.
  • timing simulation algorithm calculates the estimated value is often higher, therefore, in this step, a single delay can be used as the adjustment standard, and the timing margin to be corrected can be corrected to obtain a more accurate target timing margin.
  • the timing margin to be corrected is first determined, and then the timing margin to be corrected is corrected according to the single delay value corresponding to the components included in the second link, and the target timing margin of the second link is obtained.
  • the single delay value corresponding to the component is obtained by testing in the actual circuit, the single delay value as the correction standard can ensure the correction accuracy to a certain extent.
  • it is more reliable to use a single delay value as the correction standard for correction which can make the target timing margin of the corrected second link more accurate to a certain extent, which can save the later reach. Time required for timing closure.
  • the method for determining a timing margin may further include the following steps:
  • Links include the first link and/or the second link.
  • the preset timing simulation algorithm may be an existing algorithm selected according to actual requirements, which is not limited in this embodiment of the present invention.
  • timing analysis may be performed on the first link to be tested based on the STA tool, so as to obtain the basic timing margin.
  • the difference between the basic timing slack and the target timing slack can be calculated to obtain the slack difference.
  • the margin difference value may reflect the margin difference between the corresponding basic timing margin in the timing analysis scenario and the target timing margin in the actual scenario.
  • the second chip to be tested may be a chip to be tested, and the second chip to be tested may be the same chip as the first chip to be tested.
  • the second link may be used as the first link to be tested in S51, and the first link in the first chip to be tested may be used as the second link to be tested.
  • the steps provided in the example determine the target timing slack for the first link.
  • the second chip to be tested may also be a different chip from the first chip to be tested, which is not limited in this embodiment of the present invention.
  • the timing margin difference may also be used as a dependent variable, and the timing path delay, On Chip Variations (OCV), crosstalk, and clock uncertainty ( uncertainty) and other factors as independent variables to fit the objective function.
  • OCV On Chip Variations
  • crosstalk crosstalk
  • clock uncertainty uncertainty
  • S54 Determine a corrected margin difference value corresponding to the second link under test according to each of the margin difference values, and determine the basic timing margin of the second link under test according to the corrected margin difference value.
  • the target timing margin of the second link to be tested is obtained by correcting the amount.
  • the average value of all the margin differences may be calculated first to obtain the standard margin difference, and the standard margin difference may be directly determined as the corrected margin difference corresponding to the second link to be tested.
  • the correction margin difference value can be determined only by performing the average value calculation operation, which can improve the determination efficiency to a certain extent.
  • the difference between the basic timing margin of the second link to be tested and the difference between the correction margins can be calculated, and then the target timing margin of the second link to be tested can be obtained. quantity.
  • a preset timing simulation algorithm is used to determine the basic timing margin corresponding to the first link to be tested in the timing analysis scenario, and then the difference between the basic timing margin and the target timing margin determined in the actual scenario is calculated. margin difference between. Subsequently, when determining the timing margin of the second link to be tested in the second chip to be tested, the second link to be tested determined according to the preset timing simulation algorithm is based on the margin difference between the actual scenario and the timing analysis scenario as a reference. Correct the basic timing margin of , and obtain the target timing margin of the second link under test. In this way, by combining the margin difference between the actual scenario and the timing analysis scenario, a reference is provided for the subsequent operation of determining the timing margin, and the determination efficiency and accuracy can be improved to a certain extent.
  • the above-mentioned operation of determining the target timing margin of the current link under test when a timing violation occurs on the current link under test may include:
  • the clock path and the data path can be detected on the circuit board where the test circuit system is located.
  • the data path can represent the time when the data arrives at the component.
  • the clock path can represent the clock arrival time.
  • the timing slack corresponding to the components is calculated according to the clock path and the data path. For example, the sum of the difference obtained by subtracting the data path from the clock path and the clock period is used as the setup slack, and the difference obtained by subtracting the clock path from the data path is used as the hold slack.
  • the average value of the timing slack corresponding to the components included in the current link under test may be used as the first timing slack.
  • the maximum value of the timing margins corresponding to the components included in the current link under test is used as the first timing margin, which is not limited in this embodiment of the present invention.
  • the first timing slack may also be directly determined as the target timing slack of the current link to be tested, so that the processing steps can be simplified to a certain extent, thereby reducing the processing cost.
  • this step For the specific implementation manner of this step, reference may be made to the foregoing related descriptions, which will not be repeated here. It should be noted that the execution order of this step is not unique, and in practical application, this step may also be executed in advance to obtain the second timing margin.
  • the difference between the second timing margin and the difference may be directly used as the target timing margin of the current link under test.
  • the difference between the second timing margin and the first specific value may be used as the target timing margin of the current link under test.
  • the difference is small, for example, not greater than the preset threshold, the difference between the second timing margin and the second specific value is used as the target timing margin of the current link under test.
  • the first specific value is greater than the second specific value.
  • a preset timing simulation algorithm is used to determine the second timing margin corresponding to the current link to be tested in the timing analysis scenario, and the second timing margin is determined according to the second timing margin and the first timing margin determined in the actual scene.
  • the difference between the values determines the target timing margin of the current link under test.
  • the target timing margin of the current link to be tested is determined based on the margin difference between the actual scenario and the timing analysis scenario, which can ensure the accuracy of the determined target timing margin to a certain extent.
  • the target timing margin can be determined relatively quickly.
  • test circuit system in the embodiment of the present invention may further include a timing violation capture circuit connected to the first analog circuit.
  • steps may be used to determine that the current link under test has a timing violation:
  • the timing violation capture circuit may include a first capture circuit and a second capture circuit.
  • the first capture circuit includes a parallel first register, a first latch, and an exclusive OR gate, and the exclusive OR gate is used to perform an exclusive OR operation on the output of the first register and the output of the first latch.
  • the second capture circuit may include a parallel second register, a second latch, and an exclusive-OR gate for performing an exclusive-OR operation on the output of the second register and the output of the second latch.
  • the output value of the first capturing circuit may be acquired under the condition that the type of the target timing margin to be tested is the establishment timing margin.
  • the output value of the second capture circuit is acquired. Since the latch is level-sensitive, in the embodiment of the present invention, by setting the capture circuit, the abnormal level that occurs when the timing violation occurs can be captured by the capture circuit, thereby identifying whether a timing violation occurs in the current timing path.
  • FIG. 2 is a schematic diagram of a partial circuit structure provided by an embodiment of the present invention, as shown in FIG. 2 , wherein test_in represents an input signal, test_en represents an enable signal, clk represents a clock signal, rst_in represents a set, chain_sel Indicates the chain length selection signal.
  • 01 represents the current link to be tested
  • 02 represents the delay introduction circuit
  • 03 represents the first capture circuit.
  • the XOR result of the XOR gate in 03 that is, the output value of the first capture circuit, can be saved to the register connected behind the XOR gate.
  • the value in the register can be directly read to obtain the output value.
  • FIG. 3 is a schematic diagram of a waveform provided by an embodiment of the present invention.
  • the output of the timing violation capture circuit may be as shown in FIG. 3 , where the first row may represent the waveform of the first capture circuit, and the second row may represent the first 2. Capture the waveform of the circuit.
  • Q1 is the output port waveform of the first register
  • D2 is the input port waveform of the second-level parallel register and latch
  • Qlatch is the latch output waveform
  • QFF is the parallel register output waveform
  • vio represents the combination of the two Logical output, that is, the output value.
  • the data In SETUP mode, the data should arrive before the setup time of the register. Therefore, if the timing is satisfied, the latch and the register will collect the same signal. Accordingly, the XOR result is output as 0. In the case of timing violation, since the register acquisition signal will be delayed by one beat, the XOR result will output 1. In the HOLD test mode, when the timing is satisfied, the latch and the register will collect different signals, and accordingly, the XOR result is output as 0. In the case of timing violation, since the register acquisition signal is one beat ahead of time, the XOR result will output 1.
  • the characteristic value may be 1, and when the output value is 1, it may be determined that the current link under test has a timing violation.
  • the output value of the timing violation capturing circuit is acquired, and based on the output value, it can be determined whether the current link under test has timing violation. In this way, to a certain extent, the convenience of detecting whether a timing violation occurs can be increased, and the test efficiency can be improved.
  • the detection result may be reported when it is determined that the current link to be tested has a timing violation.
  • the detection result may include the current link length of the delay introduction circuit when the current link to be tested has a timing violation. It may further include group selection information of the link group corresponding to the current link to be tested. In this way, by reporting the detection results, it is convenient for the later link to determine the specific form of the problem in the link with timing violation, which in turn facilitates data analysis in the later stage.
  • each step in the embodiment of the present invention may be implemented based on digital logic design.
  • a hardware description language (verilog) code can be generated based on script compilation, so that each step in the embodiment of the method for determining the timing margin can be implemented more conveniently.
  • the existing analysis process such as the STA analysis process, can also be combined for design, so that the test circuit system in the embodiment of the present invention can support the STA process, thereby improving portability.
  • the transistor includes a gate, a source, and a drain. After applying the voltage to the gate, the current from the source to the drain can be controlled on and off. As the gate is shorter, the current flows faster, so as the process is upgraded, the gate is made shorter.
  • the process is also constantly updated. For example, in order to solve the leakage problem in the manufacturing process below 20nm, a field effect transistor (Fin Field-Effect Transistor, FinFET) has been developed. Due to the continuous updating of the process, the margin value or the margin scheme under the previous process is difficult to apply to the more advanced process. Therefore, how to quickly obtain the corresponding timing margin under the new process to form a mature timing analysis sign off strategy has become a difficulty.
  • FinFET Fin Field-Effect Transistor
  • the timing margin determination method proposed in the embodiment of the present invention is less affected by the manufacturing process, and can be quickly transplanted to other processes. Therefore, it can be applied to analyze the timing margin under a specific process in VLSI design.
  • the test circuit system in the embodiment of the present invention can be applied to the detection of VLSI chips under different manufacturing parties and different precision processes, and has a wide application range and is convenient, simple and flexible in design. In this way, the manufacturing process can be improved, and the performance of the process can be fully utilized, while the timing closure efficiency of the integrated circuit and the performance and quality of the integrated circuit operation can be improved. At the same time, timing closure can be achieved through more efficient determination, which can also reduce the production and design costs of integrated circuits to a certain extent.
  • a warning circuit as a timing violation
  • an adaptive circuit design such as an adaptive voltage scaling (AVS) controller
  • VVS adaptive voltage scaling
  • this digital circuit test scheme is also based on adding more timing slack. By pre-designing the test circuit system and measuring the target timing margin when the link under test actually has a timing violation in the actual circuit, the determined target timing margin can be closer to the real situation to a certain extent, and then the target timing margin can be improved. accuracy.
  • FIG. 4 is a schematic diagram of a module design of a test circuit system provided by an embodiment of the present invention.
  • SMT_GROUP_INTR represents an output interrupt signal
  • TCK, SMT_PCLK and CLK_SYS represent a clock signal
  • CLK_SYS is the clock signal used in the test process
  • TCK and SMT_PCLK are the protocol clock signals of the system.
  • IPTEST_MODE_EN is used to select the mode.
  • APB FROM ACPU_NOC indicates the input test configuration information.
  • APB_Mux2 represents the Advanced Peripheral Bus Multiplexer.
  • DAP represents the input interface for JTAG signals.
  • SMT_PGCC represents the stimulus generation and capture module
  • SMT_REG represents the configuration module
  • CHAIN_WRAP_TOP represents the delay chain module
  • SMT_MUX and SMT_RPT represent the report combing module
  • IPTEST_DAP2APB represents the interface module.
  • the IPTEST_DAP2APB module can be used to convert the JTAG input signal into configuration information conforming to the APB protocol in the IPTEST mode. You can also input configuration information directly through the APB interface in non-IPTEST mode, and the output signal can be used as the APB SLAVE configuration interface. Further, the SMT_REG module can also be used as the APB SLAVE configuration interface to complete SMT related configuration input and output test results.
  • the SMT_PGCC module can complete the conversion of the APB clock domain parameters to the system clock domain. And after receiving the test start signal, select the current test configuration according to the configuration information, output the common link length selection signal and test excitation and enable signal according to the corresponding working mode, and enable specific links in sequence. And report the test interruption after the test is completed.
  • the enable signal can be used to control the work of the chain under test, and the enable signal can be output to the corresponding link group. When a link group is tested, the enable signals in other groups are fixed and invalid, thereby preventing other groups from interfering with the current test.
  • the test stimulus is used to characterize information about how much width is used in this round of testing.
  • the input level pulse data can be collected from the first register, and the collected data can be sent from the next cycle as the starting point.
  • the specific test stimulus can be given according to the current test mode, and the content of the test stimulus corresponding to each test mode can be preset.
  • SMT_PGCC can send a pulse signal to the CHAIN_WRAP_TOP module.
  • the CHAIN_WRAP_TOP module can be the top module of all test chains, and the CHAIN_WRAP_TOP module can include link groups.
  • the four blocks included in the CHAIN_WRAP_TOP module shown in FIG. 4 represent four link groups, and the content in the blocks may represent the identifiers of the link groups. In practical application, any number of groups can be constructed for testing according to actual test requirements.
  • the SMT_MUX module can report the detection result according to the group selection information configured by the SMT_REG.
  • the SMT_RPT module can include a latch register for storing the reporting result of the link to be tested.
  • the acquisition circuit can output the current link length of the level signal or the delay introduced into the circuit when a timing violation occurs according to the current working mode to the register.
  • the register can According to the violation signal corresponding to the output of the link to be tested, the current link length and the violation level signal of the delay introduction circuit when timing violation occurs are latched.
  • the enable signal of the corresponding test chain is controlled to be invalid according to the violation level signal, so that the chain under test stops working when a timing violation occurs.
  • the automatic generation of the stimulus can be completed relatively quickly based on the SMT_PGCC, and the stimulus is transmitted to the CHAIN_WRAP_TOP module to make the test chain test, and then based on the preset test stimulus, various chains can be quickly tested. road to test.
  • the final output result can be automatically captured by the registers in the SMT_REG module through the SMT_MUX module, and then automatically reported to the SMT_RPT module, and finally output to the CPU or outside the chip through the bus.
  • the module only needs a small amount of configuration, and can complete a large amount of testing in a short period of time.
  • test data can be read out, and then the test data can be analyzed based on a preset script statistical software, manual analysis, etc., to draw a statistical conclusion. Further, it is also possible to combine a more accurate target timing margin to form a database through a large number of test results, and to determine the margin adjustment scheme through statistical analysis of the database, thereby improving chip performance, power consumption, area and cost, and optimizing timing. Provide guidance on analyzing signoff methods and processes.
  • the apparatus can be applied to a test circuit system.
  • the test circuit system includes a first simulation circuit and a delay introduction circuit.
  • the first simulation circuit The circuit is used to simulate the circuit in the first chip to be tested, and the delay introduction circuit is used to introduce a timing delay for the first simulation circuit.
  • the apparatus may include: a memory 301 and a processor 302 .
  • the memory 301 is used to store program codes.
  • the processor 302 calls the program code, and when the program code is executed, is configured to perform the following operations:
  • an embodiment of the present invention also provides a test circuit system, the test circuit system includes a control circuit, a first simulation circuit and a delay introduction circuit; the first simulation circuit is used to simulate the first chip to be tested.
  • the delay introduction circuit is used to introduce a timing delay for the first analog circuit; the control circuit is used to execute the steps in the above-mentioned timing margin determination method embodiment.
  • An embodiment of the present invention further provides a movable device, where the movable device includes a chip; the timing margin of the circuit in the chip is determined based on the test circuit system.
  • the movable device is one or more of drones, unmanned vehicles, and robots.
  • an embodiment of the present invention further provides a computer-readable storage medium, where a computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, each step in the above method for determining a timing margin is implemented, And can achieve the same technical effect, in order to avoid repetition, it is not repeated here.
  • the device embodiments described above are only illustrative, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in One place, or it can be distributed over multiple network elements. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution in this embodiment. Those of ordinary skill in the art can understand and implement it without creative effort.
  • Various component embodiments of the present invention may be implemented in hardware, or in software modules running on one or more processors, or in a combination thereof.
  • a microprocessor or a digital signal processor may be used in practice to implement some or all of the functions of some or all of the components in the computing processing device according to the embodiments of the present invention.
  • the present invention can also be implemented as apparatus or apparatus programs (eg, computer programs and computer program products) for performing part or all of the methods described herein.
  • Such a program implementing the present invention may be stored on a computer-readable medium, or may be in the form of one or more signals. Such signals may be downloaded from Internet sites, or provided on carrier signals, or in any other form.
  • FIG. 6 is a block diagram of a computing processing device provided by an embodiment of the present invention. As shown in FIG. 6 , FIG. 6 shows a computing processing device that can implement the method according to the present invention.
  • the computing processing device traditionally includes a processor 710 and a computer program product or computer readable medium in the form of a memory 720 .
  • the memory 720 may be electronic memory such as flash memory, EEPROM (electrically erasable programmable read only memory), EPROM, hard disk, or ROM.
  • the memory 720 has storage space 730 for program code for performing any of the method steps in the above-described methods.
  • the storage space 730 for program codes may include various program codes for implementing various steps in the above methods, respectively.
  • the program codes can be read from or written to one or more computer program products.
  • These computer program products include program code carriers such as hard disks, compact disks (CDs), memory cards or floppy disks.
  • Such computer program products are typically portable or fixed storage units as described with reference to FIG. 7 .
  • the storage unit may have storage segments, storage spaces, etc. arranged similarly to the memory 720 in the computing processing device of FIG. 6 .
  • the program code may, for example, be compressed in a suitable form.
  • the storage unit includes computer readable code, ie code readable by a processor such as 710 for example, which when executed by a computing processing device, causes the computing processing device to perform each of the methods described above. step.
  • any reference signs placed between parentheses shall not be construed as limiting the claim.
  • the word “comprising” does not exclude the presence of elements or steps not listed in a claim.
  • the word “a” or “an” preceding an element does not exclude the presence of a plurality of such elements.
  • the invention can be implemented by means of hardware comprising several different elements and by means of a suitably programmed computer. In a unit claim enumerating several means, several of these means may be embodied by one and the same item of hardware.
  • the use of the words first, second, and third, etc. do not denote any order. These words can be interpreted as names.

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Abstract

一种时序裕量确定方法、装置、测试电路系统及可读存储介质，该方法可以基于测试配置信息，从测试电路系统的第一模拟电路中确定出当前待测试链路，然后，通过对当前待测链路进行调整，和/或，基于延时引入电路为当前待测链路引入时序延时，以使第一模拟电路出现时序违例。最后，在当前待测链路出现时序违例时，确定当前待测链路的目标时序裕量。这样，通过预先设计测试电路系统，在实际电路中测量待测链路实际出现时序违例时的目标时序裕量，一定程度上可以使确定的目标时序裕量更贴近真实情况，进而可以提高目标时序裕量的准确性，避免由于直接设置较高的时序裕量导致最终生成的芯片的面积较大，功耗较高的问题。

Description

时序裕量确定方法、装置、测试电路系统及可读存储介质 技术领域
本发明属于网络技术领域，特别是涉及一种时序裕量确定方法、装置、测试电路系统及可读存储介质。
背景技术
目前，为了确保芯片在工作时能够满足时序收敛的要求，确保芯片能够正常工作，往往需要为芯片中电路配置合适的时序裕量。因此，如何确定芯片的时序裕量成为人们广泛关注的问题。
在先技术中，为了确保能够覆盖更多时序违例场景，为芯片留有足够的时序安全空间，往往会直接将时序裕量设置的较高。这样，会导致时序裕量的准确性较低，进而会导致最终生成的芯片的面积较大，功耗较高。
发明内容
本发明提供一种时序裕量确定方法、装置、测试电路系统及可读存储介质，以便解决时序裕量的准确性较低，进而导致最终生成的芯片的面积较大，功耗较高的问题。
为了解决上述技术问题，本发明是这样实现的：
第一方面，本发明实施例提供了一种时序裕量确定方法，应用于测试电路系统，所述测试电路系统中包括第一模拟电路及延时引入电路，所述第一模拟电路用于模拟第一待测芯片中的电路，所述延时引入电路用于为所述第一模拟电路引入时序延时，该方法包括：
接收测试配置信息；
根据所述测试配置信息，确定所述第一模拟电路中的当前待测链路；
对所述当前待测链路进行调整，和/或，基于所述延时引入电路为所述当前待测链路引入时序延时，以使所述第一模拟电路出现时序违例；
在所述当前待测链路出现时序违例时，确定所述当前待测链路的目标时序裕量。
第二方面，本发明实施例提供了一种时序裕量确定装置，应用于测试电路系统，所述测试电路系统中包括第一模拟电路及延时引入电路，所述第一模拟电路用于模拟第一待测芯片中的电路，所述延时引入电路用于为所述第一模拟电路引入时序延时，所述装置包括存储器和处理器；
所述存储器，用于存储程序代码；
所述处理器，调用所述程序代码，当所述程序代码被执行时，用于执行以下操作：
接收测试配置信息；
根据所述测试配置信息，确定所述第一模拟电路中的当前待测链路；
对所述当前待测链路进行调整，和/或，基于所述延时引入电路为所述当前待测链路引入时 序延时，以使所述第一模拟电路出现时序违例；
在所述当前待测链路出现时序违例时，确定所述当前待测链路的目标时序裕量。
第三方面，本发明实施例提供了一种测试电路系统，所述测试电路系统中包括控制电路、第一模拟电路及延时引入电路；所述第一模拟电路用于模拟第一待测芯片中的电路，所述延时引入电路用于为所述第一模拟电路引入时序延时；所述控制电路用于实现上述第一方面所述方法中的步骤。
第四方面，本发明实施例提供了一种计算机可读存储介质，用于测试电路系统，所述测试电路系统中包括第一模拟电路及延时引入电路，所述第一模拟电路用于模拟第一待测芯片中的电路，所述延时引入电路用于为所述第一模拟电路引入时序延时，所述计算机可读存储介质上存储计算机程序，所述计算机程序被处理器执行时实现以下操作：
接收测试配置信息；
根据所述测试配置信息，确定所述第一模拟电路中的当前待测链路；
对所述当前待测链路进行调整，和/或，基于所述延时引入电路为所述当前待测链路引入时序延时，以使所述第一模拟电路出现时序违例；
在所述当前待测链路出现时序违例时，确定所述当前待测链路的目标时序裕量。
在本发明实施例中，基于测试配置信息，从测试电路系统的第一模拟电路中确定出当前待测试链路，然后，通过对当前待测链路进行调整，和/或，基于延时引入电路为当前待测链路引入时序延时，以使第一模拟电路出现时序违例。最后，在当前待测链路出现时序违例时，确定当前待测链路的目标时序裕量。这样，通过预先设计测试电路系统，在实际电路中测量待测链路实际出现时序违例时的目标时序裕量，一定程度上可以使确定的目标时序裕量更贴近真实情况，进而可以提高目标时序裕量的准确性，避免由于直接设置较高的时序裕量导致最终生成的芯片的面积较大，功耗较高的问题。
附图说明
图1是本发明实施例提供的一种时序裕量确定方法的步骤流程图；
图2是本发明实施例提供的一种部分电路结构示意图；
图3是本发明实施例提供的一种波形示意图；
图4是本发明实施例提供的一种测试电路系统的模块设计示意图；
图5是本发明实施例提供的一种时序裕量确定装置的框图；
图6为本发明实施例提供的一种计算处理设备的框图；
图7为本发明实施例提供的一种便携式或者固定存储单元的框图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述， 显然，所描述的实施例是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
首先，对本发明实施例涉及的一种应用场景进行说明。目前，随着超大规模集成电路芯片制造工艺的发展，芯片时序分析的测试确认(sign off)策略也变得越加复杂。其中，sign off策略为集成电路设计与实现过程中一系列的约束条件和流程的集合，sign off策略可以由芯片制造方给出。为了确保最终芯片能够正常工作，经常会在在各个流程和环节中加入一些时序裕量。相应地，如何确定芯片中电路的时序裕量成为人们广泛关注的问题。
在一种现有实现方式中，是采用静态时序分析(static timing analysis,STA)方法，将整个待测电路设计划分成多个时序路径，计算电子信号沿每条路径的传输时间，进而判断最终的待测电路是否能正常工作。在STA工具把设计的待测电路划分为多组时序路径后，对于每组时序路径，STA工具会分别计算时钟路径和数据路径上的基本单元和连线的延时。SETUP时序检查要求时序器件输入的数据信号要在时钟沿到来一段时间前到达，HDLD时序检查要求时序器件输入数据信号要在时钟沿到达后一段时间保持不变。默认情况下，STA工具假设信号传输经过一组时序路径需要经过一个时钟周期，因此，SETUP检查时，STA工具会考虑尽可能最大的数据延时与最小的时钟延时。HDLD检查时，STA工具会考虑最小的数据延时和最大的时钟延时。
这样，为了保证时序检查可以覆盖所有的时序违例场景，所有场景都需要在STA的场景覆盖范围内。因此，在确定时序裕量时，往往都会添加部分裕量，即，将时序裕量估计的偏高。或者，在sign off策略部分流程缺乏较成熟的技术支持以及较多历史积累的情况下，尤其在较新的工艺下，为保证最终的投片成功率及良率，往往会对应增加较多的时序裕量。但是，这样就容易导致实际分析的过于悲观，从而影响最终芯片的面积、功耗、性能及成本。
为此，本发明实施例提出一种时序裕量确定方法。下面对该时序裕量确定方法进行详细说明。
图1是本发明实施例提供的一种时序裕量确定方法的步骤流程图，该方法可以应用于测试电路系统，所述测试电路系统中包括第一模拟电路及延时引入电路，所述第一模拟电路用于模拟第一待测芯片中的电路，所述延时引入电路用于为所述第一模拟电路引入时序延时，如图1所示，所述方法可以包括：
步骤101、接收测试配置信息。
本发明实施例中，第一模拟电路的具体结构及延时引入电路的具体结构可以是根据实际需求设置的。示例的，可以根据待测芯片中包含的电路结构，生成第一模拟电路。其中，待测芯片可以为一个或多个，待测芯片中可以包含当前需要测试的第一待测芯片，各个待测芯片中的电路结构可以不同。这样，通过第一模拟电路可以实现对多个待测芯片的测试，进而提高所覆盖的测试场景。进一步地，可以选用能够增加延时的元器件构建延时引入电路，使得将延时引 入电路接入第一模拟电路时，可以增大第一模拟电路的延时，进而起到引入时序延时的作用。
进一步地，测试配置信息的具体内容可以是根据当前的实际测试需求设置的。示例的，测试配置信息可以用于指示当前具体要对哪个链路进行测试。其中，链路指的是待测芯片中的电路，链路可以由多个连接的元器件组成。测试配置信息可以是用户输入的。示例的，用户可以在需要对某个链路进行测试的情况下，输入相应的测试配置信息。测试电路系统在接收到该测试配置信息之后，可以确认当前需要测试时序裕量，相应地，可以根据该测试配置信息进行后续的步骤。当然，具体实施时，还可以基于输入总线单独给出一个测试开始信号，测试电路系统在收到该测试开始信号之后，再根据该测试配置信息进行后续的步骤，进而降低误操作的概率。
步骤102、根据所述测试配置信息，确定所述第一模拟电路中的当前待测链路。
示例的，可以将测试配置信息所指示的第一模拟电路中的链路作为当前待测链路，以确保后续测试的链路为用户当前需要测试的链路。
步骤103、对所述当前待测链路进行调整，和/或，基于所述延时引入电路为所述当前待测链路引入时序延时，以使所述第一模拟电路出现时序违例。
本发明实施例中，对当前待测链路进行的调整操作，可以是能够改变当前待测链路的时序延时的操作。例如，可以是调整当前待测链路的相关参数。基于延时引入电路为当前待测链路引入时序延时，可以是为当前待测链路加入延时引入电路。通过改变当前待测链路的时序延时，使得当前待测链路可以逐渐向时序违例靠近，相应地，可以不断对当前待测链路进行调整，或者，不断改变加入的延时引入电路的长度，以使当前待测链路最终出现时序违例。
步骤104、在所述当前待测链路出现时序违例时，确定所述当前待测链路的目标时序裕量。
本发明实施例中，可以在当前待测链路刚出现时序违例时确定当前待测链路的目标时序裕量。其中，确定的目标时序裕量可以为能够修正时序违例的最小时序裕量，即，使得刚好出现时序满足的最小时序裕量。这样，一定程度上可以在使确定的目标时序裕量更贴近真实情况的同时，确保后续使用该目标时序裕量配置电路，使得实际使用时电路中存在足够的安全空间，确保电路时序收敛。
综上所述，本发明实施例提供的时序裕量确定方法，基于测试配置信息，从测试电路系统的第一模拟电路中确定出当前待测试链路，然后，通过对当前待测链路进行调整，和/或，基于延时引入电路为当前待测链路引入时序延时，以使第一模拟电路出现时序违例。最后，在当前待测链路出现时序违例时，确定当前待测链路的目标时序裕量。这样，通过预先设计测试电路系统，在实际电路中测量待测链路实际出现时序违例时的目标时序裕量，一定程度上可以使确定的目标时序裕量更贴近真实情况，进而可以提高目标时序裕量的准确性，避免由于直接设置较高的时序裕量导致最终生成的芯片的面积较大，功耗较高的问题。同时，通过避免最终生成的芯片的面积较大及功耗较高，可以降低生产成本，提高芯片性能。
可选的，本发明实施例中的测试电路系统可以设置在电路板上。由于电路实际运行使用时，会受到外界因素的影响，例如，受到实际工作温度、实际工作电压的影响。因此，相较于仅通过对电路设计进行逻辑分析，确定时序裕量的方式，本发明实施例中通过将测试电路系统设置在真实的电路板上，一定程度上可以使得测试过程可以兼顾到外界因素的影响，进而一定程度上可以使得最终确定的目标时序裕量能够更加贴近后续使用时的真实情况，进而提高目标时序裕量的准确性。
进一步地，本发明实施例中的测试电路系统可以与第一待测芯片中的电路设置在同一电路板上，即，第一待测芯片中的电路可以也设置在前述电路板上。示例的，可以在设计好第一待测芯片的电路之后，进行芯片回片，即，先生产部分用于测试的测试芯片，其中，该测试芯片中可以包含测试电路系统，即，将测试电路系统放入到相应的芯片设计中，进而实现将测试电路系统与第一待测芯片中的电路设置在同一电路板上。相应地，在后期测试时，可以基于测试电路系统内建自测试，对该测试电路的数据结果进行分析后，充分分析工艺和设计裕量，为现有芯片的工作条件设置和后续芯片的设计提供指导。进一步地，还可以同时对多个电路板上的待测芯片的电路进行测试，进而实现量产测试，方便后期基于测试结果进行电路调整。
本发明实施例中，通过进一步将测试电路系统与第一待测芯片中的电路设置在同一电路板上，可以使得测试过程可以兼顾到第一待测芯片运行时的整体情况，进而一定程度上可以提高贴近后续使用时的真实情况的贴近程度，进而进一步提高目标时序裕量的准确性。
可选的，本发明实施例中的第一模拟电路可以包括m个链路组，一个链路组中可以包括n个可用链路，可用链路可以用于模拟第一待测芯片中的第一链路，测试配置信息可以包括组选择信息。其中，测试配置信息可以是中央处理器(Central Processing Unit/Processor，CPU)或外部控制软件通过控制外围总线(Advanced Peripheral Bus，APB)输入的。
进一步地，m，n可以为正整数，m，n的具体值可以根据实际需求设置，本发明实施例对此不作限定。示例的，n可以为128，即，内部可以以128条可用链路(Chain)作为一个链路组。由于可用链路及链路组的数目可配置，结构可调整，因此，使得在构建第一模拟电路时，可以综合考虑实际时序分析流程的各项因素对时序裕量的影响，灵活性较高。
进一步地，本发明实施例中第一模拟电路中包含的元器件以及元器件之间的连接方式可以根据第一待测芯片中包含的元器件以及元器件之间的连接关系设置。这样，可以确保第一模拟电路能够准确的模拟第一待测芯片中的电路，进而确保测试得到的时序裕量的准确性。当然，还可以进一步结合芯片的工艺分析结果，sign off策略等多个维度确定第一模拟电路中组合逻辑单元类型。进一步地，第一链路可以为第一待测芯片包含的链路中使用频率大于预设频率阈值和/或结构复杂度小于预设复杂度阈值的链路。其中，预设频率阈值以及预设复杂度阈值可以根据实际需求设置。第一待测芯片包含的链路的使用频率可以是根据该链路所要实现的实际功能预估的，示例的，在所实现的实际功能为较为常用的功能时，链路的使用频率可以越高。结构 复杂度可以根据链路中包含的元器件的数量、种类以及元器件之间的连接关系确定。示例的，在数量越多、种类越多、元器件之间的连接关系越复杂的情况下，链路的结构复杂度越高。具体实施时，可以先根据预设频率阈值和/或预设复杂度阈值，确定出第一链路。然后基于第一链路的中包含的元器件以及元器件之间的连接方式，构建第一模拟电路。示例的，可以构建包含相同元器件及相同连接方式的第一模拟电路，以评估实际场景下实际电路的时序裕量。
本发明实施例中，通过仅以第一模拟电路模拟第一待测芯片中使用频率大于预设频率阈值和/或结构复杂度小于预设复杂度阈值的链路，一定程度上可以在实现对第一待测芯片进行时序测试的同时，增大测试结果的可复用程度，以及降低实现难度以及实现成本。同时，可以在确保相对复杂度较低的同时，实现尽可能多的时序电路场景的覆盖。
可选的，本发明实施例的一种实现方式中，上述根据测试配置信息，确定第一模拟电路中的当前待测链路的步骤，可以包括下述步骤：
S11、从所述测试配置信息中读取所述组选择信息。
本步骤中，组选择信息可以为能够唯一指示链路组的信息。示例的，组选择信息可以组名称、组编号，等等。具体实施时，可以先对测试配置信息进行解析，然后从中读取组选择信息。
S12、从所述m个链路组中选择所述组选择信息指示的链路组，作为所述当前待测试链路组；所述当前待测试链路组中的可用链路为所述当前待测链路。
本步骤中，可以将各个链路组的组信息与组选择信息进行匹配，将组信息与该组选择信息相匹配的链路组即为组选择信息指示的链路组。示例的，可以将各个链路组的组编号与组选择信息表征的组编号进行匹配，将组编号相匹配的链路组确定为当前待测试链路组。
本发明实施例中，通过将第一模拟电路设置为链路组的形式，这样，用户仅需在测试配置信息中设置用于指示要测试的链路组的组选择信息即可实现对特定链路组的测试，进而一定程度上提高操作的便捷性。同时，在确定当前待测链路时，仅需读取组选择信息，直接根据组选择信息即可确定出当前待测试链路，进而一定程度上可以提高确定当前待测链路的确定效率。
可选的，本发明实施例的一种实现方式中，上述基于延时引入电路为当前待测链路引入时序延时的操作，可以包括下述步骤：
S21、调整所述延时引入电路接入所述当前待测链路的链路长度；其中，不同链路长度对应引入的时序延时不同。
具体在调整接入的链路长度时，可以是调整延时引入电路中接入当前待测链路的元器件的数量。示例的，可以在第一模拟电路与延时引入电路之间设置多路选择器，基于控制信号实时控制该多路选择器，进而实现实时控制接入当前待测链路的链路长度。其中，不同的控制信号可以指示不同的长度。这样，由于多路选择器的控制信号在实际电路中实时进行调节，从而可以达到调整当前待测链路的延时的目的。
本发明实施例中，通过调整延时引入电路接入当前待测链路的链路长度，即可实现引入不 同的时序延时，进而一定程度上可以确保引入时序延时的效率。同时，由于接入链路长度所耗费的时长往往较短，因此，调整接入长度的方式一定程度上可以较为平稳的改变电路延时，进而使得电路从时序满足向时序违例状态平滑过度。
可选的，本发明实施例的一种实现方式中，延时引入电路中的元器件可以包括缓冲器和/或反向器。采用缓冲器、反向器组成延时引入电路可以在实现引入延时的同时，一定程度上避免延时引入电路的结构过于复杂以及成本较高的问题，进而降低实现难度。进一步地，延时引入电路中元器件的总数量可以与第一模拟电路所需支持的最大工作频率正相关。这样，通过设置延时引入电路中元器件的总数量与第一模拟电路所需支持的最大工作频率正相关，一定程度上可以确保延时引入电路能够覆盖较大的测试范围，进而能够确保通过调节延时引入电路可以使得第一模拟电路进入时序违例，进而确保测试效果。
可选的，本发明实施例中的测试配置信息中还可以包括初始链路长度信息。初始链路长度信息可以表征初始链路长度。相应地，调整延时引入电路接入当前待测链路的链路长度的操作，可以包括：
S21A、将所述链路长度设置为所述初始链路长度信息所指示的初始链路长度。
本步骤中，可以先确定初始链路长度信息所指示的初始链路长度，然后将接入当前待测链路的链路长度设置为初始链路长度，以在该初始链路长度下对当前待测链路进行测试。示例的，假设初始链路长度为3，那么可以改变当前待测链路与延时引入电路之间的连接关系，以使延时引入电路中的3个元器件接入当前待测链路中。相应地，可以检测当前情况下，是否出现时序违例。
S21B、若所述初始链路长度下所述当前待测链路未出现时序违例，则根据所述初始链路长度生成目标链路长度，并将所述链路长度设置为所述目标链路长度，直至所述当前待测链路出现时序违例。
如果初始链路长度下当前待测链路未出现时序违例，则说明接入当前待测链路的链路长度还需要继续调整。相应地，可以进一步将接入的链路长度设置为目标链路长度。进一步地，如果本次设置的目标链路长度也不足以使当前待测链路出现时序违例，则可以重新确定新的目标链路长度，并继续进行调整，直到出现时序违例为止。
本发明实施例中，仅需给出初始链路长度信息，即可控制将链路长度调整为不同值进行测试，这样，一定程度上可以提高测试操作的便捷性，进而提高测试效率。
进一步地，在生成目标链路长度时，可以先确定当前待测的目标时序裕量的类型，若所述目标时序裕量的类型为建立时序裕量，则对初始链路长度进行递增处理，得到至少一个目标链路长度。若目标时序裕量的类型为保持时序裕量，则对初始链路长度进行递减处理，得到至少一个目标链路长度。具体的，进行递增处理时，可以是为初始链路长度增加一个固定值，得到一个目标链路长度。相应地，如果本次生成的目标链路长度不足以使当前待测链路出现时序违 例，则为初始链路长度再增加一个固定值，以继续生成目标链路长度。示例的，假设初始链路长度为3，固定值为1，那么可以生成目标链路长度4。如果本次生成的目标链路长度4不足以使当前待测链路出现时序违例，则可以在上一轮更新后的初始链路长度的基础上，再增加一个固定值1，生成目标链路长5，以此类推，直至当前待测链路出现时序违例。进行递减处理时，可以是为初始链路长度减去一个固定值，得到一个目标链路长度。相应地，如果本次生成的目标链路长度不足以使当前待测链路出现时序违例，则为初始链路长度再减去一个固定值，以继续生成目标链路长度。示例的，假设初始链路长度为5，固定值为1，那么可以生成目标链路长度4。如果本次生成的目标链路长度4不足以使当前待测链路出现时序违例，则可以在上一轮更新后的初始链路长度的基础上，再减去加一个固定值1，生成目标链路长3，以此类推，直至当前待测链路出现时序违例。需要说明的是，具体实施时，可以是由控制模块按照预定义的顺序对于长度选择信号进行递增或递减扫描，进而实现递增处理或递减处理。长度选择信号中的长度信息可以是根据预设的sign off策略设定的。这样，通过调整上午时序分析signoff策略和约束设置，针对不同的预设的sign off策略，无需调整测试环境，可以较为快速的测试不同类型signoff条件下的时序裕量，从而减少测试量。
本发明实施例中，通过先确定目标时序裕量的类型，针对不同的类型，进行对应的递增处理或递减处理，来实现生成目标链路长度。这样，可以确保生成的目标链路长度能够匹配当前的测试场景，进而可以确保不断生成的目标链路长度能够增大/缩小电路延时，使当前待测链路最终出现SETUP模式下的时序违例/HOLD模式下的时序违例，确保测试效果。
可选的，本发明实施例的一种实现方式中，上述对所述当前待测链路进行调整的操作，可以包括下述步骤：
S31、调节所述当前待测链路的工作频率，以改变所述当前待测链路中的时序延时。
本步骤中，当前待测链路的工作频率即为当前待测链路的工作时钟频率。一般，时序延时的要求会受到工作时钟频率的影响，不同工作时钟频率下，当前待测链路的时序延时要满足的要求不同。例如，在工作时钟频率越大的情况下，当前待测链路的时序延时可以越短。需要说明的是，电路的工作时钟周期与工作时钟频率相关，工作时钟频率越高，工作时钟周期可以越小。相应地，在采用上述调整延时引入电路接入当前待测链路的链路长度，以引入时序延时的方式下，可以将当前待测链路的工作频率设置为预设固定频率，以确保由当前待测链路的工作时钟周期引起的延时数值，在时序路径中占据总延时的较大比例，进而确保测试效果。本发明实施例中，通过当前待测链路的工作频率，即可使当前待测链路的时序延时满足不同的要求，进而一定程度上可以确保引入效率。
可选的，本发明实施例的一种实现方式中，测试配置信息中还可以包括工作频率信息，相应地，上述调节所述当前待测链路的工作频率的操作，可以包括：
S31A、将所述延时引入模式的链路长度设置为预设的固定值，并将所述当前待测链路的工 作频率设置为所述工作频率信息所指示的频率。
本发明实施例中，预设的固定值可以是根据实际需求设置，示例的，预设的固定值可以采用预设的sign off配置的数值，本发明实施例对此不作限定。进一步地，先确定工作频率信息所指示的频率，然后将当前待测链路的工作频率设置为所指示的频率，以在该工作频率下对当前待测链路进行测试。
S31B、在接收到新的测试配置信息时，将所述当前待测链路的工作频率设置为所述新的测试配置信息中包括的工作频率信息所指示的频率。
本发明实施例中，可以在外部采用锁相环(Phase-Locked Loop，PLL)调频进行频率的遍历扫描，在以上一个工作频率下对当前待测链路进行测试之后，外部更新工作时钟频率，重新开始下一次的扫描，以输入携带更新的工作时钟频率的新的测试配置信息。这样，通过实时的不断调整工作频率，使得当前待测链路从时序满足向时序违例状态平滑过度。其中，HOLD模式往往不受频率影响，即，在调频模式下不受影响，因此，本步骤可以是在SETUP模式进行的，SETUP模式下每次重新设置的工作时钟频率可以越来越小，以改变电路延时，进而使电路出现SETUP模式下的时序违例。
本发明实施例中，仅需接收测试配置信息，基于测试配置信息中指定的工作频率，即可实现调整工作频率。这样，一定程度上可以提高测试操作的便捷性，进而提高测试效率。
可选的，本发明实施例的测试电路系统中还可以包括标准器件链路，具体的，可以是第一模拟电路中设置有标准器件链路，例如，第一模拟电路中设置有以标准器件链路作为可用链路的链路组。一条标准器件链路可以对应一种标准元器件，即，可以根据标准器件的不同维度，串成多种单个类型的组合逻辑单元链作为标准器件链路，用于分别分析不同标准器件的时序裕量。进一步地，标准元器件可以为第一待测芯片中各个第二链路中包含的元器件。其中，第二链路可以为第一待测芯片中除第一链路之外的链路。示例的，第二链路可以为使用频率较小，结构复杂度较高的链路。相应地，在所述当前待测链路为所述标准器件链路的情况下，确定所述当前待测链路的目标时序裕量的操作可以包括以下步骤：
S41、根据所述标准器件链路出现时序违例时所使用的工作频率，确定所述标准元器件对应的单个延时值。
对于任一标准器件链路，在以标准器件链路作为当前待测链路时，可以通过调节标准器件链路的工作频率，以改变标准器件链路中的时序延时，直至标准器件链路出现时序违例。或者，也可以是改变接入的延时引入电路的长度，以使标准器件链路出现时序违例。
进一步地，可以在标准器件链路刚好出现时序违例时，记录当前使用的工作频率。由于标准器件链路中均为同一类型的元器件，时钟偏斜(skew)较小，因此，本发明实施例中可以先确定标准器件链路当前所使用的工作频率对应的周期时长，然后计算周期时长与标准器件链路中标准元器件数量的比值，得到标准元器件对应的单个延时值。即，以工作周期近似换算链路 延时。具体的，可以将当前所使用的工作频率的倒数作为对应的周期时长，然后获取标准器件链路中标准元器件数量，例如，可以直接从标准器件链路的配置信息中读取标准元器件数量。最后，可以计算周期时长除以标准元器件数量的值，得到标准元器件对应的单个延时值。这样，通过计算周期时长与标准元器件数量的比值，即可得到标准元器件对应的单个延时值，一定程度上可以提高测试效率。同时，通过计算出标准元器件对应的单个延时值，可以为后期进行时序裕量调整时，提供较为客观准确的削减标准。
S42、根据各个所述标准元器件对应的单个延时值，确定所述第二链路的目标时序裕量。
本步骤中，由于各个标准元器件对应的单个延时值是在标准器件链路刚好出现时序违例时确定的，因此，标准元器件对应的单个延时值一定程度上可以作为避免标准器件链路出现时序违例的参照标准。相应地，可以根据标准元器件对应的单个延时值，确定第二链路的目标时序裕量。
在一种现有实现方式中，是直接根据模拟电路进行测试方案，但是模拟电路测试的设计较为复杂，因此，实现难度较大。本发明实施例中，以第二链路中包含的元器件构建标准器件链路，基于标准器件链路确定标准元器件对应的单个延时值，然后，根据各个标准元器件对应的单个延时值，确定第二链路的目标时序裕量，可以扩大测试电路系统所能覆盖的测试场景。同时，先测试标准元器件对应的单个延时值，基于标准元器件对应的单个延时值确定第二链路的目标时序裕量的方式，可以省略按照第二链路中元器件的连接关系在第一模拟电路中预先构建用于模拟第二链路的链路组的操作，进而一定程度上可以降低实现难度，节约实现成本。
可选的，本发明实施例的一种实现方式中，根据各个所述标准元器件对应的单个延时值，确定所述第二链路的目标时序裕量的操作，可以包括：
S42A、基于预设的时序仿真算法，测试所述第二链路的时序裕量，得到待修正时序裕量。
本步骤中，预设的时序仿真算法可以是根据实际需求选择的现有算法，本发明实施例对此不作限定。示例的，预设的时序仿真算法可以为STA算法，相应地，可以基于STA工具对第二链路进行时序分析，进而得到待修正时序裕量。
S42B、根据各个所述标准元器件对应的单个延时值，确定所述第二链路中包括的元器件对应的单个延时值。
本步骤中，对于任一条第二链路，可以先确定该条第二链路中包含的具体元器件。然后从所有标准元器件对应的单个延时值中，查找该条第二链路中包含的各个元器件对应的单个延时值。
S42C、根据所述第二链路中包括的元器件对应的单个延时值，对所述待修正时序裕量进行修正，得到所述第二链路的目标时序裕量；其中，所述第二链路的目标时序裕量小于所述待修正时序裕量。
由于时序仿真算法计算得到的往往会预估的较高，因此，本步骤中可以以单个延时作为调 整标准，对待修正时序裕量进行修正，以得到更为准确的目标时序裕量。
本发明实施中，先确定待修正时序裕量，然后根据第二链路中包括的元器件对应的单个延时值，对待修正时序裕量进行修正，获取第二链路的目标时序裕量的方式中，由于元器件对应的单个延时值是在实际电路中测试得到的，因此以单个延时值作为修正标准一定程度上可以确保修正精度。相应地，相较于随机修正，使用单个延时值作为修正标准进行修正的方式更加可靠，进而一定程度上可以使得修正后的第二链路的目标时序裕量更加准确，进而可以节省后期达到时序收敛所需的时间。
可选的，本发明实施例提供的时序裕量确定方法还可以包括以下步骤：
S51、对于所述第一待测芯片中的各个第一待测链路，根据预设的时序仿真算法，确定所述第一待测链路对应的基础时序裕量；所述第一待测链路包括所述第一链路和/或所述第二链路。
本步骤中，预设的时序仿真算法可以是根据实际需求选择的现有算法，本发明实施例对此不作限定。示例的，可以基于STA工具对第一待测链路进行时序分析，进而得到基础时序裕量。
S52、计算所述基础时序裕量与所述第一待测链路对应的目标时序裕量之间的裕量差值。
对于每个第一待测链路，可以计算基础时序裕量与目标时序裕量之间差值，得到裕量差值。其中，该裕量差值可以体现时序分析场景下对应的基础时序裕量与实际场景中下的目标时序裕量之间的裕量差异。
S53、对于第二待测芯片中的第二待测链路，根据所述预设的时序仿真算法确定所述第二待测链路的基础时序裕量。
本步骤中，第二待测芯片可以为需要进行测试的芯片，第二待测芯片可以与第一待测芯片为同一芯片。相应地，在一种实现方式中，可以以第二链路作为S51中的第一待测链路，以第一待测芯片中的第一链路作为第二待测链路，基于本实施例提供的步骤确定出第一链路的目标时序裕量。当然，第二待测芯片也可以与第一待测芯片为不同的芯片，本发明实施例对此不作限定。进一步地，根据预设的时序仿真算法确定第二待测链路的基础时序裕量的实现方式可以参照前述相关描述，此处不再赘述。
需要说明的是，本发明实施例中还可以以时序裕量差值作为因变量，以时序路径的延时，芯片变化度(On Chip Variations，OCV)，串扰(crosstalk)，时钟不确定性(uncertainty)等因素作为自变量，拟合目标函数。通过该目标函数可以确定signoff过程中，一条时序路径对应的各个signoff变量和最终的时序裕量(margin)的关系，为signoff策略提供参考。
S54、根据各个所述裕量差值，确定所述第二待测链路对应的修正裕量差值，并根据所述修正裕量差值对所述第二待测链路的基础时序裕量进行修正，得到所述第二待测链路的目标时序裕量。
具体的，可以是先计算所有裕量差值的均值，得到标准裕量差值，直接将标准裕量差值确定为第二待测链路对应的修正裕量差值。这样，仅需执行平均值计算操作，即可确定出修正裕 量差值，一定程度上可以提高确定效率。
进一步地，根据修正裕量差值进行修正时，可以计算第二待测链路的基础时序裕量与修正裕量差值之间的差值，进而得到第二待测链路的目标时序裕量。
本发明实施例中，通过预设的时序仿真算法确定第一待测链路在时序分析场景下对应的基础时序裕量，然后计算基础时序裕量与实际场景中下确定的目标时序裕量之间的裕量差值。后续在确定第二待测芯片中第二待测链路的时序裕量时，结合实际场景与时序分析场景的裕量差异作为参照，根据预设的时序仿真算法确定的第二待测链路的基础时序裕量进行修正，获取第二待测链路的目标时序裕量。这样，通过结合实际场景与时序分析场景的裕量差异为后续确定时序裕量的操作提供参照，一定程度上可以提高确定效率以及准确性。
可选的，本发明实施例的一种实现方式中，上述在所述当前待测链路出现时序违例时，确定所述当前待测链路的目标时序裕量的操作，可以包括：
S61、对于所述当前待测链路中的任一元器件，根据所述元器件对应的时钟路径及数据路径，计算所述元器件对应的时序裕量。
具体的，可以在测试电路系统所在的电路板上检测时钟路径及数据路径。其中，数据路径可以表示数据到达元器件的时间。时钟路径可以表示时钟到达时间。然后基于预设的计算公式，根据时钟路径及数据路径计算元器件对应的时序裕量。例如，将时钟路径减去数据路径得到的差值与时钟周期之和作为建立时序裕量，将数据路径减去时钟路径得到的差值作为保持时序裕量。
S62、根据所述元器件对应的时序裕量，确定所述当前待测链路的第一时序裕量。
示例的，可以将当前待测链路包含的元器件对应的时序裕量的均值作为第一时序裕量。当然，也可以采用其他方式，例如，将当前待测链路包含的元器件对应的时序裕量中的最大值作为第一时序裕量，本发明实施例对此不作限定。需要说明的是，在另一种实现方式中，也可以直接将第一时序裕量确定为当前待测链路的目标时序裕量，这样，一定程度上可以简化处理步骤，进而降低处理成本。
S63、根据预设的时序仿真算法，确定所述当前待测链路对应的第二时序裕量。
本步骤的具体实现方式可以参照前述相关描述，此处不再赘述。需要说明的是，本步骤的执行顺序并不唯一，实际应用时还可以预先执行本步骤得到第二时序裕量。
S64、根据所述的第二时序裕量、所述第一时序裕量以及所述第二时序裕量与所述第一时序裕量之间的差值，确定所述当前待测链路的目标时序裕量；其中，所述当前待测链路的目标时序裕量小于所述第二时序裕量且不小于所述第一时序裕量。
示例的，可以直接将第二时序裕量与该差值之差作为当前待测链路的目标时序裕量。或者，也可以在差值较大，例如，大于预设阈值的情况下，将第二时序裕量与第一特定值之差作为当前待测链路的目标时序裕量。在差值较小，例如，不大于预设阈值的情况下，将第二时序裕量 与第二特定值之差作为当前待测链路的目标时序裕量。其中，第一特定值大于第二特定值。当然，也可以是采用其他方式确定，本发明实施例对此不作限定。
本发明实施例中，通过预设的时序仿真算法确定当前待测链路在时序分析场景下对应的第二时序裕量，根据第二时序裕量与实际场景中下确定的第一时序裕量之间的差值，确定当前待测链路的目标时序裕量。这样，结合实际场景与时序分析场景之间的裕量差异，确定当前待测链路的目标时序裕量，一定程度上可以确保确定的目标时序裕量的准确性。同时，通过对比第二时序裕量以及第一时序裕量确定目标时序裕量，可以较为快速的确定出目标时序裕量。
可选的，本发明实施例中测试电路系统中还可以包括与第一模拟电路连接的时序违例捕获电路。相应地，本发明实施例中可以通过下述步骤确定当前待测链路出现时序违例：
S71、获取所述时序违例捕获电路的输出值；所述时序违例捕获电路的输出值用于表征所述第一模拟电路是否出现时序违例。
其中，时序违例捕获电路可以包括第一捕获电路及第二捕获电路。第一捕获电路包括并行的第一寄存器、第一锁存器以及异或门，该异或门用于对第一寄存器的输出及述第一锁存器的输出进行异或运算。第二捕获电路可以包括并行的第二寄存器、第二锁存器以及同或门，该同或门用于对第二寄存器的输出及第二锁存器的输出进行同或运算。相应地，在获取时序违例捕获电路的输出值时，可以在当前待测的目标时序裕量的类型为建立时序裕量的情况下，获取第一捕获电路的输出值。在当前待测的目标时序裕量的类型为保持时序裕量的情况下，获取第二捕获电路的输出值。由于锁存器具备电平敏感的特性，因此，本发明实施例中，通过设置捕获电路，可以基于捕获电路捕获时序违例时发生的异常电平，从而识别当前时序路径是否出现时序违例。
示例的，图2是本发明实施例提供的一种部分电路结构示意图，如图2所示，其中，其test_in表示输入信号、test_en表示使能信号、clk表示时钟信号、rst_in表示置位、chain_sel表示链长选择信号。01表示当前待测链路，02表示延时引入电路，03表示第一捕获电路。03中异或门的异或结果，即第一捕获电路的输出值，可以保存至异或门后边连接的寄存器。相应地，获取第一捕获电路的输出值时，可以直接读取寄存器中的数值，进而得到输出值。
进一步地，图3是本发明实施例提供的一种波形示意图，时序违例捕获电路的输出可以如图3所示，其中，第一行可以表示第一捕获电路的波形，第二行可以表示第二捕获电路的波形。Q1为第一个寄存器的输出端口波形，D2为第二级并行的寄存器与锁存器的输入端口波形，Qlatch为锁存器输出波形，QFF为并行的寄存器输出波形，vio表示两者的组合逻辑输出，即，输出值。
在SETUP模式下，数据应该要在寄存器的建立时间之前到达，因此，在时序满足的情况下，锁存器和寄存器会采集到同样的信号，相应地，异或结果输出为0。在时序违例的情况下，由于寄存器采集信号会延后一拍，进而会使得异或结果输出1。在HOLD测试模式下，在时序满足 的情况下，锁存器和寄存器会采集到不同的信号，相应地，同或结果输出为0。在时序违例的情况下，由于寄存器采集信号提前一拍，进而会使得同或结果输出1。
S72、在所述输出值为特定值的情况下，确定所述当前待测链路出现时序违例。
示例的，特征值可以为1，可以在输出值为1的情况下，确定当前待测链路出现时序违例。
本发明实施例中，通过设置时序违例捕获电路，获取时序违例捕获电路的输出值，基于输出值即可确定当前待测链路是否出现时序违例。这样，一定程度上可以增大检测是否出现时序违例的便捷性，提高测试效率。
进一步地，本发明实施例还可以在确定出当前待测链路出现时序违例的情况下，上报检测结果。其中，该检测结果中可以包括当前待测链路出现时序违例时延时引入电路的当前链路长度。进一步地还可以包括当前待测链路对应的链路组的组选择信息。这样，通过上报检测结果，可以方便后期环节确定出现时序违例的链路具体是在什么样的形态下出现问题的，进而可以方便后期进行数据分析。
需要说明的是，本发明实施例中各个步骤的实现逻辑可以是基于数字逻辑设计实现的。示例的，可以基于脚本编译生成硬件描述语言(verilog)代码实现，进而可以较为便捷的实现时序裕量确定方法实施例中的各个步骤。在具体设计时，还可以结合现有的分析流程，例如STA分析流程进行设计，以使本发明实施例中的测试电路系统可以支持STA流程，进而提高可移植性。
进一步地，实际场景中芯片制造往往依赖于集成电路工艺制造技术的发展，而集成电路通常通过无数的纳米级别的晶体管堆积而成，晶体管通常为cmos类型。其中，晶体管包括栅极(gate)，源级(source)，漏级(drain)。gate施加电压后，即可控制从source到drain的电流通断。随着栅极越短，电流通过速度越快，因此，随着工艺升级，栅极越做越短。工艺也不断发生更新，例如，为了解决20nm以下的制造工艺存在漏电问题，研发出场效应晶体管(Fin Field-Effect Transistor，FinFET)。由于工艺不断更新，之前工艺下的裕量值或裕量方案难以应用于更先进的工艺，因此如何在新工艺下迅速获取相应的时序裕量，以形成成熟的时序分析sign off策略，成为一个难点。
而本发明实施例中提出的时序裕量确定方法受到制造工艺的影响较小，可较为快速的移植到其他工艺下。因此，可以应用于超大规模集成电路设计中分析特定工艺下的时序裕量。例如，本发明实施例中的测试电路系统可以应用于不同制造方不同精度工艺下的超大规模集成电路芯片检测，应用范围较广，设计方便简单灵活。这样，可以在提高制造工艺，充分利用工艺的性能的同时，提高集成电路时序收敛效率以及集成电路工作的性能和质量。同时，通过较为高效的确定达到时序收敛，一定程度上也可以降低集成电路的生产和设计成本。进一步地，在一种现有实现方式中，往往是基于作为时序违例的示警电路，或自适应的电路设计，例如，自适应电压缩放(AVS)控制器，根据该类测试电路的时序违例情况，动态调整芯片的电压或频率，保证芯片正常工作。但是，这种数字电路测试方案中也是建立在添加更多的时序裕量的基础上。 过预先设计测试电路系统，在实际电路中测量待测链路实际出现时序违例时的目标时序裕量，一定程度上可以使确定的目标时序裕量更贴近真实情况，进而可以提高目标时序裕量的准确性。
进一步地，图4是本发明实施例提供的一种测试电路系统的模块设计示意图，如图4所示，其中，SMT_GROUP_INTR表示输出的中断信号，TCK、SMT_PCLK及CLK_SYS表示时钟信号。CLK_SYS是测试过程中使用的时钟信号，TCK及SMT_PCLK为系统的协议时钟信号。IPTEST_MODE_EN用于选择模式。APB FROM ACPU_NOC表示输入的测试配置信息。APB_Mux2表示高级外围总线多路复用器。DAP表示JTAG信号的输入接口。
SMT_PGCC表示激励产生与捕获模块，SMT_REG表示配置模块，CHAIN_WRAP_TOP表示延时链模块，SMT_MUX和SMT_RPT表示报告梳理模块，IPTEST_DAP2APB表示接口模块。
进一步地，IPTEST_DAP2APB模块可以用于在IPTEST模式下将JTAG输入信号转成符合APB协议的配置信息。也可以在非IPTEST模式下，直接通过APB接口输入配置信息，此时输出信号可以作为APB SLAVE配置接口。进一步地，SMT_REG模块也可以作为APB SLAVE配置接口，完成SMT相关配置输入，以及测试结果的输出。
SMT_PGCC模块可以完成APB时钟域参数到系统时钟域的转换。且在接收到测试开始信号后，根据配置信息选择当前的测试配置，按照相应的工作模式，输出公共的链长选择信号和测试激励与使能信号，并按照顺序使能特定链路。且在完成测试后上报测试中断。使能信号可以用于控制待测链工作，使能信号可以输出给对应的链路组。当某个链路组进行测试时，其他组内的使能信号固定无效，进而避免其他组对当前测试产生干扰。测试激励用于表征本轮测试使用多少宽度的信息。输出测试激励时，可以由第一个寄存器采集到输入的电平脉冲数据，由下一个周期作为起点发送采集到的数据。具体的测试激励可以根据当前的测试模式给出，每个测试模式对应的测试激励的内容可以预先设定的。具体的，SMT_PGCC可以发出脉冲信号传到CHAIN_WRAP_TOP模块里边。CHAIN_WRAP_TOP模块可以为所有测试链的顶层模块，CHAIN_WRAP_TOP模块中可以包括链路组。其中，图4所示的CHAIN_WRAP_TOP模块中包括的4个方框表示4个链路组，方框中的内容可以表示链路组的标识。实际应用时，可以根据实际测试需求，构建任意多个组用于测试。
进一步地SMT_MUX模块可以根据SMT_REG配置的组选择信息，上报检测结果。SMT_RPT模块可以包括用于存储待测链路的上报结果的锁存寄存器，采集电路可以根据当前工作模式将电平信号或出现时序违例时延时引入电路的当前链路长度输出到寄存器，寄存器可以根据待测链路对应输出的违例信号，锁存出现时序违例时延时引入电路的当前链路长度以及违例电平信号。同时根据违例电平信号控制对应测试链的使能信号无效，以使待测链路在出现时序违例时停止工作。基于本发明实施例提供的测试电路系统，可以基于SMT_PGCC较为快速的完成激励的自动生成，激励传送到CHAIN_WRAP_TOP模块以使测试链进行测试，进而实现基于预设定的测试激励，快速对多种链路进行测试。同时，最终的输出结果可以经过SMT_MUX模块，被 SMT_REG模块中的寄存器自动捕获，随后自动上报给SMT_RPT模块，最终通过总线输出到CPU或芯片外部。通过此设计，模块仅需要进行少量配置，即可在较短时间内完成较多的测试量。
需要说明的是，本发明实施例还可以在测试完成后，读出测试数据，然后基于预设脚本统计软件、人工分析等方式对测试数据进行分析，以得出统计结论。进一步地，还可以结合更准确的目标时序裕量，通过大量测试结果形成数据库，通过对该数据库进行统计分析，确定裕量调整方案，进而对改进芯片性能，功耗，面积和成本，优化时序分析signoff方式流程等提供指导。
图5是本发明实施例提供的一种时序裕量确定装置的框图，该装置可以应用于测试电路系统，所述测试电路系统中包括第一模拟电路及延时引入电路，所述第一模拟电路用于模拟第一待测芯片中的电路，所述延时引入电路用于为所述第一模拟电路引入时序延时，该装置可以包括：存储器301和处理器302。所述存储器301，用于存储程序代码。所述处理器302，调用所述程序代码，当所述程序代码被执行时，用于执行以下操作：
接收测试配置信息；根据所述测试配置信息，确定所述第一模拟电路中的当前待测链路；对所述当前待测链路进行调整，和/或，基于所述延时引入电路为所述当前待测链路引入时序延时，以使所述第一模拟电路出现时序违例；在所述当前待测链路出现时序违例时，确定所述当前待测链路的目标时序裕量。具体的，处理器302所能执行的操作、各个操作的具体实现过程以及所能达到的相应技术效果可以参照前述方法实施例中的相关描述，此处不再赘述。
进一步地，本发明实施例还提供一种测试电路系统，所述测试电路系统中包括控制电路、第一模拟电路及延时引入电路；所述第一模拟电路用于模拟第一待测芯片中的电路，所述延时引入电路用于为所述第一模拟电路引入时序延时；所述控制电路用于执行上述时序裕量确定方法实施例中的步骤。本发明实施例还提供一种可移动设备，所述可移动设备中包括芯片；所述芯片中电路的时序裕量是基于所述测试电路系统确定的。可选的，所述可移动设备为无人机、无人车、机器人中的一种或多种。进一步地，本发明实施例还提供一种计算机可读存储介质，所述计算机可读存储介质上存储计算机程序，所述计算机程序被处理器执行时实现上述时序裕量确定方法中的各个步骤，且能达到相同的技术效果，为避免重复，这里不再赘述。
以上所描述的装置实施例仅仅是示意性的，其中所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部模块来实现本实施例方案的目的。本领域普通技术人员在不付出创造性的劳动的情况下，即可以理解并实施。
本发明的各个部件实施例可以以硬件实现，或者以在一个或者多个处理器上运行的软件模块实现，或者以它们的组合实现。本领域的技术人员应当理解，可以在实践中使用微处理器或 者数字信号处理器来实现根据本发明实施例的计算处理设备中的一些或者全部部件的一些或者全部功能。本发明还可以实现为用于执行这里所描述的方法的一部分或者全部的设备或者装置程序(例如，计算机程序和计算机程序产品)。这样的实现本发明的程序可以存储在计算机可读介质上，或者可以具有一个或者多个信号的形式。这样的信号可以从因特网网站上下载得到，或者在载体信号上提供，或者以任何其他形式提供。
例如，图6为本发明实施例提供的一种计算处理设备的框图，如图6所示，图6示出了可以实现根据本发明的方法的计算处理设备。该计算处理设备传统上包括处理器710和以存储器720形式的计算机程序产品或者计算机可读介质。存储器720可以是诸如闪存、EEPROM(电可擦除可编程只读存储器)、EPROM、硬盘或者ROM之类的电子存储器。存储器720具有用于执行上述方法中的任何方法步骤的程序代码的存储空间730。例如，用于程序代码的存储空间730可以包括分别用于实现上面的方法中的各种步骤的各个程序代码。这些程序代码可以从一个或者多个计算机程序产品中读出或者写入到这一个或者多个计算机程序产品中。这些计算机程序产品包括诸如硬盘，紧致盘(CD)、存储卡或者软盘之类的程序代码载体。这样的计算机程序产品通常为如参考图7所述的便携式或者固定存储单元。该存储单元可以具有与图6的计算处理设备中的存储器720类似布置的存储段、存储空间等。程序代码可以例如以适当形式进行压缩。通常，存储单元包括计算机可读代码，即可以由例如诸如710之类的处理器读取的代码，这些代码当由计算处理设备运行时，导致该计算处理设备执行上面所描述的方法中的各个步骤。
本说明书中的各个实施例均采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似的部分互相参见即可。本文中所称的“一个实施例”、“实施例”或者“一个或者多个实施例”意味着，结合实施例描述的特定特征、结构或者特性包括在本发明的至少一个实施例中。此外，请注意，这里“在一个实施例中”的词语例子不一定全指同一个实施例。在此处所提供的说明书中，说明了大量具体细节。然而，能够理解，本发明的实施例可以在没有这些具体细节的情况下被实践。在一些实例中，并未详细示出公知的方法、结构和技术，以便不模糊对本说明书的理解。在权利要求中，不应将位于括号之间的任何参考符号构造成对权利要求的限制。单词“包含”不排除存在未列在权利要求中的元件或步骤。位于元件之前的单词“一”或“一个”不排除存在多个这样的元件。本发明可以借助于包括有若干不同元件的硬件以及借助于适当编程的计算机来实现。在列举了若干装置的单元权利要求中，这些装置中的若干个可以是通过同一个硬件项来具体体现。单词第一、第二、以及第三等的使用不表示任何顺序。可将这些单词解释为名称。最后应说明的是：以上实施例仅用以说明本发明的技术方案，而非对其限制；尽管参照前述实施例对本发明进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本发明各实施例技术方案的精神和范围。

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  1. 一种时序裕量确定方法，其特征在于，应用于测试电路系统，所述测试电路系统中包括第一模拟电路及延时引入电路，所述第一模拟电路用于模拟第一待测芯片中的电路，所述延时引入电路用于为所述第一模拟电路引入时序延时，所述方法包括：
    接收测试配置信息；
    根据所述测试配置信息，确定所述第一模拟电路中的当前待测链路；
    对所述当前待测链路进行调整，和/或，基于所述延时引入电路为所述当前待测链路引入时序延时，以使所述第一模拟电路出现时序违例；
    在所述当前待测链路出现时序违例时，确定所述当前待测链路的目标时序裕量。
  2. 根据权利要求1所述的方法，其特征在于，所述测试电路系统设置在电路板上。
  3. 根据权利要求1或2所述的方法，其特征在于，所述第一模拟电路包括m个链路组，一个链路组中包括n个可用链路，所述可用链路用于模拟所述第一待测芯片中的第一链路，所述测试配置信息包括组选择信息；
    所述根据所述测试配置信息，确定所述第一模拟电路中的当前待测链路，包括：
    从所述测试配置信息中读取所述组选择信息；
    从所述m个链路组中选择所述组选择信息指示的链路组，作为所述当前待测试链路组；所述当前待测试链路组中的可用链路为所述当前待测链路。
  4. 根据权利要求3所述的方法，其特征在于，所述第一模拟电路中包含的元器件以及元器件之间的连接方式根据所述第一待测芯片中包含的元器件以及元器件之间的连接关系设置；
    所述第一链路为所述第一待测芯片包含的链路中，使用频率大于预设频率阈值和/或结构复杂度小于预设复杂度阈值的链路。
  5. 根据权利要求1或2所述方法，其特征在于，所述基于所述延时引入电路为所述当前待测链路引入时序延时，包括：
    调整所述延时引入电路接入所述当前待测链路的链路长度；其中，不同链路长度对应引入的时序延时不同。
  6. 根据权利要求5所述的方法，其特征在于，所述测试配置信息中还包括初始链路长度信息；所述调整所述延时引入电路接入所述当前待测链路的链路长度，包括：
    将所述链路长度设置为所述初始链路长度信息所指示的初始链路长度；
    若所述初始链路长度下所述当前待测链路未出现时序违例，则根据所述初始链路长度生成目标链路长度，并将所述链路长度设置为所述目标链路长度，直至所述当前待测链路出现时序违例。
  7. 根据权利要求6所述的方法，其特征在于，所述根据所述初始链路长度生成目标链路长度，包括：
    确定当前待测的所述目标时序裕量的类型；
    若所述目标时序裕量的类型为建立时序裕量，则对所述初始链路长度进行递增处理，得到至少一个所述目标链路长度；
    或者，若所述目标时序裕量的类型为保持时序裕量，则对所述初始链路长度进行递减处理，得到至少一个所述目标链路长度。
  8. 根据权利要求5所述的方法，其特征在于，所述延时引入电路中的元器件包括缓冲器和/或反向器；
    所述延时引入电路中元器件的总数量与所述第一模拟电路所需支持的最大工作频率正相关。
  9. 根据权利要求1或2所述的方法，其特征在于，所述对所述当前待测链路进行调整，包括：
    调节所述当前待测链路的工作频率，以改变所述当前待测链路中的时序延时。
  10. 根据权利要求9所述的方法，其特征在于，所述测试配置信息中还包括工作频率信息；所述调节所述当前待测链路的工作频率，包括：
    将所述延时引入模式的链路长度设置为预设的固定值，并将所述当前待测链路的工作频率设置为所述工作频率信息所指示的频率；
    在接收到新的测试配置信息时，将所述当前待测链路的工作频率设置为所述新的测试配置信息中包括的工作频率信息所指示的频率。
  11. 根据权利要求1或2所述的方法，其特征在于，所述测试电路系统中还包括与所述第一模拟电路连接的时序违例捕获电路，所述方法还包括：
    获取所述时序违例捕获电路的输出值；所述时序违例捕获电路的输出值用于表征所述第一模拟电路是否出现时序违例；
    在所述输出值为特定值的情况下，确定所述当前待测链路出现时序违例。
  12. 根据权利要求11所述的方法，其特征在于，所述时序违例捕获电路包括第一捕获电路及第二捕获电路；所述第一捕获电路包括并行的第一寄存器及第一锁存器，用于对所述第一寄存器的输出及所述第一锁存器的输出进行异或运算的异或门；所述第二捕获电路包括并行的第二寄存器及第二锁存器，用于对所述第二寄存器的输出及所述第二锁存器的输出进行同或运算的同或门；所述获取所述时序违例捕获电路的输出值，包括：
    若当前待测的所述目标时序裕量的类型为建立时序裕量，则获取所述第一捕获电路的输出值；
    若当前待测的所述目标时序裕量的类型为保持时序裕量，则获取所述第二捕获电路的输出值。
  13. 根据权利要求3所述的方法，其特征在于，所述第一模拟电路中还包括以标准器件链路作为可用链路的链路组，一条标准器件链路对应一种标准元器件，所述标准元器件为所述第一待测芯片中第二链路中包含的元器件，在所述当前待测链路为所述标准器件链路的情况下，所述确定所述当前待测链路的目标时序裕量，包括：
    根据所述标准器件链路出现时序违例时所使用的工作频率，确定所述标准元器件对应的单个延时值；
    根据各个所述标准元器件对应的单个延时值，确定所述第二链路的目标时序裕量。
  14. 根据权利要求13所述的方法，其特征在于，所述根据所述标准器件链路出现时序违例时当前所使用的工作频率，确定所述标准元器件对应的单个延时值，包括：
    确定所述标准器件链路当前所使用的工作频率对应的周期时长；
    计算所述周期时长与所述标准器件链路中标准元器件数量的比值，得到所述标准元器件对应的单个延时值。
  15. 根据权利要求13所述的方法，其特征在于，所述根据各个所述标准元器件对应的单个延时值，确定所述第二链路的目标时序裕量，包括：
    基于预设的时序仿真算法，测试所述第二链路的时序裕量，得到待修正时序裕量；
    根据各个所述标准元器件对应的单个延时值，确定所述第二链路中包括的元器件对应的单个延时值；
    根据所述第二链路中包括的元器件对应的单个延时值，对所述待修正时序裕量进行修正，得到所述第二链路的目标时序裕量；其中，所述第二链路的目标时序裕量小于所述待修正时序裕量。
  16. 根据权利要求13所述的方法，其特征在于，所述方法还包括：
    对于所述第一待测芯片中的各个第一待测链路，根据预设的时序仿真算法，确定所述第一待测链路对应的基础时序裕量；所述第一待测链路包括所述第一链路和/或所述第二链路；
    计算所述基础时序裕量与所述第一待测链路对应的目标时序裕量之间的裕量差值；
    对于第二待测芯片中的第二待测链路，根据所述预设的时序仿真算法确定所述第二待测链路的基础时序裕量；
    根据各个所述裕量差值，确定所述第二待测链路对应的修正裕量差值，并根据所述修正裕量差值对所述第二待测链路的基础时序裕量进行修正，得到所述第二待测链路的目标时序裕量。
  17. 根据权利要求16所述的方法，其特征在于，所述根据各个所述裕量差值，确定所述第二待测链路对应的修正裕量差值，包括：
    计算所述裕量差值的均值，得到标准裕量差值；将所述标准裕量差值确定为所述第二待测链路对应的修正裕量差值。
  18. 根据权利要求1所述的方法，其特征在于，所述方法还包括：
    上报检测结果；其中，所述检测结果中包括所述当前待测链路出现时序违例时，所述延时引入电路的当前链路长度。
  19. 根据权利要求2所述的方法，其特征在于，所述在所述当前待测链路出现时序违例时，确定所述当前待测链路的目标时序裕量，包括：
    对于所述当前待测链路中的任一元器件，根据所述元器件对应的时钟路径及数据路径，计算所述元器件对应的时序裕量；
    根据所述元器件对应的时序裕量，确定所述当前待测链路的第一时序裕量；
    根据预设的时序仿真算法，确定所述当前待测链路对应的第二时序裕量；
    根据所述的第二时序裕量、所述第一时序裕量以及所述第二时序裕量与所述第一时序裕量之间的差值，确定所述当前待测链路的目标时序裕量；
    其中，所述当前待测链路的目标时序裕量小于所述第二时序裕量且不小于所述第一时序裕量。
  20. 根据权利要求2所述的方法，其特征在于，所述在所述当前待测链路出现时序违例时，确定所述当前待测链路的目标时序裕量，包括：
    对于所述当前待测链路中的任一元器件，根据所述元器件对应的时钟路径及数据路径，计算所述元器件对应的时序裕量；
    根据所述元器件对应的时序裕量，确定所述当前待测链路的第一时序裕量；
    将所述第一时序裕量确定为所述当前待测链路的目标时序裕量。
  21. 根据权利要求2所述的方法，其特征在于，所述第一待测芯片中的电路设置在所述电路板上。
  22. 一种时序裕量确定装置，其特征在于，应用于测试电路系统，所述测试电路系统中包括第一模拟电路及延时引入电路，所述第一模拟电路用于模拟第一待测芯片中的电路，所述延时引入电路用于为所述第一模拟电路引入时序延时，所述装置包括存储器和处理器；
    所述存储器，用于存储程序代码；
    所述处理器，调用所述程序代码，当所述程序代码被执行时，用于执行以下操作：
    接收测试配置信息；
    根据所述测试配置信息，确定所述第一模拟电路中的当前待测链路；
    对所述当前待测链路进行调整，和/或，基于所述延时引入电路为所述当前待测链路引入时序延时，以使所述第一模拟电路出现时序违例；
    在所述当前待测链路出现时序违例时，确定所述当前待测链路的目标时序裕量。
  23. 一种测试电路系统，其特征在于，所述测试电路系统中包括控制电路、第一模拟电路及延时引入电路；
    所述第一模拟电路用于模拟第一待测芯片中的电路，所述延时引入电路用于为所述第一模拟电路引入时序延时；
    所述控制电路用于实现上述权利要求1至权利要求21中任一所述方法中的步骤。
  24. 一种计算机可读存储介质，其特征在于，应用于测试电路系统，所述测试电路系统中包括第一模拟电路及延时引入电路，所述第一模拟电路用于模拟第一待测芯片中的电路，所述延时引入电路用于为所述第一模拟电路引入时序延时，所述计算机可读存储介质上存储计算机程序，所述计算机程序被处理器执行时实现以下操作：
    接收测试配置信息；
    根据所述测试配置信息，确定所述第一模拟电路中的当前待测链路；
    对所述当前待测链路进行调整，和/或，基于所述延时引入电路为所述当前待测链路引入时序延 时，以使所述第一模拟电路出现时序违例；
    在所述当前待测链路出现时序违例时，确定所述当前待测链路的目标时序裕量。
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