WO2022103107A1 - Circuit d'alimentation électrique - Google Patents

Circuit d'alimentation électrique Download PDF

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Publication number
WO2022103107A1
WO2022103107A1 PCT/KR2021/016181 KR2021016181W WO2022103107A1 WO 2022103107 A1 WO2022103107 A1 WO 2022103107A1 KR 2021016181 W KR2021016181 W KR 2021016181W WO 2022103107 A1 WO2022103107 A1 WO 2022103107A1
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WO
WIPO (PCT)
Prior art keywords
transistor
node
voltage
power supply
supply circuit
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Application number
PCT/KR2021/016181
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English (en)
Korean (ko)
Inventor
최재순
최석문
설경식
백인국
김영기
Original Assignee
주식회사 실리콘마이터스
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Application filed by 주식회사 실리콘마이터스 filed Critical 주식회사 실리콘마이터스
Priority to CN202180021342.XA priority Critical patent/CN116261825B/zh
Publication of WO2022103107A1 publication Critical patent/WO2022103107A1/fr

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
    • H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators

Definitions

  • the present invention relates to a power supply circuit. Specifically, the present invention relates to a power supply circuit in which a switched capacitor converter and a three-level buck converter are integrated.
  • the power supply circuit may be used as a voltage regulator performing functions such as charging a battery in an electronic device or converting a voltage received from an external charging device.
  • a device commonly referred to as a power management integrated circuit is included in a mobile electronic device, such as a mobile phone or a tablet, to manage power inside the electronic device.
  • the power management integrated circuit requires a voltage regulator that performs functions such as battery charging, conversion of voltage received from an external charging device, and power selection. It can be used as a voltage regulator.
  • TA chargers
  • various charging methods such as a method in which the voltage provided by an external charger is fixed, such as 5V or 9V, and a method that can be varied in the range of 3V to 11V or 3V to 20V, etc. method is being used.
  • a USB-PD PPS USB Power Delivery Programmable Power Supply
  • a USB-PD PPS USB Power Delivery Programmable Power Supply
  • a USB-PD PPS USB Power Delivery Programmable Power Supply
  • the electronic device can be charged with high speed and high efficiency by requesting an optimal voltage from an external charger according to its state.
  • the power supply circuit used in the voltage regulator needs to operate optimally in consideration of the situation in which the voltage provided from the external charger may be fixed to a predetermined value or may be varied in various voltage ranges. .
  • One object of the present invention is, according to an embodiment, a power supply capable of charging a battery at high speed and high efficiency or providing power to a system inside an electronic device in a situation in which a voltage provided from an external charger may be fixed or variable to provide a circuit.
  • One object of the present invention is, according to an embodiment, a switched capacitor converter mode (charge pump mode) and a 3-level buck converter mode ( By providing a power supply circuit that can selectively operate in the buck mode), it is possible to effectively operate for various external charging methods, as well as reduce the number of elements and reduce the size and loss of an inductor.
  • One aspect of the present invention is a power supply circuit that receives power from an external charger and provides power to a battery and/or an electronic device system, and is selected from a charge pump mode or a buck mode according to on/off switching operations of a plurality of transistors.
  • a converter in which at least some of the plurality of transistors are switched in both the charge pump mode and the buck mode; and a controller controlling the switching operation of the plurality of transistors.
  • the converter comprises: a first transistor connected between a first node and a second node (Q CH ); a second transistor connected between the second node and the third node (Q DH1 ); a third transistor (Q CL1 ) connected between the third node and the fourth node; a fourth transistor connected between the fourth node and the fifth node (Q DL ); a fifth transistor (Q DH2 ) connected between the second node and the sixth node; a sixth transistor Q CL2 connected between the sixth node and the fourth node; a flying capacitor connected between the second node and the fourth node; and an inductor connected between the sixth node and the seventh node, wherein the first node is connected to the input voltage, the third node is connected to the battery voltage, and the fifth node is connected to the reference voltage (PGND),
  • the seventh node may be connected to a system voltage.
  • the converter may further include a seventh transistor (Q BAT ) connected between the third node and the seventh node.
  • the converter is configured to have a substantially 2:1 relationship between the input voltage and the battery voltage by the switching operation of the first to fourth transistors in the charge pump mode.
  • the system voltage is lower than the input voltage by the switching operation of the first transistor, the fourth transistor, the fifth transistor, and the sixth transistor and the inductor, and the input voltage VIN ) and the system voltage VSYS can be varied.
  • the first transistor and the third transistor are simultaneously turned on/off with a duty of substantially 0.5, and the second transistor and the fourth transistor are substantially may be turned on/off opposite to that of the first transistor.
  • the current supplied from the third node to the battery may not pass through the transistor.
  • the first transistor in the buck mode, is turned on/off with a first duty, and the fifth transistor has a 180 degree phase with substantially the same duty as the first transistor. It is turned on/off in a shifted form, the sixth transistor may be turned on/off opposite to the fifth transistor, and the fourth transistor may be turned on/off opposite to the first transistor.
  • the controller may control the ratio of the input voltage to the system voltage by adjusting the first duty.
  • a current ripple frequency of the inductor may be twice a switching frequency of the first transistor.
  • the fifth transistor and the sixth transistor may not perform an on/off operation.
  • the fifth transistor and the sixth transistor may also perform a switching operation.
  • the fifth transistor may be turned on/off in the same manner as the second transistor, and the sixth transistor may be turned on/off in the same manner as the third transistor.
  • the input voltage to which the first node is connected may be an intermediate bus voltage generated from a voltage provided from the external charger.
  • an input transistor Q RB may be further included between the first node and the node connected to the external charger.
  • the second transistor, the third transistor, and the seventh transistor may be transistors capable of bidirectional control.
  • the present invention it is possible to charge a battery or provide power to an electronic device system at high speed and high efficiency in a situation in which the voltage provided from the charger may be fixed or variable.
  • a switched capacitor converter mode charge pump mode
  • a 3-level buck converter mode buck mode
  • FIG. 1 illustrates a power supply circuit according to an embodiment of the present invention.
  • 5 to 9 exemplarily describe a case in which the power supply circuit according to the embodiment of FIG. 1 operates in a 3-level buck converter mode with a duty greater than 0.5.
  • 10 to 12 exemplarily describe a case in which the power supply circuit according to the embodiment of FIG. 1 operates at a duty of 0.5 in a 3-level buck converter mode.
  • 13 to 17 exemplarily describe a case in which the power supply circuit according to the embodiment of FIG. 1 operates with a duty of less than 0.5 in a 3-level buck converter mode.
  • FIG. 1 illustrates a power supply circuit according to an embodiment of the present invention.
  • the power supply circuit may include a controller 110 , an integrated circuit 100 including a plurality of transistors, and peripheral elements (inductors, capacitors, etc.) of the integrated circuit 100 .
  • elements transistors, buffers, inductors, capacitors, etc.
  • the power supply circuit may be understood to include a converter including a plurality of transistors and passive elements and the controller 110 .
  • the battery 10 is generally viewed as a configuration outside the power supply circuit, but the battery 10 can also be considered to be included in the power supply circuit depending on circumstances.
  • the power supply circuit may receive power from an external charger TA and provide power to a battery and/or an electronic device system.
  • the power supply circuit may be used inside a mobile electronic device such as a mobile phone or tablet to perform functions such as charging a battery, converting a voltage received from an external charging device, and selecting power.
  • the power supply circuit may be used as a voltage regulator inside a power management integrated circuit (PMIC) within the mobile electronic device or as a voltage regulator that cooperates with a power management integrated circuit (PMIC) outside the power management integrated circuit (PMIC). there is.
  • PMIC power management integrated circuit
  • the power supply circuit may be connected to an external charger TA through an input port (not shown).
  • the input port may be connected to a charger TA external to the electronic device to receive power from the external charger TA.
  • the voltage provided from the external charger TA may be a fixed voltage, such as 5V or 9V, or a voltage variable in the range of 3V to 11V or 3V to 20V.
  • the input port may be a USB A-type or a USB C-type, but is not limited thereto.
  • the bus capacitor C VBUS may be connected between the bus voltage terminal VBUS and the reference voltage PGND.
  • the bus capacitor C VBUS may be selectively used as needed to stabilize the bus voltage V BUS .
  • the input transistor Q RB may be connected between the bus voltage V BUS and the intermediate bus voltage V MID .
  • the input transistor Q RB may be selectively used as needed to perform a function of transferring the bus voltage V BUS to the intermediate bus voltage V MID .
  • the input terminal transistor Q RB may perform a current regulation function for preventing an excessive current from flowing in an initial operation or a transient state of the power supply circuit.
  • the input transistor Q RB may perform a regulating function for the current and/or the battery current of the VBUS terminal.
  • a function of adjusting the battery voltage V BAT may be performed by using the input terminal transistor Q RB .
  • the input stage transistor (Q RB ) controls the intermediate bus voltage (V MID ) in such a way that, when transferring the bus voltage (V BUS ) to the intermediate bus voltage (V MID ), the voltage is lowered to transfer the battery voltage (V BAT ) can perform a function to control
  • the input transistor Q RB may perform a function of blocking the transfer of the bus voltage V BUS to the intermediate bus voltage V MID in an abnormal state.
  • the input terminal transistor Q RB may be conductive to transfer the bus voltage V BUS as the intermediate bus voltage V MID without any special processing.
  • the intermediate bus voltage V MID may be substantially equal to the bus voltage V BUS .
  • the intermediate bus capacitor C MID may be connected between the intermediate bus voltage V MID and the reference voltage PGND.
  • the intermediate bus capacitor C MID may optionally be used as needed to stabilize the intermediate bus voltage V MID .
  • the battery 10 may store power provided from the external charger TA and provide the stored power to the system voltage terminal VSYS_PWR of the electronic device as needed.
  • the battery 10 may be a lithium-ion battery mainly used in mobile electronic devices, but is not limited thereto.
  • a signal provided from the voltage sensing terminals S+ and S- of the battery 10 may be provided to the controller 110 through the battery voltage detecting terminals BATSNSP and BATSNSN of the integrated circuit 100 .
  • the battery voltage detection terminals BATSNSP and BATSNSN may be selectively used as necessary to precisely detect the voltage of the battery 10 without being affected by the operating condition of the power supply circuit.
  • the intermediate bus voltage V MID can be viewed as an input voltage of the converter
  • the intermediate bus voltage V MID can be expressed as the input voltage V IN .
  • the intermediate bus voltage V MID is generated from the voltage provided from the external charger TA.
  • the input voltage V IN is the bus voltage provided from the external charger TA. (V BUS ) may be substantially the same.
  • the converter includes a first transistor (Q CH ) connected between the first node (N1) and the second node (N2), a second transistor (Q DH1 ) connected between the second node (N2) and the third node (N3) , a third transistor (Q CL1 ) connected between the third node (N3) and the fourth node (N4), a fourth transistor (Q DL ) connected between the fourth node (N4) and the fifth node (N5), the first A fifth transistor Q DH2 connected between the second node N2 and the sixth node N6, a sixth transistor Q CL2 connected between the sixth node N6 and the fourth node N4, the second node It may include a flying capacitor C FLY connected between N2 and the fourth node N4 and an inductor L connected between the sixth node N6 and the seventh node N7 . According to an embodiment, the converter may further include a seventh transistor Q BAT connected between the seventh node N7 and the third node N3 .
  • the first node N1 may be connected to the input voltage V IN
  • the third node N3 may be connected to the battery voltage V BAT through the first output voltage terminal VOUT1
  • the fifth node N5 may be connected to the reference voltage PGND
  • the seventh node N7 may be connected to the system voltage V SYS through the system voltage terminal VSYS.
  • a system voltage capacitor C VSYS may be connected between the system voltage V SYS and the reference voltage PGND to stabilize the system voltage V SYS .
  • a battery voltage capacitor C VBAT may be connected between the battery voltage V BAT and the reference voltage PGND to stabilize the battery voltage V BAT .
  • the controller 110 may perform overall control of the power supply circuit.
  • the controller 110 may communicate with a power management integrated circuit (not shown) that manages power of the electronic device system and may transmit/receive information for controlling the power supply circuit.
  • the controller 110 controls on/off switching operations of a plurality of transistors in the power supply circuit to supply at least one of voltage, current, and power to the battery voltage terminal VBAT and the system voltage terminal VSYS. can be adjusted.
  • the controller 110 may acquire information on at least one of a voltage and a current of the battery 10 .
  • the controller 110 may acquire battery voltage information through the battery voltage detection terminals BATSNSP and BATSNSN.
  • the controller 110 may acquire battery current information detected using a current detection resistor or a current transformer (CT) through a battery current detection terminal.
  • CT current transformer
  • the controller 110 directly requests information about the voltage to be provided from the external charger (TA) to the external charger (TA) or the external charger through the power management integrated circuit (TA) can be requested.
  • the power supply circuit may include a plurality of buffers BF as illustrated in FIG. 1 .
  • Each buffer BF may be selectively used as needed to receive a signal provided by the controller 110 for driving a transistor and apply an appropriate driving signal to a corresponding transistor.
  • the buffer BF may be used to amplify a current applied to a gate terminal of the transistor, amplify a voltage, or drive a transistor in a floating state.
  • the buffer BF for driving the transistor may not be used.
  • the power supply circuit configured as described above may selectively operate among two operation modes as needed.
  • One of the two operating modes is a switched capacitor converter (SCC) mode, and the other is a three-level buck converter (3-level Buck converter) mode.
  • SCC switched capacitor converter
  • 3-level Buck converter three-level buck converter
  • the switched capacitor converter mode may be referred to as a 'charge pump mode'.
  • the 3-level buck converter mode will be briefly referred to as 'buck mode' if there is no confusion.
  • the converter in the power supply circuit may selectively operate in the charge pump mode or the buck mode according to on/off switching operations of the plurality of transistors.
  • at least some of the plurality of transistors in the converter may be configured to perform a switching operation in both the charge pump mode and the buck mode.
  • both the operation of the charge pump circuit and the operation of the 3-level buck circuit corresponding to different operation methods are possible using one circuit, and the charge pump circuit and the three It can be understood as a new circuit in which the -level buck circuit is merged into one.
  • the ratio of the input voltage V IN to the battery voltage V BAT is substantially 2:1 by the switching operation of the first transistor Q CH to the fourth transistor Q DL .
  • the fifth transistor Q DH2 and the sixth transistor Q CL2 may selectively operate as needed.
  • the charge pump mode is mainly performed when the ratio of the first node (N1) voltage (ie, the input voltage (V IN )) to the third node (N3) voltage (ie, the battery voltage (V BAT )) has a relationship of 2:1. It can be used to deliver power with high efficiency.
  • the converter in the buck mode, the switching operation of the first transistor (Q CH ), the fourth transistor (Q DL ), the fifth transistor (Q DH2 ) and the sixth transistor (Q CL2 ) and the system voltage by the inductor (L) While (V SYS ) is lower than the input voltage (V IN ), the ratio of the input voltage (V IN ) to the system voltage (V SYS ) may be varied.
  • the second transistor Q DH1 and the third transistor Q CL1 may maintain an off state.
  • the ratio (voltage conversion ratio) of the seventh node N7 voltage (ie, the system voltage V SYS ) to the first node N1 voltage (ie, the input voltage V IN ) is the first transistor (Q CH ), the fourth transistor (Q DL ), the fifth transistor (Q DH2 ), and the sixth transistor (Q CL2 ) may be controlled through control. Therefore, the buck mode can effectively operate in a situation where the ratio of the voltage of the first node (N1) to the voltage of the seventh node (N7) is not 2:1, that is, in a situation where various voltage conversion ratios are required.
  • the seventh transistor Q BAT may selectively transmit current in either direction between the system voltage node VSYS_PWR and the battery voltage node VBAT in either direction as needed. That is, the seventh transistor Q BAT transfers a current from the system voltage node VSYS_PWR to the battery voltage node VBAT to charge the battery 10 or from the battery voltage node VBAT to the system voltage node VSYS_PWR. The energy stored in the battery 10 may be supplied to the system by passing a current. This operation of the seventh transistor Q BAT may be selectively performed as needed in any mode of the charge pump mode and the buck mode.
  • the controller 110, transistors, and buffers are included in the integrated circuit 100 and passive elements (capacitors, inductors, etc.) are exemplified as being disposed outside the integrated circuit 100, but the integrated circuit 100
  • passive elements capacitors, inductors, etc.
  • the elements disposed therein may be variously changed.
  • some of the transistors and buffers may be disposed outside the integrated circuit 100 and/or some of the passive components may be disposed within the integrated circuit 100 .
  • FIG. 2 to 4 exemplarily describe a case in which the power supply circuit according to the embodiment of FIG. 1 operates in a switched capacitor converter mode (charge pump mode).
  • FIG. 2 illustrates on/off operations and main waveforms V CP , V OUT1 , and V CN of the first transistor Q CH to the fourth transistor Q DL in the charge pump mode.
  • V CP is the voltage of the second node N2
  • V OUT1 is the voltage of the third node N3
  • V CN is the voltage of the fourth node N4 .
  • the first transistor Q CH and the third transistor Q CL1 are turned on/off at the same time with a duty of substantially 0.5, and the second transistor Q DH1 and the fourth transistor (Q CL1 ) Q DL ) may be turned on/off substantially opposite to that of the first transistor Q CH .
  • the duty may be defined as a ratio of the on period to the switching period (the sum of the on period and the off period).
  • the fifth transistor Q DH2 and the sixth transistor Q CL2 may maintain an off state.
  • the fifth transistor Q DH2 and the sixth transistor Q CL2 may also perform an on/off switching operation in the charge pump mode. For this part, refer to FIGS. 18 and 19 , to be described later.
  • FIG. 3 exemplarily describes operations in the ON period of the first transistor Q CH and the third transistor Q CL1 .
  • the CP node connected to the second node N2 is connected to the input voltage V IN through the first transistor Q CH
  • the CN node connected to the fourth node N4 is connected to the third transistor Q CL1 through the third transistor Q CL1 . It is connected to the battery voltage (V BAT ). Therefore, the input voltage (V IN ) is equal to the sum of the voltage (V CFLY ) across the flying capacitor and the battery voltage (V BAT ).
  • FIG. 4 exemplarily describes operations in the ON period of the second transistor Q DH1 and the fourth transistor Q DL .
  • the CP node connected to the second node N2 is connected to the battery voltage V BAT through the second transistor Q DH1
  • the CN node connected to the fourth node N4 is connected to the fourth transistor Q DL through the It is connected to the reference voltage PGND. Accordingly, the flying capacitor voltage V CFLY and the battery voltage V BAT are equal to each other.
  • the flying capacitor voltage (V CFLY ) and the battery voltage (V BAT ) are equal to each other, and the input voltage (V IN ) is equal to the sum of the flying capacitor voltage (V CFLY ) and the battery voltage (V BAT ), as a result,
  • the flying capacitor voltage V CFLY and the battery voltage V BAT are each half of the input voltage V IN . Accordingly, the ratio of the input voltage V IN which is the voltage of the first node N1 to the battery voltage V BAT which is the voltage of the third node N3 has a relationship of 2:1.
  • the current supplied from the third node N3 to the battery 10 is directly supplied without passing through the transistor. That is, in the charge pump mode, the current for charging the battery 10 may be supplied from the third node N3 to the battery 10 without passing through the transistor, thereby reducing loss and operating with high efficiency.
  • the power supply circuit operates in the charge pump mode, the loss due to the inductor (L) is eliminated or reduced, so it can operate with higher current and higher efficiency than the buck mode using the inductor. Therefore, the charge pump mode is mainly used in situations where a large current or large power is transmitted, such as fast charging or super fast charging. According to this embodiment, when the battery is charged in the charge pump mode, the efficiency can be increased.
  • power supplied from the third node N3 to the battery voltage terminal VBAT may be supplied to the system voltage node VSYS_PWR through the seventh transistor Q BAT as needed.
  • 5 to 9 illustrate a case in which the power supply circuit according to the embodiment of FIG. 1 operates with a duty (D) greater than 0.5 in a 3-level buck converter mode (buck mode). explain negatively.
  • D duty
  • buck mode 3-level buck converter mode
  • V OUT2 is the voltage of the sixth node (N6)
  • I L is the current of the inductor (L).
  • the first transistor Q CH may be repeatedly turned on/off with an adjustable duty.
  • the duty may be defined as a ratio of the on period to the switching period (the sum of the on period and the off period).
  • the duty in the buck mode is defined as the duty of the first transistor Q CH .
  • the duty of the first transistor (Q CH ) is to be understood as the ratio of the sum of the lengths of the 1, 2 and 4 sections (the ON section of the first transistor (Q CH )) to the sum of the lengths of the sections 1 to 4 can
  • the fifth transistor Q DH2 has the same duty as the first transistor Q CH , but may be turned on/off in a substantially 180 degree phase shifted form.
  • the sixth transistor Q CL2 may be turned on/off substantially opposite to that of the fifth transistor Q DH2 .
  • the fourth transistor Q DL may be turned on/off substantially opposite to that of the first transistor Q CH .
  • the second transistor Q DH1 and the third transistor Q CL1 may maintain an off state, but the present embodiment is not limited thereto.
  • FIG. 6 exemplarily describes the operation in the period 1 of FIG. 5 , that is, the ON period of the first transistor Q CH and the sixth transistor Q CL2 .
  • the CP node connected to the second node N2 is connected to the input voltage V IN through the first transistor Q CH
  • the CN node connected to the fourth node N4 is connected to the sixth transistor Q CL2 through the It is connected to the second output voltage (V OUT2 ) and one end of the inductor (L).
  • the other end of the inductor L may be connected to the system voltage V SYS and may be selectively connected to the battery voltage V BAT through the seventh transistor Q BAT if necessary.
  • a voltage (ie, Vin/2) obtained by subtracting the flying capacitor voltage V CFLY from the input voltage V IN is applied to the second output voltage V OUT2 to which one end of the inductor L is connected, and the inductor ( A system voltage (V SYS ) is applied to the other end of L), and when the duty is greater than 0.5, the system voltage (V SYS ) is greater than half of the input voltage (V IN ) as will be described later, so the inductor current (I L ) decreases.
  • FIG. 7 exemplarily describes the operation in the period 2 of FIG. 5 , that is, the ON period of the first transistor Q CH and the fifth transistor Q DH2 .
  • the CP node connected to the second node N2 is connected to the input voltage V IN through the first transistor Q CH and the second output voltage V OUT2 and the inductor L through the fifth transistor Q DH2 .
  • ) is connected to one end of
  • the CN node connected to the fourth node N4 is in a floating state.
  • the other end of the inductor L may be connected to the system voltage V SYS and may be selectively connected to the battery voltage V BAT through the seventh transistor Q BAT if necessary.
  • the input voltage V IN is applied to the second output voltage V OUT2 to which one end of the inductor L is connected, and the system voltage V SYS is applied to the other end of the inductor L, the input voltage ( Since V IN ) is higher than the system voltage V SYS , the inductor current I L increases.
  • FIG. 8 exemplarily describes the operation in the period 3 of FIG. 5 , that is, the ON period of the fifth transistor Q DH2 and the fourth transistor Q DL .
  • the CP node connected to the second node N2 is connected to the second output voltage V OUT2 and one end of the inductor L through the fifth transistor Q DH2 .
  • the CN node connected to the fourth node N4 is connected to the reference voltage PGND through the fourth transistor Q DL .
  • the other end of the inductor L may be connected to the system voltage V SYS and may be selectively connected to the battery voltage V BAT through the seventh transistor Q BAT if necessary.
  • the flying capacitor voltage V CFLY is applied to the second output voltage V OUT2 to which one end of the inductor L is connected, and the system voltage V SYS is applied to the other end of the inductor L.
  • FIG. 9 exemplarily describes the operation in the period 4 of FIG. 5 , that is, the ON period of the first transistor Q CH and the fifth transistor Q DH2 . Since the operation in section 4 is similar to the operation in section 2, a detailed description will be omitted.
  • the average of the voltages applied to one end and the other end of the inductor L is equal to each other, so the system voltage (V SYS ) is higher than half of the input voltage (V IN ) and the input voltage (V IN ) will have a lower value than
  • the ratio of the system voltage (V SYS ) to the input voltage (V IN ) may be controlled by adjusting the ratio of the sum of sections 1 and 3 or the ratio of the sum of sections 2 and 4 with respect to the switching period.
  • the ratio of the system voltage V SYS to the input voltage V IN may be adjusted through the duty of the first transistor Q CH (for convenience of description, the duty of the first transistor Q CH is representative For example, it can also be understood as being adjusted according to the duty of other transistors).
  • the first transistor Q CH may be repeatedly turned on/off with a duty of substantially 0.5.
  • the fifth transistor Q DH2 has the same duty as the first transistor Q CH , but may be turned on/off in a substantially 180 degree phase shifted form.
  • the sixth transistor Q CL2 may be turned on/off substantially opposite to that of the fifth transistor Q DH2 .
  • the fourth transistor Q DL may be turned on/off substantially opposite to that of the first transistor Q CH .
  • FIG. 11 exemplarily describes the operation in the period 1 of FIG. 10 , that is, the ON period of the first transistor Q CH and the sixth transistor Q CL2 .
  • the CP node connected to the second node N2 is connected to the input voltage V IN through the first transistor Q CH
  • the CN node connected to the fourth node N4 is connected to the sixth transistor Q CL2 through the It is connected to the second output voltage (V OUT2 ) and one end of the inductor (L).
  • the other end of the inductor L may be connected to the system voltage V SYS and may be selectively connected to the battery voltage V BAT through the seventh transistor Q BAT if necessary.
  • a voltage (ie, Vin/2) obtained by subtracting the flying capacitor voltage V CFLY from the input voltage V IN is applied to the second output voltage V OUT2 to which one end of the inductor L is connected, and the inductor (
  • the system voltage V SYS is applied to the other end of L), and when the duty is 0.5, the system voltage V SYS becomes half of the input voltage V IN , as will be described later, so the inductor current I L is substantially (Actually, there may be a slight increase or decrease in the inductor current (I L ) due to the duty not being exactly 0.5 or the effect of parasitics, etc.).
  • FIG. 12 exemplarily describes the operation in the period 2 of FIG. 10 , that is, the on period of the fifth transistor Q DH2 and the fourth transistor Q DL .
  • the CP node connected to the second node N2 is connected to the second output voltage V OUT2 and one end of the inductor L through the fifth transistor Q DH2 .
  • the CN node connected to the fourth node N4 is connected to the reference voltage PGND through the fourth transistor Q DL .
  • the other end of the inductor L may be connected to the system voltage V SYS and may be selectively connected to the battery voltage V BAT through the seventh transistor Q BAT if necessary.
  • the flying capacitor voltage V CFLY is applied to the second output voltage V OUT2 to which one end of the inductor L is connected, and the system voltage V SYS is applied to the other end of the inductor L.
  • FIG. 13 to 17 exemplarily illustrate a case in which the power supply circuit according to the embodiment of FIG. 1 operates with a duty of less than 0.5 in a 3-level buck converter mode (buck mode).
  • buck mode 3-level buck converter mode
  • FIG. 13 is a buck mode (D ⁇ 0.5) of the first transistor (Q CH ), the fourth transistor (Q DL ), the fifth transistor (Q DH2 ), and the sixth transistor (Q CL2 ) on/off operation and main waveforms (V CP , V OUT2 , V CN , I L ) is illustrated.
  • the first transistor Q CH may be repeatedly turned on/off with an adjustable duty.
  • the duty may be defined as a ratio of the on period to the switching period (the sum of the on period and the off period).
  • the duty in the buck mode is defined as the duty of the first transistor Q CH .
  • the duty of the first transistor Q CH may be understood as a ratio of the length of the section 1 (the ON section of the first transistor Q CH ) to the sum of the lengths of sections 1 to 4.
  • the fifth transistor Q DH2 has substantially the same duty as the first transistor Q CH , but may be turned on/off in a 180 degree phase shifted form.
  • the sixth transistor Q CL2 may be turned on/off substantially opposite to that of the fifth transistor Q DH2 .
  • the fourth transistor Q DL may be turned on/off substantially opposite to that of the first transistor Q CH .
  • the second transistor Q DH1 and the third transistor Q CL1 may maintain an off state, but the present embodiment is not limited thereto.
  • FIG. 14 exemplarily describes the operation in the period 1 of FIG. 13 , that is, the ON period of the first transistor Q CH and the sixth transistor Q CL2 .
  • the CP node connected to the second node N2 is connected to the input voltage V IN through the first transistor Q CH
  • the CN node connected to the fourth node N4 is connected to the sixth transistor Q CL2 through the It is connected to the second output voltage (V OUT2 ) and one end of the inductor (L).
  • the other end of the inductor L may be connected to the system voltage V SYS and may be selectively connected to the battery voltage V BAT through the seventh transistor Q BAT if necessary.
  • a voltage (ie, Vin/2) obtained by subtracting the flying capacitor voltage V CFLY from the input voltage V IN is applied to the second output voltage V OUT2 to which one end of the inductor L is connected, and the inductor ( A system voltage (V SYS ) is applied to the other end of L), and when the duty is less than 0.5, the system voltage (V SYS ) becomes less than half of the input voltage (V IN ) as will be described later, so the inductor current (I L ) is increased
  • FIG. 15 exemplarily describes the operation in the period 2 of FIG. 13 , that is, the on period of the sixth transistor Q CL2 and the fourth transistor Q DL .
  • the CP node connected to the second node N2 is in a floating state.
  • the CN node connected to the fourth node N4 is connected to the second output voltage V OUT2 and one end of the inductor L through the sixth transistor Q CL2 and the reference voltage (Q DL ) through the fourth transistor (Q DL ) PGND).
  • the other end of the inductor L may be connected to the system voltage V SYS and may be selectively connected to the battery voltage V BAT through the seventh transistor Q BAT if necessary.
  • the reference voltage PGND is applied to the second output voltage V OUT2 to which one end of the inductor L is connected, and the system voltage V SYS is applied to the other end of the inductor L, so the inductor current I L ) decreases.
  • FIG. 16 exemplarily illustrates the operation in section 3 of FIG. 13 , that is, in the ON section of the fifth transistor Q DH2 and the fourth transistor Q DL .
  • the CP node connected to the second node N2 is connected to the second output voltage V OUT2 and one end of the inductor L through the fifth transistor Q DH2 .
  • the CN node connected to the fourth node N4 is connected to the reference voltage PGND through the fourth transistor Q DL .
  • the other end of the inductor L may be connected to the system voltage V SYS and may be selectively connected to the battery voltage V BAT through the seventh transistor Q BAT if necessary.
  • the flying capacitor voltage V CFLY is applied to the second output voltage V OUT2 to which one end of the inductor L is connected, and the system voltage V SYS is applied to the other end of the inductor L.
  • FIG. 17 exemplarily describes the operation in section 4 of FIG. 13 , that is, in the ON section of the sixth transistor Q CL2 and the fourth transistor Q DL . Since the operation in section 4 is similar to the operation in section 2, a detailed description will be omitted.
  • the first transistor Q CH is turned on/off with a first duty
  • the fifth transistor Q DH2 is substantially is turned on/off in a 180 -degree phase- shifted form while having the same duty as It is the same in that it is turned on/off opposite to the transistor Q CH .
  • the ratio of the system voltage (V SYS ) to the input voltage (V IN ) (ie, voltage conversion ratio) may be varied in a wide range while theoretically having a value between 0 and 1 according to the duty.
  • the duty may be varied in a predetermined range, for example, in the range of 0.1 to 0.9.
  • the controller may control the ratio (voltage conversion ratio) of the input voltage V IN to the system voltage V SYS by adjusting the duty (eg, the first duty) of the transistors.
  • the current ripple frequency of the inductor L may be doubled the switching frequency of the transistor (eg, the first transistor Q CH ).
  • the switching period of the first transistor Q CH is the sum of sections 1 to 4, but the current ripple period of the inductor L is the sum of sections 1 and 2 (or 3 and 4 sum of the sections) becomes half of the switching period of the first transistor (Q CH ).
  • the inductance of the inductor L can be reduced, the size and loss of the inductor L can be reduced.
  • the current supplied through the inductor L may be supplied to the system voltage node VSYS_PWR without passing through an additional transistor. Therefore, buck mode can be effectively used to power the system.
  • the battery needs to be charged in the buck mode, at least a portion of the current supplied to the system voltage node VSYS_PWR through the inductor L may be supplied to the battery 10 through the seventh transistor Q BAT .
  • the power supply circuit according to the present embodiment can selectively operate in the charge pump mode and the buck mode using one circuit having a simple structure, so that the voltage provided from the external charger can be fixed or variable.
  • the current for charging the battery 10 in the charge pump mode can be supplied to the battery 10 from the third node N3 without going through the transistor, thereby charging the battery 10 with high efficiency.
  • the current supplied to the system can be supplied from the inductor (L) to the system voltage node (VSYS_PWR) without going through the transistor, thereby increasing the efficiency when supplying power to the system.
  • the on/off operation of the first transistor Q CH to the fourth transistor Q DL and the main waveforms V CP , V OUT1 , V CN ) may be similar to that illustrated in FIG. 2 . That is, the first transistor Q CH and the third transistor Q CL1 are turned on/off simultaneously with a duty of substantially 0.5, and the second transistor Q DH1 and the fourth transistor Q DL are It may be turned on/off substantially opposite to that of the first transistor Q CH .
  • the embodiment of FIGS. 18 and 19 is different from the method illustrated in FIGS. 3 and 4 in that the fifth transistor Q DH2 and the sixth transistor Q CL2 also perform the switching operation. Specifically, the fifth transistor Q DH2 may be turned on/off in the same manner as the second transistor Q DH1 , and the sixth transistor Q CL2 may be turned on/off in the same manner as the third transistor Q CL1 . .
  • the CP node connected to the second node N2 is connected to the input voltage V IN through the first transistor Q CH
  • the CN node connected to the fourth node N4 is connected to the third transistor Q CL1 through the third transistor Q CL1 . It is connected to the battery voltage (V BAT ). Accordingly, the input voltage V IN is equal to the sum of the flying capacitor voltage V CFLY and the battery voltage V BAT .
  • the CN node is connected to the second output voltage V OUT2 and one end of the inductor L through the sixth transistor Q CL2 .
  • a path for supplying current to the system voltage node (VSYS_PWR) through the inductor (L) is additionally created in the CN node.
  • the current supplied to the system voltage node VSYS_PWR through the inductor L may be transferred to the battery 10 through the seventh transistor Q BAT depending on circumstances to be used to charge the battery 10 .
  • the CP node connected to the second node N2 is connected to the battery voltage V BAT through the second transistor Q DH1
  • the CN node connected to the fourth node N4 is connected to the fourth transistor Q DL through the It is connected to the reference voltage PGND. Accordingly, the flying capacitor voltage V CFLY and the battery voltage V BAT are equal to each other.
  • the CP node is connected to the second output voltage V OUT2 and one end of the inductor L through the fifth transistor Q DH2 .
  • a path for supplying current to the system voltage node (VSYS_PWR) through the inductor (L) is additionally created in the CP node.
  • the current supplied to the system voltage node VSYS_PWR through the inductor L may be transferred to the battery 10 through the seventh transistor Q BAT depending on circumstances to be used to charge the battery 10 .
  • the voltage conversion ratio which is the ratio of the battery voltage V BAT to the input voltage V IN
  • the voltage conversion ratio may be the same as in the embodiments of FIGS. 2 to 4 .
  • the battery through the third node N3 A path supplied to the voltage node VBAT and a path supplied to the system voltage node VSYS_PWR through the sixth node N6 and the inductor L may be formed together.
  • the system voltage node VSYS_PWR and the battery voltage node VBAT may transfer current in either direction through the seventh transistor Q BAT as needed. That is, a current is transferred from the system voltage node VSYS_PWR to the battery voltage node VBAT through the seventh transistor Q BAT to charge the battery 10 or from the battery voltage node VBAT to the system voltage node VSYS_PWR.
  • the energy stored in the battery 10 may be supplied to the system by transferring the current to the system.
  • the effective impedance on the current path is lowered to reduce losses and increase efficiency. There is this.
  • This advantage according to the embodiment of Figs. 18 and 19 may be more effective, especially in situations where large currents or powers are processed, such as fast charging or super fast charging.
  • the controller 110 may be implemented in software and stored in a computer-readable storage medium (memory, etc.), and may perform its function by an arithmetic device such as a CPU.
  • the controller 110 may be implemented as hardware such as an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA), or the like.
  • ASIC Application Specific Integrated Circuit
  • FPGA Field Programmable Gate Array
  • a transistor capable of unidirectional control may be used for the first transistor Q CH , the fourth transistor Q DL , the fifth transistor Q DH2 , and the sixth transistor Q CL2 , and the second transistor Q DH1 ), the third transistor Q CL1 , the seventh transistor Q BAT , and the input terminal transistor Q RB , a transistor capable of bidirectional control may be used.
  • a transistor capable of bidirectional control a back-gate control MOSFET or a back-to-back MOSFET may be used.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Dc-Dc Converters (AREA)

Abstract

La présente invention concerne un circuit d'alimentation électrique incorporant un convertisseur à condensateurs commutés et un convertisseur abaisseur de tension à 3 niveaux. Selon un aspect de la présente invention, l'invention concerne un circuit d'alimentation électrique qui reçoit de l'électricité provenant d'un chargeur externe et fournit de l'électricité à une batterie et/ou à un système de dispositif électronique, le circuit d'alimentation électrique comprenant : un convertisseur qui est sélectivement actionné dans un mode de pompe de charge ou dans un mode abaisseur en fonction d'une opération de commutation marche/arrêt d'une pluralité de transistors, au moins certains de la pluralité de transistors étant commutés à la fois dans le mode de pompe de charge et dans le mode abaisseur ; et un dispositif de commande permettant de commander une opération de commutation de chacun de la pluralité de transistors.
PCT/KR2021/016181 2020-11-12 2021-11-09 Circuit d'alimentation électrique WO2022103107A1 (fr)

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KR20240018743A (ko) 2022-08-02 2024-02-14 삼성디스플레이 주식회사 전원 전압 제공 회로, 그것을 포함하는 표시 장치, 및 표시 장치를 포함하는 표시 시스템
WO2024106700A1 (fr) * 2022-11-16 2024-05-23 삼성전자주식회사 Circuit d'entrée de puissance, dispositif électronique comprenant un circuit d'entrée de puissance, et son procédé de fonctionnement
WO2024137623A1 (fr) * 2022-12-19 2024-06-27 Murata Manufacturing Co., Ltd. Systèmes, circuits et procédés permettant de réduire des transitoires pendant des changements de mode dans un convertisseur multiniveau

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