WO2022095945A1 - 一种通信芯片及数据处理方法 - Google Patents

一种通信芯片及数据处理方法 Download PDF

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WO2022095945A1
WO2022095945A1 PCT/CN2021/128824 CN2021128824W WO2022095945A1 WO 2022095945 A1 WO2022095945 A1 WO 2022095945A1 CN 2021128824 W CN2021128824 W CN 2021128824W WO 2022095945 A1 WO2022095945 A1 WO 2022095945A1
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data
module
channels
alignment
output
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PCT/CN2021/128824
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English (en)
French (fr)
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丁瑞香
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中兴通讯股份有限公司
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Priority to EP21888637.2A priority Critical patent/EP4236187A4/en
Priority to JP2023526632A priority patent/JP7561276B2/ja
Publication of WO2022095945A1 publication Critical patent/WO2022095945A1/zh
Priority to US18/312,864 priority patent/US20230273767A1/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0685—Clock or time synchronisation in a node; Intranode synchronisation
    • H04J3/0697—Synchronisation in a packet node
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/10—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using random access memory
    • G06F5/12—Means for monitoring the fill level; Means for resolving contention, i.e. conflicts between simultaneous enqueue and dequeue operations
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0041—Arrangements at the transmitter end
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1673—Details of memory controller using buffers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/065—Partitioned buffers, e.g. allowing multiple independent queues, bidirectional FIFO's
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0041—Arrangements at the transmitter end
    • H04L1/0042—Encoding specially adapted to other signal generation operation, e.g. in order to reduce transmit distortions, jitter, or to improve signal shape
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0067—Rate matching
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
    • H04L7/005—Correction by an elastic buffer
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0057—Block codes

Definitions

  • the present application relates to the field of communication technologies, and in particular, to a communication chip and a data processing method.
  • the Physical Coding Sublayer (PCS) of the communication chip usually selects Reed Solomon Forward Error Correction (RS-Forward Error Correction, RS-FEC) coding when data is transmitted at a high rate Way.
  • RS-FEC requires the sending side to insert an alignment mark (AM) into the data. After the data is transmitted through an optical fiber or cable, the receiving side searches for the AM in the data stream for data synchronization and alignment.
  • AM alignment mark
  • An embodiment of the present application provides a communication chip, including: a plurality of synchronization modules, a set of cache modules, and a plurality of alignment modules;
  • the synchronization module is configured to receive the data of the corresponding channel, synchronize the received data, and store the synchronized data in the cache module;
  • the cache module includes a plurality of first-in-first-out queues FIFO; the FIFO is set to cache the synchronized data output by the corresponding synchronization module;
  • the alignment module is configured to align the synchronized data of the corresponding channels in the cache module, and combine the aligned data for output.
  • An embodiment of the present application provides a data processing method, and the method is applied to the communication chip provided by the present application, and the method includes:
  • the synchronized data output by the corresponding synchronization module is cached through each FIFO in the cache module;
  • the synchronized data of all channels in the cache module is aligned by at least one alignment module in the plurality of alignment modules, and the aligned data is combined and output.
  • FIG. 1 is a schematic structural diagram of a communication chip provided by an embodiment of the present application.
  • FIG. 2 is a flowchart of a data processing method provided by an embodiment of the present application.
  • FIG. 3 is a schematic diagram 1 of a data flow under a configuration rate provided by an embodiment of the present application.
  • FIG. 4 is a schematic diagram 2 of a data flow under a configuration rate provided by an embodiment of the present application.
  • FIG. 5 is a schematic diagram 3 of a data flow under a configuration rate provided by an embodiment of the present application.
  • FIG. 6 is a schematic diagram 4 of a data flow under a configuration rate provided by an embodiment of the present application.
  • FIG. 7 is a schematic diagram 5 of a data flow under a configuration rate provided by an embodiment of the present application.
  • the Physical Coding Sublayer (PCS) of the communication chip usually selects the Reed Solomon Forward Error Correction (RS-FEC) coding method when data is transmitted at a high rate.
  • RS-FEC requires the sending side to insert a synchronization alignment mark (AM) into the data. After the data is transmitted through an optical fiber or cable, the receiving side looks for AM in the data stream for data synchronization and alignment.
  • AM synchronization alignment mark
  • the data synchronization and alignment method received by the communication chip cannot be compatible with various protocols and rates, which leads to inflexible use of the communication chip, and greatly increases the development and use costs of the communication chip.
  • the embodiments of the present application provide a communication chip and a data processing method, which can meet the data alignment requirements of various rate configuration combinations, can reduce the occupation and waste of logic resources, and realize structure optimization.
  • the technical solutions provided by the embodiments of the present application may include multiple synchronization modules, a set of cache modules, and multiple alignment modules, wherein a set of cache modules includes multiple FIFOs, and the FIFOs cache the synchronized data output by the corresponding synchronization modules, At least one alignment module aligns the synchronized data of all channels buffered by at least one FIFO in the buffer module, and combines them for output.
  • the data alignment requirements of various rate configuration combinations can be achieved through multiple FIFOs, which can reduce the occupation and waste of logic resources. achieve structural optimization.
  • FIG. 1 is a schematic structural diagram of a communication chip provided by the present application, wherein the communication chip provided by the present application includes a physical coding sublayer (Physical Coding Sublayer, PCS) and supports an RS-FEC configuration environment.
  • PCS Physical Coding Sublayer
  • the communication chip provided by the present application includes a plurality of synchronization modules (lsync), a set of cache modules (al_fifo_8), and a plurality of alignment modules (including align_2, align_4, and align_8).
  • the synchronization module is set to receive the data of the corresponding channel, synchronize the received data, and store the synchronized data into the cache module;
  • the cache module includes multiple first-in-first-out queues FIFO;
  • FIFO is set as a cache Corresponds to the synchronized data output by the synchronization module; in the alignment module, it is set to align the synchronized data of the corresponding channel in the cache module, and combine the aligned data for output.
  • the combined output refers to the combined output.
  • the number of synchronization modules is 8, the number of alignment modules is 7; the number of FIFOs is 8, as shown in FIG. 1 , the cache module (al_fifo_8) may include 8 FIFOs, They are FIFO_0, FIFO_1, FIFO_2, FIFO_3, FIFO_4, FIFO_5, FIFO_6, FIFO_7.
  • the synchronized data output by the multiple synchronization modules are sequentially buffered in the FIFO, and the synchronization modules and the FIFO can be in one-to-one correspondence.
  • the number of synchronization modules and the number of FIFOs can be the same, the number of synchronization modules and FIFOs can also be other numbers, which can be set according to actual needs, and the number of alignment modules can also be other numbers.
  • the multiple alignment modules output data at different rates. Specifically, the size of each output data supported by multiple alignment modules is not the same, or the supported data of the data of multiple alignment modules is not exactly the same.
  • the plurality of alignment modules includes 4 first alignment modules (align_2), 2 second alignment modules (align_4) and 1 third alignment module (align_8);
  • the first alignment module is configured to align the synchronized data of the two channels buffered corresponding to the two FIFOs, and combine the synchronized data of the two channels to output;
  • the second alignment module is set to align the synchronized data of the 4 channels corresponding to the buffer memory of the 4 FIFOs, and combine and output the synchronized data of the 4 channels;
  • the third alignment module is configured to align the synchronized data of the eight channels corresponding to the eight FIFOs, and combine and output the synchronized data of the eight channels.
  • the synchronization module may be a single-channel synchronization module, and may be a synchronization state machine that completes a channel (lane) in a forward error correction (FEC) mode, and supports all Ethernet rates.
  • the first alignment module (align_2) can be an alignment module for two channel data, and can be an alignment state machine with a completion rate of 50GE (gigabit ethernet) and two FEC lanes, which can complete the data type (symbol) on two FEC lanes. ) of the merge function.
  • the second alignment module (align_4) can be an alignment module of four channel data, and can be an alignment state machine with a completion rate of 100GE and four FEC lanes, which can complete the function of merging symbols on four FEC lanes.
  • the third alignment module (align_8) can be an alignment module of 8 channels of data, and can be an alignment state machine with a completion rate of 200GE and 8 FEC lanes, which can complete the merging function of symbols on 8 FEC lanes.
  • the data source may be the output data encoded by the RS-FEC from the PCS transmitting side, and has been divided into N channels (may be 1-8) according to different FCE lanes, that is, the data on the N channels data.
  • N channels may be 1-8) according to different FCE lanes, that is, the data on the N channels data.
  • the data transmission rate is 25GE, it contains 1 FEC lane data; if the data transmission rate is 50GE, it contains 2 FEC lane data; if the data transmission size is 100GE, it contains 4 FEC lanes If the data transmission rate is 200GE, it contains the data of 8 FEC lanes.
  • the synchronization module performs data synchronization: the data on the input N channels, that is, the input data of the N channels passes through the corresponding synchronization module to complete the single FEC lane synchronization process of the N channels of data respectively.
  • the specific synchronization process is to use the alignment mark (AM) generated at a fixed period in the PCS protocol during transmission and carried in the PCS processing data stream, query the alignment mark in the data, remove the data before the alignment mark, and use the alignment mark as the transmission mark.
  • AM alignment mark
  • data boundaries please refer to IEEE 802.3-2018 clause82, 91, 108, 119, 134 and other chapters.
  • the synchronization module After the synchronization module synchronizes the data of the corresponding channel, it outputs the synchronization signal (carrying the synchronization status information) and the channel identifier (FEC lane number) to the alignment module corresponding to the configuration rate, and sends the synchronized data to the cache module.
  • the cache module includes 8 FIFOs, and the data after N-way (can be 8-way) FEC lane synchronization is directly written into the corresponding FIFO.
  • the read and flush operations in each FIFO can be controlled by the downstream alignment module (the first alignment module, the second alignment module or the third alignment module).
  • the alignment module performs data alignment: According to the configuration rate of the port, the first alignment module (align_2), the second alignment module (align_4) or the third alignment module (align_8) realizes multiple FEC lane data by controlling the upstream FIFO read and empty operations alignment. Specifically: when the N FIFOs in the buffer module have buffered the synchronized data of all channels corresponding to the configured rate, a notification message is sent to the alignment module, and the alignment module receives the notification message and the corresponding synchronization status information, At the same time, the synchronized data in the N FIFOs are read to achieve data alignment, and are sorted according to the channel identifiers and then output.
  • the first alignment module (align_2) completes data alignment at a rate of 50GE
  • the second alignment module (align_4) completes data alignment at a rate of 100GE
  • the third alignment module (align_8) completes data alignment at a rate of 200GE.
  • the configuration rate of the port can be understood as the supported rate configured by the port.
  • the communication chip provided by the present application is not limited to the structural form shown in FIG. 1 , wherein, the number of FIFOs in the synchronization module, the cache module, and the number of alignment modules can be adjusted according to actual needs.
  • the communication chip provided by this application can synchronize and align the data from the Physical Media Attachment (PMA) layer, can support multiple rate configuration methods, and can support multiple rates from the external network and CPRI. Configuration and combination to present a variety of port supported rate configuration methods, for example, it can support 4 25GE rates, or 4 50GE rates, or support 4 Common Public Radio Interface (CPRI) ports, or support 2 100GE rates port, or support one 100GE rate and two 25GE/50GE/CPRI ports, or support one 200GE rate port.
  • PMA Physical Media Attachment
  • CPRI Common Public Radio Interface
  • the communication chip provided by the present application may include multiple synchronization modules, a set of cache modules, and multiple alignment modules, wherein a set of cache modules includes multiple FIFOs, and the FIFOs cache the synchronized data output by the corresponding synchronization modules.
  • the alignment module aligns the synchronized data of all channels buffered by at least one FIFO in the buffer module, and combines them for output.
  • the data alignment requirements of various rate configuration combinations can be achieved through multiple FIFOs, which can reduce the occupation and waste of logical resources and realize the structure optimization.
  • the cache module includes 8 FIFOs, and the data alignment requirements of various rate configuration combinations are realized through 8 FIFOs. If the communication chip provided by this application is not applicable, 24 FIFOs are required to realize the same function, thus It can reduce the occupation and waste of logic resources, optimize chips, and reduce costs.
  • FIG. 2 is a data processing method provided by an embodiment of the present application. The method is applied to a communication chip provided by the present application.
  • the chip may be a chip including PCS.
  • the technical solution provided by the embodiment of the present application include:
  • S210 Receive data on the corresponding channel through the synchronization module, synchronize the received data, and store the synchronized data in the cache module.
  • S220 Cache the synchronized data output by the corresponding synchronization module through each FIFO in the buffer module.
  • S230 Align the synchronized data of all channels in the cache module through at least one alignment module in the plurality of alignment modules, and combine and output the aligned data.
  • the rates of the multiple alignment module data are not identical.
  • the number of the synchronization modules is 8
  • the number of the alignment modules is 7
  • the number of the FIFOs is 8.
  • the method further includes: sending, by the synchronization module, the synchronization state information and the channel identifier to the alignment module corresponding to the configured rate; after the buffering module caches all channels corresponding to the configured rate for synchronization In the case of the data, send a notification message to the alignment module corresponding to the configuration rate;
  • the aligning the synchronized data of all channels in the cache module and merging and outputting the aligned data includes: reading the cache in the case of receiving the synchronization state information and the notification message
  • the synchronized data of the corresponding channel in the FIFO buffer in the module is arranged and output based on the channel identifier.
  • the data on each channel can be sent by the PCS sending side at the same time. Since the physical media that may pass through the data transmission process of each channel are different, there will be delays in the data reception on some channels.
  • the data of each channel is aligned. After the synchronization module synchronizes the data of the corresponding channel, it is cached in the corresponding FIFO in the buffer module. When the synchronized data of all channels are buffered in the corresponding FIFO, the alignment module reads at the same time. The data in the non-empty FIFO realizes data alignment.
  • the alignment module when the alignment module receives the synchronization status information, it can determine that the received data has been synchronized, and when the alignment module receives the notification message, it can be determined that the cache module has cached all channels corresponding to the configuration speed. Synchronized data, so that when the alignment module receives the synchronization status information and notification message, it simultaneously reads the non-empty FIFO in the buffer module to align all channel data, and align the read data according to the channel ID. Arranged so that the output data is output in the order in which the data is sent.
  • the method further includes: when the time skew between the synchronized data of each two channels exceeds a set range, clearing the FIFO in the cache module by using the alignment module, and returning the data by using the alignment module.
  • Each synchronization module receives the data on the corresponding channel, synchronizes the received data, and stores the synchronized data in the cache module.
  • the time skew may refer to the interval between times, and the setting range may be set according to the actual situation.
  • the time skew between the synchronized data of each two channels exceeds the set range, the FIFO overflows and the data alignment fails. It is necessary to reset the non-empty FIFO and restart the synchronization alignment process.
  • the synchronization module performs data synchronization: the data on the input N channels, that is, the input data of the N channels passes through the corresponding synchronization module to complete the single FEC lane synchronization process of the N channels of data respectively.
  • the specific synchronization process is to use the alignment mark (AM) generated at a fixed period in the PCS protocol during transmission and carried in the PCS processing data stream, query the alignment mark in the data, remove the data before the alignment mark, and use the alignment mark as the transmission mark.
  • AM alignment mark
  • data boundaries please refer to IEEE 802.3-2018clause82, 91, 108, 119, 134 and other chapters.
  • the synchronization module After the synchronization module synchronizes the data of the corresponding channel, it outputs the synchronization signal (carrying the synchronization status information) and the channel identifier (FEC lane number) to the alignment module corresponding to the configuration rate, and sends the synchronized data to the cache module.
  • the cache module includes 8 FIFOs, and the data after N-way (can be 8-way) FEC lane synchronization is directly written into the corresponding FIFO.
  • the read and flush operations in each FIFO can be controlled by the downstream alignment module (the first alignment module, the second alignment module or the third alignment module).
  • the alignment module performs data alignment: According to the configuration rate of the port, the first alignment module (align_2), the second alignment module (align_4) or the third alignment module (align_8) realizes multiple FEC lane data by controlling the upstream FIFO read and empty operations alignment. Specifically: when the N FIFOs in the buffer module have buffered the synchronized data of all channels corresponding to the configured rate, a notification message is sent to the alignment module, and the alignment module receives the notification message and the corresponding synchronization status information, At the same time, the synchronized data in the N FIFOs are read to achieve data alignment, and are sorted according to the channel identifiers and then output.
  • the first alignment module (align_2) completes data alignment at a rate of 50GE
  • the second alignment module (align_4) completes data alignment at a rate of 100GE
  • the third alignment module (align_8) completes data alignment at a rate of 200GE.
  • the configuration rate of the port can be understood as the supported rate configured by the port.
  • Step 1 After reset, the third alignment module (align_8) clears the 8 FIFOs in the cache module (al_fifo_8);
  • Step 2 When a channel (when the number is less than 8) is synchronized, the corresponding FIFO can only be written but not read;
  • Step 3 When all 8 channels are synchronized and all 8 FIFOs are not empty, the cache module (al_fifo_8) starts to read the synchronized data in the 8 FIFOs at the same time, and the first read is AM;
  • Step 4 When any FIFO overflows, it means that the time skew between channels exceeds the allowable range and the alignment fails. At this time, the third alignment module (align_8) resets all 8 FIFOs and restarts the synchronous alignment process.
  • Step 5 After the alignment is successful, the 8 channels of input data are rearranged in order according to the FEC lane number given by the synchronization module and then output.
  • the alignment process of the first alignment module (align_2) and the second alignment module (align_4) is similar to that of the third alignment module (align_8), the difference is that the first alignment module (align_2) inputs data from the corresponding 2 FIFOs and controls this For the read and clear operations of the two FIFOs, the second alignment module (align_4) inputs data from the corresponding four FIFOs and controls the read and clear operations of the four FIFOs.
  • each of the synchronization modules receives data on the corresponding channel, synchronizes the received data, and synchronizes the synchronized Data is sent to the downstream receiver side.
  • the data rate of one channel is 25GE
  • the configuration rate includes four 25GE; four synchronization modules are used to receive data on four channels correspondingly, and the received data is synchronized, and the synchronized
  • the data is sent to the downstream receiving side, that is, the synchronized data does not pass through the cache module and the alignment module.
  • the reason is: since the data rate of one channel is the same, it is not necessary to combine and output the synchronized data of at least two channels, so the data output by the synchronization module can be directly sent to the downstream receiving side.
  • the configuration rate is the sum of the data rates of the two channels
  • the multiple alignment modules respectively receive data on the eight channels
  • the synchronized data of all channels in the cache module is aligned, and the aligned data is combined and output, including:
  • each first alignment module is set to cache
  • the two FIFOs in the module align the synchronized data corresponding to the two buffered channels, and combine and output the synchronized data of the two channels.
  • the data rate of one channel is 25GE
  • the configuration rate includes: 4 50GE, correspondingly receive data on 8 channels through 8 synchronization modules (lsync), and synchronize the received data, Cache the synchronized data into the corresponding 8 FIFOs; align the synchronized data buffered in the 8 FIFOs through the 4 first alignment modules (align_2), and combine the aligned data for output, where each A first alignment module (align_2) aligns the synchronized data buffered in the two FIFOs, and combines them for output.
  • the multiple alignment modules when the configuration rate is the sum of the data rates of 4 channels, and the multiple alignment modules receive data on the 8 channels, through at least one alignment module in the multiple alignment modules, Align the synchronized data of all channels in the cache module, and combine and output the aligned data, including:
  • each second alignment module is set to The four FIFOs in the module are aligned corresponding to the synchronized data of the four channels in the buffer, and the synchronized data of the four channels are combined and output.
  • the data rate of one channel is 25GE
  • the configuration rate includes two 100GE
  • the data on the eight channels is correspondingly received through eight synchronization modules (lsync), and the received data is synchronized.
  • the synchronized data is buffered into the corresponding 8 FIFOs; the synchronized data of the 8 channels buffered in the 8 FIFOs are aligned through the 2 second alignment modules (align_4), and the aligned data is combined and output.
  • each second alignment module (align_4) aligns the synchronized data of the two channels buffered in the four FIFOs, and combines them for output.
  • the configured rate includes the sum of the data rates of the 4 lanes, and the data rates of the two lanes, and the multiple alignment modules receive data on the 8 lanes
  • the 4 FIFOs are aligned with the synchronized data of the 4 channels in the cache.
  • the other 4 FIFOs in the cache module are aligned with the synchronized data of the 4 channels in the cache, and the synchronized data is aligned. Combine output.
  • the data rate of one channel is 25GE
  • the configuration rate includes one 100GE and two 50GE
  • the data on the eight channels is correspondingly received through eight synchronization modules (lsync).
  • Synchronize cache the synchronized data into the corresponding 8 FIFOs; align the synchronized data of the 4 channels buffered in the 4 FIFOs through a second alignment module (align_4), and store the synchronized data in the 4 FIFOs.
  • the synchronized data of the 4 channels are combined and output, and at the same time, the synchronized data of the 4 channels buffered in the other 4 FIFOs are aligned through the 2 first alignment modules (align_2), and the 4 channels in the other 4 FIFOs are aligned.
  • the data after channel synchronization is combined and output.
  • the alignment is performed by at least one of the multiple alignment modules.
  • module aligns the synchronized data of all channels in the cache module, and merges and outputs the aligned data, including:
  • a third alignment module Through a third alignment module, the synchronized data of the eight channels corresponding to the eight FIFOs in the cache module are aligned, and the synchronized data of the eight channels are combined and output; wherein, the third alignment module is set In order to align the synchronized data of the eight channels buffered by the eight FIFOs in the buffer module, and combine and output the synchronized data of the eight channels.
  • the data rate of one channel is 25GE
  • the configuration rate includes one 200GE
  • the data on the eight channels is correspondingly received through eight synchronization modules (lsync), and the received data is synchronized.
  • the synchronized data is buffered into the corresponding 8 FIFOs; the synchronized data of the 8 channels buffered in the 8 FIFOs is aligned through a third alignment module (align_8), and the 8 channels buffered by the 8 FIFOs are aligned.
  • the synchronized data is merged and output.
  • the technical solution provided by this application can support the configuration and combination of multiple Ethernet rates.
  • the communication chip only includes one set of buffer modules, wherein the buffer module can include 8 FIFOs.
  • the communication chip can be both Flexible configuration and use can save circuit logic resources and reduce communication chip area and power consumption.

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Abstract

本申请实施例提供一种通信芯片以及数据处理方法，其中该通信芯片包括：多个同步模块、一套缓存模块和多个对齐模块；其中，每个所述同步模块，被设置为接收对应通道的数据，并对接收的所述数据进行同步，并将同步后的数据存入缓存模块；所述缓存模块包括多个先入先出队列FIFO；所述FIFO，被设置为缓存对应同步模块输出的同步后的数据；所述多个对齐模块中的至少一个对齐模块，被设置为将所述缓存模块中的所有通道同步后的数据进行对齐，并将对齐的数据合并输出。

Description

一种通信芯片及数据处理方法
交叉引用
本申请基于申请号为“202011233275.1”、申请日为2020年11月06日的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此以引入方式并入本申请。
技术领域
本申请涉及通信技术领域，尤其涉及一种通信芯片及数据处理方法。
背景技术
随着5G通信技术的发展，高速率、高质量的数据传输成为芯片设计必须要考虑的重要问题。当需求的网络速率超过物理器件的承载能力时，多通道并行传输以实现高速率接口的方式是大势所趋。
为保证数据传输的质量，通信芯片的物理编码子层(Physical Coding Sublayer，PCS)在数据高速率传输时通常选择里德所罗门前向纠错式(RS-Forward Error Correction，RS-FEC)的编码方式。RS-FEC需要发送侧在数据中插入对齐标识(AM)，数据经过光纤或电缆传输后，接收侧在数据流中寻找AM用于数据同步对齐。
发明内容
本申请实施例提供了一种通信芯片，包括：多个同步模块、一套缓存模块和多个对齐模块；
其中，所述同步模块，被设置为接收对应通道的数据，并对接收的所述数据进行同步，并将同步后的数据存入缓存模块；
所述缓存模块包括多个先入先出队列FIFO；所述FIFO，被设置为缓存对应同步模块输出的同步后的数据；
所述对齐模块中，被设置为将所述缓存模块中的对应通道同步后的数据进行对齐，并将对齐的数据合并输出。
本申请实施例提供了一种数据处理方法，所述方法应用于本申请提供的通信芯片，所述方法包括：
通过每个同步模块接收对应通道上的数据，并对接收的所述数据进行同步，并将同步后的数据存入缓存模块；
通过缓存模块中的每个先入先出队列FIFO缓存对应同步模块输出的同步后的数据；
通过多个对齐模块中的至少一个对齐模块，将所述缓存模块中的所有通道同步后的数据进行对齐，并将对齐的数据合并输出。
附图说明
图1是本申请实施例提供的一种通信芯片的结构示意图；
图2是本申请实施例提供的一种数据处理方法流程图；
图3是本申请实施例提供的一种配置速率下的数据流示意图一；
图4是本申请实施例提供的一种配置速率下的数据流示意图二；
图5是本申请实施例提供的一种配置速率下的数据流示意图三；
图6是本申请实施例提供的一种配置速率下的数据流示意图四；
图7是本申请实施例提供的一种配置速率下的数据流示意图五。
具体实施方式
为保证数据传输的质量，通信芯片的物理编码子层(Physical Coding Sublayer，PCS)在数据高速率传输时通常选择里德所罗门前向纠错式(RS-FEC)的编码方式。RS-FEC需要发送侧在数据中插入同步对齐标识(AM)，数据经过光纤或电缆传输后，接收侧在数据流中寻找AM用于数据同步对齐。
通信芯片接收的数据同步对齐方式不能兼容多种协议和速率，导致通信芯片的使用不灵活，通信芯片研发、使用成本大大增加。
本申请实施例提供了一种通信芯片以及数据处理方法，可以实现各种速率配置组合的数据对齐需求，可以减少逻辑资源的占用和浪费，实现结构优化。
本申请实施例提供的技术方案，可以包括多个同步模块、一套缓存模块以及多个对齐模块，其中，一套缓存模块包括多个FIFO，FIFO缓存对应同步模块输出的同步后的数据，通过至少一个对齐模块将缓存模块中至少一个FIFO缓存的所有通道同步的数据进行对齐，并合并输出，可以通过多个FIFO实现各种速率配置组合的数据对齐需求，可以减少逻辑资源的占用和浪费，实现结构优化。
图1是本申请提供的一种通信芯片的结构示意图，其中，本申请提供的通信芯片包含物理编码子层(Physical Coding Sublayer，PCS)，并且支持RS-FEC配置的环境。
如图1所示，本申请提供的通信芯片包括多个同步模块(lsync)、一套缓存模块(al_fifo_8)和多个对齐模块(包括align_2，align_4，align_8)。
其中，同步模块，被设置为接收对应通道的数据，并对接收的数据进行同步，并将同步后的数据存入缓存模块；缓存模块包括多个先入先出队列FIFO；FIFO，被设置为缓存对应同步模块输出的同步后的数据；对齐模块中，被设置为将缓存模块中的对应通道同步后的数据进行对齐，并将对齐的数据合并输出。其中，合并输出是指合并后输出。
在一个示例性的方式中，同步模块的数量为8个，所述对齐模块的数量为7个；FIFO的数量为8个，如图1所示，缓存模块(al_fifo_8)可以包括8个FIFO，分别是FIFO_0，FIFO_1，FIFO_2，FIFO_3，FIFO_4，FIFO_5，FIFO_6，FIFO_7。由多个同步模块输出的同步后的数据依次缓存至FIFO中，同步模块与FIFO可以一一对应。
需要说明的是同步模块的数量与FIFO的数量可以相同，同步模块和FIFO的数量还可以是其他数量，可以根据实际需要进行设置，对齐模块的数量也可以是其他数量。
在一个示例性的方式中，多个对齐模块输出数据的速率不完全相同。具体的，多个对齐模块支持的每次输出数据的大小不完全相同，或者多个对齐模块数据的支持数据不完全相同。
在一个示例性的方式中，多个对齐模块包括4个第一对齐模块(align_2)，2个第二对齐模块(align_4)和1个第三对齐模块(align_8)；
其中，所述第一对齐模块，被设置为将两个FIFO对应缓存的两条通道同步后的数据进行对齐，并将所述两条通道同步后的数据合并输出；
所述第二对齐模块，被设置将4个FIFO对应缓存的4条通道同步后的数据进行对齐，并将所述4条通道同步后的数据合并输出；
所述第三对齐模块，被设置为将8个FIFO对应缓存的8条通道同步后的数据进行对齐，并将所述8条通道同步后的数据进行合并输出。
具体的，如图1所示，同步模块(lsync)可以是单通道同步模块，可以是完成一个前向纠错FEC模式的通道(lane)的同步状态机，支持所有以太网速率。第一对齐模块(align_2)，可以是两条通道数据的对齐模块，可以是完成速率为50GE(gigabit ethernet)，且2个FEC lane的对齐状态机，可以完成2个FEC lane上数据类型(symbol)的合并功能。第二对齐模块(align_4)可以是四条通道数据的对齐模块，可以是完成速率为100GE，且4个FEC lane的对齐状态机，可以完成4个FEC lane上的symbol的合并功能。第三对齐模块(align_8)，可以是8条通道数据的对齐模块，可以是完成速率为200GE，且8个FEC lane的对齐状态机，可以完成8个FEC lane上symbol的合并功能。
在本申请实施例中，数据源可以是从PCS发送侧RS-FEC编码后的输出数据，且已经按照不同FCE lane分为N路(可以是1-8)的数据，即N条通道上的数据。其中，若数据传输的速率为25GE，则包含1个FEC lane的数据，若数据传输的速率为50GE，则包含2个FEC lane的数据；若数据传输的大小为100GE，则包含4个FEC lane的数据；若数据传输的速率为200GE，则包含8个FEC lane的数据。
本申请提供的通信芯片进行数据处理的过程如下：
如图1所示，同步模块进行数据同步：输入的N条通道上的数据，即输入的N路数据经过对应的同步模块，分别完成N路数据的单FEC lane同步过程。具体同步的过程是，使用发送时PCS协议中固定周期产生并且携带在PCS处理数据流中的对齐标识(AM)，查询数据中的对齐标识，将对齐标识之前的数据去掉，将对齐标识作为传输数据的边界。具体可以参考IEEE 802.3-2018 clause82、91、108、119、134等章节。同步模块将对应通道的数据实现同步后，输出同步信号(携带同步状态信息)和通道标识(FEC lane号)给配置速率对应的对 齐模块，并将同步后的数据给缓存模块。
缓存模块解偏斜:缓存模块包括8个FIFO，N路(可以是8路)FEC lane同步后的数据直接写入对应的FIFO中。每个FIFO中的读取和清空操作可以由下游的对齐模块(第一对齐模块，第二对齐模块或者第三对齐模块)来进行控制。
对齐模块进行数据对齐：根据端口的配置速率，第一对齐模块(align_2)，第二对齐模块(align_4)或第三对齐模块(align_8)通过控制上游的FIFO读和清空操作实现多条FEC lane数据的对齐。具体的是：在缓存模块中的N个FIFO已经缓存与配置速率对应的全部通道同步后的数据的情况下，向对齐模块发送通知消息，对齐模块接收到该通知消息以及对应的同步状态信息，同时读取N个FIFO中同步后的数据，以实现数据的对齐，并按照通道标识进行排序后输出。其中，第一对齐模块(align_2)完成速率为50GE的数据对齐，第二对齐模块(align_4)完成速率为100GE的数据对齐，第三对齐模块(align_8)完成速率为200GE的数据对齐。其中，端口的配置速率可以理解为端口配置的支持速率。
需要说明的是，本申请提供的通信芯片并不局限于图1所示的结构形式，其中，同步模块、缓存模块中FIFO的数量以及对齐模块的数量等可以根据实际需要进行调整。
本申请提供的通信芯片，可以完成对来自物理媒介适配层(Physical Media Attachment，PMA)的数据进行同步、对齐操作，可以支持多种速率的配置方式，可以支持以外网和CPRI多种速率的配置和组合，从而呈现多种端口支持速率的配置方式，例如可以是支持4个25GE速率，或者4个50GE速率，或者支持4个通用公共无线接口(CPRI)的端口，或者支持2个100GE速率的端口，或者支持1个速率100GE以及2个25GE/50GE/CPRI的端口，或者支持1个速率200GE的端口。
本申请提供的通信芯片，可以包括多个同步模块、一套缓存模块以及多个对齐模块，其中，一套缓存模块包括多个FIFO，FIFO缓存对应同步模块输出的同步后的数据，通过至少一个对齐模块将缓存模块中至少一个FIFO缓存的所有通道同步的数据进行对齐，并合并输出，可以通过多个FIFO实现各种速 率配置组合的数据对齐需求，可以减少逻辑资源的占用和浪费，实现结构优化。在一个实施方式中，缓存模块包括8个FIFO，通过8个FIFO实现各种速率配置组合的数据对齐需求，若不适用本申请提供的通信芯片，则需要24个FIFO才能实现相同的功能，从而可以减少逻辑资源的占用和浪费，优化芯片，降低成本。
图2是本申请实施例提供的一种数据处理方法，所述方法应用于本申请提供的通信芯片，该芯片可以是包含PCS的芯片，如图2所示，本申请实施例提供的技术方案包括：
S210：通过同步模块接收对应通道上的数据，并对接收的所述数据进行同步，并将同步后的数据存入缓存模块。
S220：通过缓存模块中的每个先入先出队列FIFO缓存对应同步模块输出的同步后的数据。
S230：通过多个对齐模块中的至少一个对齐模块，将所述缓存模块中的所有通道同步后的数据进行对齐，并将对齐的数据合并输出。
其中，具体数据通信方式可以参考通过通信芯片进行通信的方法。
在一个示例性的方式中，多个所述对齐模块数据的速率不完全相同。
在一个示例性的方式中，所述同步模块的数量为8个，所述对齐模块的数量为7个；所述FIFO的数量为8个。
在一个示例性的方式中，所述方法还包括：通过所述同步模块将同步状态信息以及通道标识发送给配置速率对应的对齐模块；在所述缓存模块缓存与配置速率对应的全部通道同步后的数据的情况下，向所述配置速率对应的对齐模块发送通知消息；
所述将所述缓存模块中的所有通道同步后的数据进行对齐，并将对齐的数据合并输出，包括：在接收到所述同步状态信息以及所述通知消息的情况下，读取所述缓存模块中FIFO缓存的对应通道的同步后的数据，并基于所述通道标识将读取的数据进行排列并输出。
其中，每条通道上的数据可以是由PCS发送侧同时发送的，由于每条通道数据传输过程中可能通过的物理介质并不相同，会存在某些通道上的数据接收 会存在延迟，为了实现各条通道的数据对齐，同步模块将对应通道的数据进行同步后，缓存至缓存模块中对应的FIFO中，在全部通道同步后的数据均缓存至对应的FIFO的情况下，对齐模块同时读取非空的FIFO中的数据，实现数据的对齐。
具体的，在对齐模块接收到同步状态信息的情况下，可以判断对接收的数据进行了同步，在对齐模块接收到通知消息的情况下，可以判断缓存模块已经缓存了与配置速度对应的全部通道同步后的数据，从而对齐模块在接收到同步状态信息和通知消息的情况下，同时读取缓存模块中非空的FIFO，实现将所有通道数据进行对齐，并按照通道标识将读取的数据进行排列，从而使输出的数据按照数据发送的顺序进行输出。
在一个示例性的方式中，还包括：在每两条通道同步后的数据之间的时间偏斜超过设定范围的情况下，通过对齐模块对缓存模块中的FIFO进行清空，并返回通过每个同步模块接收对应通道上的数据，并对接收的所述数据进行同步，并将同步后的数据存入缓存模块的操作。
其中，时间偏斜可以是指时间之间的间隔，设定范围可以根据实际情况进行设置。在每两条通道同步后的数据之间的时间偏斜超过设定范围的情况下，则FIFO发生上溢，数据对齐失败，需要将非空的FIFO进行复位，重新开始同步对齐过程。
其中，本申请实施例中，具体数据处理方法可以参考通过通信芯片进行处理的方法。
如图1所示，同步模块进行数据同步：输入的N条通道上的数据，即输入的N路数据经过对应的同步模块，分别完成N路数据的单FEC lane同步过程。具体同步的过程是，使用发送时PCS协议中固定周期产生并且携带在PCS处理数据流中的对齐标识(AM)，查询数据中的对齐标识，将对齐标识之前的数据去掉，将对齐标识作为传输数据的边界。具体可以参考IEEE 802.3-2018clause82、91、108、119、134等章节。同步模块将对应通道的数据实现同步后，输出同步信号(携带同步状态信息)和通道标识(FEC lane号)给配置速率对应的对齐模块，并将同步后的数据给缓存模块。
缓存模块解偏斜:缓存模块包括8个FIFO，N路(可以是8路)FEC lane 同步后的数据直接写入对应的FIFO中。每个FIFO中的读取和清空操作可以由下游的对齐模块(第一对齐模块，第二对齐模块或者第三对齐模块)来进行控制。
对齐模块进行数据对齐：根据端口的配置速率，第一对齐模块(align_2)，第二对齐模块(align_4)或第三对齐模块(align_8)通过控制上游的FIFO读和清空操作实现多条FEC lane数据的对齐。具体的是：在缓存模块中的N个FIFO已经缓存与配置速率对应的全部通道同步后的数据的情况下，向对齐模块发送通知消息，对齐模块接收到该通知消息以及对应的同步状态信息，同时读取N个FIFO中同步后的数据，以实现数据的对齐，并按照通道标识进行排序后输出。其中，第一对齐模块(align_2)完成速率为50GE的数据对齐，第二对齐模块(align_4)完成速率为100GE的数据对齐，第三对齐模块(align_8)完成速率为200GE的数据对齐。其中，端口的配置速率可以理解为端口配置的支持速率。
其中，如图1所示，以第三对齐模块(align_8)为例，数据对齐具体操作如下：
步骤一：复位后第三对齐模块(align_8)清空缓存模块(al_fifo_8)中的8个FIFO；
步骤二：当某条通道(个数小于8条时)同步后，对应的FIFO只写不读；
步骤三：当8条通道都同步且8个FIFO都非空时，缓存模块(al_fifo_8)开始同时读取8个FIFO中同步后的数据，首次读出的就是AM；
步骤四：当任意一个FIFO发生上溢时，说明通道之间的时间偏斜超过容许范围，对齐失败，此时第三对齐模块(align_8)复位全部8个FIFO，重新开始同步对齐过程。
步骤五：对齐成功后，根据同步模块给的FEC lane号对8路输入数据按顺序重新排列后输出。
其中，第一对齐模块(align_2)，第二对齐模块(align_4)的对齐过程和第三对齐模块(align_8)类似，区别是第一对齐模块(align_2)从对应的2个FIFO输入数据并控制这2个FIFO的读和清空操作，第二对齐模块(align_4)从对应的4个FIFO输入数据并控制这4个FIFO的读和清空操作。
在一个示例性的方式中，在配置速率为一个通道的数据速率的情况下，通过每个所述同步模块接收对应通道上的数据，并对接收的所述数据进行同步，并将同步后的数据发送至下游的接收侧。具体的，如图3所示，一个通道的数据速率为25GE，配置速率包括4个25GE；通过4个同步模块对应接收4个通道上的数据，并对接收的数据进行同步，将同步后的数据发送至下游的接收侧，即同步后的数据不经过缓存模块和对齐模块。原因在于：由于配置速率为一个通道的数据速率相同，不需要将至少两条通道同步后的数据进行合并输出，故同步模块输出的数据可以直接发送至下游接收侧。
在一个示例性的方式中，在配置速率为两条通道的数据速率之和，且多个对齐模块分别对应接收8条通道上的数据的情况下，
通过多个对齐模块中的至少一个对齐模块，将所述缓存模块中的所有通道同步后的数据进行对齐，并将对齐的数据合并输出，包括：
通过4个第一对齐模块，将缓存模块中8个FIFO对应缓存的8条通道同步后的数据进行对齐，并将对齐的数据合并输出；其中，每个第一对齐模块，被设置为将缓存模块中两个FIFO对应缓存的两道通道同步后的数据进行对齐，并将所述两条通道同步后的数据合并输出。
具体的，如图4所示，一个通道的数据速率为25GE，配置速率包括：4个50GE，通过8个同步模块(lsync)对应接收8个通道上的数据，并对接收的数据进行同步，将同步后的数据缓存至对应的8个FIFO中；通过4个第一对齐模块(align_2)将8个FIFO中缓存的同步后的数据进行对齐，并将对齐的数据进行合并输出，其中，每个第一对齐模块(align_2)将2个FIFO中缓存的同步后的数据进行对齐，并合并输出。
在一个示例性的实施方式中，在配置速率为4条通道的数据速率之和，且多个对齐模块接收8条通道上的数据的情况下，通过多个对齐模块中的至少一个对齐模块，将所述缓存模块中的所有通道同步后的数据进行对齐，并将对齐的数据合并输出，包括：
通过两个第二对齐模块，将缓存模块中8个FIFO对应缓存的8条通道同步后的数据进行对齐，并将对齐的数据合并输出；其中，每个第二对齐模块，被设置为将缓存模块中4个FIFO对应缓存的4条通道同步后的数据进行对齐， 并将所述4条通道同步后的数据合并输出。
具体的，如图5所示，一个通道的数据速率为25GE，配置速率包括2个100GE，通过8个同步模块(lsync)对应接收8个通道上的数据，并对接收的数据进行同步，将同步后的数据缓存至对应的8个FIFO中；通过2个第二对齐模块(align_4)将8个FIFO中缓存的8条通道的同步后的数据进行对齐，并将对齐的数据进行合并输出，其中，每个第二对齐模块(align_4)将4个FIFO中缓存的2条通道同步后的数据进行对齐，并合并输出。
在一个示例性的实施方式中，在配置速率包括4条通道的数据速率之和，以及两条通道的数据速率，且多个对齐模块接收8条通道上的数据的情况下，
通过多个对齐模块中的至少一个对齐模块，将所述缓存模块中的所有通道同步后的数据进行对齐，并将对齐的数据合并输出，包括：通过1个第二对齐模块，将缓存模块中4个FIFO对应缓存的4条通道同步后的数据进行对齐，通过两个第一对齐模块，将缓存模块中另外4个FIFO对应缓存的4条通道同步后的数据进行对齐，将同步后的数据合并输出。
具体的，如图6所示，一个通道的数据速率为25GE，配置速率包括1个100GE和2个50GE，通过8个同步模块(lsync)对应接收8个通道上的数据，并对接收的数据进行同步，将同步后的数据缓存至对应的8个FIFO中；通过1个第二对齐模块(align_4)将4个FIFO中缓存的4条通道同步后的数据进行对齐，并将4个FIFO中4条通道同步后的数据进行合并输出，并且同时通过2个第一对齐模块(align_2)将另外4个FIFO中缓存的4条通道同步后的数据进行对齐，并将另外4个FIFO中4条通道同步后的数据进行合并输出。
在一个示例性的实施方式中，在配置的传输速率为8条通道的传输速率之和，且多个对齐模块接收8条通道上的数据的情况下，通过多个对齐模块中的至少一个对齐模块，将所述缓存模块中的所有通道同步后的数据进行对齐，并将对齐的数据合并输出，包括：
通过1个第三对齐模块，将缓存模块中8个FIFO对应缓存的8条通道同步后的数据进行对齐，并所述8条通道同步后的数据合并输出；其中，第三对齐模块，被设置为将缓存模块中8个FIFO对应缓存的8条通道同步后的数据进行对齐，并将所述8条通道同步后的数据合并输出。
具体的，如图7所示，一个通道的数据速率为25GE，配置速率包括1个200GE，通过8个同步模块(lsync)对应接收8个通道上的数据，并对接收的数据进行同步，将同步后的数据缓存至对应的8个FIFO中；通过1个第三对齐模块(align_8)将8个FIFO中缓存的8条通道同步后的数据进行对齐，并将8个FIFO缓存的8条通道同步后的数据进行合并输出。
需要说明的是图1，图2-图7中，箭头的流向为数据的流向，图2-图7中，带有箭头的曲线流向为不同配置速率下真实的数据流向。
本申请提供的技术方案可以支持多种以太网速率的配置和组合，通信芯片中只包含一套缓存模块，其中，缓存模块可以包括8个FIFO，在数据处理过程中，可以使通信芯片既可以灵活配置，使用，又可以节约电路逻辑资源，降低通信芯片面积和功耗。

Claims (12)

  1. 一种通信芯片，其特征在于，包括：多个同步模块、一套缓存模块和多个对齐模块；
    其中，所述同步模块，被设置为接收对应通道的数据，并对接收的所述数据进行同步，并将同步后的数据存入所述缓存模块；
    所述缓存模块包括多个先入先出队列FIFO；所述FIFO，被设置为缓存对应同步模块输出的同步后的数据；
    所述对齐模块，被设置为将所述缓存模块中的对应通道同步后的数据进行对齐，并将对齐的数据合并输出。
  2. 根据权利要求1所述的通信芯片，其特征在于，多个对齐模块输出数据的速率不完全相同。
  3. 根据权利要求1或2所述的通信芯片，其特征在于，所述同步模块的数量为8个，所述对齐模块的数量为7个；所述FIFO的数量为8个。
  4. 根据权利要求3所述的通信芯片，其特征在于，所述多个对齐模块包括4个第一对齐模块，2个第二对齐模块和1个第三对齐模块；
    其中，所述第一对齐模块，被设置为将两个FIFO对应缓存的两条通道同步后的数据进行对齐，并将所述两条通道同步后的数据合并输出；
    所述第二对齐模块，被设置将4个FIFO对应缓存的4条通道同步后的数据进行对齐，并将所述4条通道同步后的数据合并输出；
    所述第三对齐模块，被设置为将8个FIFO对应缓存的8条通道同步后的数据进行对齐，并将所述8条通道同步后的数据进行合并输出。
  5. 一种数据处理方法，其特征在于，所述方法应用于如权利要求1-4任一项所述的通信芯片，所述方法包括：
    通过同步模块接收对应通道上的数据，并对接收的所述数据进行同步，并将同步后的数据存入缓存模块；
    通过所述缓存模块中的每个先入先出队列FIFO缓存对应同步模块输出的同步后的数据；
    通过多个对齐模块中的至少一个对齐模块，将所述缓存模块中的所有通道同步后的数据进行对齐，并将对齐的数据合并输出。
  6. 根据权利要求5所述的方法，其特征在于，所述方法还包括：
    通过所述同步模块将同步状态信息以及通道标识发送给配置速率对应的对齐模块；
    在所述缓存模块缓存与配置速率对应的全部通道同步后的数据的情况下，向所述配置速率对应的对齐模块发送通知消息；
    所述将所述缓存模块中的所有通道同步后的数据进行对齐，并将对齐的数据合并输出，包括：
    在接收到所述同步状态信息以及所述通知消息的情况下，读取所述缓存模块中FIFO缓存的对应通道的同步后的数据，并基于所述通道标识将读取的数据进行排列并输出。
  7. 根据权利要求5所述的方法，其特征在于，
    在配置速率为一个通道的数据速率的情况下，通过每个所述同步模块接收对应通道上的数据，并对接收的所述数据进行同步，并将同步后的数据发送至下游的接收侧。
  8. 根据权利要求5或6所述的方法，其特征在于，
    在配置速率为两条通道的数据速率之和，且多个对齐模块分别对应接收8条通道上的数据的情况下，
    通过多个对齐模块中的至少一个对齐模块，将所述缓存模块中的所有通道同步后的数据进行对齐，并将对齐的数据合并输出，包括：
    通过4个第一对齐模块，将缓存模块中8个FIFO对应缓存的8条通道同步后的数据进行对齐，并将对齐的数据合并输出；
    其中，每个第一对齐模块，被设置为将缓存模块中两个FIFO对应缓存的两道通道同步后的数据进行对齐，并将所述两条通道同步后的数据合并输出。
  9. 根据权利要求5或6所述的方法，其特征在于，
    在配置速率为4条通道的数据速率之和，且多个对齐模块接收8条通道上的数据的情况下，
    通过多个对齐模块中的至少一个对齐模块，将所述缓存模块中的所有通道同步后的数据进行对齐，并将对齐的数据合并输出，包括：
    通过两个第二对齐模块，将缓存模块中8个FIFO对应缓存的8条通道同 步后的数据进行对齐，并将对齐的数据合并输出；
    其中，每个第二对齐模块，被设置为将缓存模块中4个FIFO对应缓存的4条通道同步后的数据进行对齐，并将所述4条通道同步后的数据合并输出。
  10. 根据权利要求5或6所述的方法，其特征在于，
    在配置的传输速率为8条通道的传输速率之和，且多个对齐模块接收8条通道上的数据的情况下，
    通过多个对齐模块中的至少一个对齐模块，将所述缓存模块中的所有通道同步后的数据进行对齐，并将对齐的数据合并输出，包括：
    通过1个第三对齐模块，将缓存模块中8个FIFO对应缓存的8条通道同步后的数据进行对齐，并所述8条通道同步后的数据合并输出；
    其中，第三对齐模块，被设置为将缓存模块中8个FIFO对应缓存的8条通道同步后的数据进行对齐，并将所述8条通道同步后的数据合并输出。
  11. 根据权利要求5或6所述的方法，其特征在于，在配置速率包括4条通道的数据速率之和，以及两条通道的数据速率，且多个对齐模块接收8条通道上的数据的情况下，
    通过多个对齐模块中的至少一个对齐模块，将所述缓存模块中的所有通道同步后的数据进行对齐，并将对齐的数据合并输出，包括：
    通过1个第二对齐模块，将缓存模块中4个FIFO对应缓存的4条通道同步后的数据进行对齐，并通过两个第一对齐模块，将缓存模块中另外4个FIFO对应缓存的4条通道同步后的数据进行对齐，以及将同步后的数据合并输出。
  12. 根据权利要求5或6所述的方法，其特征在于，还包括：
    在每两条通道同步后的数据之间的时间偏斜超过设定范围的情况下，通过所述对齐模块对所述缓存模块中的FIFO进行清空，并返回通过每个同步模块接收对应通道上的数据，并对接收的所述数据进行同步，并将同步后的数据存入缓存模块的操作。
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