WO2022092583A1

WO2022092583A1 - Three-dimensional flash memory and method for manufacturing same

Info

Publication number: WO2022092583A1
Application number: PCT/KR2021/013143
Authority: WO
Inventors: 송윤흡; 송창은
Original assignee: 한양대학교 산학협력단; 페디셈 주식회사
Priority date: 2020-10-29
Filing date: 2021-09-27
Publication date: 2022-05-05
Also published as: KR20220057049A; KR102497881B1

Abstract

Disclosed is a three-dimensional flash memory having a structure which includes an air gap, a method for manufacturing same, and a method for improving vertical hole defects in a three-dimensional flash memory. In order to form the air gap, a step for preparing a hole formed to extend in the vertical direction inside a channel layer, and a step for forming the air gap inside the channel layer by forming a cap that seals the top of the hole, are included. In addition, in order to improve vertical hole defects, a sacrificial film is deposited on an inner wall of at least one vertical hole so as to be filled by a spike generated on the inner wall of the at least one vertical hole, and while maintaining the sacrificial layer that is deposited on the spike, the sacrificial film that is deposited on the inner wall of the at least one vertical hole, excluding the spike, is removed.

Description

3D flash memory and manufacturing method thereof

The following embodiments relate to a three-dimensional flash memory, and more particularly, to improve a technology for a three-dimensional flash memory having a structure including an air gap and a defect in a vertical hole formed in a manufacturing process of the three-dimensional flash memory. it is technology

A flash memory device is an Electrically Erasable Programmable Read Only Memory (EEPROM), the memory being, for example, in a computer, digital camera, MP3 player, game system, memory stick. ) can be commonly used. Such a flash memory device electrically controls input/output of data by Fowler-Nordheimtunneling or hot electron injection.

Specifically, referring to FIG. 1 showing a conventional three-dimensional flash memory array, the three-dimensional flash memory array includes a common source line CSL, a bit line BL, and a common source line CSL and a bit line BL. ) may include a plurality of cell strings (CSTR) disposed between.

The bit lines are two-dimensionally arranged, and a plurality of cell strings CSTR are connected in parallel to each of the bit lines. The cell strings CSTR may be commonly connected to the common source line CSL. That is, a plurality of cell strings CSTR may be disposed between the plurality of bit lines and one common source line CSL. In this case, there may be a plurality of common source lines CSL, and the plurality of common source lines CSL may be two-dimensionally arranged. Here, the same voltage may be applied to the plurality of common source lines CSL, or each of the plurality of common source lines CSL may be electrically controlled.

Each of the cell strings CSTR includes a ground select transistor GST connected to the common source line CSL, a string select transistor SST connected to the bit line BL, and ground and string select transistors GST and SST. ) may be formed of a plurality of memory cell transistors MCT disposed between. In addition, the ground select transistor GST, the string select transistor SST, and the memory cell transistors MCT may be connected in series.

The common source line CSL may be commonly connected to sources of the ground select transistors GST. In addition, the ground select line GSL, the plurality of word lines WL0 - WL3 and the plurality of string select lines SSL disposed between the common source line CSL and the bit line BL are ground selectable. It may be used as electrode layers of the transistor GST, the memory cell transistors MCT, and the string select transistors SST, respectively. In addition, each of the memory cell transistors MCT includes a memory element. Hereinafter, the string selection line SSL may be expressed as an upper selection line USL, and the ground selection line GSL may be expressed as a lower selection line LSL.

On the other hand, the conventional 3D flash memory increases the degree of integration by vertically stacking cells in order to meet the excellent performance and low price demanded by consumers.

For example, referring to FIG. 2 showing the structure of a conventional three-dimensional flash memory, in the conventional three-dimensional flash memory, interlayer insulating layers 211 and horizontal structures 250 are alternately formed on a substrate 200 . Repeatedly formed electrode structures 215 are disposed and manufactured. The interlayer insulating layers 211 and the horizontal structures 250 may extend in the first direction. The interlayer insulating layers 211 may be, for example, a silicon oxide layer, and the lowermost interlayer insulating layer 211a of the interlayer insulating layers 211 may have a thickness smaller than that of the other interlayer insulating layers 211 . Each of the horizontal structures 250 may include first and second blocking

insulating layers

242 and 243 and an electrode layer 245 . A plurality of electrode structures 215 may be provided, and the plurality of electrode structures 215 may be disposed to face each other in a second direction crossing the first direction. The first and second directions may correspond to the x-axis and the y-axis of FIG. 2 , respectively. Trenches 240 separating the plurality of electrode structures 215 may extend in the first direction. Highly doped impurity regions may be formed in the substrate 200 exposed by the trenches 240 , so that a common source line CSL may be disposed. Although not shown, isolation insulating layers filling the trenches 240 may be further disposed.

Vertical structures 230 penetrating the electrode structure 215 may be disposed. For example, in a plan view, the vertical structures 230 may be arranged in a matrix form along the first and second directions. As another example, the vertical structures 230 may be arranged in the second direction, and may be arranged in a zigzag shape in the first direction. Each of the vertical structures 230 may include a passivation layer 224 , a charge storage layer 225 , a tunnel insulating layer 226 , and a channel layer 227 . For example, the channel layer 227 may be disposed in the form of a hollow tube therein. In this case, a buried film 228 (formed of oxide) filling the inside of the channel layer 227 may be further disposed. can A drain region D may be disposed on the channel layer 227 , and a conductive pattern 229 may be formed on the drain region D to be connected to the bit line BL. The bit line BL may extend in a direction crossing the horizontal electrodes 250 , for example, in a second direction. For example, the vertical structures 230 aligned in the second direction may be connected to one bit line BL.

The first and second blocking

insulating layers

242 and 243 included in the horizontal structures 250 and the charge storage layer 225 and the tunnel insulating layer 226 included in the vertical structures 230 are the 3D flash memory. It can be defined as an oxide-nitride-oxide (ONO) layer that is an information storage element. That is, some of the information storage elements may be included in the vertical structures 230 , and others may be included in the horizontal structures 250 . For example, among the information storage elements, the charge storage layer 225 and the tunnel insulating layer 226 are included in the vertical structures 230 , and the first and second blocking

insulating layers

242 and 243 are the horizontal structures 250 . can be included in

Epitaxial patterns 222 may be disposed between the substrate 200 and the vertical structures 230 . The epitaxial patterns 222 connect the substrate 200 and the vertical structures 230 . The epitaxial patterns 222 may contact the horizontal structures 250 of at least one layer. That is, the epitaxial patterns 222 may be disposed to be in contact with the lowermost horizontal structure 250a. According to another embodiment, the epitaxial patterns 222 may be disposed to contact the horizontal structures 250 of a plurality of layers, for example, two layers. Meanwhile, when the epitaxial patterns 222 are disposed to be in contact with the lowermost horizontal structure 250a , the lowermost horizontal structure 250a may be disposed to be thicker than the remaining horizontal structures 250 . The lowermost horizontal structure 250a in contact with the epitaxial patterns 222 may correspond to the ground selection line GSL of the 3D flash memory array described with reference to FIG. 1 , and the vertical structures 230 . The remaining horizontal structures 250 in contact with may correspond to a plurality of word lines WL0-WL3.

Each of the epitaxial patterns 222 has a recessed sidewall 222a. Accordingly, the lowermost horizontal structure 250a in contact with the epitaxial patterns 222 is disposed along the profile of the recessed sidewall 222a. That is, the lowermost horizontal structure 250a may be disposed in a convex shape inward along the recessed sidewalls 222a of the epitaxial patterns 222 .

In the conventional 3D flash memory having such a structure, as shown in FIG. 3 , since the channel layer 227 is in contact with the tunnel insulating layer 226 and the buried layer 228 inside and out, the channel layer 227 and the tunnel insulating layer ( 226), surface scattering occurs at the interface 310, and surface scattering occurs at the interface 320 between the channel layer 227 and the buried film 228, so that the channel current flowing through the channel layer 227 is reduced. have the problem of being

Accordingly, in the following embodiments, it is necessary to propose a technique for solving the problem of reducing the channel current of the existing 3D flash memory.

In addition, in the 3D flash memory, in the process of creating the vertical hole 910 in which the memory cell string is to be formed, as shown in FIGS. 9A and 9B showing the 3D flash memory in order to account for the failure of the spike generated on the inner wall of the vertical hole, vertical There may be a defect in which a spike 920 is generated on the inner wall of the hole 910 .

Accordingly, it is necessary to propose a technique for alleviating and removing the spike 920 generated on the inner wall of the vertical hole 910 in the 3D flash memory.

In one embodiment, to increase the channel current by suppressing surface scattering at the interface between the channel layers to improve the charge mobility (Mobility), a structure in which an air gap is formed extending in the vertical direction inside the channel layer of a three-dimensional flash memory and a method for manufacturing the same.

One embodiment proposes a method for improving a vertical hole defect for alleviating and removing a spike generated on an inner wall of a vertical hole in a 3D flash memory.

According to an embodiment, a 3D flash memory may include a plurality of word lines extending in a horizontal direction on a substrate and sequentially stacked; and at least one string extending in a vertical direction on the substrate through the plurality of word lines. The at least one string has a hollow tube shape and surrounds the channel layer and the channel layer extending in the vertical direction. It may include a charge storage layer extending in the vertical direction so as to extend in the vertical direction, and an air gap may be formed extending in the vertical direction inside the channel layer.

According to an aspect, the air gap may be used to improve charge mobility by suppressing surface scattering at an interface between the channel layers.

According to another aspect, a cap for maintaining the air gap may be disposed on the upper end of the at least one string.

According to another aspect, the cap may be formed of a material different from that of the channel layer.

According to an embodiment, a method of manufacturing a 3D flash memory includes: a plurality of word lines extending in a horizontal direction on a substrate and sequentially stacked; and at least one string extending in a vertical direction on the substrate through the plurality of word lines. The at least one string has a hollow tube shape and surrounds the channel layer and the channel layer extending in the vertical direction. preparing a semiconductor structure including a charge storage layer extending in the vertical direction to ensure that the channel layer includes a hole extending in the vertical direction; and forming a cap sealing the top of the hole to create an air gap in the channel layer.

According to an embodiment, a method for improving a vertical hole defect in a 3D flash memory includes a plurality of sacrificial layers extending in a horizontal direction and sequentially stacked on a substrate, and a vertical direction on the substrate to penetrate the plurality of sacrificial layers. depositing a sacrificial layer on the inner wall of the at least one vertical hole to fill the spike generated in the inner wall of the at least one vertical hole in a semiconductor structure including at least one vertical hole extending from and removing the sacrificial layer deposited on the inner wall of the at least one vertical hole except for the spike while maintaining the sacrificial layer deposited on the spike.

According to an aspect, the sacrificial layer may be made of the same material as the plurality of sacrificial layers.

According to another aspect, the depositing of the sacrificial layer on the inner wall of the at least one vertical hole may include: identifying a region in which the spike is generated in the inner wall of the at least one vertical hole; and when it is determined that the spike is generated in the region corresponding to the plurality of sacrificial layers on the inner wall of the at least one vertical hole, the sacrificial film is deposited on the inner wall of the at least one vertical hole. It may be characterized in that it further comprises the step of

According to another aspect, the depositing of the sacrificial layer on the inner wall of the at least one vertical hole may include: identifying a region where the spike is generated in the inner wall of the at least one vertical hole; and if the spike is not generated in the region corresponding to the plurality of sacrificial layers on the inner wall of the at least one vertical hole as a result of determining the region where the spike occurs, do not deposit the sacrificial film on the inner wall of the at least one vertical hole It may be characterized in that it further comprises a step of determining not to.

According to an embodiment, in a method of manufacturing a 3D flash memory for improving vertical hole defects, a plurality of sacrificial layers extending in a horizontal direction and sequentially stacked on a substrate and on the substrate to penetrate the plurality of sacrificial layers are provided. depositing a sacrificial layer on an inner wall of the at least one vertical hole to fill a spike generated in the inner wall of the at least one vertical hole in a semiconductor structure including at least one vertical hole extending in a vertical direction; removing the sacrificial layer deposited on an inner wall of the at least one vertical hole except for the spike while maintaining the sacrificial layer deposited on the spike; depositing a charge storage layer on an inner wall of the at least one vertical hole from which the sacrificial layer is removed; removing the plurality of sacrificial layers from the semiconductor structure; and forming a plurality of word lines in a space from which the plurality of sacrificial layers are removed.

One embodiment proposes a three-dimensional flash memory having a structure in which an air gap is formed extending in a vertical direction inside a channel layer and a method for manufacturing the same, thereby suppressing surface scattering at the interface between the channel layers to increase charge mobility (Mobility) can be improved to increase the channel current.

One embodiment may propose a method for improving a vertical hole defect for alleviating and removing a spike generated on an inner wall of a vertical hole in a 3D flash memory.

1 is a simplified circuit diagram illustrating an array of a conventional three-dimensional flash memory.

2 is a perspective view showing the structure of a conventional three-dimensional flash memory.

FIG. 3 is a diagram for explaining that a channel current is reduced due to surface scattering at an interface between channel layers in a conventional 3D flash memory.

4 is a Y-Z cross-sectional view illustrating a three-dimensional flash memory according to an exemplary embodiment.

FIG. 5 is a diagram for explaining increasing a channel current in the 3D flash memory shown in FIG. 4 .

6 is a flowchart illustrating a method of manufacturing a 3D flash memory according to an exemplary embodiment.

7A to 7C are Y-Z cross-sectional views illustrating a three-dimensional flash memory to explain an embodiment of the manufacturing method illustrated in FIG. 6 .

8A to 8C are Y-Z cross-sectional views illustrating a three-dimensional flash memory to explain another embodiment of the manufacturing method illustrated in FIG. 6 .

9A is an X-Y plan view illustrating a three-dimensional flash memory in order to explain a failure of a spike generated on an inner wall of a vertical hole.

9B is an X-Z cross-sectional view illustrating a three-dimensional flash memory in order to explain a failure of a spike generated on an inner wall of a vertical hole.

10 is a flowchart illustrating a method for improving a vertical hole defect according to an exemplary embodiment.

11 is a flowchart illustrating a method of manufacturing a 3D flash memory based on the method for improving vertical hole defects illustrated in FIG. 10 .

12A to 12G are X-Z cross-sectional views illustrating a three-dimensional flash memory to explain the manufacturing method illustrated in FIG. 11 .

Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. However, the present invention is not limited or limited by the examples. Also, like reference numerals in each figure denote like members.

In addition, the terms used in this specification are terms used to properly express the preferred embodiment of the present invention, which may vary depending on the intention of a user or operator or customs in the field to which the present invention belongs. Accordingly, definitions of these terms should be made based on the content throughout this specification.

Hereinafter, in the Y-Z cross-sectional view showing the three-dimensional flash memory, components such as a bit line positioned above the plurality of strings and a source line positioned below the plurality of strings are omitted for the convenience of explanation of the three-dimensional flash memory. can be illustrated and described. However, the 3D flash memory to be described later is not limited thereto, and may further include additional components based on the structure of the existing 3D flash memory illustrated with reference to FIG. 2 .

4 is a Y-Z cross-sectional view illustrating a three-dimensional flash memory according to an exemplary embodiment, and FIG. 5 is a view for explaining increasing a channel current in the three-dimensional flash memory illustrated in FIG. 4 .

4 to 5 , the 3D flash memory 400 according to an exemplary embodiment includes a plurality of word lines 410 and at least one string 420 .

The plurality of word lines 410 are sequentially stacked while extending in a horizontal direction (eg, Y direction) on the substrate 405 , respectively, W (tungsten), Ti (titanium), Ta (tantalum), Cu ( Copper), Mo (molybdenum), Ru (ruthenium), or Au (gold) is formed of a conductive material (all metal materials capable of forming ALDs are included in addition to the described metal materials), and a voltage is applied to the corresponding memory cells. Memory operations (such as a read operation, a program operation, and an erase operation) may be performed. A plurality of insulating layers 411 formed of an insulating material may be interposed between the plurality of word lines 410 .

A String Selection Line (SSL) may be disposed at the upper end of the plurality of word lines 410 , and a Ground Selection Line (GSL) may be disposed at the lower end of the plurality of word lines 410 .

At least one string 420 passes through the plurality of word lines 410 and extends in a vertical direction (eg, Z direction) on the substrate 405 , and each of a channel layer 421 and a charge storage layer ( By including 422 , a plurality of memory cells corresponding to the plurality of word lines 410 may be configured.

The charge storage layer 422 is formed to extend to surround the channel layer 421 , and traps charges or holes caused by voltages applied through the plurality of word lines 410 , or states of charges (eg, electric charges). As a component that maintains their polarization state), it may serve as a data storage in the three-dimensional flash memory 400 . For example, an oxide-nitride-oxide (ONO) layer or a ferroelectric layer may be used as the charge storage layer 422 .

The channel layer 421 is a component that performs a memory operation by a voltage applied through the plurality of word lines 410, SSL, GSL, and bit lines, and may be formed of dicrystalline silicon or polysilicon.

Here, an air gap 423 may be formed to extend in a vertical direction inside the channel layer 421 . The air gap 423 may be maintained in a vacuum state or in a state in which a gas is injected by the cap 424 disposed on the upper end of the channel layer 421 .

The air gap 423 may be used to improve charge mobility by suppressing surface scattering at the interface between the channel layers 421 . More specifically, in the structure including the air gap 423 , as shown in FIG. 5 , between the channel layer 421 and the charge storage layer 422 (eg, an external oxide layer included in the charge storage layer 422 ). Since surface scattering occurs only at the interface 510 of It can be improved to increase the channel current.

In this case, the cap 424 may be formed of a material different from that of the channel layer 421 so as not to affect or minimize the memory operation of the 3D flash memory 400 as the channel is formed in the channel layer 421 . That is, the cap 424 is made of a material that does not form a channel by the voltage applied through the plurality of word lines 410 , and thus the 3D flash memory 400 is formed in the channel layer 421 . may not affect the memory operation of Otherwise, the cap 424 is made of a material having at least a charge mobility lower than that of the channel layer 421 , so that a channel is formed in the channel layer 421 . The effect on the operation can be minimized.

6 is a flowchart illustrating a manufacturing method of a three-dimensional flash memory according to an embodiment, and FIGS. 7A to 7C are Y-Z cross-sectional views illustrating a three-dimensional flash memory to explain an embodiment of the manufacturing method shown in FIG. , FIGS. 8A to 8C are Y-Z cross-sectional views illustrating a three-dimensional flash memory to explain another embodiment of the manufacturing method illustrated in FIG. 6 .

Hereinafter, it is assumed that the manufacturing method described below is performed by an automated and mechanized manufacturing system, and the 3D flash memory manufactured through the manufacturing method may have the structure described with reference to FIGS. 4 to 5 .

Referring to FIG. 6 , in the manufacturing system according to an embodiment, in step S610 , the

semiconductor structures

710 and 810 may be prepared as shown in FIGS. 7A or 8A .

Here, the

semiconductor structures

710 and 810 extend in the horizontal direction on the

substrates

705 and 805 and pass through the plurality of

word lines

711 and 811 and the plurality of

word lines

711 and 811 sequentially stacked. Thus, at least one

string

720 and 820 extending in a vertical direction on the

substrates

705 and 805 may be included. The at least one

string

720, 820 has the channel layers 721 and 821 extending in the vertical direction in the form of an empty tube and the charge storage layer extending in the vertical direction to surround the channel layers 721 and 821 ( 722 and 822 may be included, and since the channel layers 721 and 821 have a hollow tube shape, they may include

holes

723 and 823 extending in a vertical direction therein.

Subsequently, the manufacturing system forms caps 730 and 830 for sealing the upper ends of the

holes

723 and 823 included in the

semiconductor structures

710 and 810 in step S620, so that the channel layer 721,

Air gaps

740 and 840 may be created in the interior of the 821 .

The

air gaps

740 and 840 may be used to improve charge mobility by suppressing surface scattering at the interface between the channel layers 721 and 821, and the

caps

730 and 830 are A material having a lower charge mobility than that of the channel layer 721 or a material that does not form a channel by a voltage applied through the plurality of word lines 711 is different from the channel layers 721 and 821 . It may be formed of a material.

In this case, the manufacturing system may position the

semiconductor structures

710 and 810 in the chamber in step S620 to adjust the pressure of the space in which the

semiconductor structures

710 and 810 are located.

Referring to Figs. 7b to 7c as an embodiment for step S620, the manufacturing system seals the top of the hole 723 with nonconformality polysilicon as shown in Fig. 7b, and then performs a planarization process as shown in Fig. 7c. By performing the process to form the cap 730 , the air gap 740 may be created in the channel layer 721 .

Referring to Figs. 8b to 7c as another embodiment for step S620, the manufacturing system deposits a metal material on the top of the hole 823 as shown in Fig. 8b and seals it, and then performs a planarization process as shown in Fig. 8c. By forming the cap 830 , an air gap 840 may be created in the channel layer 821 .

Hereinafter, in the X-Z cross-sectional view illustrating the three-dimensional flash memory, the three-dimensional flash memory may be illustrated and described while omitting components such as bit lines and source lines for convenience of description. However, the 3D flash memory to be described later is not limited thereto, and may further include additional components based on the structure of the existing 3D flash memory.

10 is a flowchart illustrating a method for improving a vertical hole defect according to an exemplary embodiment. Hereinafter, the method for improving the vertical hole defect described may be performed by being included in the manufacturing method of the 3D flash memory, and the execution subject may be an automated or mechanized manufacturing system. However, the present invention is not limited thereto, and when the method for improving the vertical hole defect is performed separately from the manufacturing process of the 3D flash memory, the performing subject may be an automated or mechanized defect improvement system.

In step S1010, the manufacturing system may prepare a semiconductor structure. Here, the semiconductor structure may include a plurality of sacrificial layers extending in a horizontal direction on the substrate and sequentially stacked, and at least one vertical hole extending in a vertical direction on the substrate to penetrate the plurality of sacrificial layers.

Subsequently, in step S1020 , the manufacturing system may identify a region in which a spike is generated in the inner wall of the at least one vertical hole.

As a result of determining the region where the spike is generated, if the spike is generated in a region corresponding to the plurality of sacrificial layers on the inner wall of the at least one vertical hole, the manufacturing system deposits a sacrificial film on the inner wall of the at least one vertical hole in step S1030 can decide to

On the other hand, if the spike is not generated in the region corresponding to the plurality of sacrificial layers in the inner wall of the at least one vertical hole as a result of determining the region in which the spike is generated, the manufacturing system performs the step S1040 on the inner wall of the at least one vertical hole It may be decided not to deposit a sacrificial film on the .

After operation S1030 is performed, in operation S1050 , the manufacturing system may deposit a sacrificial film on the inner wall of the at least one vertical hole so that the spike generated on the inner wall of the at least one vertical hole in the semiconductor structure is filled.

In this case, the sacrificial layer is characterized in that it is made of the same material as the plurality of sacrificial layers. That is, the manufacturing system may deposit a sacrificial film made of the same material as the plurality of sacrificial layers on the inner wall of the at least one vertical hole in step S1050 to fill the spikes with the sacrificial film.

Thereafter, in operation S1060 , the manufacturing system may remove the sacrificial film deposited on the inner wall of the at least one vertical hole in a region excluding the spike while maintaining the sacrificial film deposited on the spike.

The above-described method for improving the vertical hole defect can be performed by being included in the manufacturing method of the 3D flash memory, and the method for improving the vertical hole defect will be described again with reference to FIGS. 12A to 12G below. Also, a method of manufacturing a 3D flash memory including a method for improving vertical hole defects will be described with reference to FIG. 11 below.

11 is a flowchart illustrating a manufacturing method of a three-dimensional flash memory based on the method for improving the vertical hole defect shown in FIG. It is an X-Z cross section. The manufacturing method described below assumes that it is performed by an automated and mechanized manufacturing system.

In operation S1105 , the manufacturing system may prepare the semiconductor structure 1210 as shown in FIG. 12A . Here, the semiconductor structure 1210 extends in a horizontal direction on the substrate 1205 and passes through the plurality of sacrificial layers 1211 and the plurality of sacrificial layers 1211 sequentially stacked in the vertical direction on the substrate 1205 . It may include at least one vertical hole 1212 that is formed to extend to.

Subsequently, in step S1110 , the manufacturing system may identify a region where the spike 1213 is generated in the inner wall of the at least one vertical hole 1212 .

As a result of determining the region in which the spike 1213 is generated, when the spike 1213 is generated in the region 1212-1 corresponding to the plurality of sacrificial layers 1211 in the inner wall of the at least one vertical hole 1212, manufacturing The system may determine to deposit the sacrificial layer 1220 on the inner wall of the at least one vertical hole 1212 in operation S1115 .

On the other hand, as a result of determining the region where the spike 1213 is generated, the spike 1213 is not generated in the region 1212-1 corresponding to the plurality of sacrificial layers 1211 in the inner wall of the at least one vertical hole 1212 . Otherwise, the manufacturing system may determine not to deposit the sacrificial layer 1220 on the inner wall of the at least one vertical hole 1212 in operation S1120 .

After step S1115 is performed, the manufacturing system in step S1125 performs at least one spike 1213 generated in the inner wall of at least one vertical hole 1212 in the semiconductor structure 1210 as shown in FIG. 12B to fill at least one A sacrificial layer 1220 may be deposited on the inner wall of the vertical hole 1212 in the

In this case, the sacrificial layer 1220 is characterized in that it is made of the same material as the plurality of sacrificial layers 1211 . That is, the manufacturing system deposits the sacrificial film 1220 , which is the same material as the plurality of sacrificial layers 1211 , on the inner wall of the at least one vertical hole 1212 in step S1125 to form the sacrificial film 1220 on the spike 1213 . ) can be filled.

Next, in step S1130 , the manufacturing system maintains the sacrificial film 1220 deposited on the spike 1213 as shown in FIG. 12C , and excludes the spike 1213 from the inner wall of the at least one vertical hole 1212 . The sacrificial layer 1220 deposited in the region may be removed.

Next, in step S1135 , the manufacturing system may deposit the charge storage layer 1230 on the inner wall of the at least one vertical hole 1212 from which the sacrificial layer 1220 is removed as shown in FIG. 12D .

Next, in operation S1140 , the manufacturing system may remove the plurality of sacrificial layers 1211 from the semiconductor structure 1210 as shown in FIG. 12E . In this case, the manufacturing system may remove the sacrificial layer 1220 deposited on the spike 1213 together with the plurality of sacrificial layers 1211 in operation S1140 .

Next, in operation S1145 , the manufacturing system may form a plurality of word lines 1240 in the space 1211-1 from which the plurality of sacrificial layers 1211 are removed as shown in FIG. 12F .

Thereafter, in step S1150 , the manufacturing system may form the channel layer 1250 in the charge storage layer 1230 as shown in FIG. 12G .

As such, the spike 1213 is filled with the same material as the sacrificial layer 1211 on which the word line 1240 is to be formed, and the spike 1213 is also removed in the process of removing the sacrificial layer 1211, so that steps S1105 to S1150 ), the 3D flash memory can solve the problem that the word line 1240 is non-uniformly formed by the spikes generated in the vertical hole.

As described above, although the embodiments have been described with reference to the limited embodiments and drawings, various modifications and variations are possible from the above description by those skilled in the art. For example, the described techniques are performed in an order different from the described method, and/or the described components of the system, structure, apparatus, circuit, etc. are combined or combined in a different form than the described method, or other components Or substituted or substituted by equivalents may achieve an appropriate result.

Therefore, other implementations, other embodiments, and equivalents to the claims are also within the scope of the following claims.

Claims

a plurality of word lines extending in a horizontal direction on a substrate and sequentially stacked; and

at least one string extending in a vertical direction on the substrate through the plurality of word lines, the at least one string having a hollow tube shape to surround the channel layer and the channel layer extending in the vertical direction and a charge storage layer extending in the vertical direction;

including,

Inside the channel layer,

3D flash memory, characterized in that the air gap (air gap) is formed to extend in the vertical direction.
According to claim 1,

The air gap is

3D flash memory, characterized in that it is used to improve charge mobility by suppressing surface scattering at the interface between the channel layers.
The method of claim 1,

At the upper end of the at least one string,

3D flash memory, characterized in that a cap (Cap) for maintaining the air gap is disposed.
4. The method of claim 3,

The cap is

3D flash memory, characterized in that it is formed of a material different from that of the channel layer.
a plurality of word lines extending in a horizontal direction on a substrate and sequentially stacked; and at least one string extending in a vertical direction on the substrate through the plurality of word lines. The at least one string has a hollow tube shape and surrounds the channel layer and the channel layer extending in the vertical direction. preparing a semiconductor structure including a charge storage layer extending in the vertical direction to ensure that the channel layer includes a hole extending in the vertical direction; and

forming an air gap inside the channel layer by forming a cap sealing the top of the hole;

A method of manufacturing a three-dimensional flash memory comprising a.
6. The method of claim 5,

The air gap is

A method of manufacturing a three-dimensional flash memory, characterized in that it is used to improve charge mobility by suppressing surface scattering at an interface between the channel layers.
6. The method of claim 5,

The cap is

A method of manufacturing a three-dimensional flash memory, characterized in that it is formed of a material different from that of the channel layer.
A method for improving vertical hole defects in a three-dimensional flash memory, the method comprising:

In a semiconductor structure comprising: a plurality of sacrificial layers extending in a horizontal direction on a substrate and sequentially stacked; and at least one vertical hole extending in a vertical direction on the substrate to penetrate the plurality of sacrificial layers, the at least one depositing a sacrificial film on the inner wall of the at least one vertical hole to fill the spike generated on the inner wall of the vertical hole; and

removing the sacrificial layer deposited on an inner wall of the at least one vertical hole except for the spike while maintaining the sacrificial layer deposited on the spike;

A method for improving vertical hole defects, including.
9. The method of claim 8,

The sacrificial film,

The method for improving the vertical hole defect, characterized in that the same material as the plurality of sacrificial layers.
9. The method of claim 8,

The step of depositing the sacrificial film on the inner wall of the at least one vertical hole comprises:

identifying an area in which the spike is generated in the inner wall of the at least one vertical hole; and

As a result of determining the region in which the spike is generated, when the spike is generated in a region corresponding to the plurality of sacrificial layers on the inner wall of the at least one vertical hole, it is determined to deposit the sacrificial film on the inner wall of the at least one vertical hole step

Vertical hole defect improvement method, characterized in that it further comprises.
9. The method of claim 8,

The step of depositing the sacrificial film on the inner wall of the at least one vertical hole comprises:

identifying an area in which the spike is generated in the inner wall of the at least one vertical hole; and

If the spike is not generated in the region corresponding to the plurality of sacrificial layers on the inner wall of the at least one vertical hole as a result of determining the region where the spike occurs, do not deposit the sacrificial film on the inner wall of the at least one vertical hole step to decide

Vertical hole defect improvement method, characterized in that it further comprises.
A method of manufacturing a three-dimensional flash memory for improving vertical hole defects, the method comprising:

In a semiconductor structure comprising: a plurality of sacrificial layers extending in a horizontal direction on a substrate and sequentially stacked; and at least one vertical hole extending in a vertical direction on the substrate to penetrate the plurality of sacrificial layers, the at least one depositing a sacrificial film on the inner wall of the at least one vertical hole to fill the spike generated on the inner wall of the vertical hole;

removing the sacrificial layer deposited on an inner wall of the at least one vertical hole except for the spike while maintaining the sacrificial layer deposited on the spike;

depositing a charge storage layer on an inner wall of the at least one vertical hole from which the sacrificial layer is removed;

removing the plurality of sacrificial layers from the semiconductor structure; and

forming a plurality of word lines in a space from which the plurality of sacrificial layers are removed;

A method of manufacturing a three-dimensional flash memory comprising a.
13. The method of claim 12,

The sacrificial film,

The method of manufacturing a three-dimensional flash memory, characterized in that the same material as the plurality of sacrificial layers.
13. The method of claim 12,

The step of depositing the sacrificial film on the inner wall of the at least one vertical hole comprises:

identifying an area in which the spike is generated in the inner wall of the at least one vertical hole; and

As a result of determining the region in which the spike is generated, when the spike is generated in a region corresponding to the plurality of sacrificial layers on the inner wall of the at least one vertical hole, it is determined to deposit the sacrificial film on the inner wall of the at least one vertical hole step

Method of manufacturing a three-dimensional flash memory further comprising a.
13. The method of claim 12,

The step of depositing the sacrificial film on the inner wall of the at least one vertical hole comprises:

identifying an area in which the spike is generated in the inner wall of the at least one vertical hole; and

If the spike is not generated in the region corresponding to the plurality of sacrificial layers on the inner wall of the at least one vertical hole as a result of determining the region where the spike occurs, do not deposit the sacrificial film on the inner wall of the at least one vertical hole step to decide

Vertical hole defect improvement method, characterized in that it further comprises.