WO2022091803A1 - Method for producing semiconductor element, semiconductor element, and semiconductor device - Google Patents

Method for producing semiconductor element, semiconductor element, and semiconductor device Download PDF

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Publication number
WO2022091803A1
WO2022091803A1 PCT/JP2021/038102 JP2021038102W WO2022091803A1 WO 2022091803 A1 WO2022091803 A1 WO 2022091803A1 JP 2021038102 W JP2021038102 W JP 2021038102W WO 2022091803 A1 WO2022091803 A1 WO 2022091803A1
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Prior art keywords
mask
gan layer
semiconductor
manufacturing
layer
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PCT/JP2021/038102
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French (fr)
Japanese (ja)
Inventor
克典 東
高吉 藤田
克明 正木
雄一郎 林
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京セラ株式会社
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Priority to JP2022559002A priority Critical patent/JPWO2022091803A1/ja
Publication of WO2022091803A1 publication Critical patent/WO2022091803A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/47—Schottky barrier electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/868—PIN diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/872—Schottky diodes

Definitions

  • the present disclosure relates to a method for manufacturing a semiconductor device, a semiconductor device, and a semiconductor device.
  • Patent Document 1 describes a GaN-based SBD (Schottky Barrier Diode) in which a GaN-based semiconductor is manufactured by an ELO (Epitaxial Lateral Overgrown) method using a mask made of SiO 2 .
  • the method for manufacturing a semiconductor element is a step of providing a first mask having a part open on the surface of the substrate and a step of forming a second mask so as to cover a part of the first mask.
  • the first mask includes a step of covering the first mask from the surface of the substrate exposed from the opening and epitaxially growing the second mask so as to expose the second mask to grow the first semiconductor layer. Includes a donor element in the first semiconductor layer, and the second mask does not contain a donor element in the first semiconductor layer.
  • the semiconductor device according to one embodiment is manufactured by the above-mentioned method for manufacturing a semiconductor device.
  • the semiconductor device includes a semiconductor device manufactured by the above-mentioned method for manufacturing a semiconductor device.
  • FIG. 1 is a schematic cross-sectional view for explaining a method for manufacturing a semiconductor device according to an embodiment.
  • FIG. 2 is a process diagram for explaining a method for manufacturing a semiconductor device according to an embodiment.
  • FIG. 3 is a process diagram for explaining an example of a growth mask manufacturing process included in the method for manufacturing a semiconductor device according to an embodiment.
  • FIG. 4 is a process diagram for explaining a method for manufacturing a semiconductor device according to an embodiment.
  • FIG. 5 is a schematic cross-sectional view for explaining a method for manufacturing a semiconductor element and the semiconductor element according to the embodiment.
  • FIG. 6 is a top view including a configuration in which a plurality of semiconductor elements are arranged in parallel.
  • FIG. 1 is a schematic cross-sectional view for explaining a method for manufacturing a semiconductor device according to an embodiment.
  • FIG. 2 is a process diagram for explaining a method for manufacturing a semiconductor device according to an embodiment.
  • FIG. 3 is a process diagram for explaining an example of a growth mask
  • FIG. 7 is a schematic cross-sectional view for explaining the semiconductor device according to the first modification of the embodiment.
  • FIG. 8 is a schematic cross-sectional view for explaining the semiconductor element according to the second modification of the embodiment.
  • FIG. 9 is a process diagram for explaining a method for manufacturing a semiconductor device according to the second modification of the embodiment.
  • the ELO method is carried out to grow flat crystals in a state where n + -type layers that are auto-doped on the mask are associated and the entire surface of the mask is covered to obtain Si.
  • the semiconductor element 1 is a power semiconductor used in a switching circuit of a power converter such as an inverter and a converter.
  • FIG. 1 is a schematic cross-sectional view for explaining a method of manufacturing the semiconductor element 1 according to the embodiment.
  • FIG. 2 is a process diagram for explaining the manufacturing method of the semiconductor element 1 according to the embodiment.
  • the first mask 21 is formed on the surface 11a of the base substrate (board) 11
  • the second mask 23 is formed on the surface 21a of the first mask 21.
  • the semiconductor layer 31 is formed on the surface 23a of the second mask 23.
  • the semiconductor layer 31 has an n + GaN layer 32 which is a first semiconductor layer, an n ⁇ GaN layer 33 which is a second semiconductor layer, and an n + GaN layer 34 which is a third semiconductor layer. ..
  • a first mask 21 made of, for example, SiO 2 is formed on the surface 11a of the GaN layer on the surface of the substrate 11 shown in FIG. 1 (step ST11) (first step). More specifically, a first mask 21 having a part of opening is provided on the surface 11a of the substrate 11. In other words, a first mask 21 having an opening 21s at least in a part thereof is provided on the surface 11a of the substrate 11.
  • the back surface of the surface layer of the substrate 11 opposite to the front surface 11a of the GaN layer may be supported by other than GaN such as a silicon substrate (not shown).
  • the substrate that supports the back surface of the GaN layer on the surface of the substrate 11 may be, for example, a sapphire substrate or a SiC (Silicon Carbide) substrate.
  • the first mask 21 contains an element that becomes a donor in the semiconductor layer 31.
  • the first mask 21 may be amorphous.
  • the first mask 21 has an opening 21s at least in part.
  • the thickness d1 of the first mask 21 is thinner than the thickness d2 of the GaN layer 32.
  • the sum of the thickness d1 of the first mask 21 and the thickness d3 of the second mask 23 may be thicker or thinner than the thickness d2 of the GaN layer 32.
  • the sum of the thickness d1 of the first mask 21 and the thickness d3 of the second mask 23 is thinner than the sum of the thickness d2 of the GaN layer 32 and the thickness d4 of the GaN layer 33.
  • the sum of the thickness d1 of the first mask 21 and the thickness d3 of the second mask 23 is thicker than the thickness d2 of the GaN layer 32.
  • the surface 21a of the first mask 21 is closer to the substrate 11 than the surface 32b of the GaN layer 32.
  • the surface 23a of the second mask 23 is separated from the surface 11a of the substrate 11 from the surface 32b of the GaN layer 32.
  • the step 24 is formed by the first mask 21 and the second mask 23. The step 24 is formed so as to face the opening 21s and the opening 23s.
  • a second mask 23 made of, for example, AlOx is formed on the surface 21a of the first mask 21 (step ST12) (second step). More specifically, the second mask 23 is formed so as to cover a part of the first mask 21. In other words, the second mask 23 is provided so as to cover at least a part of the surface 21a of the first mask 21.
  • the second mask 23 does not contain an element that becomes a donor in the semiconductor layer 31.
  • a material containing no Si such as AlON, W, and GaO may be used in addition to AlOx.
  • the second mask 23 covers at least a part of the surface 21a of the first mask 21.
  • the second mask 23 is arranged to include a position (hereinafter, referred to as “separation position”) P for separating the plurality of semiconductor elements 1 into individual pieces. In other words, the second mask 23 is arranged at a position including between the adjacent semiconductor elements 1.
  • the width w in the lateral direction orthogonal to the stacking direction of the second mask 23 may be, for example, 20 ⁇ m or more and 100 ⁇ m or less. If the width w is smaller than 20 ⁇ m, dry etching may not be properly performed in step ST46 described later. When the width w is larger than 100 ⁇ m, debris is generated on the second mask 23 when the ELO method is carried out in step ST13 described later.
  • the thickness d3 of the second mask 23 in the stacking direction is such that the surface 23a of the second mask 23 is separated from the surface 11a of the substrate 11 from the surface 33a of the GaN layer 33. It may have such a thickness. In other words, the sum of the thickness d1 of the first mask 21 and the thickness d3 of the second mask 23 may be thicker than the thickness d2 of the GaN layer 32.
  • the thickness d3 of the second mask 23 in the stacking direction may be, for example, 3 ⁇ m or more.
  • the peripheral portion of the semiconductor layer 31 is executed by executing the ELO method in step ST13.
  • the step is transferred to.
  • the thickness d3 in the stacking direction of the second mask 23 is such that the surface 23a of the second mask 23 is the surface 32b of the GaN layer 32 and the surface 11a of the substrate 11.
  • the thickness may be about the same.
  • the sum of the thickness d1 of the first mask 21 and the thickness d3 of the second mask 23 may be as thick as the thickness d2 of the GaN layer 32.
  • the thickness d3 in the stacking direction of the second mask 23 may be thinner than when the semiconductor element 1 having the mesa structure or trench structure is manufactured. ..
  • the thickness d3 of the second mask 23 in the stacking direction may be, for example, 1 ⁇ m or less.
  • FIG. 3 is a process diagram for explaining an example of a growth mask making process included in the manufacturing method of the semiconductor element 1 according to the embodiment.
  • An example of a growth mask making step including the first step and the second step will be described in detail with reference to FIG.
  • the process of step ST21 to step ST28 corresponds to step ST11 and step ST12.
  • a first mask 21 made of SiO 2 is formed on the surface 11a of the GaN layer on the surface of the substrate 11 (step ST21). More specifically, the first mask 21 is provided so as to cover the entire surface of the substrate 11 on the surface 11a.
  • the second mask 23 is formed on the surface 21a of the first mask 21 (step ST22). More specifically, the second mask 23 is provided so as to cover the entire surface of the first mask 21 on the surface 21a.
  • a resist mask 22 is formed on the surface 23a of the second mask 23 (step ST23). More specifically, the resist mask 22 is provided so as to cover a part of the surface 23a of the second mask 23.
  • the resist mask 22 is a photo on the surface 23a of the second mask 23 so as to cover the portion where the second mask 23 is not wet-etched in step S24, in other words, the portion where the second mask 23 is arranged after the execution of step S28.
  • the pattern is arranged using lithography.
  • a plurality of resist masks 22 are arranged at intervals on the surface 23a of the second mask 23.
  • the thickness d5 of the resist mask 22 is thicker than the thickness d3 of the second mask 23.
  • step ST24 Wet etching the second mask 23 (step ST24). More specifically, a part of the second mask 23 is wet-etched until the first mask 21 is exposed. At this time, since the resist mask 22 is present, the second mask 23 located below the resist mask 22 is not wet-etched. As a result, the side surface 21d of the first mask 21 and the side surface 23d of the second mask 23 are generated. By forming the side surface 21d of the first mask 21, the surface 21a'which is one step lower than the surface 21a is formed.
  • Etching the resist mask 22 (step ST25). More specifically, the resist mask 22 located on the surface 23a of the second mask 23 is etched. As a result, the surface 23a of the second mask 23 is exposed.
  • a resist pattern 25 having an opening 25s is formed on the surface 21a of the first mask 21 and the surface 23a of the second mask 23 (step ST26). More specifically, the resist pattern 25 is formed so as to cover the surface 21a'and the side surface 21d of the first mask 21 and the surface 23a and the side surface 23d of the second mask 23. At this time, the upper surface 25a of the resist pattern 25 becomes substantially flat.
  • step ST27 Wet etching the first mask 21 (step ST27). More specifically, the first mask 21 exposed in the opening 25s of the resist pattern 25 is wet-etched until the substrate 11 is exposed.
  • step ST28 Wet etching the resist pattern 25 (step ST28). More specifically, the resist pattern 25 located on the first mask 21 and the second mask 23 is wet-etched. As a result, the resist pattern 25 on the first mask 21 and the second mask 23 is removed, and a part of the surface 21a'of the first mask and the surface 23a of the second mask 23 are exposed.
  • the thickness d1 of the first mask 21 should be thicker than the thickness d3 of the second mask 23.
  • step ST24 While performing step ST24, the first mask 21 is wet-etched, and the thickness d1 becomes thinner than that of step ST23.
  • the growth mask is formed, and at the separation position P, the second mask 23 formed on the first mask 21 is exposed.
  • the surface 11a of the substrate 11 in the portion corresponding to the opening 21s is exposed from the opening 21s of the first mask 21.
  • the surfaces 11a located at both ends of the substrate 11 may be covered with the first mask 21.
  • the entire side surface or the back surface of the substrate 11 may be covered with the first mask 21.
  • the entire surface excluding the opening 21s may be covered with the first mask 21.
  • the GaN layer as the semiconductor layer 31 is formed from the surface 11a of the substrate 11 exposed from the opening 21s by using the above-mentioned ELO technique (step ST13) (third step). More specifically, as shown in FIG. 1, the semiconductor element 1 having the semiconductor layer 31 is formed by covering the first mask 21 from the surface 11a exposed from the opening 21s, and epitaxially growing the semiconductor so as to expose the second mask 23. Produce (third step).
  • the first mask 21 is covered and epitaxially grown so as to expose the second mask 23, and the first semiconductor is formed.
  • the GaN layer 32 which is a layer, is grown. More specifically, using ELO technology, in an epitaxial device (not shown), a high impurity concentration n + is used to cover the first mask 21 from the surface 11a of the substrate 11 exposed from the opening 21s and expose the second mask 23.
  • the type GaN layer 32 is epitaxially grown. In the present embodiment, the shape of the step 24 is transferred to the surface 32a of the GaN layer 32 of the semiconductor layer 31.
  • the GaN layer 32 first grows in the vertical direction from the surface 11a exposed from the opening 21s, and then grows in the horizontal direction so as to fill the step 24. As a result, the surface 32b of the GaN layer 32 becomes substantially flat.
  • the GaN layer 32 is auto-doped with impurities from the material constituting the first mask 21.
  • the impurity is Si (Silicon)
  • the GaN layer 32 is a highly concentrated n + semiconductor layer.
  • the doping amount of n-type impurities is controlled so that the electron carrier concentration is 10 18 cm -3 or more.
  • the GaN layer 32 stops epitaxial growth before associating.
  • the GaN layer 32 When the GaN layer 32 is formed, the entire surface of the first mask 21 provided on the substrate 11 is covered with the GaN layer 32 and the second mask 23. This reduces autodoping from the first mask 21 during ELO growth.
  • the GaN layer 33 which is the second semiconductor layer is grown. More specifically, in order to obtain a desired impurity concentration profile, the low impurity concentration GaN layer 33 is epitaxially grown so as to cover the GaN layer 32.
  • the GaN layer 33 first grows in the vertical direction from the surface 32b of the GaN layer 32, and then grows in the horizontal direction so as to fill the step 24. As a result, the surface 33b of the GaN layer 33 is also substantially flat.
  • the GaN layer 33 stops epitaxial growth before associating.
  • the GaN layer 33 is an n-semiconductor layer.
  • the doping amount of the n-type impurity is controlled in the GaN layer 33 so that the electron carrier concentration is less than 10 17 cm -3 . Since the GaN layer 33 is not in contact with the first mask 21 during epitaxial growth, autodoping is reduced. Further, since the first mask 21 is covered with the GaN layer 32 and the second mask 23, the autodoping of the GaN layer 33 is reduced.
  • the GaN layer 34 having a high impurity concentration is epitaxially grown so as to cover the GaN layer 33.
  • the GaN layer 34 first grows in the vertical direction from the surface 33b of the GaN layer 33, and then grows in the horizontal direction. As a result, the upper surface 34a of the GaN layer 34 is also substantially flat.
  • the GaN layer 34 stops epitaxial growth before associating.
  • the GaN layer 34 is an n + semiconductor layer.
  • the doping amount of n-type impurities is controlled so that the electron carrier concentration is 10 19 cm -3 or more. This high-concentration layer has low electrical resistance, and the electrical resistance of the joint with the electrode metal attached in the subsequent step can be lowered.
  • the semiconductor element 1 having the GaN layer 32 and the GaN layer 33 of the semiconductor layer 31 to which the shape of the step 24 is transferred is manufactured.
  • the semiconductor layer 31 is formed on the substrate 11, and the GaN layer 32 which is an n + type semiconductor layer, the GaN layer 33 which is an n ⁇ type semiconductor layer, and the GaN layer 34 which is an n + type semiconductor layer are laminated from the surface. Epitaxially grown to.
  • the semiconductor layers 31 are not associated with each other, so that the second mask 23 is exposed at the separation position P.
  • FIG. 4 is a process diagram for explaining the manufacturing method of the semiconductor device 2 according to the embodiment.
  • FIG. 5 is a schematic cross-sectional view for explaining the manufacturing method of the semiconductor element 1 and the semiconductor element 1 according to the embodiment. Steps ST41 to ST46 are performed after performing steps ST11 to ST13.
  • the semiconductor layer 31 of the semiconductor element 1 is attached to the support substrate 51 (step ST41). More specifically, the upper surface 34a of the GaN layer 34, which is the back surface 31b of the semiconductor layer 31 on the opposite side to the substrate 11, is bonded to the support substrate 51. As the bonding, the electrical resistance of the connection may be reduced by using a metal-based bonding or a direct bonding.
  • the back surface electrode 61 is formed on the support substrate 51 (step ST42). More specifically, the back surface electrode 61 is formed on the upper surface of the support substrate 51 by, for example, sputtering.
  • the back surface electrode 61 is, for example, an Al layer plated with Ti, Ni, or Au.
  • the back surface electrode 61 may be formed after the top surface electrode metal film 43, which will be described later, is formed. When the step of raising the temperature is included, the influence on the back surface electrode 61 can be avoided by performing step ST42 at the end.
  • the support substrate 51 may be a semiconductor having a high impurity concentration so as to have low electrical resistance.
  • step ST43 Remove the mask by wet etching (step ST43). More specifically, the second mask 23 and the first mask 21 exposed at the separation position P are melted by wet etching.
  • the semiconductor layer 31 is peeled off from the substrate 11 in a state where the upper surface 34a of the GaN layer 34, which is the back surface 31b of the semiconductor layer 31, is bonded to the support substrate 51 (step ST44). More specifically, the semiconductor layer 31 is peeled from the substrate 11 by cracking the crystal in the vicinity of the opening 21s with ultrasonic waves or the like.
  • step ST45 After peeling, it is turned upside down with the semiconductor element 1 (step ST45).
  • step ST46 Perform dry etching (step ST46). More specifically, the GaN layer 32 is melted by dry etching.
  • the dry-etched semiconductor element 1 has a mesa structure.
  • the step between the surfaces 32a and the surface 32c shown in FIG. 5 may be 0.5 ⁇ m or less, or may be about 0.1 ⁇ m.
  • the level difference between the surface 32b and the surface 32c shown in FIG. 5 may be about 0.5 ⁇ m or more and 10 ⁇ m or less.
  • step ST46 the surface 32a of the GaN layer 32 of the semiconductor layer 31 in contact with the first mask 21 and the second mask 23 is dry-etched to transfer the step 24.
  • the step of the GaN layer 32 is transferred to form a step 33c that is one step lower than the surface 33a of the GaN layer 33 and a step 33d that is one step lower than the step 33c.
  • a mesa structure or a trench structure is formed in the GaN layer 33 by transferring the step.
  • a case where the step 33c is used as a mesa structure is illustrated as an example.
  • step ST46 instead of dry etching the surface 32a of the GaN layer 32, the surface 32a of the GaN layer 32 may be polished to transfer the step 24. By polishing, damage to the semiconductor layer 31 can be reduced.
  • the electric field applied to the end of the electrode can be relaxed, so an element with high withstand voltage can be manufactured.
  • the semiconductor device 1 can be used, for example, as an SBD having a Schottky junction.
  • the manufacturing process described above is carried out simultaneously and in parallel so as to simultaneously manufacture a plurality of semiconductor elements 1 as shown in FIG. That is, a plurality of openings 21s are formed in the first mask 21. By associating one semiconductor element 1 with one opening 21s, a plurality of semiconductor elements 1 are simultaneously manufactured. In FIG. 1, a plurality of semiconductor elements 1 to be manufactured are arranged in parallel.
  • FIG. 6 is a top view including a configuration in which a plurality of semiconductor elements 1 are arranged in parallel. Specifically, as shown in FIG. 6, a common back surface electrode 61 is die-bonded to one electrode pad 201 on the mounting substrate 200, and each top surface electrode metal film is bonded to another electrode pad 202 by a bonding wire 52. Connecting.
  • the plurality of semiconductor elements 1 are manufactured so as to be arranged side by side in a certain direction.
  • the semiconductor element 1 has a long shape in a direction substantially orthogonal to the direction in which the semiconductor elements 1 are arranged in a plan view. By arranging the semiconductor elements 1 in line with such a shape, the junction area of the diode can be increased.
  • the semiconductor element 1 manufactured in this way can be used as various semiconductor devices 2 according to the application.
  • the second mask 23 that does not contain the element that becomes the donor or acceptor in the semiconductor layer 31 is superimposed on at least a part of the first mask 21 that contains the element that becomes the donor or acceptor in the semiconductor layer 31. Deploy.
  • the lateral end portion of the first mask 21 is covered with the second mask 23.
  • the epitaxial growth can be stopped before the GaN layer 32 is associated.
  • the occurrence of autodoping from the first mask 21 to the GaN layer 33 can be reduced.
  • the manufacturing time can be shortened and the labor required for manufacturing can be reduced.
  • the second mask 23 formed on the first mask 21 is exposed at the separation position P.
  • the second mask 23 and the first mask 21 can be removed from the separation position P by wet etching.
  • the semiconductor element 1 can be manufactured without performing dry etching for removing the first mask and the second mask 23 at the time of manufacturing. Since the present embodiment does not require dry etching for removing the first mask and the second mask 23, damage to the semiconductor can be reduced. Further, the present embodiment can reduce the occurrence of defects caused by dry etching for removing the first mask and the second mask 23.
  • the width w of the second mask 23 is, for example, 20 ⁇ m or more and 100 ⁇ m or less.
  • dry etching can be appropriately performed in step ST46.
  • the second mask 23 is arranged including a position where the plurality of semiconductor elements 1 are separated into individual pieces. According to this embodiment, since the semiconductor layer 31 does not associate at the separation position P, the plurality of semiconductor elements 1 can be easily separated into individual pieces.
  • the semiconductor element 1 in which the mesa structure or the trench structure is formed can be manufactured by transferring the step 24 of the first mask 21.
  • FIG. 7 is a schematic cross-sectional view for explaining the semiconductor element 1 according to the modified example 1 of the embodiment.
  • the semiconductor element 1 has a JBS (Junction Barrier Schottky) structure in which a pn junction and a Schottky junction are combined, which is connected to the anode. More specifically, the semiconductor device 1 according to the modification 1 is provided with a Schottky metal film (not shown) which is a metal layer (barrier metal), and a Schottky junction between the GaN layer 33 and the Schottky metal film is provided.
  • JBS Joint Barrier Schottky
  • the semiconductor device 1 manufactured by the manufacturing method according to the modified example 1 has a JBS structure formed on the surface 33a of the GaN layer 33.
  • the semiconductor device 2 includes such a semiconductor element 1.
  • Steps ST11 and ST12 are performed in the same manner as in the embodiment.
  • Steps ST41 to ST45 are performed in the same manner as in the embodiment.
  • a GaN layer as a semiconductor layer 31 is formed from the surface 11a of the substrate 11 exposed from the opening 21s (step ST13). More specifically, first, as in the embodiment, the n + type GaN layer 32 having a high impurity concentration is epitaxially grown.
  • the GaN layer 35 having a low impurity concentration is epitaxially grown so as to cover the GaN layer 32.
  • the GaN layer 35 first grows in the vertical direction from the surface 32b of the GaN layer 32 exposed from the opening 23s, and then grows in the horizontal direction so as to fill the step 24.
  • the GaN layer 35 is a p + type semiconductor layer.
  • the doping amount of the p-type impurity is controlled in the GaN layer 35 so that the hole carrier concentration is 10 18 cm -3 or more.
  • the surface 35b of the GaN layer 35 is substantially flat.
  • the GaN layer 35 has, for example, a thickness d6 of about 20 nm or more.
  • the subsequent GaN layer 33 first grows in the vertical direction from the surface 35b of the exposed GaN layer 35, and then grows in the horizontal direction so as to fill the step 24.
  • the GaN layer 34 first grows in the vertical direction from the surface 33b of the exposed GaN layer 33, and then grows in the horizontal direction.
  • step ST46 Dry etching the entire GaN layer 32 and a part of the GaN layer 35 (step ST46). More specifically, the entire surface of the surface 32a of the GaN layer 32 of the semiconductor layer 31 and a part of the GaN layer 35 in contact with the first mask 21 are dry-etched. Specifically, the GaN layer 32 and the GaN layer 35 are melted by at least either dry etching or wet etching. When the GaN layer 32 and the GaN layer 35 are wet-etched, the thickness d6 of the GaN layer 32 and the GaN layer 35 may be reduced to 1 ⁇ m or less. As a result, the GaN layer 35 formed on the surface 33a of the GaN layer 33 is removed except for a part.
  • the remaining GaN layer 35 is arranged in a rectangular frame shape on the surface 33a of the GaN layer 33.
  • the remaining GaN layers 35 are arranged in a triple nested manner, but the present invention is not limited to this, and one or more may be arranged.
  • the outer GaN layer 35 may be formed to be wider than the inner GaN layer 35.
  • the entire GaN layer 32 and a part of the GaN layer 35 may be polished. More specifically, the entire surface of the surface 32a of the GaN layer 32 of the semiconductor layer 31 and a part of the GaN layer 35 may be polished in contact with the first mask 21. Specifically, the GaN layer 32 is polished until the GaN layer 35 is exposed. After that, a part of the GaN layer 35 is masked and the GaN layer 35 is dry-etched. As a result, since the GaN layer 35 is thinner than the GaN layer 32, the etching rate becomes low and damage to the semiconductor layer 31 can be reduced without taking time.
  • the JBS structure can be formed by removing the entire GaN layer 32 of the semiconductor layer 31 and a part of the GaN layer 35 in contact with the first mask 21.
  • the electric field applied to the end of the electrode can be relaxed by forming the field plate.
  • the semiconductor element 1 having an increased surge withstand current can be manufactured.
  • the semiconductor element 1 having an increased withstand voltage can be manufactured.
  • FIG. 8 is a schematic cross-sectional view for explaining the semiconductor element 1 according to the second modification of the embodiment.
  • FIG. 9 is a process diagram for explaining a method of manufacturing the semiconductor device 2 according to the second modification of the embodiment.
  • the semiconductor device 1 according to the second modification has a JBS structure and a FLR (Field Limiting Ring) structure.
  • the semiconductor device 1 manufactured by the manufacturing method according to the modification 2 has an FLR structure formed on the surface 33a of the GaN layer 33.
  • the semiconductor device 2 includes such a semiconductor element 1.
  • the semiconductor element 1 does not have a mesa structure but has an FLR structure.
  • the sum of the thickness d1 of the first mask 21 and the thickness d3 of the second mask 23 may be about the same as the thickness d2 of the GaN layer 32.
  • the thickness d3 of the second mask 23 in the stacking direction may be, for example, 1 ⁇ m or less.
  • the semiconductor element 1 shown in FIG. 9 executes the same process as the semiconductor element 1 of the modification 1 from step ST11 to step ST45.
  • the GaN layer 35 remaining after the execution of step ST46 is arranged in a quadruple nested manner.
  • the inner triple GaN layer 35 forms a JBS structure and the outer GaN layer 35 forms an FLR structure.
  • JBS and FLR structures are not limited to this.
  • a Schottky metal film 41 to be Schottky bonded is formed on the surface 33a of the exposed GaN layer 33 (step ST47).
  • the Schottky metal film 41 covers the intermediate portion of the surface 33a of the exposed GaN layer 33 and the GaN layer 35 arranged in the intermediate portion of the surface 33a of the GaN layer 33.
  • the Schottky metal film 41 is arranged so as to cover the inner GaN layer 35 and the surface 33a of the GaN layer 33 exposed between them.
  • a Schottky junction between the GaN layer 33 and the Schottky metal film 41 is provided.
  • the Schottky metal film 41 is not arranged on the peripheral edge of the surface 33a of the GaN layer 33, in other words, on the portion forming the FLR structure.
  • the shotkey metal film 41 is, for example, Ni, Al, Pd, or the like.
  • the insulating film 42 which is an insulating layer, is formed (step ST48).
  • the insulating film 42 is arranged so as to cover the peripheral portion of the surface 33a of the exposed GaN layer 33 and the GaN layer 35 arranged on the peripheral portion of the surface 33a of the GaN layer 33.
  • step ST48 the insulating film 42 is arranged except for the intermediate portion of the surface 33a of the GaN layer 33.
  • the insulating film 42 is arranged outside the Schottky metal film 41. As a result, the pn junction is not connected to the anode.
  • the top electrode metal film 43 is formed on the Schottky metal film 41 and the insulating film 42 (step ST49).
  • the top electrode metal film 43 is arranged so as to cover the GaN layer 35 covered with the Schottky metal film 41. Further, the top electrode metal film 43 forms a so-called field plate on the insulating film 42.
  • the top electrode metal film 43 is arranged on the outer GaN layer 35 covered with the insulating film 42 and the inner GaN layer 35 covered with the Schottky metal film 41, respectively.
  • the FLR structure is formed by covering the outer GaN layer 35 with the insulating film 42 and the top electrode metal film 43.
  • the top electrode metal films 43 are separated from each other and are not in contact with each other.
  • the electric field applied to the end of the electrode can be relaxed, making it a device with high withstand voltage.
  • the field plate may be separated from the top electrode.
  • the GaN layer 35 of the semiconductor layer 31 in contact with the first mask 21 can be removed by dry etching to form the JBS structure and the FLR structure.
  • the semiconductor element 1 having an increased withstand voltage can be manufactured.
  • the shape of the step 24 may have an inclination or may have rounded corners.
  • the shape may have two or more steps. Further, the step is not limited to a step that rises upward from the opening 21s toward the outside in the radial direction, and a step that descends downward can also be implemented. Therefore, a convex shape can be formed by forming a shape that once goes up and goes down. A trench structure can also be formed by transferring the convex shapes of the first mask 21 and the second mask 23. Therefore, the mesa structure may be a trench structure. Further, one or a plurality of trench structures and a mesa structure at the outermost edge can be formed from the center of the semiconductor element 1 toward the outside in the radial direction.

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Abstract

This method for producing a semiconductor element comprises: a step for providing, on the surface (11a) of a substrate (11), a first mask (21), a part of which is open; a step for forming a second mask (23) to cover a part of the first mask (21); and a step for epitaxially growing a GaN layer (32) from the surface (11a) of the substrate (11), which is exposed by the opening, so that the GaN layer (32) covers the first mask (21) while the second mask (23) is exposed. The first mask (21) contains an element that serves as a donor for the GaN layer (32), and the second mask (23) does not contain an element that serves as a donor for the GaN layer (32).

Description

半導体素子の製造方法、半導体素子及び半導体装置Manufacturing method of semiconductor element, semiconductor element and semiconductor device
　本開示は、半導体素子の製造方法、半導体素子及び半導体装置に関する。 The present disclosure relates to a method for manufacturing a semiconductor device, a semiconductor device, and a semiconductor device.
　特許文献１には、ＧａＮ系半導体をＳｉＯ２からなるマスクを用いて、ＥＬＯ（Ｅｐｉｔａｘｉａｌ　Ｌａｔｅｒａｌ　ＯｖｅｒＧｒｏｗｔｈ）法で作製するＧａＮ系ＳＢＤ（Ｓｃｈｏｔｔｋｙ　Ｂａｒｒｉｅｒ　Ｄｉｏｄｅ）が記載されている。 Patent Document 1 describes a GaN-based SBD (Schottky Barrier Diode) in which a GaN-based semiconductor is manufactured by an ELO (Epitaxial Lateral Overgrown) method using a mask made of SiO 2 .
特許第４６３８９５８号公報Japanese Patent No. 4638958
　１つの態様に係る半導体素子の製造方法は、基板の表面に、一部が開口している第１マスクを設ける工程と、前記第１マスクの一部を覆うように第２マスクを形成する工程と、前記開口から露出する前記基板の表面から、前記第１マスクを覆い、前記第２マスクを露出させるようにエピタキシャル成長させて、第１半導体層を成長する工程と、を含み、前記第１マスクは、前記第１半導体層におけるドナーとなる元素を含み、前記第２マスクは、前記第１半導体層におけるドナーとなる元素を含まない。 The method for manufacturing a semiconductor element according to one aspect is a step of providing a first mask having a part open on the surface of the substrate and a step of forming a second mask so as to cover a part of the first mask. The first mask includes a step of covering the first mask from the surface of the substrate exposed from the opening and epitaxially growing the second mask so as to expose the second mask to grow the first semiconductor layer. Includes a donor element in the first semiconductor layer, and the second mask does not contain a donor element in the first semiconductor layer.
　１つの態様に係る半導体素子は、上記の半導体素子の製造方法により製造される。 The semiconductor device according to one embodiment is manufactured by the above-mentioned method for manufacturing a semiconductor device.
　１つの態様に係る半導体装置は、上記の半導体素子の製造方法により製造された半導体素子を含む。 The semiconductor device according to one embodiment includes a semiconductor device manufactured by the above-mentioned method for manufacturing a semiconductor device.
図１は、実施形態に係る半導体素子の製造方法を説明するための断面模式図である。FIG. 1 is a schematic cross-sectional view for explaining a method for manufacturing a semiconductor device according to an embodiment. 図２は、実施形態に係る半導体素子の製造方法を説明するための工程図である。FIG. 2 is a process diagram for explaining a method for manufacturing a semiconductor device according to an embodiment. 図３は、実施形態に係る半導体素子の製造方法に含まれる成長マスク作成工程の一例を説明するための工程図である。FIG. 3 is a process diagram for explaining an example of a growth mask manufacturing process included in the method for manufacturing a semiconductor device according to an embodiment. 図４は、実施形態に係る半導体装置の製造方法を説明するための工程図である。FIG. 4 is a process diagram for explaining a method for manufacturing a semiconductor device according to an embodiment. 図５は、実施形態に係る半導体素子の製造方法及び半導体素子を説明するための断面模式図である。FIG. 5 is a schematic cross-sectional view for explaining a method for manufacturing a semiconductor element and the semiconductor element according to the embodiment. 図６は、複数の半導体素子を並列配置した構成を含む上面図である。FIG. 6 is a top view including a configuration in which a plurality of semiconductor elements are arranged in parallel. 図７は、実施形態の変形例１に係る半導体素子を説明するための断面模式図である。FIG. 7 is a schematic cross-sectional view for explaining the semiconductor device according to the first modification of the embodiment. 図８は、実施形態の変形例２に係る半導体素子を説明するための断面模式図である。FIG. 8 is a schematic cross-sectional view for explaining the semiconductor element according to the second modification of the embodiment. 図９は、実施形態の変形例２に係る半導体装置の製造方法を説明するための工程図である。FIG. 9 is a process diagram for explaining a method for manufacturing a semiconductor device according to the second modification of the embodiment.
　従来のＥＬＯ技術を用いた製造方法においては、マスク中のＳｉが結晶中に取り込まれる、オートドープが発生する可能性がある。Ｓｉは、ＧａＮ系半導体の中で、ｎ型ドープ材となるので、１０１６／ｃｍ３台以下の低いドープ濃度を実現することが困難である。 In the manufacturing method using the conventional ELO technique, there is a possibility that autodoping may occur in which Si in the mask is incorporated into the crystal. Since Si is an n-type doping material among GaN-based semiconductors, it is difficult to realize a low doping concentration of 10 16 / cm 3 units or less.
　低いドープ濃度を実現する方法として、ＥＬＯ法を実施して、マスク上でオートドープされるｎ＋型の層を会合させマスクの全面を覆った状態で、フラットな結晶を成長させることによって、Ｓｉがドープしないｎ－型の層を形成する方法がある。この方法では、ｎ＋型の層を会合させるために、製造に時間を要する。 As a method for achieving a low dope concentration, the ELO method is carried out to grow flat crystals in a state where n + -type layers that are auto-doped on the mask are associated and the entire surface of the mask is covered to obtain Si. There is a method of forming an n-type layer that is not doped. In this method, it takes time to manufacture in order to associate the n + type layers.
　以下に実施形態に係る半導体素子の製造方法、半導体素子及び半導体装置について説明する。半導体素子１は、インバータ及びコンバータのような電力変換器のスイッチング回路に使用されるパワー半導体である。 The method for manufacturing a semiconductor element, the semiconductor element, and the semiconductor device according to the embodiment will be described below. The semiconductor element 1 is a power semiconductor used in a switching circuit of a power converter such as an inverter and a converter.
［実施形態］
（製造方法）
　図１は、実施形態に係る半導体素子１の製造方法を説明するための断面模式図である。図２は、実施形態に係る半導体素子１の製造方法を説明するための工程図である。図１に示すように、半導体素子１は、製造工程において、ベース基板（基板）１１の表面１１ａに第１マスク２１が形成され、第１マスク２１の表面２１ａに第２マスク２３が形成され、第２マスク２３の表面２３ａに半導体層３１が形成される。本実施形態では、半導体層３１は、第１半導体層であるｎ＋ＧａＮ層３２と、第２半導体層であるｎ－ＧａＮ層３３と、第３半導体層であるｎ＋ＧａＮ層３４とを有する。 [Embodiment]
(Production method)
FIG. 1 is a schematic cross-sectional view for explaining a method of manufacturing the semiconductor element 1 according to the embodiment. FIG. 2 is a process diagram for explaining the manufacturing method of the semiconductor element 1 according to the embodiment. As shown in FIG. 1, in the semiconductor element 1, in the manufacturing process, the first mask 21 is formed on the surface 11a of the base substrate (board) 11, and the second mask 23 is formed on the surface 21a of the first mask 21. The semiconductor layer 31 is formed on the surface 23a of the second mask 23. In the present embodiment, the semiconductor layer 31 has an n + GaN layer 32 which is a first semiconductor layer, an n − GaN layer 33 which is a second semiconductor layer, and an n + GaN layer 34 which is a third semiconductor layer. ..
（成長マスク作成工程）
　まず、図１に示す基板１１表層のＧａＮ層の表面１１ａに例えばＳｉＯ２による第１マスク２１を形成する（ステップＳＴ１１）（第１工程）。より詳しくは、基板１１の表面１１ａに、一部が開口している第１マスク２１を設ける。言い換えると、基板１１の表面１１ａ上に少なくとも一部に開口部２１ｓを有する第１マスク２１を設ける。 (Growth mask making process)
First, a first mask 21 made of, for example, SiO 2 is formed on the surface 11a of the GaN layer on the surface of the substrate 11 shown in FIG. 1 (step ST11) (first step). More specifically, a first mask 21 having a part of opening is provided on the surface 11a of the substrate 11. In other words, a first mask 21 having an opening 21s at least in a part thereof is provided on the surface 11a of the substrate 11.
　基板１１表層のＧａＮ層の表面１１ａと反対側の裏面は、図示しないシリコン基板等のＧａＮ以外で支持されていてもよい。基板１１表層のＧａＮ層の裏面を支持する基板は、例えばサファイア基板又はＳｉＣ（Ｓｉｌｉｃｏｎ　Ｃａｒｂｉｄｅ）基板であってもよい。 The back surface of the surface layer of the substrate 11 opposite to the front surface 11a of the GaN layer may be supported by other than GaN such as a silicon substrate (not shown). The substrate that supports the back surface of the GaN layer on the surface of the substrate 11 may be, for example, a sapphire substrate or a SiC (Silicon Carbide) substrate.
　第１マスク２１は、半導体層３１におけるドナーとなる元素を含む。第１マスク２１の材料としてはＳｉＯ２の他にＳｉＮ、ＡｌＳｉＯ等を用いてもよい。第１マスク２１は、アモルファス状のものであってもよい。第１マスク２１は、少なくとも一部に開口部２１ｓを有する。 The first mask 21 contains an element that becomes a donor in the semiconductor layer 31. As the material of the first mask 21, SiN, AlSiO, or the like may be used in addition to SiO 2 . The first mask 21 may be amorphous. The first mask 21 has an opening 21s at least in part.
　第１マスク２１の厚さｄ１は、ＧａＮ層３２の厚さｄ２より薄い。第１マスク２１の厚さｄ１と第２マスク２３の厚さｄ３との合計は、ＧａＮ層３２の厚さｄ２より厚くても薄くてもよい。第１マスク２１の厚さｄ１と第２マスク２３の厚さｄ３との合計は、ＧａＮ層３２の厚さｄ２とＧａＮ層３３の厚さｄ４との合計より薄い。本実施形態では、第１マスク２１の厚さｄ１と第２マスク２３の厚さｄ３との合計は、ＧａＮ層３２の厚さｄ２より厚い。第１マスク２１の表面２１ａは、ＧａＮ層３２の表面３２ｂより基板１１に近い。本実施形態では、第２マスク２３の表面２３ａは、ＧａＮ層３２の表面３２ｂより基板１１の表面１１ａから離れている。第１マスク２１と第２マスク２３とによって、段差２４が形成される。段差２４は、開口部２１ｓ及び開口部２３ｓに面して形成される。 The thickness d1 of the first mask 21 is thinner than the thickness d2 of the GaN layer 32. The sum of the thickness d1 of the first mask 21 and the thickness d3 of the second mask 23 may be thicker or thinner than the thickness d2 of the GaN layer 32. The sum of the thickness d1 of the first mask 21 and the thickness d3 of the second mask 23 is thinner than the sum of the thickness d2 of the GaN layer 32 and the thickness d4 of the GaN layer 33. In the present embodiment, the sum of the thickness d1 of the first mask 21 and the thickness d3 of the second mask 23 is thicker than the thickness d2 of the GaN layer 32. The surface 21a of the first mask 21 is closer to the substrate 11 than the surface 32b of the GaN layer 32. In the present embodiment, the surface 23a of the second mask 23 is separated from the surface 11a of the substrate 11 from the surface 32b of the GaN layer 32. The step 24 is formed by the first mask 21 and the second mask 23. The step 24 is formed so as to face the opening 21s and the opening 23s.
　第１マスク２１の表面２１ａに例えばＡｌＯｘによる第２マスク２３を形成する（ステップＳＴ１２）（第２工程）。より詳しくは、第１マスク２１の一部を覆うように第２マスク２３を形成する。言い換えると、第１マスク２１の表面２１ａ上の少なくとも一部を覆うように第２マスク２３を設ける。 A second mask 23 made of, for example, AlOx is formed on the surface 21a of the first mask 21 (step ST12) (second step). More specifically, the second mask 23 is formed so as to cover a part of the first mask 21. In other words, the second mask 23 is provided so as to cover at least a part of the surface 21a of the first mask 21.
　第２マスク２３は、半導体層３１におけるドナーとなる元素を含まない。第２マスク２３の材料としてはＡｌＯｘの他にＡｌＯＮ、Ｗ、ＧａＯ等のＳｉを含まない材料を用いてもよい。第２マスク２３は、第１マスク２１の表面２１ａ上の少なくとも一部を覆う。第２マスク２３は、複数の半導体素子１を個片に分離する位置（以下、「分離位置」という）Ｐを含んで配置されている。言い換えると、第２マスク２３は、隣り合う半導体素子１の間を含む位置に配置されている。 The second mask 23 does not contain an element that becomes a donor in the semiconductor layer 31. As the material of the second mask 23, a material containing no Si such as AlON, W, and GaO may be used in addition to AlOx. The second mask 23 covers at least a part of the surface 21a of the first mask 21. The second mask 23 is arranged to include a position (hereinafter, referred to as “separation position”) P for separating the plurality of semiconductor elements 1 into individual pieces. In other words, the second mask 23 is arranged at a position including between the adjacent semiconductor elements 1.
　第２マスク２３の積層方向と直交する横方向の幅ｗは、例えば２０μｍ以上１００μｍ以下であってもよい。幅ｗが２０μｍより小さい場合、後述するステップＳＴ４６においてドライエッチングが適切に実施できないおそれがある。幅ｗが１００μｍより大きい場合、後述するステップＳＴ１３においてＥＬＯ法を実施する際に、第２マスク２３上にデブリが発生する。 The width w in the lateral direction orthogonal to the stacking direction of the second mask 23 may be, for example, 20 μm or more and 100 μm or less. If the width w is smaller than 20 μm, dry etching may not be properly performed in step ST46 described later. When the width w is larger than 100 μm, debris is generated on the second mask 23 when the ELO method is carried out in step ST13 described later.
　メサ構造又はトレンチ構造を有する半導体素子１を製造する場合、第２マスク２３の積層方向の厚さｄ３は、第２マスク２３の表面２３ａがＧａＮ層３３の表面３３ａより基板１１の表面１１ａから離れるような厚さを有してもよい。言い換えると、第１マスク２１の厚さｄ１と第２マスク２３の厚さｄ３との合計は、ＧａＮ層３２の厚さｄ２より厚くてもよい。第２マスク２３の積層方向の厚さｄ３は、例えば、３μｍ以上であってもよい。第１マスク２１の厚さｄ１と第２マスク２３の厚さｄ３との合計が、ＧａＮ層３２の厚さｄ２より厚い場合、ステップＳＴ１３においてＥＬＯ法を実行することにより、半導体層３１の周縁部に段差が転写される。 When manufacturing a semiconductor element 1 having a mesa structure or a trench structure, the thickness d3 of the second mask 23 in the stacking direction is such that the surface 23a of the second mask 23 is separated from the surface 11a of the substrate 11 from the surface 33a of the GaN layer 33. It may have such a thickness. In other words, the sum of the thickness d1 of the first mask 21 and the thickness d3 of the second mask 23 may be thicker than the thickness d2 of the GaN layer 32. The thickness d3 of the second mask 23 in the stacking direction may be, for example, 3 μm or more. When the sum of the thickness d1 of the first mask 21 and the thickness d3 of the second mask 23 is thicker than the thickness d2 of the GaN layer 32, the peripheral portion of the semiconductor layer 31 is executed by executing the ELO method in step ST13. The step is transferred to.
　メサ構造又はトレンチ構造を有さない半導体素子１を製造する場合、第２マスク２３の積層方向の厚さｄ３は、第２マスク２３の表面２３ａがＧａＮ層３２の表面３２ｂと基板１１の表面１１ａから同程度となる厚さでよい。言い換えると、第１マスク２１の厚さｄ１と第２マスク２３の厚さｄ３との合計は、ＧａＮ層３２の厚さｄ２と同程度の厚さでよい。メサ構造又はトレンチ構造を有さない半導体素子１を製造する場合、第２マスク２３の積層方向の厚さｄ３は、メサ構造又はトレンチ構造を有する半導体素子１を製造する場合に比べて薄くてよい。第２マスク２３の積層方向の厚さｄ３は、例えば、１μｍ以下であってもよい。 When the semiconductor element 1 having no mesa structure or trench structure is manufactured, the thickness d3 in the stacking direction of the second mask 23 is such that the surface 23a of the second mask 23 is the surface 32b of the GaN layer 32 and the surface 11a of the substrate 11. The thickness may be about the same. In other words, the sum of the thickness d1 of the first mask 21 and the thickness d3 of the second mask 23 may be as thick as the thickness d2 of the GaN layer 32. When the semiconductor element 1 having no mesa structure or trench structure is manufactured, the thickness d3 in the stacking direction of the second mask 23 may be thinner than when the semiconductor element 1 having the mesa structure or trench structure is manufactured. .. The thickness d3 of the second mask 23 in the stacking direction may be, for example, 1 μm or less.
（成長マスク作成工程の一例）
　図３は、実施形態に係る半導体素子１の製造方法に含まれる成長マスク作成工程の一例を説明するための工程図である。図３を用いて、第１工程と第２工程とを含む成長マスク作成工程の一例について詳しく説明する。ステップＳＴ２１ないしステップＳＴ２８の工程が、ステップＳＴ１１及びステップＳＴ１２に対応する。 (Example of growth mask making process)
FIG. 3 is a process diagram for explaining an example of a growth mask making process included in the manufacturing method of the semiconductor element 1 according to the embodiment. An example of a growth mask making step including the first step and the second step will be described in detail with reference to FIG. The process of step ST21 to step ST28 corresponds to step ST11 and step ST12.
　基板１１表層のＧａＮ層の表面１１ａにＳｉＯ２による第１マスク２１を形成する（ステップＳＴ２１）。より詳しくは、基板１１の表面１１ａ上の全面を覆うように第１マスク２１を設ける。 A first mask 21 made of SiO 2 is formed on the surface 11a of the GaN layer on the surface of the substrate 11 (step ST21). More specifically, the first mask 21 is provided so as to cover the entire surface of the substrate 11 on the surface 11a.
　第２マスク２３を第１マスク２１の表面２１ａ上に形成する（ステップＳＴ２２）。より詳しくは、第１マスク２１の表面２１ａ上の全面を覆うように第２マスク２３を設ける。 The second mask 23 is formed on the surface 21a of the first mask 21 (step ST22). More specifically, the second mask 23 is provided so as to cover the entire surface of the first mask 21 on the surface 21a.
　第２マスク２３の表面２３ａにレジストマスク２２を形成する（ステップＳＴ２３）。より詳しくは、第２マスク２３の表面２３ａ上の一部を覆うようにレジストマスク２２を設ける。レジストマスク２２は、第２マスク２３の表面２３ａ上において、ステップＳ２４において第２マスク２３をウエットエッチングしない部分、言い換えると、ステップＳ２８の実行後に第２マスク２３が配置される部分を覆うようにフォトリソグラフィを用いてパターン配置される。第２マスク２３の表面２３ａ上には、複数のレジストマスク２２が間隔を空けて配置される。レジストマスク２２の厚さｄ５は、第２マスク２３の厚さｄ３より厚い。 A resist mask 22 is formed on the surface 23a of the second mask 23 (step ST23). More specifically, the resist mask 22 is provided so as to cover a part of the surface 23a of the second mask 23. The resist mask 22 is a photo on the surface 23a of the second mask 23 so as to cover the portion where the second mask 23 is not wet-etched in step S24, in other words, the portion where the second mask 23 is arranged after the execution of step S28. The pattern is arranged using lithography. A plurality of resist masks 22 are arranged at intervals on the surface 23a of the second mask 23. The thickness d5 of the resist mask 22 is thicker than the thickness d3 of the second mask 23.
　第２マスク２３をウエットエッチングする（ステップＳＴ２４）。より詳しくは、第１マスク２１が露出するまで、第２マスク２３の一部をウエットエッチングする。このとき、レジストマスク２２があるため、レジストマスク２２の下部に位置する第２マスク２３は、ウエットエッチングされない。これによって、第１マスク２１の側面２１ｄ、第２マスク２３の側面２３ｄが生じる。第１マスク２１の側面２１ｄが形成されることにより、表面２１ａより一段低い表面２１ａ´が形成される。 Wet etching the second mask 23 (step ST24). More specifically, a part of the second mask 23 is wet-etched until the first mask 21 is exposed. At this time, since the resist mask 22 is present, the second mask 23 located below the resist mask 22 is not wet-etched. As a result, the side surface 21d of the first mask 21 and the side surface 23d of the second mask 23 are generated. By forming the side surface 21d of the first mask 21, the surface 21a'which is one step lower than the surface 21a is formed.
　レジストマスク２２をエッチングする（ステップＳＴ２５）。より詳しくは、第２マスク２３の表面２３ａ上に位置するレジストマスク２２をエッチングする。これによって、第２マスク２３の表面２３ａは露出する。 Etching the resist mask 22 (step ST25). More specifically, the resist mask 22 located on the surface 23a of the second mask 23 is etched. As a result, the surface 23a of the second mask 23 is exposed.
　第１マスク２１の表面２１ａと第２マスク２３の表面２３ａに開口部２５ｓを持つレジストパターン２５を形成する（ステップＳＴ２６）。より詳しくは、第１マスク２１の表面２１ａ′と側面２１ｄ、第２マスク２３の表面２３ａと側面２３ｄを覆うようにレジストパターン２５を形成する。このとき、レジストパターン２５の上面２５ａはほぼ平坦となる。 A resist pattern 25 having an opening 25s is formed on the surface 21a of the first mask 21 and the surface 23a of the second mask 23 (step ST26). More specifically, the resist pattern 25 is formed so as to cover the surface 21a'and the side surface 21d of the first mask 21 and the surface 23a and the side surface 23d of the second mask 23. At this time, the upper surface 25a of the resist pattern 25 becomes substantially flat.
　第１マスク２１をウエットエッチングする（ステップＳＴ２７）。より詳しくは、基板１１が露出するまで、レジストパターン２５の開口部２５ｓにおいて露出する第１マスク２１をウエットエッチングする。 Wet etching the first mask 21 (step ST27). More specifically, the first mask 21 exposed in the opening 25s of the resist pattern 25 is wet-etched until the substrate 11 is exposed.
　レジストパターン２５をウエットエッチングする（ステップＳＴ２８）。より詳しくは、第１マスク２１、第２マスク２３上に位置するレジストパターン２５をウエットエッチングする。これにより、第１マスク２１、第２マスク２３上のレジストパターン２５は除去され、第１マスクの表面２１ａ´の一部と第２マスク２３の表面２３ａが露出する。 Wet etching the resist pattern 25 (step ST28). More specifically, the resist pattern 25 located on the first mask 21 and the second mask 23 is wet-etched. As a result, the resist pattern 25 on the first mask 21 and the second mask 23 is removed, and a part of the surface 21a'of the first mask and the surface 23a of the second mask 23 are exposed.
　ステップＳＴ２２を行った後、第１マスク２１の厚さｄ１は第２マスク２３の厚さｄ３より厚くなるほうがよい。 After performing step ST22, the thickness d1 of the first mask 21 should be thicker than the thickness d3 of the second mask 23.
　ステップＳＴ２４を行っている間に、第１マスク２１がウエットエッチングされて、ステップＳＴ２３に比べて厚さｄ１が薄くなる。 While performing step ST24, the first mask 21 is wet-etched, and the thickness d1 becomes thinner than that of step ST23.
　このようにして、成長マスクが形成されて、分離位置Ｐにおいては、第１マスク２１上に形成された第２マスク２３が露出する。第１マスク２１の開口部２１ｓから、開口部２１ｓに対応する部分の基板１１の表面１１ａが露出する。なお、基板１１の両端に位置する表面１１ａが第１マスク２１に覆われていてもよい。また、基板１１の側面又は裏面の全体が第１マスク２１に覆われていてもよい。後述する気相成長法において用いる原料ガスに接触しうる面のうち、開口部２１ｓを除く全体が、第１マスク２１に覆われていてもよい。 In this way, the growth mask is formed, and at the separation position P, the second mask 23 formed on the first mask 21 is exposed. The surface 11a of the substrate 11 in the portion corresponding to the opening 21s is exposed from the opening 21s of the first mask 21. The surfaces 11a located at both ends of the substrate 11 may be covered with the first mask 21. Further, the entire side surface or the back surface of the substrate 11 may be covered with the first mask 21. Of the surfaces that can come into contact with the raw material gas used in the vapor phase growth method described later, the entire surface excluding the opening 21s may be covered with the first mask 21.
（半導体層成長工程）
　次に、図２に戻って、上述したＥＬＯ技術を用いて開口部２１ｓから露出する基板１１の表面１１ａから半導体層３１としてのＧａＮ層を形成する（ステップＳＴ１３）（第３工程）。より詳しくは、図１に示すように、開口部２１ｓから露出する表面１１ａから第１マスク２１を覆い、第２マスク２３を露出させるように半導体をエピタキシャル成長させ、半導体層３１を有する半導体素子１を作製する（第３工程）。 (Semiconductor layer growth process)
Next, returning to FIG. 2, the GaN layer as the semiconductor layer 31 is formed from the surface 11a of the substrate 11 exposed from the opening 21s by using the above-mentioned ELO technique (step ST13) (third step). More specifically, as shown in FIG. 1, the semiconductor element 1 having the semiconductor layer 31 is formed by covering the first mask 21 from the surface 11a exposed from the opening 21s, and epitaxially growing the semiconductor so as to expose the second mask 23. Produce (third step).
　具体的には、まず、図１に示すように、開口部２１ｓから露出する基板１１の表面１１ａから、第１マスク２１を覆い、第２マスク２３を露出させるようにエピタキシャル成長させて、第１半導体層であるＧａＮ層３２を成長する。より詳しくは、ＥＬＯ技術を用いて、図示しないエピタキシャル装置において、開口部２１ｓから露出する基板１１の表面１１ａから第１マスク２１を覆い、第２マスク２３を露出させるように、高不純物濃度のｎ＋型のＧａＮ層３２をエピタキシャル成長させる。本実施形態では、半導体層３１のＧａＮ層３２の面３２ａには、段差２４の形状が転写される。ＧａＮ層３２は、開口部２１ｓから露出する表面１１ａから、まず縦方向に成長し、その後、段差２４を埋めるように横方向に成長させる。これによりＧａＮ層３２の表面３２ｂは、ほぼ平坦となる。ＧａＮ層３２は、結晶成長時、第１マスク２１を構成する材料から、不純物がオートドープされる。不純物がＳｉ（Ｓｉｌｉｃｏｎ）であるとき、ＧａＮ層３２は、高濃度にドーピングされたｎ＋半導体層である。ＧａＮ層３２は、１０１８ｃｍ－３以上の電子キャリア濃度となるよう、ｎ型不純物のドープ量がコントロールされる。ＧａＮ層３２は、会合する前にエピタキシャル成長を停止させる。 Specifically, first, as shown in FIG. 1, from the surface 11a of the substrate 11 exposed from the opening 21s, the first mask 21 is covered and epitaxially grown so as to expose the second mask 23, and the first semiconductor is formed. The GaN layer 32, which is a layer, is grown. More specifically, using ELO technology, in an epitaxial device (not shown), a high impurity concentration n + is used to cover the first mask 21 from the surface 11a of the substrate 11 exposed from the opening 21s and expose the second mask 23. The type GaN layer 32 is epitaxially grown. In the present embodiment, the shape of the step 24 is transferred to the surface 32a of the GaN layer 32 of the semiconductor layer 31. The GaN layer 32 first grows in the vertical direction from the surface 11a exposed from the opening 21s, and then grows in the horizontal direction so as to fill the step 24. As a result, the surface 32b of the GaN layer 32 becomes substantially flat. During crystal growth, the GaN layer 32 is auto-doped with impurities from the material constituting the first mask 21. When the impurity is Si (Silicon), the GaN layer 32 is a highly concentrated n + semiconductor layer. In the GaN layer 32, the doping amount of n-type impurities is controlled so that the electron carrier concentration is 10 18 cm -3 or more. The GaN layer 32 stops epitaxial growth before associating.
　ＧａＮ層３２が形成されると、基板１１上に設けられた第１マスク２１は、ＧａＮ層３２及び第２マスク２３で全面が覆われる。これにより、ＥＬＯ成長時に、第１マスク２１からのオートドープが低減される。 When the GaN layer 32 is formed, the entire surface of the first mask 21 provided on the substrate 11 is covered with the GaN layer 32 and the second mask 23. This reduces autodoping from the first mask 21 during ELO growth.
　第１半導体層であるＧａＮ層３２を成長する工程の後に、第２半導体層であるＧａＮ層３３を成長する。より詳しくは、さらに所望の不純物濃度プロファイルを得るため、ＧａＮ層３２を覆うように低不純物濃度のＧａＮ層３３をエピタキシャル成長させる。ＧａＮ層３３は、ＧａＮ層３２の表面３２ｂから、まず縦方向に成長し、その後、段差２４を埋めるように横方向に成長させる。これによりＧａＮ層３３の表面３３ｂも、ほぼ平坦となる。ＧａＮ層３３は、会合する前にエピタキシャル成長を停止させる。ＧａＮ層３３は、ｎ－半導体層である。ＧａＮ層３３は、１０１７ｃｍ－３未満の電子キャリア濃度となるよう、ｎ型不純物のドープ量が、コントロールされる。ＧａＮ層３３は、エピタキシャル成長時に、第１マスク２１と接していないので、オートドープが低減される。また第１マスク２１が、ＧａＮ層３２及び第２マスク２３で覆われているので、ＧａＮ層３３のオートドープが低減される。 After the step of growing the GaN layer 32 which is the first semiconductor layer, the GaN layer 33 which is the second semiconductor layer is grown. More specifically, in order to obtain a desired impurity concentration profile, the low impurity concentration GaN layer 33 is epitaxially grown so as to cover the GaN layer 32. The GaN layer 33 first grows in the vertical direction from the surface 32b of the GaN layer 32, and then grows in the horizontal direction so as to fill the step 24. As a result, the surface 33b of the GaN layer 33 is also substantially flat. The GaN layer 33 stops epitaxial growth before associating. The GaN layer 33 is an n-semiconductor layer. The doping amount of the n-type impurity is controlled in the GaN layer 33 so that the electron carrier concentration is less than 10 17 cm -3 . Since the GaN layer 33 is not in contact with the first mask 21 during epitaxial growth, autodoping is reduced. Further, since the first mask 21 is covered with the GaN layer 32 and the second mask 23, the autodoping of the GaN layer 33 is reduced.
　さらにＧａＮ層３３を覆うように、高不純物濃度のＧａＮ層３４をエピタキシャル成長させる。ＧａＮ層３４は、ＧａＮ層３３の表面３３ｂから、まず縦方向に成長し、その後、横方向に成長させる。これによりＧａＮ層３４の上面３４ａも、ほぼ平坦となる。ＧａＮ層３４は、会合する前にエピタキシャル成長を停止させる。ＧａＮ層３４は、ｎ＋半導体層である。ＧａＮ層３４は、１０１９ｃｍ－３以上の電子キャリア濃度となるよう、ｎ型不純物のドープ量が、コントロールされる。この高濃度の層は、電気抵抗が低く、その後の工程で付ける電極金属との接合部の電気抵抗を低くできる。 Further, the GaN layer 34 having a high impurity concentration is epitaxially grown so as to cover the GaN layer 33. The GaN layer 34 first grows in the vertical direction from the surface 33b of the GaN layer 33, and then grows in the horizontal direction. As a result, the upper surface 34a of the GaN layer 34 is also substantially flat. The GaN layer 34 stops epitaxial growth before associating. The GaN layer 34 is an n + semiconductor layer. In the GaN layer 34, the doping amount of n-type impurities is controlled so that the electron carrier concentration is 10 19 cm -3 or more. This high-concentration layer has low electrical resistance, and the electrical resistance of the joint with the electrode metal attached in the subsequent step can be lowered.
　以上のようにして、図５に示すように、段差２４の形状が転写された半導体層３１のＧａＮ層３２及びＧａＮ層３３を有する半導体素子１を作製する。半導体層３１は、基板１１の上に作成され、表面から、ｎ＋型半導体層であるＧａＮ層３２、ｎ－型半導体層であるＧａＮ層３３、及びｎ＋型半導体層であるＧａＮ層３４を積層方向にエピタキシャル成長される。 As described above, as shown in FIG. 5, the semiconductor element 1 having the GaN layer 32 and the GaN layer 33 of the semiconductor layer 31 to which the shape of the step 24 is transferred is manufactured. The semiconductor layer 31 is formed on the substrate 11, and the GaN layer 32 which is an n + type semiconductor layer, the GaN layer 33 which is an n− type semiconductor layer, and the GaN layer 34 which is an n + type semiconductor layer are laminated from the surface. Epitaxially grown to.
　半導体層３１が形成されると、半導体層３１が会合していないので、第２マスク２３は、分離位置Ｐにおいて露出している。 When the semiconductor layer 31 is formed, the semiconductor layers 31 are not associated with each other, so that the second mask 23 is exposed at the separation position P.
　つづいて、図４、図５を参照して、半導体素子１を含む半導体装置２の製造方法を説明する。図４は、実施形態に係る半導体装置２の製造方法を説明するための工程図である。図５は、実施形態に係る半導体素子１の製造方法及び半導体素子１を説明するための断面模式図である。ステップＳＴ４１ないしステップＳＴ４６は、ステップＳＴ１１ないしステップＳＴ１３を行った後に行われる。 Subsequently, a method of manufacturing the semiconductor device 2 including the semiconductor element 1 will be described with reference to FIGS. 4 and 5. FIG. 4 is a process diagram for explaining the manufacturing method of the semiconductor device 2 according to the embodiment. FIG. 5 is a schematic cross-sectional view for explaining the manufacturing method of the semiconductor element 1 and the semiconductor element 1 according to the embodiment. Steps ST41 to ST46 are performed after performing steps ST11 to ST13.
　支持基板５１に、半導体素子１の半導体層３１を貼り付ける（ステップＳＴ４１）。より詳しくは、基板１１に対する反対側の半導体層３１の裏面３１ｂであるＧａＮ層３４の上面３４ａを支持基板５１に接合する。接合は、金属を介した接合や、直接接合を用い接続の電気抵抗を低減してもよい。 The semiconductor layer 31 of the semiconductor element 1 is attached to the support substrate 51 (step ST41). More specifically, the upper surface 34a of the GaN layer 34, which is the back surface 31b of the semiconductor layer 31 on the opposite side to the substrate 11, is bonded to the support substrate 51. As the bonding, the electrical resistance of the connection may be reduced by using a metal-based bonding or a direct bonding.
　支持基板５１に裏面電極６１を形成する（ステップＳＴ４２）。より詳しくは、支持基板５１の上面に裏面電極６１を例えばスパッタ等で形成する。裏面電極６１は、例えば、Ａｌ層にＴｉ、Ｎｉ、Ａｕめっきを施したものである。なお、裏面電極６１の形成は、後述する上面電極金属膜４３が形成された後に形成されてもよい。温度を上げる工程が含まれる場合等に、ステップＳＴ４２を最後に行うことで、裏面電極６１への影響を避けることができる。 The back surface electrode 61 is formed on the support substrate 51 (step ST42). More specifically, the back surface electrode 61 is formed on the upper surface of the support substrate 51 by, for example, sputtering. The back surface electrode 61 is, for example, an Al layer plated with Ti, Ni, or Au. The back surface electrode 61 may be formed after the top surface electrode metal film 43, which will be described later, is formed. When the step of raising the temperature is included, the influence on the back surface electrode 61 can be avoided by performing step ST42 at the end.
　又は、予め裏面電極６１が配置された支持基板５１を用いてもよい。支持基板５１は、低電気抵抗となるよう、高不純物濃度の半導体であってもよい。 Alternatively, a support substrate 51 on which the back surface electrode 61 is arranged in advance may be used. The support substrate 51 may be a semiconductor having a high impurity concentration so as to have low electrical resistance.
　ウエットエッチングによってマスクを除去する（ステップＳＴ４３）。より詳しくは、分離位置Ｐにおいて露出している第２マスク２３及び第１マスク２１をウエットエッチングで溶解させる。 Remove the mask by wet etching (step ST43). More specifically, the second mask 23 and the first mask 21 exposed at the separation position P are melted by wet etching.
　半導体層３１の裏面３１ｂであるＧａＮ層３４の上面３４ａを支持基板５１に接合した状態で半導体層３１を基板１１から剥離する（ステップＳＴ４４）。より詳しくは、超音波等で開口部２１ｓの近傍の結晶に亀裂を入れることで、基板１１から半導体層３１を剥離する。 The semiconductor layer 31 is peeled off from the substrate 11 in a state where the upper surface 34a of the GaN layer 34, which is the back surface 31b of the semiconductor layer 31, is bonded to the support substrate 51 (step ST44). More specifically, the semiconductor layer 31 is peeled from the substrate 11 by cracking the crystal in the vicinity of the opening 21s with ultrasonic waves or the like.
　剥離した後、半導体素子１と上下反転させる（ステップＳＴ４５）。 After peeling, it is turned upside down with the semiconductor element 1 (step ST45).
　ドライエッチングをする（ステップＳＴ４６）。より詳しくは、ＧａＮ層３２をドライエッチングで溶解させる。本実施形態では、ドライエッチングされた半導体素子１は、メサ構造を有する。 Perform dry etching (step ST46). More specifically, the GaN layer 32 is melted by dry etching. In the present embodiment, the dry-etched semiconductor element 1 has a mesa structure.
　図１、図５等では、説明のため、全ての段差を大きく描いた。図５に示す面３２ａと面３２ｃの段差は０．５μｍ以下であってもよく、０．１μｍ程度であってもよい。図５に示す面３２ｂと面３２ｃの段差は、０．５μｍ以上１０μｍ以下程度であってもよい。 In Fig. 1, Fig. 5, etc., all the steps are drawn large for the sake of explanation. The step between the surfaces 32a and the surface 32c shown in FIG. 5 may be 0.5 μm or less, or may be about 0.1 μm. The level difference between the surface 32b and the surface 32c shown in FIG. 5 may be about 0.5 μm or more and 10 μm or less.
　ステップＳＴ４６において、第１マスク２１及び第２マスク２３に接した、半導体層３１のＧａＮ層３２の面３２ａをドライエッチングして、段差２４を転写する。これにより、ＧａＮ層３２の段差が転写されて、ＧａＮ層３３の面３３ａに対し、周囲に一段下がった段差３３ｃ及び、段差３３ｃから一段下がった段差３３ｄが形成されている。ＧａＮ層３３は、段差を転写することによってメサ構造又はトレンチ構造が形成される。本実施形態では、一例として段差３３ｃをメサ構造として利用する場合を図示する。 In step ST46, the surface 32a of the GaN layer 32 of the semiconductor layer 31 in contact with the first mask 21 and the second mask 23 is dry-etched to transfer the step 24. As a result, the step of the GaN layer 32 is transferred to form a step 33c that is one step lower than the surface 33a of the GaN layer 33 and a step 33d that is one step lower than the step 33c. A mesa structure or a trench structure is formed in the GaN layer 33 by transferring the step. In this embodiment, a case where the step 33c is used as a mesa structure is illustrated as an example.
　また、ステップＳＴ４６において、ＧａＮ層３２の面３２ａをドライエッチングする代わりに、ＧａＮ層３２の面３２ａを研磨して、段差２４を転写してもよい。研磨することで、半導体層３１へのダメージを低減できる。 Further, in step ST46, instead of dry etching the surface 32a of the GaN layer 32, the surface 32a of the GaN layer 32 may be polished to transfer the step 24. By polishing, damage to the semiconductor layer 31 can be reduced.
　メサ段差を形成することにより、電極端部に加わる電界を緩和できるため、耐圧の高い素子を作製できる。 By forming a mesa step, the electric field applied to the end of the electrode can be relaxed, so an element with high withstand voltage can be manufactured.
　以上により半導体素子１が製造される。半導体素子１は例えばショットキー接合を有するＳＢＤとして使用可能である。 From the above, the semiconductor element 1 is manufactured. The semiconductor device 1 can be used, for example, as an SBD having a Schottky junction.
　以上説明した製造プロセスを、図１に示すように複数の半導体素子１を同時に製造するように同時並行して実施する。すなわち、第１マスク２１に複数の開口部２１ｓを形成する。一の開口部２１ｓに対し一の半導体素子１を対応させることによって、複数の半導体素子１を同時に作製する。図１では、作製する複数の半導体素子１が並列に配置される構成となっている。 The manufacturing process described above is carried out simultaneously and in parallel so as to simultaneously manufacture a plurality of semiconductor elements 1 as shown in FIG. That is, a plurality of openings 21s are formed in the first mask 21. By associating one semiconductor element 1 with one opening 21s, a plurality of semiconductor elements 1 are simultaneously manufactured. In FIG. 1, a plurality of semiconductor elements 1 to be manufactured are arranged in parallel.
　各半導体素子１は、分離位置Ｐにおいて個片に分離して半導体装置２としてもよい。大容量化が必要な場合には、一例として、図１に示すように複数の半導体素子１で支持基板５１及び裏面電極６１を共有したまま、図６に示すように実装して半導体装置２として利用してもよい。図６は、複数の半導体素子１を並列配置した構成を含む上面図である。具体的には、図６に示すように、共通の裏面電極６１を実装基板２００上の一の電極パッド２０１にダイボンディングし、個々の上面電極金属膜をボンディングワイヤ５２により他の電極パッド２０２に接続する。このように実装基板２００を実装することで、複数のダイオードを並列接続して大容量化し利用することができる。このとき、複数の半導体素子１を一定方向に並べて配置するように製造する。半導体素子１は、平面視で、半導体素子１が並ぶ方向に対する略直交方向に長尺な形状とする。半導体素子１をこのような形状と並びとすることで、ダイオードの接合面積を大きくできる。このように製造された半導体素子１は、用途に合わせて様々な半導体装置２として利用可能である。 Each semiconductor element 1 may be separated into individual pieces at the separation position P to form the semiconductor device 2. When it is necessary to increase the capacity, as an example, as shown in FIG. 1, a plurality of semiconductor elements 1 share the support substrate 51 and the back surface electrode 61, and the semiconductor device 2 is mounted as shown in FIG. You may use it. FIG. 6 is a top view including a configuration in which a plurality of semiconductor elements 1 are arranged in parallel. Specifically, as shown in FIG. 6, a common back surface electrode 61 is die-bonded to one electrode pad 201 on the mounting substrate 200, and each top surface electrode metal film is bonded to another electrode pad 202 by a bonding wire 52. Connecting. By mounting the mounting board 200 in this way, a plurality of diodes can be connected in parallel to increase the capacity and use them. At this time, the plurality of semiconductor elements 1 are manufactured so as to be arranged side by side in a certain direction. The semiconductor element 1 has a long shape in a direction substantially orthogonal to the direction in which the semiconductor elements 1 are arranged in a plan view. By arranging the semiconductor elements 1 in line with such a shape, the junction area of the diode can be increased. The semiconductor element 1 manufactured in this way can be used as various semiconductor devices 2 according to the application.
（効果）
　以上により、本実施形態では、半導体層３１におけるドナー又はアクセプタとなる元素を含む第１マスク２１の少なくとも一部に重ねて、半導体層３１におけるドナー又はアクセプタとなる元素を含まない第２マスク２３を配置する。本実施形態では、第１マスク２１の横方向の端部が、第２マスク２３で覆われている。本実施形態によれば、ＧａＮ層３２が会合する前にエピタキシャル成長を停止できる。また、本実施形態によれば、第１マスク２１が第２マスク２３及びＧａＮ層３２で覆われることにより、第１マスク２１からＧａＮ層３３へのオートドープの発生を低減できる。このような本実施形態によれば、ｎ＋型の層を会合させる必要がないため、製造時間を短縮し、製造に要する手間を削減できる。 (effect)
As described above, in the present embodiment, the second mask 23 that does not contain the element that becomes the donor or acceptor in the semiconductor layer 31 is superimposed on at least a part of the first mask 21 that contains the element that becomes the donor or acceptor in the semiconductor layer 31. Deploy. In the present embodiment, the lateral end portion of the first mask 21 is covered with the second mask 23. According to this embodiment, the epitaxial growth can be stopped before the GaN layer 32 is associated. Further, according to the present embodiment, since the first mask 21 is covered with the second mask 23 and the GaN layer 32, the occurrence of autodoping from the first mask 21 to the GaN layer 33 can be reduced. According to this embodiment, since it is not necessary to associate the n + type layers, the manufacturing time can be shortened and the labor required for manufacturing can be reduced.
　本実施形態では、分離位置Ｐにおいて、第１マスク２１上に形成された第２マスク２３が露出する。本実施形態では、マスク除去の際に、ウエットエッチングによって、分離位置Ｐから第２マスク２３及び第１マスク２１を除去できる。このように、本実施形態によれば、半導体素子１の製造時に、第１マスク及び第２マスク２３の除去のためのドライエッチングを実施せずに製造できる。本実施形態は、第１マスク及び第２マスク２３の除去のためのドライエッチングを要しないので、半導体に与えるダメージを低減できる。また、本実施形態は、第１マスク及び第２マスク２３の除去のためのドライエッチングに起因する不良の発生を低減できる。 In the present embodiment, the second mask 23 formed on the first mask 21 is exposed at the separation position P. In the present embodiment, when removing the mask, the second mask 23 and the first mask 21 can be removed from the separation position P by wet etching. As described above, according to the present embodiment, the semiconductor element 1 can be manufactured without performing dry etching for removing the first mask and the second mask 23 at the time of manufacturing. Since the present embodiment does not require dry etching for removing the first mask and the second mask 23, damage to the semiconductor can be reduced. Further, the present embodiment can reduce the occurrence of defects caused by dry etching for removing the first mask and the second mask 23.
　本実施形態では、第２マスク２３の幅ｗは、例えば２０μｍ以上１００μｍ以下である。本実施形態では、分離位置Ｐにおいて、第１マスク２１及び第２マスク２３を除去した後、ステップＳＴ４６においてドライエッチングを適切に実施できる。本実施形態では、ステップＳＴ１３においてＥＬＯ法を実施する際に、第２マスク２３上にデブリが発生することを抑制できる。 In the present embodiment, the width w of the second mask 23 is, for example, 20 μm or more and 100 μm or less. In the present embodiment, after removing the first mask 21 and the second mask 23 at the separation position P, dry etching can be appropriately performed in step ST46. In the present embodiment, it is possible to suppress the generation of debris on the second mask 23 when the ELO method is carried out in step ST13.
　本実施形態では、第２マスク２３は、複数の半導体素子１を個片に分離する位置を含んで配置されている。本実施形態によれば、分離位置Ｐにおいて半導体層３１が会合しないので、複数の半導体素子１を個片に容易に分離できる。 In the present embodiment, the second mask 23 is arranged including a position where the plurality of semiconductor elements 1 are separated into individual pieces. According to this embodiment, since the semiconductor layer 31 does not associate at the separation position P, the plurality of semiconductor elements 1 can be easily separated into individual pieces.
　本実施形態によれば、第１マスク２１の段差２４を転写することによってメサ構造又はトレンチ構造が形成された半導体素子１を製造できる。 According to this embodiment, the semiconductor element 1 in which the mesa structure or the trench structure is formed can be manufactured by transferring the step 24 of the first mask 21.
［変形例１］
　図７を参照して、実施形態の変形例１について説明する。図７は、実施形態の変形例１に係る半導体素子１を説明するための断面模式図である。半導体素子１は、アノードに接続された、ｐｎ接合とショットキー接合とを組み合わせたＪＢＳ（Ｊｕｎｃｔｉｏｎ　Ｂａｒｒｉｅｒ　Ｓｃｈｏｔｔｋｙ）構造を有する。より詳しくは、変形例１に係る半導体素子１は、金属層（バリアメタル）である図示しないショットキー金属膜を設けてＧａＮ層３３とショットキー金属膜とのショットキー接合を設ける。 [Modification 1]
A modified example 1 of the embodiment will be described with reference to FIG. 7. FIG. 7 is a schematic cross-sectional view for explaining the semiconductor element 1 according to the modified example 1 of the embodiment. The semiconductor element 1 has a JBS (Junction Barrier Schottky) structure in which a pn junction and a Schottky junction are combined, which is connected to the anode. More specifically, the semiconductor device 1 according to the modification 1 is provided with a Schottky metal film (not shown) which is a metal layer (barrier metal), and a Schottky junction between the GaN layer 33 and the Schottky metal film is provided.
　図７に示すように、変形例１に係る製造方法によって製造された半導体素子１は、ＧａＮ層３３の面３３ａ上にＪＢＳ構造が形成されている。半導体装置２は、このような半導体素子１を含む。 As shown in FIG. 7, the semiconductor device 1 manufactured by the manufacturing method according to the modified example 1 has a JBS structure formed on the surface 33a of the GaN layer 33. The semiconductor device 2 includes such a semiconductor element 1.
　図７を参照して、半導体素子１を含む半導体装置２の製造方法を説明する。ステップＳＴ１１、ステップＳＴ１２は、実施形態と同様に行う。ステップＳＴ４１ないしステップＳＴ４５は、実施形態と同様に行う。 A method of manufacturing the semiconductor device 2 including the semiconductor element 1 will be described with reference to FIG. 7. Steps ST11 and ST12 are performed in the same manner as in the embodiment. Steps ST41 to ST45 are performed in the same manner as in the embodiment.
　ＥＬＯ技術を用いて開口部２１ｓから露出する基板１１の表面１１ａから半導体層３１としてのＧａＮ層を形成する（ステップＳＴ１３）。より詳しくは、まず、実施形態と同様に、高不純物濃度のｎ＋型のＧａＮ層３２をエピタキシャル成長させる。 Using the ELO technique, a GaN layer as a semiconductor layer 31 is formed from the surface 11a of the substrate 11 exposed from the opening 21s (step ST13). More specifically, first, as in the embodiment, the n + type GaN layer 32 having a high impurity concentration is epitaxially grown.
　ＧａＮ層３２を覆うように低不純物濃度のＧａＮ層３５をエピタキシャル成長させる。ＧａＮ層３５は、開口部２３ｓから露出するＧａＮ層３２の表面３２ｂから、まず縦方向に成長し、その後、段差２４を埋めるように横方向に成長させる。ＧａＮ層３５は、ｐ＋型半導体層である。ＧａＮ層３５は、１０１８ｃｍ－３以上のホールキャリア濃度となるよう、ｐ型不純物のドープ量がコントロールされる。ＧａＮ層３５の表面３５ｂは、ほぼ平坦となる。ＧａＮ層３５は、例えば２０ｎｍ程度以上の厚さｄ６を有する。 The GaN layer 35 having a low impurity concentration is epitaxially grown so as to cover the GaN layer 32. The GaN layer 35 first grows in the vertical direction from the surface 32b of the GaN layer 32 exposed from the opening 23s, and then grows in the horizontal direction so as to fill the step 24. The GaN layer 35 is a p + type semiconductor layer. The doping amount of the p-type impurity is controlled in the GaN layer 35 so that the hole carrier concentration is 10 18 cm -3 or more. The surface 35b of the GaN layer 35 is substantially flat. The GaN layer 35 has, for example, a thickness d6 of about 20 nm or more.
　続くＧａＮ層３３は、露出するＧａＮ層３５の表面３５ｂから、まず縦方向に成長し、その後、段差２４を埋めるように横方向に成長させる。 The subsequent GaN layer 33 first grows in the vertical direction from the surface 35b of the exposed GaN layer 35, and then grows in the horizontal direction so as to fill the step 24.
　さらにＧａＮ層３４は、露出するＧａＮ層３３の表面３３ｂから、まず縦方向に成長し、その後、横方向に成長させる。 Further, the GaN layer 34 first grows in the vertical direction from the surface 33b of the exposed GaN layer 33, and then grows in the horizontal direction.
　ＧａＮ層３２の全体及びＧａＮ層３５の一部をドライエッチングする（ステップＳＴ４６）。より詳しくは、第１マスク２１に接した、半導体層３１のＧａＮ層３２の面３２ａの全面及び、ＧａＮ層３５の一部をドライエッチングする。具体的には、ＧａＮ層３２及びＧａＮ層３５をドライエッチング又はウエットエッチングの少なくともどちらかで溶解させる。なお、ＧａＮ層３２及びＧａＮ層３５をウエットエッチングする場合には、ＧａＮ層３２及びＧａＮ層３５の厚さｄ６を１μｍ以下に薄くてもよい。これにより、ＧａＮ層３３の面３３ａ上に形成されたＧａＮ層３５が一部を残して除去される。変形例１では、残ったＧａＮ層３５は、ＧａＮ層３３の面３３ａに矩形の枠状に配置されている。変形例１では、残ったＧａＮ層３５は、三重の入れ子状に配置されているがこれに限定されず、１つ以上配置されていればよい。残ったＧａＮ層３５のうち、外側のＧａＮ層３５は、内側のＧａＮ層３５に比べて幅が広く形成されていてもよい。 Dry etching the entire GaN layer 32 and a part of the GaN layer 35 (step ST46). More specifically, the entire surface of the surface 32a of the GaN layer 32 of the semiconductor layer 31 and a part of the GaN layer 35 in contact with the first mask 21 are dry-etched. Specifically, the GaN layer 32 and the GaN layer 35 are melted by at least either dry etching or wet etching. When the GaN layer 32 and the GaN layer 35 are wet-etched, the thickness d6 of the GaN layer 32 and the GaN layer 35 may be reduced to 1 μm or less. As a result, the GaN layer 35 formed on the surface 33a of the GaN layer 33 is removed except for a part. In the first modification, the remaining GaN layer 35 is arranged in a rectangular frame shape on the surface 33a of the GaN layer 33. In the first modification, the remaining GaN layers 35 are arranged in a triple nested manner, but the present invention is not limited to this, and one or more may be arranged. Of the remaining GaN layer 35, the outer GaN layer 35 may be formed to be wider than the inner GaN layer 35.
　ＧａＮ層３２の全体及びＧａＮ層３５の一部をドライエッチングする代わりに、ＧａＮ層３２の全体及びＧａＮ層３５の一部を研磨してもよい。より詳しくは、第１マスク２１に接した、半導体層３１のＧａＮ層３２の面３２ａの全面及び、ＧａＮ層３５の一部を研磨してもよい。具体的には、ＧａＮ層３５が露出するまで、ＧａＮ層３２を研磨する。その後、ＧａＮ層３５の一部をマスクし、ＧａＮ層３５をドライエッチングする。これにより、ＧａＮ層３５は、ＧａＮ層３２より薄いので、エッチングレートが低くなり時間をかけずに半導体層３１へのダメージを低減できる。 Instead of dry etching the entire GaN layer 32 and a part of the GaN layer 35, the entire GaN layer 32 and a part of the GaN layer 35 may be polished. More specifically, the entire surface of the surface 32a of the GaN layer 32 of the semiconductor layer 31 and a part of the GaN layer 35 may be polished in contact with the first mask 21. Specifically, the GaN layer 32 is polished until the GaN layer 35 is exposed. After that, a part of the GaN layer 35 is masked and the GaN layer 35 is dry-etched. As a result, since the GaN layer 35 is thinner than the GaN layer 32, the etching rate becomes low and damage to the semiconductor layer 31 can be reduced without taking time.
　以上により、第１マスク２１に接した、半導体層３１のＧａＮ層３２の全体及びＧａＮ層３５の一部を残して除去して、ＪＢＳ構造を形成できる。変形例１では、フィールドプレートを形成することにより、電極端部に加わる電界を緩和できる。変形例１によれば、サージ耐量電流を高めた半導体素子１を製造できる。変形例１によれば、耐圧性を高めた半導体素子１を製造できる。 From the above, the JBS structure can be formed by removing the entire GaN layer 32 of the semiconductor layer 31 and a part of the GaN layer 35 in contact with the first mask 21. In the first modification, the electric field applied to the end of the electrode can be relaxed by forming the field plate. According to the first modification, the semiconductor element 1 having an increased surge withstand current can be manufactured. According to the first modification, the semiconductor element 1 having an increased withstand voltage can be manufactured.
［変形例２］
　図８、図９を参照して、実施形態の変形例２について説明する。図８は、実施形態の変形例２に係る半導体素子１を説明するための断面模式図である。図９は、実施形態の変形例２に係る半導体装置２の製造方法を説明するための工程図である。変形例２に係る半導体素子１は、ＪＢＳ構造及びＦＬＲ（Ｆｉｅｌｄ　Ｌｉｍｉｔｉｎｇ　Ｒｉｎｇ）構造を有する。 [Modification 2]
A modified example 2 of the embodiment will be described with reference to FIGS. 8 and 9. FIG. 8 is a schematic cross-sectional view for explaining the semiconductor element 1 according to the second modification of the embodiment. FIG. 9 is a process diagram for explaining a method of manufacturing the semiconductor device 2 according to the second modification of the embodiment. The semiconductor device 1 according to the second modification has a JBS structure and a FLR (Field Limiting Ring) structure.
　図８に示すように、変形例２に係る製造方法によって製造された半導体素子１は、ＧａＮ層３３の面３３ａ上にＦＬＲ構造が形成されている。半導体装置２は、このような半導体素子１を含む。半導体素子１は、メサ構造を有しておらず、ＦＬＲ構造を有する。 As shown in FIG. 8, the semiconductor device 1 manufactured by the manufacturing method according to the modification 2 has an FLR structure formed on the surface 33a of the GaN layer 33. The semiconductor device 2 includes such a semiconductor element 1. The semiconductor element 1 does not have a mesa structure but has an FLR structure.
　変形例２において、第１マスク２１の厚さｄ１と第２マスク２３の厚さｄ３との合計は、ＧａＮ層３２の厚さｄ２と同程度の厚さでよい。第２マスク２３の積層方向の厚さｄ３は、例えば、１μｍ以下であってもよい。 In the second modification, the sum of the thickness d1 of the first mask 21 and the thickness d3 of the second mask 23 may be about the same as the thickness d2 of the GaN layer 32. The thickness d3 of the second mask 23 in the stacking direction may be, for example, 1 μm or less.
　図９に示す半導体素子１は、ステップＳＴ１１からステップＳＴ４５までは、変形例１の半導体素子１と同様の工程を実行する。 The semiconductor element 1 shown in FIG. 9 executes the same process as the semiconductor element 1 of the modification 1 from step ST11 to step ST45.
　変形例２では、ステップＳＴ４６の実施後に残ったＧａＮ層３５は、四重の入れ子状に配置されている。例えば、内側の三重のＧａＮ層３５はＪＢＳ構造を形成し、外側のＧａＮ層３５はＦＬＲ構造を形成する。ＪＢＳ構造及びＦＬＲ構造の例はこれに限定されない。 In the second modification, the GaN layer 35 remaining after the execution of step ST46 is arranged in a quadruple nested manner. For example, the inner triple GaN layer 35 forms a JBS structure and the outer GaN layer 35 forms an FLR structure. Examples of JBS and FLR structures are not limited to this.
　露出するＧａＮ層３３の面３３ａにショットキー接合するショットキー金属膜４１を形成する（ステップＳＴ４７）。ショットキー金属膜４１により、露出するＧａＮ層３３の面３３ａの中間部、及び、ＧａＮ層３３の面３３ａの中間部に配置されたＧａＮ層３５が覆われる。ショットキー金属膜４１は、内側のＧａＮ層３５及びその間に露出するＧａＮ層３３の面３３ａを覆って配置される。ＧａＮ層３３とショットキー金属膜４１とのショットキー接合が設けられる。ショットキー金属膜４１は、ＧａＮ層３３の面３３ａの周縁部、言い換えると、ＦＬＲ構造を形成する部分には配置されない。 A Schottky metal film 41 to be Schottky bonded is formed on the surface 33a of the exposed GaN layer 33 (step ST47). The Schottky metal film 41 covers the intermediate portion of the surface 33a of the exposed GaN layer 33 and the GaN layer 35 arranged in the intermediate portion of the surface 33a of the GaN layer 33. The Schottky metal film 41 is arranged so as to cover the inner GaN layer 35 and the surface 33a of the GaN layer 33 exposed between them. A Schottky junction between the GaN layer 33 and the Schottky metal film 41 is provided. The Schottky metal film 41 is not arranged on the peripheral edge of the surface 33a of the GaN layer 33, in other words, on the portion forming the FLR structure.
　ショットキー金属膜４１は、例えばＮｉ、Ａｌ、Ｐｄなどである。 The shotkey metal film 41 is, for example, Ni, Al, Pd, or the like.
　絶縁層である絶縁膜４２を形成する（ステップＳＴ４８）。絶縁膜４２は、露出するＧａＮ層３３の面３３ａの周縁部、及び、ＧａＮ層３３の面３３ａの周縁部に配置されたＧａＮ層３５を覆って配置される。 The insulating film 42, which is an insulating layer, is formed (step ST48). The insulating film 42 is arranged so as to cover the peripheral portion of the surface 33a of the exposed GaN layer 33 and the GaN layer 35 arranged on the peripheral portion of the surface 33a of the GaN layer 33.
　ステップＳＴ４８において、絶縁膜４２は、ＧａＮ層３３の面３３ａの中間部を除いて配置される。絶縁膜４２は、ショットキー金属膜４１より外側に配置される。これにより、ｐｎ接合は、アノードに接続されない。 In step ST48, the insulating film 42 is arranged except for the intermediate portion of the surface 33a of the GaN layer 33. The insulating film 42 is arranged outside the Schottky metal film 41. As a result, the pn junction is not connected to the anode.
　ショットキー金属膜４１上及び絶縁膜４２上に上面電極金属膜４３を形成する（ステップＳＴ４９）。上面電極金属膜４３は、ショットキー金属膜４１によって覆われたＧａＮ層３５を覆って配置される。また、上面電極金属膜４３は、絶縁膜４２上で所謂フィールドプレートを形成する。上面電極金属膜４３は、絶縁膜４２によって覆われた外側のＧａＮ層３５と、ショットキー金属膜４１によって覆われた内側のＧａＮ層３５とにそれぞれ配置される。変形例２では、絶縁膜４２及び上面電極金属膜４３によって外側のＧａＮ層３５が覆われることによって、ＦＬＲ構造が形成されている。上面電極金属膜４３同士は、離間しており接触していない。 The top electrode metal film 43 is formed on the Schottky metal film 41 and the insulating film 42 (step ST49). The top electrode metal film 43 is arranged so as to cover the GaN layer 35 covered with the Schottky metal film 41. Further, the top electrode metal film 43 forms a so-called field plate on the insulating film 42. The top electrode metal film 43 is arranged on the outer GaN layer 35 covered with the insulating film 42 and the inner GaN layer 35 covered with the Schottky metal film 41, respectively. In the second modification, the FLR structure is formed by covering the outer GaN layer 35 with the insulating film 42 and the top electrode metal film 43. The top electrode metal films 43 are separated from each other and are not in contact with each other.
　フィールドプレートを形成することにより、電極端部に加わる電界を緩和できるため、耐圧の高いデバイスになる。フィールドプレートは、上部電極と分離してもよい。 By forming a field plate, the electric field applied to the end of the electrode can be relaxed, making it a device with high withstand voltage. The field plate may be separated from the top electrode.
　以上により、第１マスク２１に接した、半導体層３１のＧａＮ層３５をドライエッチングで一部を残して除去して、ＪＢＳ構造及びＦＬＲ構造を形成できる。このようにして、変形例２によれば、耐圧性を高めた半導体素子１を製造できる。 From the above, the GaN layer 35 of the semiconductor layer 31 in contact with the first mask 21 can be removed by dry etching to form the JBS structure and the FLR structure. In this way, according to the modification 2, the semiconductor element 1 having an increased withstand voltage can be manufactured.
　本出願の開示する実施形態は、発明の要旨及び範囲を逸脱しない範囲で変更することができる。さらに、本出願の開示する実施形態及びその変形例は、適宜組み合わせることができる。 The embodiments disclosed in this application can be changed without departing from the gist and scope of the invention. Further, the embodiments disclosed in the present application and variations thereof can be combined as appropriate.
　添付の請求項に係る技術を完全かつ明瞭に開示するために特徴的な実施形態に関し記載してきた。しかし、添付の請求項は、上記実施形態に限定されるべきものでなく、本明細書に示した基礎的事項の範囲内で当該技術分野の当業者が創作しうるすべての変形例及び代替可能な構成を具現化するように構成されるべきである。 A characteristic embodiment has been described in order to completely and clearly disclose the technique according to the attached claim. However, the attached claims are not limited to the above embodiments, and all modifications and alternatives that can be created by those skilled in the art within the scope of the basic matters shown in the present specification are possible. It should be configured to embody a unique configuration.
　また、段差２４の形状は、傾斜を有してもよいし、角部を丸めてもよい。 Further, the shape of the step 24 may have an inclination or may have rounded corners.
　なお、以上の実施形態に拘わらず、形状は、段差が２箇所以上あるものであってもよい。また、開口部２１ｓから径方向の外側に向かって上へ上がる段差に限定されず、下へ下がる段差も実施できる。したがって、一旦上へ上がって下へ下がる形状とすることで凸な形状も形成できる。第１マスク２１及び第２マスク２３の凸な形状を転写することで、トレンチ構造も形成できる。したがって、上記メサ構造は、トレンチ構造としてもよい。また、半導体素子１の中心から径方向の外側に向かって１又は複数のトレンチ構造と、最外縁のメサ構造とを形成することもできる。 Regardless of the above embodiment, the shape may have two or more steps. Further, the step is not limited to a step that rises upward from the opening 21s toward the outside in the radial direction, and a step that descends downward can also be implemented. Therefore, a convex shape can be formed by forming a shape that once goes up and goes down. A trench structure can also be formed by transferring the convex shapes of the first mask 21 and the second mask 23. Therefore, the mesa structure may be a trench structure. Further, one or a plurality of trench structures and a mesa structure at the outermost edge can be formed from the center of the semiconductor element 1 toward the outside in the radial direction.
　１　半導体素子
　２　半導体装置
　１１　基板
　１１ａ　表面
　２１　第１マスク
　２１ｄ　側面
　２１ｓ　開口部
　２２　レジストマスク
　２３　第２マスク
　２３ｄ　側面
　２３ｓ　開口部
　２４　段差
　２５　レジストパターン
　２５ｓ　開口部
　３１　半導体層
　３１ｂ　裏面
　３２　ＧａＮ層（第１半導体層）
　３３　ＧａＮ層（第２半導体層）
　３４　ＧａＮ層（第３半導体層）
　５１　支持基板
　６１　裏面電極
　２００　実装基板
　２０１　電極パッド
　２０２　電極パッド 1 Semiconductor element 2 Semiconductor device 11 Substrate 11a Surface 21 First mask 21d Side surface 21s Opening 22 Resist mask 23 Second mask 23d Side surface 23s Opening 24 Step 25 Resist pattern 25s Opening 31 Semiconductor layer 31b Back side 32 GaN layer (1st Semiconductor layer)
33 GaN layer (second semiconductor layer)
34 GaN layer (third semiconductor layer)
51 Support board 61 Back side electrode 200 Mounting board 201 Electrode pad 202 Electrode pad

Claims (13)

  1. 　基板の表面に、一部が開口している第１マスクを設ける工程と、
    　前記第１マスクの一部を覆うように第２マスクを形成する工程と、
    　前記開口から露出する前記基板の表面から、前記第１マスクを覆い、前記第２マスクを露出させるようにエピタキシャル成長させて、第１半導体層を成長する工程と、
    　を含み、
    　前記第１マスクは、前記第１半導体層におけるドナーとなる元素を含み、
    　前記第２マスクは、前記第１半導体層におけるドナーとなる元素を含まない、
    　半導体素子の製造方法。     The process of providing a first mask with a partial opening on the surface of the substrate, and
    The step of forming the second mask so as to cover a part of the first mask, and
    A step of covering the first mask from the surface of the substrate exposed from the opening and epitaxially growing the second mask so as to expose the second mask to grow the first semiconductor layer.
    Including
    The first mask contains an element that becomes a donor in the first semiconductor layer.
    The second mask does not contain an element that becomes a donor in the first semiconductor layer.
    Manufacturing method for semiconductor devices.
  2. 　前記第１半導体層を成長する工程の後に、第２半導体層を成長する工程、をさらに含み、
    　前記第１半導体層は、ｎ＋型半導体層であり、
    　前記第２半導体層は、ｎ－型半導体層である、請求項１に記載の半導体素子の製造方法。     After the step of growing the first semiconductor layer, a step of growing a second semiconductor layer is further included.
    The first semiconductor layer is an n + type semiconductor layer, and is an n + type semiconductor layer.
    The method for manufacturing a semiconductor element according to claim 1, wherein the second semiconductor layer is an n-type semiconductor layer.
  3. 　前記第２マスクの積層方向と直交する横方向の幅は、２０μｍ以上１００μｍ以下である、請求項１または請求項２に記載の半導体素子の製造方法。 The method for manufacturing a semiconductor element according to claim 1 or 2, wherein the width in the lateral direction orthogonal to the stacking direction of the second mask is 20 μm or more and 100 μm or less.
  4. 　前記第２マスクは、複数の前記半導体素子を個片に分離する位置を含んで配置されている、請求項１から請求項３のいずれか一項に記載の半導体素子の製造方法。 The method for manufacturing a semiconductor element according to any one of claims 1 to 3, wherein the second mask is arranged including a position for separating the plurality of the semiconductor elements into individual pieces.
  5. 　ショットキー接合を設ける、請求項１から請求項４のいずれか一項に記載の半導体素子の製造方法。 The method for manufacturing a semiconductor device according to any one of claims 1 to 4, wherein a Schottky junction is provided.
  6. 　ＪＢＳ構造を有している、請求項１から請求項４のいずれか一項に記載の半導体素子の製造方法。 The method for manufacturing a semiconductor device according to any one of claims 1 to 4, which has a JBS structure.
  7. 　メサ構造を有する、請求項５または請求項６に記載の半導体素子の製造方法。 The method for manufacturing a semiconductor device according to claim 5 or 6, which has a mesa structure.
  8. 　前記第２マスクの積層方向の厚さは、３μｍ以上である、請求項７に記載の半導体素子の製造方法。 The method for manufacturing a semiconductor element according to claim 7, wherein the thickness of the second mask in the stacking direction is 3 μm or more.
  9. 　ＦＬＲを有する、請求項５または請求項６に記載の半導体素子の製造方法。 The method for manufacturing a semiconductor device according to claim 5 or 6, which has FLR.
  10. 　前記第２マスクの積層方向の厚さは、１μｍ以下である、請求項９に記載の半導体素子の製造方法。 The method for manufacturing a semiconductor device according to claim 9, wherein the thickness of the second mask in the stacking direction is 1 μm or less.
  11. 　ｎ＋型半導体のドープ濃度は、１０１８／ｃｍ３以上である、請求項１から請求項１０のいずれか一項に記載の半導体素子の製造方法。 The method for manufacturing a semiconductor device according to any one of claims 1 to 10, wherein the doping concentration of the n + type semiconductor is 10 18 / cm 3 or more.
  12. 　請求項１から請求項１１のいずれか一項に記載の半導体素子の製造方法により製造された半導体素子。 A semiconductor device manufactured by the method for manufacturing a semiconductor device according to any one of claims 1 to 11.
  13. 　請求項１から請求項１１のいずれか一項に記載の半導体素子の製造方法により製造された半導体素子を含む半導体装置。 A semiconductor device including a semiconductor device manufactured by the method for manufacturing a semiconductor device according to any one of claims 1 to 11.
PCT/JP2021/038102 2020-10-28 2021-10-14 Method for producing semiconductor element, semiconductor element, and semiconductor device WO2022091803A1 (en)

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JP2008546181A (en) * 2005-05-17 2008-12-18 アンバーウェーブ システムズ コーポレイション Lattice-mismatched semiconductor structure with low dislocation defect density and related device manufacturing method
JP2012119409A (en) * 2010-11-30 2012-06-21 Nippon Telegr & Teleph Corp <Ntt> Semiconductor element, semiconductor optical element, and semiconductor integrated element
JP2019204833A (en) * 2018-05-22 2019-11-28 日本電信電話株式会社 Optical device structure and manufacturing method thereof

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003234546A (en) * 2002-02-07 2003-08-22 Nec Corp Semiconductor multilayer film, semiconductor element using the film, and manufacturing method thereof
JP2008546181A (en) * 2005-05-17 2008-12-18 アンバーウェーブ システムズ コーポレイション Lattice-mismatched semiconductor structure with low dislocation defect density and related device manufacturing method
JP2012119409A (en) * 2010-11-30 2012-06-21 Nippon Telegr & Teleph Corp <Ntt> Semiconductor element, semiconductor optical element, and semiconductor integrated element
JP2019204833A (en) * 2018-05-22 2019-11-28 日本電信電話株式会社 Optical device structure and manufacturing method thereof

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