WO2022088056A1 - 形成叉型结构中侧墙的方法和叉型结构的半导体器件 - Google Patents

形成叉型结构中侧墙的方法和叉型结构的半导体器件 Download PDF

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WO2022088056A1
WO2022088056A1 PCT/CN2020/125335 CN2020125335W WO2022088056A1 WO 2022088056 A1 WO2022088056 A1 WO 2022088056A1 CN 2020125335 W CN2020125335 W CN 2020125335W WO 2022088056 A1 WO2022088056 A1 WO 2022088056A1
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layer
channel
doping
trench
dielectric layer
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PCT/CN2020/125335
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English (en)
French (fr)
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万光星
黄威森
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华为技术有限公司
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Priority to CN202080105292.9A priority Critical patent/CN116261788A/zh
Priority to PCT/CN2020/125335 priority patent/WO2022088056A1/zh
Priority to EP20959218.7A priority patent/EP4228008A4/en
Publication of WO2022088056A1 publication Critical patent/WO2022088056A1/zh
Priority to US18/309,205 priority patent/US20230261081A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H01L29/0669—Nanowires or nanotubes
    • H01L29/0673—Nanowires or nanotubes oriented parallel to a substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H01L29/42392—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor fully surrounding the channel, e.g. gate-all-around
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66439—Unipolar field-effect transistors with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/775—Field effect transistors with one dimensional charge carrier gas channel, e.g. quantum wire FET
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic

Definitions

  • the present application relates to the field of semiconductor technology, and in particular, to a method for forming a spacer in a fork structure and a fork structure semiconductor device.
  • Existing forksheet structures include: sidewalls, NMOS and PMOS on both sides of the sidewall. Due to the smaller width of the sidewall, the distance between NMOS and PMOS is reduced.
  • the current principle of forming the sidewall is as follows: firstly, an overlapping layer is formed, a trench is formed in the overlapping layer by photolithography, and the trench is filled to form the sidewall.
  • the sidewall spacers are formed by filling the trenches, and the width of the trenches is determined by photolithography, the width of the sidewall spacers is also determined by photolithography. Since the width of the sidewall is relatively small, the above-mentioned method of forming the sidewall requires higher lithography precision and lithography capability.
  • the present application provides a method for forming a sidewall in a fork-shaped structure and a semiconductor device with a fork-shaped structure, which are used to solve the problem that the method of forming the sidewall requires high lithography precision and lithography capability.
  • the present application provides a method for forming a sidewall in a fork-type structure, comprising: providing a substrate; forming an overlapping layer in which a first material and a second material are sequentially stacked on the substrate; forming a first mask layer on the layer; forming a first trench in the first mask layer; by forming a second mask layer on the first mask layer and in the first trench , forming a second trench in the first trench; using anisotropic etching to etch the second mask layer in a direction perpendicular to the substrate, until the second mask layer is removed the second mask layer between the sidewalls of the trenches and on the lower surface of the first trench to form a third trench based on the second trench; using the second mask layer As a protective layer, etch down from the lower surface of the third trench to form a fourth trench that penetrates the overlapping layer and extends into the substrate; forming in the fourth trench side wall.
  • the width of the spacer is determined by the width of the fourth trench, and the principle of forming the fourth trench is to form the first trench in the first mask layer, and A second trench is formed in the first trench by forming a second mask layer in the first trench, and the second trench is removed along the direction perpendicular to the substrate by anisotropic etching.
  • the width of the first trench is larger than that of the fourth trench, that is, the width of the first trench is relatively large. In this way, during the process of forming the first trench, The requirements for lithography precision and lithography capability are reduced, and further, in the process of forming the sidewall, the requirements for lithography precision and lithography capability are reduced.
  • the method further includes: forming a first overlapping structure and a second overlapping structure on both sides of the sidewall, wherein the first overlapping structure, the second overlapping structure
  • the stacked structure and the side walls are covered with a first dielectric layer and a second dielectric layer, one end of the first dielectric layer is flush with one end of the first overlapped structure and the second overlapped structure, and the One end of the second dielectric layer is flush with the other ends of the first overlapping structure and the second overlapping structure, and the other end of the first dielectric layer is a predetermined distance from the other end of the second dielectric layer distance; remove the first target material covered by the first dielectric layer and the second dielectric layer in the first overlapping structure, and remove the first dielectric layer and the second dielectric layer in the second overlapping structure.
  • the first target material is a material not used to form the first channel layer among the first material and the second material; the second target material is the first material and the second material In the material not used for forming the second channel layer, the doping types of the first doping structure and the second doping structure are opposite.
  • the method further includes: forming a first gate insulating layer on the first channel layer, and forming a second gate insulating layer on the second channel layer; A first gate conductive layer is formed on a gate insulating layer, and a second gate conductive layer is formed on the second gate insulating layer.
  • the materials of the first gate insulating layer and the second gate insulating layer are the same, and the materials of the first gate conductive layer and the second gate conductive layer are the same; The materials of the first gate conductive layer and the second gate conductive layer are the same.
  • the method further includes: removing the spacer between the first dielectric layer and the second dielectric layer; removing the spacer between the first channel layer and the second dielectric layer; A gate insulating layer is formed on the two channel layers; a gate conductive layer is formed on the gate insulating layer.
  • the forming the first overlapping structure and the second overlapping structure on both sides of the sidewall includes: removing the mask layer to be removed and the mask layer located below the mask layer to be removed overlapping layers to form a fifth overlapping structure and a sixth overlapping structure located on both sides of the sidewall, wherein the mask layer to be removed is a first mask located outside the sidewall of the first trench a film layer; forming a dummy gate structure covering the fifth overlapping structure, the sixth overlapping structure and the spacer, wherein the length of the dummy gate structure is equal to the preset distance; The first dielectric layer and the second dielectric layer are formed at both ends of the dummy gate structure; the dummy gate structure, the first dielectric layer and the second dielectric are removed from the fifth overlapping structure the area covered by the layer to obtain the first overlapping structure; remove the area not covered by the dummy gate structure, the first dielectric layer and the second dielectric layer in the sixth overlapping structure to The second overlapping structure is obtained.
  • the method before forming the plurality of first channel layers and the plurality of second channel layers, the method further includes: removing the dummy gate structure.
  • the method further includes: forming a fifth dielectric layer on the substrate, the plurality of first channel layers, the plurality of second channel layers, the A doping structure and the second doping structure are located on the fifth dielectric layer.
  • the materials of the first channel layer and the second channel layer are different.
  • the first doping structure is P-type doping
  • the second doping structure is N-type doping
  • the material of the first channel layer is silicon germanium
  • the The material of the second channel layer is silicon.
  • the present application provides a semiconductor device with a fork structure, including: a substrate; sidewall spacers arranged vertically on the substrate; a plurality of first channel layers on one side wall of the wall, the first channel layers extending along the side wall of the side wall; and arranged on the side wall of the side wall at intervals along the direction perpendicular to the substrate a plurality of second channel layers on the other side, the second channel layers extending along the side of the sidewall spacer; the first doping structures arranged at both ends of the plurality of first channel layers, arranged a second doping structure at both ends of the plurality of second channel layers, the doping type of the first doping structure is opposite to that of the second doping structure; covering the plurality of second doping structures One end of the first surface of a channel layer and a first dielectric layer at one end of the first surface of the plurality of second channel layers cover the other ends of the first surfaces of the plurality of first channel layers and the second dielectric layer at the other end of the first
  • the semiconductor device further includes: a fifth dielectric layer on the substrate, the plurality of first channel layers, the plurality of second channels A layer, the first doped structure and the second doped structure are located on the fifth dielectric layer.
  • the first gate insulating layer and the second gate insulating layer have the same material, and the first gate conductive layer and the second gate conductive layer have the same material; or the The materials of the first gate conductive layer and the second gate conductive layer are the same.
  • the spacer between the first dielectric layer and the second dielectric layer is removed; the surface of the first channel layer that is in contact with the removed spacer
  • the first gate insulating layer and the first gate conductive layer are arranged in sequence; the second gate insulating layer and the second gate are sequentially arranged on the surface of the second channel layer in contact with the removed sidewall spacer Conductive layer; the materials of the first gate insulating layer and the second gate insulating layer are the same, and the materials of the first gate conductive layer and the second gate conductive layer are the same.
  • the materials of the first channel layer and the second channel layer are different.
  • the first doping structure is P-type doping
  • the second doping structure is N-type doping
  • the material of the first channel layer is silicon germanium
  • the The material of the second channel layer is silicon.
  • FIG. 1 is a schematic flowchart of forming a side wall according to an embodiment of the present application
  • FIG. 2 is a schematic structural diagram of a substrate, an overlapping layer and a first mask layer after forming the substrate according to an embodiment of the present application;
  • FIG. 3 is a schematic structural diagram after forming the first trench according to an embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of a third trench after forming according to an embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of the sidewalls provided in an embodiment of the present application.
  • FIG. 6 is a schematic flow chart of a first process provided by the embodiment of the present application.
  • FIG. 7 is a schematic structural diagram after forming a fifth overlapping structure and a sixth overlapping structure according to an embodiment of the present application.
  • FIG. 8 is a schematic structural diagram after forming a gap according to an embodiment of the present application.
  • FIG. 9 is a schematic structural diagram after forming a dummy gate structure according to an embodiment of the present application.
  • FIG. 10 is a schematic structural diagram after forming a first overlapping structure and a second overlapping structure according to an embodiment of the present application.
  • FIG. 11 is a schematic structural diagram after forming the first doping structure and the second doping structure according to an embodiment of the present application.
  • Figure 12 is a plan view of Figure 11 along the a-a' direction;
  • FIG. 13 is a schematic structural diagram after forming the first channel layer and the second channel layer according to an embodiment of the present application.
  • FIG. 14 is a schematic structural diagram after forming a first gate insulating layer, a second gate insulating layer, a first gate conductive layer, and a second gate conductive layer according to an embodiment of the present application;
  • 15 is a schematic structural diagram of forming an electrode structure and an isolation layer provided by an embodiment of the present application.
  • 16 is an energy band diagram of a first field effect transistor and a second field effect transistor
  • FIG. 17 is a schematic structural diagram after removing the sidewall between the first dielectric layer and the second dielectric layer according to an embodiment of the present application.
  • FIG. 18 is a schematic structural diagram after forming a gate insulating layer and a gate conductive layer according to an embodiment of the present application.
  • FIG. 19 is a schematic structural diagram after forming a fifth dielectric layer, an electrode structure and an isolation layer provided by an embodiment of the present application.
  • At least one (item) refers to one or more, and "a plurality” refers to two or more.
  • “And/or” is used to describe the relationship between related objects, indicating that there can be three kinds of relationships, for example, “A and/or B” can mean: only A, only B, and both A and B exist , where A and B can be singular or plural.
  • the character “/” generally indicates that the associated objects are an “or” relationship.
  • At least one item(s) below” or similar expressions thereof refer to any combination of these items, including any combination of single item(s) or plural items(s).
  • At least one (a) of a, b or c can mean: a, b, c, "a and b", “a and c", “b and c", or "a and b and c" ", where a, b, c can be single or multiple.
  • Fig. 1 is the schematic flow chart of forming sidewall provided by the embodiment of the application, as shown in Fig. 1, the method includes:
  • the material of the substrate 201 is silicon
  • the first material 2021 is silicon germanium
  • the second material 2022 is silicon
  • the overlapping layer 202 is sequentially overlapped by silicon germanium and silicon
  • the first mask layer 203 is formed of an oxide layer (oxide) 2031, a polysilicon (a-Si) layer 2032 and a silicon nitride (SiN) layer 2033, which are sequentially stacked.
  • oxide layer (oxide) 2031 oxide layer
  • a-Si polysilicon
  • SiN silicon nitride
  • the material of the substrate 201 can also be a semiconductor material such as germanium, and the first material 2021 and the second material 2022 can also be, for example, germanium, a semiconductor compound (ie, a semiconductor compound of four-cluster elements, three or five-cluster elements elemental semiconductor compounds) and other semiconductor materials.
  • the number of layers included in the overlapping layer 202 may also be determined according to design requirements.
  • the first mask layer 203 may also include more or less layers, which are not particularly limited here.
  • the material of the first mask layer 203 may also be other materials used in the semiconductor manufacturing process that can be used as a mask layer, which is not particularly limited here.
  • the first trench 205 vertically penetrates the polysilicon (a-Si) layer 2032 and the silicon nitride (SiN) layer 2033 in the first mask layer 203 , namely the first A trench 205 does not completely penetrate the first mask layer 203 .
  • the process of forming the first trench 203 may be as follows: coating photoresist on the first mask layer 203, and exposing and developing the photoresist to remove the first mask layer 203 for forming the first trench 205. The photoresist at the position is obtained to obtain the developed photoresist 204 in FIG. 2. As shown in FIG.
  • the area where the photoresist is removed is used to form the first trench 205;
  • the first mask layer 203 is etched downward in the area not covered by the photoresist 204 by anisotropic etching to form the first trench 205 .
  • the etched depth is the sum of the thicknesses of the polysilicon (a-Si) layer 2032 and the silicon nitride (SiN) layer 2033 in the first mask layer 203 . It should be noted that the above-mentioned process of forming the first trench 205 is only exemplary, and is not intended to limit the present application.
  • the first trench 205 may also be vertical and completely penetrate the first mask layer 203, and the first trench 205 may also be vertical and penetrate the polysilicon (a-Si) layer 2032, silicon nitride (SiN ) layer 2033 and a part of the oxide layer (oxide) 2031.
  • a-Si polysilicon
  • SiN silicon nitride
  • the photoresist 204 on the first mask layer 203 is removed.
  • the width of the first trench 205 is C, which is determined according to the width of the sidewall and the widths of the first channel layer and the second channel layer formed on both sides of the sidewall. The spacers, the first channel layer and the second channel layer will be described below.
  • Form a second trench in the first trench by forming a second mask layer on the first mask layer and in the first trench.
  • the material of the second mask layer can be, for example, oxide or silicon nitride, which is not particularly limited.
  • the material of the second mask layer and the material of the first mask layer may be the same or different, which are not particularly limited here. It should be noted that, when the first mask layer is composed of multiple materials, the material of the second mask layer may be the same as one of the multiple materials constituting the first mask layer, or may be the same as that constituting the first mask layer. Various materials of a mask layer are different.
  • the process of forming the second mask layer may be: forming a second mask layer on the surface of the structure after the first trench is formed by deposition, that is, on the first mask layer and in the first trench (that is, the first mask layer).
  • a second mask layer is formed on the sidewalls and the lower surface of the trench). Since there is a height difference between the lower surface of the first trench and the upper surface of the first mask layer, the second trench can be formed in the first trench by forming the second mask layer.
  • the third trench 207 uses the second mask layer 206 as its sidewall, and the lower surface of the third trench 207 and the lower surface of the first trench 205 Flat, that is, the lower surface of the third trench 207 is flat with the upper surface of the oxide layer (oxide) 2031 in the first mask layer 203 .
  • the material of the second mask layer 206 is silicon nitride.
  • anisotropic etching is adopted, and the second mask layer is used as a protective layer to etch downwards from the lower surface of the third trench to form a third groove extending through the overlapping layer and extending into the substrate.
  • the fourth trench may not completely penetrate the substrate, or may completely penetrate the substrate, which is not particularly limited here.
  • the fourth trench is filled to form sidewalls.
  • the material of the spacer can be, for example, an insulating material such as oxide or SiN.
  • the material of the sidewall may be the same as or different from the material of the second mask layer.
  • the material of the spacer 208 is the same as the material of the second mask layer 206 , that is, the material of the spacer 208 is silicon nitride. It should be noted that, in FIG. 5 , after the sidewall spacers are formed, the silicon nitride on the polysilicon layer 2032 is removed.
  • the thickness of the second mask layer that is, the thickness of the second mask layer on the sidewall of the first trench (ie, B in FIG. 4 )
  • the control of the width of the sidewall and the realization of self-alignment in the process of forming the sidewall reduce the dependence on the lithography process and the requirements on the lithography accuracy and lithography capability.
  • the size of the sidewall spacer is further reduced, thereby further reducing the size of the semiconductor device.
  • the width of the spacer is determined by the width of the fourth trench, and the principle of forming the fourth trench is to form the first trench in the first mask layer.
  • a trench, and a second trench is formed in the first trench by forming a second mask layer in the first trench, and the second trench is removed along the direction perpendicular to the substrate by anisotropic etching.
  • a second mask layer is located between the sidewalls of the two trenches and on the lower surface of the first trench to obtain a third trench, and under the protection of the second mask layer, from the lower surface of the third trench
  • the surface starts to be etched downward to form a fourth trench that penetrates the overlapping layer and extends into the substrate, that is, during the formation of the fourth trench, only the photolithography process is used in the formation of the first trench , and since the fourth trench is formed in the first trench, the width of the first trench is larger than the width of the fourth trench, that is, the width of the first trench is relatively large.
  • the requirements for lithography precision and lithography capability are reduced, and further, in the process of forming sidewalls, the requirements for lithography precision and lithography capability are reduced.
  • the semiconductor device of the forksheet structure may be formed by any one of various process flows.
  • the following two process flows are used as examples to describe the process flow of forming a semiconductor device with a forksheet structure.
  • first overlapped structure and a second overlapped structure on both sides of the sidewall, wherein the first overlapped structure, the second overlapped structure and the sidewall are covered with a first dielectric layer and a second dielectric layer, and the first overlapped structure, the second overlapped structure and the sidewall are covered with a first dielectric layer and a second dielectric layer.
  • One end of a dielectric layer is flush with one end of the first overlapping structure and the second overlapping structure
  • one end of the second dielectric layer is flush with the other ends of the first overlapping structure and the second overlapping structure, and the other end of the first dielectric layer
  • One end is separated from the other end of the second dielectric layer by a predetermined distance.
  • the lengths of the first overlapping structure and the second overlapping structure are both smaller than the lengths of the side walls.
  • the process of forming the first overlapping structure and the second overlapping structure on both sides of the sidewall may include:
  • a fifth overlapping structure and a sixth overlapping structure located on both sides of the sidewall are formed, wherein the mask layer to be removed is located on both sides of the sidewall.
  • a first mask layer outside the sidewall of the first trench is a polysilicon layer 2032 and an oxide layer (oxide) 2031 located outside the sidewall of the first trench in the first mask layer 203 .
  • the fifth overlapping structure and the sixth overlapping structure obtained after removing the mask layer to be removed and the underlying overlapping layer are shown in FIG.
  • the fifth overlapping structure 209 and the sixth overlapping structure Overlapping structures 210 are located on both sides of the sidewalls 208 . It should be noted that in the process of forming the fifth overlapping structure 209 and the sixth overlapping structure 210, the second mask layer 206 and the sidewall spacer 208 also have a certain loss in their heights.
  • a gap 211 is formed between the substrate 201 , the fifth stack structure 209 and the sixth stack structure 210 by etching the substrate 201 , And a fifth dielectric layer is formed in the gap 211 by means of deposition.
  • the substrate 201 can be separated from the fifth overlapping structure 209 and the sixth overlapping structure 210 by the fifth dielectric layer, so that the substrate 201 can be separated from the fifth overlapping structure 209 and the sixth overlapping structure 210 by the fifth dielectric layer.
  • the field effect transistors formed by the six overlapping structures 210 are separated, thereby avoiding the connection between the field effect transistors formed based on the fifth overlapping structure 209 and the sixth overlapping structure 210 and the substrate 201 to form parasitic devices, which improves the performance of the field effect transistors. performance.
  • the material of the fifth dielectric layer may be, for example, insulating materials such as oxide and silicon nitride, which are not particularly limited in this application.
  • the field effect transistor formed based on the fifth overlapping structure includes a plurality of first channel layers and first doping structures, etc.
  • the field effect transistor formed based on the sixth overlapping structure includes a plurality of second channels layer and second doping structure, etc. It can be seen from the above that since the fifth overlapping structure and the sixth overlapping structure are located on the fifth dielectric layer, there are a plurality of first channel layers and a first doping structure, a plurality of second channel layers and a second doping structure. The heterostructures are all located on the fifth dielectric layer.
  • the above-mentioned manner of forming the fifth dielectric layer is only exemplary, and is not intended to limit the present application.
  • the dummy gate structure 213 covers the fifth overlapping structure 209 , the sixth overlapping structure 210 and the sidewall spacer 208 , as well as the fifth overlapping structure 209 and the sixth overlapping structure 209 .
  • the overlapping structure 210 is located on the fifth dielectric layer 212 .
  • the length of the dummy gate structure 213 is b.
  • a first dielectric layer and a second dielectric layer are formed on both ends of the dummy gate structure, and the regions in the fifth overlapping structure that are not covered by the dummy gate structure, the first dielectric layer and the second dielectric layer are removed, so as to obtain the first dielectric layer.
  • Materials of the first dielectric layer and the second dielectric layer may be insulating materials such as oxide or silicon nitride.
  • the first overlapping structure 216 and the second overlapping structure 217 are located on both sides of the sidewall 208 , and the first overlapping structure 216 , the second overlapping structure 217 and the The spacers 208 are covered by the dummy gate structure 213 , the first dielectric layer 214 and the second dielectric layer 215 , and the first dielectric layer 214 and the second dielectric layer 215 are located at both ends of the dummy gate structure 213 .
  • the first target material is a material of the first material and the second material that is not used to form the first channel layer; the second target material is a material of the first material and the second material that is not used to form the second channel layer.
  • the first target material and the second target material may be the same or different, which is not specifically limited in this application.
  • the first material is silicon germanium
  • the second material is silicon
  • the first target material is silicon
  • the second target material is silicon germanium
  • the materials of the third dielectric layer and the fourth dielectric layer may be insulating materials such as oxide or silicon nitride, for example.
  • the material of the third dielectric layer and the material of the fourth dielectric layer may be the same or different.
  • the first overlapping structure in which the first target material is removed and the third dielectric layer is formed is named as the third overlapping structure
  • the second overlapping structure in which the second target material is removed and the fourth dielectric layer is formed The structure is named the fourth overlapping structure.
  • first doping structure Form a first doping structure at both ends of the third overlapping structure, and form a second doping structure at both ends of the fourth overlapping structure.
  • the doping types of the first doping structure and the second doping structure are opposite, that is, if the doping type of the first doping structure is N type, the doping type of the second doping structure is P type.
  • the doping type of the heterostructure is P-type, and the doping type of the second doping structure is N-type.
  • a first doped structure may be formed at both ends of the third overlapping structure, and a second doped structure may be formed at both ends of the fourth overlapping structure by means of deposition.
  • the doping may be deposited first and then doping, that is, doping is not performed during the deposition process, or a doping structure corresponding to the doping type may be deposited.
  • the materials of the first doping structure and the second doping structure before doping can be, for example, semiconductor materials such as silicon, germanium, and silicon germanium.
  • the number of the first doping structures 220 is two, which are respectively located at two ends of the third overlapping structure, and the number of the second doping structures 221 is two , respectively located at both ends of the fourth overlapping structure.
  • FIG. 11 is a three-dimensional view. In order to clearly show the structures blocked by the first doping structure 220 and the second doping structure 221 in the figure, the first doping structure 220 and the second doping structure 221 are shown in a translucent manner.
  • FIG. 12 is a plan view of FIG. 11 along a-a' direction. In FIG.
  • the first material 2021 is silicon germanium
  • the second material 2022 is silicon
  • the first target material is the second material, that is, the first target material is silicon
  • the second target material is the first material, that is, the second target material is silicon germanium.
  • the third dielectric layer 222 is located in the region from which the first target material has been removed
  • the fourth dielectric layer 223 is located in the region from which the second target material has been removed.
  • the first field effect transistor is a field effect transistor formed based on the first overlapping structure (ie the fifth overlapping structure), and the second field effect transistor is formed based on the second overlapping structure (ie the sixth overlapping structure). Field effect transistor.
  • the first channel layer is the channel region of the first field effect transistor
  • the second channel layer is the channel region of the second field effect transistor
  • the material of the first channel layer and the material of the second channel layer may be the same or different, which are not particularly limited here. It should be noted that, if the material of the first channel layer and the material of the second channel layer are different, the first channel layer and the second channel layer can be respectively corresponding to the types of field effect transistors. Appropriate materials are selected for the material of the first channel layer and the second channel layer to improve the performance of the field effect transistor.
  • the first channel layer and the second channel layer may or may not be doped, which is not particularly limited here. It should be noted that, if the first channel layer and the second channel layer are doped, the doping type of the first channel layer is opposite to that of the first doping structure, and the doping type of the second channel layer is opposite. The type is opposite to that of the second doping structure.
  • the dummy gate structure needs to be removed, and then the third overlapping structure is removed.
  • the first target material is used to form a plurality of first channel layers, and the second target material in the fourth overlapping structure is removed to form a plurality of second channel layers.
  • the first material 2021 is silicon germanium
  • the second material 2022 is silicon
  • the first target material is silicon
  • the second target material is silicon germanium
  • the first channel layer The material of 224 is silicon germanium
  • the material of the second channel layer 225 is silicon
  • the doping type of the first doping structure 220 is P-type
  • the doping type of the second doping structure is N-type
  • the doping type of the first channel layer Neither 224 nor the second channel layer 225 are doped.
  • the channel type of the field effect transistor formed based on the first overlapping structure is P-type
  • the channel type of the field effect transistor formed based on the second overlapping structure is N-type.
  • silicon germanium material helps to improve the performance of the P-type field effect transistor
  • the channel layer made of silicon material helps to improve the performance of the N-type field effect transistor, therefore, silicon is selected as the second channel layer.
  • silicon germanium is selected as the material of the first channel layer 224, so as to improve the performance of the field effect transistor formed based on the first overlapping structure and the field effect transistor formed based on the second overlapping structure.
  • FIG. 13 is a schematic structural diagram of the first channel layer and the second channel layer formed on the basis of the cross-sectional view taken along the A-A' direction in FIG. 11 . Since FIG. 13 is a perspective view, the second doping structure is blocked by other structures.
  • Form a first gate insulating layer on the first channel layer form a second gate insulating layer on the second channel layer, and form a first gate conductive layer on the first gate insulating layer, and form a first gate insulating layer on the second gate insulating layer
  • a second gate conductive layer is formed on the layer.
  • the materials of the first gate insulating layer and the second gate insulating layer may be silicon dioxide or high-k materials (eg, ZrO 2 , HfO 2 , Al 2 O 3 , etc.), etc., which are not particularly limited here.
  • the materials of the first gate conductive layer and the second gate conductive layer can be, for example, metal materials or heavily doped polysilicon, etc., which are not particularly limited here.
  • the materials of the first gate insulating layer and the second gate insulating layer may be the same or different, and the materials of the first gate conductive layer and the second gate conductive layer may be the same or different. If the materials of the first gate insulating layer and the second gate insulating layer are the same and/or the materials of the first gate conductive layer and the second gate conductive layer are the same, the manufacturing process can be simplified and the manufacturing cost can be saved.
  • a first gate insulating layer is formed on the exposed surface of the first channel layer 224
  • a second gate insulating layer is formed on the exposed surface of the second channel layer 225 .
  • the exposed surface of the first channel layer 224 is the surface of the first channel layer 224 that is not in contact with other structures
  • the exposed surface of the second channel layer 225 is the surface of the second channel layer 225 that is not in contact with other structures, and depositing a first gate conductive layer on a surface of the first gate insulating layer away from the first channel layer, and depositing a second gate conductive layer on a surface of the second gate insulating layer away from the second channel layer. It should be noted that, in FIG.
  • the first gate insulating layer and the first gate conductive layer are not shown separately, that is, 227 in FIG. 14 is used to indicate the combination of the first gate insulating layer and the first gate conductive layer
  • the second gate insulating layer and the second gate conductive layer are not shown separately, that is, 228 in FIG. 14 is used to indicate the combination of the second gate insulating layer and the second gate conductive layer.
  • the first gate insulating layer and the first gate conductive layer are also formed on the sidewalls. In order to simplify the manufacturing process, it is not necessary to remove them.
  • the first gate insulating layer and the first gate conductive layer on the sidewalls.
  • the second gate insulating layer and the second gate conductive layer also have the same situation, which will not be repeated here.
  • the semiconductor device fabricated by the above process includes two field effect transistors, namely a first field effect transistor and a second field effect transistor, wherein: the first field effect transistor includes a plurality of first channel layers, a first field effect transistor A doping structure, a first gate insulating layer and a first gate conductive layer.
  • the plurality of first channel layers are the channel regions of the first field effect transistor, the first gate insulating layer and the first gate conductive layer constitute the gate of the first field effect transistor, and the first doping structure constitutes the first field source and drain regions of effect transistors.
  • the second field effect transistor includes a plurality of second channel layers, a second doping structure, a second gate insulating layer and a second gate conductive layer.
  • the plurality of second channel layers are channel regions of the second field effect transistor, the second gate insulating layer and the second gate conductive layer constitute the gate of the second field effect transistor, and the second doping structure constitutes the second field source and drain regions of effect transistors.
  • the metal contact effect of the conductive layers of the gate electrodes in the first field effect transistor and the second field effect transistor can be eliminated, that is, the Metal gate contact effect.
  • the channel types of the first field effect transistor and the second field effect transistor are opposite. That is, if the doping type of the first doping structure is N type and the doping type of the second doping structure is P type, the channel type of the first field effect transistor is N type, and the channel type of the second field effect transistor is N type.
  • the type is P-type; that is, if the doping type of the first doping structure is P-type and the doping type of the second doping structure is N-type, the channel type of the first field effect transistor is P-type, and the second field-effect transistor The channel type of the effect transistor is N-type.
  • the Electrode structures 229 are formed on the first gate conductive layer and the second gate conductive layer.
  • the electrode structure 229 is also used to fill the gaps between adjacent first gate conductive layers and the gaps between adjacent second gate conductive layers.
  • the material of the electrode structure 229 includes but is not limited to metal materials such as aluminum and silver.
  • an isolation layer 230 may also be formed on the electrode structures 229 by means of deposition.
  • the material of the isolation layer 230 may be, for example, an insulating material such as oxide and silicon nitride, which is not particularly limited in this embodiment of the present application.
  • the first dielectric layer and the fifth dielectric layer may also be replaced with air.
  • the semiconductor device includes:
  • a plurality of second channel layers 225 are sequentially arranged on the other side of the sidewall spacer 208, wherein the first channel layer 224 extends along the sidewall of the sidewall 208, and the second channel layer 225 Extending along the side surfaces of the spacers 208, the first doping structures 220 disposed at both ends of the plurality of first channel layers 224, and the second doping structures 220 disposed at both ends of the plurality of second channel layers 225 (in FIG.
  • the doping type of the first doping structure 220 is opposite to that of the second doping structure, covering one end of the first surface of the plurality of first channel layers 224 and the plurality of second channel layers 225 A first dielectric layer (not shown in FIG.
  • the first surface of the plurality of first channel layers 224 covers the other ends of the first surfaces of the plurality of first channel layers 224 and the first surfaces of the plurality of second channel layers 225 the second dielectric layer 215 at the other end, wherein the first surfaces of the plurality of first channel layers 224 are the surfaces of the plurality of first channel layers 224 away from the sidewall spacers 208, The first surface is the surface of the plurality of second channel layers 225 away from the sidewall spacers 208 , and the third dielectric layer (not shown in FIG. 15 ) is disposed on both ends of the second surfaces of the plurality of first channel layers 224 , A fourth dielectric layer (not shown in FIG.
  • the second surfaces of the plurality of first channel layers 224 are a plurality of first trenches
  • the surface of the channel layer 224 adjacent to its first surface and parallel to the substrate 201, the second surface of the plurality of second channel layers 224 is the second surface of the plurality of second channel layers 224 adjacent to its first surface and parallel to the substrate the surface parallel to the bottom 201; the first gate insulating layer and the first gate conductive layer are sequentially arranged on the first channel layer 224, and the second gate insulating layer and the second gate conductive layer are sequentially arranged on the second channel layer 225 layer.
  • the first gate insulating layer and the first gate conductive layer are not shown separately, that is, 227 in FIG. 15 is used to indicate the combination of the first gate insulating layer and the first gate conductive layer
  • the second gate insulating layer and the second gate conductive layer are not shown separately, that is, 228 in FIG. 15 is used to indicate the combination of the second gate insulating layer and the second gate conductive layer.
  • the semiconductor device includes two field effect transistors, namely the first field effect transistor and the second field effect transistor, and the first field effect transistor and the second field effect transistor are respectively located on both sides of the sidewall.
  • the plurality of first channel layers are used as the channel regions of the first field effect transistors
  • the first doping structure is used as the source and drain regions of the first field effect transistors
  • the first gate insulating layer and the first gate conductive layer are used as the first
  • the gate region of the field effect transistor, the first dielectric layer, the second dielectric layer and the third dielectric layer isolate the gate region and the source and drain regions of the first field effect transistor.
  • a plurality of second channel layers are used as channel regions of the second field effect
  • the second doping structure is used as the source and drain regions of the second field effect transistor
  • the second gate insulating layer and the second gate conductive layer are used as the second field effect transistor.
  • the gate region, the first dielectric layer, the second dielectric layer and the fourth dielectric layer isolate the gate region and the source and drain regions of the second field effect transistor.
  • the doping type of the first doping structure 220 is opposite to that of the second doping structure, that is, the channel types of the first field effect transistor and the second field effect transistor are opposite. That is, if the doping type of the first doping structure 220 is N-type (that is, the channel type of the first field effect transistor is N-type), the doping type of the second doping structure is P-type (that is, the second field-effect transistor is the doping type The channel type of the effect transistor is P-type); if the doping type of the first doping structure 220 is P-type (that is, the channel type of the first field effect transistor is P-type), the doping type of the second doping structure is P-type The type is N-type (ie, the channel type of the second field effect transistor is N-type).
  • the materials of the first channel layer 224 and the second channel layer 225 are different, the first channel layer 224 and the second channel layer 225 are not on the same plane, and the first channel layer 224 has different materials.
  • the upper surface is level with the lower surface of the second channel layer 225 .
  • the first channel layer and the second channel layer may be respectively the type of field effect transistor corresponding to the first channel layer and the second channel layer.
  • Appropriate materials are selected for the channel layer and the second channel layer to improve the performance of the field effect transistor, thereby improving the driving performance of the semiconductor device.
  • the doping type of the first doping structure is P-type, that is, the channel type of the first field effect transistor is P-type
  • the doping type of the second doping structure is N-type type, that is, the channel type of the second field effect transistor is N type
  • the channel layer made of silicon material helps to improve the performance of the P-type field effect transistor.
  • silicon germanium is selected as the material of the first channel layer
  • silicon is selected as the material of the second channel layer.
  • the materials of the first channel layer 224 and the second channel layer 225 may also be the same.
  • the materials of the first gate insulating layer and the second gate insulating layer may be the same or different, which are not particularly limited in this embodiment of the present application.
  • the materials of the first gate conductive layer and the second gate conductive layer may be the same or different, which are not particularly limited in this embodiment of the present application.
  • the first field effect transistor and the second field effect transistor have different VT (threshold voltage), and the VT of the field effect transistor can be understood as the gate conduction The difference between the work function of the layer and the Fermi level of the channel layer.
  • the VT of the first field effect transistor that is, the difference between the work function of the first gate conductive layer and the Fermi level of the first channel layer
  • the VT of the second field effect transistor that is, the first
  • the first value and the second value are different.
  • the first value is related to the channel type of the first field effect transistor, the structure of the first field effect transistor, and the parameters of each part of the first field effect transistor.
  • the second value is related to the channel of the second field effect transistor. The type, the structure of the second field effect transistor and the parameters of each part of the second field effect transistor are related.
  • the channel type of the field effect transistor is N type, the difference between the work function of the gate conductive layer and the Fermi level of the channel layer is greater than 0. If the channel type of the field effect transistor is P type , the difference between the work function of the gate conductive layer and the Fermi level of the channel layer is less than 0.
  • the VT of the field effect transistor (ie, the difference between the work function of the gate conductive layer and the Fermi level of the channel layer) can meet the requirements by at least one of the following four methods. in:
  • the Fermi level of the channel layer is changed.
  • the Fermi level of the channel layer is changed by adjusting the ratio of each component in the semiconductor compound.
  • the material of the gate insulating layer is a high-k material, then by selecting an appropriate high-k material of the gate insulating layer and/or changing the fabrication process of the gate insulating layer (such as annealing conditions, etc.) work function is affected.
  • the gate conductive layer is made by selecting a metal material corresponding to the work function to obtain a gate conductive layer that meets the work function requirements, and if the material of the gate conductive layer is heavily doped For doped polysilicon, the work function of the gate conductive layer is changed by changing the doping type and concentration of the polysilicon.
  • the work function of the gate conductive layer and/or the Fermi level of the channel layer can be adjusted by at least one of the above four methods, so that the VT of the field effect transistor can meet the requirements.
  • the Fermi levels of the first channel layer and the second channel layer are adjusted by at least one of the following two methods, so that the first gate conductive layer has a
  • the difference between the work function and the Fermi level of the first channel layer is a first value
  • the difference between the work function of the second gate conductive layer and the Fermi level of the second channel layer is a second value, that is, we get
  • the VT of the first field effect transistor and the VT of the second field effect transistor meet the requirements, where:
  • Mode 1 If the material of the first channel layer and/or the material of the second channel layer is a semiconductor compound, adjust the composition ratio of the semiconductor compound.
  • Mode 2 Adjust the doping type and doping concentration of the first channel layer and the second channel layer.
  • the materials of the first gate insulating layer and the second gate insulating layer are the same, and the materials of the first gate conductive layer and the second gate conductive layer are the same, that is, the first field effect transistor and the second field effect transistor share the same material
  • the Fermi energy levels of the first channel layer and the second channel layer are adjusted in the above manner, so that the VT of the first field effect transistor and the VT of the second field effect transistor meet the requirements .
  • the first field effect transistor and the second field effect transistor share the gate conductive layer and the gate insulating layer, the metal contact effect of the gates of the first field effect transistor and the second field effect transistor is eliminated, that is, the metal gate contact The effect is improved, the performance of the device is improved, and the fabrication process of the semiconductor device is also simplified.
  • the Fermi levels of the first channel layer and the second channel layer are adjusted in the above-mentioned manner, so that the VT of the first field effect transistor and the VT of the second field effect transistor meet the requirements by means of the energy band difference, thereby making the first field effect transistor meet the requirements.
  • the field effect transistor and the second field effect transistor can share the gate insulating layer and the gate conductive layer.
  • FIG. 16 is an energy band diagram of the first field effect transistor and the second field effect transistor.
  • the first field effect transistor is a P-channel field effect transistor
  • the second field effect transistor is an N-channel field effect transistor
  • the material of the first channel layer is silicon germanium
  • the material of the second channel layer is silicon germanium.
  • the material is silicon
  • the first gate conductive layer and the second gate conductive layer use the same material
  • the first gate insulating layer and the second gate insulating layer use the same material.
  • the materials of the first gate conductive layer and the second gate conductive layer can be determined according to the Fermi level of the second channel layer (the Fermi level of silicon), so that the first gate conductive layer and the second gate conductive layer are The work function WF of the gate conductive layer is greater than the Fermi level Efn of the second channel layer, and the VT of the second field effect transistor is the second value. Then, by adjusting the silicon germanium composition, the first channel layer is changed.
  • the Fermi level Efp is such that the Fermi level Efp of the first channel layer is greater than the work function WF of the first gate conductive layer and the second gate conductive layer, and the VT of the first field effect transistor is a first value.
  • Ecp in FIG. 16 is the conduction band of the first channel layer
  • Evp is the valence band of the first channel layer
  • Ecn is the conduction band of the second channel layer
  • Evn is the valence band of the second channel layer.
  • the materials of the first gate conductive layer and the second gate conductive layer are the same, at least one of the following three methods can be used to make the work function of the first gate conductive layer and the first channel layer
  • the difference between the Fermi levels of is a first value
  • the difference between the work function of the second gate conductive layer and the Fermi level of the second channel layer is a second value
  • Method 1 The materials of the first gate insulating layer and the second gate insulating layer are high-k materials, and the type of the high-k material and/or the first gate insulating layer corresponding to the first gate insulating layer and the second gate insulating layer respectively is adjusted. layer and the fabrication process of the second gate insulating layer (eg, annealing temperature, time, etc.).
  • Mode 2 If the material of the first channel layer and/or the material of the second channel layer is a semiconductor compound, adjust the composition ratio of the semiconductor compound.
  • Mode 3 Adjust the doping type and doping concentration of the first channel layer and the second channel layer.
  • the first channel is adjusted by the above method.
  • the metal contact effect of the gates of the first field effect transistor and the second field effect transistor is eliminated, the device performance is improved, and the semiconductor is simplified. device fabrication process.
  • the Fermi level of the first channel layer and the second channel layer and/or the work function of the first gate conductive layer and the work function of the second gate conductive layer are adjusted in the above-mentioned manner, so that the The VT of the field effect transistor and the VT of the second field effect transistor meet the requirements, so that the first field effect transistor and the second field effect transistor can share the gate conductive layer.
  • the work function of the first gate conductive layer and the Fermi energy of the first channel layer can be adjusted by at least one of the following three methods, under the condition that the materials of the first gate insulating layer and the second gate insulating layer are the same.
  • the difference between the levels is a first value
  • the difference between the work function of the second gate conductive layer and the Fermi level of the second channel layer is a second value, where:
  • the first way is to adjust the doping type and doping concentration of the first channel layer and the second channel layer.
  • the composition ratio of the semiconductor compound is adjusted.
  • Mode 3 Select appropriate metal materials of the first gate conductive layer and the second gate conductive layer or adjust the first gate conductive layer and the second gate conductive layer (if the first gate conductive layer and the second gate conductive layer are heavily doped of polysilicon) doping type and concentration.
  • the Fermi level and/or the third channel layer of the first channel layer and the second channel layer are adjusted by the above method.
  • the work function of the first gate conductive layer and the work function of the second gate conductive layer make the VT of the first field effect transistor and the VT of the second field effect transistor meet the requirements.
  • the fabrication process of the semiconductor device is simplified.
  • the semiconductor device further includes a first field effect transistor and a second field effect transistor.
  • Five dielectric layers 212, the fifth dielectric layer 212 is located between the substrate 201 and the field effect transistor, that is, the fifth dielectric layer 212 is located on the substrate 201, and a plurality of first channel layers 224, a plurality of second channel layers
  • the layer 225 , the first doped structure 220 and the second doped structure are located on the fifth dielectric layer 212 .
  • the semiconductor device further includes an electrode structure 229, and the electrode structure 229 is located on the first gate conductive layer and the second gate conductive layer, and is used for The first gate conductive layer and the second gate conductive layer are communicated.
  • the semiconductor device further includes an isolation layer 230 covering the electrode structures 229 .
  • the isolation layer 230 is provided with an opening, so that the electrode structure 229 can be drawn out from the opening.
  • FIG. 15 is only a structure of the semiconductor device fabricated by the first process flow, and is not used to limit the present application.
  • the process of the second technological process is as follows:
  • first process flow is the same as the second process flow in forming a plurality of first channel layers and a plurality of second channel layers and the processes before it, therefore, only the formation of a plurality of first channel layers in the second process is described below.
  • the process after one channel layer and multiple second channel layers is described, as follows:
  • the spacer between the first dielectric layer and the second dielectric layer is removed by etching.
  • the structure after removing the spacer between the first dielectric layer and the second dielectric layer is shown in FIG. 17 .
  • a gate insulating layer is formed on the first channel layer and the second channel layer by means of deposition. Specifically, a gate insulating layer is deposited on the exposed surface of the first channel layer and the exposed surface of the second channel layer. Since the exposed surfaces of the first channel layer and the second channel layer have been described above, they will not be repeated here.
  • the material of the insulating layer can be, for example, silicon dioxide or high-k material (eg, ZrO 2 , HfO 2 , Al 2 O 3 , etc.), etc., which are not particularly limited here.
  • a gate conductive layer is formed on the gate insulating layer by means of deposition.
  • the material of the gate conductive layer can be, for example, a metal material, heavily doped polysilicon, etc., which is not particularly limited here.
  • a gate-all-around structure can be formed, that is, the gate region formed by the gate insulating layer and the gate conductive layer covers the four sides of the first channel layer and the second channel layer, thereby improving the gate driving capability of the device.
  • FIG. 18 a semiconductor device in which a gate insulating layer and a gate conductive layer are sequentially formed on the first channel layer and the second channel layer is shown in FIG. 18 .
  • the gate insulating layer and the gate conductive layer form a gate-all-around structure on the first channel layer 224 and the second channel layer 225 .
  • the gate insulating layer and the gate conductive layer are not shown separately in FIG. 18 , that is, 231 in FIG. 18 is used to indicate the combination of the gate insulating layer and the conductive layer.
  • the semiconductor device includes two field effect transistors, namely the first field effect transistor and the second field effect transistor, wherein a plurality of first channel layers are used as the channel regions of the first field effect, and the first doping
  • the structure serves as the source and drain regions of the first field effect transistor, the gate insulating layer and the gate conductive layer serve as the gate region of the first field effect transistor, and the first dielectric layer, the second dielectric layer and the third dielectric layer connect the first field effect transistor.
  • the gate region and the source-drain region are isolated.
  • the plurality of second channel layers are used as channel regions of the second field effect
  • the second doping structure is used as the source and drain regions of the second field effect transistor
  • the gate insulating layer and the gate conductive layer are also used as the gate of the second field effect transistor region
  • the first dielectric layer, the second dielectric layer and the fourth dielectric layer isolate the gate region and the source and drain regions of the second field effect transistor.
  • the process is simplified, and the metal contact between the gates of the first field effect transistor and the second field effect transistor can also be eliminated. effect.
  • the spacers are removed, the exposed areas of the first channel layer and the second channel layer are increased, thereby increasing the coverage areas of the gate insulating layer and the gate conductive layer, thereby increasing the gate control capability of the device.
  • the fifth dielectric layer 212 , the electrode structure 229 and the isolation layer 230 may also be formed. Since the fifth dielectric layer 212 and the electrode structure are formed The purpose and principle of 229 and the isolation layer 230 are the same as those in the first process flow, so they will not be repeated here.
  • the spacer 208 between the first dielectric layer and the second dielectric layer 215 is removed, and a first gate insulating layer and a first gate conductive layer are sequentially provided on the surface of the first channel layer 224 in contact with the removed spacer 208 layer, a second gate insulating layer and a second gate conductive layer are sequentially disposed on the surface of the second channel layer 225 in contact with the removed spacers 208, wherein the materials of the first gate insulating layer and the second gate insulating layer are the same , the materials of the first gate conductive layer and the second gate conductive layer are the same.
  • the first gate insulating layer and the second gate insulating layer are collectively referred to as gate insulating layers. Since the materials of the first gate conductive layer and the second gate conductive layer are the same, the first gate conductive layer and the second gate conductive layer are collectively referred to as gate conductive layers. Based on this, in FIG. 19 , the gate insulating layer and the conductive layer are not shown separately, that is, 231 in FIG. 19 is used to indicate the combination of the gate insulating layer and the conductive layer.
  • the gate-all-around structure includes the first channel layer and the first channel layer.
  • a gate insulating layer and a first gate conductive layer and a gate-all-around structure is formed on the second channel layer (the gate-all-around structure includes a second gate insulating layer and a second gate conductive layer) to increase the gate driving capability of the device.
  • the materials of the first gate insulating layer and the second gate insulating layer are the same, the materials of the first gate conductive layer and the second gate conductive layer are the same, so that the first field effect transistor and the second field effect transistor form a common gate
  • the structure simplifies the technological process and reduces the manufacturing cost.
  • the first field effect transistor and the second field effect transistor have different VT (threshold voltage), and the VT of the field effect transistor can be understood as the gate conduction
  • VT threshold voltage
  • the VT of the field effect transistor can be understood as the gate conduction
  • the VT of the first field effect transistor (the difference between the work function of the gate conductive layer and the Fermi level of the first channel layer) is the first value
  • the VT of the second field effect transistor (the work function of the gate conductive layer)
  • the difference from the Fermi level of the second channel layer) is a second value, and the first value and the second value are different.
  • the gate insulating layer and the gate conductive layer are shared by the first field effect transistor and the second field effect transistor. Therefore, at least one of the following two methods can be used.
  • the difference between the work function of the gate conductive layer (ie the first gate conductive layer) and the Fermi level of the first channel layer is a first value
  • the work function of the gate conductive layer (ie the second gate conductive layer) is a second value, where:
  • Mode 1 If the material of the first channel layer and/or the material of the second channel layer is a semiconductor compound, adjust the composition ratio of the semiconductor compound.
  • Mode 2 Adjust the doping type and doping concentration of the first channel layer and the second channel layer.
  • the Fermi levels of the first channel layer and the second channel layer are adjusted in the above manner, so that the first The VT of the field effect transistor and the VT of the second field effect transistor meet the requirements.
  • the first field effect transistor and the second field effect transistor share the gate conductive layer and the gate insulating layer, the metal contact effect of the gates of the first field effect transistor and the second field effect transistor is eliminated, the device performance is improved, and at the same time The fabrication process of the semiconductor device is also simplified.
  • the Fermi levels of the first channel layer and the second channel layer are adjusted in the above-mentioned manner, so that the VT of the first field effect transistor and the VT of the second field effect transistor meet the requirements by means of the energy band difference, thereby making the first field effect transistor meet the requirements.
  • the field effect transistor and the second field effect transistor can share the gate insulating layer and the gate conductive layer.
  • the above-mentioned semiconductor device further includes The fifth dielectric layer 212, the fifth dielectric layer 212 is located between the substrate 201 and the field effect transistor, that is, the fifth dielectric layer 212 is located on the substrate 201, and has a plurality of first channel layers 224 and a plurality of second channel layers.
  • the channel layer 225 , the first doping structure 220 and the second doping structure are located on the fifth dielectric layer 212 .
  • the semiconductor device further includes an electrode structure 229 located on the gate conductive layer.
  • the semiconductor device further includes an isolation layer 230 covering the electrode structures 229 . It should be noted that the isolation layer 230 is provided with an opening, so that the electrode structure 229 can be drawn out from the opening.

Abstract

一种形成叉型结构中侧墙的方法，包括：提供衬底（201）；在衬底（201）上形成第一材料（2021）和第二材料（2022）依次层叠的交叠层（202）；在交叠层（202）上形成第一掩膜层（203）；在第一掩膜层（203）中形成第一沟槽（205）；通过在第一掩膜层（203）上和第一沟槽（205）内形成第二掩膜层（206）的方式，在第一沟槽（205）中形成第二沟槽；采用各向异性的刻蚀方式沿着与衬底（201）垂直的方向刻蚀第二掩膜层（206），直至去除位于第二沟槽的侧壁之间且位于第一沟槽（205）的下表面上的第二掩膜层（206），以基于第二沟槽形成第三沟槽（207）；以第二掩膜层（206）作为保护层，从第三沟槽（207）的下表面开始向下刻蚀，形成贯穿交叠层（202）并延伸至衬底（201）中的第四沟槽；在第四沟槽中形成侧墙（208）。所述方法降低了在形成侧墙（208）的过程中对光刻精度和光刻能力的要求。

Description

形成叉型结构中侧墙的方法和叉型结构的半导体器件 技术领域
本申请涉及半导体技术领域，尤其涉及一种形成叉型结构中侧墙的方法和一种叉型结构的半导体器件。
背景技术
随着集成电路工艺的持续演进，新工艺和新结构不断被提出。2019年IMEC提出了forksheet(叉型)结构，由于其可以有效减小NMOS(N-Metal-Oxide-Semiconductor，N型金属-氧化物-半导体)与PMOS(P-Metal-Oxide-Semiconductor，P型金属-氧化物-半导体)之间的距离，从而减小标准单元的面积，因此被认为是下一代先进工艺的潜在方向。
现有的forksheet结构包括：侧墙，位于侧墙两侧的NMOS和PMOS。由于侧墙的宽度较小，因此减小了NMOS与PMOS之间的距离。目前形成侧墙的原理为：首先形成交叠层，通过光刻在交叠层中形成沟槽，以及填充沟槽形成侧墙。
由于通过填充沟槽的方式形成侧墙，而沟槽的宽度由光刻决定，因此，侧墙的宽度同样由光刻决定。又由于侧墙的宽度比较小，因此上述形成侧墙的方式对光刻精度和光刻能力要求较高。
发明内容
本申请提供了一种形成叉型结构中侧墙的方法和一种叉型结构的半导体器件，用于解决形成侧墙的方式对光刻精度和光刻能力要求较高的问题。
第一方面，本申请一种形成叉型结构中侧墙的方法，包括：提供衬底；在所述衬底上形成第一材料和第二材料依次层叠的交叠层；在所述交叠层上形成第一掩膜层；在所述第一掩膜层中形成第一沟槽；通过在所述第一掩膜层上和所述第一沟槽内形成第二掩膜层的方式，在所述第一沟槽中形成第二沟槽；采用各向异性的刻蚀方式沿着与所述衬底垂直的方向刻蚀所述第二掩膜层，直至去除位于所述第二沟槽的侧壁之间且位于所述第一沟槽的下表面上的所述第二掩膜层，以基于所述第二沟槽形成第三沟槽；以所述第二掩膜层作为保护层，从所述第三沟槽的下表面开始向下刻蚀，形成贯穿所述交叠层并延伸至所述衬底中的第四沟槽；在所述第四沟槽中形成侧墙。
由于在第四沟槽中形成侧墙，因此，侧墙的宽度由第四沟槽的宽度决定，而第四沟槽的形成原理是通过在第一掩膜层中形成第一沟槽，以及通过在第一沟槽中形成第二掩膜层的方式在第一沟槽中形成第二沟槽，并通过各向异性的刻蚀方式沿着垂直衬底的方向去除位于第二沟槽的侧壁之间且位于第一沟槽的下表面上的第二掩膜层，以得到第三沟槽，以及在第二掩膜层的保护下，从第三沟槽的下表面开始向下刻蚀，形成贯穿交叠层并延伸至衬底中的第四沟槽，即在第四沟槽的形成过程中，仅在第一沟槽的形成过程中使用了光刻工艺，又由于第四沟槽在第一沟槽内形成，因此，第一沟槽的宽度大于第四沟槽的宽度， 即第一沟槽的宽度相对较大，这样，在形成第一沟槽的过程中，降低了对于光刻精度和光刻能力的要求，进而在形成侧墙的过程中，降低了对于光刻精度和光刻能力的要求。
在一种可能的实现方式中，所述方法还包括：在所述侧墙两侧形成第一交叠结构和第二交叠结构，其中，所述第一交叠结构、所述第二交叠结构和所述侧墙上覆盖有第一介质层和第二介质层，所述第一介质层的一端与所述第一交叠结构和所述第二交叠结构的一端持平，所述第二介质层的一端与所述第一交叠结构和所述第二交叠结构的另一端持平，所述第一介质层的另一端与所述第二介质层的另一端相距一预设距离；去除所述第一交叠结构中被所述第一介质层和所述第二介质层覆盖的第一目标材料，去除所述第二交叠结构中被所述第一介质层和所述第二介质层覆盖的第二目标材料；在去除所述第一目标材料的区域中形成第三介质层，以得到第三交叠结构；在去除所述第二目标材料的区域中形成第四介质层，以得到第四交叠结构；在所述第三交叠结构的两端形成第一掺杂结构，在所述第四交叠结构的两端形成第二掺杂结构；去除所述第三交叠结构中的第一目标材料，以形成多个第一沟道层；去除所述第四交叠结构中的第二目标材料，以形成多个第二沟道层；其中，所述第一目标材料为所述第一材料和所述第二材料中不用于形成所述第一沟道层的材料；所述第二目标材料为所述第一材料和所述第二材料中不用于形成所述第二沟道层的材料，所述第一掺杂结构和所述第二掺杂结构的掺杂类型相反。
在一种可能的实现方式中所述方法还包括：在所述第一沟道层上形成第一栅绝缘层，在所述第二沟道层上形成第二栅绝缘层；在所述第一栅绝缘层上形成第一栅导电层，在所述第二栅绝缘层上形成第二栅导电层。
在一种可能的实现方式中所述第一栅绝缘层和所述第二栅绝缘层的材料相同，所述第一栅导电层和所述第二栅导电层的材料相同；或者所述第一栅导电层和所述第二栅导电层的材料相同。
在一种可能的实现方式中，所述方法还包括：去除位于所述第一介质层和所述第二介质层之间的所述侧墙；在所述第一沟道层和所述第二沟道层上形成栅绝缘层；在所述栅绝缘层上形成栅导电层。
在一种可能的实现方式中，所述在所述侧墙两侧形成第一交叠结构和第二交叠结构包括：通过去除待去除掩膜层以及位于所述待去除掩膜层下方的交叠层，形成位于所述侧墙两侧的第五交叠结构和第六交叠结构，其中，所述待去除掩膜层为位于所述第一沟槽的侧壁外的第一掩膜层；形成覆盖所述第五交叠结构、所述第六交叠结构和所述侧墙的假栅结构，其中，所述假栅结构的长度与所述预设距离相等；在所述假栅结构的两端形成所述第一介质层和所述第二介质层；去除所述第五交叠结构中未被所述假栅结构、所述第一介质层和所述第二介质层覆盖的区域，以得到所述第一交叠结构；去除所述第六交叠结构中未被所述假栅结构、所述第一介质层和所述第二介质层覆盖的区域，以得到所述第二交叠结构。
在一种可能的实现方式中，在形成所述多个第一沟道层和所述多个第二沟道层之前还包括：去除所述假栅结构。
在一种可能的实现方式中，所述方法还包括：在所述衬底上形成第五介质层，所述多个第一沟道层、所述多个第二沟道层、所述第一掺杂结构和所述第二掺杂结构位于所述第五介质层上。
在一种可能的实现方式中，所述第一沟道层和所述第二沟道层的材料不同。
在一种可能的实现方式中，所述第一掺杂结构为P型掺杂，所述第二掺杂结构为N型掺杂，所述第一沟道层的材料为硅锗，所述第二沟道层的材料为硅。
第二方面，本申请提供一种叉型结构的半导体器件，包括：衬底；垂直设置在所述衬底上的侧墙；沿着与所述衬底垂直的方向依次间隔设置在所述侧墙的一个侧面上的多个第一沟道层，所述第一沟道层沿着所述侧墙的侧面延伸；沿着与所述衬底垂直的方向依次间隔设置在所述侧墙的另一个侧面上的多个第二沟道层，所述第二沟道层沿着所述侧墙的侧面延伸；设置在所述多个第一沟道层两端的第一掺杂结构，设置在所述多个第二沟道层两端的第二掺杂结构，所述第一掺杂结构的掺杂类型与所述第二掺杂结构的掺杂类型相反；覆盖在所述多个第一沟道层的第一表面的一端和所述多个第二沟道层的第一表面的一端的第一介质层，覆盖在所述多个第一沟道层的第一表面的另一端和所述多个第二沟道层的第一表面的另一端的第二介质层，其中，所述多个第一沟道层的第一表面为所述多个第一沟道层中远离所述侧墙的表面，所述多个第二沟道层的第一表面为所述多个第二沟道层中远离所述侧墙的表面；设置在所述多个第一沟道层的第二表面的两端的第三介质层，设置在所述多个第二沟道层的第二表面的两端的第四介质层，其中，所述多个第一沟道层的第二表面为所述多个第一沟道层中与其第一表面相邻且与所述衬底平行的表面，所述多个第二沟道层的第二表面为所述多个第二沟道层中与其第一表面相邻且与所述衬底平行的表面；依次设置在所述第一沟道层上的第一栅绝缘层和第一栅导电层，依次设置在所述第二沟道层上的第二栅绝缘层和第二栅导电层。
在一种可能的实现方式中，其特征在于，所述半导体器件还包括：位于所述衬底上的第五介质层，所述多个第一沟道层、所述多个第二沟道层、所述第一掺杂结构和所述第二掺杂结构位于所述第五介质层上。
在一种可能的实现方式中，所述第一栅绝缘层和所述第二栅绝缘层的材料相同，所述第一栅导电层和所述第二栅导电层的材料相同；或者所述第一栅导电层和所述第二栅导电层的材料相同。
在一种可能的实现方式中，位于所述第一介质层与所述第二介质层之间的侧墙被去除；所述第一沟道层中与去除的所述侧墙接触的表面上依次设置有所述第一栅绝缘层和第一栅导电层；所述第二沟道层中与去除的所述侧墙接触的表面上依次设置有所述第二栅绝缘层和第二栅导电层；所述第一栅绝缘层和所述第二栅绝缘层的材料相同，所述第一栅导电层和所述第二栅导电层的材料相同。
在一种可能的实现方式中，所述第一沟道层与所述第二沟道层的材料不同。
在一种可能的实现方式中，所述第一掺杂结构为P型掺杂，所述第二掺杂结构为N型掺杂，所述第一沟道层的材料为硅锗，所述第二沟道层的材料为硅。
附图说明
图1为本申请实施例提供的形成侧墙的流程示意图；
图2为本申请实施例提供的形成衬底、交叠层和第一掩膜层后的结构示意图；
图3为本申请实施例提供的形成第一沟槽后的结构示意图；
图4为本申请实施例提供的形成第三沟槽后的结构示意图；
图5为本申请实施例提供的形成侧墙后的结构示意图；
图6为本申请实施例提供的第一种工艺的流程示意图；
图7为本申请实施例提供的形成第五交叠结构和第六交叠结构后的结构示意图；
图8为本申请实施例提供的形成间隙后的结构示意图；
图9为本申请实施例提供的形成假栅结构后的结构示意图；
图10为本申请实施例提供的形成第一交叠结构和第二交叠结构后的结构示意图；
图11为本申请实施例提供的形成第一掺杂结构和第二掺杂结构后的结构示意图；
图12为图11沿着a-a’方向的刨面图；
图13为本申请实施例提供的形成第一沟道层和第二沟道层后的结构示意图；
图14为本申请实施例提供的形成第一栅绝缘层、第二栅绝缘层、第一栅导电层和第二栅导电层后的结构示意图；
图15为本申请实施例提供的形成电极结构和隔离层的结构示意图；
图16为第一场效应晶体管和第二场效应晶体管的能带图；
图17为本申请实施例提供的去除第一介质层和第二介质层之间的侧墙后的结构示意图；
图18为本申请实施例提供的形成栅绝缘层和栅导电层后的结构示意图；
图19为本申请实施例提供的形成第五介质层、电极结构和隔离层后的结构示意图。
具体实施方式
下面将结合附图，对本申请中的技术方案进行描述。
为使本申请的目的、技术方案和优点更加清楚，下面将结合本申请中的附图，对本申请中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
本申请的说明书实施例和权利要求书及附图中的术语“第一”、“第二”等仅用于区分描述的目的，而不能理解为指示或暗示相对重要性，也不能理解为指示或暗示顺序。此外，术语“包括”和“具有”以及他们的任何变形，意图在于覆盖不排他的包含，例如，包含了一系列步骤或单元。方法、系统、产品或设备不必限于清楚地列出的那些步骤或单元，而是可包括没有清楚地列出的或对于这些过程、方法、产品或设备固有的其它步骤或单元。
应当理解，在本申请中，“至少一个(项)”是指一个或者多个，“多个”是指两个或两个以上。“和/或”，用于描述关联对象的关联关系，表示可以存在三种关系，例如，“A和/或B”可以表示：只存在A，只存在B以及同时存在A和B三种情况，其中A，B可以是单数或者复数。字符“/”一般表示前后关联对象是一种“或”的关系。“以下至少一项(个)”或其类似表达，是指这些项中的任意组合，包括单项(个)或复数项(个)的任意组合。例如，a，b或c中的至少一项(个)，可以表示：a，b，c，“a和b”，“a和c”，“b和c”，或“a和b和c”，其中a，b，c可以是单个，也可以是多个。
为了解决上述技术问题，本申请提供了一种形成叉型结构中侧墙的方法。图1为本申 请实施例提供的形成侧墙的流程示意图，如图1所示，该方法包括：
101、提供衬底。
102、在衬底上形成第一材料和第二材料依次层叠的交叠层，第一材料与第二材料不同。
103、在交叠层上形成第一掩膜层。
参考图2所示，在一种可能的实现方式中，衬底201的材料为硅，第一材料2021为硅锗，第二材料2022为硅，交叠层202由硅锗和硅依次交叠形成，第一掩膜层203由依次层叠的氧化层(oxide)2031、多晶硅(a-Si)层2032以及氮化硅(SiN)层2033构成。需要说明的是，在图2中，在氮化硅(SiN)层2033上覆盖有一层显影后的光刻胶204，显影后的光刻胶204的制作过程将在下文中说明，此处不再赘述。
在其他可能的实现方式中，衬底201的材料还可以为锗等半导体材料，第一材料2021和第二材料2022例如还可以为锗、半导体化合物(即四簇元素的半导体化合物、三五簇元素的半导体化合物)等半导体材料。交叠层202中所包括的层的数量也可以根据设计需求确定。第一掩膜层203还可以包括更多层或者更少层，此处不作特殊限定。第一掩膜层203的材料还可以为半导体制造工艺中使用的其他能够作为掩膜层的材料，此处不作特殊限定。
104、在第一掩膜层中形成第一沟槽。
参考图3所示，在一种可能的实现方式中，第一沟槽205垂直贯穿第一掩膜层203中的多晶硅(a-Si)层2032以及氮化硅(SiN)层2033，即第一沟槽205未完全贯穿第一掩膜层203。形成第一沟槽203的过程可以为：在第一掩膜层203上涂光刻胶，对光刻胶进行曝光显影，以去除第一掩膜层203上用于形成第一沟槽205的位置处的光刻胶，得到图2中的显影后的光刻胶204，如图2所示，去除光刻胶的区域用于形成第一沟槽205；接下来，在显影后的光刻胶204的保护下采用各向异性蚀刻的方式，在未被光刻胶204覆盖的区域向下刻蚀第一掩膜层203，以形成第一沟槽205。刻蚀的深度为第一掩膜层203中的多晶硅(a-Si)层2032和氮化硅(SiN)层2033的厚度之和。需要说明的是，上述形成第一沟槽205的过程仅为示例性的，并不用于限定本申请。
在其他可能的实现方式中，第一沟槽205也可以垂直且完全贯穿第一掩膜层203，第一沟槽205还可以垂直且贯穿多晶硅(a-Si)层2032、氮化硅(SiN)层2033以及氧化层(oxide)2031的一部分。
需要说明的是，在形成第一沟槽205后，去除第一掩膜层203上的光刻胶204。在本申请实施例中，第一沟槽205的宽度为C，其根据侧墙的宽度和侧墙两侧形成的第一沟道层和第二沟道层的宽度确定。侧墙、第一沟道层和第二沟道层将在下文中说明。
105、通过在第一掩膜层上和第一沟槽内形成第二掩膜层的方式，在第一沟槽中形成第二沟槽。
第二掩膜层的材料例如可以为氧化物或者氮化硅等，此不作特殊限定。第二掩膜层的材料与第一掩膜层的材料可以相同，也可以不同，此处不作特殊限定。需要说明的是，在第一掩膜层由多种材料构成的情况下，第二掩膜层的材料可以与构成第一掩膜层的多种材料中的一种相同，也可以与构成第一掩膜层的多种材料不同。
形成第二掩膜层的过程可以为：通过沉积的方式在形成第一沟槽后的结构表面形成第 二掩膜层，即在第一掩膜层上和第一沟槽内(即第一沟槽的侧壁和下表面上)形成第二掩膜层。由于第一沟槽的下表面与第一掩膜层的上表面存在高度差，因此，通过形成第二掩膜层的方式可以在第一沟槽中形成第二沟槽。
106、采用各向异性的刻蚀方式沿着与衬底垂直的方向刻蚀第二掩膜层，直至去除位于第二沟槽的侧壁之间且位于第一沟槽的下表面上的第二掩膜层，以基于第二沟槽形成第三沟槽。
在上述刻蚀的过程中，第一掩膜层上的第二掩膜层也会被消耗掉一部分。
参考图4所示，在一种可能的实现方式中，第三沟槽207以第二掩膜层206作为其侧壁，且第三沟槽207的下表面与第一沟槽205的下表面持平，即第三沟槽207的下表面与第一掩膜层203中的氧化层(oxide)2031的上表面持平。以及在图4中，第二掩膜层206的材料为氮化硅。
107、以第二掩膜层作为保护层，从第三沟槽的下表面开始向下刻蚀，形成贯穿交叠层并延伸至衬底中的第四沟槽。
在该过程中，采用各向异性的刻蚀方式，以第二掩膜层作为保护层从第三沟槽的下表面开始向下刻蚀，形成贯穿交叠层并延伸至衬底中的第四沟槽。需要说明的是，第四沟槽可以不完全贯穿衬底，也可以完全贯穿衬底，此处不作特殊限定。
108、在第四沟槽中形成侧墙。
具体的，填充第四沟槽，形成侧墙。侧墙的材料例如可以为氧化物或者SiN等绝缘材料等。侧墙的材料可以与第二掩膜层的材料相同，也可以不同。
参见图5所示，在一种可能的实现方式中，侧墙208的材料与第二掩膜层206的材料相同，即侧墙208的材料为氮化硅。需要说明的是，在图5中，形成侧墙后，去掉了多晶硅层2032上的氮化硅。
显然，通过控制第二掩膜层的厚度(即第一沟槽的侧壁上的第二掩膜层的厚度(即图4中B))来控制第四沟槽的宽度，从而实现了对侧墙的宽度的控制，以及在形成侧墙的过程中实现了自对准，减少了对光刻工艺的依赖，降低了对光刻精度和光刻能力的要求，另外，通过上述方式还可以更进一步减小侧墙的尺寸，进而进一步缩小半导体器件的尺寸。
由上可知，由于在第四沟槽中形成侧墙，因此，侧墙的宽度由第四沟槽的宽度决定，而第四沟槽的形成原理是通过在第一掩膜层中形成第一沟槽，以及通过在第一沟槽中形成第二掩膜层的方式在第一沟槽中形成第二沟槽，并通过各向异性的刻蚀方式沿着垂直衬底的方向去除位于第二沟槽的侧壁之间且位于第一沟槽的下表面上的第二掩膜层，以得到第三沟槽，以及在第二掩膜层的保护下，从第三沟槽的下表面开始向下刻蚀，形成贯穿交叠层并延伸至衬底中的第四沟槽，即在第四沟槽的形成过程中，仅在第一沟槽的形成过程中使用了光刻工艺，又由于第四沟槽在第一沟槽内形成，因此，第一沟槽的宽度大于第四沟槽的宽度，即第一沟槽的宽度相对较大，这样，在形成第一沟槽的过程中，降低了对于光刻精度和光刻能力的要求，进而在形成侧墙的过程中，降低了对于光刻精度和光刻能力的要求。
在形成侧墙后，可以通过多种工艺流程中的任一种形成forksheet结构的半导体器件。下面，以下述两种工艺流程为例对形成forksheet结构的半导体器件的工艺流程进行说明。
如图6所示，第一种工艺流程的过程如下：
601、在侧墙两侧形成第一交叠结构和第二交叠结构，其中，第一交叠结构、第二交叠结构和侧墙上覆盖有第一介质层和第二介质层，第一介质层的一端与第一交叠结构和第二交叠结构的一端持平，第二介质层的一端与第一交叠结构和第二交叠结构的另一端持平，第一介质层的另一端与第二介质层的另一端相距一预设距离。第一交叠结构和第二交叠结构的长度均小于侧墙的长度。
在一种可能的实现方式中，形成侧墙两侧的第一交叠结构和第二交叠结构的过程可以包括：
首先，通过去除待去除掩膜层以及位于待去除掩膜层下方的交叠层，形成位于侧墙两侧的第五交叠结构和第六交叠结构，其中，待去除掩膜层为位于第一沟槽的侧壁外的第一掩膜层。参照图5所示，在一种可能的实现方式中，待去除掩膜层为第一掩膜层203中位于第一沟槽的侧壁外的多晶硅层2032和氧化层(oxide)2031，在图5的基础上，去除待去除掩膜层以及其下方的交叠层后得到的第五交叠结构和第六交叠结构如图7所示，其中，第五交叠结构209和第六交叠结构210位于侧墙208的两侧。需要说明的是，在形成第五交叠结构209和第六交叠结构210的过程中，第二掩膜层206和侧墙208在其高度上也存在一定的损耗。
在另一种可能的实现方式中，为了避免基于第五交叠结构和第六交叠结构形成的场效应晶体管与衬底连接形成寄生器件，从而影响场效应晶体管的性能，在形成第五交叠结构和第六交叠结构之后，参照图8所示，通过刻蚀衬底201的方式，在衬底201与第五交叠结构209和第六交叠结构210之间形成一个间隙211，以及通过沉积的方式在该间隙211中形成第五介质层。这样，就可以通过第五介质层将衬底201与第五交叠结构209和第六交叠结构210隔开，从而通过第五介质层将衬底201与基于第五交叠结构209和第六交叠结构210形成的场效应晶体管隔开，进而避免基于第五交叠结构209和第六交叠结构210形成的场效应晶体管与衬底201连接，形成寄生器件，提升了场效应晶体管的性能。
第五介质层的材料例如可以为氧化物、氮化硅等绝缘材料，本申请对此不作特殊限定。
需要说明的是，基于第五交叠结构形成的场效应晶体管包括多个第一沟道层和第一掺杂结构等，基于第六交叠结构形成的场效应晶体管包括多个第二沟道层和第二掺杂结构等。由上可知，由于第五交叠结构和第六交叠结构位于第五介质层上，因此，多个第一沟道层、第一掺杂结构，多个第二沟道层、第二掺杂结构均位于第五介质层上。
需要说明的是，上述形成第五介质层的方式仅为示例性的，并不用于限定本申请。
然后，形成覆盖第五交叠结构、第六交叠结构和侧墙的假栅结构，其中，假栅结构的长度与上述预设距离相等。假栅结构的长度根据器件的设计要求确定，此处不作特殊限定。参考图9所示，在一种可能的实现方式中，假栅结构213覆盖在第五交叠结构209、第六交叠结构210和侧墙208上，以及第五交叠结构209和第六交叠结构210位于第五介质层212上。假栅结构213的长度为b。
最后，在假栅结构的两端形成第一介质层和第二介质层，以及去除第五交叠结构中未被假栅结构、第一介质层和第二介质层覆盖的区域，以得到第一交叠结构，去除第六交叠结构中未被假栅结构、第一介质层和第二介质层覆盖的区域，以得到第二交叠结构。
第一介质层和第二介质层的材料可以为氧化物或者氮化硅等绝缘材料。参见图10所 示，在一种可能的实现方式中，第一交叠结构216和第二交叠结构217位于侧墙208两侧，且第一交叠结构216、第二交叠结构217和侧墙208被假栅结构213、第一介质层214和第二介质层215覆盖，第一介质层214和第二介质层215位于假栅结构213两端。
602、去除第一交叠结构中被第一介质层和第二介质层覆盖的第一目标材料，去除第二交叠结构中被第一介质层和第二介质层覆盖的第二目标材料。
第一目标材料为第一材料和第二材料中不用于形成第一沟道层的材料；第二目标材料为第一材料和第二材料中不用于形成第二沟道层的材料。第一目标材料与第二目标材料可以相同，也可以不同，本申请对此不作特殊限定。
在一种可能的实现方式中，第一材料为硅锗，第二材料为硅，第一目标材料为硅，第二目标材料为硅锗。
603、在去除第一目标材料的区域中形成第三介质层，以得到第三交叠结构，在去除第二目标材料的区域中形成第四介质层，以得到第四交叠结构。
第三介质层和第四介质层的材料例如可以为氧化物或者氮化硅等绝缘材料。第三介质层的材料与第四介质层的材料可以相同，也可以不同。
需要说明的是，将去除了第一目标材料并形成第三介质层的第一交叠结构命名为第三交叠结构，将去除了第二目标材料并形成第四介质层的第二交叠结构命名为第四交叠结构。
604、在第三交叠结构的两端形成第一掺杂结构，在第四交叠结构的两端形成第二掺杂结构。第一掺杂结构和第二掺杂结构的掺杂类型相反，即若第一掺杂结构的掺杂类型为N型，则第二掺杂结构的掺杂类型为P型，若第一掺杂结构的掺杂类型为P型，则第二掺杂结构的掺杂类型为N型。
在604中，可以通过沉积的方式在第三交叠结构的两端形成第一掺杂结构，在第四交叠结构的两端形成第二掺杂结构。需要说明的是，在形成第一掺杂结构和第二掺杂结构时，可以先沉积再掺杂，即在沉积的过程中不进行掺杂，也可以沉积对应掺杂类型的掺杂结构。掺杂之前的第一掺杂结构和第二掺杂结构的材料例如可以为：硅、锗、硅锗等半导体材料等。
参见图11所示，在一种可能的实现方式中，第一掺杂结构220的数量为两个，并分别位于第三交叠结构的两端，第二掺杂结构221的数量为两个，分别位于第四交叠结构的两端。需要说明的是，图11为立体图，为了便于清楚表示图中被第一掺杂结构220和第二掺杂结构221遮挡的结构，采用半透明的方式显示第一掺杂结构220和第二掺杂结构221。图12为图11沿着a-a’方向的刨面图，在图12中，第一材料2021为硅锗，第二材料2022为硅，第三交叠结构218和第四交叠结构219位于侧墙208两侧，第一目标材料为第二材料，即第一目标材料为硅，第二目标材料为第一材料，即第二目标材料为硅锗。第三介质层222位于去除了第一目标材料的区域中，第四介质层223位于去除了第二目标材料的区域中。
通过形成第一掺杂结构，得到第一场效应晶体管的源漏区域，通过形成第二掺杂结构，得到第二场效应晶体管的源漏区域。其中，第一场效应晶体管为基于第一交叠结构(即第五交叠结构)形成的场效应晶体管，第二场效应晶体管为基于第二交叠结构(即第六交叠结构)形成的场效应晶体管。
605、去除第三交叠结构中的第一目标材料，以形成多个第一沟道层，去除第四交叠 结构中的第二目标材料，以形成多个第二沟道层。第一目标材料和第二目标材料已经在上文中进行了说明，因此此处不再赘述。
第一沟道层为第一场效应晶体管的沟道区域，第二沟道层为第二场效应晶体管的沟道区域。
第一沟道层的材料和第二沟道层的材料可以相同，也可以不同，此处不作特殊限定。需要说明的是，若第一沟道层的材料和第二沟道层的材料不同，则可以分别根据第一沟道层和第二沟道层所对应的场效应晶体管的类型，分别为第一沟道层的材料和第二沟道层选择合适的材料，以提升场效应晶体管的性能。
第一沟道层和第二沟道层可以掺杂，也可以不掺杂，此处不作特殊限定。需要说明的是，若第一沟道层和第二沟道层掺杂，则第一沟道层的掺杂类型与第一掺杂结构的掺杂类型相反，第二沟道层的掺杂类型与第二掺杂结构的掺杂类型相反。
需要说明的是，在一种可能的实现方式中，若第三交叠结构和第四交叠结构上覆盖有假栅结构，则需要去除假栅结构，然后，去除第三交叠结构中的第一目标材料，以形成多个第一沟道层，去除第四交叠结构中的第二目标材料，以形成多个第二沟道层。
参见图13所示，在一种可能的实现方式中，第一材料2021为硅锗，第二材料2022为硅，第一目标材料为硅，第二目标材料为硅锗，第一沟道层224的材料为硅锗，第二沟道层225的材料为硅，第一掺杂结构220的掺杂类型为P型，第二掺杂结构的掺杂类型为N型，第一沟道层224和第二沟道层225均未掺杂。由上可知，由于第一掺杂结构220的掺杂类型为P型，第二掺杂结构的掺杂类型为N型，因此，基于第一交叠结构形成的场效应晶体管的沟道类型为P型，基于第二交叠结构形成的场效应晶体管的沟道类型为N型。又由于硅锗材料制作的沟道层有助于提升P型场效应晶体管的性能，硅材料制作的沟道层有助于提升N型场效应晶体管的，因此，选择硅作为第二沟道层225的材料，选择硅锗作为第一沟道层224的材料，以提升基于第一交叠结构形成的场效应晶体管和基于第二交叠结构形成的场效应晶体管的性能。
需要说明的是，图13为以图11沿着A-A’方向的剖视图为基础形成的第一沟道层和第二沟道层的结构示意图。由于图13为立体图，因此，第二掺杂结构被其他结构遮挡。
606、在第一沟道层上形成第一栅绝缘层，在第二沟道层上形成第二栅绝缘层，以及在第一栅绝缘层上形成第一栅导电层，在第二栅绝缘层上形成第二栅导电层。
第一栅绝缘层和第二栅绝缘层的材料例如可以为二氧化硅或者high-k材料(例如ZrO 2、HfO 2、Al 2O 3等)等，此处不作特殊限定。第一栅导电层和第二栅导电层的材料例如可以为金属材料或重掺杂的多晶硅等，此处不作特殊限定。
第一栅绝缘层和第二栅绝缘层的材料可以相同，也可以不同，第一栅导电层和第二栅导电层的材料可以相同，也可以不同。若第一栅绝缘层和第二栅绝缘层的材料相同和/或第一栅导电层和第二栅导电层的材料相同，则可以简化制作工艺，节约制作成本。
参见图14所示，在一种可能的实现方式中，在第一沟道层224的暴露面上形成第一栅绝缘层，在第二沟道层225的暴露面上形成第二栅绝缘层。第一沟道层224的暴露面为第一沟道层224中未与其他结构接触的表面，第二沟道层225的暴露面为第二沟道层225中未与其他结构接触的表面，以及在第一栅绝缘层中远离第一沟道层的表面沉积第一栅导电层，在第二栅绝缘层中远离第二沟道层的表面沉积第二栅导电层。需要说明的是，在图 14中，第一栅绝缘层和第一栅导电层并未分开示出，即图14中的227用于指示第一栅绝缘层和第一栅导电层的组合体，同理，第二栅绝缘层和第二栅导电层并未分开示出，即图14中的228用于指示第二栅绝缘层和第二栅导电层的组合体。此外，如图14所示，在形成第一栅绝缘层和第一栅导电层后，侧墙上也同样形成了第一栅绝缘层和第一栅导电层，为了简化制作工艺，可以不用去除侧墙上的第一栅绝缘层和第一栅导电层。同样第二栅绝缘层和第二栅导电层也存在同样的情况，此处不再赘述。
由上可知，通过上述工艺制作的半导体器件包括两个场效应晶体管，分别为第一场效应晶体管和第二场效应晶体管，其中：第一场效应晶体管包括多个第一沟道层、第一掺杂结构、第一栅绝缘层和第一栅导电层。多个第一沟道层为第一场效应晶体管的沟道区域，第一栅绝缘层和第一栅导电层构成了第一场效应晶体管的栅极，第一掺杂结构构成了第一场效应晶体管的源漏区域。第二场效应晶体管包括多个第二沟道层、第二掺杂结构、第二栅绝缘层和第二栅导电层。多个第二沟道层为第二场效应晶体管的沟道区域，第二栅绝缘层和第二栅导电层构成了第二场效应晶体管的栅极，第二掺杂结构构成了第二场效应晶体管的源漏区域。
在此基础上，若第一栅导电层和第二栅导电层的材料相同，则可以消除第一场效应晶体管和第二场效应晶体管中的栅极的导电层的金属接触效应，即消除了金属栅接触效应。
由于第一掺杂结构和第二掺杂结构的掺杂类型相反，因此，第一场效应晶体管与第二场效应晶体管的沟道类型相反。即若第一掺杂结构的掺杂类型为N型，第二掺杂结构的掺杂类型为P型，则第一场效应晶体管的沟道类型为N型，第二场效应晶体管的沟道类型为P型；即若第一掺杂结构的掺杂类型为P型，第二掺杂结构的掺杂类型为N型，则第一场效应晶体管的沟道类型为P型，第二场效应晶体管的沟道类型为N型。
参见图15所示，在一种可能的实现方式中，为了便于向第一栅导电层和第二栅导电层施加电压，还可以在形成第一栅导电层和第二栅导电层之后，在第一栅导电层和第二栅导电层上形成电极结构229。电极结构229还用于填充相邻的第一栅导电层之间的间隙、相邻的第二栅导电层之间的间隙。电极结构229的材料包括但不限于铝、银等金属材料。
参见图15所示，为了隔离相邻半导体器件的电极结构，还可以通过沉积的方式在电极结构229上形成隔离层230。隔离层230的材料例如可以为氧化物、氮化硅等绝缘材料，本申请实施例对此不作特殊限定。
需要说明的是，在另一种可能的实现方式中，第一介质层与第五介质层也可以替换为空气。
下面，对通过上述第一种工艺流程制作的forksheet结构的半导体器件的结构进行说明。
参见图15所示，半导体器件包括：
衬底201，垂直设置在衬底201上的侧墙208，沿着与衬底201垂直的方向依次间隔设置在侧墙208的一个侧面上的多个第一沟道层224，沿着与衬底201垂直的方向依次间隔设置在侧墙208的另一个侧面上的多个第二沟道层225，其中，第一沟道层224沿着侧墙208的侧面延伸，第二沟道层225沿着侧墙208的侧面延伸，设置在多个第一沟道层224两端的第一掺杂结构220，设置在多个第二沟道层225的两端的第二掺杂结构(图15中未示出)，其中，第一掺杂结构220与第二掺杂结构的掺杂类型相反，覆盖在多个第一 沟道层224的第一表面的一端和多个第二沟道层225的第一表面的一端的第一介质层(图15中未示出)，覆盖在多个第一沟道层224的第一表面的另一端和多个第二沟道层225的第一表面的另一端的第二介质层215，其中，多个第一沟道层224的第一表面为多个第一沟道层224中远离侧墙208的表面，多个第二沟道层225的第一表面为多个第二沟道层225中远离侧墙208的表面，设置在多个第一沟道层224的第二表面的两端的第三介质层(图15中未示出)，设置在多个第二沟道层225的第二表面的两端的第四介质层(图15中未示出)，其中，多个第一沟道层224的第二表面为多个第一沟道层224中与其第一表面相邻且与衬底201平行的表面，多个第二沟道层224的第二表面为多个第二沟道层224中与其第一表面相邻且与衬底201平行的表面；依次设置在第一沟道层224上的第一栅绝缘层和第一栅导电层，依次设置在第二沟道层225上的第二栅绝缘层和第二栅导电层。
需要说明的是，在图15中，第一栅绝缘层和第一栅导电层并未分开示出，即图15中的227用于指示第一栅绝缘层和第一栅导电层的组合体，同理，第二栅绝缘层和第二栅导电层并未分开示出，即图15中的228用于指示第二栅绝缘层和第二栅导电层的组合体。
上述各个部分的材料以及位置关系已经在上文中进行了说明，因此此处不再赘述。
由上可知，半导体器件包括两个场效应晶体管，分别为第一场效应晶体管和第二场效应晶体管，第一场效应晶体管和第二场效应晶体管分别位于侧墙的两侧。其中，多个第一沟道层作为第一场效应晶体管的沟道区域，第一掺杂结构作为第一场效应晶体管的源漏区域，第一栅绝缘层和第一栅导电层作为第一场效应晶体管栅极区域，第一介质层、第二介质层以及第三介质层将第一场效应晶体管的栅极区域和源漏区域隔离。多个第二沟道层作为第二场效应的沟道区域，第二掺杂结构作为第二场效应晶体管的源漏区域，第二栅绝缘层和第二栅导电层作为第二场效应晶体管栅极区域，第一介质层、第二介质层以及第四介质层将第二场效应晶体管的栅极区域和源漏区域隔离。
第一掺杂结构220与第二掺杂结构的掺杂类型相反，即第一场效应晶体管与第二产效应晶体管的沟道类型相反。即，若第一掺杂结构220的掺杂类型为N型(即第一场效应晶体管的沟道类型为N型)，则第二掺杂结构的掺杂类型为P型(即第二场效应晶体管的沟道类型为P型)；若第一掺杂结构220的掺杂类型为P型(即第一场效应晶体管的沟道类型为P型)，则第二掺杂结构的掺杂类型为N型(即第二场效应晶体管的沟道类型为N型)。
参见图15所示，第一沟道层224与第二沟道层225的材料不同，第一沟道层224与第二沟道层225不在同一个平面上，且第一沟道层224的上表面与第二沟道层225的下表面持平。
在第一沟道层224的材料和第二沟道层225的材料不同的情况下，可以分别根据第一沟道层和第二沟道层所对应的场效应晶体管的类型，分别为第一沟道层和第二沟道层选择合适的材料，以提升场效应晶体管的性能，进而提升半导体器件的驱动性能。
例如，在一种可行的实现方式中，若第一掺杂结构的掺杂类型为P型，即第一场效应晶体管的沟道类型为P型，第二掺杂结构的掺杂类型为N型，即第二场效应晶体管的沟道类型为N型，则，由于硅锗材料制作的沟道层有助于提升P型场效应晶体管的性能，硅材料制作的沟道层有助于提升N型场效应晶体管的，因此，为了提升第一场效应晶体管和第二场效应晶体管的性能，第一沟道层的材料选择硅锗，第二沟道层的材料选择硅。
需要说明的是，在另一种可能的实现方式中，第一沟道层224与第二沟道层225的材料也可以相同。
第一栅绝缘层和第二栅绝缘层的材料可以相同，也可以不同，本申请实施例对此不作特殊限定。第一栅导电层和第二栅导电层的材料可以相同，也可以不同，本申请实施例对此不作特殊限定。
由于第一场效应晶体管和第二场效应晶体管的沟道类型相反，因此，第一场效应晶体管和第二场效应晶体管具有不同的VT(阈值电压)，场效应晶体管的VT可以理解为栅导电层的功函数与沟道层的费米能级的差值。换言之，若第一场效应晶体管的VT(即第一栅导电层的功函数与第一沟道层的费米能级的差值)为第一数值，第二场效应晶体管的VT(即第二栅导电层的功函数与第二沟道层的费米能级的差值)为第二数值，则第一数值和第二数值不同。第一数值与第一场效应晶体管的沟道类型、第一场效应晶体管的结构以及第一场效应晶体管的各个部分的参数等相关，同理，第二数值与第二场效应晶体管的沟道类型、第二场效应晶体管的结构以及第二场效应晶体管的各个部分的参数等相关。
需要说明的是，若场效应晶体管的沟道类型为N型，则栅导电层的功函数与沟道层的费米能级的差值大于0，若场效应晶体管的沟道类型为P型，则栅导电层的功函数与沟道层的费米能级的差值小于0。
可以通过下述四种方式中的至少一种使场效应晶体管的VT(即栅导电层的功函数与沟道层的费米能级的差值)满足要求。其中：
第一种，通过调节沟道层的掺杂浓度和掺杂类型，改变沟道层的费米能级。
第二种，若沟道层的材料为半导体化合物，则通过调节半导体化合物中的各组分的比例，改变沟道层的费米能级。
第三种，若栅绝缘层的材料为high-k材料，则通过选择合适的栅绝缘层的high-k材料和/或改变栅绝缘层的制作工艺(例如退火条件等)，对栅导电层的功函数产生影响。
第四种，由于不同的金属材料具有不同的功函数，因此通过选择对应功函数的金属材料来制作栅导电层，得到符合功函数要求的栅导电层，以及若栅导电层的材料为重掺杂的多晶硅，则通过改变多晶硅的掺杂类型和浓度来改变栅导电层的功函数。
由上可知，通过上述四种方式中的至少一种方式，调节栅导电层的功函数和/或沟道层的费米能级，以使场效应晶体管的VT满足要求。
基于上述原理，在第一栅绝缘层和第二栅绝缘层的材料相同，第一栅导电层和第二栅导电层的材料相同的情况下(即第一栅导电层的功函数和第二栅导电层的功函数相同且确定的情况下)，通过以下两种方式中的至少一种，调节第一沟道层和第二沟道层的费米能级，使得第一栅导电层的功函数与第一沟道层的费米能级的差值为第一数值，第二栅导电层的功函数与第二沟道层的费米能级的差值为第二数值，即使得第一场效应晶体管的VT和第二场效应晶体管的VT满足要求，其中：
方式一：若第一沟道层的材料和/或第二沟道层的材料为半导体化合物，则调节半导体化合物的组分比例。
方式二：调节第一沟道层和第二沟道层的掺杂类型和掺杂浓度。
显然，在第一栅绝缘层和第二栅绝缘层的材料相同，第一栅导电层和第二栅导电层的 材料相同的情况下，即在第一场效应晶体管和第二场效应晶体管共用栅绝缘层和栅导电层的条件下，通过上述方式调节第一沟道层和第二沟道层的费米能级，使得第一场效应晶体管的VT和第二场效应晶体管的VT满足要求。此外，由于第一场效应晶体管和第二场效应晶体管共用栅导电层和栅绝缘层，因此，消除了第一场效应晶体管和第二场效应晶体管的栅极的金属接触效应，即金属栅接触效应，提升了器件性能，同时还简化了半导体器件的制作工艺。另外，通过上述方式调节第一沟道层和第二沟道层的费米能级，以借助能带差使得第一场效应晶体管的VT和第二场效应晶体管的VT满足要求，进而使得第一场效应晶体管和第二场效应晶体管能够共用栅绝缘层和栅导电层。
例如，图16为第一场效应晶体管和第二场效应晶体管的能带图。在图16所示，第一场效应晶体管为P沟道的场效应晶体管，第二场效应晶体管为N沟道的场效应晶体管，第一沟道层的材料为硅锗，第二沟道层的材料为硅，第一栅导电层和第二栅导电层采用相同的材料，第一栅绝缘层和第二栅绝缘层采用相同的材料。
在此基础上，可以首先根据第二沟道层的费米能级(硅的费米能级)确定第一栅导电层和第二栅导电层的材料，使得第一栅导电层和第二栅导电层的功函数WF大于第二沟道层的费米能级Efn，且第二场效应的晶体管的VT为第二数值，然后，通过调节硅锗组分，改变第一沟道层的费米能级Efp，使得第一沟道层的费米能级Efp大于第一栅导电层和第二栅导电层的功函数WF，且第一场效应晶体管的VT为第一数值。图16中的Ecp为第一沟道层的导带，Evp为第一沟道层的价带，Ecn为第二沟道层的导带，Evn为第二沟道层的价带。
基于上述原理，在第一栅导电层和第二栅导电层的材料相同的情况下，可以通过以下三种方式中的至少一种，使第一栅导电层的功函数与第一沟道层的费米能级的差值为第一数值，第二栅导电层的功函数与第二沟道层的费米能级的差值为第二数值，其中：
方式一：第一栅绝缘层和第二栅绝缘层的材料为high-k材料，调节第一栅绝缘层和第二栅绝缘层分别对应的high-k材料的类型和/或第一栅绝缘层和第二栅绝缘层的制作工艺(例如退火温度、时间等)。
方式二、若第一沟道层的材料和/或第二沟道层的材料为半导体化合物，则调节半导体化合物的组分比例。
方式三、调节第一沟道层和第二沟道层的掺杂类型和掺杂浓度。
显然，在第一场效应晶体管和第二场效应晶体管共用栅导电层的条件下(即在第一栅导电层和第二栅导电层的材料相同的条件下)，通过上述方式调节第一沟道层和第二沟道层的费米能级和/或第一栅导电层的功函数和第二栅导电层的功函数，使得第一场效应晶体管的VT和第二场效应晶体管的VT满足要求。此外，由于第一场效应晶体管和第二场效应晶体管共用栅导电层，消除了第一场效应晶体管和第二场效应晶体管的栅极的金属接触效应，提升了器件性能，同时还简化了半导体器件的制作工艺。另外，通过上述方式调节第一沟道层和第二沟道层的费米能级和/或第一栅导电层的功函数和第二栅导电层的功函数，以借助能带差使得第一场效应晶体管的VT和第二场效应晶体管的VT满足要求，使得第一场效应晶体管和第二场效应晶体管能够共用栅导电层。
需要说明的是，上述方式仅为示例性的，并不用于限定本申请。
可以通过以下三种方式中的至少一种，在第一栅绝缘层和第二栅绝缘层的材料相同的情况下，使第一栅导电层的功函数与第一沟道层的费米能级的差值为第一数值，第二栅导电层的功函数与第二沟道层的费米能级的差值为第二数值，其中：
方式一，调节第一沟道层和第二沟道层的掺杂类型和掺杂浓度。
方式二，若第一沟道层的材料和/或第二沟道层的材料为半导体化合物，则调节半导体化合物的组分比例。
方式三，选择合适的第一栅导电层和第二栅导电层的金属材料或者调节第一栅导电层和第二栅导电层(若第一栅导电层和第二栅导电层为重掺杂的多晶硅)的掺杂类型和浓度。
显然，通过上述方式，在第一场效应晶体管和第二场效应晶体管共用栅绝缘层的条件下，通过上述方式调节第一沟道层和第二沟道层的费米能级和/或第一栅导电层的功函数和第二栅导电层的功函数，使得第一场效应晶体管的VT和第二场效应晶体管的VT满足要求。此外，由于第一场效应晶体管和第二场效应晶体管共用栅绝缘层，简化了半导体器件的制作工艺。
需要说明的是，上述方式仅为示例性的，并不用于限定本申请。
参见图15所示，为了避免衬底与第一场效应晶体管和第二场效应晶体管连接，以形成寄生器件，从而影响第一场效应晶体管和第二场效应晶体管的性能，半导体器件还包括第五介质层212，该第五介质层212位于衬底201和场效应晶体管之间，即第五介质层212位于衬底201上，且多个第一沟道层224、多个第二沟道层225、第一掺杂结构220和第二掺杂结构位于第五介质层212上。
为了便于向第一栅导电层和第二栅导电层施加电压，如图15所示，半导体器件还包括电极结构229，电极结构229位于第一栅导电层和第二栅导电层上，用于连通第一栅导电层和第二栅导电层。
为了隔离相邻半导体器件的电极结构，如图15所示，半导体器件还包括隔离层230，该隔离层230覆盖在电极结构229上。需要说明的是，隔离层230上设置有开孔，以从该开孔引出电极结构229。
需要说明的是，由于上述各个部分已经在上文中进行了说明，因此此处不再赘述。以及，图15仅为通过第一种工艺流程制作的半导体器件的一种结构，并不用于限定本申请。
第二种工艺流程的过程如下：
由于第一种工艺流程与第二种工艺流程在形成多个第一沟道层和多个第二沟道层及其之前的流程相同，因此，下面仅对第二种工艺中形成多个第一沟道层和多个第二沟道层之后的流程进行说明，具体如下：
通过刻蚀的方式去除位于第一介质层和第二介质层之间的侧墙。在一种可能的实现方式中，去除第一介质层和第二介质层之间的侧墙后的结构参见图17所示。
通过沉积的方式在第一沟道层和第二沟道层上形成栅绝缘层。具体的，在第一沟道层的暴露面上和第二沟道层的暴露面上沉积栅绝缘层。由于第一沟道层和第二沟道层的暴露 面已经在上文中进行了说明，此处不再赘述。绝缘层的材料例如可以为二氧化硅或者high-k材料(例如ZrO 2、HfO 2、Al 2O 3等)等，此处不作特殊限定。
通过沉积的方式，在栅绝缘层上形成栅导电层。栅导电层的材料例如可以为金属材料和重掺杂的多晶硅等，此处不作特殊限定。
由上可知，由于去除了位于第一介质层和第二介质层之间的侧墙，因此，第一沟道层和第二沟道层的四个侧面均暴露在外面。这样，就可以形成环栅结构，即栅绝缘层和栅导电层构成的栅极区域覆盖第一沟道层和第二沟道层的四个侧面，提升了器件的栅驱动能力。
在一种可能的实现方式中，在第一沟道层和第二沟道层上依次形成栅绝缘层和栅导电层的半导体器件如图18所示。参见图18可知，栅绝缘层和栅导电层在第一沟道层224和第二沟道层225上形成了环栅结构。需要说明的是，在图18中并未将栅绝缘层和栅导电层分开示出，即图18中的231用于指示栅绝缘层和导电层的组合体。
由上可知，半导体器件包括两个场效应晶体管，分别为第一场效应晶体管和第二场效应晶体管，其中，多个第一沟道层作为第一场效应的沟道区域，第一掺杂结构作为第一场效应晶体管的源漏区域，栅绝缘层和栅导电层作为第一场效应晶体管的栅极区域，第一介质层、第二介质层以及第三介质层将第一场效应晶体管的栅极区域和源漏区域隔离。多个第二沟道层作为第二场效应的沟道区域，第二掺杂结构作为第二场效应晶体管的源漏区域，栅绝缘层和栅导电层还作为第二场效应晶体管的栅极区域，第一介质层、第二介质层以及第四介质层将第二场效应晶体管的栅极区域和源漏区域隔离。
由于第一沟道层和第二沟道层上共用了栅绝缘层和栅导电层，因此，简化了工艺，同时还可以消除第一场效应晶体管和第二场效应晶体管的栅极的金属接触效应。此外，由于去除了侧墙，因此增加了第一沟道层和第二沟道层的暴露面积，进而增加了栅绝缘层和栅导电层的覆盖面积，从而增加了器件的栅控能力。
在第二种工艺流程中，参见图19所示，在一种可行的实现方式中，也可以形成第五介质层212、电极结构229和隔离层230，由于形成第五介质层212、电极结构229和隔离层230的目的和原理与第一种工艺流程中的原理和目的相同，因此此处不再赘述。
下面，对通过上述第二种工艺流程制作的forksheet结构的半导体器件的结构进行说明。
参见图19所示，该半导体器件与上述第一种制作工艺制作的半导体器件的区别在于：
位于第一介质层与第二介质层215之间的侧墙208被去除，第一沟道层224中与去除的侧墙208接触的表面上依次设置有第一栅绝缘层和第一栅导电层，第二沟道层225中与去除的侧墙208接触的表面上依次设置有第二栅绝缘层和第二栅导电层，其中，第一栅绝缘层和第二栅绝缘层的材料相同，第一栅导电层和第二栅导电层的材料相同。
需要说明的是，由于第一栅绝缘层和第二栅绝缘层的材料相同，因此，将第一栅绝缘层和第二栅绝缘层统称为栅绝缘层。由于第一栅导电层和第二栅导电层的材料相同，因此，将第一栅导电层和第二栅导电层统称为栅导电层。基于此，在图19中，栅绝缘层和导电层并未分开示出，即图19中的231用于指示栅绝缘层和导电层的组合体。
由上可知，通过去除侧墙，使得第一沟道层和第二沟道层的四个侧面均暴露在外面，从而可以在第一沟道层上形成环栅结构(环栅结构包括第一栅绝缘层和第一栅导电层)， 在第二沟道层上形成环栅结构(环栅结构包括第二栅绝缘层和第二栅导电层)，增加了器件的栅极驱动能力。此外，由于第一栅绝缘层和第二栅绝缘层的材料相同，第一栅导电层和第二栅导电层的材料相同，这样，第一场效应晶体管和第二场效应晶体管形成了共栅结构，简化了工艺流程，降低制作成本。
由于第一场效应晶体管和第二场效应晶体管的沟道类型相反，因此，第一场效应晶体管和第二场效应晶体管具有不同的VT(阈值电压)，场效应晶体管的VT可以理解为栅导电层的功函数与沟道层的费米能级的差值。换言之，第一场效应晶体管的VT(栅导电层的功函数与第一沟道层的费米能级的差值)为第一数值，第二场效应晶体管的VT(栅导电层的功函数与第二沟道层的费米能级的差值)为第二数值，且第一数值和第二数值不同。
由于在通过第二种工艺流程制作的forksheet结构的半导体器件中，第一场效应晶体管和第二场效应晶体管共用了栅绝缘层和栅导电层，因此，可以通过以下两种方式中的至少一种，使栅导电层(即第一栅导电层)的功函数与第一沟道层的费米能级的差值为第一数值，栅导电层(即第二栅导电层)的功函数与第二沟道层的费米能级的差值为第二数值，其中：
方式一：若第一沟道层的材料和/或第二沟道层的材料为半导体化合物，则调节半导体化合物的组分比例。
方式二：调节第一沟道层和第二沟道层的掺杂类型和掺杂浓度。
显然，在第一场效应晶体管和第二场效应晶体管共用栅绝缘层和栅导电层的条件下，通过上述方式调整第一沟道层和第二沟道层的费米能级，使得第一场效应晶体管的VT和第二场效应晶体管的VT满足要求。此外，由于第一场效应晶体管和第二场效应晶体管共用栅导电层和栅绝缘层，消除了第一场效应晶体管和第二场效应晶体管的栅极的金属接触效应，提升了器件性能，同时还简化了半导体器件的制作工艺。另外，通过上述方式调节第一沟道层和第二沟道层的费米能级，以借助能带差使得第一场效应晶体管的VT和第二场效应晶体管的VT满足要求，进而使得第一场效应晶体管和第二场效应晶体管能够共用栅绝缘层和栅导电层。
为了避免衬底与第一场效应晶体管和第二场效应晶体管连接，以形成寄生器件，从而影响第一场效应晶体管和第二场效应晶体管的性能，如图19所示，上述半导体器件还包括第五介质层212，该第五介质层212位于衬底201和场效应晶体管之间，即第五介质层212位于衬底201上，且多个第一沟道层224、多个第二沟道层225、第一掺杂结构220和第二掺杂结构位于第五介质层212上。
为了便于向栅导电层(即第一栅导电层和第二栅导电层)施加电压，参见图19所示，半导体器件还包括电极结构229，电极结构229位于栅导电层上。为了隔离不同半导体器件的电极结构229，半导体器件还包括隔离层230，该隔离层230覆盖在电极结构229上。需要说明的是，隔离层230上设置有开孔，以从该开孔引出电极结构229。
需要说明的是，在上述提供的关于结构和工艺流程的附图均是在形成两个完全相同的叉型结构的半导体器件的基础上绘制的。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟 悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (16)

  1. 一种形成叉型结构中侧墙的方法，其特征在于，包括：
    提供衬底；
    在所述衬底上形成第一材料和第二材料依次层叠的交叠层；
    在所述交叠层上形成第一掩膜层；
    在所述第一掩膜层中形成第一沟槽；
    通过在所述第一掩膜层上和所述第一沟槽内形成第二掩膜层的方式，在所述第一沟槽中形成第二沟槽；
    采用各向异性的刻蚀方式沿着与所述衬底垂直的方向刻蚀所述第二掩膜层，直至去除位于所述第二沟槽的侧壁之间且位于所述第一沟槽的下表面上的所述第二掩膜层，以基于所述第二沟槽形成第三沟槽；
    以所述第二掩膜层作为保护层，从所述第三沟槽的下表面开始向下刻蚀，形成贯穿所述交叠层并延伸至所述衬底中的第四沟槽；
    在所述第四沟槽中形成侧墙。
  2. 根据权利要求1所述的方法，其特征在于，所述方法还包括：
    在所述侧墙两侧形成第一交叠结构和第二交叠结构，其中，所述第一交叠结构、所述第二交叠结构和所述侧墙上覆盖有第一介质层和第二介质层，所述第一介质层的一端与所述第一交叠结构和所述第二交叠结构的一端持平，所述第二介质层的一端与所述第一交叠结构和所述第二交叠结构的另一端持平，所述第一介质层的另一端与所述第二介质层的另一端相距一预设距离；
    去除所述第一交叠结构中被所述第一介质层和所述第二介质层覆盖的第一目标材料，去除所述第二交叠结构中被所述第一介质层和所述第二介质层覆盖的第二目标材料；
    在去除所述第一目标材料的区域中形成第三介质层，以得到第三交叠结构；
    在去除所述第二目标材料的区域中形成第四介质层，以得到第四交叠结构；
    在所述第三交叠结构的两端形成第一掺杂结构，在所述第四交叠结构的两端形成第二掺杂结构；
    去除所述第三交叠结构中的第一目标材料，以形成多个第一沟道层；
    去除所述第四交叠结构中的第二目标材料，以形成多个第二沟道层；
    其中，所述第一目标材料为所述第一材料和所述第二材料中不用于形成所述第一沟道层的材料；所述第二目标材料为所述第一材料和所述第二材料中不用于形成所述第二沟道层的材料，所述第一掺杂结构和所述第二掺杂结构的掺杂类型相反。
  3. 根据权利要求2所述的方法，其特征在于，所述方法还包括：
    在所述第一沟道层上形成第一栅绝缘层，在所述第二沟道层上形成第二栅绝缘层；
    在所述第一栅绝缘层上形成第一栅导电层，在所述第二栅绝缘层上形成第二栅导电层。
  4. 根据权利要求3所述的方法，其特征在于，所述第一栅绝缘层和所述第二栅绝缘层的材料相同，所述第一栅导电层和所述第二栅导电层的材料相同；或者
    所述第一栅导电层和所述第二栅导电层的材料相同。
  5. 根据权利要求2所述的方法，其特征在于，所述方法还包括：
    去除位于所述第一介质层和所述第二介质层之间的所述侧墙；
    在所述第一沟道层和所述第二沟道层上形成栅绝缘层；
    在所述栅绝缘层上形成栅导电层。
  6. 根据权利要求2～5中任一项所述的方法，其特征在于，所述在所述侧墙两侧形成第一交叠结构和第二交叠结构包括：
    通过去除待去除掩膜层以及位于所述待去除掩膜层下方的交叠层，形成位于所述侧墙两侧的第五交叠结构和第六交叠结构，其中，所述待去除掩膜层为位于所述第一沟槽的侧壁外的第一掩膜层；
    形成覆盖所述第五交叠结构、所述第六交叠结构和所述侧墙的假栅结构，其中，所述假栅结构的长度与所述预设距离相等；
    在所述假栅结构的两端形成所述第一介质层和所述第二介质层；
    去除所述第五交叠结构中未被所述假栅结构、所述第一介质层和所述第二介质层覆盖的区域，以得到所述第一交叠结构；
    去除所述第六交叠结构中未被所述假栅结构、所述第一介质层和所述第二介质层覆盖的区域，以得到所述第二交叠结构。
  7. 根据权利要求6所述的方法，其特征在于，在形成所述多个第一沟道层和所述多个第二沟道层之前还包括：
    去除所述假栅结构。
  8. 根据权利要求2～7中任一项所述的方法，其特征在于，所述方法还包括：
    在所述衬底上形成第五介质层，所述多个第一沟道层、所述多个第二沟道层、所述第一掺杂结构和所述第二掺杂结构位于所述第五介质层上。
  9. 根据权利要求2～8中任一项所述的方法，其特征在于，所述第一沟道层和所述第二沟道层的材料不同。
  10. 根据权利要求2～9中任一项所述的方法，其特征在于，所述第一掺杂结构为P型掺杂，所述第二掺杂结构为N型掺杂，所述第一沟道层的材料为硅锗，所述第二沟道层的材料为硅。
  11. 一种叉型结构的半导体器件，其特征在于，包括：
    衬底；
    垂直设置在所述衬底上的侧墙；
    沿着与所述衬底垂直的方向依次间隔设置在所述侧墙的一个侧面上的多个第一沟道层，所述第一沟道层沿着所述侧墙的侧面延伸；
    沿着与所述衬底垂直的方向依次间隔设置在所述侧墙的另一个侧面上的多个第二沟道层，所述第二沟道层沿着所述侧墙的侧面延伸；
    设置在所述多个第一沟道层两端的第一掺杂结构，设置在所述多个第二沟道层两端的第二掺杂结构，所述第一掺杂结构的掺杂类型与所述第二掺杂结构的掺杂类型相反；
    覆盖在所述多个第一沟道层的第一表面的一端和所述多个第二沟道层的第一表面的一端的第一介质层，覆盖在所述多个第一沟道层的第一表面的另一端和所述多个第二沟道层的第一表面的另一端的第二介质层，其中，所述多个第一沟道层的第一表面为所述多个第一沟道层中远离所述侧墙的表面，所述多个第二沟道层的第一表面为所述多个第二沟道层中远离所述侧墙的表面；
    设置在所述多个第一沟道层的第二表面的两端的第三介质层，设置在所述多个第二沟道层的第二表面的两端的第四介质层，其中，所述多个第一沟道层的第二表面为所述多个第一沟道层中与其第一表面相邻且与所述衬底平行的表面，所述多个第二沟道层的第二表面为所述多个第二沟道层中与其第一表面相邻且与所述衬底平行的表面；
    依次设置在所述第一沟道层上的第一栅绝缘层和第一栅导电层，依次设置在所述第二沟道层上的第二栅绝缘层和第二栅导电层。
  12. 根据权利要求11所述的半导体器件，其特征在于，所述半导体器件还包括：
    位于所述衬底上的第五介质层，所述多个第一沟道层、所述多个第二沟道层、所述第一掺杂结构和所述第二掺杂结构位于所述第五介质层上。
  13. 根据权利要求11或12所述的半导体器件，其特征在于，所述第一栅绝缘层和所述第二栅绝缘层的材料相同，所述第一栅导电层和所述第二栅导电层的材料相同；或者
    所述第一栅导电层和所述第二栅导电层的材料相同。
  14. 根据权利要求11或12所述的半导体器件，其特征在于，位于所述第一介质层与所述第二介质层之间的侧墙被去除；
    所述第一沟道层中与去除的所述侧墙接触的表面上依次设置有所述第一栅绝缘层和第一栅导电层；
    所述第二沟道层中与去除的所述侧墙接触的表面上依次设置有所述第二栅绝缘层和第二栅导电层；
    所述第一栅绝缘层和所述第二栅绝缘层的材料相同，所述第一栅导电层和所述第二栅导电层的材料相同。
  15. 根据权利要求11～14中任一项所述的半导体器件，其特征在于，所述第一沟道层与所述第二沟道层的材料不同。
  16. 根据权利要求11～14中任一项所述的半导体器件，其特征在于，所述第一掺杂结构为P型掺杂，所述第二掺杂结构为N型掺杂，所述第一沟道层的材料为硅锗，所述第二沟道层的材料为硅。
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