WO2022087950A1

WO2022087950A1 - Time-of-flight measurement circuit and control method and electronic apparatus thereof

Info

Publication number: WO2022087950A1
Application number: PCT/CN2020/124743
Authority: WO
Inventors: 林奇青; 范铨奇; 杨富强
Original assignee: 深圳市汇顶科技股份有限公司
Priority date: 2020-10-29
Filing date: 2020-10-29
Publication date: 2022-05-05
Also published as: CN114270214A

Abstract

Provided are a time-of-flight measurement circuit and control method and electronic apparatus thereof. The time-of-flight measurement circuit (100, 400, 600) comprises a pixel array (102, 602), a first controller (104), and a time-to-digital converter (106, 406, 606). The pixel array (102,602) comprises m rows × n columns of pixel cells (P11–P1n, P21–P2n, ... Pm1–Pmn, P11'–P1n', P21'–P2n', ... Pm1'–Pmn'). The first controller (104) is coupled to the input end of a first buffer of each of the first column pixel units (P11–Pm1, P11'–Pm1'), and the input end of the first buffer of the pixel cell Pxy is coupled to the output end of the first buffer of the pixel cell Px(y-1), x being an integer from 1 to m, and y being an integer from 2 to n, wherein in a test mode, the first controller (104) transmits a first trigger signal sequentially by means of the first buffers Ba1 to Ban in the pixel cells Pa1 to Pan, a being any integer from 1 to m, and, if a is less than m, the first trigger signal arriving at the pixel cells Pm1–Pmn from the output ends of the pixel cells Pa1–Pan.

Description

Time-of-flight measurement circuit, control method and electronic device

technical field

The present application relates to a time-of-flight measurement circuit, and more particularly, to a time-of-flight measurement circuit capable of obtaining internal delay information in a test mode, as well as a related control method and electronic device.

Background technique

Time-of-flight measurement technology includes direct time-of-flight measurement technology and indirect time-of-flight measurement technology (also known as indirect time-of-flight measurement technology). and the time interval between the emitted light pulses, the time of flight of the light can be obtained, and then the depth information can be calculated from the measured time of flight. The difficulty of direct time-of-flight measurement technology is that it needs to be able to distinguish very fine time differences. For example, if a ranging accuracy of 1.5 cm is required, the resolution needs to be 10 picoseconds.

However, in reality, when the direct flight time measurement technology is implemented, various non-ideal errors may contribute errors to the measured flight time. Therefore, how to improve the accuracy has become one of the urgent problems to be solved in this field.

SUMMARY OF THE INVENTION

One of the objectives of the present application is to disclose a time-of-flight measurement circuit, a related control method and an electronic device to solve the above problems.

An embodiment of the present application discloses a time-of-flight measurement circuit, including: a pixel array, including m rows×n columns of pixel units, where m, n are positive integers, and each of the pixel units includes: a photosensitive sensor; and a first buffer, wherein the time that the first buffer delays the passing signal is a first buffer time delay; wherein the pixel unit outputs the sensing result of the photosensitive sensor in a general mode, and the The pixel unit outputs the buffered result output by the first buffer in the test mode; the first controller is coupled to the input end of the first buffer of each of the pixel units in the first column, and the first controller The input of the first buffer of the pixel unit at row x, column y is coupled to the output of the first buffer of the pixel unit at row x, column y-1, where x is 1 to m The integer of , y is an integer from 2 to n, wherein in the test mode, the first controller transmits a first trigger signal, so that the first trigger signal passes through the first to yth row of the xth row in sequence Each of the first buffers of the pixel units in the column, when x is less than m, the first trigger signal is further transmitted from the output end of the first buffer of the pixel unit in the xth row and the yth column through the output end of the first buffer. The output terminal of the pixel unit at the xth row and the yth column is output to the pixel unit at the (x+1)th row and the yth column until reaching the pixel unit at the mth row and the yth column; and a time-to-digital converter , including: a counter, coupled to the first controller, and counting according to a reference clock; n registers, including the first register to the nth register, correspondingly coupled to The n outputs of the pixel units in the 1st to nth columns of the mth row, wherein the yth temporary register is based on the a first trigger signal to temporarily store the first count value of the counter; and a first start time register, coupled to the input ends of the m first buffers of the m pixel units in the first column , for receiving the first trigger signal, and the first start time register temporarily stores the first start time count value of the counter according to the received first trigger signal.

An embodiment of the present application discloses a method for controlling a time-of-flight measurement circuit, including: controlling the time-of-flight measurement circuit to enter the test mode; using the first controller to transmit the a first trigger signal, so that the first trigger signal sequentially passes through the first buffer of each pixel unit in the pixel units in the xth row, the first column to the xth row and the nth column, so as to obtain: the first count value of the first start time; the first count value of the y-th register, which corresponds to the y-th first buffer delay and the x-th row and the y-th column of the pixel unit to the y-th the sum of the pixel path delays of the temporary register; and the reference count value of the reference register, which corresponds to m first buffer delays; according to the first start time count value and the reference count value to obtain the first buffer delay; according to the first start time count value and the first count value to obtain the first trigger signal through the xth row 1st to yth after the respective first buffers in the pixel units are listed, the total path delay transmitted to the y-th register through the pixel units in the y-th column x-th row to the m-th row; and according to the The first buffer delay and the total path delay obtain the pixel path delay from the pixel unit in the xth row and the yth column to the yth temporary register.

An embodiment of the present application discloses a method for controlling a time-of-flight measurement circuit, including: controlling the time-of-flight measurement circuit to enter the test mode; using the first controller to transmit the a first trigger signal, so that the first trigger signal sequentially passes through the first buffer of each pixel unit in the pixel units in the xth row, the first column to the xth row and the nth column, so as to obtain: the first count value of the first start time; the first count value of the y-th register, which corresponds to the y-th first buffer delay and the x-th row and the y-th column of the pixel unit to the y-th The sum of the pixel path delays of the temporary registers; and the first count value of the z-th temporary register, which corresponds to the z-th first buffer delay and the x-th row and the z-th column. The sum of the pixel path delays from the pixel unit to the z-th register, where z is an integer from 1 to n, and y and z are different integers; the second controller is used to transmit the The second trigger signal is to pass the second trigger signal through the second buffer of each pixel unit in the pixel units of the xth row and the nth column to the xth row and the first column in sequence, so as to obtain: the count value of the second start time; the second count value of the y-th temporary register, which corresponds to (n-y+1) delays of the second buffer and the x-th row and the y-th column The sum of the pixel path delays from the pixel unit to the y-th temporary register; and the second count value of the z-th temporary register, which corresponds to (n-y+1) all The sum of the delay of the second buffer and the delay of the pixel path from the pixel unit of the xth row and the zth column to the zth temporary register; according to the first start time count value, the yth The first count value of the register and the first count value of the z-th register are obtained to obtain the first trigger signal through the respective pixel units in the x-th row, the 1-th column, and the y-th column. After the first buffer, the first total path delay of the pixel units in the y-th column from the x-th row to the m-th row is transferred to the y-th temporary register, and the first trigger signal is obtained. After the respective first buffers of the pixel units in the 1st to zth columns of the xth row, the first buffer is transferred to the second buffer of the zth register through the pixel units of the zth column, the xth to the mth row. total path delay; the first count value is obtained according to the second start time count value, the second count value of the y-th temporary register, and the second count value of the z-th temporary register After the two trigger signals pass through the respective second buffers in the pixel units in the nth to yth columns in the xth row, they are then transmitted to the yth temporary through the pixel units in the yth column, from the xth to the mth row. The third total path delay of the register, and after the second trigger signal is obtained through the second buffers in the pixel units in the nth row and the zth column of the xth row, the second trigger signal passes through the zth column. to the fourth total path delay transferred from the pixel unit in the mth row to the zth register; and according to the first total path delay, the second total path delay, the third total path delay The path delay and the fourth total path delay are used to obtain the first buffer delay, the second buffer delay, the pixel unit in the xth row and the yth column to the yth temporary the pixel path delay of the register, and the pixel path delay from the pixel unit in the xth row and the zth column to the zth temporary register.

An embodiment of the present application discloses an electronic device including the above-mentioned time-of-flight measurement circuit.

An embodiment of the present application discloses an electronic device, including a time-of-flight measurement circuit, including: a pixel array, including m rows×n columns of pixel units, where m, n are positive integers, and each of the pixel units includes : a photosensitive sensor; and a first buffer, wherein the time that the first buffer delays the passing signal is the first buffer time delay; wherein the pixel unit outputs the sensing result of the photosensitive sensor in the general mode , and the pixel unit outputs the buffered result output by the first buffer in the test mode; and the controller is configured to: control the flight time measurement circuit to enter the general mode, so that the xth row and the yth column are The sensing result of the photosensitive sensor of the pixel unit outputs the corresponding first time-of-flight signal through the y-th temporary register, and makes the sensing result of the photosensitive sensor of the pixel unit in the x-th row and the z-th column. As a result, the corresponding second time-of-flight signal is output through the z-th temporary register; according to the first flight-time signal and the pixel path delay from the pixel unit in the x-th row and the y-th column to the y-th temporary register Obtain the corrected first flight time signal; and obtain the corrected second flight time signal according to the second flight time signal and the pixel path delay from the pixel unit in the xth row and the zth column to the zth temporary register time signal, wherein the pixel path delay from the pixel unit at the xth row and the yth column to the yth temporary register and the pixel path from the pixel unit at the xth row and the zth column to the zth temporary register The pixel path delay of the controller is measured by controlling the time-of-flight measurement circuit in the test mode by the controller.

The flight time measurement circuit of the present application can obtain the internal time delay information in the test mode, which can be used to correct the measured flight time to improve the accuracy.

Description of drawings

FIG. 1 is a schematic diagram of a first embodiment of a time-of-flight measurement circuit of the present application.

FIG. 2 is a circuit diagram of a pixel unit in the pixel array of FIG. 1 .

FIG. 3 is a schematic diagram for explaining a transmission manner of the first trigger signal in the time-of-flight measurement circuit of FIG. 1 .

FIG. 4 is a schematic diagram of a second embodiment of the time-of-flight measurement circuit of the present application.

FIG. 5 is a schematic diagram for explaining a transmission manner of the first trigger signal in the time-of-flight measurement circuit of FIG. 4 .

FIG. 6 is a schematic diagram of a third embodiment of the time-of-flight measurement circuit of the present application.

FIG. 7 is a circuit diagram of a pixel unit in the pixel array of FIG. 6 .

FIG. 8 is a schematic diagram for explaining a transmission manner of the second trigger signal in the time-of-flight measurement circuit of FIG. 6 .

FIG. 9 is a schematic diagram for illustrating the use of the first trigger signal and the second trigger signal to measure the time-of-flight measurement circuit of FIG. 6 .

Detailed ways

The following disclosure provides various implementations, or illustrations, that can be used to implement various features of the present disclosure. Specific examples of components and configurations are described below to simplify the present disclosure. As can be appreciated, these descriptions are exemplary only, and are not intended to limit the present disclosure. For example, in the description below, forming a first feature on or over a second feature may include some embodiments in which the first and second features are in direct contact with each other; and may also include Certain embodiments may have additional components formed between the first and second features described above, such that the first and second features may not be in direct contact. Furthermore, the present disclosure may reuse reference numerals and/or reference numerals in various embodiments. Such reuse is for brevity and clarity, and does not in itself represent a relationship between the different embodiments and/or configurations discussed.

Furthermore, the use of spatially relative terms, such as "below", "below", "below", "above", "above" and the like, may be used to facilitate the description of the drawings. relationship between one component or feature shown with respect to another component or feature. These spatially relative terms are intended to encompass many different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be positioned in other orientations (eg, rotated 90 degrees or at other orientations) and these spatially relative descriptors should be interpreted accordingly.

Notwithstanding that the numerical ranges and parameters setting forth the broader scope of the application are approximations, the numerical values set forth in the specific examples have been reported as precisely as possible. Any numerical value, however, inherently contains the standard deviation resulting from individual testing methods. As used herein, "about" generally means within plus or minus 10%, 5%, 1%, or 0.5% of the actual value of a particular value or range. Alternatively, the word "about" means that the actual value lies within an acceptable standard error of the mean, as considered by one of ordinary skill in the art to which this application pertains. It should be understood that all ranges, quantities, numerical values and percentages used herein (for example, to describe material amounts, time durations, temperatures, operating conditions, quantity ratios and other similar) are modified by "about". Therefore, unless otherwise stated to the contrary, the numerical parameters disclosed in this specification and the accompanying claims are approximate numerical values and may be changed as required. At a minimum, these numerical parameters should be construed to mean the number of significant digits indicated and the numerical values obtained by applying ordinary rounding. Numerical ranges are expressed herein as from one endpoint to the other or between the endpoints; unless otherwise indicated, the numerical ranges recited herein are inclusive of the endpoints.

In fact, when the direct flight time measurement technology is implemented, various non-ideal errors may contribute errors to the measured flight time, especially the delay of the transmission path inside the chip, which will directly affect the measured flight time. The time-of-flight measurement circuit and the control method of the present application can estimate the time delay of the above-mentioned transmission path inside the chip in the test mode, and use the time delay of the transmission path calculated in the test mode to calculate the time delay in the general mode. Correct the flight time. The details are described below.

FIG. 1 is a schematic diagram of a first embodiment of a time-of-flight measurement circuit of the present application. The time-of-flight measurement circuit 100 includes a pixel array 102 , a first controller 104 and a time-to-digital converter 106 . Specifically, the pixel array 102 includes m rows×n columns of pixel units, where m and n are positive integers. For example, the pixel unit P11 represents the pixel unit in the first row and the first column in the pixel array 102 , and the pixel unit Pmn represents the pixel unit The pixel unit in the mth row and the nth column in the array 102 .

Each pixel unit in the pixel array 102 includes a photosensitive sensor and a first buffer. Generally, the photosensitive sensor can be implemented by a single-photon avalanche diode, but the present application is not limited thereto. In addition, the time that the first buffer delays the passing signal is the first buffer delay TB1, and the first buffer delay TB1 of the first buffer of each pixel unit in the pixel array 102 is substantially the same as each other . The time-of-flight measurement circuit 100 has a general mode and a test mode. In the general mode, each pixel unit in the pixel array 102 outputs the sensing result of the photosensor, and in the test mode, it outputs the first The buffered result of the buffer output.

Please refer to FIG. 1 and FIG. 2 together. FIG. 2 is a circuit diagram of the pixel units P22 , P23 , P32 and P33 in the pixel array 102 . It should be noted that each pixel unit in the pixel array 102 is the same, so the pixel units P22, P23, P32 and P33 shown in FIG. 2 can also be used to describe other pixel units not shown. Taking the pixel unit P22 as an example, it can be seen that it further includes an OR gate O22 and an AND gate A22, wherein the first input terminal of the OR gate O22 is coupled to the photosensitive sensor D22, and the second input terminal of the OR gate O22 is used to obtain a The controller 104 receives the test mode enable signal TE, and the test mode enable signal TE is used to indicate that the time-of-flight measurement circuit 100 is currently in the test mode or the normal mode. The first input terminal of the AND gate A22 is coupled to the output terminal of the OR gate O22, and the second input terminal of the AND gate A22 is coupled to the output terminal of the first buffer B22.

Therefore, taking the pixel unit P22 as an example, in the general mode, the enable signal TE is 0 (low logic level), and the OR gate O22 will output the sensing result of the photosensor to the first gate of the AND gate A22 An input terminal, when RS2 is set to 1 (high logic level), it means to select and read the pixel units P21-P2n in the second row. At this time, the high logic level passes through the first buffer B22 to make the AND gate A22 The second input terminal is also at a high logic level, so that the AND gate A22 outputs the output of the OR gate O22, that is, outputs the sensing result of the photosensitive sensor.

In the test mode, also taking the pixel unit P22 as an example, the enable signal TE is 1 (high logic level), and the OR gate O22 will continue to output 1 (high logic level) to the first of the AND gate A22 The input terminal makes the output of the AND gate A22 follow the input of the second input terminal of the AND gate A22, even though the AND gate A22 outputs the buffered result output by the first buffer B22.

When the time-of-flight measurement circuit 100 is implemented in hardware, for example, when the time-of-flight measurement circuit 100 is implemented in a chip, on the layout (layout) of the integrated circuit, the first controller 104 is closer to the pixel units P11~ The side where Pm1 is located is correspondingly coupled to the input terminals of the first buffers B11 ˜Bm1 of the pixel units P11 ˜Pm1 in the first column through the paths RS1 ˜RSm, and the pixel units in the xth row and the yth column of the pixel units The input terminal of the first buffer is coupled to the output terminal of the first buffer of the pixel unit in the xth row and the y-1th column, where x is an integer from 1 to m, and y is an integer from 2 to n . For example, the input terminals of the first buffers B12-Bm2 of the pixel units P12-Pm2 in the second row are coupled to the output terminals of the first buffers B11-Bm1 in the pixel units P11-Pm1 in the first row, and so on. .

In the test mode, the first controller 104 can transmit the first trigger signal S1 to any row of pixel units in the pixel array 102 , for example, when transmitting the first trigger signal S1 to the pixel units Pa1 to Pan of the a-th row, where a is Any integer from 1 to m, the first controller 104 transmits the first trigger signal S1 through the path RSa, and the first trigger signal S1 sequentially passes through the first buffers Ba1-Ban in the pixel units Pa1-Pan of the a-th row, namely In Figure 1, a lateral transfer to the left is presented. After the first trigger signal S1 enters each pixel unit Pa1-Pan, it will also be output from the output end of each pixel unit Pa1-Pan to the input end of the next row of pixel units via AND gates Aa1-Aan, that is, in FIG. 1, It presents a downward vertical transmission, that is to say, when a is less than m, the first trigger signal S1 will be output from the respective output terminals of the pixel units Pa1-Pan in the a-th row, and then pass through the (a+1)th row in sequence. to the pixel unit of the mth row; when a is equal to m, the first trigger signal S1 is directly output from the respective output terminals of the pixel units Pm1 to Pmn of the mth row to the time-to-digital converter 106 outside the pixel array 102 .

The time-to-digital converter 106 includes a counter 108, n registers L1-Ln and a first start time register LS1. The counter 108 counts according to the reference clock. The n registers L1-Ln include registers L1 to Ln. When the time-of-flight measurement circuit 100 is implemented in hardware, for example, when the time-of-flight measurement circuit 100 is implemented in chips, the layout of the integrated circuit , the registers L1-Ln are located on the side of the adjacent pixel units Pm1-Pmn, and are correspondingly coupled to the n output terminals of the pixel units Pm1-Pmn. The registers L1-Ln are based on the slave pixel units Pm1-Pmn The first trigger signal S1 received by the n output terminals of Pmn temporarily stores the first count value of the counter 108 . That is to say, when the pixel unit Pm1 outputs the first trigger signal S1 to the register L1, the register L1 temporarily stores the counting result of the counter 108 as the first count value. In this embodiment, the counter 108 is coupled to the first controller 104, and the first controller 104 can reset the counter 108, that is, clear the counter 108 to zero.

FIG. 3 is a schematic diagram for explaining a transmission manner of the first trigger signal S1 in the time-of-flight measurement circuit 100 . In FIG. 3, the first controller 104 transmits the first trigger signal S1 through the path RS1, and the first trigger signal S1 will pass through all the pixel units P11-P1n in the first row in sequence to the left, and continue from the pixel units in the first row P11 to P1n respectively pass through all the pixel units in the 2nd to the mth row downwards in sequence, and then output to the temporary registers L1 to Ln. From leaving the first controller 104 to entering the registers L1-Ln, the first trigger signal S1 will pass through n different paths, namely D11-D1n, and the total path delays caused by the n paths D11-D1n are different. As a result, the time at which the registers L1 to Ln receive the first trigger signal S1 are different, and the corresponding registers L1 to Ln temporarily store the first count values output by the counter 108 at different times respectively, that is, the number of the n registers. The temporarily stored n first count values are also different. Generally speaking, the total path delay caused by the n paths D11 ˜ D1 n increases sequentially, and therefore, the n first count values temporarily stored in the registers L1 ˜ Ln also increase sequentially.

The first start time register LS1 is coupled to the input terminals of the m first buffers of the m pixel units P11 ˜Pm1 in the first column. When the unit transmits the first trigger signal S1, the first start time register LS1 receives the first trigger signal S1 and temporarily stores the first start time count value of the counter 108 according to the received first trigger signal S1. Therefore, by deducting the first count value of the first start time of the first start time register LS1 from the n first count values temporarily stored in the registers L1 ˜ Ln respectively, the n paths caused by D11 ˜ D1n can be obtained. Total path delays T11 to T1n.

Therefore, for the pixel units in the first row to the mth row in the pixel array 102, the first controller 104 transmits the first trigger signal S1 to the temporary registers L1-Ln through different paths RS1-RSm, and there are n paths respectively, namely There are a total of n*m paths D11-D1n, D21-D2n, D31-D3n, ..., Dm1-Dmn. When the time-of-flight measurement circuit 100 is to be tested, the test mode enable signal TE can be used to control the time-of-flight measurement circuit 100 to enter the test mode, and then the pixels in the first row to the mth row in the pixel array 102 can be tested. The unit obtains n*m paths D11-D1n, D21-D2n, D31-D3n, . . . , Dm1-Dmn in m times in the manner of FIG. 3 . It can be seen from Figure 3 that:

Total path delay Tab = b*TB1 + delay from Pab to Lb (1)

, where a is any integer from 1 to m, and b is any integer from 1 to n. For example, the total path delay caused by the path D11 is T11=1*the first buffer delay TB1+the pixel path delay from the pixel unit P11 to the register L1, the total path delay caused by the path D12 is T12=2*the first A buffer delay TB1 + pixel path delay from pixel unit P12 to register L2, and so on. In some embodiments, when the first controller 104 transmits the first trigger signal S1 , the counter 108 can be reset at the same time to prevent the counter 108 from overflowing. It should be noted that the above-mentioned pixel path delay from Pab to Lb includes the sum of the delay of AND gate Aab and the delay from the output of AND gate Aab to Lb according to the circuit diagram embodiment of the pixel unit in FIG. 2 .

4 is a schematic diagram of a second embodiment of the time-of-flight measurement circuit of the present application. The difference between the time-of-flight measurement circuit 400 and the time-of-flight measurement circuit 100 is that the time-to-digital converter 406 of the time-of-flight measurement circuit 400 is compared with A reference register LR is added to the time-to-digital converter 106 of the time-of-flight measurement circuit 100, and the reference register LR is coupled to the m first buffers of the m pixel units in the n-th column of the pixel array 102. The output terminal is used for receiving the first trigger signal S1, and the reference register LR temporarily stores the reference count value of the counter 108 according to the received first trigger signal S1. The purpose of the reference register LR is explained as follows.

FIG. 5 is a schematic diagram for explaining the transmission method of the first trigger signal S1 in the time-of-flight measurement circuit 400. As shown in FIG. In Fig. 5, in addition to the n*m paths D11-D1n, D21-D2n, D31-D3n, ..., Dm1-Dmn, there are also m paths D1R-DmR that do not pass through in the downward vertical transmission Any pixel unit directly reaches the reference register LR. Assuming that the path that does not pass through the pixel unit does not generate a delay during the downward vertical transmission, the total path delays T1R-TmR caused by the paths D1R-DmR are all equal and equal to n*the first buffer delay TB1. Therefore, by deducting the first start time count value of the first start time register LS1 from the reference count value temporarily stored in the reference register LR, the total path delays T1R to TmR caused by the paths D1R to DmR can be obtained, Divide by n again to obtain the first buffer delay TB1. The pixel path delay from Pab to Lb can be obtained by taking the first buffer delay TB1 into equation (1), where a is any integer from 1 to m, and b is any integer from 1 to n. Therefore, after the time-of-flight measurement circuit 400 introduces the reference register LR, the first buffer delay TB1 and the pixel path delay from Pab to Lb can be further obtained.

6 is a schematic diagram of a third embodiment of the time-of-flight measurement circuit of the present application. The difference between the time-of-flight measurement circuit 600 and the time-of-flight measurement circuit 100 is that each of the pixel arrays 602 of the time-of-flight measurement circuit 600 The pixel unit also includes a second buffer, wherein the second buffer delays passing signals by a second buffer delay TB2, and each pixel unit outputs the first buffer or the The buffered result output by the second buffer. In addition, a second controller 604 is added to the flight time measurement circuit 600, and the time-to-digital converter 106 further includes a second start time register LS2.

Please refer to FIG. 6 and FIG. 7 together. FIG. 7 is a circuit diagram of the pixel units P22 ′, P23 ′, P32 ′ and P33 ′ in the pixel array 602 . It should be noted that each pixel unit in the pixel array 602 is the same, so the pixel units P22', P23', P32' and P33' shown in FIG. 7 can also be used to describe other not-shown pixel units. Taking the pixel unit P22' as an example, it can be seen that it further includes a first OR gate O22, a second OR gate O22' and an AND gate A22, wherein the first input end of the first OR gate O22 is coupled to the photosensitive sensor D22, and the first OR gate O22 is coupled to the photosensitive sensor D22. The second input terminal of the OR gate O22 is used to receive the test mode enable signal TE from the first controller 104 and the second controller 604. The test mode enable signal TE is used to indicate that the time-of-flight measurement circuit 100 is currently in the Test mode or the general mode described. The first input terminal of the second OR gate O22' is coupled to the output terminal of the first buffer B22, and the second input terminal of the second OR gate O22' is coupled to the output terminal of the second buffer B22'. The first input terminal of the AND gate A22 is coupled to the output terminal of the first OR gate O22, and the second input terminal of the AND gate A22 is coupled to the output terminal of the second OR gate O22'.

When the time-of-flight measurement circuit 100 is implemented in hardware, for example, when the time-of-flight measurement circuit 100 is implemented in a chip, on the layout of the integrated circuit, the second controller 604 is closer to the pixel units P1n' to Pmn' in the nth row adjacent to each other. on the side where it is located, and are correspondingly coupled to the input terminals of the second buffers B11 ′-Bm1 ' of the pixel units P1n'-Pmn' in the n-th column through the paths RS1'-RSm', and the y-th row of the x-th row is y- The input terminal of the second buffer of the pixel unit in column 1 is coupled to the output terminal of the second buffer of the pixel unit in the xth row and the yth column, where x is an integer from 1 to m, and y is An integer from 2 to n. For example, the input terminals of the second buffers B11'-Bm1' of the pixel units P11'-Pm1' in the first row are coupled to the second buffers B12'-Bm2' of the pixel units P12'-Pm2' in the second row output, and so on.

In the test mode, the second controller 604 can transmit the second trigger signal S2 for any row of pixel units in the pixel array 602 , for example, when transmitting the second trigger signal S2 for the pixel units Pan′˜Pa1 ′ in the a-th row, wherein a is any integer from 1 to m, the second controller 604 transmits the second trigger signal S2 through the path RSa', and the second trigger signal S2 sequentially passes through the second buffers in the pixel units Pan'-Pa1' in the a-th row Ban'-Ba1', that is, in the case of Fig. 6, present the lateral transfer to the right. After the second trigger signal S2 enters each pixel unit Pan'-Pa1', it will also be output from the output end of each pixel unit Pan'-Pa1' to the input end of the next row of pixel units via AND gates Aan'-Aa1', that is, Referring to FIG. 6 , the vertical transmission is downward, that is to say, when a is less than m, the second trigger signal S2 will be output from the respective output terminals of the pixel units Pan' to Pa1' in the a-th row, and then sequentially. Through the (a+1)th row to the mth row of pixel units; when a is equal to m, the second trigger signal S2 will be directly output from the respective output terminals of the mth row of pixel units Pmn' to Pm1' to the outside of the pixel array 102 The time-to-digital converter 606.

For the second trigger signal S2, the registers Ln-L1 temporarily store the second count value of the counter 108 based on the second trigger signal S2 received from the n output terminals of the pixel units Pmn-Pm1, respectively. That is, when the pixel unit Pmn outputs the second trigger signal S2 to the register Ln, the register Ln temporarily stores the counting result of the counter 108 as the second count value. In this embodiment, the counter 108 is further coupled to the second controller 604 , and the second controller 604 can reset the counter 108 , that is, clear the counter 108 to zero.

FIG. 8 is a schematic diagram for explaining a transmission manner of the second trigger signal S2 in the time-of-flight measurement circuit 600 . In FIG. 8 , the second controller 604 transmits the second trigger signal S2 through the path RS1 ′, and the second trigger signal S2 will pass through the first row of pixel units P1n ′ to P11 ′ in sequence to the right, and continue from the first row of pixel units P1n'-P11' respectively pass through the pixel units in the 2nd to the m-th row downward in sequence, and then output to the temporary registers Ln-L1. From leaving the second controller 604 to entering the registers Ln-L1, the second trigger signal S2 passes through n different paths, namely D1n'-D11', and the total path delay caused by the n paths D1n'-D11' are different, resulting in different times at which the registers Ln-L1 receive the second trigger signal S2, and the corresponding registers Ln-L1 temporarily store the second count values output by the counter 108 at different times, that is, n The n second count values temporarily stored in the temporary register are also different. Generally speaking, the total path delay caused by the n paths D1n'-D11' increases in sequence, so the n second count values temporarily stored in the registers Ln-L1 also increase in sequence.

The second start time register LS2 is coupled to the input terminals of the m second buffers of the m pixel units P1n' to Pmn' in the nth column. Therefore, when the second controller 604 wants to When any row of pixel units transmits the second trigger signal S2, the second start time register LS2 will also receive the second trigger signal S2, and temporarily store the second start time of the counter 108 according to the received second trigger signal S2. Start time count value. Therefore, by deducting the second start time count value of the second start time register LS2 from the n second count values temporarily stored in the registers Ln to L1, n paths D1n' to D11 can be obtained. 'The total path delay caused by T1n'～T11'.

Therefore, for the pixel units in the first row to the mth row in the pixel array 602, the second controller 604 transmits the second trigger signal S2 to the temporary registers Ln-L1 through different paths RS1-RSm, and there are n paths respectively, namely There are a total of n*m paths D1n' to D11', D2n' to D21', D3n' to D31', ..., Dmn' to Dm1'. When the time-of-flight measurement circuit 600 is to be tested, the test mode enable signal TE can be used to control the time-of-flight measurement circuit 600 to enter the test mode, and then the pixels in the first row to the mth row in the pixel array 602 can be tested. The unit obtains n*m paths D1n' to D11', D2n' to D21', D3n' to D31', . . . , Dmn' to Dm1' in m times in the manner of FIG. 8 . It can be seen from Figure 8 that:

Total path delay Tab'=(n-b+1)*TB2+Pab' to Lb delay (2)

, where a is any integer from 1 to m, and b is any integer from 1 to n. For example, the total path delay T11' caused by the path D11'=n*the second buffer delay TB2+the pixel path delay from the pixel unit P11' to the register L1, the total path delay TD12 caused by the path D12' =(n-1)*second buffer delay TB2+pixel path delay from pixel unit P12' to temporary register L2, and so on. In some embodiments, when the second controller 604 transmits the second trigger signal S2, the counter 108 may be reset at the same time to prevent the counter 108 from overflowing.

In addition, when using the first controller 104 to transmit the first trigger signal S1, equation (1) can be rewritten as:

Tab=b*TB1+Pab' to Lb pixel path delay (3)

Using the first controller 104 together with the second controller 604, the time-of-flight measurement circuit 400 can further obtain the first buffer delay TB1, the second buffer delay TB2 and the pixel path time from Pab' to Lb extension. The specific description is shown in FIG. 9 .

In Figure 9, use:

Total path delay of path D12 T12=2*TB1+P12' to pixel path delay of L2

(4)

The total path delay of the path D1n T1n=n*TB1+P1n' to the pixel path delay of Ln

(5)

Total path delay of path D12' T12'=(n-1)*TB2+P12' to pixel path delay of L2 (6)

Total path delay of path D1n' T1n'=1*TB2+P1n' to pixel path delay of Ln

(7)

With a total of four unknowns (first buffer delay TB1, second buffer delay TB2, pixel path delay from P12' to L2, pixel path delay from P1n' to Ln), four The four measured total path delays (T12, T1n, T12', T1n') obtained from the paths (D12, D1n, D12', D1n') are brought into equations (4) to (7) to obtain Four unknowns, therefore, the embodiment of FIG. 9 has the same effect as the embodiment of FIG. 5 .

The present application also provides a chip, which includes the time-of-flight measurement circuit 100/400/600. The present application also provides an electronic device including the time-of-flight measurement circuit 100/400/600 or the chip. The electronic device may be any electronic device such as a smart phone, a personal digital assistant, a handheld computer system, a tablet computer or a digital camera.

The time-of-flight measurement circuit 100/400/600 of the present application can obtain the pixels of the first control circuit 104 and/or the second control circuit 604 arriving at the time-to-digital converter 106/406/606 through the pixel array 102/602 in the test mode path delay, and for the paths D11~D1n, D21~D2n, D31~D3n, ..., Dm1~Dmn passing through each pixel unit, a pixel path delay can be estimated separately, which is more efficient than the general practice. Accurate, when the flight time measurement circuit 100/400/600 is used for the calibration of the flight time measurement in the normal mode, the accuracy of the flight time measurement can be improved. Taking FIG. 5 as an example, when measuring the flight time in the general mode, when RS2 is set to 1 (high logic level), it means that the pixel units P21 to P2n in the second row are selected to be read. When the photosensitive sensor D21 of the sensor detects the reflected photons, the sensing result passes through the OR gate O21 and the AND gate A23 and then transmits it vertically downwards, and reaches the temporary register L1 through the pixel units P31~Pm1. The delay during this time is not a flight. time, but an additional delay. However, the present application can pre-estimate the delay during this period, that is, it is close to the pixel path delay from P21 to Lb calculated in the embodiments of FIG. 5 and FIG. The calculated pixel path delay from P21 to Lb does not include the delay of OR gate O21). In this way, the accuracy of the flight time can be further improved by deducting the pixel path delay from P21 to Lb from the flight time obtained by the time-to-digital converter.

In addition, each embodiment of the above-mentioned control method of the time-of-flight measurement circuit in the test mode and the general mode can be performed using a controller (not shown in the figure), and the controller can be located in the Inside or outside the time of flight measurement circuit, or partially within the time of flight measurement circuit and partially outside the time of flight measurement circuit.

The foregoing description briefly sets forth features of certain embodiments of the application, so that those skilled in the art to which this application pertains can more fully understand the various aspects of the present disclosure. It should be apparent to those skilled in the art to which this application pertains that they can readily use the present disclosure as a basis to design or modify other processes and structures for carrying out the same purposes and/or of the embodiments described herein achieve the same advantages. Those with ordinary knowledge in the technical field to which this application belongs should understand that these equivalent embodiments still belong to the spirit and scope of the present disclosure, and various changes, substitutions and alterations can be made without departing from the spirit of the present disclosure. with scope.

Claims

A time-of-flight measurement circuit, comprising:

A pixel array, including m rows×n columns of pixel units, where m, n are positive integers, and each of the pixel units includes:

photosensors; and

a first buffer, wherein the time by which the first buffer delays the passing signal is the first buffer delay;

wherein the pixel unit outputs the sensing result of the photosensitive sensor in the general mode, and the pixel unit outputs the buffering result output by the first buffer in the test mode;

a first controller coupled to the input of the first buffer of each of the pixel units in the first column, and the input of the first buffer of the pixel unit in the xth row and the yth column The terminal is coupled to the output terminal of the first buffer of the pixel unit in the xth row and the y-1th column, where x is an integer from 1 to m, and y is an integer from 2 to n, wherein in the test mode , the first controller transmits a first trigger signal, so that the first trigger signal sequentially passes through the first buffers of the pixel units in the 1st to yth columns of the xth row, when x is less than m When , the first trigger signal is further output from the output end of the first buffer of the pixel unit at the xth row and the yth column to the output end of the pixel unit at the xth row and the yth column. (x+1) the pixel unit of row y column until reaching the pixel unit of row m and column y; and

Time-to-digital converters, including:

a counter, coupled to the first controller, and counting according to a reference clock;

n registers, including the first register to the nth register, are correspondingly coupled to the n output ends of the pixel units in the mth row, the 1st to the nth column, wherein, The y-th temporary register temporarily stores the first count value of the counter based on the first trigger signal received from the output terminal of the pixel unit in the m-th row and the y-th column; and

a first start time register, coupled to the input ends of the m first buffers of the m pixel units in the first column, for receiving the first trigger signal, the first start time The register temporarily stores the count value of the first start time of the counter according to the received first trigger signal.
The time-of-flight measurement circuit of claim 1, wherein each of the pixel units further comprises:

OR gate, wherein the first input terminal of the OR gate is coupled to the photosensitive sensor, and the second input terminal of the OR gate is used to receive a test mode enable signal from the first controller, the test mode an enable signal to indicate that the time-of-flight measurement circuit is currently in the test mode or the general mode; and

and gate, wherein the first input terminal of the AND gate is coupled to the output terminal of the OR gate, and the second input terminal of the AND gate is coupled to the output terminal of the first buffer.
The time-of-flight measurement circuit according to claim 1 or 2, wherein the time-to-digital converter further comprises:

a reference register, coupled to the output ends of the m first buffers of the m pixel units in the nth column, and used for receiving the first trigger signal, the reference register according to the received The first trigger signal temporarily stores the reference count value of the counter.
The time-of-flight measurement circuit of claim 1, wherein each of the pixel units further comprises:

a second buffer, wherein the second buffer delays the passing signal by a second buffer delay, and the pixel cell outputs the first buffer or the second buffer output in the test mode the buffered result;

The time-of-flight measurement circuit further includes:

a second controller coupled to the input terminal of the second buffer of each of the pixel units in the nth column, and the second buffer of the pixel unit in the xth row and the y-1th column The input terminal of t is coupled to the output terminal of the second buffer of the pixel unit in the xth row and the yth column, wherein in the test mode, the second controller transmits a second trigger signal to make the The second trigger signal passes through the respective second buffers of the pixel units in the nth to yth columns of the xth row in sequence. When x is less than m, the second trigger signal further starts from the xth row and the yth The output terminal of the second buffer of the pixel unit of the column is output to the pixel unit of the (x+1)th row and the yth column through the output terminal of the pixel unit of the xth row and the yth column until reaching the The pixel unit of the mth row and the yth column;

wherein the counter is further coupled to the second controller, and the time-to-digital converter further includes:

The second start time register is coupled to the input ends of the m second buffers of the m pixel units in the nth column, and is used for receiving the second trigger signal. The second start time register The start time register temporarily stores the second start time count value of the counter according to the received second trigger signal, wherein the n registers are respectively based on each pixel unit from the mth row. The second trigger signal received by one output terminal is used to temporarily store the second count value of the counter.
The time-of-flight measurement circuit of claim 4, wherein each of the pixel units further comprises:

a first OR gate, wherein a first input of the first OR gate is coupled to the photosensor, and a second input of the first OR gate is used to receive a test mode enable from the first controller a signal, the test mode enable signal is used to indicate that the time-of-flight measurement circuit is currently in the test mode or the general mode;

A second OR gate, wherein the first input terminal of the second OR gate is coupled to the output terminal of the first buffer, and the second input terminal of the second OR gate is coupled to the second buffer the output; and

AND gate, wherein the first input terminal of the AND gate is coupled to the output terminal of the first OR gate, and the second input terminal of the AND gate is coupled to the output terminal of the second OR gate.
A control method for the time-of-flight measurement circuit according to claim 3, characterized in that, comprising:

controlling the flight time measurement circuit to enter the test mode;

The first trigger signal is transmitted by the first controller at a first time point, so that the first trigger signal sequentially passes through each of the pixel units in the pixel units in the xth row and the first column to the xth row and the nth column. The first buffer of a pixel unit to obtain:

the first start time count value;

The first count value of the y-th register corresponds to the y-th first buffer delay and the pixel path from the pixel unit at the x-th row and the y-th column to the y-th register the sum of the delays; and

the reference count value of the reference register, which corresponds to m delays of the first buffer;

obtaining the first buffer delay according to the first start time count value and the reference count value;

After the first trigger signal is obtained according to the first start time count value and the first count value and passes through the respective first buffers in the pixel units of the xth row, the 1st to the yth column, and then the total path delay passed from the pixel units in the yth column xth to the mth row to the yth register; and

The pixel path delay from the pixel unit in the xth row and the yth column to the yth temporary register is obtained according to the first buffer delay and the total path delay.
The control method of claim 6, further comprising:

The counter is reset at the first point in time with the first controller.
The control method of claim 6, further comprising:

controlling the flight time measurement circuit to enter the general mode, so that the sensing result of the photosensitive sensor of the pixel unit in the xth row and the yth column outputs the corresponding flight time signal through the yth temporary register; and

The modified time-of-flight signal is obtained according to the time-of-flight signal and the pixel path delay from the pixel unit in the x-th row and the y-th column to the y-th temporary register.
A control method for the time-of-flight measurement circuit according to claim 4 or 5, characterized in that, comprising:

controlling the flight time measurement circuit to enter the test mode;

The first trigger signal is transmitted by the first controller at a first time point, so that the first trigger signal sequentially passes through each of the pixel units in the pixel units in the xth row and the first column to the xth row and the nth column. The first buffer of a pixel unit to obtain:

the first start time count value;

The first count value of the y-th register corresponds to the y-th first buffer delay and the pixel path from the pixel unit at the x-th row and the y-th column to the y-th register the sum of the delays; and

The first count value of the z-th register corresponds to the z-th first buffer delay and the pixel path from the pixel unit at the x-th row and the z-th column to the z-th register The sum of delays, where z is an integer from 1 to n, and y and z are different integers;

The second trigger signal is transmitted by the second controller at a second time point, so that the second trigger signal sequentially passes through each pixel unit in the pixel unit of the xth row and the nth column to the xth row and the first column. The second buffer of a pixel unit to obtain:

the second start time count value;

The second count value of the y-th register corresponds to (n-y+1) delays of the second buffer and the pixel units in the x-th row and the y-th column to the y-th the sum of the pixel path delays of the scratchpad; and

The second count value of the z-th register corresponds to (n-y+1) delays of the second buffer and the pixel units in the x-th row and the z-th column to the z-th the sum of the pixel path delays of the scratchpad;

According to the first start time count value, the first count value of the y-th register, and the first count value of the z-th register, the first trigger signal is obtained through the x-th register. After the respective first buffers in the pixel units in the 1st to the yth column, the first buffer is transferred to the first buffer of the yth register through the pixel units in the yth column, the xth to the mth row. path delay, and after obtaining the first trigger signal through the respective first buffers in the pixel units in the xth row, the 1st to the zth column, and then through the zth column, the xth to the mth row, the the second total path delay from the pixel unit to the z-th temporary register;

The second trigger signal is obtained according to the second start time count value, the second count value of the y-th register, and the second count value of the z-th register. After each of the second buffers in the pixel units in the nth to yth columns of the xth row, it is then transferred to the third buffer of the yth register through the pixel units of the yth column from the xth to the mth row. The total path delay is obtained, and after the second trigger signal passes through the respective second buffers in the pixel units in the nth row of the xth row to the zth column, and then passes through the zth row of the xth to the mth row. a fourth total path delay for the pixel unit to pass to the z-th register; and

According to the first total path delay, the second total path delay, the third total path delay and the fourth total path delay, the first buffer delay, the Two buffer delays, the pixel path delay from the pixel unit at the xth row and the yth column to the yth temporary register, and the pixel unit at the xth row and the zth column from the pixel unit to the zth temporary buffer the pixel path delay of the device.
The control method of claim 9, further comprising:

using the first controller to reset the counter at the first point in time; and

The counter is reset at the second point in time with the second controller.
The control method of claim 9, further comprising:

Controlling the flight time measurement circuit to enter the general mode, so that the sensing result of the photosensitive sensor of the pixel unit in the xth row and the yth column outputs the corresponding first flight time signal through the yth temporary register , and make the sensing result of the photosensitive sensor of the pixel unit in the xth row and the zth column output the corresponding second time-of-flight signal through the zth temporary register;

obtaining a corrected first time-of-flight signal according to the first time-of-flight signal and the pixel path delay from the pixel unit in the x-th row and the y-th column to the y-th temporary register; and

The corrected second time-of-flight signal is obtained according to the second time-of-flight signal and the pixel path delay from the pixel unit in the x-th row and the z-th column to the z-th temporary register.
An electronic device, comprising:

The time-of-flight measurement circuit of claim 1 .
An electronic device, comprising:

Time-of-flight measurement circuit, including:

A pixel array, including m rows×n columns of pixel units, where m, n are positive integers, and each of the pixel units includes:

photosensors; and

a first buffer, wherein the time by which the first buffer delays the passing signal is the first buffer delay;

wherein the pixel unit outputs a sensing result of the photosensitive sensor in a general mode, and the pixel unit outputs a buffered result output by the first buffer in a test mode; and

Controller for:

Controlling the flight time measurement circuit to enter the general mode, so that the sensing result of the photosensitive sensor of the pixel unit in the xth row and the yth column outputs the corresponding first flight time signal through the yth temporary register , and make the sensing result of the photosensitive sensor of the pixel unit in the xth row and the zth column output the corresponding second time-of-flight signal through the zth temporary register;

obtaining a corrected first time-of-flight signal according to the first time-of-flight signal and the pixel path delay from the pixel unit in the x-th row and the y-th column to the y-th temporary register; and

obtaining a corrected second time-of-flight signal according to the second time-of-flight signal and the pixel path delay from the pixel unit in the x-th row and the z-th column to the z-th temporary register,

Wherein, the pixel path delay from the pixel unit in the x-th row and the y-th column to the y-th temporary register and the pixel from the pixel unit in the x-th row and the z-th column to the z-th temporary register The path delay is measured by the controller controlling the flight time measurement circuit in the test mode.