WO2022082936A1 - 一种负显影光刻工艺的全芯片快速仿真方法、负显影光刻胶模型、opc模型及电子设备 - Google Patents

一种负显影光刻工艺的全芯片快速仿真方法、负显影光刻胶模型、opc模型及电子设备 Download PDF

Info

Publication number
WO2022082936A1
WO2022082936A1 PCT/CN2020/133696 CN2020133696W WO2022082936A1 WO 2022082936 A1 WO2022082936 A1 WO 2022082936A1 CN 2020133696 W CN2020133696 W CN 2020133696W WO 2022082936 A1 WO2022082936 A1 WO 2022082936A1
Authority
WO
WIPO (PCT)
Prior art keywords
photoresist
equation
full
negative development
model
Prior art date
Application number
PCT/CN2020/133696
Other languages
English (en)
French (fr)
Inventor
高世嘉
谢理
Original Assignee
东方晶源微电子科技（北京）有限公司深圳分公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 东方晶源微电子科技（北京）有限公司深圳分公司 filed Critical 东方晶源微电子科技（北京）有限公司深圳分公司
Priority to KR1020237017402A priority Critical patent/KR20230087605A/ko
Publication of WO2022082936A1 publication Critical patent/WO2022082936A1/zh
Priority to US18/305,350 priority patent/US20230384692A1/en

Links

Images

Classifications

    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
    • G03F7/70491—Information management, e.g. software; Active and passive control, e.g. details of controlling exposure processes or exposure tool monitoring processes
    • G03F7/705—Modelling or simulating from physical phenomena up to complete wafer processes or whole workflow in wafer productions
    • G03F7/70504—Optical system modelling, e.g. lens heating models
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/20—Design optimisation, verification or simulation
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/36—Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/68—Preparation processes not covered by groups G03F1/20 - G03F1/50
    • G03F1/70—Adapting basic layout or design of masks to lithographic process requirements, e.g., second iteration correction of mask patterns for imaging
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/0002—Lithographic processes using patterning methods other than those involving the exposure to radiation, e.g. by stamping
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
    • G03F7/70491—Information management, e.g. software; Active and passive control, e.g. details of controlling exposure processes or exposure tool monitoring processes
    • G03F7/705—Modelling or simulating from physical phenomena up to complete wafer processes or whole workflow in wafer productions
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
    • G03F7/70605—Workpiece metrology
    • G03F7/70616—Monitoring the printed patterns
    • G03F7/70625—Dimensions, e.g. line width, critical dimension [CD], profile, sidewall angle or edge roughness
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/10—Complex mathematical operations
    • G06F17/11—Complex mathematical operations for solving equations, e.g. nonlinear equations, general mathematical optimization problems
    • G06F17/13—Differential equations
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
    • G06F2119/14—Force analysis or force optimisation, e.g. static or dynamic forces

Definitions

  • the invention relates to the technical field of integrated circuit lithography, in particular to a full-chip fast simulation method of a negative development lithography process, a negative development photoresist model, an OPC model and an electronic device.
  • the lithography process is the most important manufacturing process in the modern VLSI manufacturing process, that is, an important means to transfer the design pattern of the integrated circuit on the mask to the silicon wafer through the lithography machine.
  • the process window available for manufacturing is getting smaller and smaller, the entire lithography process needs to be precisely controlled, and the requirements for the accuracy of computational lithography are getting higher and higher.
  • An accurate computational lithography model can theoretically explore ways to increase the lithography resolution and process window, and guide the optimization of process parameters.
  • the more advanced photoresist technology is negative development.
  • the negative development technique is different from the positive development technique in the modeling process.
  • the deformation of the photoresist mainly depends on the distribution of the acid of the photoresist after the photoresist reaction, that is, the distribution of the light field. Since the imaging optical simulation process of computational lithography can be calculated more accurately based on the physical imaging model, it is easy to obtain more accurate results for the photoresist modeling of forward development.
  • the photoresist developed in the negative direction due to the thermal shrinkage effect of the photoresist during the post-baking process, the photoresist will generate additional deformation beyond the light field distribution, and this part of the deformation is very difficult to capture.
  • this effect It is also very important for the modeling of negative developing photoresist.
  • the size of a chip can be up to 32mm*26mm, the line width of the smallest pattern may be only 10nm, and the layout file of a lithography layer can reach hundreds of GB, so the model speed is very critical. technical indicators. Therefore, a model that takes into account the accuracy and speed is needed to simulate the negative development photoresist.
  • the present invention provides a full-chip fast simulation method of a negative development lithography process, and a negative development photoresist. Models, OPC models and electronic equipment.
  • the thermal shrinkage effect in the process is elastic deformation.
  • the elastic deformation of the photoresist is analyzed based on elastic mechanics, and one of stress and strain is set as the equivalent of the photoresist deformation variable to obtain an equivalent equation.
  • the equation is a differential equation; and S3, select Taylor expansion to approximate the equivalent equation to obtain an approximate value of stress or strain, and adjust the light field distribution according to the approximate value to obtain a suitable acid concentration distribution.
  • the obtaining of the equivalent equation includes the following steps: S21, the external force is correlated with the stress through the balance equation, the stress is correlated with the strain through the physical equation, and the strain is correlated with the displacement through the geometric equation; and S22.
  • the photoresist is set as a plane, so as to simplify the balance equation, the physical equation and the geometric equation.
  • the present invention also provides an electronic device, which includes one or more processors; a storage device for storing one or more programs, when the one or more programs are stored by the one or more programs
  • the processor executes such that the one or more processors implement any of the methods described above.
  • the deformation of the photoresist is analyzed based on elastic mechanics, and one of stress and strain is set as the equivalent of the photoresist deformation variable to obtain an equivalent equation, and the Taylor expansion is used to analyze the above and the like.
  • the effect equation is approximated to obtain the approximate value of stress or strain, and the light field distribution is adjusted according to the approximate value to obtain a suitable acid concentration distribution, so that the exposure pattern is the closest to the target pattern, which can be very good for the thermal shrinkage effect process.
  • the deformation of the photoresist is analyzed to improve the accuracy of the lithography calculation process.
  • the Taylor expansion is used to fit the thermal shrinkage effect to improve the calculation speed. Therefore, the complex calculation of the full-chip negative development lithography process is solved. The problem.
  • the photoresist is set as a plane, thereby simplifying the equilibrium equation, the physical equation and the geometric equation, so that the simplified equivalent equation and Taylor expansion Therefore, the differential solution of the equivalent equation is not required, which can improve the calculation speed and ensure the accuracy.
  • the negatively developed photoresist model, OPC model and electronic device provided by the present invention also have the above beneficial effects.
  • Fig. 1 is the flow chart of the whole-chip fast simulation method of the negative development lithography process provided in the first embodiment of the present invention
  • FIG. 2 is a schematic diagram of a differential unit cell corresponding to the photoresist in the present invention.
  • step S2 in the full-chip rapid simulation method of the negative development lithography process provided in the first embodiment of the present invention
  • FIG. 4 is a schematic diagram of the initial light field distribution in the negative development photoresist model provided by the second embodiment of the present invention.
  • FIG. 5 is a schematic diagram of the light field distribution after the negative development photoresist model provided by the second embodiment of the present invention optimizes the initial light field distribution
  • 6A is a schematic diagram of a group of measurement points used in OPC model fitting provided by the third embodiment of the present invention.
  • 6B is a schematic diagram of group B measurement points used for OPC model fitting provided by the third embodiment of the present invention.
  • 6C is a schematic diagram of a group C of measurement points used for OPC model fitting provided by the third embodiment of the present invention.
  • 6D is a schematic diagram of the D group of measurement points used for OPC model fitting provided by the third embodiment of the present invention.
  • 6E is a schematic diagram of the E group of measurement points used for OPC model fitting provided by the third embodiment of the present invention.
  • Fig. 7 is the columnar comparison chart of the root mean square obtained by group A-group E used for OPC model fitting provided by the third embodiment of the present invention.
  • FIG. 8 is a schematic diagram of a module of an electronic device provided in a fourth embodiment of the present invention.
  • FIG. 9 is a schematic structural diagram of a computer system suitable for implementing the server of the embodiment of the present invention.
  • a first embodiment of the present invention provides a full-chip fast simulation method for a negative development lithography process, including the following steps:
  • the negative development technology is an image inversion development technology, which is opposite to the traditional development technology.
  • a negative image can be obtained by using a traditional positive photoresist.
  • the photoresist composition used in this technique contains a resin and a photoacid generator, wherein the resin structure has acid-labile or acid-cleavable organic groups, and in the post-exposure baking, the exposed areas are exposed to the photoacid generator. Under the action of the acid generated by the light, the unstable groups or acid cleavable groups in the resin are cleaved, changing from hydrophobicity to hydrophilicity, so that its solubility in organic solvents is reduced, while the unexposed part remains organic.
  • the image distribution and shape after exposure are directly related to the distribution of acid, and the distribution of acid is directly related to the distribution of the light field. Therefore, the distribution of acid concentration in the photoresist is set as a function of the light field distribution.
  • the quality of the corresponding exposure image can be adjusted by correspondingly adjusting the parameters of the light field distribution.
  • the full-chip rapid simulation method of the negative development lithography process further includes the following steps:
  • the photoresist is usually a resin material including macromolecules, which has a certain elasticity. Therefore, the photoresist can be set to be an elastomer material with a certain elasticity, so that the photoresist can be set in the post-baking process.
  • the thermal shrinkage effect in is elastic deformation. Based on elastic mechanics, the elastic deformation of the photoresist is analyzed, and the light field distribution is adjusted feedback according to the analysis result, so as to obtain the appropriate acid concentration distribution and obtain the exposure image required by the composite.
  • one of stress and strain can be set as the equivalent of the photoresist deformation variable to obtain an equivalent equation.
  • each differential unit has three normal stresses ⁇ x , ⁇ y , ⁇ z , six shear Stress ⁇ xy , ⁇ xz , ⁇ yx , ⁇ yz , ⁇ zx , ⁇ zy , where the direction of the normal stress is determined by the normal direction, the first subscript of the shear stress represents the action surface, and the second subscript represents the action direction .
  • the symbols for normal stress and shear stress are the same as those in the textbooks of elastic mechanics. The following indicators and symbols about elasticity are also consistent with the definitions in the elasticity textbooks, so no further explanations will be given.
  • the change of side and included angle is shear strain, so three normal strain components are obtained, ⁇ x ,
  • a differential unit body that is, an elastic body, remains a continuum before and after deformation.
  • u, v, and w correspond to the displacements in the x-direction, y-direction, and z-direction, respectively, and the photoresist can be called an elastomer.
  • the obtaining of the equivalent equation includes the following steps:
  • the photoresist is set as a plane, so as to simplify the balance equation, the physical equation and the geometric equation.
  • the external force in elastic mechanics, can be correlated with the stress through the equilibrium equation, the stress can be correlated with the strain through the physical equation, and the strain can be correlated with the displacement through the geometric equation.
  • step S22 since the thickness of the photoresist is relatively thin, generally only about 100 nm, it can be assumed that the photoresist is a plane, which can simplify the solution process and improve the operation speed.
  • the following first provides an analysis procedure for analyzing strain.
  • the strain components of a differential unit cell at a certain point are: ⁇ x and ⁇ y
  • the total strain ⁇ is the difference between the strains ⁇ x and ⁇ y in the x and y directions
  • Overlay specifically:
  • the displacement variable can be obtained by calculating the exposed image data combined with the parameters of the lithography machine.
  • an equivalent equation can also be obtained by forming a correlation between stress and strain or other indicators, which will not be described here.
  • the full-chip rapid simulation method of the negative development lithography process further includes the following steps:
  • Taylor expansion formula provided in this embodiment is only an example and is not intended to be limiting. In other embodiments, other Taylor expansions are also possible.
  • each order sub-item of Taylor expansion is selected to fit and calculate the shrinkage effect. Since each order sub-term of Taylor expansion is relatively simple expression, fast calculation can be achieved. For the modeling of the whole chip, it has A relatively concise backpropagation expression that can be represented can meet our requirements for speed while maintaining accuracy.
  • the second embodiment of the present invention provides a negative development photoresist model, which is obtained based on the full-chip rapid simulation method of the negative development photolithography process as provided in the first embodiment.
  • FIG. 5 corresponds to an image of the light field distribution when the light field distribution is adjusted to be optimal, wherein the light brightness corresponds to T11 and T21. From the comparison between Figure 5 and Figure 4, it can be clearly seen that there is a very obvious effect of squeezing the line segment at the end point, and the place corresponding to the long line segment and the end point has a very obvious inward shrinkage.
  • the third embodiment of the present invention provides an OPC model, which includes an initial OPC model and a negatively developed photoresist model as provided in the second embodiment.
  • the general initial OPC model includes a background light intensity distribution function, a light intensity gradient function, a light intensity curve function, a photobase distribution function, and a photoacid distribution function.
  • a total of 818 gauges are provided to fit the obtained OPC model.
  • 608 monitoring points under the one-dimensional mask as described in Figures 6A-6C named as group A (group A), group B (group B) and group C (group C), among which group A
  • group A There were a total of 428 monitoring points, a total of 94 monitoring points in group B, and a total of 86 monitoring points in group C.
  • group D and group E There were a total of 428 monitoring points, a total of 94 monitoring points in group B, and a total of 86 monitoring points in group C.
  • group D and group E monitoring points under the two-dimensional mask as shown in Figures 6D and 6E, among which group D has a total of 17 monitoring points, and group E has a total of 17 monitoring points.
  • the root mean square of all monitoring points without model processing is (AI): 4.319 (RMS), after negative development model processing is (NTD): 1.289 (RMS), after positive development model processing is (PTD) ): 2.025 (RMS).
  • the corresponding root mean square (RMS) of each group is (the following table):
  • FIG. 7 corresponds to the bar graph in the above table, and the obvious difference between the three can be seen more intuitively from the bar graph.
  • a fourth embodiment of the present invention provides an electronic device 300 including one or more processors 302;
  • storage device 301 for storing one or more programs
  • the one or more processors 302 When the one or more programs are executed by the one or more processors 302 , the one or more processors 302 implement a method for fast full-chip simulation of a negative development lithography process as provided in the first implementation any step.
  • FIG. 9 shows a schematic structural diagram of a computer system 800 suitable for implementing a terminal device/server of an embodiment of the present invention.
  • the terminal device/server shown in FIG. 5 is only an example, and should not impose any limitations on the functions and scope of use of the embodiments of the present application.
  • a computer system 800 includes a central processing unit (CPU) 801, which can be loaded into a random access memory (RAM) 803 according to a program stored in a read only memory (ROM) 802 or a program from a storage section 808 Instead, various appropriate actions and processes are performed.
  • RAM random access memory
  • ROM read only memory
  • various programs and data required for the operation of the system 800 are also stored.
  • the CPU 801, the ROM 802, and the RAM 803 are connected to each other through a bus 804.
  • An input/output (I/O) interface 805 is also connected to bus 804 .
  • the following components are connected to the I/O interface 805: an input section 806 including a keyboard, a mouse, etc.; an output section 807 including a cathode ray tube (CRT), a liquid crystal display (LCD), etc., and a speaker, etc.; a storage section 808 including a hard disk, etc. ; and a communication section 809 including a network interface card such as a LAN card, a modem, and the like. The communication section 809 performs communication processing via a network such as the Internet.
  • a drive 810 is also connected to the I/O interface 805 as needed.
  • a removable medium 811 such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, etc., is mounted on the drive 810 as needed so that a computer program read therefrom is installed into the storage section 808 as needed.
  • embodiments of the present disclosure include a computer program product comprising a computer program carried on a computer-readable medium, the computer program containing program code for performing the method illustrated in the flowchart.
  • the computer program may be downloaded and installed from the network via the communication portion 809, and/or installed from the removable medium 811.
  • CPU central processing unit
  • the above-described functions defined in the method of the present invention are performed.
  • the computer-readable medium described in the present invention may be a computer-readable signal medium or a computer-readable storage medium, or any combination of the above two.
  • the computer readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus or device, or a combination of any of the above. More specific examples of computer readable storage media may include, but are not limited to, electrical connections with one or more wires, portable computer disks, hard disks, random access memory (RAM), read only memory (ROM), erasable Programmable read only memory (EPROM or flash memory), fiber optics, portable compact disk read only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.
  • RAM random access memory
  • ROM read only memory
  • EPROM or flash memory erasable Programmable read only memory
  • CD-ROM compact disk read only memory
  • optical storage devices magnetic storage devices, or any suitable combination of the foregoing.
  • Computer program code for performing the operations of the present application may be written in one or more programming languages, including object-oriented programming languages—such as Java, Smalltalk, C++, but also conventional procedural programming language - such as "C" language or similar programming language.
  • the program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer, or entirely on the remote computer or server.
  • the remote computer may be connected to the user's computer through any kind of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (eg, using an Internet service provider through Internet connection).
  • LAN local area network
  • WAN wide area network
  • Internet service provider e.g., using an Internet service provider through Internet connection.
  • each block in the flowchart or block diagrams may represent a module, segment, or portion of code that contains one or more logical functions for implementing the specified functions executable instructions.
  • the functions noted in the blocks may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved.
  • each block of the block diagrams and/or flowchart illustrations, and combinations of blocks in the block diagrams and/or flowchart illustrations can be implemented in dedicated hardware-based systems that perform the specified functions or operations , or can be implemented in a combination of dedicated hardware and computer instructions.
  • the thermal shrinkage effect in is elastic deformation, the elastic deformation of the photoresist is analyzed based on elastic mechanics, and one of stress and strain is set as the equivalent of the photoresist deformation variable to obtain an equivalent equation, the equivalent equation is a differential equation; and selects Taylor expansion to perform approximate calculation on the equivalent equation to obtain an approximate value of stress or strain, and adjusts the light field distribution according to the approximate value to obtain a suitable acid concentration distribution.

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Mathematical Optimization (AREA)
  • Computational Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Data Mining & Analysis (AREA)
  • Geometry (AREA)
  • Evolutionary Computation (AREA)
  • Computer Hardware Design (AREA)
  • Operations Research (AREA)
  • Algebra (AREA)
  • Databases & Information Systems (AREA)
  • Software Systems (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Management, Administration, Business Operations System, And Electronic Commerce (AREA)

Abstract

一种负显影光刻工艺的全芯片快速仿真方法、负显影光刻胶模型、OPC模型及电子设备，涉及集成电路光刻技术领域。该方法，基于弹性力学对光刻胶的形变进行分析，设定应力、应变之一者作为光刻胶形变量的等效以获得等效方程，选用泰勒展开式对所述等效方程进行近似计算以获得应力或者应变的近似值，根据所述近似值对光场分布进行调整以获得合适的酸浓度分布，使得曝光图形和目标图形最接近，能很好的对热收缩效应过程中光刻胶的形变进行分析，提高光刻计算过程中的准确性，同时，采用泰勒展开式对热收缩效应进行拟合，提高计算速度，因此，解决了全芯片负向显影光刻工艺计算复杂的问题。

Description

一种负显影光刻工艺的全芯片快速仿真方法、负显影光刻胶模型、OPC模型及电子设备 【技术领域】
发明涉及集成电路光刻技术领域，尤其涉及一种负显影光刻工艺的全芯片快速仿真方法、负显影光刻胶模型、OPC模型及电子设备。
【背景技术】
光刻工艺是现代超大规模集成电路制造过程中最重要的制造工艺，即通过光刻机将掩模上集成电路的设计图形转移到硅片上的重要手段。随着特征尺寸逐渐缩小，可用于制造的工艺窗口越来越小，整个光刻工艺过程都需要做到精准控制，对计算光刻精确程度的要求也越来越高。准确的计算光刻模型可以从理论上探索增大光刻分辨率和工艺窗口的途径，指导工艺参数的优化。
而目前比较先进的光刻胶技术均为负向显影。负向显影技术在建模的过程中有别于正向显影技术。在正向显影技术中，光刻胶的形变主要取决于光刻胶经过光照反应后的酸的分布，也就是光场的分布。由于计算光刻的成像光学仿真过程可以较为准确的基于物理成像模型计算出，所以，对于正向显影的光刻胶建模容易得到较为准确的结果。而在负向显影的光刻胶中，由于后烘过程光刻胶的热收缩效应，光刻胶会产生超出光场分布的额外形变，而这部分形变是十分难以捕捉的，同时这种效应对于负向显影光刻胶的建模又是十分重要的。而对于全芯片来说，一个芯片的尺寸最大可达32mm*26mm，其中最小图形的线宽可能只有10nm，一个光刻层的版图文件可达几百个GB，所以模型速度又是非常关键的技术指标。所以需要一种兼顾准确程度和速度的模型对负向显影光刻胶进行模拟仿真。
【发明内容】
为克服现有光刻技术中对负向显影光刻胶进行模拟仿真的准确性差以及优化速度低的缺陷，本发明提供一种负显影光刻工艺的全芯片快速仿真方法、负显影光刻胶模型、OPC模型及电子设备。
为了解决上述技术问题，本发明提供一种负显影光刻工艺的全芯片快速仿真方法，包括如下步骤：S1、通过光学模型得到光刻胶的光场分布，设定光场分布为E(x,y)，且设定光刻胶中酸浓度的分布为光场分布的函数，即S(x,y)＝F(E(x,y))；S2、设定光刻胶在后烘过程中的热收缩效应为弹性形变，基于弹性力学对光刻胶的弹性形变进行分析，设定应力、应变之一者作为光刻胶形变量的等效以获得等效方程，所述等效方程为微分方程；及S3、选用泰勒展开式对所述等效方程进行近似计算以获得应力或者应变的近似值，根据所述近似值对光场分布进行调整以获得合适的酸浓度分布。
优选地，根据连续性假设，弹性体在变形前和变形后仍保持为连续体，假设弹性体中某点在变形过程中由位置M(x,y,z)移动至M′(x′,y′,z′)，这一过程为连续过程，所有
Figure PCTCN2020133696-appb-000001
w(x,y,z)＝w′(x,y,z)-w，其中u、v、w分别对应为x方向、y方向和z方向上的位移，光刻胶可以称为弹性体；
在上述步骤S2中，所述等效方程的获得包括如下步骤：S21、外力通过平衡方程与应力形成相互关联，应力通过物理方程与应变形成相互关联，应变通过几何方程与位移形成相互关联；及S22、基于光刻胶的厚度尺寸较薄，将所述光刻胶设定为一个平面，从而对所述平衡方程、所述物理方程以及所述几何方程简化。
优选地，基于简化后的几何方程获得关于应变与位移之间形成关联的等效方程。
优选地，以下公式中涉及到的符号定义均与弹性力学 中的定义一致，因此不再一一定义；在上述步骤S22中，将所述光刻胶设定为一个平面时对应设定σ z＝0，τ zx＝0，
Figure PCTCN2020133696-appb-000002
简化后的几何方程为：
Figure PCTCN2020133696-appb-000003
优选地，所述等效方程如下：
Figure PCTCN2020133696-appb-000004
优选地，与所述等效方程相似的泰勒展开式如下，
Figure PCTCN2020133696-appb-000005
其中：0＜θ＜1、h和k为一个常数。
本发明为了解决上述技术问题还提供一种电子设备，其包括一个或多个处理器；存储装置，用于存储一个或多个程序，当所述一个或多个程序被所述一个或多个处理器执行，使得所述一个或多个处理器实现如上所述的任一项方法。
与现有技术相比，基于弹性力学对光刻胶的形变进行分析，设定应力、应变之一者作为光刻胶形变量的等效以获得等效方程，选用泰勒展开式对所述等效方程进行近似计算以获得应力或者应变的近似值，根据所述近似值对光场分布进行调整以获得合适的酸浓度分布，使得曝光图形和目标图形最接近，能很好的对热收缩效应过程中光刻胶的形变进行分析，提高光刻计算过程中的准确性，同时， 采用泰勒展开式对热收缩效应进行拟合，提高计算速度，因此，解决了全芯片负向显影光刻工艺计算复杂的问题。
基于光刻胶的厚度尺寸较薄，将所述光刻胶设定为一个平面，从而对所述平衡方程、所述物理方程以及所述几何方程简化，使得简化后的等效方程和泰勒展开式具有较大的相似性，因此，不需要对等效方程进行微分求解，能很好的提高计算速度，同时很好的保证准确性。
本发明提供的负显影光刻胶模型、OPC模型以及电子设备同样具有如上所述的有益效果。
【附图说明】
图1是本发明第一实施例中提供的负显影光刻工艺的全芯片快速仿真方法的流程图；
图2是本发明中光刻胶对应的微分单元体的示意图；
图3是本发明第一实施例中提供的负显影光刻工艺的全芯片快速仿真方法中步骤S2的细节流程图；
图4是本发明第二实施例提供的负显影光刻胶模型中初始光场分布示意图；
图5是本发明第二实施例提供的负显影光刻胶模型对初始光场分布优化之后的光场分布的示意图；
图6A是本发明第三实施例提供的OPC模型拟合所使用的A组测量点的示意；
图6B是本发明第三实施例提供的OPC模型拟合所使用的B组测量点的示意图；
图6C是本发明第三实施例提供的OPC模型拟合所使用的C组测量点的示意图；
图6D是本发明第三实施例提供的OPC模型拟合所使用的D组测量点的示意图；
图6E是本发明第三实施例提供的OPC模型拟合所使用的E组测量点的示意图；
图7是本发明第三实施例提供的OPC模型拟合所使用的A组-E组获得的均方根的柱状对比图；
图8是本发明第四实施例中提供的电子设备的模块示意图；
图9是适于用来实现本发明实施例的服务器的计算机系统的结构示意图。
【具体实施方式】
为了使本发明的目的，技术方案及优点更加清楚明白，以下结合附图及实施实例，对本发明进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本发明，并不用于限定本发明。
请参阅图1，本发明第一实施例提供负显影光刻工艺的全芯片快速仿真方法，包括如下步骤：
S1、通过光学模型得到光刻胶的光场分布，设定光场分布为E(x,y)，且设定光刻胶中酸浓度的分布为光场分布的函数，即S(x,y)＝F(E(x,y))。
在本步骤中，负向显影技术是一种图像反转的显影技术，它与传统的显影技术相反，通过使用特殊的有机溶剂显影可以借助由传统的正型光刻胶来得到负向的图像。该技术中所使用的光刻胶组合物含有树脂和光产酸剂，其中，树脂结构具有酸不稳定或者酸可裂解的有机基团，在曝光后的烘焙中，曝光区域在光产酸剂受到光照所产生的酸的作用下，树脂中不稳定基团或酸可裂解基团断裂，由疏水性转变为亲水性，从而使得其在有机溶剂中溶解度降低，而未曝光部分仍保持在有机溶剂中溶解度高的性质，因而在显影过程中能够被有机溶剂制成的显影液除去。因此，与传统的正型光刻胶显影过程中曝光部分被溶解相反，该技术使得正型光刻胶在显影时非曝光部分被溶解，曝光部分被保留。
因此，可以获知曝光之后的图像分布和形状与酸的分布直接关联，而酸的分布直接关联于光场的分布情况。因此，设定光刻胶中酸浓度的分布为光场分布的函数。在制备芯片的过程中，对应调节光场分布的参数即可调整对应的曝光图像的质量。
请再次参阅图1，负显影光刻工艺的全芯片快速仿真方法还包括如下步骤：
S2、设定光刻胶在后烘过程中的热收缩效应为弹性形变，基于弹性力学对光刻胶的弹性形变进行分析，设定应力、应变之一者作为光刻胶形变量的等效以获得等效方程，所述等效方程为微分方程。
在本步骤中，光刻胶通常为包括高分子的树脂材料，其具有一定的弹性，因此，可以设定光刻胶为具有一定弹性的弹性体材料，从而设定光刻胶在后烘过程中的热收缩效应为弹性形变。基于弹性力学对光刻胶的弹性形变进行分析，根据分析结果反馈调节光场分布，从而获得合适的酸浓度分布，以获得复合要求的曝光图像。
具体分析的过程中，可以设定应力、应变之一者作为光刻胶形变量的等效以获得等效方程。
请参阅图2，在具体的分析过程中，可以将光刻胶分成若干个微分单元体，根据弹性力学分析，每一个微分单元体有三个正应力σ x，σ y，σ z，六个剪应力τ xy，τ xz，τ yx，τ yz，τ zx，τ zy，其中正应力的方向由法线方向确定，剪应力的第一个下标代表作用面，第二个下标代表作用方向。关于正应力和剪应力的符号是对应弹性力学教科书上的符号定义一致。以下出现的关于弹性力学的指标符号也均与弹性力学教课书上的定义一致，因此，不再做过多的解释。
根据剪应力互等定理有τ xy＝τ yx，τ yz＝τ zy，τ xz＝τ zx。
Figure PCTCN2020133696-appb-000006
边与夹角的变化为剪应变，故得到三个正应变分量，ε x，
Figure PCTCN2020133696-appb-000007
微分单元体，也即弹性体在变形前和变形后仍保持为连续体。假设弹性体中某点在变形过程中由M(x,y,z)移动至
Figure PCTCN2020133696-appb-000008
w(x,y,z)＝w′(x,y,z)-w。其中，其中u、v、w分别对应为x方向、y方向和z方向上的位移，光刻胶可以称为弹性体。
请参阅图3，在上述步骤S2中，所述等效方程的获得包括如下步骤：
S21、外力通过平衡方程与应力形成相互关联，应力通过物理方程与应变形成相互关联，应变通过几何方程与位移形成相互关联；及
S22、基于光刻胶的厚度尺寸较薄，将所述光刻胶设定为一个平面，从而对所述平衡方程、所述物理方程以及所述几何方程简化。
在上述步骤S21中，在弹性力学中，外力通过平衡方程可以与应力形成相互关联，应力通过物理方程可以与应变形成相互关联，应变通过几何方程可以与位移形成相互关联。
其中平衡方程为：
Figure PCTCN2020133696-appb-000009
物理方程为：
Figure PCTCN2020133696-appb-000010
几何方程为：
Figure PCTCN2020133696-appb-000011
Figure PCTCN2020133696-appb-000012
在上述步骤S22中，由于光刻胶厚度较薄，一般厚度只有100nm左右，所以可以假设光刻胶为一个平面，这样可以简化求解过程，提高运算速度。
当将光刻胶设定为一个平面时，有σ z＝0，τ zx＝0，τ zy＝0，w＝0，所以上面的方程会被简化，而且u，v仅为x,y的
Figure PCTCN2020133696-appb-000013
其中平衡方程为：
Figure PCTCN2020133696-appb-000014
几何方程为：
Figure PCTCN2020133696-appb-000015
由于我们关注的是光刻胶的弹性形变，通过对弹性形变量的分析以调整关于广场的分布，从而调节酸浓度的分布，为了分析弹性形变量，所以我们选择应力或者应变之一者进行分析。
以下首先提供对应变进行分析的分析过程。当将光刻胶平面化之后，某个微分单元体在某点受到的应变分量为：ε x和ε y，而应变总量ε为关于x方向和y方向上的应变ε x和ε y的叠加，具体为：
Figure PCTCN2020133696-appb-000016
根据简化公式可以得出微分单元体的应变与位移之间的关联公式，也即对应的等效方程如下：
Figure PCTCN2020133696-appb-000017
在实际的应用过程中，可以通过曝光后的图像数据结 合光刻机的参数计算获得位移变量。
在一些其他实施方式中，也可以形成关于应力与应变或者其他指标的关联方式获得等效方程，在此不做过多的介绍。
请再次参阅图1，负显影光刻工艺的全芯片快速仿真方法还包括如下步骤：
S3、选用泰勒展开式对所述等效方程进行近似计算以获得应力或者应变的近似值，根据所述近似值对光场分布进行调整以获得合适的酸浓度分布。
在本步骤中，由于是将方程进行简化之后获得的简化模型，也即等效方程，需要考虑速度，所以我们不考虑微分方程求解的过程，也即避免直接求解等效方程。通过观察，不难发现等效方程与泰勒展开式有很大的相似之处，所以，选用泰勒展开式对所述等效方程进行近似计算以获得应力或者应变的近似值，根据所述近似值对光场分布进行调整以获得合适的酸浓度分布。
在本实施例中，提供的泰勒展开公式如下：
Figure PCTCN2020133696-appb-000018
其中，(0＜θ＜1)，其中h和k为常数。
在本实施例中提供的泰勒展开公式仅仅是一个示例，不做为限定。在其他实施例中，还可以是其他的泰勒展开式。
需要说明的是：选取泰勒展开各阶子项对收缩效应进行拟合计算，由于泰勒展开各阶子项均为相对简单表达式，从而可以实现快速计算，对于全芯片的建模来说，拥有可表示的相对简洁的后向传播表达式，可以满足我们对速度的要求，同时也能保证准确性。
本发明第二实施例提供一种负显影光刻胶模型，其基于如第一实施例提供的负显影光刻工艺的全芯片快速仿真方法获得。
请参阅4和图5，在图4中为初始时选定一块掩模版图区域，生成一个512*512的掩模版图像，对应为图中的每个方格的M区域，然后通过步骤S1中所述的光学模型，得到它的光场分布图像，对应图4中的发亮区域，分别对应为T1和T2。进一步，基于步骤S2和步骤S3中操作对光场分布进行处理，得到模拟的经过热收缩效应之后的图像，在调整的过程中，往往需要多次的反复调整方能得到合适的广场分布，以获得合格的曝光图形。图5对应为调整至光场分布达到最优时的光场分布图像，其中光亮度对应变为T11和T21。通过图5和图4的对比可以很清晰的看出，端点处有很明显的向线段挤压的效应，长线段和端点相对应的地方有很明显的向内收缩。
本发明第三实施例提供一种OPC模型，其包括初始OPC模型和如第二实施例所提供的负显影光刻胶模型。一般初始OPC模型包括背景光强度分布函数、光强梯度函数、光强曲线函数、光碱分布函数、以及光酸分布函数等。加入如上所述的负显影光刻胶模型之后，其能很好的适应于负性光刻胶工艺，能很好的模拟和计算负型光刻胶的热收缩效应，提高光刻工艺的准确性。
请参阅图6A至6E，共提供818个监测点(gauges)对获得的OPC模型进行拟合。其中，包括如图6A-6C所述的在一维掩模下的608个监测点，分别命名为A组(group A)、B组(group B)和C组(group C)，其中A组总共428个监测点，B组总共94个监测点，C组总共86个监测点。还包括如图6D和6E所示的二维掩模下的210个监测点，分别命名为D组(group D)、E组(group E)，其中D组总共17个监测点，E组总共94个监测点，C组总共193个监测点。所有监测点在没有经过模型处理时的均方根为(AI)：4.319(RMS)，经过负向显影模型处理之后为(NTD)：1.289(RMS)，经过正向显影模型处理之后为(PTD)：2.025(RMS)。
每一组对应的均方根(RMS)为(如下表格)：
Figure PCTCN2020133696-appb-000019
综合以上数据可以看出，在通过基于负向光刻胶模型建立的OPC模型模拟之后获得的均方根数值较小，所述的OPC模型具有较优的性能。
请参阅图7，其对应为上述表格中的柱状图，从柱状图可以更加直观的看出三者之间的明显差异。
请参阅图8，本发明的第四实施提供一种电子装置300，其包括一个或多个处理器302；
存储装置301，用于存储一个或多个程序，
当所述一个或多个程序被所述一个或多个处理器302执行，使得所述一个或多个处理器302实现如第一实施提供的一种负显影光刻工艺的全芯片快速仿真方法的任一步骤。
下面参考图9，其示出了适于用来实现本发明实施例的终端设备/服务器的计算机系统800的结构示意图。图5示出的终端设备/服务器仅仅是一个示例，不应对本申请实施例的功能和使用范围带来任何限制。
如图9所示，计算机系统800包括中央处理单元(CPU)801，其可以根据存储在只读存储器(ROM)802中的程序或者从存储部分808加载到随机访问存储器(RAM)803中的程序而执行各种适当的动作和处理。在RAM 803中，还存储有系统800操作所需的各种程序和数据。CPU 801、ROM 802以及RAM 803通过总线804彼此相连。输入/输出(I/O)接口805也连接至总线804。
以下部件连接至I/O接口805：包括键盘、鼠标等的输入部分806；包括诸如阴极射线管(CRT)、液晶显示器(LCD)等以及扬声器等的输出部分807；包括硬盘等的存储部分808；以及包括诸如LAN卡、调制解调器等的网络接口卡的通信部分809。通信部分809经由诸如因特网的网络执行通信处理。驱动器810也根据需要连接至I/O接口805。可拆卸介质811，诸如磁盘、光盘、磁光盘、半导体存储器等等，根据需要安装在驱动器810上，以便于从其上读出的计算机程序根据需要被安装入存储部分808。
根据本公开的实施例，上文参考流程图描述的过程可以被实现为计算机软件程序。例如，本公开的实施例包括一种计算机程序产品，其包括承载在计算机可读介质上的计算机程序，该计算机程序包含用于执行流程图所示的方法的程序代码。在这样的实施例中，该计算机程序可以通过通信部分809从网络上被下载和安装，和/或从可拆卸介质811被安装。在该计算机程序被中央处理单元(CPU)801执行时，执行本发明的方法中限定的上述功能。需要说明的是，本发明所述的计算机可读介质可以是计算机可读信号介质或者计算机可读存储介质或者是上述两者的任意组合。计算机可读存储介质例如可以是—但不限于—电、磁、光、电磁、红外线、或半导体的系统、装置或器件，或者任意以上的组合。计算机可读存储介质的更具体的例子可以包括但不限于：具有一个或多个导线的电连接、便携式计算机磁盘、硬盘、随机访问存储器(RAM)、只读存储器(ROM)、可擦式可编程只读存储器(EPROM或闪存)、光纤、便携式紧凑磁盘只读存储器(CD-ROM)、光存储器件、磁存储器件、或者上述的任意合适的组合。
可以以一种或多种程序设计语言或其组合来编写用于执行本申请的操作的计算机程序代码，所述程序设计语言包括面向对象的程序设计语言—诸如Java、Smalltalk、C++，还包括常规的过程式程序设计语言—诸如“C”语言或类似的程序设计语言。程序代码可以完全地在用户计算机上执行、部分地在用户计算机上执行、作为一个独立的 软件包执行、部分在用户计算机上部分在远程计算机上执行、或者完全在远程计算机或服务器上执行。在涉及远程计算机的情形中，远程计算机可以通过任意种类的网络——包括局域网(LAN)或广域网(WAN)—连接到用户计算机，或者，可以连接到外部计算机(例如利用因特网服务提供商来通过因特网连接)。
附图中的流程图和框图，图示了按照本发明各种实施例的系统、方法和计算机程序产品的可能实现的体系架构、功能和操作。在这点上，流程图或框图中的每个方框可以代表一个模块、程序段、或代码的一部分，该模块、程序段、或代码的一部分包含一个或多个用于实现规定的逻辑功能的可执行指令。也应当注意，在有些作为替换的实现中，方框中所标注的功能也可以以不同于附图中所标注的顺序发生。例如，两个接连地表示的方框实际上可以基本并行地执行，它们有时也可以按相反的顺序执行，这依所涉及的功能而定。也要注意的是，框图和/或流程图中的每个方框、以及框图和/或流程图中的方框的组合，可以用执行规定的功能或操作的专用的基于硬件的系统来实现，或者可以用专用硬件与计算机指令的组合来实现。
上述计算机可读介质承载有一个或者多个程序，当上述一个或者多个程序被该装置执行时，使得该装置：通过光学模型得到光刻胶的光场分布，设定光场分布为E(x,y)，且设定光刻胶中酸浓度的分布为光场分布的函数，即S(x,y)＝F(E(x,y))；设定光刻胶在后烘过程中的热收缩效应为弹性形变，基于弹性力学对光刻胶的弹性形变进行分析，设定应力、应变之一者作为光刻胶形变量的等效以获得等效方程，所述等效方程为微分方程；及选用泰勒展开式对所述等效方程进行近似计算以获得应力或者应变的近似值，根据所述近似值对光场分布进行调整以获得合适的酸浓度分布。
以上所述仅为本发明较佳实施例而已，并不用以限制本发明，凡在本发明原则之内所作的任何修改，等同替换和改进等均应包含本发明的保护范围之内。

Claims (9)

  1. 一种负显影光刻工艺的全芯片快速仿真方法，其特征在于：包括如下步骤：
    S1、通过光学模型得到光刻胶的光场分布，设定光场分布为E(x,y)，且设定光刻胶中酸浓度的分布为光场分布的函数，即S(x,y)＝F(E(x,y))；
    S2、设定光刻胶在后烘过程中的热收缩效应为弹性形变，基于弹性力学对光刻胶的弹性形变进行分析，设定应力、应变之一者作为光刻胶形变量的等效以获得等效方程，所述等效方程为微分方程；及
    S3、选用泰勒展开式对所述等效方程进行近似计算以获得应力或者应变的近似值，根据所述近似值对光场分布进行调整以获得合适的酸浓度分布。
  2. 如权利要求1所述的负显影光刻工艺的全芯片快速仿真方法，其特征在于：
    根据连续性假设，弹性体在变形前和变形后仍保持为连续体，假设弹性体中某点在变形过程中由位置M(x,y,z)移动至M′(x′,y′,z′)，这一过程为连续
    Figure PCTCN2020133696-appb-100001
    w(x,y,z)＝w′(x,y,z)-w，其中u、v、w分别对应为x方向、y方向和z方向上的位移，光刻胶对应称为弹性体；
    在上述步骤S2中，所述等效方程的获得包括如下步骤：
    S21、外力通过平衡方程与应力形成相互关联，应力通过物理方程与应变形成相互关联，应变通过几何方程与位移形成相互关联；及
    S22、基于光刻胶的厚度尺寸较薄，将所述光刻胶设定为一个平面，从而对所述平衡方程、所述物理方程以及所述几何方程简化。
  3. 如权利要求2所述的负显影光刻工艺的全芯片快速仿真方法，其特征在于：
    基于简化后的几何方程获得关于应变与位移之间形成关联的等效方程。
  4. 如权利要求3所述的负显影光刻工艺的全芯片快速仿真方法，其特征在于：以下公式中涉及到的符号定义均与弹性力学中的定义一致；
    在上述步骤S22中，将所述光刻胶设定为一个平面时对应设定σ z＝0，τ zx＝0，τ zy＝0，w＝0；
    Figure PCTCN2020133696-appb-100002
  5. 如权利要求4所述的负显影光刻工艺的全芯片快速仿真方法，其特征在于：所述等效方程如下：
    Figure PCTCN2020133696-appb-100003
  6. 如权利要求5所述的负显影光刻工艺的全芯片快速仿真方法，其特征在于：与所述等效方程相似的泰勒展开式如下，
    Figure PCTCN2020133696-appb-100004
    Figure PCTCN2020133696-appb-100005
  7. 一种负显影光刻胶模型，其特征在于：基于如权利要求1所述的一种负显影光刻工艺的全芯片快速仿真方法获得。
  8. 一种OPC模型，其特征在于：提供初始OPC模型并加入如权利要求7所述的负显影光刻胶模型。
  9. 一种电子设备，其特征在于：其包括一个或多个处理器；
    存储装置，用于存储一个或多个程序，
    当所述一个或多个程序被所述一个或多个处理器执行，使得所述一个或多个处理器实现如权利要求1所述的负显影光刻工艺的全芯片快速仿真方法。
PCT/CN2020/133696 2020-10-23 2020-12-03 一种负显影光刻工艺的全芯片快速仿真方法、负显影光刻胶模型、opc模型及电子设备 WO2022082936A1 (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
KR1020237017402A KR20230087605A (ko) 2020-10-23 2020-12-03 Ntd 광식각 공정에 의한 풀칩 패스트 시뮬레이션 방법, ntd 포토레지스트 모델, opc 모델 및 전자 장치
US18/305,350 US20230384692A1 (en) 2020-10-23 2023-04-23 Method for full-chip quick simulation of negative tone development photolithography process, negative tone development photoresist model, opc model, and electronic device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202011153654.X 2020-10-23
CN202011153654.XA CN112257270A (zh) 2020-10-23 2020-10-23 一种负显影光刻工艺的全芯片快速仿真方法、负显影光刻胶模型、opc模型及电子设备

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US18/305,350 Continuation US20230384692A1 (en) 2020-10-23 2023-04-23 Method for full-chip quick simulation of negative tone development photolithography process, negative tone development photoresist model, opc model, and electronic device

Publications (1)

Publication Number Publication Date
WO2022082936A1 true WO2022082936A1 (zh) 2022-04-28

Family

ID=74261887

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2020/133696 WO2022082936A1 (zh) 2020-10-23 2020-12-03 一种负显影光刻工艺的全芯片快速仿真方法、负显影光刻胶模型、opc模型及电子设备

Country Status (4)

Country Link
US (1) US20230384692A1 (zh)
KR (1) KR20230087605A (zh)
CN (1) CN112257270A (zh)
WO (1) WO2022082936A1 (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114488705A (zh) * 2022-01-13 2022-05-13 东方晶源微电子科技（北京）有限公司 一种负向显影光刻胶模型优化方法
CN117008428B (zh) * 2023-09-26 2024-01-26 全芯智造技术有限公司 光刻仿真方法、设备和介质

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101738848A (zh) * 2008-11-24 2010-06-16 上海华虹Nec电子有限公司 基于可变光酸扩散长度建立opc模型的方法
US20170192357A1 (en) * 2014-02-24 2017-07-06 Tokyo Electron Limited Methods and techniques to use with photosensitized chemically amplified resist chemicals and processes
CN107844644A (zh) * 2017-10-26 2018-03-27 上海集成电路研发中心有限公司 一种建立晶圆形貌opc模型的方法
CN109558610A (zh) * 2017-09-26 2019-04-02 京东方科技集团股份有限公司 膜层刻蚀区域等效力学参数的计算方法和设备
CN111433680A (zh) * 2017-12-04 2020-07-17 Asml荷兰有限公司 用于预测层变形的系统和方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101738848A (zh) * 2008-11-24 2010-06-16 上海华虹Nec电子有限公司 基于可变光酸扩散长度建立opc模型的方法
US20170192357A1 (en) * 2014-02-24 2017-07-06 Tokyo Electron Limited Methods and techniques to use with photosensitized chemically amplified resist chemicals and processes
CN109558610A (zh) * 2017-09-26 2019-04-02 京东方科技集团股份有限公司 膜层刻蚀区域等效力学参数的计算方法和设备
CN107844644A (zh) * 2017-10-26 2018-03-27 上海集成电路研发中心有限公司 一种建立晶圆形貌opc模型的方法
CN111433680A (zh) * 2017-12-04 2020-07-17 Asml荷兰有限公司 用于预测层变形的系统和方法

Also Published As

Publication number Publication date
CN112257270A (zh) 2021-01-22
US20230384692A1 (en) 2023-11-30
KR20230087605A (ko) 2023-06-16

Similar Documents

Publication Publication Date Title
US20230384692A1 (en) Method for full-chip quick simulation of negative tone development photolithography process, negative tone development photoresist model, opc model, and electronic device
EP3063785B1 (en) Process-induced distortion prediction and feedforward and feedback correction of overlay errors
CN105825036B (zh) 一种版图设计规则的优化方法及系统
US8572520B2 (en) Optical proximity correction for mask repair
US8473271B2 (en) Fast photolithography process simulation to predict remaining resist thickness
US20230288814A1 (en) Method for simulation of negative tone development photolithography process, negative tone development photoresist model, opc model, and electronic device
US20040102912A1 (en) Automatic calibration of a masking process simulator
CN111581907B (zh) 一种Hessian-Free的光刻掩模优化方法、装置及电子设备
WO2023060737A1 (zh) 量子体系下的期望值估计方法、装置、设备及系统
CN108228981B (zh) 基于神经网络的opc模型生成方法及实验图案的预测方法
JP7344203B2 (ja) マイクロリソグラフィのためのマスクの認定のための方法
US10691015B2 (en) Integrated mask-aware lithography modeling to support off-axis illumination and multi-tone masks
US20220301662A1 (en) Information processing system, information processing device, learning device, information processing method, learning method, and program
CN117669473B (zh) 用于模型校准的方法、电子设备及存储介质
Latypov et al. Gaussian random field EUV stochastic models, their generalizations and lithographically meaningful stochastic metrics
TWI422986B (zh) 用於光學近接修正的粗修影像模式化
US20240126179A1 (en) Optical imaging method, device and system for photolithography system
WO2023151581A1 (zh) 用于图像处理的方法、设备、存储介质和程序产品
WO2023134175A1 (zh) 一种负向显影光刻胶模型优化方法
US20230121176A1 (en) Expectation value estimation method and apparatus in quantum system, device, and system
Strojwas et al. Layout manufacturability analysis using rigorous 3-D topography simulation
CN111611764B (zh) 一种光瞳评价方法及其系统、电子装置
JP3181563B2 (ja) レジストパターン形状のシミュレーション方法およびシミュレーション装置
TWI284788B (en) Simulation method and device of exposure system
CN111897188A (zh) 超大数值孔径严格矢量成像系统偏振像差的检测方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 20958513

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 20237017402

Country of ref document: KR

Kind code of ref document: A

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 20958513

Country of ref document: EP

Kind code of ref document: A1