WO2022082743A1

WO2022082743A1 - ARCITECTURE, STRUCTURE, METHOD AND MEMORY ARRAY FOR 3D FeFET TO ENABLE 3D FERROELETRIC NONVOLATILE DATA STORAGE

Info

Publication number: WO2022082743A1
Application number: PCT/CN2020/123293
Authority: WO
Inventors: Jun Liu
Original assignee: Yangtze Advanced Memory Industrial Innovation Center Co., Ltd
Priority date: 2020-10-23
Filing date: 2020-10-23
Publication date: 2022-04-28
Also published as: CN112437959A; CN112437959B

Abstract

A new cell structure to implement 3D ferroelectric field effect transistor (FeFET) to enable 3D ferroelectric nonvolatile data storage is presented to increase data storage density and reduce memory bit cost. The 3D FeFET is a vertical gate all around transistor with recessed ferroelectric gate oxide to achieve nonvolatility in a 4F2 cell footprint, where F is the minimum processing size. In the new cell structure, cross point array is employed with perpendicular bit lines (BL) (101a, 101b, 101c) and perpendicular word lines (WL) (102a, 102b, 102c), and can be stacked in two or more decks (111, 112, 113) with the 3D FeFET memory cells to enable an effective cell size of 2F2 in two decks and 1F2 in four decks.

Description

AN ARCITECTURE, STRUCTURE, METHOD AND MEMORY ARRAY FOR 3D FeFET TO ENABLE 3D FERROELETRIC NONVOLATILE DATA STORAGE

TECHNICAL FIELD

The present disclosure generally relates to three-dimensional electronic memories including ferroelectric field effect transistor, and more particularly, to increasing the data storage density of memory cells and reduce memory bit cost.

BACKGROUND

Planar memory cells are scaled to smaller sizes by improving process technology, circuit design, programming algorithm, and fabrication process. However, as feature sizes of the memory cells approach a lower limit, planar process and fabrication techniques become challenging and costly. As such, memory density for planar memory cells approaches an upper limit.

A ferroelectric random-access memory (FeRAM) uses a planar transistor as a selection device for the ferroelectric memory cell to form a two dimensional memory array. FeRAM is a random-access memory similar to dynamic random-access memory (DRAM) , but FeRAM uses a memory cell with a ferroelectric capacitor instead of a dielectric capacitor to store data. There are two types of FeRAM, one using a ferroelectric capacitor to store data and the other using a ferroelectric field effect transistor (FeFET) to store data. Compared with conventional FeRAM 1T-1C memory cells, FeFET is a 1T/C memory cell without a standalone ferroelectric capacitor. FeFET incorporates a ferroelectric gate dielectric in a complementary metal oxide semiconductor (CMOS) transistor. Thus, FeFET shows nonvolatile characteristics due to the fact that the two stable, remnant polarization states of the now ferroelectric gate insulator modify the threshold voltage even when the supply voltage is removed. Accordingly, the binary states are encoded in the threshold voltage of the transistor.

Memory bit density of two-dimensional, planar FeFET is highly dependent on transistor size with a minimum memory cell size defined by capacitance requirement in order to denote the data difference. As a result, it is necessary to implement a novel three-dimensional (3D) memory cell structure to further reduce cell footprint and bit cost.

SUMMARY

The following summary is included in order to provide a basic understanding of aspects and features of the disclosure. This summary is not an extensive overview and as such it is not intended to particularly identify key or critical elements or to delineate the scope of the disclosure. Its sole purpose is to present concepts in a summarized format.

In one aspect, a new cell structure to implement 3D Ferroelectric field effect transistor (FeFET) to enable 3D ferroelectric nonvolatile data storage is presented to increase data storage density and reduce memory bit cost. The 3D FeFET is a vertical gate all around transistor with recessed ferroelectric gate oxide to achieve nonvolatility in a 4F2 cell footprint, where F is the minimum processing size. In the present new cell structure, cross point array is employed with perpendicular bit lines (BL) and perpendicular word lines (WL) , and can be stacked in two or more decks with the 3D FeFET memory cells to enable an effective cell size of 2F2 in two decks and 1F2 in four decks, where F is the minimum processing size.

Using FeFET produces the smallest 4F2 cell size due to 3D vertical FeFET memory cell. The 3D vertical FeFET memory cell also has less process cost due to 1T/C memory cell that builds memory cell into access transistor. The cross-point architecture and vertical transistor enables an effective cell size of 4F2 on each deck. The 3D FeFET architecture with shared bit lines increase memory bit density and decrease silicon cost with multiple decks. The architecture enables an effective cell size of 2F2 for two decks of FeFET cells and an effective cell size of 1F2 for four decks of FeFET cells.

A cross-point architecture to implement 3D FeFET memory array including a plurality of cell decks comprising a vertical gate all around FeFET cell, wherein the plurality of cell decks are stacked. The vertical gate all around FeFET cell enables a cross point array and provides an effective cell size being 4F2 per deck. The vertical gate all around FeFET enables a 4F2 cell area, while the plurality of cell decks share a bit line. The vertical gate all around FeFET cell is a 1T/C cell.

A three-dimensional memory array including a cross point array architecture. The cross point array architecture includes a plurality of cell decks including word lines and bit lines. The word lines of the plurality of cell decks are parallel or perpendicular and the bit lines of the plurality of cell decks are perpendicular to the word lines. The plurality of cell decks further comprise a FeFET cell. The FeFET cell includes a vertical FeFET transistor. The FeFET cell is accessed by the bit lines through the vertical FeFET transistor.

A three-dimensional FeRAM memory cell including a vertical gate all around FeFET. The vertical gate all around FeFET includes a recessed ferroelectric gate dielectric and a solid or hollow channel.

A method of fabricating a three-dimensional memory array including forming parallel polysilicon word lines for a first deck, forming an array of vertical channel holes in the parallel polysilicon word lines, recessing a portion in the array of vertical channel holes, depositing ferroelectric gate dielectric material into the recess; and inserting a vertical transistor into the vertical channel to form a three-dimensional FeFET memory cell on a vertical transistor. The vertical transistor is solid or hollow. The method may also include forming parallel bit lines and positioning the parallel bit lines perpendicularly to the parallel polysilicon word lines. The method may be repeated to form a second deck.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing aspects, features and advantages of the present disclosure will be further appreciated when considered with reference to the following description of exemplary embodiments and accompanying drawings, wherein like reference numerals represent like elements. In describing the exemplary embodiments of the present disclosure illustrated in the drawings, specific terminology may be used for the sake of clarity. However, the aspects of the present disclosure are not intended to be limited to the specific terms used.

Fig. 1 is an isometric view of a section of a prior planar memory cell.

Fig. 2 is a plan view of a section of a prior planar memory array.

Figs. 3A and 3B are plan views of a section of three-dimensional cross-point memory according to an embodiment.

Fig. 4 is a plan view of a section of memory array of three-dimensional cross-point memory in accordance with the embodiment of Figs. 3A and 3B.

Figs. 5A and 5B are plan views of a section of three-dimensional cross-point memory according to an additional embodiment.

Fig. 6 is a plan view of a section of three-dimensional cross-point memory according to an embodiment.

Fig. 7 is a plan view of a section of three-dimensional cross-point memory according to an embodiment.

Fig. 8 is a plan view of a section of three-dimensional cross-point memory according to an embodiment.

Figs. 9 is a plan view of a section of three-dimensional cross-point memory according to an embodiment.

Fig. 10 is a plan view of a section of three-dimensional cross-point memory according to an embodiment.

Fig. 11 is a plan view of a section of three-dimensional cross-point memory according to an embodiment.

Fig. 12 is a plan view of a section of three-dimensional cross-point memory according to an embodiment.

DETAILED DESCRIPTION

The present technology is applied in the field of three-dimensional memory. A generalized example of a planar memory cell is shown in Fig. 1. In particular, Fig. 1 is a plan view of a prior Ferroelectric random access memory (FeRAM) cell using a FeFET to store data. The memory cell 10 includes a FeFET 11 attached to a word line 14 extending along the X direction on one surface of the FeFET. The FeFET 11 is also attached to a plate 12 on another surface of the FeFET. The memory cell may also include word line 14 extending along the Y direction and a bit line (not pictured) , the bit line extending along the X direction. In any event, an individual memory cell may be accessed by selectively activating the word line and bit line corresponding to the cell.

FIG. 2 is a plan view of section of a planar memory circuit of a prior configuration. The figure depicts the section as viewed along the Z (depth) direction. The section includes a word line extending in the Y (vertical) direction 1, a bit line extending along the X (horizontal) direction 13 and corresponding to a memory cells (not shown) . The word lines, top cell bit lines, and bottom cell bit lines (not pictured) are typically formed according to a 20 nm /20 nm Line /Space (L/S) pattern and are formed on a silicon substrate.

The developers of the present technology have recognized the drawbacks arising from the prior configuration and provide the present technology in light of such drawbacks.

Figs. 3A and 3B are plan views of a section of three-dimensional cross-point memory according to an embodiment. Fig. 4 is a plan view of a section of memory array of three-dimensional cross-point memory in accordance with the embodiment of Figs. 3A and 3B.

Fig. 3A shows a vertical single capacitor 100 according to an embodiment of the disclosure. The vertical single capacitor 100 includes a first cell deck 111, a second cell deck 112, and a third cell deck 112. The first cell deck 111 is positioned between a common plate 106, which may be a complementary metal oxide semiconductor (CMOS) , and the second cell deck, the second cell deck 112 is positioned between the first cell deck 111 and the third cell deck 113 while the third cell deck 113 is positioned above the second cell deck 112 to enable 3D cross point architecture. The second deck 112 is positioned such that the word lines 102b and the FeFET 103b are offset from the word lines of the first cell deck and the

third cell deck

102a, 102c and the FeFET of the first cell deck and the

third cell deck

103a, 103c. The cell decks may be implemented to be parallel in all decks. Alternatively, the decks may be implemented to be perpendicular as can be seen in Figs. 5A and 5B. In Figs. 5A and 5B, the second cell deck 112 is positioned to be perpendicular to the third deck 113 to further reduce capacitive coupling between the two decks. The vertical single capacitor 100 may be a 1T/C. Each cell deck includes

bit lines

101a, 101b, 101c extending in the X direction and

word lines

102a, 102b, 102c extending in the Y direction, wherein the

word lines

102a, 102b, and 102c may be perpendicular to the

bit lines

101a, 101b, 101c. The

FeFET

103a, 103b, 103c of each deck is placed within the recesses of the

word lines

102a, 102b, 102c and is connected to

vertical transistor

104a, 104b, 104c as can be seen in Fig. 3A. The vertical single capacitor 100 may not be limited to three decks, but may include a plurality of decks stacked on top of each other. The vertical single capacitor 100 utilizes a vertical gate all around

transistor

104a, 104b, 104c with recessed

ferroelectric gate oxide

103a, 103b, 103c to achieve nonvolatility in a 4F2 cell footprint, where F is the minimum processing size. Fig. 3B shows a vertical single capacitor 100 according to the embodiment shown in Fig. 3A in a three-dimensional view.

Fig. 4 is a plan view of a section of memory array of three-dimensional cross-point memory in accordance with the embodiment of Figs. 3A and 3B. Fig. 4 shows the memory array 400 of the vertical single capacitor 100 described in Figs. 3A and 3B. As can be seen in Fig. 4, the first section 414 is configured similarly to the second section 415. The first section 414 as described herein may also apply to the second section 415. The memory array 400 of the single capacitor 100 may be implemented as cross-point architecture. The memory array 400 includes word lines of each

cell deck

402a, 402b, 402c extending in the Y direction and bit lines of each

cell deck

401a, 401b, 401c extending in the X direction. A

FeFET

403a, 403b, 403c and

vertical transistor

404a, 404b, 404c may be implemented in each cell deck of the memory array 400 as described in Figs. 3A and 3B. The first cell deck 411 is positioned between the CMOS 406 and the second cell deck 412. The second cell deck 412 is positioned between the first cell deck 411 and the third cell deck 413. The third cell deck 413 is positioned on the second cell deck 412. The word lines and bit lines of the

cell decks

411, 412, 413 may be implemented to be parallel in all decks. Alternatively, the word lines and bit lines of the cell decks may be implemented to be perpendicular.

Figs. 7 to 12 show a method for fabricating the three-dimensional vertical single capacitor in accordance with Figs. 3A, 3B and 4. A method for fabricating the three-dimensional vertical single capacitor according to another embodiment is shown. In Fig. 6, a common plate 106 is formed for the first deck. The common plate may be a complementary metal oxide semiconductor. In Fig. 7, parallel word lines 102 are formed for the first deck 111. The word lines may be doped with polysilicon. As can be seen in Fig. 8, channel holes 107 are formed in the word lines 102, wherein the channel holes land on the common plate 106. The channel holes 107 are then recessed with tetramethylammonium hydroxide as can be seen in Fig. 9. In Fig. 10 after the recess is formed, the ferroelectric gate material 103 is deposited in the recess to form the transistor gate for vertical FeFET. In Fig. 11, the poly channel for vertical transistor 104 is formed. The vertical transistor 104 may be solid or hollow. In Fig. 12, the parallel bit lines 101 are formed to be perpendicular to the word lines 102. This method may be repeated to form the second and

third decks

112, 113 which are stacked to form the vertical 3D FeFET array of Figs. 3A and 3B.

Most of the foregoing alternative examples are not mutually exclusive, but may be implemented in various combinations to achieve unique advantages. As these and other variations and combinations of the features discussed above may be utilized without departing from the subject matter defined by the claims, the foregoing description of the embodiments should be taken by way of illustration rather than by way of limitation of the subject matter defined by the claims. As an example, the preceding operations do not have to be performed in the precise order described above. Rather, various steps can be handled in a different order, such as reversed, or simultaneously. Steps can also be omitted unless otherwise stated. In addition, the provision of the examples described herein, as well as clauses phrased as "such as, " "including" and the like, should not be interpreted as limiting the subject matter of the claims to the specific examples; rather, the examples are intended to illustrate only one of many possible embodiments. Further, the same reference numbers in different drawings may identify the same or similar elements.

Although the present disclosure herein has been described with reference to particular embodiments, it is to be understood that these embodiments are merely illustrative of the principles and applications of the present disclosure. It is therefore to be understood that numerous modifications may be made to the illustrative embodiments and that other arrangements may be devised without departing from the spirit and scope of the present disclosure as defined by the appended claims.

Claims

A cross-point architecture to implement 3D FeFET memory array comprising:

a plurality of cell decks comprising a vertical gate all around FeFET cell, wherein the plurality of cell decks are stacked;

wherein the vertical gate all around FeFET cell enables a cross point array and provides an effective cell size being 4F2 per deck;

wherein the vertical gate all around FeFET enables a 4F2 cell area; and

wherein the plurality of cell decks share a bit line.
The cross-point architecture according to claim 1, wherein the vertical gate all around FeFET cell is a 1T/C cell.
A three-dimensional memory array comprising:

a cross point array architecture, wherein the cross point array architecture comprises a plurality of cell decks including word lines and bit lines,

the word lines of the plurality of cell decks are parallel or perpendicular,

the bit lines of the plurality of cell decks are perpendicular to the word lines, wherein the plurality of cell decks further comprise a FeFET cell.
The three-dimensional memory array according to claim 4, wherein the FeFET cell includes a vertical FeFET transistor.
The three-dimensional memory array according to claim 5, wherein the FeFET cell is accessed by the bit lines through the vertical FeFET transistor.
A three-dimensional FeRAM memory cell comprising

a vertical gate all around FeFET,

wherein the vertical gate all around FeFET includes a recessed ferroelectric gate dielectric and a solid or hollow channel.
The three-dimensional FeRAM memory cell according to claim 6, wherein the vertical gate includes a vertical FeFET transistor.
The three-dimensional FeRAM memory cell according to claim 6, wherein the vertical gate is accessed by bit lines through the vertical FeFET transistor.
A method of fabricating a three-dimensional memory array comprising:

forming parallel polysilicon word lines for a first deck;

forming an array of vertical channel holes in the parallel polysilicon word lines;

recessing a portion in the array of vertical channel holes;

depositing ferroelectric gate dielectric material into the recess; and

inserting a vertical transistor into the vertical channel to form a three-dimensional FeFET memory cell on a vertical transistor;

wherein the vertical transistor is solid or hollow.
The method according to claim 8, further comprising forming parallel bit lines and positioning the parallel bit lines perpendicularly to the parallel polysilicon word lines.
The method according to claim 8, wherein the method is repeated to form a second deck.