WO2022082718A1

WO2022082718A1 - Architecture, method and memory cell for 3d nand style mfmis fefet to enable 3d ferroelectric nonvolatile data storage

Info

Publication number: WO2022082718A1
Application number: PCT/CN2020/123204
Authority: WO
Inventors: Jun Liu
Original assignee: Yangtze Advanced Memory Industrial Innovation Center Co., Ltd
Priority date: 2020-10-23
Filing date: 2020-10-23
Publication date: 2022-04-28
Also published as: CN112470277A

Abstract

A three-dimensional memory including a substrate (310), a stack of alternating stack buffer layers (320) and stack conductor layers (330) formed on the substrate (310), and a channel formed in the stack and extending in a depth direction from a top surface of the stack to a top surface of the substrate (310). The channel may include a channel insulator layer (338) formed on a surface of the stack in the channel and a channel semiconductor layer (340) formed on a surface of the channel insulator layer (338). The stack conductor layer (330) may include a first metal section, a second metal section, and a ferroelectric material (334) positioned between the first metal section and the second metal section.

Description

[Title established by the ISA under Rule 37.2] ARCHITECTURE, METHOD AND MEMORY CELL FOR 3DNAND STYLE MFMIS FEFET TO ENABLE 3D FERROELECTRIC NONVOLATILE DATA STORAGE

TECHNICAL FIELD

The present disclosure generally relates to three-dimensional electronic memories, and more particularly, to increasing the density of memory cells in 3D NAND-style Ferroelectric field-effect transistor (FeFET) memories.

BACKGROUND

Planar memory cells are scaled to smaller sizes by improving process technology, circuit design, programming algorithm, and fabrication process. However, as feature sizes of the memory cells approach a lower limit, planar process and fabrication techniques become challenging and costly. As such, memory density for planar memory cells approaches an upper limit. A three-dimensional (3D) memory architecture for accessing memory of the three-dimensional (3D) memory architecture can address the density limitation in planar memory cells.

As semiconductor technology advances, 3D memory devices, such as 3D NAND memory devices, keep scaling more buffer/conductor layers. As a result, fabrication processes within the channel holes of the buffer/conductor layers become more and more difficult.

SUMMARY

The presently disclosed 3D memory architectures solve the problems of current state of the art 3D memory architectures, and provide many more benefits. The presently disclosed architectures have the advantages of increasing data storage density and reducing memory bit cost. In particular, the presently disclosed architectures utilize recessed mid-metal gates to realize an increase coupling ratio and to improve FeFET switching capability. Formation of the gates within a three-dimensional stack, one on top of the other, may form a NAND string to increase bit density and to reduce cost while providing better performance and power than conventional 3D NAND memory cells.

In accordance with an aspect, provided is a three-dimensional memory including a substrate, a stack of alternating stack buffer layers and stack conductor layers formed on the substrate, and a channel formed in the stack and extending in a depth direction from a top surface of the stack to a top surface of the substrate. The channel may include a channel insulator layer formed on a surface of the stack in the channel, and a channel semiconductor layer formed on a surface of the channel insulator layer. At least one stack conductor layer may include a first metal section, a second metal section, and a ferroelectric material positioned between the first metal section and the second metal section.

In some examples, the first metal section may have a first thickness in the depth direction, and the second metal section may have a second thickness in the depth direction, and the first thickness may be greater than the second thickness.

In some examples, the ferroelectric material may have a thickness in the depth direction equal to the first thickness at an interface between the ferroelectric material and the first metal section.

In some examples, the ferroelectric material may be formed as a layer covering each of the first metal section and surfaces of the stack buffer layers adjacent to the at least one stack conductor layer and having a recess, and the second metal section may be formed in the recess of the ferroelectric material.

In some examples, the second metal section, the ferroelectric material, the first metal section, the channel insulator and the channel semiconductor layer may be configured to form a field effect transistor (FET) .

In some examples, the channel insulator layer may be a silicon dioxide layer and the channel semiconductor layer may be a polysilicon layer.

In some examples, each of the first metal section and the second metal section may include a platinum-rhodium alloy layer.

In some examples, the ferroelectric material may be a lead zirconate titanate thin (PZT) film.

In accordance with another aspect, provided is a method of forming a three-dimensional memory. The method may include forming a stack of alternating stack buffer layers and stack separator layers on a top surface of a substrate, forming a channel in the stack, the channel extending in a depth direction from a top surface of the stack to the top surface of the substrate, removing portions of the stack separator layers exposed by forming the channel, depositing a first metal layer over the exposed portions of the stack separator layers, removing a portion of the first metal layer in the channel to form first metal sections separated by the stack buffer layers, depositing a channel insulator layer on a surface of the stack in the channel, depositing a channel semiconductor layer on a surface of the channel insulator layer, removing remaining portions of the stack separator layer from the stack, depositing ferroelectric material sections over the first metal sections, and depositing second metal sections over the ferroelectric material sections.

In some examples, the stack separator layers may be nitride layers, and the portions and remaining portions of the stack separator layers may be removed by a wet chemical batch process using hot phosphoric acid.

In some examples, removing a portion of the first metal layer may include an isotropic etching process.

In some examples, removing a portion of the first metal layer may expose a top surface of the substrate in the channel.

In some examples, the channel insulator layer may be deposited over the top surface of the substrate, and the method may include removing a portion of the channel insulator layer in contact with the top surface of the substrate to expose the top surface of the substrate. The channel semiconductor layer may be deposited on the exposed top surface of the substrate.

In some examples, the method may further include, after depositing the channel semiconductor layer, filling a remaining cavity of the channel with an insulating material.

In accordance with yet another aspect, provided is a ferroelectric memory cell formed between buffer layers of a stack layout formed on a substrate. The ferroelectric memory cell may include a metal-insulator-semiconductor structure having a first capacitance and a metal-ferroelectric-metal structure having a second capacitance and formed in a cavity between the buffer layers. An insulator and semiconductor of the metal-insulator-semiconductor structure may be formed on an interior surface of a channel extending vertically through the stack layout to a top surface of the substrate.

In some examples, the metal-insulator-semiconductor structure and the metal-ferroelectric-metal structure may be configured to divide a gate voltage applied to a gate of the ferroelectric memory cell based on a ratio of the first capacitance and the second capacitance.

In some examples, the ferroelectric memory cell may be configured to operate as a field-effect-transistor.

In some examples, the metal-ferroelectric-metal structure may include a first metal section having a first thickness and in contact with the insulator, a second metal section having a second thickness less than the first thickness, and a ferroelectric material positioned between the first metal section and the second metal section.

In some examples, the ferroelectric material may have a recess, and the second metal section may be formed in the recess of the ferroelectric material.

In accordance with yet a further aspect, provided is a three-dimensional ferroelectric memory cell array including a stack of alternating stack buffer layers and stack conductor layers formed on a substrate, each stack conductor layer having formed therein a metal-ferroelectric-metal structure, and a channel formed in the stack and extending in a depth direction from a top surface of the stack to a top surface of the substrate, the channel including a vertical channel semiconductor layer and a vertical channel insulator layer in connection with each of the metal-ferroelectric-metal structures to form a plurality of metal-insulator-semiconductor structures.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing aspects, features and advantages of the present disclosure will be further appreciated when considered with reference to the following description of exemplary embodiments and accompanying drawings, wherein like reference numerals represent like elements. In describing the exemplary embodiments of the present disclosure illustrated in the drawings, specific terminology may be used for the sake of clarity. However, the aspects of the present disclosure are not intended to be limited to the specific terms used.

Fig. 1 is a functional diagram of a conventional Fe-FET memory cell.

Fig. 2 is a side view of a section of a conventional 3D NAND-style FeFET memory.

Fig. 3 is a side view of a 3D NAND-style FeFET memory according to an embodiment.

Fig. 4 is a flow diagram of a routine for forming the 3D NAND-style FeFET memory of Fig. 3.

Figs. 5A-5I are side views of steps of the routine of Fig. 4.

DETAILED DESCRIPTION

The present technology is applied in the field of three-dimensional memory, and particularly a three-dimensional NAND (3D NAND) -style ferroelectric field-effect transistor (FeFET) memory.

A generalized example of a basic FeFET is shown in Fig. 1. In particular, Fig. 1 is a side view of a conventional FeFET memory cell 100. The memory cell 100 is formed on a substrate 110. In the particular example of Fig. 1, the FeFET is an n-channel FeFET, in which the p-doped substrate 112 has n-doped source and

drain regions

114, 116 positioned at the source 122 and drain 124 of the transistor. A metal gate contact 132 is formed over a gate region of the substrate between the source 122 and drain 124 regions. In operation, a voltage applied to the gate contact 132 can control the opening of a channel 142 between the source 122 and drain 124, causing a flow of current between the source 122 and drain 124. The gate contact 132 may be arranged as a contact for a word line in a memory array, whereby a voltage applied to the gate biases the memory cell and causes data to be programmed to or read from the cell if a voltage is applied across the source and drain.

Unlike a standard field-effect transistor (FET) , which conventionally features an insulator or dielectric material between the metal gate and substrate, such as an oxide, the FeFET includes a ferroelectric material 134 in place of the insulator or dielectric material. Additionally, unlike a standard FeRAM, in which a capacitor is provided separate from the transistor, the ferroelectric material of the FeFET serves as both the transistor gate and the capacitor. The ferroelectric material 134 may be a bismuth titanate (Bi ₄Ti ₃O ₁₂) ferroelectric, or Pb _1-xLn _xTiO ₃ (PLT) or other related mixed zironconate/titanates (PLZT) formed as a thin film. The ferroelectric material features two stable polarization states, enabling it to store a binary state (e.g., above threshold voltage vs. below threshold voltage) even when a bias voltage is removed.

One alternative to the standard FeFET structure is a metal-ferroelectric-metal-insulator-semiconductor (MFMIS) structure. Interfacing ferroelectric materials with semiconductor materials can cause intermixing problems, which can cause degradation of the ferroelectric material. In an MFMIS structure, the ferroelectric layer is separated from the semiconductor layer, so the problems of intermixing and degradation are avoided.

The MFMIS structure may be thought of as two structures: an MFM structure and an MIS structure. These structures may share a single middle-metal (or mid-metal) layer, or each structure may have its own mid-metal layer interfacing the other structure’s mid-metal layer. Each structure may have its own capacitance, whereby a voltage applied to the gate of the MFMIS structure is divided between the two capacitive structures. Depending on the type of insulator material used to buffer the semiconductor from the ferroelectric material, a relatively high voltage may be needed to operate the MFMIS FeFET.

Efforts have been made to increase storage density for FeFET memory cells. Fig. 2 shows an example involving a 3D NAND-style MFMIS cell array 200, in which a stack of alternating insulating buffer layers 220 and conducting layers 232 are formed on a substrate 210. The MFMIS FeFET cells of the array 200 are aligned vertically within a channel that is formed in the stack.

Each cell may be considered its own MFMIS structure, including one of the metal layers 232 formed in the alternating stack, and a portion of each of the ferroelectric layer 234, the second metal or mid-metal layer 236, the insulator layer 238 and the semiconductor layer 240 overlaying the metal layer 232. The ferroelectric layer 234, mid-metal layer 236, insulator layer 238 and semiconductor layer 240 may be formed vertically around a perimeter of a hollowed out channel formed in the stack. An insulating material 222 may be used to fill a portion of the channel not occupied by the other layers. Similar to the FeFET structure of Fig. 1, each metal layer 232 may be connected to a word line of the memory array, whereby a voltage applied to the contact of the metal layer 232 causes data to be programmed to or read from the cell if a voltage is applied to a bit line connected to a top of the channel.

In the example of Fig. 2, the mid-metal layer functions as the middle electrode of the MFMIS structure, and this middle electrode is shared by all cells in the channel. However, sharing the middle electrode causes severe crosstalk among cells situated in the same channel. An additional difficulty is that the layering process for the mid-metal layer 236, the insulator layer 238 and the semiconductor layer 240 carries a risk that a short circuit may occur between the middle electrode and the semiconductor layer, for instance at a top or bottom edge of the channel.

Fig. 3 shows a 3D NAND-style MFMIS cell array 300 according to an embodiment of the present disclosure. The array includes multiple MFMIS cell structures arranged in a vertical direction. The MFMIS cell structures may be formed within a stack of alternating stack buffer layers 320 and stack conductor layers 330 formed on a substrate 310. Furthermore, the MFMIS cell structures may be formed in a vertical channel formed in the stack layers 320, 330 in a depth direction. In some examples, the stack conductor layers 310 may have a thickness of between about 80 nm to 110 nm, and may preferably be about 100 nm, and the stack buffer layers 320 may have a thickness of between about 90 nm to 160 nm, and may preferably be about 150 nm.

Each stack conductor layer may include a plurality of conductor layers that make up part of the MFMIS structure. In the example of Fig. 3, the stack conductor layer 330 includes each of a gate metal 332 positioned as the gate contact of the MFMIS structure, a ferroelectric material 334, and a mid-metal 336 that serves both as the metal of the MIS portion of the MFMIS structure, as well as the metal opposite the gate metal 332 in the MFM portion of the MFMIS structure. The ferroelectric material is positioned in between each of the gate metal 332 and the mid-metal 334. Each of the gate metal 332 and mid-metal portions may include a layer of conductive material, such as a platinum-rhodium alloy. The ferroelectric material may include a layer of ferroelectric material, such as a lead zirconate titanate (PZT) thin film.

In the example of Fig. 3, the channel is a cylindrical hole that extends from a top surface of the stack to a top surface of the substrate 310. Additionally, in the example of Fig. 3, the channel is tapered, having a diameter that is larger at the top surface of the stack than at the top surface of the substrate 310. Rounding and tapering the channel may improve the ability to cleanly deposit uniform layers onto the sidewalls of the channel. Nonetheless, in other examples, the channel may be a different shape, such as oblong or square, and may have a consistent diameter from top to bottom.

In the example of Fig. 3, a channel insulator layer 338 is formed on a surface of the sidewall of the channel and within the channel. The channel insulator layer 338 may include an insulator material such as silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. The silicon dioxide layer may have a thickness of between about 5 to 15 nm. The channel insulator layer 338 functions as the insulator in the middle of the MIS portion of the MFMIS structure. The channel insulator layer 338 contacts the mid-metal portion 336 of each of the MFM portions formed in the conductor layers 330 of the stack, whereby the mid metal portion 336 functions as the metal portion in the MIS component of the MFMIS structure.

A channel semiconductor layer 340 is formed on the surface of the channel insulator layer 338. The channel semiconductor layer 340 may include a semiconductor material such as polysilicon. The polysilicon layer may have a thickness of between about 5 to 15 nm. The channel insulator layer 338 separates the channel semiconductor layer 340 from the mid-metal portion 336 of each conductor layer 330 in the stack. As such, the layering of the layering channel semiconductor layer 338 and channel semiconductor layer 340 over the interior surface of the channel results in the formation of a plurality of metal-insulator-semiconductor structures. Additionally, with the layering of two metal sections within each conductor layer 330 and the positioning of a ferroelectric material 334 between each of the two

metal sections

332, 336, layering of the layering channel semiconductor layer 338 and channel semiconductor layer 340 over the interior surface of the channel results in the formation of a plurality of MFMIS structures.

In the example of Fig. 3, the sections of the MFM portion have different widths or thicknesses in the depth direction. In particular, the gate metal 332 has a thickness of between about 5 to 15 nm, whereas each of the ferroelectric material 334 and the mid metal 336 have thicknesses greater than that of the gate metal, such as between about 5 to 15 nm. More particularly, a portion of the conductor layer 330 in which the mid metal 336 is deposited may be filled with the mid metal, 336, such that an entire height of the conductor layer 330 in the depth direction is filled with the mid metal in that portion. The ferroelectric material 334 may then be deposited over a remaining portion of the conductor layer 330, but without filling an entire height of the remaining portion of the conductor layer 330. For example, the ferroelectric material may be formed as a layer over a top surface of the conductor layer 330 (adjacent to the buffer layer immediately above) and bottom surface of the conductor layer 330 (adjacent to the buffer layer immediately below) and on a sidewall of the mid metal 336. This may leave a cavity into which the gate metal 332 is then deposited. The layer of ferroelectric material may have a thickness of between about 5 to 15 nm, although the portion of the ferroelectric material 334 interfacing with the mid metal 336 may have a thickness in the depth direction equal to that of the mid metal 336 thickness.

Collectively, the gate metal 332, the ferroelectric material 334, the mid metal 336, the channel insulator layer 338 and the channel semiconductor layer 340 form a field effect transistor (FET) having two capacitance regions corresponding to the MFM and MIS structures therein.

Fig. 4 is a flow diagram of a routine 400 for forming the example 3D NAND-style FeFET memory shown in Fig. 3. It should be understood that, in some instances, the order of steps in routine 400 may be changed. Further, in some instances, steps of the routine 400 may be omitted, other steps may be added, or any combination of the two. Additionally, Figs. 5A-5I are side views of a 3D NAND-style FeFET memory being fabricated according to the steps of routine 400 in order to illustrate the routine.

At block 402 the stack is formed on a top surface of a substrate. Formation of the stack layers may involve known deposition techniques and processes, including but not limited to atomic layer deposition (ALD) , chemical vapor deposition (CVD) , and physical vapor deposition (PVD) . The stack may include alternating stack buffer layers and stack separator layers. The buffer layers may include a buffer material, such as an oxide material, for instance silicon dioxide. The stack separator layers may serve as placeholder material which is eventually removed and replaced with the conductor materials for the MFM portion of the memory cell structure. For example, the separator layers may include a nitride material.

At block 404, one or more channels are formed in the stack. The channel may be formed in a depth direction extending from a top surface of the stack to the top surface of the substrate. The channels may be formed using any conventional process known in the art, such as a patterning and/or dry or wet etching process. Fig. 5A illustrates a portion of a semiconductor stack having alternating oxide layers 320 and nitride layers 325 formed on a substrate 310, and two channels formed within the stack.

Forming the channels results in exposure of the stack layers along an interior surface of the channels. At block 406, recesses are formed in the separator layers of the stack. The recesses may be formed by removing portions of the nitride. This may be accomplished using a wet chemical batch process, such as one that uses hot phosphoric acid. Fig. 5B shows a plurality of recesses 326 formed along an edge of the channels. As a result of the recess forming step, a side-to-side length of any given oxide layer may be greater than a side to side length of each of the immediately adjacent nitride layers above and below the given oxide layer.

At block 408, the mid-metal layer is deposited over the exposed portions and into the recesses of the nitride layers . Depositing the mid-metal layer causes the recesses formed at block 406 to be filled with the mid-metal. Excess mid-metal is deposited in order to ensure that all recesses are completely filled. Fig. 5C shows the mid-metal 336 having been formed over the channels and filling the recesses 326. As can be seen from Fig. 5C, enough mid-metal 336 may be deposited to form a complete layer of the material over the interior surface of the channel.

At block 410, the layer of mid-metal formed on the interior surface of the channel is removed. Removing the mid-metal may involve an isotropic etching process, and may result in the portions of the mid-metal formed in the recesses being separated from one another. Stated another way, the oxide layers may fully separate each mid-metal from the adjacent mid-metals. Fig. 5D shows the individual mid-metal portions 336 separated from one another, with the remaining portion of the mid-metal, previously formed within the channel, having been removed.

At block 412, a channel insulator layer is deposited on an interior surface of the channel. The channel insulator layer may be silicon dioxide, and may be deposited in a uniform layer over each of the channels. Fig. 5E shows a channel insulator layer 338 deposited with a relatively uniform thickness. In some instances, tapering of the channel sidewalls makes the relatively uniform deposition easier to perform.

At block 414, a portion of the channel insulator layer at a base of the channel is removed. The portion may be removed using any conventional process known in the art, such as a patterning and/or dry or wet etching process. Removal of the channel insulator layer portion may expose the top surface of the substrate at the bottom of the channel. Fig. 5E also shows a bottom portion of the channel insulator layer 338 missing where the layer comes in contact with the top surface of the substrate 310.

At block 416, a channel semiconductor layer is deposited on a surface of the channel insulator layer. The channel semiconductor layer may be polysilicon, and the deposition may cover the entire channel in a relatively uniform layer of the polysilicon. The layer may be formed using known thin-film deposition processes, such as ALD, CVD, PVD, or another suitable process. Fig. 5E also shows a channel semiconductor layer 340 having been deposited with a relatively uniform thickness over the channel sidewalls as well as the exposed top surface of the substrate 310. As noted above in connection with the channel insulator layer, in some instances, tapering of the channel sidewalls makes the relatively uniform deposition easier to perform.

At block 418, a remaining unfilled portion of the channel is filled with a filler material. The filler material may be an electrically insulating material such as a dielectric, or more particularly such as an oxide, or even more particularly such as silicon dioxide. The filler material is provided to cover the channel semiconductor layer and ensure that the memory cells are electrically insulated. In the example of Fig. 5F, the entire channel is filled with a filler material 322, and the channel semiconductor layer 340 is fully covered by the material, although in other cases, an opening may be left in the channel.

At block 420, remaining portions of the stack separator layers are removed. In the case of nitride separate layers, the removal may be accomplished using a wet chemical batch process, such as one that uses hot phosphoric acid. Removal of the nitride forms recesses in contact with the mid-metal within the stack. Fig. 5G shows a plurality of second recesses 328 formed within the channels’ stack layers.

At block 422, a layer of ferroelectric material sections are deposited in the recesses formed by removing the stack separator layers. The ferroelectric material may cover and contact the mid-metal in the stack. Fig. 5H shows a thin film of ferroelectric material 334 formed in the recesses 328 left by removing the remaining nitride, and further shows the ferroelectric material 334 covering the mid-metal 338 as well covering as upper and lower surfaces of the recesses 328.

At block 424, a layer of gate metal is deposited in a remaining portion of the recesses formed by removing the stack separator layers. The layer of gate metal may be formed over the ferroelectric material, such that the ferroelectric material is sandwiched between the gate metal and mid-metal. Fig. 5I shows gate metal 432 filling the entire remaining portions of the recesses 328 left by removing the remaining nitride, and covering the ferroelectric material 334 as well covering as upper and lower surfaces of the recesses 328.

The routine 400 results in each channel including a plurality of electrically separated FeFET memory cells aligned in a vertical direction, whereby each nitride layer of the original stack is replaced with a gate of a separate transistor element. Additionally, each transistor element has the advantages of the MFMIS structure for FeFET stacks, since each nitride layer of the original stack is replaced with a ferroelectric material sandwiches between two metals. Lastly, each transistor element has the advantages of an electrically isolated FeFET element, since the MFM portion of each structure is physically separated and electrically isolated from the other MFM portions of the adjacent cells. This may result in a reduction or even elimination of crosstalk between components of the array.

Additionally, the routine 400 results in an increased surface area between the mid-metal and ferroelectric material. Previously, the coupling area between the gate metal and ferroelectric materials was limited to a cross-sectional area of the gate metal exposed by the channel, since the ferroelectric material would be deposited entirely in the channel and would contact the gate metal only at that exposed cross-section. However, by depositing both the ferroelectric material and the gate metal within a conductive layer of the stack, a coupling area of the two materials can be controlled based on the geometries of the deposited materials. Particularly, in the examples shown above, the ferroelectric material is formed as a thin film having a cavity into which the gate metal can be filled. The concave nature of the shape of the ferroelectric material increases its surface area, which in turn increases the coupling area between it and the gate metal. Ultimately, this can result in an increased electric field in the ferroelectric film, achieving a better coupling ratio and can improve FeFET switching capability.

The presently disclosed embodiments may be implemented as part of a three-dimensional ferroelectric nonvolatile data storage device, such as a memory array including FeFET-based memory cells. In practice, bit lines may be positioned above the channels formed in the stack, and each gate metal electrode may be connected to a respective word line. As a result, a given memory cell may be accessed by biasing each of a bit line connected to the channel in which the given memory cell is formed, a word line connected to the gate electrode of the given memory cell. Accessing a memory cell may involve, reading data from the memory cell, programming data to the memory cell, or a combination of the two.

Although the present disclosure herein has been described with reference to particular embodiments, it is to be understood that these embodiments are merely illustrative of the principles and applications of the present disclosure. It is therefore to be understood that numerous modifications may be made to the illustrative embodiments and that other arrangements may be devised without departing from the spirit and scope of the present disclosure as defined by the appended claims.

Claims

A three-dimensional memory comprising:

a substrate;

a stack of alternating stack buffer layers and stack conductor layers formed on the substrate; and

a channel formed in the stack and extending in a depth direction from a top surface of the stack to a top surface of the substrate, wherein the channel includes:

a channel insulator layer formed on a surface of the stack in the channel; and

a channel semiconductor layer formed on a surface of the channel insulator layer, wherein at least one stack conductor layer comprises:

a first metal section;

a second metal section; and

a ferroelectric material positioned between the first metal section and the second metal section.
The three-dimensional memory according to claim 1, wherein the first metal section has a first thickness in the depth direction, and wherein the second metal section has a second thickness in the depth direction, wherein the first thickness is greater than the second thickness.
The three-dimensional memory according to claim 2, wherein the ferroelectric material has a thickness in the depth direction equal to the first thickness at an interface between the ferroelectric material and the first metal section.
The three-dimensional memory according to claim 3, wherein the ferroelectric material is formed as a layer covering each of the first metal section and surfaces of the stack buffer layers adjacent to the at least one stack conductor layer and having a recess, and wherein the second metal section is formed in the recess of the ferroelectric material.
The three-dimensional memory according to claim 1, wherein the second metal section, the ferroelectric material, the first metal section, the channel insulator and the channel semiconductor layer are configured to form a field effect transistor (FET) .
The three-dimensional memory according to claim 1, wherein the channel insulator layer is a silicon dioxide layer and wherein the channel semiconductor layer is a polysilicon layer.
The three-dimensional memory according to claim 1, wherein each of the first metal section and the second metal section includes a platinum-rhodium alloy layer.
The three-dimensional memory according to claim 1, wherein the ferroelectric material is a lead zirconate titanate thin (PZT) film.
A method of forming a three-dimensional memory comprising:

forming a stack of alternating stack buffer layers and stack separator layers on a top surface of a substrate;

forming a channel in the stack, the channel extending in a depth direction from a top surface of the stack to the top surface of the substrate;

removing portions of the stack separator layers exposed by forming the channel;

depositing a first metal layer over the exposed portions of the stack separator layers;

removing a portion of the first metal layer in the channel to form first metal sections separated by the stack buffer layers;

depositing a channel insulator layer on a surface of the stack in the channel;

depositing a channel semiconductor layer on a surface of the channel insulator layer;

removing remaining portions of the stack separator layer from the stack;

depositing ferroelectric material sections over the first metal sections; and

depositing second metal sections over the ferroelectric material sections.
The method according to claim 9, wherein the stack separator layers are nitride layers, and wherein the portions and the remaining portions of the stack separator layers are removed by a wet chemical batch process using hot phosphoric acid.
The method of claim 9, wherein removing a portion of the first metal layer comprises an isotropic etching process.
The method of claim 9, wherein removing a portion of the first metal layer exposes a top surface of the substrate in the channel.
The method of claim 12, wherein the channel insulator layer is deposited over the top surface of the substrate, wherein the method further comprises removing a portion of the channel insulator layer in contact with the top surface of the substrate to expose the top surface of the substrate, and wherein the channel semiconductor layer is further deposited on the exposed top surface of the substrate.
The method of claim 9, further comprising, after depositing the channel semiconductor layer, filling a remaining cavity of the channel with an insulating material.
A ferroelectric memory cell formed between buffer layers of a stack layout formed on a substrate, the ferroelectric memory cell comprising:

a metal-insulator-semiconductor structure having a first capacitance, wherein an insulator and semiconductor of the metal-insulator-semiconductor structure are formed on an interior surface of a channel extending vertically through the stack layout to a top surface of the substrate; and

a metal-ferroelectric-metal structure having a second capacitance and formed in a cavity between the buffer layers.
The ferroelectric memory cell according to claim 15, wherein the metal-insulator-semiconductor structure and the metal-ferroelectric-metal structure are configured to divide a gate voltage applied to a gate of the ferroelectric memory cell based on a ratio of the first capacitance and the second capacitance.
The ferroelectric memory cell according to claim 15, wherein the ferroelectric memory cell is configured to operate as a field-effect-transistor.
The ferroelectric memory cell according to claim 15, wherein the metal-ferroelectric-metal structure comprises:

a first metal section having a first thickness and in contact with the insulator;

a second metal section having a second thickness less than the first thickness; and

a ferroelectric material positioned between the first metal section and the second metal section.
The ferroelectric memory cell according to claim 18, wherein the ferroelectric material has a recess, and wherein the second metal section is formed in the recess of the ferroelectric material.
A three-dimensional ferroelectric memory cell array, comprising:

a stack of alternating stack buffer layers and stack conductor layers formed on a substrate, wherein each stack conductor layer has formed therein a metal-ferroelectric-metal structure; and

a channel formed in the stack and extending in a depth direction from a top surface of the stack to a top surface of the substrate, wherein the channel includes a vertical channel semiconductor layer and a vertical channel insulator layer in connection with each of the metal-ferroelectric-metal structures to form a plurality of metal-insulator-semiconductor structures.