CN117615575A

CN117615575A - Semiconductor structure

Info

Publication number: CN117615575A
Application number: CN202311740360.0A
Authority: CN
Inventors: 苏义旭; 王枫; 刘忠明; 张阳; 于业笑; 方嘉; 代成仁
Original assignee: Changxin Technology Group Co ltd
Current assignee: Changxin Technology Group Co ltd
Priority date: 2023-12-15
Filing date: 2023-12-15
Publication date: 2024-02-27

Abstract

Embodiments of the present disclosure relate to the field of semiconductors, and provide a semiconductor structure having an array region, including: the active columns are positioned in the array area, are arranged along a first direction and a second direction, and extend along a third direction; a word line extending along a first direction, the word line covering sidewalls of the plurality of active pillars along the first direction; a bit line extending in a second direction, the bit line connecting one ends of the plurality of active pillars in a third direction along the second direction; a word line plug located at a side of the word line adjacent to the bit line in the third direction and electrically contacting the word line; a bit line plug located at a side of the bit line away from the active pillar in a third direction and electrically contacting the bit line; and on the plane where the first direction and the second direction are located, the orthographic projection of the bit line plug and the orthographic projection of the word line plug are both positioned in the array region, so that the integration density of the semiconductor structure is at least improved.

Description

Semiconductor structure

Technical Field

Embodiments of the present disclosure relate to the field of semiconductors, and in particular, to a semiconductor structure.

Background

The memory is a memory means for storing programs and various data information. Random Access Memory (Random Access Memory, RAM) used in a typical computer system can be divided into dynamic Random Access Memory (Dynamic Random Access Memory, DRAM) and Static Random Access Memory (SRAM), which are semiconductor Memory devices commonly used in computers and are composed of a plurality of repeated Memory cells.

The memory cell generally includes a capacitor and a transistor, one of a source or a drain of the transistor is connected to a bit line structure, the other of the source or the drain is connected to the capacitor, the capacitor includes a capacitance contact structure and a capacitance, and a word line structure of the memory cell can control opening or closing of a channel region of the transistor, thereby reading data information stored in the capacitor through the bit line structure, or writing data information into the capacitor through the bit line structure for storage.

Currently, the integration density of semiconductor structures is to be increased.

Disclosure of Invention

Embodiments of the present disclosure provide a semiconductor structure that is at least beneficial for improving the integration density of the semiconductor structure.

According to some embodiments of the present disclosure, an aspect of an embodiment of the present disclosure provides a semiconductor structure having an array region, including: the active columns are positioned in the array area, are arranged along a first direction and a second direction, and extend along a third direction; a word line extending along a first direction, the word line covering sidewalls of the plurality of active pillars along the first direction; a bit line extending in a second direction, the bit line connecting one ends of the plurality of active pillars in a third direction along the second direction; a word line plug located at a side of the word line adjacent to the bit line in the third direction and electrically contacting the word line; a bit line plug located at a side of the bit line away from the active pillar in a third direction and electrically contacting the bit line; on the plane of the first direction and the second direction, the orthographic projection of the bit line plug and the orthographic projection of the word line plug are both positioned in the array area.

In some embodiments, adjacent bit line plugs are offset in a first direction and/or adjacent word line plugs are offset in a second direction.

In some embodiments, adjacent bit line plugs are aligned in a first direction and/or adjacent word line plugs are aligned in a second direction.

In some embodiments, the word line plug includes first and second portions connected in sequence, the first portion being located between adjacent active pillars and in electrical contact with the word line, the second portion being located on a side of the first portion in a third direction away from the word line, the first portion having a smaller dimension in the first direction than the second portion.

In some embodiments, further comprising: and the protective layer covers two opposite side surfaces of the plurality of active columns along the first direction in the second direction, and covers two opposite side surfaces of the bit line along the first direction, and the word line plug is positioned between the protective layers of the side surfaces of the two adjacent active columns.

In some embodiments, the protective layer comprises: the first protection layer covers two side surfaces of the bit line opposite to each other along the first direction and covers two side surfaces of the active column opposite to each other along the first direction; the second protection layer covers the surface of the first protection layer far away from the bit line and the surface of the first protection layer far away from the active column, and the word line plug is positioned between the second protection layers on the side surfaces of two adjacent active columns; wherein the material of the first protective layer is different from the material of the second protective layer.

In some embodiments, further comprising: and the dummy bit line extends along the second direction, is positioned at the outermost side of the bit lines arranged along the first direction, and is overlapped with the orthographic projection of the word line plug on the plane along the first direction and the second direction.

In some embodiments, the dummy bit line has a first width and the bit line has a second width in the first direction, the first width being greater than the second width and less than 2 times the second width.

In some embodiments, the dimension of the bit line plug is greater than the dimension of the bit line in a direction perpendicular to the second direction.

In some embodiments, further comprising: and the capacitor extends along the third direction, is positioned on one side of the active column away from the bit line along the third direction and is electrically contacted with the active column.

The technical scheme provided by the embodiment of the disclosure has at least the following advantages:

in the semiconductor structure provided by the embodiment of the disclosure, the active pillars extend along the third direction and are arranged along the first direction and the second direction so as to form a transistor structure arranged along the first direction and the second direction, and the transistor structure extends along the third direction. The word lines cover the sidewalls of the plurality of active pillars in a first direction, and the bit lines connect one ends of the plurality of active pillars in a second direction, so that the word lines and the bit lines can control the plurality of transistor structures in the first direction and the second direction, respectively. The semiconductor structure may have an array region for forming transistor structures arranged in an array, and a peripheral region for forming a circuit structure for controlling the transistor structures, the active pillars being located in the array region of the semiconductor structure, the correspondingly formed transistor structures being located in the array region, and the orthographic projections of the word line plugs and the orthographic projections of the bit line plugs being located in the array region on a plane in which the first direction and the second direction are located, that is, the word line plugs and the bit line plugs being located in the array region without changing the division of the array region and the peripheral region in the conventional semiconductor structure, so that the space occupied by the word line plugs and the bit line plugs in the peripheral region can be avoided, and the integration density of the semiconductor structure is advantageously improved.

Drawings

One or more embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings, which are not to be construed as limiting the embodiments unless specifically indicated otherwise; in order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the conventional technology, the drawings required for the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present disclosure, and other drawings may be obtained according to these drawings without inventive effort to those of ordinary skill in the art.

FIG. 1 is a schematic diagram of a partial structure of an array region of a semiconductor structure according to an embodiment of the present disclosure;

FIG. 2 is a schematic diagram showing a partial cross-sectional structure of a first semiconductor structure along a direction parallel to a bit line according to one embodiment of the present disclosure;

FIG. 3 is a schematic diagram showing a partial cross-sectional structure of a first semiconductor structure along a direction parallel to a word line according to an embodiment of the present disclosure;

FIG. 4 is a schematic diagram showing a partial cross-sectional structure of a second semiconductor structure along a direction parallel to a bit line according to one embodiment of the present disclosure;

Fig. 5 to 9 are schematic partial cross-sectional views of various semiconductor structures along a direction parallel to a word line according to an embodiment of the present disclosure;

FIG. 10 is a schematic diagram of a seventh semiconductor structure according to an embodiment of the present disclosure along a partial cross-sectional structure parallel to a word line direction;

FIG. 11 is a partial top view of the semiconductor structure of FIG. 10 along a third direction;

fig. 12-18 are partial top views of various semiconductor structures along a third direction provided in accordance with an embodiment of the present disclosure;

fig. 19 to 27 are schematic structural diagrams corresponding to respective steps of a method for manufacturing a semiconductor structure according to another embodiment of the present disclosure.

Detailed Description

Embodiments of the present disclosure will be described in detail below with reference to the attached drawings. However, those of ordinary skill in the art will understand that in the various embodiments of the present disclosure, numerous technical details have been set forth in order to provide a better understanding of the present disclosure. However, the technical solutions claimed in the present disclosure can be implemented without these technical details and with various changes and modifications based on the following embodiments. The semiconductor structure provided in this embodiment will be described in detail below with reference to the accompanying drawings.

Fig. 1 is a schematic partial structure diagram of an array region of a semiconductor structure according to an embodiment of the present application.

Referring to fig. 1, a semiconductor structure includes: a plurality of active pillars 100, word lines 200, bit lines 300, word line plugs 201, and bit line plugs 301. Wherein the active pillars 100 are arranged along the first direction X and the second direction Y, and the active pillars 100 extend along the third direction Z; the word line 200 extends along a first direction X, in which the word line 200 covers sidewalls of the plurality of active pillars 100; the bit line 300 extends in the second direction Y, and in the second direction Y, the bit line 300 connects one ends of the plurality of active pillars 100 in the third direction Z; the word line plug 201 is located at a side of the word line 200 adjacent to the bit line 300 in the third direction Z, and is in electrical contact with the word line 200; the bit line plug 301 is located on a side of the bit line 300 away from the active pillar 100 in the third direction Z and is in electrical contact with the bit line 300.

The active pillars 100 extend along the third direction Z and are aligned along the first direction X and the second direction Y, so that transistor structures aligned along the first direction X and the second direction Y are conveniently formed, and the transistor structures extend along the third direction Z, and in a plane where the first direction X and the second direction Y are located, the transistor structures may not occupy excessive areas, so as to be beneficial to improving the alignment density of the transistor structures and improving the space utilization rate of the semiconductor structure. The word line 200 covers sidewalls of the plurality of active pillars 100 in the first direction X, and the bit line 300 is connected to one end of the plurality of active pillars 100 in the second direction Y, so that the word line 200 and the bit line 300 can control the plurality of transistor structures in the first direction X and the second direction Y, respectively.

In some embodiments, the semiconductor structure may have an array region for forming an array-arranged transistor structure and a peripheral region for forming a circuit structure for controlling the transistor structure, the active pillars 100 are located in the array region of the semiconductor structure, the correspondingly configured transistor structures are located in the array region, and the orthographic projections of the word line plugs 201 and the orthographic projections of the bit line plugs 301 are located in the array region on the plane where the first direction X and the second direction Y are located, that is, the word line plugs 201 and the bit line plugs 301 are located in the array region without changing the division of the array region and the peripheral region in the conventional semiconductor structure, so that the space occupied by the word line plugs 201 and the bit line plugs 301 in the peripheral region can be avoided, which is beneficial for improving the integration density of the semiconductor structure.

The shapes of the active pillars 100, word lines 200, bit lines 300, word line plugs 201, and bit line plugs 301 shown in fig. 1 do not constitute limitations on the active pillars 100, word lines 200, bit lines 300, word line plugs 201, and bit line plugs 301. The shapes of the active columns, the word lines, the bit lines, the word line plugs and the bit line plugs can be designed according to actual conditions, for example, the shapes of the active columns can be cylinders, elliptic cylinders, quadrangular cylinders or polygonal cylinders; the word line can be in the shape of a cylinder, an elliptic cylinder, a quadrangular prism or a polygonal prism; the shape of the bit line can be a cylinder, an elliptic cylinder, a quadrangular prism or a polygonal prism; the word line plug shape can be a cylinder, an elliptic cylinder, a quadrangular prism or a polygonal prism; the bit line plug shape may be a cylinder, an elliptical cylinder, a quadrangular prism, or a polygonal prism.

FIG. 2 is a schematic diagram showing a partial cross-sectional structure of a first semiconductor structure along a direction parallel to a bit line according to one embodiment of the present disclosure; fig. 3 is a schematic view of a partial cross-sectional structure of a first semiconductor structure along a direction parallel to a word line according to an embodiment of the disclosure.

Referring to fig. 2 and 3, in some embodiments, the active pillar 100 may include a first doped region 101, a channel region 103, and a second doped region 102 sequentially arranged along a third direction Z. The word line 200 may cover the channel region 103 of the active pillar 100, and the bit line 300 may be in electrical contact with the first doped region 101 of the active pillar 100. In some embodiments, the bit lines may also be in electrical contact with the second doped regions of the active pillars, with respective bit line plugs located on sides of the bit lines in a third direction away from the second doped regions, and word line plugs located on sides of the word lines in the third direction closer to the second doped regions.

The first doped region 101 and the second doped region 102 may have P-type or N-type doped ions therein, for example, the N-type ions may be specifically phosphorus ions, arsenic ions or antimony ions; the P-type ion may be specifically a boron ion, an indium ion, or a gallium ion.

The material of the active pillars 100 may include semiconductor materials such as silicon, gallium arsenide, silicon carbide, or gallium nitride.

The material of the active pillars 100 may further include at least one of IGZO (Indium gallium zinc Oxide ), IWO (tungsten doped Indium Oxide, indium Tungsten Oxide), or ITO (Indium Tin Oxide).

The material of the word line 200 may include at least one of polysilicon, titanium nitride, titanium aluminide, tantalum nitride, nickel silicide, cobalt silicide, tantalum, aluminum, lanthanum, titanium, or tungsten.

In some embodiments, a gate dielectric layer may also be included between the word line and the sidewalls of the active pillars. The material of the gate dielectric layer may include silicon oxide, silicon nitride, metal oxide, metal oxynitride, metal silicide, high-K material, ferroelectric material, antiferroelectric material, or combinations thereof.

The sidewall of the word line 200 surrounding the active pillar 100 is illustrated in fig. 1 to facilitate increasing the contact area between the word line 200 and the channel region 103 and improving the control gate control capability of the word line 200. In some embodiments, the word line may also cover only a portion of the sidewall of one side of the active pillar in the second direction.

The material of bit line 300 may comprise a single metal, a metal compound, or an alloy. Wherein the single metal can be cobalt, nickel, molybdenum, titanium, tungsten, tantalum or platinum; the metal compound may be tungsten nitride, tantalum nitride or titanium nitride; the alloy may be an alloy material composed of at least 2 of cobalt, nickel, molybdenum, titanium, tungsten, tantalum, or platinum.

The material of the word line plug 201 may include a metal or metal alloy of one or more of copper, aluminum, nickel, tungsten, silver, gold, etc.

In some embodiments, the material of the word line plug 201 may be the same as or different from the material of the word line 200.

The material of the bit line plug 301 may include a metal or metal alloy of one or more of copper, aluminum, nickel, tungsten, silver, gold, etc.

In some embodiments, the material of bit line plug 301 may be the same as or different from the material of bit line 300.

FIG. 4 is a schematic diagram showing a partial cross-sectional structure of a second semiconductor structure along a direction parallel to a bit line according to one embodiment of the present disclosure; fig. 5 is a schematic view of a partial cross-sectional structure of a second semiconductor structure along a direction parallel to a word line according to an embodiment of the present disclosure.

Referring to fig. 4 and 5, in some embodiments, the semiconductor structure may further include: the capacitor 400, the capacitor 400 extends along the third direction Z, and the capacitor 400 is located at a side of the active pillar 100 away from the bit line 300 along the third direction Z and is in electrical contact with the active pillar 100. In this manner, the transistor structure and corresponding capacitor 400 may form a memory cell to which the word line 200 and bit line 300 may store or read. In addition, the capacitor 400 and the word line plug 201 are respectively located at two ends of the active column, and the capacitor 400 and the bit line plug 302 are respectively located at two ends of the active column, so that the space utilization rate of the semiconductor structure is improved, and meanwhile, the problems of parasitic capacitance or electric leakage and the like caused by too close distance between the word line plug 201 or the bit line plug 301 and the capacitor 400 can be avoided, and the stability of the semiconductor structure is improved.

In some embodiments, the capacitor may include an upper plate, a dielectric layer, and a lower plate stacked in sequence, wherein the lower plate extends in a third direction, and one end is electrically connected to an end of the active pillar remote from the bit line; the dielectric layer covers the side surface of the lower polar plate and the surface of the lower polar plate far away from the active column along the third direction; the upper polar plate covers the surface of the dielectric layer far away from the upper polar plate.

In some embodiments, the bottom plate may be in direct electrical contact with the active pillars to electrically connect the capacitor with the active pillars. In some embodiments, the capacitor may further include a contact structure, where the contact structure is located between the lower plate and the active column, and the capacitor is electrically connected to the active column through the contact structure, so as to reduce a contact resistance between the lower plate and the active column, and improve signal transmission efficiency.

The material of the upper and lower plates may include at least one of platinum nickel, titanium, tantalum, cobalt, polysilicon, copper, tungsten, tantalum nitride, titanium nitride, or ruthenium.

The material of the dielectric layer may include silicon oxide, tantalum oxide, hafnium oxide, zirconium oxide, niobium oxide, titanium oxide, barium oxide, strontium oxide, yttrium oxide, lanthanum oxide, praseodymium oxide or barium strontium titanate.

The material of the contact structure may include copper, silver, gold, tungsten, tin, lead, or the like.

In some embodiments, the semiconductor structure may further include: and a driving transistor located at a side of the word line plug away from the word line in the third direction and located at a side of the bit line plug away from the bit line in the third direction, wherein one of a gate, a source or a drain of the driving transistor is electrically connected with the word line plug or the bit line plug. Therefore, the driving transistor and the capacitor can be respectively positioned at two ends of the active column, the storage unit and the driving transistor are arranged in the third direction, and the driving transistor can occupy no area on the plane where the first direction and the second direction are positioned, so that the space utilization rate of the semiconductor structure is improved.

In the drawings provided in this embodiment, an included angle between the first direction X and the second direction Y is 90 °, and an included angle between a plane in which the first direction X and the second direction Y are located and the third direction Z is 90 °. In some embodiments, the included angle between the first direction and the second direction may be 30 °, 45 ° or 60 °, and the included angle between the plane in which the first direction and the second direction are located and the third direction may be 30 °, 45 ° or 60 °, which does not constitute a limitation of the included angles among the first direction, the second direction and the third direction.

Fig. 6 is a schematic diagram of a partial cross-sectional structure of a third semiconductor structure along a direction parallel to a word line according to an embodiment of the present disclosure.

Referring to fig. 6, in some embodiments, the word line plug 201 may include a first portion 221 and a second portion 211 connected in sequence, the first portion 221 being located between adjacent active pillars 100 and being in electrical contact with the word line 200, the second portion 211 being located at a side of the first portion 221 away from the word line 200 in a third direction Z, the first portion 221 having a smaller size than the second portion 211 in the first direction X. In this way, the end surface area of the word line plug 201 far away from the word line 200 along the third direction Z is larger than the end surface area of the word line plug 201 near the word line 200 along the third direction Z, so as to facilitate improving the contact window for electrically connecting the word line plug 201 with other devices, avoiding the problem of disconnection of the word line plug, and improving the stability of the semiconductor structure.

In some embodiments, the spacing between the first portion 221 and the adjacent active pillars 100 in the first direction X is 5nm to 15nm in size, which may be, for example, 5nm, 5.4nm, 6nm, 6.6nm, 7nm, 7.5nm, 8nm, 9.3nm, 10.2nm, 11.6nm, 12.8nm, 13.7nm, 14.5nm, 15nm, or the like. Since the first portion 221 is located between the first doped regions 101 of adjacent active pillars 100, in order to avoid leakage between the first portion 221 and the first doped regions 101 of the active pillars 100, the width of the first portion 221 needs to be within a proper range.

For example, the width of the first portion 221 may be 20nm to 30nm, such as 20nm, 22nm, 25nm, 27nm, 29nm, or 30nm, in the first direction X.

The material of the first portion 221 and the material of the second portion 211 may each comprise a metal or metal alloy of one or more of copper, aluminum, nickel, tungsten, silver, gold, etc.

In some embodiments, the material of the first portion 221 may be different from the material of the second portion 211, so that the material with lower contact resistance with the word line 200 may be selected to make the first portion 221, and the material with higher conductivity may be selected to make the second portion 211, so as to reduce the contact resistance between the word line plug 201 and the word line 200 and improve the signal transmission efficiency of the word line plug 201.

In some embodiments, the material of the first portion 221 may also be the same as the material of the second portion 211.

Fig. 7 is a schematic view of a partial cross-sectional structure of a fourth semiconductor structure along a direction parallel to a word line according to an embodiment of the present disclosure.

Referring to fig. 7, in some embodiments, the semiconductor structure may further include: the protection layer 500, in the second direction Y, the protection layer 500 covers two sides of the plurality of active pillars 100 opposite in the first direction X, and covers two sides of the bit line 300 opposite in the first direction X, and the word line plug 201 is located between the protection layers 500 of the adjacent two active pillar 100 sides. Thus, the problem of short circuit between the word line plug 201 and the bit line 300 can be avoided, which is beneficial to improving the stability of the semiconductor structure.

Fig. 8 is a schematic diagram of a partial cross-sectional structure of a fifth semiconductor structure along a direction parallel to a word line according to an embodiment of the disclosure.

Referring to fig. 8, in some embodiments, the protective layer 500 may further include: a first protection layer 501, the first protection layer 501 covering two sides of the bit line 300 opposite in the first direction X, and covering two sides of an end of the active pillar 100 near the bit line 300 opposite in the first direction X; a second protection layer 502, wherein the second protection layer 502 covers the surface of the first protection layer 501 far away from the bit line 300, and covers the surface of the first protection layer 501 far away from the active pillars 100, and the word line plug 201 is located between the second protection layers 502 on the sides of two adjacent active pillars 100; wherein the material of the first protection layer 501 is different from the material of the second protection layer 502. In this way, when the word line plug 201 is formed between the adjacent bit lines 300 and the active pillars 100, the second protection layer 502 can be used as an etching stop layer, so that the side surface of the bit line 300 or the side surface of the active pillar 100 close to one end of the bit line is prevented from being damaged by etching in the etching process, and the subsequently formed word line plug 201 cannot be in contact with the active pillar 100 or the bit line 300, so that the problem of electric leakage or short circuit is avoided, and the stability of the semiconductor structure is improved.

The materials of the first protective layer 501 and the second protective layer 502 may each include silicon oxide, silicon nitride, silicon oxynitride, or the like.

Fig. 9 is a schematic diagram of a partial cross-sectional structure of a sixth semiconductor structure along a direction parallel to a word line according to an embodiment of the disclosure.

In some embodiments, the dimension of the bit line plug 301 may be greater than the dimension of the bit line 300 in a direction perpendicular to the second direction Y. The bit line plugs 301, the bit lines 300 and the active pillars 100 are arranged along the third direction Z, so that the size of the bit line plugs 301 can be unaffected by the size of the active pillars 100 or the bit lines 300, and the size of the bit line plugs 301 is larger than that of the bit lines 300 without affecting the word line plugs 201, which is beneficial for the electrical connection of the bit line plugs 301 with other devices, and improves the contact window between the bit line plugs 301 and other structures, thereby improving the signal transmission efficiency.

For example, the bit line plug 301 may have a size of 20nm to 30nm, such as 20nm, 22nm, 25nm, 27nm, 29nm, or 30nm, in a direction perpendicular to the second direction Y.

The dimension of the bit line plug 301 in the extension direction along the bit line 300, i.e., the second direction Y, may not be affected by the dimension of the bit line 300, but the dimension of the bit line plug 301 still needs to be within a proper range to avoid the influence of the oversized dimension of the bit line plug 301 on other device structures. For example, in the second direction Y, the bit line plug 301 may have a size of 60nm to 65nm, specifically 60nm, 61nm, 62nm, 62.5nm, 63nm, 64nm, or 65nm.

In some embodiments, the dimension of the bit line plug may be less than or equal to the dimension of the bit line along a direction perpendicular to the second direction.

In fig. 1, on a plane along the first direction X and the second direction Y, bit line plugs 301 are aligned along the first direction X, and word line plugs 201 are offset along the second direction Y, for example.

In some embodiments, adjacent bit line plugs 301 may also be arranged offset along the first direction X.

In some embodiments, adjacent word line plugs 201 may also be aligned in the second direction Y.

FIG. 10 is a schematic diagram of a seventh semiconductor structure according to an embodiment of the present disclosure along a partial cross-sectional structure parallel to a word line direction; FIG. 11 is a partial top view of the semiconductor structure of FIG. 10 along a third direction; fig. 12-18 are partial top views of various semiconductor structures along a third direction provided in an embodiment of the present disclosure.

Referring to fig. 10 and 11 in combination, in some embodiments, the semiconductor structure may further include: dummy bit line 202, dummy bit line 202 extends along second direction Y, dummy bit line 202 is located at the outermost side of plurality of bit lines 300 arranged along first direction X, and the orthographic projection of word line plug 201 overlaps with the orthographic projection of dummy bit line 202 on the plane along first direction X and second direction Y. Thus, the size of the word line plug 201 is not affected by the distance between the adjacent active pillars 100, which is beneficial to increasing the size of the word line plug 201 to reduce the contact resistance of the word line plug 201, and the bit line plug 301 is distant from the word line plug 201 to avoid the problem of parasitic capacitance or short circuit between the word line plug 201 and the bit line plug 301.

It should be noted that, the dummy bit line 202 and the bit line 300 are prepared by the same process, but in this embodiment, the dummy bit line 202 is not electrically connected to other device structures, and only a formation region is provided for the word line plug 201.

In some embodiments, in the first direction X, the width of the dummy bit line 202 is a first width W1, the width of the bit line 300 is a second width W2, and the first width W1 is greater than the second width W2 and less than 2 times the second width W2. In this way, on the plane along the first direction X and the second direction Y, the word line plug 201 is still maintained in the array region and may not occupy a larger area, so as to avoid causing space burden of the semiconductor structure, which is beneficial to improving the integration density of the semiconductor structure.

In some embodiments, the width W1 of the dummy bit line 202 may be 50nm to 100nm, such as 50nm, 60nm, 70nm, 80nm, 90nm, or 100nm, in the first direction X.

Referring to fig. 11 and 12 in combination, in some embodiments, where the semiconductor structure includes dummy bit lines 202, word line plugs 201 are located at ends of the word lines 200, and the word line plugs 201 of the plurality of word lines 200 may be aligned in the second direction Y, wherein the bit line plugs 301 may be aligned in the first direction X as in fig. 12, such that the bit line plugs 301 may be disposed at ends of the bit lines 300; or the bit line plugs 301 may be arranged offset in the first direction X as shown in fig. 11. In fig. 12, on the plane along the first direction X and the second direction Y, the areas occupied by the word line plugs 201 and the bit line plugs 301 are located at the edge positions of the array region, so that the area of the array region is saved, and the manufacturing of the word line plugs 201 and the bit line plugs 301 is facilitated. In fig. 11, the bit line plugs 301 are arranged in a staggered manner, compared to the bit line plugs 301 in fig. 12, the spacing between adjacent bit line plugs 301 is larger, so as to avoid the problem of leakage or parasitic capacitance between adjacent bit line plugs 301.

Referring to fig. 13, when the dummy bit line 202 is not provided in the semiconductor structure, the word line plug 201 may be provided in the array region and aligned in the second direction Y. Thus, the dummy bit line 202 may not be provided, the space of the array region may be further increased, and the word line plug 201 and the bit line plug 301 may be more flexibly arranged in the array region without occupying more area.

Referring to fig. 14, when the dummy bit line 202 is not provided in the semiconductor structure, the word line plug 201 may be provided in the array region and staggered in the second direction Y. This is advantageous in that the word line plugs 201 are prevented from being affected by each other, and parasitic capacitance is further reduced.

Referring to fig. 15, when the word line plugs 201 are aligned in the second direction Y, or, referring to fig. 16, when the word line plugs 201 are aligned in the second direction Y, there may be a part of the bit line plugs 301 aligned and another part of the bit line plugs 301 misaligned with respect to the bit line plugs 301. Thus, the bit line plug 301 makes room for the word line plug 201, which is advantageous for increasing the size of the word line plug 201, reducing the contact resistance of the word line plug 201, and avoiding the problem of leakage or parasitic capacitance between the word line plug 201 and the bit line plug 301. Similarly, referring to fig. 17, the word line plugs 201 may be partially aligned, and the other portion may be offset, so that the distance between the word line plugs 201 and the bit line plugs 301 is larger, and the respective dimensions may be designed larger, so as to be beneficial to reducing the contact resistance and delay of the word line plugs 201 and the bit line plugs 301.

In some embodiments, referring to fig. 18 and 6 in combination, when the word line plug 201 includes the first portion 221 and the second portion 211, the second portion 211 may also have a size larger than that of the bit line 300 in the first direction X, so as to further increase the top surface area of the word line plug 201 and improve the electrical connection stability of the word line plug 201 with other device structures. In the design process of an actual semiconductor structure, the word line plug 201 may be designed smaller as shown in fig. 12 to 17 in order to meet the design requirements of a miniaturized semiconductor structure. Thus, the distance between the word line plugs 201 increases, and the parasitic capacitance decreases, thereby reducing the risk of leakage between the word line plugs 201 and the bit line plugs 301, and reducing the delay.

In some embodiments, the word line plugs may be offset in the second direction, and each 2, 4 or 5 aligned word line plugs may be used as one word line plug group, and adjacent word line plug groups may be offset. Similarly, the bit line plugs may be arranged in a staggered manner along the first direction, and each 2, 3 or 6 bit line plugs aligned with each other may be used as one bit line plug group, and adjacent bit line plug groups are arranged in a staggered manner.

It will be appreciated that the arrangements of word line plugs or bit line plugs provided in the above embodiments may be combined arbitrarily without conflict to obtain a new embodiment. In the design process of the actual semiconductor structure, the arrangement and the size of the word line plug 201 and the bit line plug 301 can be comprehensively adjusted in combination with the above embodiments, so that the distance between the word line plug and the bit line plug is as large as possible, and the problem of leakage or parasitic capacitance between the word line plug and the bit line plug is avoided.

In the semiconductor structure provided in the embodiment of the present disclosure, the active pillars 100 extend along the third direction Z and are arranged along the first direction X and the second direction Y, so that transistor structures arranged along the first direction X and the second direction Y are formed conveniently, and the transistor structures extend along the third direction Z. The word line 200 covers sidewalls of the plurality of active pillars 100 in the first direction X, and the bit line 300 is connected to one end of the plurality of active pillars 100 in the second direction Y, so that the word line 200 and the bit line 300 can control the plurality of transistor structures in the first direction X and the second direction Y, respectively. The semiconductor structure may have an array region for forming transistor structures arranged in an array, and a peripheral region for forming a circuit structure for controlling the transistor structures, the active pillars 100 are located in the array region of the semiconductor structure, the transistor structures correspondingly formed are located in the array region, and the orthographic projections of the word line plugs 201 and the orthographic projections of the bit line plugs 301 are located in the array region on the plane where the first direction X and the second direction Y are located, that is, the word line plugs 201 and the bit line plugs 301 are located in the array region without changing the division of the array region and the peripheral region in the conventional semiconductor structure, so that the space occupied by the word line plugs 201 and the bit line plugs 301 in the peripheral region can be avoided, which is beneficial for improving the integration density of the semiconductor structure.

Another embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, which can be used to form the semiconductor structure to increase the integration density of the semiconductor structure. It should be noted that, in the same or corresponding parts as those of the above embodiments, reference may be made to the corresponding descriptions of the above embodiments, and detailed descriptions thereof will be omitted. The method for manufacturing the semiconductor structure according to the present embodiment will be described in detail below with reference to the accompanying drawings.

Fig. 19 to 27 are schematic structural diagrams corresponding to respective steps of a method for manufacturing a semiconductor structure according to another embodiment of the present disclosure. Fig. 20 to 27 are schematic cross-sectional structures along AA1 and BB1 directions of fig. 19.

Referring to fig. 19 to 27, the method of manufacturing a semiconductor structure includes:

referring to fig. 19, a substrate 110 is provided, the substrate 110 including an array region for forming transistor structures arranged in an array, and a peripheral region for forming circuit structures controlling the transistor structures; a plurality of active pillars 100 are formed on the array region of the substrate 110, the active pillars 100 being aligned in the first direction X and the second direction Y, the active pillars 100 extending in the third direction Z, the active pillars 100 including a first doped region 101, a channel region 103, and a second doped region 102 sequentially aligned in the third direction Z.

Note that, in fig. 19, only the array region of the substrate 110 is shown, and other structures may be provided on the peripheral region of the substrate 110, and the structure of the peripheral region is not limited in this embodiment.

In some embodiments, the substrate 110 may be a silicon substrate, a silicon germanium substrate, a gallium arsenide substrate, a silicon carbide substrate, a gallium nitride substrate, or the like.

The material of the active column 100 may also be at least one of IGZO, IWO, or ITO.

In some embodiments, providing the substrate 110 and forming the active pillars 100 may include: providing an initial substrate 120; a plurality of first trenches 111 extending in the first direction X and a plurality of second trenches 112 extending in the second direction Y are formed in the initial substrate 120, the initial substrate 120 remaining between the first trenches 111 and the second trenches 112 serves as the active column 100, and the initial substrate 120 remaining at the bottoms of the first trenches 111 and the second trenches 112 serves as the substrate 110. As such, the material of the substrate 110 may be the same as that of the active pillars 100.

In some embodiments, providing the substrate and the active pillars may further comprise: a semiconductor layer is formed on a substrate, and an active pillar is formed by patterning the semiconductor layer, so that a material of the active pillar may be different from a material of the substrate.

In some embodiments, the corners of the active pillars may also be chamfered after the active pillars are formed to avoid problems of tip discharge at the corners of the active pillars.

After the active pillar 100 is formed, the first doped region 101 and the second doped region 102 may be subjected to a doping process so that P-type or N-type doped ions, for example, N-type ions may be specifically phosphorus ions, arsenic ions or antimony ions, are included in the first doped region 101 and the second doped region 102; the P-type ion may be specifically a boron ion, an indium ion, or a gallium ion.

In some embodiments, the depth of the first trench 111 within the initial substrate 120 may be less than the depth of the second trench 112 within the initial substrate 120. In some embodiments, the depth of the first trench in the initial substrate may also be greater than or equal to the depth of the second trench in the initial substrate.

Referring to fig. 20, word lines 200 are formed, the word lines 200 extending in a first direction X, and in the first direction X, the word lines 200 cover sidewalls of channel regions 103 of a plurality of active pillars 100, and insulating layers 130 are filled between adjacent word lines 200 and between adjacent active pillars 100.

In some embodiments, forming the word line may include: forming an insulating layer, wherein the insulating layer fills the first groove and the second groove; patterning the insulating layer to form a plurality of word line trenches extending in a first direction, the word line trenches exposing channel region sidewalls of the plurality of active pillars; forming a gate dielectric layer, wherein the gate dielectric layer covers the surface of the channel region of the active column; filling the word line trench to form a word line; an insulating layer is reformed on top of the word line.

The material forming the insulating layer may include silicon oxide, silicon nitride, silicon oxynitride, or the like.

The material forming the gate dielectric layer may include silicon oxide, silicon nitride, metal oxide, metal oxynitride, metal silicide, high-K material, ferroelectric material, antiferroelectric material, or combinations thereof.

The material forming the word line 200 may include at least one of polysilicon, titanium nitride, titanium aluminide, tantalum nitride, nickel silicide, cobalt silicide, tantalum, aluminum, lanthanum, titanium, or tungsten.

Referring to fig. 21, a bit line 300 is formed, the bit line 300 extending in a second direction Y in which the bit line Y connects one ends of the plurality of active pillars 100 in a third direction Z.

Referring to fig. 20, the end of the active pillar 100 away from the substrate 110 in the third direction Z is the first end (i.e., the end of the first doped region 101 away from the channel region 103) with the end of the active pillar 100 near the substrate 110 in the third direction Z being the second end (i.e., the end of the second doped region 102 away from the channel region 103).

In some embodiments, after forming the active pillars 100 and word lines 200, prior to forming the bit lines 300, comprising: a planarization process is performed to remove the substrate 110 to expose the end surface of the first end of the active pillar 100, and then a bit line 300 is formed at the first end of the active pillar 100, i.e., the bit line 300 is located at the end surface of the second doped region 102. The planarization process may remove the substrate 110 at the first end of the active pillars 100, and may remove the insulating layer (shallow trench isolation structure) between the bottoms of the active pillars 100, so that the height of the bit lines 300 may be reduced during subsequent formation to avoid air gaps in the bit lines 300.

In some embodiments, the planarization process may employ a chemical mechanical polishing process.

In some embodiments, forming the bit line 300 may include: removing a portion of the thickness of the active pillars 100 (i.e., a portion of the second doped region); forming a metal layer on an end surface of the first end of the active column 100; a heat treatment process is performed to react a portion of the active pillars 100 with the metal layer to form a metal compound layer, which serves as the bit lines 300. The contact resistance of the bit line 300 and the active pillar 100 may be reduced through a heat treatment process.

In some embodiments, the heat treatment process includes a rapid thermal annealing process.

In some embodiments, the material forming the metal layer may be a single metal, a metal compound, or an alloy. Wherein the single metal can be cobalt, nickel, molybdenum, titanium, tungsten, tantalum or platinum; the metal compound may be tungsten nitride, tantalum nitride or titanium nitride; the alloy may be an alloy material composed of at least 2 of cobalt, nickel, molybdenum, titanium, tungsten, tantalum, or platinum.

In some embodiments, the metal layer may also be directly used as the bit line.

Referring to fig. 22, a word line plug 201 and a bit line plug 301 are formed, the word line plug 201 being located on a side of the word line 200 in the third direction Z close to the bit line 300, the bit line plug 301 being located on a side of the bit line 300 in the third direction Z away from the active pillar 100, i.e. both the word line plug 201 and the bit line plug 301 are close to the first end of the active pillar 100.

In some embodiments, forming word line plug 201 and bit line plug 301 includes: forming a filling layer 140, wherein the filling layer 140 is positioned on the surface of the bit line 300 far away from the active column 100 and the surface of the insulating layer 130; patterning the filling layer 140 and the insulating layer 130 to form a word line plug hole 203 and a bit line plug hole 303, wherein the orthographic projection of the word line plug hole 203 overlaps with the orthographic projection of the word line 200 on a plane where the first direction X and the second direction Y are located, the orthographic projection of the bit line plug hole 303 overlaps with the bit line 300, the word line plug hole 203 exposes a surface of the word line 200 near the first end of the active pillar 100 in the third direction Z, and the bit line plug hole 303 exposes a surface of the bit line 300 near the first end of the active pillar 100 in the third direction Z; word line plug holes 203 are filled to form word line plugs 201, and bit line plug holes 303 are filled to form bit line plugs 301.

The material forming the filling layer 140 may include silicon oxide, silicon nitride, silicon oxynitride, or the like.

The material forming the word line plug 201 may include a metal or metal alloy of one or more of copper, aluminum, nickel, tungsten, silver, gold, and the like.

The material forming the bit line plug 301 may include a metal or metal alloy of one or more of copper, aluminum, nickel, tungsten, silver, gold, and the like.

In some embodiments, the dimension of the space between the word line plug 201 and the adjacent active pillars 100 in the first direction X may be a dimension of the space may be 5nm to 15nm, for example, may be 5nm, 5.4nm, 6nm, 6.6nm, 7nm, 7.5nm, 8nm, 9.3nm, 10.2nm, 11.6nm, 12.8nm, 13.7nm, 14.5nm, 15nm, or the like.

In some embodiments, referring to fig. 23, after forming the bit line 300, before forming the word line plug 201, it may further include: removing portions of the insulating layer 130 of the two sides of the bit line 300 opposite in the first direction X and portions of the insulating layer 130 of the two sides of the active column 100 opposite in the first direction X; forming a first protection layer 501, the first protection layer 501 covering both sides of the bit line 300 opposite in the first direction X and covering both sides of the active column 100 opposite in the first direction X; a second protective layer 502 is formed, the second protective layer 502 covering a surface of the first protective layer 501 remote from the bit line 300 and covering a surface of the first protective layer 501 remote from the active pillars 100, the material of the second protective layer 502 being different from the material of the first protective layer 501. Forming the word line plug 201 includes: a word line plug 201 is formed between the second protective layers 502 on the sides of adjacent active pillars 100. In this way, when forming the word line plug hole, the second protection layer 502 can be used as an etching stop layer, so that the side surface of the bit line 300 or the side surface of the active column 100 close to one end of the bit line is prevented from being damaged by etching in the etching process, and the formed word line plug 201 cannot be contacted with the active column 100 or the bit line 300, so that the problem of electric leakage or short circuit is avoided, and the stability of the semiconductor structure is improved.

The material forming the first protective layer 501 and the material forming the second protective layer 502 may each include silicon oxide, silicon nitride, silicon oxynitride, or the like.

In some embodiments, referring to fig. 24, forming the word line plug holes 203 may include: forming a first word line plug hole 213, the first word line plug hole 213 being located at a side of the bit line 300 away from the active pillars 100 in the third direction Z, the first word line plug hole 213 may have a size equal to or greater than a pitch between adjacent active pillars 100 in the first direction X; forming a second word line plug hole 223, the second word line plug hole 223 being in communication with the first word line plug hole 213, the second word line plug hole 223 being located between adjacent active pillars 100, the second word line plug hole 223 having a smaller size than the first word line plug hole 213 in the first direction X; the first word line plug hole 213 and the second word line plug hole 223 are filled to form the word line plug 201. As such, the word line plug 201 may include a first portion 221 and a second portion 211 connected in sequence, the first portion 221 being located between adjacent active pillars 100 and being in electrical contact with the word line 200, the second portion 211 being located at a side of the first portion 221 away from the word line 200 in the third direction Z, the first portion 221 having a smaller size than the second portion 211 in the first direction X. The end surface area of the word line plug 201 far away from the word line 200 along the third direction Z is larger than the end surface area of the word line plug 201 near the word line 200 along the third direction Z, which is beneficial to improving the contact window for electrically connecting the word line plug 201 with other devices, avoiding the problem of disconnection of the word line plug 201 and improving the stability of the semiconductor structure.

In some embodiments, the dimension of the spacing between the first portion 221 and the adjacent active pillars 100 in the first direction X may be 5nm to 15nm, for example, may be 5nm, 5.4nm, 6nm, 6.6nm, 7nm, 7.5nm, 8nm, 9.3nm, 10.2nm, 11.6nm, 12.8nm, 13.7nm, 14.5nm, 15nm, or the like.

Referring to fig. 25, in some embodiments, after forming the word line plug 201 and the bit line plug 301, it may further include: providing a second wafer 150, wherein a plurality of driving transistors (not shown in the figure) are arranged in the second wafer 150, and the surface of the second wafer 150 is provided with a bonding pad 151, wherein the bonding pad 151 is electrically connected with one of a grid electrode, a source electrode or a drain electrode of the driving transistors; placing the second wafer 150 opposite the word line plug 201 and the bit line plug 301 so that the word line plug 201 or the bit line plug 301 is in contact with the pad 151; a bonding process is performed to electrically contact the word line plug 201 with the pad 151 and to electrically contact the bit line plug 301 with the pad 151.

The material of the bonding pad 151 may include copper, silver, gold, tungsten, tin, lead, or the like. In some embodiments, the material of the bonding pad 151 may be the same as the material of the word line plug 201 and/or the bit line plug 301 to facilitate the bonding process, to facilitate electrical contact of the word line plug 201 with the bonding pad 151, and/or to facilitate electrical contact of the bit line plug 301 with the bonding pad 151.

In some embodiments, the active pillars 100 may also have a side end surface that is remote from the bit line 300 in the third direction Z: forming a contact structure 170, the contact structure 170 being located at an end face of the second end of the active pillar 100 (i.e., an end face of the first doped region 101); providing a first wafer 160, wherein a plurality of capacitors 400 are arranged in the first wafer 160, and one ends of the capacitors 400 are exposed on the surface of the first wafer 160; placing the first wafer 160 opposite the contact structure 170 such that the capacitor 400 is in contact with the contact structure 170; a bonding process is performed to electrically contact the capacitor 400 with the contact structure 170.

In this way, the active pillars 100 and the corresponding capacitors 400 form memory cells, and the driving transistors can control the conduction of the word lines 200 and the bit lines 300 through the word line plugs 201 and the bit line plugs 301 to read or store the memory cells. The memory cells and the driving transistors are arranged in the third direction Z, so that the memory cells and the corresponding driving transistors can occupy no excessive area in the plane where the first direction X and the second direction Y are located, and the space utilization rate of the semiconductor structure is improved.

The material forming the contact structure 170 may include copper, silver, gold, tungsten, tin, lead, or the like.

Referring to fig. 26, in some embodiments, a bit line 300 may also be formed at the second end of the active pillar 100, i.e., the bit line 300 is located at the end face of the first doped region 101.

In some embodiments, forming the bit line 300 may include: removing a portion of the thickness of the active column 101 (i.e., a portion of the first doped region 101); forming a metal layer on an end surface of the second end of the active column 100; a heat treatment process is performed to react a portion of the active pillars 100 with the metal layer to form a metal compound layer, which serves as the bit lines 300.

The material of the metal layer can be single metal, metal compound or alloy. Wherein the single metal can be cobalt, nickel, molybdenum, titanium, tungsten, tantalum or platinum; the metal compound may be tungsten nitride, tantalum nitride or titanium nitride; the alloy may be an alloy material composed of at least 2 of cobalt, nickel, molybdenum, titanium, tungsten, tantalum, or platinum.

In some embodiments, the metal layer may also be directly used as the bit line.

In some embodiments, forming the word line plug 201 and the bit line plug 301 may include: forming a filling layer 140, wherein the filling layer 140 is positioned on the surface of the bit line 300 far away from the active column 100 and the surface of the insulating layer 130; patterning the filling layer 140 and the insulating layer 130 to form a word line plug hole 203 and a bit line plug hole 303, wherein the orthographic projection of the word line plug hole 203 overlaps with the orthographic projection of the word line 200 on a plane where the first direction X and the second direction Y are located, the orthographic projection of the bit line plug hole 303 overlaps with the bit line 300, the word line plug hole 203 exposes a surface of the word line 200 near the first end of the active pillar 100 in the third direction Z, and the bit line plug hole 303 exposes a surface of the bit line 300 near the first end of the active pillar 100 in the third direction Z; the wordline plug holes are filled to form wordline plugs 201 and the bitline plug holes are filled to form bitline plugs 301.

Referring to fig. 27, in some embodiments, after forming the word line plug 201 and the bit line plug 301, it may further include: performing planarization to remove the substrate 110 to expose the end face of the first end of the active column 100; forming a contact structure 170 at an end face of the first end of the active pillar 100; providing a first wafer 160, wherein a plurality of capacitors 400 are arranged in the first wafer 160, and one ends of the capacitors 400 are exposed on the surface of the first wafer 160; placing the first wafer 160 opposite the contact structure 170 such that the capacitor 400 is in contact with the contact structure 170; a bonding process is performed to electrically contact the capacitor 400 with the contact structure 170.

In some embodiments, it may further include: providing a second wafer 150, wherein a plurality of driving transistors are arranged in the second wafer 150, a bonding pad 151 is arranged on the surface of the second wafer 150, and the bonding pad 151 is electrically connected with one of a grid electrode, a source electrode or a drain electrode of the driving transistors; placing the base second wafer 150 opposite the word line plug 201 and the bit line plug 301 so that the word line plug 201 or the bit line plug 301 is in contact with the pad 151; a bonding process is performed to electrically contact the word line plug 201 with the pad 151 and to electrically contact the bit line plug 301 with the pad 151. In this way, the active pillars 100 and the corresponding capacitors 400 form memory cells, and the driving transistors can control the conduction of the word lines 200 and the bit lines 300 through the word line plugs 201 and the bit line plugs 301 to read or store the memory cells. The memory cells and the driving transistors are arranged in the third direction Z, so that the memory cells and the corresponding driving transistors can occupy no excessive area in the plane where the first direction X and the second direction Y are located, and the space utilization rate of the semiconductor structure is improved.

According to the method for manufacturing the semiconductor structure, the formed active column 100 extends along the third direction Z and is arranged along the first direction X and the second direction Y, so that the formed transistor structure is arranged along the first direction X and the second direction Y conveniently, and extends along the third direction Z, and the transistor structure does not occupy too much area on the plane where the first direction X and the second direction Y are located, so that the arrangement density of the transistor structure is improved, and the space utilization rate of the semiconductor structure is improved. The word line 200 is formed to cover sidewalls of the plurality of active pillars 100 in the first direction X, and the bit line 300 is formed to connect one ends of the plurality of active pillars 100 in the second direction Y, so that the word line 200 and the bit line 300 can control the plurality of transistor structures in the first direction X and the second direction Y, respectively. The active pillars 100 are located in the array region of the semiconductor structure, and the correspondingly configured transistor structures are located in the array region, and the orthographic projections of the word line plugs 201 and the orthographic projections of the bit line plugs 301 are located in the array region on the plane where the first direction X and the second direction Y are located, that is, the word line plugs 201 and the bit line plugs 301 are located in the array region without changing the division of the array region and the peripheral region in the conventional semiconductor structure, so that the space occupied by the word line plugs 201 and the bit line plugs 301 in the peripheral region can be avoided, and the integration density of the semiconductor structure can be improved.

It will be understood by those of ordinary skill in the art that the foregoing embodiments are specific examples of implementing the disclosure, and that various changes in form and details may be made therein without departing from the spirit and scope of the disclosure.

Claims

1. A semiconductor structure having an array region, comprising:

a plurality of active pillars located in the array region, the active pillars being arranged in a first direction and a second direction, the active pillars extending in a third direction;

a word line extending along the first direction, the word line covering sidewalls of the plurality of active pillars in the first direction;

a bit line extending in the second direction, the bit line connecting one ends of the plurality of active pillars in the third direction in the second direction;

a word line plug located at a side of the word line adjacent to the bit line in the third direction and electrically contacting the word line;

a bit line plug located at a side of the bit line away from the active pillar in the third direction and in electrical contact with the bit line;

and on the plane where the first direction and the second direction are located, the orthographic projection of the bit line plug and the orthographic projection of the word line plug are both positioned in the array region.

2. The semiconductor structure of claim 1, wherein adjacent ones of the bit line plugs are arranged offset in the first direction and/or adjacent ones of the word line plugs are arranged offset in the second direction.

3. The semiconductor structure of claim 1, wherein adjacent ones of the bit line plugs are aligned in the first direction and/or adjacent ones of the word line plugs are aligned in the second direction.

4. The semiconductor structure of claim 1, wherein the word line plug comprises first and second portions connected in sequence, the first portion being located between adjacent ones of the active pillars and in electrical contact with the word line, the second portion being located on a side of the first portion remote from the word line in the third direction, a dimension of the first portion being smaller than a dimension of the second portion in the first direction.

5. The semiconductor structure of claim 1, further comprising:

and a protective layer covering two sides of the plurality of active pillars opposite along the first direction in the second direction, and covering two sides of the bit line opposite along the first direction, wherein the word line plug is positioned between the protective layers of two adjacent active pillar sides.

6. The semiconductor structure of claim 5, wherein the protective layer comprises:

a first protection layer covering both sides of the bit line opposite in the first direction and covering both sides of the active pillar opposite in the first direction;

the second protection layer covers the surface of the first protection layer far away from the bit line and the surface of the first protection layer far away from the active column, and the word line plug is positioned between the second protection layers on the side surfaces of two adjacent active columns;

wherein the material of the first protective layer is different from the material of the second protective layer.

7. The semiconductor structure of claim 1, further comprising: and the dummy bit line extends along the second direction, is positioned at the outermost side of the bit lines arranged along the first direction, and the orthographic projection of the word line plug overlaps with the orthographic projection of the dummy bit line on the plane along the first direction and the second direction.

8. The semiconductor structure of claim 7, wherein in the first direction, the width of the dummy bit line is a first width and the width of the bit line is a second width, the first width being greater than the second width and less than 2 times the second width.

9. The semiconductor structure of claim 1, wherein a dimension of the bit line plug is greater than a dimension of the bit line in a direction perpendicular to the second direction.

10. The semiconductor structure of claim 1, further comprising: and the capacitor extends along the third direction, is positioned on one side of the active column away from the bit line along the third direction, and is electrically contacted with the active column.