WO2022077950A1 - 埋入式位线及其形成方法 - Google Patents

埋入式位线及其形成方法 Download PDF

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Publication number
WO2022077950A1
WO2022077950A1 PCT/CN2021/101424 CN2021101424W WO2022077950A1 WO 2022077950 A1 WO2022077950 A1 WO 2022077950A1 CN 2021101424 W CN2021101424 W CN 2021101424W WO 2022077950 A1 WO2022077950 A1 WO 2022077950A1
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WIPO (PCT)
Prior art keywords
bit line
layer
barrier layer
trench
buried
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PCT/CN2021/101424
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English (en)
French (fr)
Inventor
吴公一
陆勇
徐朋辉
Original Assignee
长鑫存储技术有限公司
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Priority to US17/460,443 priority Critical patent/US11877440B2/en
Publication of WO2022077950A1 publication Critical patent/WO2022077950A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines

Definitions

  • the present invention relates to the technical field of semiconductor devices, in particular to a buried bit line and a method for forming the same.
  • a semiconductor memory includes a plurality of bit lines, which are usually formed on a substrate and arranged in parallel along a predetermined direction. With the continuous reduction of the size of semiconductor devices, the size of the spacing between adjacent bit lines is also gradually reduced, so that a large parasitic capacitance is easily generated between adjacent bit lines, thereby causing a serious delay problem of the memory.
  • One aspect of the present application provides a buried bit line formed in a bit line trench in a substrate, the buried bit line comprising: a first bit line layer formed in the bit line trench, and the top of the first bit line layer is lower than the surface of the substrate; a first barrier layer is formed at least partially between the first bit line layer and the inner wall of the bit line trench; A line layer, formed in the bit line trench, is used for connecting the first bit line layer with the drain region in the substrate.
  • Another aspect of the present application provides a method for forming a buried bit line, comprising: forming a first barrier layer on an inner wall of a bit line trench; forming a first bit line layer in the bit line trench, and the The top of the first bit line layer is lower than the surface of the substrate; a second bit line layer is formed in the bit line trench, and the second bit line layer is connected to the first bit line layer and the inside of the substrate the drain region.
  • FIG. 1 is a schematic top view of a buried bit line according to an embodiment
  • FIG. 2 is a schematic cross-sectional view of the buried bit line 100 in the embodiment of FIG. 1 along the AA' direction;
  • FIG. 3 is a schematic cross-sectional view of a buried bit line according to another embodiment
  • FIG. 4 is a schematic cross-sectional view of a buried bit line according to another embodiment
  • FIG. 5 is a schematic cross-sectional view of a buried bit line according to still another embodiment
  • FIG. 6 is a flowchart of a method for forming a buried bit line in the embodiment of FIG. 2;
  • FIG. 7 is a flowchart of a method for forming a buried bit line in the embodiment of FIG. 3;
  • step S101 is a schematic cross-sectional view of the substrate provided before step S101;
  • step S101 is a schematic cross-sectional view of the buried bit line after step S101;
  • FIG. 10 is a schematic cross-sectional view of the buried bit line after step S102;
  • FIG. 11 is a schematic cross-sectional view of the buried bit line after step S210;
  • step S240 is a schematic cross-sectional view of the buried bit line after step S240;
  • step S330 is a schematic cross-sectional view of the buried bit line after step S330;
  • step S401 is a schematic cross-sectional view of the buried bit line after step S401;
  • FIG. 16 is a flowchart of the method for forming the buried bit line in the embodiment of FIG. 4;
  • 17 is a schematic cross-sectional view of the buried bit line after step S220;
  • FIG. 19 is a schematic cross-sectional view of the buried bit line after step S360.
  • FIG. 1 is a schematic top view of the buried bit line 100 according to an embodiment
  • FIG. 2 is a schematic cross-sectional view of the buried bit line 100 in the embodiment of FIG.
  • active regions 300 and word lines 200 are also shown in FIG. 1 .
  • an active region 300 and an isolation structure 400 are formed in the substrate.
  • the word line 200 runs through the plurality of active regions 300 along the first direction, and divides the active regions 300 into source regions 310 and drain regions 320, which are arranged along the second direction. Specifically, two adjacent word lines 200 divide one active region 300 into one drain region 320 and two source regions 310, and one drain region 320 and two source regions 310 are in the second direction.
  • the source regions 310 , the drain regions 320 , and the source regions 310 are arranged in sequence.
  • the included angle between the first direction and the second direction is an acute angle, and the acute angle means that the second direction can overlap with the first direction after turning an included angle less than 90° in the clockwise direction.
  • the word line 200 is a buried word line 200, and the word line 200 includes a gate dielectric layer, a word line 200 metal, and a buried insulating layer sequentially formed in the trenches of the word line 200, and the buried insulating layer covers the gate dielectric layer and the buried insulating layer.
  • Word line 200 metal is
  • the bit line runs through the plurality of active regions 300 along the third direction, and the projection of the bit line in the direction perpendicular to the substrate coincides with the drain region 320 .
  • the third direction is perpendicular to the first direction.
  • the buried bit line 100 is formed in the bit line trench 11 in the substrate, and the buried bit line 100 includes a first bit line layer 110 , a first barrier layer 120 and a second bit line layer 110 .
  • the two bit line layer 130 is formed in the bit line trench 11 in the substrate, and the buried bit line 100 includes a first bit line layer 110 , a first barrier layer 120 and a second bit line layer 110 .
  • the two bit line layer 130 is perpendicular to the first direction.
  • the first bit line layer 110 is formed in the bit line trench 11, and the top of the first bit line layer 110 is lower than the surface of the substrate.
  • the depth of the bit line trench 11 is 60 nm to 150 nm, and the width of the bit line trench 11 is 10 nm to 60 nm.
  • the depth of the bit line trench 11 can be 100 nm and the width is 30 nm.
  • the height of the first bit line layer 110 is 30 nm to 120 nm, for example, 40 nm.
  • the depth of the bit line trench 11 and the height of the first bit line layer 110 both refer to the dimension in the direction perpendicular to the substrate, and the width of the bit line trench 11 refers to the dimension parallel to the substrate and perpendicular to the buried bit
  • the dimension in the extending direction of the wire 100 is the dimension in the first direction.
  • the first bit line layer 110 is connected to the bit line contact structure in the peripheral circuit region, so as to read and write and store data from the external structure.
  • the first barrier layer 120 is formed at least partially between the first bit line layer 110 and the inner wall of the bit line trench 11 .
  • the fact that the first barrier layer 120 is at least partially formed between the first bit line layer 110 and the inner wall of the bit line trench 11 means that the first barrier layer 120 can completely cover the first bit line layer 110 toward the bit line trench 11 and the first barrier layer 120 may further cover part or all of the inner wall of the bit line trench 11 .
  • the second bit line layer 130 is formed in the bit line trench 11 for connecting the first bit line layer 110 with the drain region 320 in the substrate.
  • the second bit line layer 130 completely fills the remaining space in the bit line trench 11, thereby connecting the first bit line layer 110 with the drain region 320 in the substrate.
  • the drain region 320 and the first bit line layer 110 are connected through the second bit line layer 130, and the drain region 320 and the source region 310 are turned on or off under the control of the word line 200 signal.
  • the first bit line layer 110 When the first bit line layer 110 , When the signal transmission path between the second bit line layer 130 , the drain region 320 , the source region 310 and the storage capacitor is turned on, the transmission of the stored data can be realized.
  • the word line 200 is connected to the gate of the transistor in the memory, and is used to control the turn-on and turn-off of the transistor, that is, to control the turn-on and turn-off of the conductive channel between the source region 310 and the drain region 320, buried type
  • the bit line 100 is connected to the drain region 320 , and the storage capacitor is connected to the source region 310 .
  • the transistor when the transistor is turned on, the corresponding conductive channel is turned on, and the signal is transmitted from the drain region 320 to the corresponding source region 310 or from the source region 310 to the corresponding drain region 320, thereby realizing the storage of data.
  • parasitic capacitance is the determining factor of the RC delay of the memory, and directly affects the data transfer performance of the memory.
  • the distance between adjacent bit line structures can be effectively increased, thereby effectively reducing the parasitic capacitance between two adjacent bit lines, and
  • the parasitic capacitance between the bit line and the cell node contact structure reduces the overall parasitic capacitance of the memory and improves the delay of data information transmission.
  • the process flow of the buried bit line 100 of the present embodiment is simple, and The improvement effect is better.
  • the diffusion phenomenon of the material of the first bit line layer 110 can be effectively prevented, that is, the damage of the first bit line layer 110 can be prevented, and the conduction of the first bit line layer 110 can be avoided.
  • the problems of reduced performance and increased resistance can further reduce the RC delay of the buried bit line 100 and improve the data transmission speed and reliability of the memory.
  • the buried bit line 100 shown is a linear structure.
  • the buried bit line 100 may also adopt other linear structures, such as The fold line or wave shape should not limit the protection scope of the present invention unduly.
  • the material of the second bit line layer 130 is doped polysilicon.
  • Doping elements in the doped polysilicon may include at least one of arsenic (As) and phosphorus (P).
  • As arsenic
  • P phosphorus
  • the conductivity of the polysilicon can be effectively improved, thereby reducing the resistance of the second bit line layer 130, thereby improving the problem of RC delay of the memory.
  • the active region 300 can be directly contacted with the second bit line layer 130 composed of doped polysilicon. Through the above arrangement, the buried bit line 100 of the present embodiment can be naturally formed between the active region 300 and the doped polysilicon.
  • An ohmic contact is formed at the contact surface of the polysilicon, so there is no need to additionally prepare a metal silicide layer at the contact surface of the active region 300 and the second bit line layer 130 to realize the ohmic contact, so that smaller process flows can be achieved.
  • the total resistance of the buried bit line 100 The total resistance of the buried bit line 100 .
  • FIG. 3 is a schematic cross-sectional view of the buried bit line 100 according to another embodiment.
  • the top of the first barrier layer 120 is flush with the top of the first bit line layer 110 .
  • the first barrier layer 120 is used to electrically isolate the first bit line layer 110 from the active region 300, thereby preventing leakage current and other phenomena, thereby improving the reliability of the memory.
  • the contact area of the second bit line layer 130 can be increased, thereby reducing the contact resistance of the second bit line layer 130, thereby reducing the device
  • the RC delay increases the transmission speed of the signal.
  • the material of the first barrier layer 120 can be at least one of titanium nitride, silicon oxide, silicon oxynitride, titanium silicon nitride and silicon nitride, and the above materials can effectively isolate the first bit line layer 110 from the The source region 300 is formed, thereby preventing the material of the first bit line layer 110 from diffusing, thereby improving the reliability of the first bit line layer 110 .
  • the buried bit line 100 further includes a second barrier layer 140 , and the second barrier layer 140 is formed at least partially between the second bit line layer 130 and the inner wall of the bit line trench 11 . between.
  • the second barrier layer 140 formed between the second bit line layer 130 and the substrate can prevent the doping elements in the second bit line layer 130 from diffusing to the active region 300, for example, preventing arsenic or phosphorus from diffusing into the active region 300 diffusion, so as to avoid the decrease of the doping concentration in the doped polysilicon, thereby preventing the decrease of the conductivity of the doped polysilicon.
  • the buried bit line 100 further includes a third barrier layer 160 , and the third barrier layer 160 is formed between the second bit line layer 130 and the first bit line layer 110 .
  • the third barrier layer 160 formed between the second bit line layer 130 and the first bit line layer 110 can reduce the contact resistance between the metal material in the film layers such as the first bit line layer 110 and the polysilicon, thereby further improving the memory performance.
  • the material of the second barrier layer 140 is cobalt silicide or titanium silicide.
  • the materials of the second barrier layer 140 and the third barrier layer 160 may be the same. If the materials of the second barrier layer 140 and the third barrier layer 160 are the same, they may be prepared through the same process flow, so as to improve the device performance. preparation efficiency. In other embodiments, the materials of the second barrier layer 140 and the third barrier layer 160 may also be different. Specifically, the two film layers that need to be blocked by the second barrier layer 140 are the second bit line layer 130 and the substrate, respectively. , the film layers to be blocked by the third barrier layer 160 are the first bit line layer 110 and the second bit line layer 130 respectively. It can be understood that different materials have different blocking requirements. The material of the film layer is selected from the corresponding barrier layer material, so as to obtain a better barrier effect, thereby improving the electrical performance of the device.
  • a contact metal layer 150 is formed between the third barrier layer 160 and the first bit line layer 110 , and the contact metal layer 150 and the third barrier layer 160 form an ohmic contact, reducing the bit line Contact resistance.
  • the material of the contact metal layer 150 may be cobalt, so as to form an ohmic contact with the second barrier layer 140 made of cobalt silicide.
  • the material of the contact metal layer 150 may also be titanium, so as to form an ohmic contact with the second barrier layer 140 made of titanium silicide.
  • the contact performance can be further improved by forming the ohmic contact between the contact metal layer 150 and the third barrier layer 160, thereby reducing the RC delay of the memory.
  • the second barrier layer 140 is formed at least partially between the second bit line layer 130 and the first barrier layer 120 and the top of the first barrier layer 120 and the top of the second barrier layer 140 are both flush with the surface of the substrate.
  • the second barrier layer 140 covers the inner wall of the first barrier layer 120 . If the third barrier layer 160 is formed on the surface of the first line layer 110 , the second barrier layer 140 is formed on the surface of the third barrier layer 160 and covers the first barrier layer 160 .
  • the inner wall of the barrier layer 120 is a schematic cross-sectional view of the buried bit line 100 according to another embodiment.
  • the second barrier layer 140 is formed at least partially between the second bit line layer 130 and the first barrier layer 120 and the top of the first barrier layer 120 and the top of the second barrier layer 140 are both flush with the surface of the substrate.
  • the second barrier layer 140 covers the inner wall of the first barrier layer 120 . If the third barrier layer 160 is formed on the surface of the first line layer 110 , the second barrier layer 140 is formed on the surface of the third barrier layer 160 and covers
  • the material of the second bit line layer 130 is doped polysilicon
  • the material of the second barrier layer 140 is titanium nitride
  • the material of the first barrier layer 120 is silicon nitride.
  • the second bit line layer 130 is covered with the second barrier layer 140 and the first barrier layer 120 in sequence, so that the second bit line layer 130 and the substrate can be better electrically isolated, so as to obtain more Good blocking effect.
  • a bit line contact structure needs to be connected to the end of each buried bit line 100 to obtain the bit line signal from the outside.
  • the center of the bit line contact structure needs to be aligned with the symmetry axis of the second bit line layer 130 parallel to its extending direction, so as to increase the contact area between the contact structure and the second bit line layer 130 and reduce the contact Contact resistance between the structure and the second bit line layer 130 . It can be understood that, in the actual fabrication process, it cannot be ensured that the contact structure is completely aligned with the second bit line layer 130, and therefore, the problem of performance degradation of the memory is likely to be caused.
  • the first barrier layer 120 and the second barrier layer 140 are provided.
  • the first barrier layer 120 and the second barrier layer 140 will not be damaged during the etching process, that is, the difference between the area and position of the contact window and the design value is effectively reduced, thereby preventing the contact structure and the second bit line
  • the contact between layers 130 is abnormal. Therefore, the buried bit line 100 of this embodiment can improve the process window for forming the contact structure, form the buried bit line 100 and the contact structure more accurately, improve the reliability and accuracy of the memory, and improve the operating speed of the memory .
  • FIG. 5 is a schematic cross-sectional view of the buried bit line 100 according to still another embodiment.
  • the third barrier layer 160 covers the first bit line layer 110 and the top of the first barrier layer 120 .
  • the second bit line layer 130 and the second barrier layer 140 are formed on the surface of the third barrier layer 160 , and the tops of the second bit line layer 130 and the second barrier layer 140 are both flush with the surface of the substrate.
  • the third barrier layer 160 is not only used to separate the first bit line layer 110 and the second bit line layer 130, but also used to separate the first barrier layer 120 and the second barrier layer 140, so as to obtain better device performance. It should be noted that FIG. 2 to FIG.
  • FIG. 6 is a flowchart of the method for forming the buried bit line 100 in the embodiment of FIG. 2 .
  • the method for forming the buried bit line 100 in this embodiment includes steps S100 to S300 .
  • first barrier layer 120 forming the first barrier layer 120 on the inner wall of the bit line trench 11 .
  • ALD atomic layer deposition
  • the material of the first barrier layer 120 can be titanium nitride or titanium silicon nitride.
  • the thickness of the first barrier layer 120 can be 3 nm to 8 nm.
  • the first barrier layer 120 can be 5 nm thick. Titanium nitride.
  • a first bit line layer 110 is formed in the bit line trench 11, and the top of the first bit line layer 110 is lower than the surface of the substrate.
  • the depth of the bit line trench 11 is 60 nm to 150 nm, and the width of the bit line trench 11 is 10 nm to 60 nm.
  • the depth of the bit line trench 11 can be 100 nm and the width is 30 nm.
  • the height of the first bit line layer 110 is 30 nm to 120 nm, for example, 40 nm. That is, the top of the first bit line layer 110 is lower than the surface of the substrate.
  • a second bit line layer 130 is formed in the bit line trench 11, and the second bit line layer 130 communicates with the first bit line layer 110 and the drain region 320 in the substrate.
  • FIG. 7 is a flowchart of the method for forming the buried bit line 100 in the embodiment of FIG. 3 . Referring to FIG. 7 , in one embodiment, steps S101 to S102 are further included before step S100 .
  • FIG. 8 is a schematic cross-sectional view of the substrate provided before step S101
  • FIG. 9 is a cross-sectional schematic view of the buried bit line 100 after step S101 .
  • the material of the hard mask layer 12 may be silicon nitride.
  • the hard mask layer 12 is etched to form openings on the hard mask layer 12, the openings expose part of the surface of the substrate in a direction perpendicular to the substrate, and the openings are shaped and positioned in accordance with the bit lines to be formed The shape and position of the grooves 11 are matched.
  • FIG. 10 is a schematic cross-sectional view of the buried bit line 100 after step S102.
  • the bit line trench 11 can be formed by dry etching or wet etching process. According to the requirements of the process and device, the depth of the bit line trench 11 is 60 nm to 150 nm, and the width of the bit line trench 11 is 10 nm to 60 nm.
  • step S200 includes steps S210 to S220.
  • FIG. 11 is a schematic cross-sectional view of the buried bit line 100 after step S210.
  • the bit line metal layer 111 can be formed by chemical vapor deposition (CVD), and the top of the bit line metal layer 111 is higher than the surface of the substrate. , to ensure that the bit line metal layer 111 completely fills the bit line trench 11 .
  • CVD chemical vapor deposition
  • CMP chemical mechanical polishing
  • the material of the bit line metal layer 111 may be, for example, tungsten.
  • bit line metal layer 111 etch back the bit line metal layer 111 to a predetermined depth, and the remaining bit line metal layer 111 is used as the first bit line layer 110 .
  • the bit line metal layer 111 can be etched back to a predetermined depth by dry etch, and when the bit line metal layer 111 is etched, the first barrier layer 120 on the surface of the substrate can be removed simultaneously. Further, the bit line metal layer 111 with a thickness of 30 nm to 120 nm can be etched back from the surface of the substrate to form the first bit line layer 110 .
  • step S300 before forming the second bit line layer 130 in the bit line trench 11, step S300 further includes:
  • FIG. 12 is a schematic cross-sectional view of the buried bit line 100 after step S230. Wet etching can be used to remove part of the first barrier layer 120 on the inner wall of the bit line trench 11 after step S220, and The first barrier layer 120 having the same height as the first bit line layer 110 remains.
  • step S300 before forming the second bit line layer 130 in the bit line trench 11, step S300 further includes:
  • FIG. 13 is a schematic cross-sectional view of the buried bit line 100 after step S240.
  • Forming the contact metal layer 150 in the bit line trench 11 includes forming titanium or cobalt on the inner wall of the bit line trench 11, that is, the contact
  • the material of the metal layer 150 may be titanium or cobalt.
  • titanium or cobalt may be formed on the inner wall of the bit line trench 11 by adopting a physical vapor deposition process (Physical Vapor Deposition, PVD).
  • step S300 includes steps S310 to S330.
  • S310 filling the bit line trench 11 with polysilicon, and doping the polysilicon with arsenic by in-situ doping during filling.
  • chemical vapor deposition Chemical Vapor Deposition, CVD
  • CVD chemical Vapor Deposition
  • S320 The surface of the polysilicon is planarized by a chemical mechanical polishing process.
  • FIG. 14 is a schematic cross-sectional view of the buried bit line 100 after step S330.
  • the step further includes:
  • Step S400 heat treatment on the substrate, so that the contact surface between the second bit line layer 130 and the contact metal layer 150 and the contact surface between the second bit line layer 130 and the substrate react, and the reaction generates the second barrier layer 140 and the second barrier layer 140 .
  • Three barrier layers 160 That is, a schematic cross-sectional view of the buried bit line 100 as shown in FIG. 3 is formed.
  • step S401 is further included before step S400 : etching and removing the second bit line layer 130 , the bit line metal layer 111 and the hard mask layer 12 on the surface of the substrate, and the etching stops at the shallow trench isolation structure 400 , and remove residual etching byproducts from the surface by wet etching.
  • FIG. 15 is a schematic cross-sectional view of the buried bit line 100 after step S401 .
  • step S100 is a flowchart of the method for forming the buried bit line 100 in the embodiment of FIG. 4 .
  • steps S101 and S102 are included before step S100 .
  • S101 Form a patterned hard mask layer 12 on a substrate.
  • the material of the hard mask layer 12 can be silicon nitride
  • the hard mask layer 12 is etched to form an opening on the hard mask layer 12, and the opening exposes a part of the surface of the substrate along a direction perpendicular to the substrate, And the shape and position of the opening match the shape and position of the bit line trench 11 to be formed.
  • bit line trench 11 the substrate is exposed through the hard mask layer 12 to a set depth to form the bit line trench 11 .
  • the bit line trench 11 can be formed by dry etching or wet etching process. According to process and device requirements, the depth of the bit line trench 11 is 60 nm to 150 nm, and the width of the bit line trench 11 is 10 nm to 60 nm.
  • step S100 includes: forming a first barrier layer 120 on the surface of the trench by using an atomic layer deposition process.
  • the material of the first barrier layer 120 may be, for example, at least one of silicon nitride, silicon oxide, and silicon oxynitride.
  • the thickness of the first barrier layer 120 may be 2 nm to 10 nm, for example, may be 5 nm.
  • step S200 includes steps S210 to S220.
  • bit line metal layer 111 may be formed by chemical vapor deposition (CVD), and the top of the bit line metal layer 111 is higher than the surface of the substrate to ensure that the bit line metal layer 111 completely fills the bit line trench 11 .
  • CVD chemical vapor deposition
  • CMP chemical mechanical polishing
  • the material of the bit line metal layer 111 may be, for example, tungsten.
  • bit line metal layer 111 etch back the bit line metal layer 111 to a predetermined depth, and the remaining bit line metal layer 111 is used as the first bit line layer 110 .
  • the cross-sectional schematic diagrams of the buried bit line 100 after steps S101 to S210 can be referred to FIG. 9 to FIG. 11
  • the cross-sectional schematic diagram of the buried bit line 100 after step S220 can be referred to FIG. 17 .
  • step S270 is further included before step S300.
  • a second barrier layer 140 is formed on the inner wall of the bit line trench 11 by using an atomic layer deposition (ALD) process.
  • ALD atomic layer deposition
  • FIG. 18 is a schematic cross-sectional view of the buried bit line 100 after step S270.
  • the material of the second barrier layer 140 can be titanium nitride or titanium silicon nitride.
  • the thickness may be 2 nm to 8 nm, for example, the second barrier layer 140 may be titanium nitride with a thickness of 5 nm.
  • the second barrier layer 140 is formed on the surface of the first barrier layer 120 .
  • the same process flow can be used to prepare the second barrier layer 140 and the third barrier layer 160, that is, step S270 and step S280 are performed simultaneously to reduce The number of process flows, thereby improving the fabrication efficiency of the device, for example, the atomic layer deposition process can be used to form the second barrier layer 140 on the inner wall of the bit line trench 11 and simultaneously form the third barrier layer on the surface of the first bit line layer 110 160.
  • the second barrier layer 140 and the third barrier layer 160 may be formed in steps.
  • the present embodiment does not specifically limit the preparation sequence of the second barrier layer 140 and the third barrier layer 160 , that is, does not specifically limit whether to prepare the second barrier layer 140 or the third barrier layer 160 first.
  • the third barrier layer 160 may be formed on the surface of the first line layer 110 first, and then the second barrier layer 140 may be formed on the surface of the first barrier layer 120 .
  • step S300 includes steps S340 to S360.
  • S340 Filling the bit line trench 11 with polysilicon, and doping the polysilicon with arsenic by in-situ doping during filling.
  • chemical vapor deposition Chemical Vapor Deposition, CVD
  • CVD chemical Vapor Deposition
  • S350 The surface of the polysilicon is planarized by a chemical mechanical polishing process.
  • FIG. 19 is a schematic cross-sectional view of the buried bit line 100 after step S360.
  • step S300 further includes step S410 : etching and removing the second bit line layer 130 , the second barrier layer 140 , the first barrier layer 120 and the hard mask layer 12 on the surface of the substrate, and the etching stops at The top of the shallow trench isolation structure 400 .
  • the buried bit line 100 prepared by using the method embodiments of FIG. 6 , FIG. 7 and FIG. 16 corresponds to the structure in the aforementioned product embodiment of the buried bit line 100 , and each film layer structure The function is the same as that of the product, and will not be repeated in the method examples.
  • steps in the flowcharts of FIGS. 6 , 7 and 16 are sequentially displayed in accordance with the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, the execution of these steps is not strictly limited to the order, and these steps may be performed in other orders. Moreover, at least a part of the steps in FIG. 6 , FIG. 7 and FIG. 16 may include multiple sub-steps or multiple stages, and these sub-steps or stages are not necessarily executed at the same time, but may be executed at different times. The order of execution of the sub-steps or phases is also not necessarily sequential, but may be performed alternately or alternately with other steps or at least a portion of the sub-steps or phases of the other steps.

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Abstract

本发明涉及一种埋入式位线及其形成方法，埋入式位线形成于衬底内的位线沟槽中，埋入式位线包括：第一位线层，形成于位线沟槽中，且第一位线层的顶部低于衬底的表面第一阻挡层，至少部分形成于第一位线层和位线沟槽的内壁之间；第二位线层，形成于位线沟槽中，用于连通第一位线层和衬底内的漏极区。

Description

埋入式位线及其形成方法
本申请要求于2020年10月15日提交的申请号为202011101808.0、名称为“埋入式位线及其形成方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及半导体器件技术领域，特别是涉及一种埋入式位线及其形成方法。
背景技术
随着半导体集成电路技术的不断发展，集成电路中的半导体元件的排布密度也相应地不断增加，从而导致相邻的半导体元件之间的距离也不断缩小，进而直接导致相邻的两个半导体元件之间的寄生电容增加。半导体存储器作为一种被广泛使用的半导体器件，其性能也受到寄生电容的制约。
示例性地，半导体存储器中包括多条位线，多条位线通常是形成在衬底上并沿着预定方向平行排布。随着半导体器件尺寸的不断缩减，相邻的位线之间的间距尺寸也逐渐缩减，从而导致相邻的位线之间极易产生较大的寄生电容，进而致使存储器的延迟问题严重。
发明内容
本申请一方面提供一种埋入式位线，形成于衬底内的位线沟槽中，所述埋入式位线包括：第一位线层，形成于所述位线沟槽中，且所述第一位线层的顶部低于所述衬底的表面；第一阻挡层，至少部分形成于所述第一位线层和所述位线沟槽的内壁之间；第二位线层，形成于所述位线沟槽中，用于连通所述第一位线层和所述衬底内的漏极区。
本申请另一方面提供一种埋入式位线的形成方法，包括：在位线沟槽的内壁上形成第一阻挡层；在所述位线沟槽中形成第一位线层，所述第一位线层的顶部低于衬底的表面；在所述位线沟槽中形成第二位线层，所述第二位线层连通所述第一位线层和所述衬底内的漏极区。
本发明的各个实施例的细节将在下面的附图和描述中进行说明。根据说明书、附图以及权利要求书的记载，本领域技术人员将容易理解本发明的其它特征、解决的问题以及有益效果。
附图说明
为了更好地描述和说明本申请的实施例，可参考一幅或多幅附图，但用于描述附图的附 加细节或示例不应当被认为是对本申请的发明创造、目前所描述的实施例或优选方式中任何一者的范围的限制。
图1为一实施例的埋入式位线的俯视示意图；
图2为图1实施例的埋入式位线100沿AA’方向的剖面示意图；
图3为另一实施例的埋入式位线的剖面示意图；
图4为又一实施例的埋入式位线的剖面示意图；
图5为再一实施例的埋入式位线的剖面示意图；
图6为图2实施例的埋入式位线的形成方法的流程图；
图7为图3实施例的埋入式位线的形成方法的流程图；
图8为步骤S101前提供的衬底的剖面示意图；
图9为步骤S101后的埋入式位线的剖面示意图；
图10为步骤S102后的埋入式位线的剖面示意图；
图11为步骤S210后的埋入式位线的剖面示意图；
图12为步骤S230后的埋入式位线的剖面示意图；
图13为步骤S240后的埋入式位线的剖面示意图；
图14为步骤S330后的埋入式位线的剖面示意图；
图15为步骤S401后的埋入式位线的剖面示意图；
图16为图4实施例的埋入式位线的形成方法的流程图；
图17为步骤S220后的埋入式位线的剖面示意图；
图18为步骤S270后的埋入式位线的剖面示意图；
图19为步骤S360后的埋入式位线的剖面示意图。
具体实施方式
为了便于理解本发明，下面将参照相关附图对本发明进行更全面的描述。附图中给出了本发明的首选实施例。但是，本发明可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本发明的公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本发明的技术领域的技术人员通常理解的含义相同。本文中在本发明的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本发明。本文可能所使用的术语“及/或”包括一个或多个相关的所列项目的任意的和所有的组合。
在本发明的描述中，需要理解的是，可能存在的术语“上”、“下”、“竖直”、“水平”、“内”、 “外”等指示的方位或位置关系为基于附图所示的方法或位置关系，仅是为了便于描述本发明和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本发明的限制。
图1为一实施例的埋入式位线100的俯视示意图，图2为图1实施例的埋入式位线100沿AA’方向的剖面示意图，为了便于说明，除埋入式位线100外，图1中还示出了有源区300和字线200。参考图1和图2，在本实施例中，衬底中形成有有源区300和隔离结构400。
其中，字线200沿第一方向贯穿多个有源区300，并将有源区300划分为源极区310和漏极区320，源极区310和漏极区320沿第二方向排列。具体地，相邻的两条字线200将一个有源区300划分为一个漏极区320和两个源极区310，且一个漏极区320和两个源极区310在第二方向上以源极区310、漏极区320、源极区310的顺序依次排列。其中，第一方向与第二方向之间的夹角为锐角，锐角是指第二方向沿顺时针方向转过小于90°的夹角后可以与第一方向重合。示例性地，字线200为埋入式字线200，字线200包括在字线200沟槽中依次形成的栅电介质层、字线200金属和掩埋绝缘层，掩埋绝缘层覆盖栅电介质层和字线200金属。
进一步地，位线沿第三方向贯穿多个有源区300，且位线在垂直于衬底的方向上的投影与漏极区320相重合。其中，第三方向与第一方向相垂直。参考图2，在本实施例中，埋入式位线100形成于衬底内的位线沟槽11中，埋入式位线100包括第一位线层110、第一阻挡层120和第二位线层130。
第一位线层110形成于位线沟槽11中，且第一位线层110的顶部低于衬底的表面。其中，位线沟槽11的深度为60nm至150nm，位线沟槽11的宽度为10nm至60nm，例如，位线沟槽11的深度可以为100nm且宽度为30nm。第一位线层110的高度为30nm至120nm，例如为40nm。其中，位线沟槽11的深度和第一位线层110的高度均是指垂直于衬底方向上的尺寸，位线沟槽11的宽度是指平行于衬底且垂直于埋入式位线100的延伸方向上的尺寸，即第一方向上的尺寸。其中，第一位线层110在外围电路区与位线接触结构连接，从而从外部结构读写存储数据。
第一阻挡层120至少部分形成于第一位线层110和位线沟槽11的内壁之间。其中，第一阻挡层120至少部分形成于第一位线层110和位线沟槽11的内壁之间是指，第一阻挡层120可以完全覆盖第一位线层110朝向位线沟槽11的内壁的多个表面，且第一阻挡层120也可以进一步覆盖位线沟槽11的部分或全部的内壁。
第二位线层130形成于位线沟槽11中，用于连通第一位线层110和衬底内的漏极区320。第二位线层130完全填充位线沟槽11内的剩余空间，从而连通第一位线层110和衬底内的 漏极区320。漏极区320和第一位线层110通过第二位线层130连通，漏极区320和源极区310在字线200信号的控制下导通或断开，当第一位线层110、第二位线层130、漏极区320、源极区310和存储电容之间的信号传输路径导通时，即可实现存储数据的传输。
即，字线200连接至存储器中的晶体管的栅极，用于控制晶体管的开启和关闭，即控制源极区310和漏极区320之间导电沟道的导通和断开，埋入式位线100连接至漏极区320，存储电容连接至源极区310。具体地，当晶体管开启时，相应的导电沟道导通，信号从漏极区320传输至相应的源极区310或从源极区310传输至相应的漏极区320，从而实现存储数据的读写；当晶体管关闭时，相应的导电沟道断开，源极区310与漏极区320之间不发生信号传输。
根据寄生电容的产生原理可知，在形成寄生电容的两个电极板的尺寸不变的前提下，增大电极板之间的间距或减小两个电极板之间的相对面积，都可以有效降低寄生电容，而且，寄生电容是存储器的RC延迟的决定因素，直接影响着存储器的数据传输性能。
因此，在本实施例中，通过设置埋入式位线100，可以有效增大相邻的位线结构之间的距离，从而有效减小相邻的两条位线之间的寄生电容，以及位线与电容接触结构(cell node contact)之间的寄生电容，进而降低存储器整体的寄生电容，改善数据信息传输的延迟的问题。相比采用空气间隔层(air gap)或采用低介电材料(low k material)等用于减低金属导线间的寄生电容的方法，本实施例的埋入式位线100的工艺流程简单，且改善效果较好。而且，本实施例通过设置第一阻挡层120，可以有效防止第一位线层110的材料的扩散现象，即，防止第一位线层110的损伤，以避免第一位线层110的导电性能降低、电阻增大的问题，从而进一步降低了埋入式位线100的RC延迟，提高了存储器的数据传输速度和可靠性。
需要说明的是，在图1所示的实施例中，示出的埋入式位线100为直线型结构，在其它实施例中，埋入式位线100也可以采用其它线型结构，例如折线型或波浪型，此处不应过分限制本发明的保护范围。
在其中一个实施例中，第二位线层130的材料为掺杂多晶硅。掺杂多晶硅中的掺杂元素可以包括砷(As)和磷(P)中的至少一种。在本实施例中，通过在多晶硅中掺杂砷或磷可以有效提升多晶硅的导电性能，从而降低第二位线层130的电阻，进而改善存储器的RC延迟的问题。进一步地，可以使有源区300直接接触由掺杂多晶硅构成的第二位线层130，通过以上设置方式，本实施例的埋入式位线100可以自然地在有源区300和掺杂多晶硅的接触面处形成欧姆接触，因此，无需在有源区300和第二位线层130的接触面处额外制备金属硅化物层以实现欧姆接触，从而以较少的工艺流程实现了较小的埋入式位线100的总电阻。
图3为另一实施例的埋入式位线100的剖面示意图，参考图3，在本实施例中，第一阻 挡层120的顶部与第一位线层110的顶部相齐平。第一阻挡层120用于电性隔离第一位线层110和有源区300，从而防止漏电流等现象，进而提高存储器的可靠性。当第一阻挡层120的顶部与第一位线层110的顶部相齐平时，可以增大第二位线层130的接触面积，从而减小第二位线层130的接触电阻，进而降低器件的RC延迟，提高信号的传输速度。进一步地，第一阻挡层120材料可以为氮化钛、氧化硅、氮氧化硅、钛氮化硅和氮化硅中的至少一种，上述材料可以有效地隔离第一位线层110和有源区300，从而防止第一位线层110的材料发生扩散，进而提高第一位线层110的可靠性。
在其中一个实施例中，继续参考图3，埋入式位线100还包括第二阻挡层140，第二阻挡层140至少部分形成于第二位线层130和位线沟槽11的内壁之间。其中，形成在第二位线层130与衬底之间的第二阻挡层140可以防止第二位线层130中的掺杂元素向有源区300扩散，例如防止砷或磷向有源区300扩散，从而避免掺杂多晶硅中的掺杂浓度降低，进而防止掺杂多晶硅的导电性能下降。
在其中一个实施例中，继续参考图3，埋入式位线100还包括第三阻挡层160，第三阻挡层160形成于第二位线层130与第一位线层110之间。形成在第二位线层130与第一位线层110之间的第三阻挡层160可以降低第一位线层110等膜层中的金属材料与多晶硅之间的接触电阻，从而进一步提升存储器的性能。在其中一个实施例中，第二阻挡层140的材料为硅化钴或硅化钛。
在一些实施例中，第二阻挡层140和第三阻挡层160的材料可以相同，若第二阻挡层140和第三阻挡层160的材料相同，则可以通过同一工艺流程进行制备，以提高器件的制备效率。在另一些实施例中，第二阻挡层140和第三阻挡层160的材料也可以不同，具体地，需第二阻挡层140阻挡的两个膜层分别为第二位线层130和衬底，需第三阻挡层160阻挡的膜层分别为第一位线层110和第二位线层130，可以理解的是，不同的材料具有不同的阻挡需求，因此，可以根据需阻挡的两个膜层的材料选择对应的阻挡层材料，从而获得更好的阻挡效果，进而提升器件的电学性能。
在其中一个实施例中，继续参考图3，第三阻挡层160和第一位线层110之间形成有接触金属层150，接触金属层150和第三阻挡层160形成欧姆接触，降低位线接触电阻。示例性地，接触金属层150的材料可以为钴，以与硅化钴材质的第二阻挡层140形成欧姆接触。另一示例性地，接触金属层150的材料也可以为钛，以与硅化钛材质的第二阻挡层140形成欧姆接触。本实施例通过使接触金属层150和第三阻挡层160形成欧姆接触可以进一步提升接触性能，从而降低存储器的RC延迟。
图4为又一实施例的埋入式位线100的剖面示意图，参考图4，在本实施例中，第二阻 挡层140至少部分形成于第二位线层130和第一阻挡层120之间，且第一阻挡层120的顶部和第二阻挡层140的顶部均与衬底的表面相齐平。第二阻挡层140覆盖第一阻挡层120的内壁，若第一位线层110表面形成有第三阻挡层160，则第二阻挡层140形成于第三阻挡层160的表面，且覆盖第一阻挡层120的内壁。示例性地，第二位线层130的材料为掺杂多晶硅，第二阻挡层140的材料为氮化钛，第一阻挡层120的材料为氮化硅。基于本实施的结构，第二位线层130外部依次包覆有第二阻挡层140和第一阻挡层120，因此可以更好地电性隔离第二位线层130和衬底，从而获得更好的阻挡效果。
进一步地，在每根埋入式位线100的末端需要连接有位线接触结构，以从外部获取位线信号。在设计过程中，位线接触结构的中心需要与第二位线层130的平行于其延伸方向的对称轴相对齐，从而增大接触结构与第二位线层130的接触面积，以降低接触结构与第二位线层130之间的接触电阻。可以理解的是，在实际制备过程中，无法确保接触结构与第二位线层130完全对齐，因此，容易导致存储器的性能下降的问题。在本实施例中，通过设置与第二位线层130的蚀刻性能不同的第一阻挡层120和第二阻挡层140，即使在形成接触结构的蚀刻过程中发生了位置偏移的现象，第一阻挡层120和第二阻挡层140也不会在蚀刻过程中受到损伤，即，有效减小了接触窗的面积和位置与设计值之间的差异，从而防止了接触结构和第二位线层130之间的接触异常。因此，本实施例的埋入式位线100可以改善形成接触结构的工艺窗口，更加准确地形成埋入式位线100和接触结构，提升了存储器的可靠性和准确性，改善存储器的运行速度。
图5为再一实施例的埋入式位线100的剖面示意图，参考图5，在本实施例中，第三阻挡层160覆盖第一位线层110和第一阻挡层120的顶部，第二位线层130和第二阻挡层140形成于第三阻挡层160的表面，且第二位线层130的顶部和第二阻挡层140的顶部均与衬底的表面相齐平。在本实施例中，第三阻挡层160不仅用于间隔第一位线层110和第二位线层130，还用于间隔第一阻挡层120和第二阻挡层140，从而获得更好的器件性能。需要说明的是，图2至图5提供了多个不同的实施例，但示出的实施例仅用于辅助说明，而不用于具体限定本申请的保护范围，其他与本申请的构思相同的实施方式也属于本申请的保护范围。
图6为图2实施例的埋入式位线100的形成方法的流程图，参考图6，本实施例的埋入式位线100的形成方法包括步骤S100至S300。
S100：在位线沟槽11的内壁上形成第一阻挡层120。具体地，可以采用原子层沉积工艺(Atomic layer deposition，ALD)在位线沟槽11的内壁形成第一阻挡层120。第一阻挡层120的材料可以氮化钛或钛氮化硅，根据工艺及器件性能需求，第一阻挡层120的厚度可以为3nm至8nm，例如，第一阻挡层120可以为厚度为5nm的氮化钛。
S200：在位线沟槽11中形成第一位线层110，第一位线层110的顶部低于衬底的表面。其中，位线沟槽11的深度为60nm至150nm，位线沟槽11的宽度为10nm至60nm，例如，位线沟槽11的深度可以为100nm且宽度为30nm。第一位线层110的高度为30nm至120nm，例如为40nm。即，第一位线层110的顶部低于衬底的表面。
S300：在位线沟槽11中形成第二位线层130，第二位线层130连通第一位线层110和衬底内的漏极区320。
图7为图3实施例的埋入式位线100的形成方法的流程图，参考图7，在其中一个实施例中，步骤S100前还包括步骤S101至S102。
S101：在衬底上形成图形化的硬掩膜层12。具体地，图8为步骤S101前提供的衬底的剖面示意图，图9为步骤S101后的埋入式位线100的剖面示意图，硬掩膜层12的材料可以为氮化硅。参考图9，对硬掩膜层12进行蚀刻以在硬掩膜层12上形成开口，开口沿垂直于衬底的方向暴露部分衬底的表面，且开口的形状和位置与待形成的位线沟槽11的形状和位置相匹配。
S102：通过硬掩膜层12暴露的衬底至设定深度，以形成位线沟槽11。具体地，图10为步骤S102后的埋入式位线100的剖面示意图，可以通过干法蚀刻或湿法蚀刻工艺形成位线沟槽11，根据工艺及器件需求，位线沟槽11的深度为60nm至150nm，位线沟槽11的宽度为10nm至60nm。
在其中一个实施例中，步骤S200包括步骤S210至S220。
S210：在位线沟槽11中填充位线金属层111。具体地，图11为步骤S210后的埋入式位线100的剖面示意图，可以采用化学气相沉积(CVD)形成位线金属层111，且使位线金属层111的顶部高于衬底的表面，以确保位线金属层111完全填满位线沟槽11。形成位线金属层111后，可以对衬底进行化学机械抛光工艺(Chemical Mechanical Polishing，CMP)处理，以提高位线金属层111的表面的平整度，从而在后续蚀刻步骤中获得较为准确的蚀刻深度。其中，位线金属层111的材料例如可以为钨。
S220：回刻位线金属层111至预设深度，剩余的位线金属层111作为第一位线层110。具体地，可以通过干法蚀刻(dry etch)回刻位线金属层111至预设深度，而且，在对位线金属层111进行蚀刻时，可以同时去除衬底表面的第一阻挡层120。进一步地，可以从衬底表面向下回刻30nm至120nm的位线金属层111，以形成第一位线层110。
在其中一个实施例中，步骤S300在位线沟槽11中形成第二位线层130前，还包括：
S230：回刻第一阻挡层120至预设深度，以使剩余的第一阻挡层120的顶部与第一位线层110的顶部相齐平。具体地，图12为步骤S230后的埋入式位线100的剖面示意图，可以 采用湿法蚀刻(wet etch)去除步骤S220后位线沟槽11的内壁上的部分第一阻挡层120，并保留与第一位线层110的高度相同的第一阻挡层120。
在其中一个实施例中，步骤S300在位线沟槽11中形成第二位线层130前，还包括：
S240：在位线沟槽11中形成接触金属层150，接触金属层150覆盖第一位线层110、第一阻挡层120以及位线沟槽11的内壁。具体地，图13为步骤S240后的埋入式位线100的剖面示意图，在位线沟槽11中形成接触金属层150包括在位线沟槽11的内壁上形成钛或钴，即，接触金属层150的材料可以为钛或钴。进一步地，可以采用物理气相沉积工艺(Physical Vapor Deposition，PVD)在位线沟槽11的内壁上形成钛或钴。在其中一个实施例中，步骤S300包括步骤S310至S330。
S310：在位线沟槽11中填充多晶硅，并在填充时通过原位掺杂的方式在多晶硅中掺杂砷。具体地，可以采用化学气相沉积(Chemical Vapor Deposition，CVD)在位线沟槽11中沉积多晶硅。
S320：通过化学机械抛光工艺平坦化处理多晶硅的表面。
S330：对多晶硅进行离子注入以在多晶硅中掺杂磷，掺杂后的多晶硅作为第二位线层130。具体地，图14为步骤S330后的埋入式位线100的剖面示意图。
步骤S300在位线沟槽11中形成第二位线层130后，还包括：
步骤S400：对衬底进行热处理，以使第二位线层130和接触金属层150的接触面以及第二位线层130和衬底的接触面发生反应，反应生成第二阻挡层140和第三阻挡层160。即，形成如图3所示的埋入式位线100的剖面示意图。
在其中一个实施例中，步骤S400前还包括步骤S401：蚀刻去除衬底表面的第二位线层130、位线金属层111以及硬掩膜层12，且蚀刻停止在浅沟槽隔离结构400的顶部，并通过湿法蚀刻去除表面残余的蚀刻副产物。具体地，图15为步骤S401后的埋入式位线100的剖面示意图。
图16为图4实施例的埋入式位线100的形成方法的流程图，参考图16，在本实施例中，与图7实施例相似地，步骤S100前包括步骤S101和步骤S102。
S101：在衬底上形成图形化的硬掩膜层12。具体地，硬掩膜层12的材料可以为氮化硅，对硬掩膜层12进行蚀刻以在硬掩膜层12上形成开口，开口沿垂直于衬底的方向暴露部分衬底的表面，且开口的形状和位置与待形成的位线沟槽11的形状和位置相匹配。
S102：通过硬掩膜层12暴露的衬底至设定深度，以形成位线沟槽11。具体地，可以通过干法蚀刻或湿法蚀刻工艺形成位线沟槽11，根据工艺及器件需求，位线沟槽11的深度为60nm至150nm，位线沟槽11的宽度为10nm至60nm。
在其中一个实施例中，步骤S100包括：采用原子层沉积工艺在沟槽表面形成第一阻挡层120。具体地，第一阻挡层120的材料例如可以为氮化硅、氧化硅和氮氧化硅中的至少一种。进一步地，根据工艺及器件性能需求，第一阻挡层120的厚度可为2nm至10nm，例如可以为5nm。
在其中一个实施例中，步骤S200包括步骤S210至S220。
S210：在位线沟槽11中填充位线金属层111。具体地，可以采用化学气相沉积(CVD)形成位线金属层111，且使位线金属层111的顶部高于衬底的表面，以确保位线金属层111完全填满位线沟槽11。形成位线金属层111后，可以对衬底进行化学机械抛光工艺(Chemical Mechanical Polishing，CMP)处理，以提高位线金属层111的表面的平整度，从而在后续蚀刻步骤中获得较为准确的蚀刻深度。其中，位线金属层111的材料例如可以为钨。
S220：回刻位线金属层111至预设深度，剩余的位线金属层111作为第一位线层110。
具体地，步骤S101至步骤S210后的埋入式位线100的剖面示意图可对应参考图9至图11，步骤S220后的埋入式位线100的剖面示意图可参考图17。
在其中一个实施例中，步骤S300前还包括步骤S270。
S270：采用原子层沉积工艺(Atomic layer deposition，ALD)在位线沟槽11的内壁形成第二阻挡层140。具体地，图18为步骤S270后的埋入式位线100的剖面示意图，第二阻挡层140的材料可以氮化钛或钛氮化硅，根据工艺及器件性能需求，第二阻挡层140的厚度可以为2nm至8nm，例如，第二阻挡层140可以为厚度为5nm的氮化钛。在第一阻挡层120的表面形成第二阻挡层140。
S280：在第一位线层110的表面形成第三阻挡层160。
进一步地，若第二阻挡层140和第三阻挡层160的材料相同，则可以采用同一工艺流程制备第二阻挡层140和第三阻挡层160，即，步骤S270和步骤S280同时执行，以减少工艺流程的数量，从而提高器件的制备效率，例如，可以采用原子层沉积工艺在位线沟槽11的内壁形成第二阻挡层140并同时在第一位线层110的表面形成第三阻挡层160。
再进一步地，若第二阻挡层140和第三阻挡层160的材料相同，则可以分步形成第二阻挡层140和第三阻挡层160。而且，本实施例不具体限定第二阻挡层140和第三阻挡层160的制备顺序，即，不具体限定先制备第二阻挡层140还是先制备第三阻挡层160。示例性地，可以先在第一位线层110的表面形成第三阻挡层160，然后在第一阻挡层120的表面形成第二阻挡层140。
在其中一个实施例中，步骤S300包括步骤S340至步骤S360。
S340：在位线沟槽11中填充多晶硅，并在填充时通过原位掺杂的方式在多晶硅中掺杂 砷。具体地，可以采用化学气相沉积(Chemical Vapor Deposition，CVD)在位线沟槽11中沉积多晶硅。
S350：通过化学机械抛光工艺平坦化处理多晶硅的表面。
S360：对多晶硅进行离子注入以在多晶硅中掺杂磷，并对衬底进行快速热处理，热处理后的多晶硅作为第二位线层130。具体地，图19为步骤S360后的埋入式位线100的剖面示意图。
在其中一个实施例中，步骤S300后还包括步骤S410：蚀刻去除衬底表面的第二位线层130、第二阻挡层140、第一阻挡层120以及硬掩膜层12，且蚀刻停止在浅沟槽隔离结构400的顶部。
需要说明的是，采用图6、图7和图16的方法实施例制备的埋入式位线100与前述埋入式位线100的产品实施例中的结构相对应，且每个膜层结构的作用与产品相同，在方法实施例中不再进行赘述。
应该理解的是，虽然图6、图7和图16的流程图中的各个步骤按照箭头的指示依次显示，但是这些步骤并不是必然按照箭头指示的顺序依次执行。除非本文中有明确的说明，这些步骤的执行并没有严格的顺序限制，这些步骤可以以其它的顺序执行。而且，图6、图7和图16中的至少一部分步骤可以包括多个子步骤或者多个阶段，这些子步骤或者阶段并不必然是在同一时刻执行完成，而是可以在不同的时刻执行，这些子步骤或者阶段的执行顺序也不必然是依次进行，而是可以与其它步骤或者其它步骤的子步骤或者阶段的至少一部分轮流或者交替地执行。
以上实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。

Claims (15)

  1. 一种埋入式位线，形成于衬底内的位线沟槽中，所述埋入式位线包括：
    第一位线层，形成于所述位线沟槽中，且所述第一位线层的顶部低于所述衬底的表面；
    第一阻挡层，至少部分形成于所述第一位线层和所述位线沟槽的内壁之间；
    第二位线层，形成于所述位线沟槽中，用于连通所述第一位线层和所述衬底内的漏极区。
  2. 根据权利要求1所述的埋入式位线，其中，还包括：
    第二阻挡层，至少部分形成于所述第二位线层和所述位线沟槽的内壁之间。
  3. 根据权利要求2所述的埋入式位线，其中，所述埋入式位线还包括第三阻挡层，所述第三阻挡层形成于所述第二位线层与所述第一位线层之间。
  4. 根据权利要求3所述的埋入式位线，其中，所述第一阻挡层的顶部与所述第一位线层的顶部相齐平。
  5. 根据权利要求4所述的埋入式位线，其中，所述第三阻挡层和所述第一位线层之间形成有接触金属层，所述接触金属层和所述第三阻挡层形成欧姆接触。
  6. 根据权利要求3所述的埋入式位线，其中，所述第二阻挡层至少部分形成于所述第二位线层和所述第一阻挡层之间。
  7. 根据权利要求6所述的埋入式位线，其中，所述第一阻挡层的顶部和所述第二阻挡层的顶部均与所述衬底的表面相齐平。
  8. 根据权利要求3至7任一项所述的埋入式位线，其中，所述第二阻挡层和所述第三阻挡层的材料相同。
  9. 一种埋入式位线的形成方法，包括：
    在位线沟槽的内壁上形成第一阻挡层；
    在所述位线沟槽中形成第一位线层，所述第一位线层的顶部低于衬底的表面；
    在所述位线沟槽中形成第二位线层，所述第二位线层连通所述第一位线层和所述衬底内的漏极区。
  10. 根据权利要求9所述的埋入式位线的形成方法，其中，所述在所述位线沟槽中形成第二位线层前，还包括：
    在所述位线沟槽中形成接触金属层，所述接触金属层覆盖所述第一位线层、所述第一阻挡层以及所述位线沟槽的内壁。
  11. 根据权利要求10所述的埋入式位线的形成方法，其中，所述在所述位线沟槽中形成接触金属层前，还包括：
    回刻所述第一阻挡层至预设深度，以使剩余的所述第一阻挡层的顶部与所述第一位线层 的顶部相齐平。
  12. 根据权利要求9所述的埋入式位线的形成方法，其中，所述在所述位线沟槽中形成第二位线层后，还包括：
    对所述衬底进行热处理，以使所述第二位线层和所述接触金属层的接触面以及所述第二位线层和所述衬底的接触面发生反应，反应生成第二阻挡层和第三阻挡层。
  13. 根据权利要求9所述的埋入式位线的形成方法，其中，所述第一阻挡层的顶部与所述衬底的表面相齐平，所述在所述位线沟槽中形成第二位线层前，还包括：
    在所述第一阻挡层的表面形成第二阻挡层。
  14. 根据权利要求13所述的埋入式位线的形成方法，其中，所述在所述位线沟槽中形成第二位线层前，还包括：
    在所述第一位线层的表面形成第三阻挡层。
  15. 根据权利要求9至14任一项所述的埋入式位线的形成方法，其中，所述在所述位线沟槽中形成第一位线层，所述第一位线层的顶部低于衬底的表面，包括：
    在所述位线沟槽中填充位线金属层；
    回刻所述位线金属层至预设深度，剩余的所述位线金属层作为所述第一位线层。
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