WO2022077724A1

WO2022077724A1 - Gate driving circuit and display panel

Info

Publication number: WO2022077724A1
Application number: PCT/CN2020/132778
Authority: WO
Inventors: 刘毅
Original assignee: Tcl华星光电技术有限公司
Priority date: 2020-10-15
Filing date: 2020-11-30
Publication date: 2022-04-21
Also published as: CN112233630B; CN112233630A

Abstract

A gate driving circuit (00) and a display panel. A cycle of a clock signal is (a*T), and a duty cycle thereof is (T-2)/(2*T). A delay time between two adjacent stages of clock signals is a. A falling edge and a rising edge of a signal of a first input end (301) of a first pull-down module respectively pull down a signal of a first output end (302) and a signal of a second output end (303). If k％M is an odd number, a kth-stage gate signal line (20k) is connected to the first output end (302), and the corresponding first input end is connected to a (k％M)th-stage clock signal line.

Description

Gate Drive Circuits and Display Panels

technical field

The present application relates to the field of display technology, in particular to the field of display panel manufacturing technology, and in particular to a gate driving circuit and a display panel.

Background technique

For LCD (Lip1uid Crystal Disp1lay, liquid crystal display) panels, the narrow border technology is used to move the gate drive circuit to the same side of the source drive circuit, and the pull-down circuit is set on the opposite side of the source drive circuit, which can achieve narrow The frame also ensures that the pixel has sufficient charging time.

At present, all pull-down circuits convert the clock signal to obtain the required pull-down signal, and then apply the pull-down signal to the corresponding gate signal to realize the pull-down of the gate signal; however, the existing pull-down circuit can only be applied to For a clock signal with a duty cycle of 50%, for a clock signal with a duty cycle of less than 50%, the rising edge of some clock signals is delayed for a period of time compared to the falling edge of the corresponding gate signal that is pulled down, causing the LCD panel. The gate signal in the middle part cannot be pulled down in time, which reduces the charging time of the corresponding pixel, so that the brightness of the pixels in different regions of the LCD panel varies greatly, which reduces the uniformity of the display screen of the LCD panel.

Therefore, it is necessary to provide a gate driving circuit and a display panel that can improve the charging time of the pixels to improve the uniformity of the display screen of the LCD panel.

technical problem

The embodiments of the present application provide a gate driving circuit and a display panel, wherein the falling edge and the rising edge of the signal at the first input terminal of the first pull-down module pull down the signal at the first output terminal and the signal at the second output terminal respectively. The clock signal with a ratio of (T-2)/(2*T) passes through "If k%M is an odd number, the kth gate signal line is connected to the first output terminal, and the corresponding first input terminal is connected to the (kth) %M) level clock signal line, otherwise, the kth level gate signal line is connected to the second output terminal, and the corresponding first input terminal is connected to the [(k%M)+f+g1*T]th level clock signal line, And [(k%M)+f+g1*T] is an odd number" setting, where M is the total odd number of clock signal lines, T=M, f=(T-2)/2; to solve the problem of existing LCD Some gate signals in the pixel driving circuit of the panel cannot be pulled down in time, which reduces the charging time of the corresponding pixel, so that the brightness of the pixels in different areas of the LCD panel varies greatly.

technical solutions

The embodiments of the present application provide a gate drive circuit, and the gate drive circuit includes:

A multi-level clock signal line, the multi-level clock signal line includes a first-level clock signal line to an M-th level clock signal line, and the first-level clock signal line to the M-th level clock signal line respectively transmits the first level From the clock signal to the M-th stage clock signal, the period of each stage clock signal is (a*T), the duty cycle of each stage clock signal is (T-2)/(2*T), and the adjacent two stages The offset between the clock signals is a, wherein the M is an even number greater than 2, the a is the duration of a unit time period, and the T is the number of a in one cycle of each stage of the clock signal , the T is equal to the M;

A multi-level gate signal line, the multi-level gate signal line includes a first-level gate signal line to an N-th level gate signal line, and the first-level gate signal line to the N-th level gate signal line The lines transmit the gate signal of the first stage to the gate signal of the nth stage respectively, and the gate signal line of the _mth stage and the gate signal line of the (n _m +j*M) stage are both connected to the clock signal line of the _mth stage, and so that the gate signal of the _mth stage and the gate signal of the (n _m +j*M)th stage are respectively synchronized by a corresponding period in the clock signal of the _mth stage of the n mth, wherein the N is an integer not less than the M , the n _m is an integer not less than 1 and not greater than the M, and the j is a positive integer;

A plurality of first pull-down modules, each of the first pull-down modules in the plurality of first pull-down modules includes a first input terminal, a first output terminal and a second output terminal, and the drop of the signal of the first input terminal The edge and the rising edge are respectively used to pull down the signal of the first output end and the signal of the second output end, the first input end is connected to the first-level clock signal line, the first output end and the second output end Connect different two-stage gate signal lines respectively;

Wherein, for the k-th gate signal line in the multi-level gate signal lines:

If k%M is an odd number, the gate signal line of the kth stage is connected to the first output terminal of one of the first pull-down modules, and the first input terminal of the first pull-down module is connected to the (k%Mth) ) level clock signal line, otherwise, the kth level gate signal line is connected to the second output end of one of the first pull-down modules, and the first input end of the first pull-down module is connected to the [(kth %M)+f+g1*T] level clock signal line, wherein, the f is (T-2)/2, the g1 is an integer, the [(k%M)+f+g1*T] is an odd number not less than 1 and not greater than said M; or

If k%M is an even number, the gate signal line of the kth stage is connected to the first output terminal of one of the first pull-down modules, and the first input terminal of the first pull-down module is connected to the (k%Mth) ) level clock signal line, otherwise, the kth level gate signal line is connected to the second output end of one of the first pull-down modules, and the first input end of the first pull-down module is connected to the [(kth %M)+f+g2*T] level clock signal line, wherein the g2 is an integer, and the [(k%M)+f+g2*T] is an even number not less than 1 and not greater than the M .

In one embodiment, each of the first pull-down modules further includes:

A first switch transistor, the first switch transistor is connected to the first input terminal and the second output terminal, and the signal of the first input terminal pulls down the signal of the second output terminal through the first switch transistor.

In one embodiment, the first switching transistor is an N-type transistor, the source of the first switching transistor is connected to the first voltage source, and the gate of the first switching transistor is connected to the corresponding first input terminal, so the The drain of the first switching transistor is connected to the corresponding second output terminal, wherein the first voltage source provides a low voltage or a ground voltage.

In one embodiment, each of the first pull-down modules further includes a first inverter and a second switching transistor;

The first inverter is connected to the first input terminal and the second switching transistor, the first inverter is used to input a first inverted signal to the second switching transistor, and the first inverter is used at any time. The inverted signal and the signal of the first input terminal are the first voltage or the second voltage, and the first inverted signal is different from the signal of the first input terminal at any time;

The second switch transistor is connected to the first output terminal, and the first inverted signal pulls down the signal of the first output terminal through the second switch transistor.

In one embodiment, the second switch transistor is an N-type transistor, the source of the second switch transistor is connected to the first voltage source, and the gate of the second switch transistor is connected to the first inverter The drain of the second switching transistor is connected to the corresponding first output.

In one embodiment, the first switch transistor and the second switch transistor are both N-type transistors, and each first pull-down module further includes:

a first capacitor, two ends of the first capacitor are respectively connected to the drain of the first switching transistor and the output end of the first inverter;

A second capacitor, two ends of the second capacitor are respectively connected to the drain of the second switching transistor and the same line as the signal of the first input terminal.

In one embodiment, the gate driving circuit further includes:

a plurality of second pull-down modules, each of the second pull-down modules in the plurality of second pull-down modules includes a second input terminal and a third output terminal, and the rising edge of the signal of the second input terminal is used to pull down the third output The second input terminal and the third output terminal are respectively connected to the first-level clock signal line and the first-level gate signal line;

Wherein, for the k-th gate signal line in the multi-level gate signal lines:

If k%M is an odd number, the gate signal line of the kth stage is connected to the first output terminal of one of the first pull-down modules, and the first input terminal of the first pull-down module is connected to the (k%Mth) ) level clock signal line, otherwise, the kth level gate signal line is connected to the second output end of one of the first pull-down modules, and the first input end of the first pull-down module is connected to the [(kth %M)+f+g1*T] level clock signal line, or the kth level gate signal line is connected to the third output end of one of the second pull-down modules, and the second input end of the second pull-down module Connect the [(k%M)+f+g1*T] stage clock signal line; or

If k%M is an even number, the gate signal line of the kth stage is connected to the first output terminal of one of the first pull-down modules, and the first input terminal of the first pull-down module is connected to the (k%Mth) ) level clock signal line, otherwise, the kth level gate signal line is connected to the second output end of one of the first pull-down modules, and the first input end of the first pull-down module is connected to the [(kth %M)+f+g2*T] level clock signal line, or the k-th level gate signal line is connected to the third output end of one of the second pull-down modules, and the second input end of the second pull-down module Connect the [(k%M)+f+g2*T]-th stage clock signal line.

In one embodiment, each second pull-down module further includes:

A third switching transistor, the third switching transistor is connected to the second input terminal and the third output terminal, and the signal of the second input terminal pulls down the signal of the third output terminal through the third switching transistor.

In one embodiment, the third switch transistor is an N-type transistor, and each second pull-down module further includes:

A third capacitor, two ends of the third capacitor are respectively connected to the drain of the third switching transistor and the inverted signal of the signal of the second input terminal, and the inverted signal of the signal of the second input terminal and the The signal at the gate of the third switching transistor is opposite.

In one embodiment, some of the first pull-down modules in the plurality of first pull-down modules further include an inverting terminal, and the part of the first pull-down modules and the plurality of second pull-down modules are in one-to-one correspondence, and any The signal of the inverting terminal and the signal of the corresponding second input terminal of the second pull-down module at any time are the third voltage or the fourth voltage, and the signal of the inverting terminal and the second input terminal of the corresponding second pull-down module at any time. different signals;

Wherein, the signal of the second input terminal of the second pull-down module is the same as the signal of the corresponding first input terminal of the first pull-down module.

In one embodiment, the gate driving circuit further includes:

a plurality of third pull-down modules, each of the third pull-down modules in the plurality of third pull-down modules includes a third input terminal and a fourth output terminal, and the falling edge of the signal of the third input terminal is used to pull down the fourth output The third input terminal and the fourth output terminal are respectively connected to the first-level clock signal line and the first-level gate signal line;

Wherein, for the k-th gate signal line in the multi-level gate signal lines:

If k%M is an odd number, the gate signal line of the kth stage is connected to the first output terminal of one of the first pull-down modules, and the first input terminal of the first pull-down module is connected to the (k%Mth) ) level clock signal line, or the kth level gate signal line is connected to the fourth output terminal of one of the third pull-down modules, and the third input terminal of the third pull-down module is connected to the (k%M)th level clock signal line, otherwise, the k-th gate signal line is connected to the second output terminal of one of the first pull-down modules, and the first input terminal of the first pull-down module is connected to the [(k%M)th +f+g1*T] class clock signal line; or

If k%M is an even number, the gate signal line of the kth stage is connected to the first output terminal of one of the first pull-down modules, and the first input terminal of the first pull-down module is connected to the (k%Mth) ) level clock signal line, or the kth level gate signal line is connected to the fourth output terminal of one of the third pull-down modules, and the third input terminal of the third pull-down module is connected to the (k%M)th level clock signal line, otherwise, the k-th gate signal line is connected to the second output end of one of the first pull-down modules, and the first input end of the first pull-down module is connected to [(k%M)+ f+g2*T] level clock signal line.

In one embodiment, each of the third pull-down modules further includes a second inverter and a fourth switch transistor;

The second inverter is connected to the third input terminal and the fourth switching transistor, and the second inverter is used to input a second inverted signal to the fourth switching transistor, and the second inverter is used at any time. The inverted signal and the signal of the third input terminal are the fifth voltage or the sixth voltage, and the second inverted signal is different from the signal of the third input terminal at any time;

The fourth switch transistor is connected to the fourth output terminal, and the second inverted signal pulls down the signal of the fourth output terminal through the fourth switch transistor.

In one embodiment, the fourth switch transistor is an N-type transistor, and each third pull-down module further includes:

a fourth capacitor, the two ends of the fourth capacitor are respectively connected to the drain of the fourth switch transistor and the same line as the signal of the third input terminal, and the signal of the third input terminal is connected to the fourth switch The gate of the transistor has the opposite signal.

In one embodiment, the gate driving circuit further includes:

A multi-stage conversion module, the multi-stage conversion module includes a first-stage conversion module to an N-th stage conversion module, the first-stage conversion module to the N-th conversion module and the first-stage gate signal line respectively There is a one-to-one correspondence with the gate signal lines of the Nth stage, and the two ends of each conversion module from the first stage conversion module to the Nth stage conversion module are respectively connected to the corresponding gate signal line and the corresponding clock signal. line, the first-stage conversion module to the N-th stage conversion module are respectively used to convert the clock signal transmitted in the corresponding clock signal line into the corresponding gate signal and transmit the corresponding gate signal to the corresponding gate signal pole signal line.

In one embodiment, the M is 8 or 12.

The embodiment of the present application further provides a display panel, the display panel includes a gate driving circuit, the display panel further includes a display area, a first area and a second area, the first area and the second area are disposed opposite to each other, The display area is located between the first area and the second area, the multi-level clock signal lines and the multi-level gate signal lines are located in the first area of the display area, the plurality of The first pull-down module is located in the second area of the display area, and the gate driving circuit includes:

A multi-level gate signal line, the multi-level gate signal line includes a first-level gate signal line to an N-th level gate signal line, and the first-level gate signal line to the N-th level gate signal line The lines transmit the gate signal of the first stage to the gate signal of the Nth stage respectively, and the gate signal line of the nmth stage and the gate signal line of the (nm+j*M)th stage are both connected to the clock signal line of the nmth stage, so that the nmth stage The stage gate signal and the (nm+j*M)th stage gate signal are respectively synchronized by a corresponding period in the nmth stage clock signal, wherein the N is an integer not less than the M, and the nm is not less than an integer less than 1 and not greater than the M, and the j is a positive integer;

Wherein, for the k-th gate signal line in the multi-level gate signal lines:

If k%M is an even number, the gate signal line of the kth stage is connected to the first output terminal of one of the first pull-down modules, and the first input terminal of the first pull-down module is connected to the (k%Mth) ) level clock signal line, otherwise, the kth level gate signal line is connected to the second output end of one of the first pull-down modules, and the first input end of the first pull-down module is connected to the [(kth %M)+f+g2*T] level clock signal line, wherein the g2 is an integer, and the [(k%M)+f+g2*T] is an even number not less than 1 and not greater than the M ;

multi-level first gate connection lines, the multi-level first gate connection lines and the multi-level gate signal lines are in one-to-one correspondence, the multi-level first gate connection lines pass through the display area, the multi-level first gate connection lines Two ends of each level of the first gate connecting lines in the multi-level first gate connecting lines are respectively connected to the corresponding gate signal lines and the corresponding first pull-down modules, so as to electrically connect the corresponding gate signal lines and the corresponding first pull-down modules. The first drop-down module.

In an embodiment, some of the clock signal lines in the multi-level clock signal lines are connected to the plurality of first pull-down modules, and the gate driving circuit further includes:

A multi-level pull-down connection line, the multi-level pull-down connection line is located in the second area, the multi-level pull-down connection line is in one-to-one correspondence with the partial clock signal lines, and each level of the multi-level pull-down connection line is pulled down The connecting line connects the corresponding first-level clock signal line and the corresponding at least one first pull-down module.

In one embodiment, the display panel further includes a plurality of pixel driving units, the plurality of pixel driving units are arrayed in the display area, and the gate driving circuit further includes:

multi-level second gate connection lines, the multi-level second gate connection lines and the multi-level first gate connection lines are arranged to intersect, the multi-level second gate connection lines and the multi-level first gate connection lines The gate connection lines are in one-to-one correspondence, and each level of the second gate connection lines in the multi-level second gate connection lines is connected to a corresponding row or column of pixel driving units;

A plurality of connection points, a connection point is provided at the intersection of each level of the second gate connection line and the corresponding first gate connection line in the multi-level second gate connection lines, and the plurality of connection points are The corresponding first gate connection line and the corresponding second gate connection line are electrically connected.

In one embodiment, the gate driving circuit further includes:

Wherein, for the k-th gate signal line in the multi-level gate signal lines:

In one embodiment, the gate driving circuit further includes:

Wherein, for the k-th gate signal line in the multi-level gate signal lines:

beneficial effect

The present application provides a gate driving circuit and a display panel, including an M-level clock signal line, an N-level gate signal line, and a plurality of first pull-down modules. The period of the clock signal is (a*T) and the duty cycle is ( T-2)/(2*T), the delay time of the adjacent two-stage clock signals is a, and the gate signal lines of the n _mth and (n _m +j*M) stages are respectively separated by the n _mth stage clock signal lines. The corresponding one cycle synchronization, the falling edge and rising edge of the signal at the first input end of the first pull-down module pull down the signal at its first output end and the signal at its second output end respectively. For the k-th gate signal line, this scheme Through "If k%M is an odd number, the k-th gate signal line is connected to the first output terminal, and the corresponding first input terminal is connected to the (k%M)-th stage clock signal line, otherwise, the k-th stage gate signal line The line is connected to the second output terminal, the corresponding first input terminal is connected to the [(k%M)+f+g1*T] stage clock signal line, and [(k%M)+f+g1*T] is an odd number” In the timing diagram, the falling edge of the gate signal G(m) of the (m+8*i) stage corresponds to the rising edge of the inverted clock signal XCK(m) of the mth stage, and the (m- 3+8*i) The falling edge of the gate signal G(m) corresponds to the rising edge of the m-th stage clock signal CK(m). Therefore, the multi-level clock signal in this scheme can promote the multi-level signal Pull down to shorten the falling time of the multi-level gate signal, thereby improving the charging time of the pixel and improving the uniformity of the display screen of the display panel.

Description of drawings

The present invention will be further described below with reference to the accompanying drawings. It should be noted that the accompanying drawings in the following description are only used to explain some embodiments of the present invention, and for those skilled in the art, without creative efforts, other Attached.

FIG. 1 is a circuit diagram of a gate drive circuit provided by an embodiment of the present application;

FIG. 2 is a circuit diagram of another gate driving circuit provided by an embodiment of the present application;

FIG. 3 is a circuit diagram of another gate driving circuit provided by an embodiment of the present application;

FIG. 4 is a timing diagram of some signals in the gate driving circuit provided by the embodiment of the present application;

5 is a circuit diagram of a first pull-down module provided by an embodiment of the present application;

6 is a circuit diagram of a second pull-down module provided by an embodiment of the present application;

7 is a circuit diagram of a third pull-down module provided by an embodiment of the present application;

FIG. 8 is a structural diagram of a display panel provided by an embodiment of the present application;

FIG. 9 is a structural diagram of another display panel according to an embodiment of the present application.

Embodiments of the present invention

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, but not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the protection scope of the present application.

The terms "first", "second", "third", and "fourth" in this application are used to distinguish different objects, rather than to describe a specific order. Furthermore, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device comprising a series of steps or modules is not limited to the listed steps or modules, but optionally also includes unlisted steps or modules, or optionally also includes Other steps or modules inherent to these processes, methods, products or devices.

Reference herein to an "embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the present application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor a separate or alternative embodiment that is mutually exclusive of other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

The embodiments of the present application provide a gate driving circuit, and the gate driving circuit includes but is not limited to the following embodiments and combinations of the following embodiments.

In one embodiment, as shown in FIG. 1 , the gate driving circuit 00 includes:

A multi-level clock signal line 10, the multi-level clock signal line 10 includes a first-level clock signal line 101 to an M-th level clock signal line 10M, and the first-level clock signal line 101 to the M-th level clock signal line 10M transmits the first-level clock signal to the M-th level clock signal respectively, the period of each level clock signal is (a*T), and the duty cycle of each level clock signal is (T-2)/(2*T) , the offset between adjacent two-stage clock signals is a, wherein the M is an even number greater than 2, the a is the duration of a unit time period, and the T is one cycle of each stage of the clock signal The number of a described in, the T is equal to the M;

A multi-level gate signal line 20, the multi-level gate signal line 20 includes a first-level gate signal line 201 to an N-th level gate signal line 20N, and the first-level gate signal line 201 to the nth level gate signal line 201 The N-stage gate signal line 20N transmits the first-stage gate signal to the N-th stage gate signal respectively, the n-th _m -stage gate signal line 20n and the (n _m +j*M)-th stage gate signal line 20(n _m +j*M) are all connected to the n _mth stage clock signal line 10nm , so that the _{n mth} _stage gate signal and the (nm +j*M)th stage gate signal are respectively corresponding to the _{n mth} _stage clock signal One cycle synchronization of , wherein, the N is an integer not less than the M, the n _m is an integer not less than 1 and not greater than the M, and the j is a positive integer;

A plurality of first pull-down modules, each of the first pull-down modules in the plurality of first pull-down modules includes a first input end 301, a first output end 302 and a second output end 303, the first input end The falling edge and the rising edge of the signal of 301 are used to pull down the signal of the first output terminal 302 and the signal of the second output terminal 303 respectively. The first input terminal 301 is connected to the first-level clock signal line, and the first An output end 302 and the second output end 303 are respectively connected to different two-stage gate signal lines;

Wherein, for the k-th gate signal line 20k in the multi-level gate signal lines 20:

If k%M is an odd number, the k-th stage gate signal line 20k is connected to the first output terminal 302 of one of the first pull-down modules, and the first input terminal 301 of the first pull-down module is connected to the ( k%M) level clock signal line 10 (k%M), otherwise, the k-th level gate signal line 20k is connected to the second output end 303 of one of the first pull-down modules, and the first pull-down module The first input end 301 of the module is connected to the [(k%M)+f+g1*T]-th stage clock signal line 10[(k%M)+f+g1*T], where the f is (T- 2)/2, the g1 is an integer, and the [(k%M)+f+g1*T] is an odd number not less than 1 and not greater than the M; or

If k%M is an even number, the gate signal line of the k-th stage is connected to the first output terminal 302 of one of the first pull-down modules, and the first input terminal 301 of the first pull-down module is connected to the first output terminal 301 of the first pull-down module. (k%M)-level clock signal line 10 (k%M), otherwise, the k-th level gate signal line 20k is connected to the second output end 303 of one of the first pull-down modules, and the first pull-down module The first input end 301 of the pull module is connected to the [(k%M)+f+g2*T]th stage clock signal line 10[(k%M)+f+g2*T], wherein the g2 is an integer, The [(k%M)+f+g2*T] is an even number not less than 1 and not greater than the M.

It can be understood that the total number of stages M of the multi-stage clock signal lines, the number T of the unit duration a in each cycle of each stage of the clock signal, and the duty cycle of each stage of the clock signal have the following relationship: For example, when When the total number of stages M=T=8, the duty cycle of the clock signal of each stage is (T-2)/(2*T)=3/8, and for example, when the total number of stages M=T=12, each The duty ratio of the first-level clock signal is (T-2)/(2*T)=5/12, that is, this embodiment is mainly aimed at the clock signal whose duty ratio is not equal to 50%.

It should be noted that, as shown in FIG. 1 , the gate driving circuit 00 further includes: a multi-stage conversion module, the multi-stage conversion module includes a first-stage conversion module 01 to an N-th stage conversion module ON, the The first-stage conversion module 01 to the N-th stage conversion module ON are in one-to-one correspondence with the first-stage gate signal lines 201 to the N-th stage gate signal line 20N, and the first-stage conversion modules 01 to The two ends of each conversion module in the N-th level conversion module ON are respectively connected to the corresponding gate signal line and the corresponding clock signal line, and the first-level conversion module 01 to the N-th level conversion module ON are respectively used for It is used to convert the clock signal transmitted in the corresponding clock signal line into the corresponding gate signal and transmit the corresponding gate signal to the corresponding gate signal line. For example, an n-th stage conversion module On is provided between the n-th stage clock signal line 10n and the n-th stage gate signal line 20n, and the n-th stage conversion module On makes the n-th stage gate signal One of the cycles of the n-stage clock signals is synchronized, that is, the n-th stage gate signal is a signal in one of the cycles of the n-th stage clock signal, wherein the n is not less than 1 and not greater than the N the integer. Wherein, the high voltage in the nth stage gate signal may be equal to the high voltage in the corresponding period of the nth stage clock signal, but the low voltage in the nth stage gate signal may be greater than the Therefore, the multi-level gate signal can be pulled down by the multi-level clock signal.

Further, as shown in FIG. 1 , since the first input terminal 301 is connected to the primary clock signal line, that is, the signal of the first input terminal 301 is the same as the clock signal transmitted in the corresponding clock signal line. For example, the first input terminal 301 of the first pull-down module on the right in FIG. 1 is connected to the first-stage clock signal line 101 , that is, the signal of the first input terminal 301 of the first pull-down module on the right side and the first-stage clock The signal is the same.

Wherein, as shown in Figure 2-3, M=T=8 is taken as an example for description here. Specifically, the multi-level clock signal line 10 includes the first-level clock signal line 101 to the eighth-level clock signal line 108 , and the multi-level gate signal line 20 includes the first-level gate signal line 201 to the Nth level. The gate signal line 20N, the n _mth stage gate signal line 20n _m and the (n _m +8*j)th stage gate signal line 20(n _m +8*j) are all connected to the n _mth stage clock signal line 10n _m , so that the gate signal of the _m -th stage and the gate signal of the (n _m +8*j)-th stage are both synchronized by one of the periods of the clock signal of the _m -th stage of the n m , wherein the n _m can be taken over not less than 1 and not greater than all integers of the M, the j can take all positive integers. For example, taking _nm = 1, it means that the gate signal lines 201 of the first stage, the gate signal lines 209 of the ninth stage, and the gate signal lines of the seventeenth stage, the number of which is increased by 8, respectively pass through the corresponding gate signal lines. The conversion modules are all connected to the first-level clock signal line 101; taking _nm = 2, it means that the second-level gate signal line 202, the tenth-level gate signal line 2010, and the eighteenth-level gate signal line have an increment of 8. The multi-level gate signal lines are respectively connected to the second-level clock signal lines 102 through corresponding conversion modules.

It can be understood that the arrangement order of the multi-level gate signal lines in the embodiment of FIGS. 2-3 is different from the arrangement order of the multi-level gate signal lines in the embodiment of FIG. The connection between the first pull-down module and the first pull-down module, the multi-stage gate signal lines are arranged according to the principle of proximity, and the two-stage gate signal lines that can share the same first pull-down module are arranged adjacent to each other. , effectively avoiding the problem that the lines of the multi-level gate signal lines are set longer or more bent, so that the lines are short-circuited or the signals in the lines interfere with each other.

In one embodiment, as shown in FIGS. 1-3 , a display area 000 may be set between the plurality of first pull-down modules and the multi-level clock signal lines 10 , which is used here to indicate the display area The relative positional relationship between 000 and the gate driving circuit 00 does not indicate the relative size relationship between the display area 000 and the gate driving circuit 00 . Of course, the above embodiments are not limited to the display area 000 being located between the plurality of first pull-down modules and the multi-level clock signal lines 10. For example, the display area 000 may also be located in the A side of the plurality of first pull-down modules away from the multi-level clock signal line 10 or a side of the multi-level clock signal line 10 away from the plurality of first pull-down modules. It can be understood that the display area 000 may be provided with a light-emitting layer or a liquid crystal layer, and the light-emitting layer or the liquid crystal layer may be controlled by the gate driving circuit 00 and other circuits to perform screen display.

Wherein, as shown in FIG. 4 , the first-level clock signal line 101 to the eighth-level clock signal line 108 transmit the first-level clock signal CK(1) to the eighth-level clock signal CK(8) respectively, and each The period of the one-stage clock signal is 8a, the duty cycle of each stage's clock signal is 3/8, and the offset between two adjacent two-stage clock signals is a. For example, the third-stage clock signal CK(3) is delayed by a from the second-stage clock signal CK(2), and the second-stage clock signal CK(2) is delayed by a from the first-stage clock signal CK(1). It can be understood that, since a is the duration of a unit time period, each cycle of each stage of the clock signal may sequentially include a first high voltage with a duration of (3*a) and a first high voltage with a duration of (5*a). Two low voltage.

Further, the gate signal line 20n _m of the n _mth stage and the gate signal line 20 of the (n _m +8*j) stage (n _m +8*j) the multi-level gate signal lines of which the number of levels is incremented by 8 pass through respectively. The corresponding n _m th conversion modules 0nm are all connected to the _n _m th stage clock signal lines 10nm , so as to be synchronized by corresponding periods in the _n _m _th stage clock signal CK(nm ). Specifically, when n _m is any integer not less than 1 and not greater than 8, and j is any positive integer, the gate signal G(n _m ) of the n _mth stage is converted by the _{n mth} _stage through the corresponding conversion module 0nm The first cycle in the clock signal CK(n _m ) is synchronized, and the gate signal G(n _m +8*j) of the (n _m +8*j) stage passes through the corresponding conversion module 0(n _m +8*j) Synchronized by the (j+1)th cycle in the n-th stage clock signal CK(n _m ); it can be seen that the corresponding clock signal CK(n _m ) selected by any conversion module 0(n _m +8* _j ) The ordinal number of the cycle being synchronized in is related to the j. As shown in FIG. 4 , where m is an integer not less than 1 and not greater than 8, for example, the gate signal G(m) of the mth stage can be synchronized by one of the periods t1 in the clock signal CK(m) of the mth stage, and the For example, the (m+1)th stage gate signal G(m+1) can be synchronized by one of the periods t2 in the (m+1)th stage clock signal CK(m+1), wherein the period t2 is delayed by a from the period t1 , the (m+8)th stage gate signal G(m+8) can be synchronized by one of the periods t3 in the mth stage clock signal CK(m), wherein the period t3 in the mth stage clock signal CK(m) is a period after period t1.

Further, as shown in FIG. 4 , at any time, the sum of the inverted clock signal XCK(m) of the mth stage clock signal CK(m) and the mth stage clock signal CK(m) is a constant value, and The voltages of the inverted clock signal XCK(m) and the m-th stage clock signal CK(m) are different. For example, in any cycle, one cycle of the m-th stage clock signal CK(m) may sequentially include continuous The first high voltage with a duration of (3*a) and the second low voltage with a duration of (5*a), on the contrary, within one cycle of the m-th inversion clock signal XCK(m) The second low voltage having a duration of (3*a) and the first high voltage having a duration of (5*a) are sequentially included.

It should be noted that, as shown in FIG. 4 , when the m is an integer greater than 3 and not greater than 8, the (mth) can be obtained according to the above-mentioned rules for synchronizing the multi-level gate signals with the multi-level clock signals. The timing chart of the +5) stage gate signal G(m+5) and the (m-3)th stage gate signal G(m-3). Among them, the falling edge of the mth stage gate signal G(m) corresponds to the rising edge of the mth stage inversion clock signal XCK(m), and the (m+5)th stage gate signal G(m+5) and The falling edge of the gate signal G(m-3) of the (m-3) stage corresponds to the rising edge of the clock signal CK(m) of the mth stage; further, since the clock signals of each stage are periodic signals, that is, the The falling edge of the (m+8*i1) stage gate signal G(m) also corresponds to the rising edge of the mth stage inverted clock signal XCK(m), and the (m-3+8*i2) stage gate signal The falling edge of G(m) also corresponds to the rising edge of the m-th clock signal CK(m), wherein the i1 and the i2 are both integers not less than 0, and the i1 and the i2 may be equal Or not equal; therefore, the m-th inversion clock signal XCK(m) can pull down the (m+8*i1)-th gate signal G(m+8*i1), and the m-th stage clock signal CK(m) The gate signal G(m-3+8*i2) of the (m-3+8*i2)th stage can be pulled low.

It can be understood that in each first pull-down module, the falling edge and the rising edge of the signal of the first input terminal 301 are used to pull down the signal of the first output terminal 302 and the second output terminal 303 respectively. , wherein the falling edge of the signal of the first input terminal 301 is used to pull down the signal of the first output terminal 302 specifically: the rising edge of the inverted signal corresponding to the signal of the first input terminal 301 is used to pull down the signal the signal of the first output terminal 302 . According to the above analysis, if the m-th stage clock signal line 10m is connected to the first input terminal 301, the signal of the first input terminal 301 is CK(m), and the corresponding inverted signal is XCK(m) , that is, the rising edge of the inverted signal XCK(m) corresponding to the signal of the first input terminal 301 can pull down the signal of the first output terminal 302 and the signal CK(m) of the first input terminal 301 The rising edge can pull down the signal of the second output terminal 303. Therefore, in the same first pull-down module, the first output terminal 302 can be connected to the (m+8*i1)-th gate signal line 20 (m +8*i1), and the second output terminal 303 can be connected to the (m-3+8*i2)-th gate signal line 20 (m-3+8*i2).

Therefore, for any first pull-down module, the first input terminal 301 is connected to the m-th clock signal line 10m, and the first output terminal 302 and the second output terminal 303 can be respectively connected to the (m-th level) +8*i1) stage gate signal line 20 (m+8*i1) and (m-3+8*i2) th stage gate signal line 20 (m-3+8*i2).

On the one hand, all clock signal lines with an odd number of stages can be selected as pull-down signals. As shown in FIG. 2 , for example, when the first input terminal 301 is connected to the first-stage clock signal line 101 , the first output terminal 302 and the second output terminal 303 can be respectively connected to the (1+8*i1 ) level gate signal line 20 (1+8*i1) and the (-2+8*i2)-th level gate signal line 20 (-2+8*i2); for another example, the first input end 301 is connected to When the third-stage clock signal line 103 is used, the first output terminal 302 and the second output terminal 303 can be connected to the (3+8*i1)-th stage gate signal line 20 (3+8*i1) and the third-stage gate signal line 20 (3+8*i1), respectively. (8*i2) level gate signal line 20 (8*i2); for another example, when the first input end 301 is connected to the fifth level clock signal line 105, the first output end 302 and the second output end The terminals 303 can be respectively connected to the (5+8*i1)-th stage gate signal line 20 (5+8*i1) and the (2+8*i2)-th stage gate signal line 20 (2+8*i2).

Further, on the basis of taking M=T=8 as an example, here should be based on "If k%M is an odd number, the k-th gate signal line 20k is connected to the first pull-down module of one of the first pull-down modules. An output terminal 302'' is connected in a related connection manner.

As shown in FIG. 2, for the first-level gate signal line 201, where k=1, k%M=1, that is, k%M is an odd number, the first-level gate signal line 201 is connected to one of them The first output terminal 302 of the first pull-down module, and the first input terminal 301 of the first pull-down module is connected to the first-level clock signal line 101; for the same reason, for example, the third-level gate signal line 203 is connected to one of them The first output terminal 302 of the first pull-down module, and the first input terminal 301 of the first pull-down module is connected to the third-level clock signal line 103; for example, the fifth-level gate signal line 205 is connected to one of the first The first output terminal 302 of the pull-down module, and the first input terminal 301 of the first pull-down module is connected to the fifth-level clock signal line 105; for example, the ninth-level gate signal line 209 is connected to one of the first pull-down The first output terminal 302 of the module, and the first input terminal 301 of the first pull-down module is connected to the first-level clock signal line 101 .

As shown in FIG. 2, for the second-level gate signal line 201, k=2, k%M=2, that is, k%M is an even number, and f=(T-2)/2=3, because [(k%M)+f+g1*T] is an odd number not less than 1 and not greater than the M, and the g1 is an integer, that is, [(k%M)+f+g1*T]=5, then The second-level gate signal line 202 is connected to the second output terminal 303 of one of the first pull-down modules, and the first input terminal 301 of the first pull-down module is connected to the fifth-level clock signal line 105; the same is true For example, the gate signal line 204 of the fourth stage is connected to the second output terminal 303 of one of the first pull-down modules, and the first input terminal 301 of the first pull-down module is connected to the clock signal line 107 of the seventh stage; The stage gate signal line 206 is connected to the second output terminal 303 of one of the first pull-down modules, and the first input terminal 301 of the first pull-down module is connected to the first stage clock signal line 101; for example, the tenth stage gate The pole signal line 2010 is connected to the second output terminal 303 of one of the first pull-down modules, and the first input terminal 301 of the first pull-down module is connected to the fifth-level clock signal line 105 .

On the other hand, all clock signal lines with an even number of stages can be selected as pull-down signals. As shown in FIG. 3 , for example, the first input terminal 301 is connected to the second-level clock signal line 102 , and the first output terminal 302 and the second output terminal 303 can be connected to the (2+8*i1) stage gate signal line 20 (2+8*i1) and (-1+8*i2) stage gate signal line 20 (-1+8*i2); for another example, the first input end 301 is connected to the first stage gate signal line 20 (-1+8*i2); The 4-stage clock signal line 104, the first output terminal 302 and the second output terminal 303 can be connected to the (4+8*i1)th stage gate signal line 20 (4+8*i1) and the (1st +8*i2) level gate signal line 20 (1+8*i2); for another example, the first input end 301 is connected to the sixth level clock signal line 106, the first output end 302 and the second The output terminals 303 can be respectively connected to the (6+8*i1)-th stage gate signal line 20 (6+8*i1) and the (3+8*i2)-th stage gate signal line 20 (3+8*i2).

In the same way, on the basis of taking M=T=8 as an example, here it is based on “If k%M is an even number, the k-th gate signal line 20k is connected to the first pull-down module of one of the first pull-down modules. The output terminal 302" is connected by the relevant wiring method.

As shown in FIG. 3 , for the second-level gate signal line 201, where k=2, k%M=2, that is, k%M is an even number, the second-level gate signal line 202 is connected to one of them The first output terminal 302 of the first pull-down module, and the first input terminal 301 of the first pull-down module is connected to the second-level clock signal line 102; similarly, for example, the fourth-level gate signal line 204 is connected to one of the The first output terminal 302 of the first pull-down module, and the first input terminal 301 of the first pull-down module is connected to the fourth-level clock signal line 104; for example, the sixth-level gate signal line 206 is connected to one of the first The first output terminal 302 of the pull-down module, and the first input terminal 301 of the first pull-down module is connected to the sixth-level clock signal line 106; for example, the tenth-level gate signal line 2010 is connected to one of the first pull-down The first output terminal 302 of the module, and the first input terminal 301 of the first pull-down module is connected to the second-level clock signal line 102 .

As shown in FIG. 3, for the first-level gate signal line 201, k=1, k%M=1, that is, k%M is an odd number, and f=(T-2)/2=3, because [(k%M)+f+g2*T] is an odd number not less than 1 and not greater than the M, and the g2 is an integer, that is, [(k%M)+f+g2*T]=4, then The first-level gate signal line 201 is connected to the second output terminal 303 of one of the first pull-down modules, and the first input terminal 301 of the first pull-down module is connected to the fourth-level clock signal line 104; the same is true For example, the gate signal line 203 of the third stage is connected to the second output terminal 303 of one of the first pull-down modules, and the first input terminal 301 of the first pull-down module is connected to the clock signal line 106 of the sixth stage; The stage gate signal line 205 is connected to the second output terminal 303 of one of the first pull-down modules, and the first input terminal 301 of the first pull-down module is connected to the eighth stage clock signal line 108; for example, the ninth stage gate The pole signal line 209 is connected to the second output terminal 303 of one of the first pull-down modules, and the first input terminal 301 of the first pull-down module is connected to the fourth-level clock signal line 104 .

To sum up, when the duty cycle of the multi-stage clock signal is (T-2)/(2*T), no matter selecting all the clock signal lines with odd number of stages as pull-down signals or selecting all stages as The even-numbered clock signal lines are used as pull-down signals, and the multi-level gate signals can be pulled down by the corresponding clock signals according to the connection method. Therefore, the above embodiment can realize that when the duty cycle of the multi-level clock signals is not equal to 50% , the multi-level gate signal is pulled down in time, which shortens the falling time of the multi-level gate signal, improves the charging time of the corresponding pixel, and improves the uniformity of the display screen of the display panel.

In an embodiment, as shown in FIG. 5 , each of the first pull-down modules further includes: a first switch transistor 304, the first switch transistor 304 is connected to the first input terminal 301 and the second output terminal 303 , the signal of the first input terminal 301 pulls down the signal of the second output terminal 303 through the first switching transistor 304 .

Specifically, as shown in FIG. 5 , the first switch transistor 304 may be an N-type transistor, the source of the first switch transistor 304 is connected to the first voltage source 02 , and the gate of the first switch transistor 304 is connected to Corresponding to the first input terminal 301, the drain of the first switching transistor 304 is connected to the corresponding second output terminal 303, wherein the first voltage source 02 provides a low voltage or a ground voltage. It can be known from the switching characteristics of the N-type transistor that when the source is connected to a low voltage or a ground voltage, and a higher voltage is applied to the gate, the N-type transistor is turned on, and the voltage of the drain is pulled down by the voltage of the source. Therefore, according to the above analysis, when m>3, if the first input terminal 301 is connected to the m-th clock signal line 10m, and the second output terminal 303 is connected to (m-3+8*i) stage gate signal line 20(m-3+8*i), the rising edge of the mth stage clock signal CK(m) can pull down the (m-3+8*i)th stage gate signal G(m- 3+8*i), in order to shorten the falling time of the gate signal G(m-3+8*i) of the (m-3+8*i) stage, improve the charging time of the corresponding pixel, and improve the display panel’s performance. The uniformity of the displayed picture, wherein the i is an integer not less than 0.

In an embodiment, as shown in FIG. 5 , each first pull-down module further includes a first inverter 305 and a second switching transistor 306 ; the first inverter 305 is connected to the first input terminal 301 and the second switch transistor 306, the first inverter 305 is used to input a first inversion signal to the second switch transistor 306, the first inversion signal and the first input terminal at any time The signal of 301 is the first voltage or the second voltage, and the first inverted signal is different from the signal of the first input terminal 301 at any time; the second switching transistor 306 is connected to the first output terminal 302 , the first inversion signal pulls down the signal of the first output terminal 302 through the second switch transistor 306 .

Specifically, as shown in FIG. 5 , the first inverter 305 includes four N-type transistors, the source of each N-type transistor is connected to the first voltage source 02 , and the drain of each N-type transistor is connected to the first voltage source 02 . The second voltage source 03 is connected, and the second voltage source 03 provides a high voltage. According to the relevant characteristics of the N-type transistor, the signal at the input end and the signal at the output end of the first inverter 305 satisfy the signal at any time when the signal is different. the first voltage and the second voltage; further, the second switch transistor 306 may also be an N-type transistor, the source of the second switch transistor 306 is connected to the first voltage source 02, the The gates of the two switching transistors 306 are connected to the output terminal of the first inverter 305, and the drains of the second switching transistors 306 are connected to the corresponding first output terminal 302. Similarly, when the first inverter The input terminal of 305 is connected to the first input terminal 301 to connect to the m-th stage clock signal line 10m, and the first output terminal 302 is connected to the (m+8*i)-th stage gate signal line 20 (m+ 8*i), the falling edge of the mth stage clock signal CK(m) can pull down the (mth stage) through the rising edge of the mth stage inverted clock signal XCK(m) generated by the first inverter 305 +8*i) level gate signal G(m+8*i), to shorten the falling time of the (m+8*i)-th level gate signal G(m+8*i), and improve the charging of the corresponding pixel time, improving the uniformity of the display screen of the display panel.

Further, each first pull-down module further includes a first capacitor 307 and a second capacitor 308, two ends of the first capacitor 307 are respectively connected to the drain of the first switching transistor 304 and the first inverting The two ends of the second capacitor 308 are respectively connected to the drain of the second switching transistor 306 and the same line as the signal of the first input terminal 301 . It can be understood that the signal at the output end of the first inverter 305 and the signal at the gate of the second switching transistor 306 are mutually inverse signals, and the signal at the first input end 301 is the same as the signal at the first input end 301. The signals of the gates of the two switching transistors 306 are mutually inverse signals. Therefore, the first capacitor 307 and the second capacitor 308 can solve the capacitive coupling of the first switching transistor 304 and the capacitive coupling of the second switching transistor 306 respectively. The corresponding gate signal distortion problem caused by capacitive coupling.

In one embodiment, as shown in FIG. 6 , the gate driving circuit 00 further includes:

A plurality of second pull-down modules, each of the plurality of second pull-down modules includes a second input end 401 and a third output end 402, and the rising edge of the signal of the second input end 401 is used to pull down all the second pull-down modules. The signal of the third output terminal 402, the second input terminal 401 and the third output terminal 402 are respectively connected to the first-level clock signal line and the first-level gate signal line;

Wherein, for the k-th gate signal line in the multi-level gate signal lines:

If k%M is an odd number, the gate signal line of the k-th stage is connected to the first output terminal 302 of one of the first pull-down modules, and the first input terminal 301 of the first pull-down module is connected to the (k-th stage) %M) level clock signal line, otherwise, the k-th level gate signal line is connected to the second output end 303 of one of the first pull-down modules, and the first input end 301 of the first pull-down module is connected to [(k%M)+f+g1*T]-th stage clock signal line, or the k-th stage gate signal line is connected to the third output terminal 402 of one of the second pull-down modules, and the second pull-down module The second input terminal 401 of the is connected to the [(k%M)+f+g1*T]-th stage clock signal line; or

If k%M is an even number, the gate signal line of the k-th stage is connected to the first output terminal 302 of one of the first pull-down modules, and the first input terminal 301 of the first pull-down module is connected to the (k-th stage) %M) level clock signal line, otherwise, the kth level gate signal line is connected to the second output end 402 of one of the first pull-down modules, and the first input end 401 of the first pull-down module is connected to [(k%M)+f+g2*T]-th stage clock signal line, or the k-th stage gate signal line is connected to the third output terminal 402 of one of the second pull-down modules, and the second pull-down module The second input terminal 401 of the [(k%M)+f+g2*T]th stage clock signal line is connected.

It should be noted that the difference between this embodiment and the embodiments in FIGS. 2-3 above is that this embodiment includes the second pull-down module in addition to the first pull-down module, and in each In the second pull-down module, the rising edge of the signal of the second input terminal 401 is used to pull down the signal of the third output terminal 402, that is, each of the second pull-down modules is only used to pull down the corresponding first-level gate. Further, it can be seen from Figure 4 that when m>3, the falling edge of the gate signal G(m-3+8*i) of the (m-3+8*i) stage and the clock signal of the mth stage The rising edge of CK(m) corresponds to, and according to the function of the second pull-down module, that is, the m-th stage clock signal CK(m) can pull down the (m-3+8*i)-th stage gate signal G(m-3 +8*i), so for any second pull-down module, the second input terminal 401 is connected to the mth level clock signal line 10m, and the third output terminal 402 can be connected to the (m-3+8*th level) i) Stage gate signal line.

In one embodiment, as shown in FIG. 6 , each second pull-down module further includes: a third switch transistor 403 , the third switch transistor 403 is connected to the second input terminal 401 and the third output terminal 402 , the signal of the second input terminal 401 pulls down the signal of the third output terminal 402 through the third switch transistor 403 .

Specifically, as shown in FIG. 6 , the third switching transistor 403 may be an N-type transistor, the source of the third switching transistor 403 is connected to the first voltage source 02 , and the gate of the third switching transistor 403 is connected to the first voltage source 02 . The electrode is connected to the corresponding second input terminal 401 , and the drain of the third switching transistor 403 is connected to the corresponding third output terminal 402 . Reference may be made to the above related description of the first switching transistor 304 . Similarly, when m>3, if the second input terminal 401 is connected to the m-th level clock signal line 10m, and the third output terminal 402 is connected to the (m-3+8*i)-th level gate signal line 20(m-3+8*i), then the rising edge of the m-th stage clock signal CK(m) can pull down the (m-3+8*i)-th stage gate signal G(m-3+8*i ), in order to shorten the falling time of the gate signal G(m-3+8*i) of the (m-3+8*i) stage, improve the charging time of the corresponding pixel, and improve the uniformity of the display screen of the display panel .

Further, each second pull-down module further includes a third capacitor 404, two ends of the third capacitor 404 are respectively connected to the drain of the third switching transistor 403 and the inversion of the signal of the second input terminal 401 signal, and the inverted signal of the signal of the second input terminal 401 is opposite to the signal of the gate of the third switching transistor 403 , in the same way, the third capacitor 404 can solve the capacitive coupling of the third switching transistor 403 And the corresponding gate signal distortion problem.

In an embodiment, as shown in FIG. 5 , some of the first pull-down modules in the plurality of first pull-down modules further include an inverting terminal 309 , and some of the first pull-down modules and the plurality of second pull-down modules further include an inverting terminal 309 . The pull-down modules are in one-to-one correspondence. The signal of the inverting terminal 309 at any time and the signal of the second input terminal 401 of the corresponding second pull-down module are the third voltage or the fourth voltage, and the signal of the inverting terminal 309 at any time is the third voltage or the fourth voltage. The signal is different from the signal of the second input terminal 401 of the corresponding second pull-down module; wherein the signal of the second input terminal 401 of the second pull-down module is the same as the corresponding signal of the first input terminal 301 of the first pull-down module. The signal is the same.

It can be understood that because the end of the third capacitor 404 away from the third switch transistor 403 needs to be connected to the inverted signal of the signal of the second input end 401 to achieve the above functions, but the second pull-down module does not include Inverter, it should be noted that under the premise that the signal of the second input terminal 401 of the second pull-down module is the same as the signal of the first input terminal 301 of the corresponding first pull-down module, the corresponding first pull-down module The signal of the inversion terminal 309 of the pull-down module is substantially the inversion signal of the signal of the second input terminal 401 of the second pull-down module. Therefore, the second pull-down module can share the inversion signal of the corresponding first pull-down module. The phase converter 305 , that is, the end of the third capacitor 404 away from the third switching transistor 403 may be connected to the inverting end 309 of the corresponding first pull-down module.

In one embodiment, as shown in FIG. 7 , the gate driving circuit further includes:

A plurality of third pull-down modules, each of the third pull-down modules in the plurality of third pull-down modules includes a third input end 501 and a fourth output end 502, and the falling edge of the signal of the third input end 501 is used to pull down all the third pull-down modules. The signal of the fourth output terminal 502, the third input terminal 501 and the fourth output terminal 502 are respectively connected to the first-level clock signal line and the first-level gate signal line;

Wherein, for the k-th gate signal line in the multi-level gate signal lines:

If k%M is an odd number, the gate signal line of the k-th stage is connected to the first output terminal 302 of one of the first pull-down modules, and the first input terminal 301 of the first pull-down module is connected to the (k-th stage) %M) level clock signal line, or the kth level gate signal line is connected to the fourth output terminal 502 of one of the third pull-down modules, and the third input terminal 501 of the third pull-down module is connected to the (k%) M) level clock signal line, otherwise, the kth level gate signal line is connected to the second output terminal 303 of one of the first pull-down modules, and the first input terminal 301 of the first pull-down module is connected to the first pull-down module. [(k%M)+f+g1*T] level clock signal line; or

If k%M is an even number, the gate signal line of the k-th stage is connected to the first output terminal 302 of one of the first pull-down modules, and the first input terminal 301 of the first pull-down module is connected to the (k-th stage) %M) level clock signal line, or the kth level gate signal line is connected to the fourth output terminal 502 of one of the third pull-down modules, and the third input terminal 501 of the third pull-down module is connected to the (k%) M) level clock signal line, otherwise, the kth level gate signal line is connected to the second output end 303 of one of the first pull-down modules, and the first input end 301 of the first pull-down module is connected to [ (k%M)+f+g2*T] level clock signal line.

It should be noted that the difference between this embodiment and the above embodiments in FIGS. 2-3 is that in addition to the first pull-down module, this embodiment also includes the third pull-down module, and in each In the third pull-down module, the falling edge of the signal of the third input terminal 501 is used to pull down the signal of the fourth output terminal 502, that is, each of the third pull-down modules is only used to pull down the corresponding primary gate. Further, it can be seen from Figure 4 that when m>0, the falling edge of the gate signal G(m+8*i) of the (m+8*i) stage and the inverted clock signal XCK of the mth stage ( The rising edge of m) corresponds to, so the falling edge of the gate signal G(m) of the (m+8*i) stage corresponds to the falling edge of the clock signal CK(m) of the mth stage, and according to the function of the third pull-down module , that is, the m-th inversion clock signal XCK(m) obtained after the m-th stage clock signal CK(m) is changed can pull down the (m+8*i)-th gate signal G(m+8*i) , so for any third pull-down module, the third input terminal 501 is connected to the m-th level clock signal line 10m, and the fourth output terminal 502 can be connected to the (m+8*i)-th level gate signal line .

In an embodiment, as shown in FIG. 7 , each third pull-down module further includes a second inverter 503 and a fourth switching transistor 504; the second inverter 503 is connected to the third input terminal 501 and the The fourth switch transistor 504 and the second inverter 503 are used to input a second inversion signal to the fourth switch transistor 504, the second inversion signal and the third input terminal 501 at any time The signal is the fifth voltage or the sixth voltage, and the second inverted signal is different from the signal of the third input terminal 501 at any time; the fourth switching transistor 504 is connected to the fourth output terminal 502, The second inverted signal pulls down the signal of the fourth output terminal 502 through the fourth switch transistor 504 .

Specifically, as shown in FIG. 7 , the fourth switch transistor 504 may be an N-type transistor, the source of the fourth switch transistor 504 is connected to the first voltage source 02 , and the gate of the fourth switch transistor 504 is connected to the first voltage source 02 . The pole is connected to the output terminal of the second inverter 503, and the drain of the fourth switching transistor 504 is connected to the corresponding fourth output terminal 502. Here, you can refer to the above about the first inverter 305 and the corresponding fourth output terminal 502. The related description of the second switching transistor 306 is described above. Similarly, when m>0, if the input terminal of the second inverter 503 is connected to the third input terminal 501 to connect the m-th stage clock signal line 10m, and the fourth output terminal 502 is connected to The (m+8*i)-th stage gate signal line 20 (m+8*i), then the falling edge of the m-th stage clock signal CK(m) passes through the m-th stage inverter generated by the second inverter 503 The rising edge of the phase clock signal XCK(m) can pull down the (m+8*i)-th gate signal G(m+8*i) to shorten the (m+8*i)-th gate signal G( The falling duration of m+8*i) improves the charging time of the corresponding pixel and improves the uniformity of the display screen of the display panel.

Further, each third pull-down module further includes a fourth capacitor 505 , and two ends of the fourth capacitor 505 are respectively connected to the drain of the fourth switch transistor 504 and the same signal as the third input terminal 501 . circuit, and the signal of the third input terminal 501 is opposite to the signal of the gate of the fourth switch transistor 504 , similarly, the fourth capacitor 505 can solve the corresponding problem caused by the capacitive coupling of the fourth switch transistor 504 the problem of gate signal distortion.

Embodiments of the present application further provide a display panel. As shown in FIGS. 8-9 , the display panel 100 includes the gate driving circuit 00 described in any of the above, and the display panel 100 includes a display area 04 , a first Area 05 and second area 06, the first area 05 and the second area 06 are arranged opposite, the display area 04 is located between the first area 05 and the second area 06, the multi-level The clock signal line 10 and the multi-level gate signal line 20 are both located in the first region 05 , the plurality of first pull-down modules are located in the second region 06 , and the gate driving circuit 00 further includes: A multi-level first gate connection line 60, the multi-level first gate connection line 60 and the multi-level gate signal line 20 are in one-to-one correspondence, and the multi-level first gate connection line 60 runs through the display In area 04, the two ends of each level of the first gate connection lines in the multi-level first gate connection lines 60 are respectively connected to the corresponding gate signal lines and the corresponding first pull-down modules to electrically connect the corresponding The gate signal line and the corresponding first pull-down module.

Wherein, the display panel may be an LCD display panel, an OLED (Organic Light-Emitting Diode, organic light emitting diode) display panel or a Micro LED (Micro Light Emitting Diode, micro light emitting diode) display panel.

Wherein, the first area 05 and the second area 06 may be located above and below the display area 04, respectively, or to the left and right of the display area 04, further, the display panel 100 may also include a source driver circuit, and the source driver circuit and the gate driver circuit 00 may be arranged in the same area of the display panel 100 except for the display area 04. For example, in FIGS. 8-9, According to the disposition area of the gate drive circuit 00 , the source drive circuit can be disposed in the first area 05 or the second area 06 , so as to avoid disposing additional areas on both sides of the display panel 100 to Carrying the source driving circuit increases the screen ratio of the display panel 100 .

Specifically, as shown in FIGS. 8-9 , the multi-level clock signal line 10 includes a first-level clock signal line 101 to an eighth-level clock signal line 108 as an example for description here. According to the above analysis, when m is any integer not less than 1 and not greater than 8, and j is any positive integer, the m-th gate signal line and the (m+8*j)-th gate signal line are both connected The m-th stage clock signal line, so that the m-th stage gate signal and the (m+8*j)-th stage gate signal are respectively synchronized by the 1st cycle and the (j+1)th cycle in the m-th stage clock signal, That is, the gate signal lines of the first, ninth, and 17th stages are all connected to the clock signal line 101 of the first stage, and the gate signal lines of the second, tenth, and 18th stages are all connected to the clock signal line of the second stage. The 19th-level gate signal lines are all connected to the third-level clock signal lines, the 4th, 12th, and 20th level gate signal lines are all connected to the fourth-level clock signal lines, and so on, the 8th and 16th level gate signal lines are connected. Level 8 clock signal line. Wherein, a conversion module is arranged between each gate signal line of the multi-level gate signal line 20 and the corresponding clock signal line, for example, the fourth level gate signal line 204 and the fourth level clock signal line There is a fourth conversion module 04 between 104, a sixth conversion module 06 between the sixth level gate signal line 206 and the sixth level clock signal line 106, and the seventh level gate signal line 207 and the seventh A seventh conversion module 07 is provided between the level clock signal line 107, a 29th conversion module 029 is provided between the 23rd level gate signal line 2023 and the fifth level clock signal line 105, and the 29th level gate signal line A 29th conversion module 029 is arranged between 2029 and the fifth-level clock signal line 105; line connection to obtain the corresponding gate signal.

In an embodiment, as shown in FIGS. 8-9 , some of the clock signal lines in the multi-level clock signal lines 10 are connected to the plurality of first pull-down modules, and the gate driving circuit 00 further includes: a plurality of first pull-down modules. The multi-level pull-down connection lines 70 are also located in the second region 06. The multi-level pull-down connection lines 70 correspond to the part of the clock signal lines one-to-one. The multi-level pull-down connection lines 70 The two ends of the pull-down connection lines of each level are connected to the corresponding level-1 clock signal lines and the corresponding at least one first pull-down module. Specifically, the multi-level pull-down connection line 70 includes a first-level pull-down connection line 701 to a fourth-level pull-down connection line 704, and the first-level pull-down connection line 701 to the fourth-level pull-down connection line 704 are respectively electrically The first-stage clock signal line 101 , the third-stage clock signal line 103 , the fifth-stage clock signal line 105 , and the seventh-stage clock signal line 107 are electrically connected.

In one embodiment, as shown in FIG. 8 , the gate driving circuit 00 may pull down the multi-level gate signals by connecting the clock signals of the multi-level odd-numbered stages to the corresponding first pull-down modules, where the following The multi-level gate signal lines 20 include first-level gate signal lines 201 to 24-level gate signal lines 2024 , and the multi-level first gate connection lines 60 include first-level first gate connection lines 601 The first gate connection line 6024 to the 24th level is described as an example. As shown in Table 1, the total number of gate signals is 24 levels as an example for illustration, so w1 can be 0, 1, 2 in turn, "AB" represents the first pull-down module, "a1" and "a1" The "b1 terminal" represents the second output terminal 303 and the first output terminal 302 of any one of the first pull-down modules, respectively.

Table 1

Specifically, according to the correlation analysis of FIG. 2 above, it can be known that if k%8 is an odd number, the k-th gate signal line is connected to the first output end 302 of one of the first pull-down modules, and the The first input end 301 of the pull-down module is connected to the (k%8)th stage clock signal line. For example, in Table 1, the (8*w1+p1)th stage gate signal G(8*w1+p1) passes through the AB The b1 terminal is pulled down by the p1-level clock signal CK(p1). Correspondingly, as shown in FIG. 8, the (8*w1+p1)-level gate signal line 20 (8*w1+p1) is connected to the first lower The first output end 302 of the pull-up module is pulled down by the p1-th stage clock signal line 10 (p1), wherein the p1 can be taken as 1, 3, and 5 in sequence; otherwise, if k%8 is an even number, the The gate signal line of the k-th stage is connected to the second output terminal 303 of one of the first pull-down modules, and the first input terminal 301 of the first pull-down module is connected to the [(k%8)+3+8*g1th ] stage clock signal line, for example, in Table 1, the gate signal G(8*w1+q1) of the (8*w1+q1) stage passes through the a1 terminal of AB to be received by the [(k%8)+3+8* g1] stage clock signal CK[(k%8)+3+8*g1] is pulled low, correspondingly, as shown in FIG. 8, the gate signal line 20 (8*w1+q1) of the (8*w1+q1) stage q1) Connect the second output terminal 303 of the first pull-down module to be pulled down by the [(k%8)+3+8*g1]th stage clock signal line 10[(k%8)+3+8*g1] , wherein the p1 is taken over 2, 4, and 6 in sequence. Wherein, the [(k%8)+f+g1*T] is an odd number not less than 1 and not greater than the 8.

To sum up, as shown in FIG. 8 and Table 1, the 24-level gate signal lines are divided into three periods, and each period traverses 8 levels of continuous gate signal lines, and every two levels of gate signal lines A first pull-down module can be shared according to the above connection relationship, so there is no redundant start-stage gate signal line and end-stage gate signal line, and the first pull-down module, the second pull-down module or the the third pull-down module.

In an embodiment, the gate driving circuit 00 can also pull down the multi-level gate signals by connecting the clock signals of the multi-level even-numbered stages to the corresponding first pull-down modules. For the specific connection relationship and signal pull-down relationship, reference may be made to the relevant description of FIG. 3 above and the “gate drive circuit 00 may pull down the multi-stage odd-numbered stage by connecting the clock signal of the multi-stage odd-numbered stage to the corresponding first pull-down module. gate signal".

In an embodiment, as shown in FIG. 9 , the gate driving circuit 00 can connect the clock signals of the multi-stage odd-numbered stages to the corresponding first pull-down module, the corresponding second pull-down module and the corresponding third pull-down module. The module pulls down the multi-level gate signal. Here, the multi-level gate signal line 20 includes the first-level gate signal line 201 to the 32-level gate signal line 2032, and the multi-level first gate The connection line 60 includes the first-level first gate connection line 601 to the 32nd-level first gate connection line 6032 as an example for description. As shown in Table 2, the total number of stages of the gate signal is 32 stages as an example for description, so w2 can be 0, 1, 2, 3 in sequence, "AB" represents the first pull-down module, "A" Indicates the second pull-down module, "B" indicates the third pull-down module, "a1 end" and "b1 end" respectively indicate the second output end 303 and the first output end 302 of any first pull-down module, "a2 end" represents the third output terminal 402 of any second pull-down module, and "b2 terminal" represents the fourth output terminal 502 of any third pull-down module.

Table 2

Specifically, when the gate driving circuit 00 further includes a second pull-down module and a third pull-down module, it can be known from the above related analysis about FIGS. 6-7 that:

If k%8 is an odd number, the gate signal line of the k-th stage is connected to the first output terminal 302 of one of the first pull-down modules, and the first input terminal 301 of the first pull-down module is connected to the (k-th stage) %8) stage clock signal line, for example, in Table 2, the (8*w2+p2) stage gate signal G(8*w2+p2) passes through the b1 terminal of AB to be pulled by the p2 stage clock signal CK(p2) low, correspondingly, as shown in FIG. 9, the gate signal line 20 (8*w2+p2) of the (8*w2+p2) stage is connected to the first output terminal 302 of the first pull-down module to be clocked by the p2 stage The signal line 10 (p2) is pulled down, wherein the p2 can be taken through 1, 3, and 5 in sequence. For example, in FIG. 9, only the gate signals of the 1st, 3rd, 5th, 7th, 9th... The lines are all connected to the first output end 302 of one of the first pull-down modules, and are pulled down by the corresponding clock signal line as an example;

Alternatively, the k-th gate signal line is connected to the fourth output terminal 502 of one of the third pull-down modules, and the third input terminal 501 of the third pull-down module is connected to the (k% 8)-th stage clock signal line, for example In Table 2, the gate signal G(8*w2+p2) of the (8*w2+p2) stage passes through the b2 terminal of B to be pulled down by the p2 stage clock signal CK(p2). Correspondingly, as shown in Figure 9 As shown, the gate signal line 20 (8*w2+p2) of the (8*w2+p2) stage is connected to the fourth output terminal 502 of the third pull-down module to be pulled down by the clock signal line 10 (p2) of the p2 stage, wherein , the p2 can be taken from 1, 3, and 5 in sequence. For example, in FIG. 9, on the basis of the above embodiment, only the gate signal lines of the 29th and 31st stages are connected to the fourth output terminal of one of the third pull-down modules. 502 is taken as an example of being pulled down by the corresponding clock signal line;

On the contrary, if k%8 is an even number, the gate signal line of the k-th stage is connected to the second output terminal 303 of one of the first pull-down modules, and the first input terminal 301 of the first pull-down module is connected to the first pull-down module. [(k%8)+3+8*g1] stage clock signal line, for example, in Table 2, the gate signal G(8*w2+q2) of the (8*w2+q2) stage passes through the a1 terminal of AB to be The stage [(k%8)+3+8*g1] clock signal CK[(k%8)+3+8*g1] is pulled low, correspondingly, as shown in Figure 9, the stage (8*w2+q2 ) stage gate signal line 20 (8*w2+q2) is connected to the second output terminal 303 of the first pull-down module to be connected to the [(k%8)+3+8*g1]th stage clock signal line 10[(k %8)+3+8*g1] is pulled down, wherein, the q2 can be taken over 2, 4, and 6 in sequence. Specifically, for example, in FIG. 9, only the 6th, 8th, 10th... The gate signal lines are all connected to the second output end 303 of one of the first pull-down modules, and are pulled down by the corresponding clock signal line as an example;

Or the k-th gate signal line is connected to the third output terminal 402 of one of the second pull-down modules, and the second input terminal 402 of the second pull-down module is connected to the [(k%M)+f+g2* T] stage clock signal line, for example, in Table 2, the gate signal G(8*w2+q2) of the (8*w2+q2)th stage passes through the a2 terminal of A to be received by the [(k%8)+3+8th stage *g1] stage clock signal CK[(k%8)+3+8*g1] is pulled low, correspondingly, as shown in FIG. 9, the (8*w2+q2) stage gate signal line 20 (8*w2 +q2) Connect the third output terminal 402 of the second pull-down module to be pulled down by the [(k%8)+3+8*g1]-th stage clock signal line 10[(k%8)+3+8*g1] , wherein, the q2 can be taken from 2, 4, and 6 in sequence. Specifically, for example, in FIG. 9, only the second and fourth gate signal lines are connected to the third output end 402 of one of the second pull-down modules. Take being pulled down by the corresponding clock signal line as an example.

To sum up, as shown in FIG. 9 and Table 2, the 24-level gate signal lines are divided into three periods and several scattered gate signal lines, and the fourth-level gate connection line 604 starting from the left and the second-level gate connection line 602 can both be connected to the second pull-down module; 8 levels of discontinuous gate signal lines are traversed in each subsequent cycle, and can be sorted according to the above connection relationship, so that each adjacent two-level gate signal line The pole signal lines share a first pull-down module; then after the third cycle, the (8*3+7) gate signal lines 20 (8*3+7) and the (8*3+5) gate The pole signal lines 20 (8*3+5) cannot be covered by the periodically arranged first pull-down modules, that is, the 31st-level gate signal G(31) and the 29th-level gate signal G(29) can be connected to The third pull-down module described above.

In an embodiment, the gate driving circuit 00 can also pull down the multi-level gate by connecting the clock signals of the multi-level even-numbered stages to the corresponding first pull-down module, the second pull-down module and the third pull-down module. Signal. For the specific connection relationship and signal pull-down relationship, reference may be made to the relevant description of FIG. 3 above and the “gate drive circuit 00 may connect the clock signals of multiple stages and odd-numbered stages to the corresponding first pull-down module, second pull-down module and The third pull-down module pulls the multi-level gate signal".

It can be understood that, regardless of whether the multi-level pull-down connection lines are electrically connected to the odd-numbered or even-numbered clock signal lines, the number of the multi-level pull-down connection lines used to connect the multi-level pull-down connection lines and the The number of connecting lines of the multi-level clock signal lines is small, which can occupy less area of the two sides of the display panel 100 , thereby increasing the screen ratio of the display panel 100 .

In an embodiment, as shown in FIGS. 8-9 , the display panel further includes a plurality of pixel driving units, and the plurality of pixel driving units are arranged in the display area 04 in an array, and the gate driving circuit further includes: Including: multi-level second gate connection lines, the multi-level second gate connection lines and the multi-level first gate connection lines are arranged to intersect, the multi-level second gate connection lines and the multi-level first gate connection lines The first gate connection lines are in one-to-one correspondence, and the connection of the multi-level second gate connection lines corresponds to a row or a column of pixel driving units; a plurality of connection points, each level of the multi-level second gate connection lines A connection point is provided at the intersection of the second gate connection line and the corresponding first gate connection line, and the plurality of connection points are used to electrically connect the corresponding first gate connection line and the corresponding second gate connecting line.

Further, according to the relevant descriptions in Figures 5-6, it can be known that under the premise that the signal of the second input terminal 401 of the second pull-down module is the same as the signal of the first input terminal 301 of the corresponding first pull-down module, One end of the third capacitor 404 away from the third switch transistor 403 may be connected to the inverting terminal 309 of the corresponding first pull-down module to share the corresponding inverter 305 of the first pull-down module. Therefore, as shown in FIG. 9, for example, the first second pull-down module and the fourth first pull-down module from left to right are both connected to the fourth-level pull-down connection line 704. Therefore, the first pull-down connection line from left to right The end 405 of the third capacitor 404 in the second pull-down module that is far away from the third switch transistor 403 can be connected to the inverting end 309 of the fourth first pull-down module. Of course, if the signal of the second input terminal 401 of one of the second pull-down modules is the same as the signal of the third input terminal 501 of one of the third pull-down modules, the second pull-down modules can also share the corresponding third pull-down module. of the second inverter 503 .

In one embodiment, as shown in FIGS. 8-9 , the display panel 100 further includes a plurality of pixel driving units, and the plurality of pixel driving units are arranged in the display area 04 in an array, and the gate driving circuit 00 further includes: multi-level second gate connection lines 80, the multi-level second gate connection lines 80 and the multi-level first gate connection lines 60 are arranged to intersect, the multi-level second gate connection lines 80 is in one-to-one correspondence with the multi-level first gate connection lines 60, and each level of the multi-level second gate connection lines 80 is connected to a corresponding row or column of pixel driving units; a plurality of A connection point 90 , a connection point is provided at the intersection of each stage of the second gate connection line and the corresponding first gate connection line in the multi-level second gate connection lines 80 , the plurality of connection points 90 It is used to electrically connect the corresponding first gate connection line and the corresponding second gate connection line.

Wherein, as shown in FIGS. 8-9 , the multi-level first gate connection lines 60 are arranged in parallel along the horizontal direction, the multi-level second gate connection lines 80 are arranged in parallel along the vertical direction, and the multi-level second gate connection lines 80 are arranged in parallel along the vertical direction. The essence of each connection point 90 may include a via hole and a connection body disposed in the via hole, each connection body is connected to the corresponding first gate connection line and the corresponding second gate connection line located in different layers, each connection body One row of pixel driving units corresponding to the first level of the second gate connection line. For any positive integer n that is not less than 1 and not greater than the N, the n-th first gate connection line 60n is longitudinally arranged, and the two ends of the n-th first gate connection line 60n are respectively connected to the n-th gate The pole signal line 20n and the corresponding pull-down module, the second gate connecting line 80n of the nth stage is arranged laterally, and the intersection of the second gate connecting line 80n of the nth stage and the first gate connecting line 60n of the nth stage is provided with a n connection points 90n, the nth connection point 90n is used to electrically connect the nth level second gate connection line 80n and the nth level first gate connection line 60n, and the nth level second gate connection line Line 80n connects the pixel driving units in the nth row.

Specifically, for example, as shown in FIG. 8 , a twentieth connection point 9020 is provided at the intersection of the twentieth-level second gate connection line 8020 and the twentieth-level first gate connection line 6020 , and the 20th connection point 9020 It is used to electrically connect the 20th-level second gate connection line 8020 and the 20th-level first gate connection line 6020, and the 20th-level second gate connection line 8020 is connected to the 20th row of pixel driving units; another example is FIG. 9 As shown, a 25th connection point 9025 is provided at the intersection of the 25th-level second gate connection line 80250 and the 25th-level first gate connection line 6025, and the 25th connection point 9025 is used to electrically connect the The second gate connection line 8025 of the 25th level and the first gate connection line 6025 of the 25th level, and the second gate connection line 8025 of the 25th level is connected to the pixel driving unit of the 25th row.

It should be noted that, compared with Figs. 8-9, it can be seen that the distance between some connection points in the embodiment of Fig. 8 is too close, which may cause a short circuit between the part of the connection point or the signals transmitted by the part of the connection point interfere with each other, but In the embodiment of FIG. 9 , except for the leftmost two connection points and the rightmost two connection points, the rest of the connection points are evenly distributed and have large intervals, which effectively avoids the above problems.

Claims

A gate drive circuit, wherein the gate drive circuit comprises:

A multi-level clock signal line, the multi-level clock signal line includes a first-level clock signal line to an M-th level clock signal line, and the first-level clock signal line to the M-th level clock signal line respectively transmits the first level From the clock signal to the M-th stage clock signal, the period of each stage clock signal is (a*T), the duty cycle of each stage clock signal is (T-2)/(2*T), and the adjacent two stages The offset between the clock signals is a, wherein the M is an even number greater than 2, the a is the duration of a unit time period, and the T is the number of a in one cycle of each stage of the clock signal , the T is equal to the M;

A multi-level gate signal line, the multi-level gate signal line includes a first-level gate signal line to an N-th level gate signal line, and the first-level gate signal line to the N-th level gate signal line The lines transmit the gate signal of the first stage to the gate signal of the Nth stage respectively, and the gate signal line of the nmth stage and the gate signal line of the (nm+j*M)th stage are both connected to the clock signal line of the nmth stage, so that the nmth stage The stage gate signal and the (nm+j*M)th stage gate signal are respectively synchronized by a corresponding period in the nmth stage clock signal, wherein the N is an integer not less than the M, and the nm is not less than an integer less than 1 and not greater than the M, and the j is a positive integer;

A plurality of first pull-down modules, each of the first pull-down modules in the plurality of first pull-down modules includes a first input terminal, a first output terminal and a second output terminal, and the drop of the signal of the first input terminal The edge and the rising edge are respectively used to pull down the signal of the first output end and the signal of the second output end, the first input end is connected to the first-level clock signal line, the first output end and the second output end Connect different two-stage gate signal lines respectively;

Wherein, for the k-th gate signal line in the multi-level gate signal lines:

If k%M is an odd number, the gate signal line of the kth stage is connected to the first output terminal of one of the first pull-down modules, and the first input terminal of the first pull-down module is connected to the (k%Mth) ) level clock signal line, otherwise, the kth level gate signal line is connected to the second output end of one of the first pull-down modules, and the first input end of the first pull-down module is connected to the [(kth %M)+f+g1*T] level clock signal line, wherein, the f is (T-2)/2, the g1 is an integer, the [(k%M)+f+g1*T] is an odd number not less than 1 and not greater than said M; or

If k%M is an even number, the gate signal line of the kth stage is connected to the first output terminal of one of the first pull-down modules, and the first input terminal of the first pull-down module is connected to the (k%Mth) ) level clock signal line, otherwise, the kth level gate signal line is connected to the second output end of one of the first pull-down modules, and the first input end of the first pull-down module is connected to the [(kth %M)+f+g2*T] level clock signal line, wherein the g2 is an integer, and the [(k%M)+f+g2*T] is an even number not less than 1 and not greater than the M .
The gate driving circuit of claim 1, wherein each of the first pull-down modules further comprises:

A first switch transistor, the first switch transistor is connected to the first input terminal and the second output terminal, and the signal of the first input terminal pulls down the signal of the second output terminal through the first switch transistor.
The gate driving circuit according to claim 2, wherein the first switching transistor is an N-type transistor, a source of the first switching transistor is connected to a first voltage source, and a gate of the first switching transistor is connected to The corresponding first input terminal, the drain of the first switching transistor is connected to the corresponding second output terminal, wherein the first voltage source provides a low voltage or a ground voltage.
The gate driving circuit of claim 2, wherein each of the first pull-down modules further comprises a first inverter and a second switching transistor;

The first inverter is connected to the first input terminal and the second switching transistor, the first inverter is used to input a first inverted signal to the second switching transistor, and the first inverter is used at any time. The inverted signal and the signal of the first input terminal are the first voltage or the second voltage, and the first inverted signal is different from the signal of the first input terminal at any time;

The second switch transistor is connected to the first output terminal, and the first inverted signal pulls down the signal of the first output terminal through the second switch transistor.
The gate driving circuit according to claim 4, wherein the second switching transistor is an N-type transistor, the source of the second switching transistor is connected to the first voltage source, and the gate of the second switching transistor is connected to the first voltage source. The pole is connected to the output terminal of the first inverter, and the drain of the second switching transistor is connected to the corresponding first output terminal.
The gate driving circuit according to claim 4, wherein the first switch transistor and the second switch transistor are both N-type transistors, and each first pull-down module further comprises:

a first capacitor, two ends of the first capacitor are respectively connected to the drain of the first switching transistor and the output end of the first inverter;

A second capacitor, two ends of the second capacitor are respectively connected to the drain of the second switching transistor and the line with the same signal as the first input terminal.
The gate drive circuit of claim 1, wherein the gate drive circuit further comprises:

a plurality of second pull-down modules, each of the second pull-down modules in the plurality of second pull-down modules includes a second input terminal and a third output terminal, and the rising edge of the signal of the second input terminal is used to pull down the third output The second input terminal and the third output terminal are respectively connected to the first-level clock signal line and the first-level gate signal line;

Wherein, for the k-th gate signal line in the multi-level gate signal lines:

If k%M is an odd number, the gate signal line of the kth stage is connected to the first output terminal of one of the first pull-down modules, and the first input terminal of the first pull-down module is connected to the (k%Mth) ) level clock signal line, otherwise, the kth level gate signal line is connected to the second output end of one of the first pull-down modules, and the first input end of the first pull-down module is connected to the [(kth %M)+f+g1*T] level clock signal line, or the kth level gate signal line is connected to the third output end of one of the second pull-down modules, and the second input end of the second pull-down module Connect the [(k%M)+f+g1*T] stage clock signal line; or

If k%M is an even number, the gate signal line of the kth stage is connected to the first output terminal of one of the first pull-down modules, and the first input terminal of the first pull-down module is connected to the (k%Mth) ) level clock signal line, otherwise, the kth level gate signal line is connected to the second output end of one of the first pull-down modules, and the first input end of the first pull-down module is connected to the [(kth %M)+f+g2*T] level clock signal line, or the k-th level gate signal line is connected to the third output end of one of the second pull-down modules, and the second input end of the second pull-down module Connect the [(k%M)+f+g2*T]-th stage clock signal line.
The gate driving circuit of claim 7, wherein each second pull-down module further comprises:

A third switching transistor, the third switching transistor is connected to the second input terminal and the third output terminal, and the signal of the second input terminal pulls down the signal of the third output terminal through the third switching transistor.
The gate driving circuit according to claim 8, wherein the third switch transistor is an N-type transistor, and each second pull-down module further comprises:

A third capacitor, two ends of the third capacitor are respectively connected to the drain of the third switching transistor and the inverted signal of the signal of the second input terminal, and the inverted signal of the signal of the second input terminal and the The signal at the gate of the third switching transistor is opposite.
The gate driving circuit according to claim 8, wherein a part of the first pull-down modules in the plurality of first pull-down modules further comprises an inverting terminal, and the part of the first pull-down modules and the plurality of first pull-down modules further comprise an inverting terminal. The two pull-down modules are in one-to-one correspondence, the signal of the inverting terminal at any time and the signal of the second input terminal of the corresponding second pull-down module are the third voltage or the fourth voltage, and the signal of the inverting terminal at any time corresponds to the corresponding first voltage. The signals of the second input terminals of the two pull-down modules are different;

Wherein, the signal of the second input terminal of the second pull-down module is the same as the signal of the corresponding first input terminal of the first pull-down module.
The gate drive circuit of claim 1, wherein the gate drive circuit further comprises:

a plurality of third pull-down modules, each of the third pull-down modules in the plurality of third pull-down modules includes a third input terminal and a fourth output terminal, and the falling edge of the signal of the third input terminal is used to pull down the fourth output The third input terminal and the fourth output terminal are respectively connected to the first-level clock signal line and the first-level gate signal line;

Wherein, for the k-th gate signal line in the multi-level gate signal lines:

If k%M is an odd number, the gate signal line of the kth stage is connected to the first output terminal of one of the first pull-down modules, and the first input terminal of the first pull-down module is connected to the (k%Mth) ) level clock signal line, or the kth level gate signal line is connected to the fourth output terminal of one of the third pull-down modules, and the third input terminal of the third pull-down module is connected to the (k%M)th level clock signal line, otherwise, the k-th gate signal line is connected to the second output terminal of one of the first pull-down modules, and the first input terminal of the first pull-down module is connected to the [(k%M)th +f+g1*T] class clock signal line; or

If k%M is an even number, the gate signal line of the kth stage is connected to the first output terminal of one of the first pull-down modules, and the first input terminal of the first pull-down module is connected to the (k%Mth) ) level clock signal line, or the kth level gate signal line is connected to the fourth output terminal of one of the third pull-down modules, and the third input terminal of the third pull-down module is connected to the (k%M)th level clock signal line, otherwise, the k-th gate signal line is connected to the second output end of one of the first pull-down modules, and the first input end of the first pull-down module is connected to [(k%M)+ f+g2*T] level clock signal line.
The gate driving circuit of claim 11, wherein each of the third pull-down modules further comprises a second inverter and a fourth switching transistor;

The second inverter is connected to the third input terminal and the fourth switching transistor, and the second inverter is used to input a second inverted signal to the fourth switching transistor, and the second inverter is used at any time. The inverted signal and the signal of the third input terminal are the fifth voltage or the sixth voltage, and the second inverted signal is different from the signal of the third input terminal at any time;

The fourth switch transistor is connected to the fourth output terminal, and the second inverted signal pulls down the signal of the fourth output terminal through the fourth switch transistor.
The gate driving circuit according to claim 12, wherein the fourth switch transistor is an N-type transistor, and each third pull-down module further comprises:

a fourth capacitor, the two ends of the fourth capacitor are respectively connected to the drain of the fourth switch transistor and the same line as the signal of the third input terminal, and the signal of the third input terminal is connected to the fourth switch The gate of the transistor has the opposite signal.
The gate drive circuit of claim 1, wherein the gate drive circuit further comprises:

A multi-stage conversion module, the multi-stage conversion module includes a first-stage conversion module to an N-th stage conversion module, the first-stage conversion module to the N-th conversion module and the first-stage gate signal line respectively There is a one-to-one correspondence with the gate signal lines of the Nth stage, and the two ends of each conversion module from the first stage conversion module to the Nth stage conversion module are respectively connected to the corresponding gate signal line and the corresponding clock signal. line, the first-stage conversion module to the N-th stage conversion module are respectively used to convert the clock signal transmitted in the corresponding clock signal line into the corresponding gate signal and transmit the corresponding gate signal to the corresponding gate signal pole signal line.
The gate driving circuit according to claim 1, wherein the M is 8 or 12.
A display panel, wherein the display panel includes a gate drive circuit, the display panel further includes a display area, a first area and a second area, the first area and the second area are arranged oppositely, the A display area is located between the first area and the second area, the multi-level clock signal lines and the multi-level gate signal lines are both located in the first area of the display area, the plurality of first The pull-down module is located in the second area of the display area, and the gate driving circuit includes:

A multi-level clock signal line, the multi-level clock signal line includes a first-level clock signal line to an M-th level clock signal line, and the first-level clock signal line to the M-th level clock signal line respectively transmits the first level From the clock signal to the M-th stage clock signal, the period of each stage clock signal is (a*T), the duty cycle of each stage clock signal is (T-2)/(2*T), and the adjacent two stages The offset between the clock signals is a, wherein the M is an even number greater than 2, the a is the duration of a unit time period, and the T is the number of a in one cycle of each stage of the clock signal , the T is equal to the M;

A multi-level gate signal line, the multi-level gate signal line includes a first-level gate signal line to an N-th level gate signal line, and the first-level gate signal line to the N-th level gate signal line The lines transmit the gate signal of the first stage to the gate signal of the Nth stage respectively, and the gate signal line of the nmth stage and the gate signal line of the (nm+j*M)th stage are both connected to the clock signal line of the nmth stage, so that the nmth stage The stage gate signal and the (nm+j*M)th stage gate signal are respectively synchronized by a corresponding period in the nmth stage clock signal, wherein the N is an integer not less than the M, and the nm is not less than an integer less than 1 and not greater than the M, and the j is a positive integer;

A plurality of first pull-down modules, each of the first pull-down modules in the plurality of first pull-down modules includes a first input terminal, a first output terminal and a second output terminal, and the drop of the signal of the first input terminal The edge and the rising edge are respectively used to pull down the signal of the first output end and the signal of the second output end, the first input end is connected to the first-level clock signal line, the first output end and the second output end Connect different two-stage gate signal lines respectively;

Wherein, for the k-th gate signal line in the multi-level gate signal lines:

If k%M is an odd number, the gate signal line of the kth stage is connected to the first output terminal of one of the first pull-down modules, and the first input terminal of the first pull-down module is connected to the (k%Mth) ) level clock signal line, otherwise, the kth level gate signal line is connected to the second output end of one of the first pull-down modules, and the first input end of the first pull-down module is connected to the [(kth %M)+f+g1*T] level clock signal line, wherein, the f is (T-2)/2, the g1 is an integer, the [(k%M)+f+g1*T] is an odd number not less than 1 and not greater than said M; or

If k%M is an even number, the gate signal line of the kth stage is connected to the first output terminal of one of the first pull-down modules, and the first input terminal of the first pull-down module is connected to the (k%Mth) ) level clock signal line, otherwise, the kth level gate signal line is connected to the second output end of one of the first pull-down modules, and the first input end of the first pull-down module is connected to the [(kth %M)+f+g2*T] level clock signal line, wherein the g2 is an integer, and the [(k%M)+f+g2*T] is an even number not less than 1 and not greater than the M ;

multi-level first gate connection lines, the multi-level first gate connection lines and the multi-level gate signal lines are in one-to-one correspondence, the multi-level first gate connection lines pass through the display area, the multi-level first gate connection lines Two ends of each level of the first gate connecting lines in the multi-level first gate connecting lines are respectively connected to the corresponding gate signal lines and the corresponding first pull-down modules, so as to electrically connect the corresponding gate signal lines and the corresponding first pull-down modules. The first drop-down module.
The display panel according to claim 16, wherein some of the clock signal lines in the multi-level clock signal lines are connected to the plurality of first pull-down modules, and the gate driving circuit further comprises:

A multi-level pull-down connection line, the multi-level pull-down connection line is located in the second area, the multi-level pull-down connection line is in one-to-one correspondence with the partial clock signal lines, and each level of the multi-level pull-down connection line is pulled down The connecting line connects the corresponding first-level clock signal line and the corresponding at least one first pull-down module.
The display panel according to claim 16, wherein the display panel further comprises a plurality of pixel driving units, the plurality of pixel driving units are arrayed in the display area, and the gate driving circuit further comprises:

multi-level second gate connection lines, the multi-level second gate connection lines and the multi-level first gate connection lines are arranged to intersect, the multi-level second gate connection lines and the multi-level first gate connection lines The gate connection lines are in one-to-one correspondence, and each level of the second gate connection lines in the multi-level second gate connection lines is connected to a corresponding row or column of pixel driving units;

A plurality of connection points, a connection point is provided at the intersection of each level of the second gate connection line and the corresponding first gate connection line in the multi-level second gate connection lines, and the plurality of connection points are The corresponding first gate connection line and the corresponding second gate connection line are electrically connected.
The display panel of claim 16, wherein the gate driving circuit further comprises:

a plurality of second pull-down modules, each of the second pull-down modules in the plurality of second pull-down modules includes a second input terminal and a third output terminal, and the rising edge of the signal of the second input terminal is used to pull down the third output The second input terminal and the third output terminal are respectively connected to the first-level clock signal line and the first-level gate signal line;

Wherein, for the k-th gate signal line in the multi-level gate signal lines:

If k%M is an odd number, the gate signal line of the kth stage is connected to the first output terminal of one of the first pull-down modules, and the first input terminal of the first pull-down module is connected to the (k%Mth) ) level clock signal line, otherwise, the kth level gate signal line is connected to the second output end of one of the first pull-down modules, and the first input end of the first pull-down module is connected to the [(kth %M)+f+g1*T] level clock signal line, or the kth level gate signal line is connected to the third output end of one of the second pull-down modules, and the second input end of the second pull-down module Connect the [(k%M)+f+g1*T] stage clock signal line; or

If k%M is an even number, the gate signal line of the kth stage is connected to the first output terminal of one of the first pull-down modules, and the first input terminal of the first pull-down module is connected to the (k%Mth) ) level clock signal line, otherwise, the kth level gate signal line is connected to the second output end of one of the first pull-down modules, and the first input end of the first pull-down module is connected to the [(kth %M)+f+g2*T] level clock signal line, or the k-th level gate signal line is connected to the third output end of one of the second pull-down modules, and the second input end of the second pull-down module Connect the [(k%M)+f+g2*T]-th stage clock signal line.
The display panel of claim 16, wherein the gate driving circuit further comprises:

a plurality of third pull-down modules, each of the third pull-down modules in the plurality of third pull-down modules includes a third input terminal and a fourth output terminal, and the falling edge of the signal of the third input terminal is used to pull down the fourth output The third input terminal and the fourth output terminal are respectively connected to the first-level clock signal line and the first-level gate signal line;

Wherein, for the k-th gate signal line in the multi-level gate signal lines:

If k%M is an odd number, the gate signal line of the kth stage is connected to the first output terminal of one of the first pull-down modules, and the first input terminal of the first pull-down module is connected to the (k%Mth) ) level clock signal line, or the k-th level gate signal line is connected to the fourth output terminal of one of the third pull-down modules, and the third input terminal of the third pull-down module is connected to the (k%M)-th level clock signal line, otherwise, the k-th gate signal line is connected to the second output terminal of one of the first pull-down modules, and the first input terminal of the first pull-down module is connected to the [(k%M)th +f+g1*T] class clock signal line; or

If k%M is an even number, the gate signal line of the kth stage is connected to the first output terminal of one of the first pull-down modules, and the first input terminal of the first pull-down module is connected to the (k%Mth) ) level clock signal line, or the kth level gate signal line is connected to the fourth output terminal of one of the third pull-down modules, and the third input terminal of the third pull-down module is connected to the (k%M)th level clock signal line, otherwise, the k-th gate signal line is connected to the second output end of one of the first pull-down modules, and the first input end of the first pull-down module is connected to [(k%M)+ f+g2*T] level clock signal line.